1
0
mirror of https://github.com/DigitalDevices/dddvb.git synced 2023-10-10 13:37:43 +02:00
dddvb/ddbridge/ddbridge-main.c

432 lines
11 KiB
C
Raw Normal View History

2015-08-05 17:22:42 +02:00
/*
* ddbridge.c: Digital Devices PCIe bridge driver
*
2017-05-17 19:42:25 +02:00
* Copyright (C) 2010-2017 Digital Devices GmbH
2015-08-05 17:22:42 +02:00
* Ralph Metzler <rjkm@metzlerbros.de>
* Marcus Metzler <mocm@metzlerbros.de>
2016-02-12 18:28:00 +01:00
*
2015-08-05 17:22:42 +02:00
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, point your browser to
* http://www.gnu.org/copyleft/gpl.html
2015-08-05 17:22:42 +02:00
*/
#include "ddbridge.h"
2017-08-02 20:22:52 +02:00
#include "ddbridge-io.h"
2015-08-05 17:22:42 +02:00
#ifdef CONFIG_PCI_MSI
static int msi = 1;
module_param(msi, int, 0444);
MODULE_PARM_DESC(msi,
" Control MSI interrupts: 0-disable, 1-enable (default)");
#endif
2015-08-05 17:22:42 +02:00
2017-10-22 19:55:07 +02:00
#if (KERNEL_VERSION(4, 8, 0) > LINUX_VERSION_CODE)
int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
{
if (dev->msix_enabled) {
struct msi_desc *entry;
int i = 0;
for_each_pci_msi_entry(entry, dev) {
if (i == nr)
return entry->irq;
i++;
}
WARN_ON_ONCE(1);
return -EINVAL;
}
if (dev->msi_enabled) {
struct msi_desc *entry = first_pci_msi_entry(dev);
if (WARN_ON_ONCE(nr >= entry->nvec_used))
return -EINVAL;
} else {
if (WARN_ON_ONCE(nr > 0))
return -EINVAL;
}
return dev->irq + nr;
}
#endif
2015-08-05 17:22:42 +02:00
/****************************************************************************/
/****************************************************************************/
/****************************************************************************/
2016-04-15 23:53:20 +02:00
static void __devexit ddb_irq_disable(struct ddb *dev)
2016-04-15 18:08:51 +02:00
{
2016-05-02 16:27:32 +02:00
if (dev->link[0].info->regmap->irq_version == 2) {
2016-05-03 22:05:29 +02:00
ddbwritel(dev, 0x00000000, INTERRUPT_V2_CONTROL);
2016-04-15 18:08:51 +02:00
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_1);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_2);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_3);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_4);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_5);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_6);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_7);
} else {
ddbwritel(dev, 0, INTERRUPT_ENABLE);
ddbwritel(dev, 0, MSI1_ENABLE);
}
2016-04-15 23:53:20 +02:00
}
static void __devexit ddb_irq_exit(struct ddb *dev)
{
ddb_irq_disable(dev);
2016-04-15 18:08:51 +02:00
if (dev->msi == 2)
2017-10-22 19:55:07 +02:00
free_irq(pci_irq_vector(dev->pdev, 1), dev);
free_irq(pci_irq_vector(dev->pdev, 0), dev);
2016-04-15 18:08:51 +02:00
#ifdef CONFIG_PCI_MSI
2017-10-22 19:55:07 +02:00
if (dev->msi) {
pci_free_irq_vectors(dev->pdev);
2016-04-15 18:08:51 +02:00
pci_disable_msi(dev->pdev);
2017-10-22 19:55:07 +02:00
}
2016-04-15 18:08:51 +02:00
#endif
}
2015-08-05 17:22:42 +02:00
static void __devexit ddb_remove(struct pci_dev *pdev)
{
2017-08-26 22:04:37 +02:00
struct ddb *dev = (struct ddb *)pci_get_drvdata(pdev);
2015-08-05 17:22:42 +02:00
2015-12-10 18:26:45 +01:00
ddb_device_destroy(dev);
2015-08-05 17:22:42 +02:00
ddb_nsd_detach(dev);
ddb_ports_detach(dev);
ddb_i2c_release(dev);
if (dev->link[0].info->ns_num)
ddbwritel(dev, 0, ETHER_CONTROL);
2016-04-15 18:08:51 +02:00
ddb_irq_exit(dev);
2015-08-05 17:22:42 +02:00
ddb_ports_release(dev);
ddb_buffers_free(dev);
ddb_unmap(dev);
2015-12-21 13:48:44 +01:00
pci_set_drvdata(pdev, NULL);
2015-08-05 17:22:42 +02:00
pci_disable_device(pdev);
}
2017-09-25 19:20:17 +02:00
#if (KERNEL_VERSION(3, 8, 0) <= LINUX_VERSION_CODE)
2015-08-05 17:22:42 +02:00
#define __devinit
#define __devinitdata
#endif
2016-04-15 18:08:51 +02:00
static int __devinit ddb_irq_msi(struct ddb *dev, int nr)
{
int stat = 0;
2016-04-15 18:08:51 +02:00
#ifdef CONFIG_PCI_MSI
if (msi && pci_msi_enabled()) {
2017-09-25 19:20:17 +02:00
#if (KERNEL_VERSION(3, 15, 0) <= LINUX_VERSION_CODE)
2017-10-22 19:55:07 +02:00
#if (KERNEL_VERSION(4, 8, 0) <= LINUX_VERSION_CODE)
stat = pci_alloc_irq_vectors(dev->pdev, 1, nr,
PCI_IRQ_MSI | PCI_IRQ_MSIX);
2017-04-10 17:32:16 +02:00
#else
stat = pci_enable_msi_range(dev->pdev, 1, nr);
2017-04-10 11:45:43 +02:00
#endif
2016-04-15 18:08:51 +02:00
if (stat >= 1) {
dev->msi = stat;
dev_info(dev->dev, "using %d MSI interrupt(s)\n",
dev->msi);
2017-08-26 22:04:37 +02:00
} else {
dev_info(dev->dev, "MSI not available.\n");
2017-08-26 22:04:37 +02:00
}
2016-04-15 18:08:51 +02:00
#else
stat = pci_enable_msi_block(dev->pdev, nr);
if (stat == 0) {
2016-04-15 19:16:04 +02:00
dev->msi = nr;
dev_info(dev->dev, "using %d MSI interrupts\n", nr);
2016-05-02 16:27:32 +02:00
} else if (stat == 1) {
2016-04-15 18:08:51 +02:00
stat = pci_enable_msi(dev->pdev);
2016-05-02 16:27:32 +02:00
dev->msi = 1;
2016-04-15 18:08:51 +02:00
}
2017-04-16 21:20:52 +02:00
if (stat < 0)
dev_info(dev->dev, "MSI not available.\n");
2016-04-15 18:08:51 +02:00
#endif
}
#endif
2016-04-15 18:08:51 +02:00
return stat;
}
static int __devinit ddb_irq_init2(struct ddb *dev)
{
int stat;
int irq_flag = IRQF_SHARED;
dev_info(dev->dev, "init type 2 IRQ hardware block\n");
2016-04-15 18:08:51 +02:00
ddbwritel(dev, 0x00000000, INTERRUPT_V2_CONTROL);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_1);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_2);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_3);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_4);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_5);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_6);
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_7);
ddb_irq_msi(dev, 1);
if (dev->msi)
irq_flag = 0;
2017-10-22 19:55:07 +02:00
stat = request_irq(pci_irq_vector(dev->pdev, 0), ddb_irq_handler_v2,
2017-08-26 22:04:37 +02:00
irq_flag, "ddbridge", (void *)dev);
2016-04-15 18:08:51 +02:00
if (stat < 0)
return stat;
2017-04-16 21:20:52 +02:00
2016-05-03 22:05:29 +02:00
ddbwritel(dev, 0x0000ff7f, INTERRUPT_V2_CONTROL);
2016-04-15 18:08:51 +02:00
ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_1);
ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_2);
ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_3);
ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_4);
ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_5);
ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_6);
ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_7);
return stat;
}
2017-04-16 21:20:52 +02:00
2016-04-15 18:08:51 +02:00
static int __devinit ddb_irq_init(struct ddb *dev)
{
int stat;
int irq_flag = IRQF_SHARED;
2017-04-16 21:20:52 +02:00
2016-05-02 16:27:32 +02:00
if (dev->link[0].info->regmap->irq_version == 2)
2016-04-15 18:08:51 +02:00
return ddb_irq_init2(dev);
2017-04-16 21:20:52 +02:00
2016-04-15 18:08:51 +02:00
ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE);
ddbwritel(dev, 0x00000000, MSI1_ENABLE);
ddbwritel(dev, 0x00000000, MSI2_ENABLE);
ddbwritel(dev, 0x00000000, MSI3_ENABLE);
ddbwritel(dev, 0x00000000, MSI4_ENABLE);
ddbwritel(dev, 0x00000000, MSI5_ENABLE);
ddbwritel(dev, 0x00000000, MSI6_ENABLE);
ddbwritel(dev, 0x00000000, MSI7_ENABLE);
ddb_irq_msi(dev, 2);
if (dev->msi)
irq_flag = 0;
if (dev->msi == 2) {
2017-10-22 19:55:07 +02:00
stat = request_irq(pci_irq_vector(dev->pdev, 0), ddb_irq_handler0,
2017-08-26 22:04:37 +02:00
irq_flag, "ddbridge", (void *)dev);
2016-04-15 18:08:51 +02:00
if (stat < 0)
return stat;
2017-10-22 19:55:07 +02:00
stat = request_irq(pci_irq_vector(dev->pdev, 1), ddb_irq_handler1,
2017-08-26 22:04:37 +02:00
irq_flag, "ddbridge", (void *)dev);
2016-04-15 18:08:51 +02:00
if (stat < 0) {
2017-10-22 19:55:07 +02:00
free_irq(pci_irq_vector(dev->pdev, 0), dev);
2016-04-15 18:08:51 +02:00
return stat;
}
2017-07-18 01:25:55 +02:00
} else {
2016-04-15 18:08:51 +02:00
#ifdef DDB_TEST_THREADED
2017-10-22 19:55:07 +02:00
stat = request_threaded_irq(pci_irq_vector(dev->pdev, 0),
dev->pdev->irq, ddb_irq_handler,
2016-04-15 18:08:51 +02:00
irq_thread,
irq_flag,
2017-08-26 22:04:37 +02:00
"ddbridge", (void *)dev);
2016-04-15 18:08:51 +02:00
#else
2017-10-22 19:55:07 +02:00
stat = request_irq(pci_irq_vector(dev->pdev, 0),
ddb_irq_handler,
2017-08-26 22:04:37 +02:00
irq_flag, "ddbridge", (void *)dev);
2016-04-15 18:08:51 +02:00
#endif
if (stat < 0)
return stat;
}
/*ddbwritel(dev, 0xffffffff, INTERRUPT_ACK);*/
if (dev->msi == 2) {
ddbwritel(dev, 0x0fffff00, INTERRUPT_ENABLE);
ddbwritel(dev, 0x0000000f, MSI1_ENABLE);
} else {
ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE);
ddbwritel(dev, 0x00000000, MSI1_ENABLE);
}
return stat;
}
2015-08-05 17:22:42 +02:00
static int __devinit ddb_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct ddb *dev;
int stat = 0;
if (pci_enable_device(pdev) < 0)
return -ENODEV;
2016-04-21 20:11:09 +02:00
pci_set_master(pdev);
if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
return -ENODEV;
2017-04-16 21:20:52 +02:00
2017-08-26 22:04:37 +02:00
dev = vzalloc(sizeof(*dev));
if (!dev)
2015-08-05 17:22:42 +02:00
return -ENOMEM;
mutex_init(&dev->mutex);
dev->has_dma = 1;
dev->pdev = pdev;
dev->dev = &pdev->dev;
pci_set_drvdata(pdev, dev);
dev->link[0].ids.vendor = id->vendor;
dev->link[0].ids.device = id->device;
dev->link[0].ids.subvendor = id->subvendor;
dev->link[0].ids.subdevice = pdev->subsystem_device;
2015-08-05 17:22:42 +02:00
dev->link[0].dev = dev;
dev->link[0].info = get_ddb_info(id->vendor, id->device,
id->subvendor, pdev->subsystem_device);
dev_info(dev->dev, "device name: %s\n", dev->link[0].info->name);
2015-08-05 17:22:42 +02:00
dev->regs_len = pci_resource_len(dev->pdev, 0);
dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
pci_resource_len(dev->pdev, 0));
if (!dev->regs) {
dev_err(dev->dev, "not enough memory for register map\n");
2015-08-05 17:22:42 +02:00
stat = -ENOMEM;
goto fail;
}
if (ddbreadl(dev, 0) == 0xffffffff) {
dev_err(dev->dev, "cannot read registers\n");
2015-08-05 17:22:42 +02:00
stat = -ENODEV;
goto fail;
}
dev->link[0].ids.hwid = ddbreadl(dev, 0);
dev->link[0].ids.regmapid = ddbreadl(dev, 4);
2015-08-05 17:22:42 +02:00
dev_info(dev->dev, "HW %08x REGMAP %08x\n",
dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
2015-08-05 17:22:42 +02:00
if (dev->link[0].info->ns_num) {
ddbwritel(dev, 0, ETHER_CONTROL);
2016-05-02 16:27:32 +02:00
ddb_reset_ios(dev);
2015-08-05 17:22:42 +02:00
}
ddbwritel(dev, 0, DMA_BASE_READ);
if (dev->link[0].info->type != DDB_MOD)
ddbwritel(dev, 0, DMA_BASE_WRITE);
2016-02-12 18:28:00 +01:00
if (dev->link[0].info->type == DDB_MOD
&& dev->link[0].info->version <= 1) {
if (ddbreadl(dev, 0x1c) == 4)
dev->link[0].info =
get_ddb_info(0xdd01, 0x0201, 0xdd01, 0x0004);
}
if (dev->link[0].info->type == DDB_MOD
&& dev->link[0].info->version == 2) {
u32 lic = ddbreadl(dev, 0x1c) & 7;
switch (lic) {
case 0:
dev->link[0].info =
get_ddb_info(0xdd01, 0x0210, 0xdd01, 0x0000);
break;
case 1:
dev->link[0].info =
get_ddb_info(0xdd01, 0x0210, 0xdd01, 0x0003);
break;
case 3:
dev->link[0].info =
get_ddb_info(0xdd01, 0x0210, 0xdd01, 0x0002);
break;
default:
break;
}
2015-08-05 17:22:42 +02:00
}
2016-04-15 18:08:51 +02:00
stat = ddb_irq_init(dev);
if (stat < 0)
goto fail0;
2017-04-16 21:20:52 +02:00
2015-08-05 17:22:42 +02:00
if (ddb_init(dev) == 0)
return 0;
2016-02-12 18:28:00 +01:00
ddb_irq_exit(dev);
2015-08-05 17:22:42 +02:00
fail0:
dev_err(dev->dev, "fail0\n");
2015-08-05 17:22:42 +02:00
if (dev->msi)
pci_disable_msi(dev->pdev);
fail:
dev_err(dev->dev, "fail\n");
2015-08-05 17:22:42 +02:00
ddb_unmap(dev);
2015-12-21 13:48:44 +01:00
pci_set_drvdata(pdev, NULL);
2015-08-05 17:22:42 +02:00
pci_disable_device(pdev);
return -1;
}
/****************************************************************************/
/****************************************************************************/
/****************************************************************************/
#define DDB_DEVICE_ANY(_device) \
{ PCI_DEVICE_SUB(0xdd01, _device, 0xdd01, PCI_ANY_ID) }
2017-04-07 12:28:55 +02:00
static const struct pci_device_id ddb_id_table[] __devinitconst = {
DDB_DEVICE_ANY(0x0002),
2017-04-07 12:28:55 +02:00
DDB_DEVICE_ANY(0x0003),
DDB_DEVICE_ANY(0x0005),
DDB_DEVICE_ANY(0x0006),
DDB_DEVICE_ANY(0x0007),
DDB_DEVICE_ANY(0x0008),
DDB_DEVICE_ANY(0x0011),
DDB_DEVICE_ANY(0x0012),
DDB_DEVICE_ANY(0x0013),
DDB_DEVICE_ANY(0x0201),
DDB_DEVICE_ANY(0x0203),
DDB_DEVICE_ANY(0x0210),
DDB_DEVICE_ANY(0x0220),
DDB_DEVICE_ANY(0x0320),
DDB_DEVICE_ANY(0x0321),
DDB_DEVICE_ANY(0x0322),
DDB_DEVICE_ANY(0x0323),
DDB_DEVICE_ANY(0x0328),
DDB_DEVICE_ANY(0x0329),
2015-08-05 17:22:42 +02:00
{0}
};
2017-04-07 12:28:55 +02:00
MODULE_DEVICE_TABLE(pci, ddb_id_table);
2015-08-05 17:22:42 +02:00
static struct pci_driver ddb_pci_driver = {
.name = "ddbridge",
2017-04-07 12:28:55 +02:00
.id_table = ddb_id_table,
2015-08-05 17:22:42 +02:00
.probe = ddb_probe,
.remove = ddb_remove,
};
static __init int module_init_ddbridge(void)
{
int stat;
2015-08-05 17:22:42 +02:00
pr_info("Digital Devices PCIE bridge driver "
2015-08-05 17:22:42 +02:00
DDBRIDGE_VERSION
2017-05-17 19:42:25 +02:00
", Copyright (C) 2010-17 Digital Devices GmbH\n");
stat = ddb_init_ddbridge();
if (stat < 0)
return stat;
2015-08-05 17:22:42 +02:00
stat = pci_register_driver(&ddb_pci_driver);
if (stat < 0)
ddb_exit_ddbridge(0, stat);
2015-08-05 17:22:42 +02:00
return stat;
}
static __exit void module_exit_ddbridge(void)
{
pci_unregister_driver(&ddb_pci_driver);
ddb_exit_ddbridge(0, 0);
2015-08-05 17:22:42 +02:00
}
module_init(module_init_ddbridge);
module_exit(module_exit_ddbridge);
MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR");
MODULE_LICENSE("GPL");
MODULE_VERSION(DDBRIDGE_VERSION);