add support for cxd2854 (not for dvb-s/s2)
This commit is contained in:
Ralph Metzler
parent
fb022009ee
commit
2ec7863b04
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@ -1,9 +1,10 @@
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/*
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* Driver for the Sony CXD2843ER DVB-T/T2/C/C2 demodulator.
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* Also supports the CXD2837ER DVB-T/T2/C and the
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* CXD2838ER ISDB-T demodulator.
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* Also supports the CXD2837ER DVB-T/T2/C, the
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* CXD2838ER ISDB-T demodulator and the
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* CXD2854 DVB-T/T2/C/C2 ISDB-T demodulator.
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*
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* Copyright (C) 2013-2015 Digital Devices GmbH
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* Copyright (C) 2013-2016 Digital Devices GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -42,7 +43,7 @@
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#define USE_ALGO 1
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enum demod_type { CXD2843, CXD2837, CXD2838 };
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enum demod_type { CXD2843, CXD2837, CXD2838, CXD2854 };
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enum demod_state { Unknown, Shutdown, Sleep, ActiveT,
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ActiveT2, ActiveC, ActiveC2, ActiveIT };
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enum t2_profile { T2P_Base, T2P_Lite };
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@ -83,16 +84,17 @@ struct cxd_state {
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unsigned long tune_time;
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u32 LastBERNominator;
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u32 LastBERNumerator;
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u32 LastBERDenominator;
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u8 BERScaleMax;
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u8 is2k14;
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u8 is24MHz;
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};
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static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
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{
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struct i2c_msg msg = {
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.addr = adr, .flags = 0, .buf = data, .len = len};
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.addr = adr, .flags = 0, .buf = data, .len = len};
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if (i2c_transfer(adap, &msg, 1) != 1) {
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pr_err("cxd2843: i2c_write error\n");
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return -1;
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@ -409,7 +411,8 @@ static void Active_to_Sleep(struct cxd_state *state)
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writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */
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writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */
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writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */
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writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
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writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */
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state->state = Sleep;
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}
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@ -432,7 +435,42 @@ static void ActiveT2_to_Sleep(struct cxd_state *state)
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writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */
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writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */
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writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */
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writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
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writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */
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state->state = Sleep;
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}
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static void ActiveIT_to_Sleep(struct cxd_state *state)
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{
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if (state->state <= Sleep)
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return;
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writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS */
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writeregt(state, 0x00, 0x80, 0x3F); /* Enable HighZ 1 */
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writeregt(state, 0x00, 0x81, 0xFF); /* Enable HighZ 2 */
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if (state->is2k14) {
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writebitst(state, 0x10, 0x69, 0x05, 0x07);
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writebitst(state, 0x10, 0x6b, 0x07, 0x07);
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writebitst(state, 0x10, 0x9d, 0x14, 0xff);
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writebitst(state, 0x10, 0xd3, 0x00, 0x1f);
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writebitst(state, 0x10, 0xed, 0x01, 0x01);
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writebitst(state, 0x10, 0xe2, 0x4e, 0x80);
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writebitst(state, 0x10, 0xf2, 0x03, 0x10);
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writebitst(state, 0x10, 0xde, 0x32, 0x3f);
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writebitst(state, 0x15, 0xde, 0x03, 0x03);
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writebitst(state, 0x1e, 0x73, 0x00, 0xff);
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writebitst(state, 0x63, 0x81, 0x01, 0x01);
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}
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writeregx(state, 0x00, 0x18, 0x01); /* Disable ADC 4 */
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writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */
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writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */
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writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */
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writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
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writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */
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state->state = Sleep;
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}
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@ -478,7 +516,8 @@ static void ActiveC2_to_Sleep(struct cxd_state *state)
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writeregt(state, 0x00, 0x43, 0x0A); /* Disable ADC 2 */
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writeregt(state, 0x00, 0x41, 0x0A); /* Disable ADC 1 */
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writeregt(state, 0x00, 0x30, 0x00); /* Disable ADC Clock */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF level Monitor */
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writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
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writeregt(state, 0x00, 0x2C, 0x00); /* Disable Demod Clock */
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state->state = Sleep;
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}
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@ -582,7 +621,8 @@ static void Sleep_to_ActiveT(struct cxd_state *state, u32 iffreq)
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ConfigureTS(state, ActiveT);
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writeregx(state, 0x00, 0x17, 0x01); /* Mode */
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writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */
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writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
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writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */
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writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */
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{
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@ -678,7 +718,8 @@ static void Sleep_to_ActiveT2(struct cxd_state *state, u32 iffreq)
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writeregx(state, 0x00, 0x17, 0x02); /* Mode */
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writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */
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writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
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writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */
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writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */
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@ -730,7 +771,8 @@ static void Sleep_to_ActiveC(struct cxd_state *state, u32 iffreq)
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writeregx(state, 0x00, 0x17, 0x04); /* Mode */
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writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */
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writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
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writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */
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writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */
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@ -801,7 +843,8 @@ static void Sleep_to_ActiveC2(struct cxd_state *state, u32 iffreq)
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writeregx(state, 0x00, 0x17, 0x05); /* Mode */
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writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */
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writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
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writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */
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writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */
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@ -873,9 +916,12 @@ static void BandSettingIT(struct cxd_state *state, u32 iffreq)
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/* Add EQ Optimisation for tuner here */
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writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data));
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writeregt(state, 0x10, 0xD7, 0x00); /* System Bandwidth */
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writebitst(state, 0x10, 0xD7, 0x00, 0x07); /* System Bandwidth */
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/*u8 CL_data[] = { 0x13, 0xFC }; */
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writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data));
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writebitst(state, 0x12, 0x71, 0x03, 0x07);
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writeregt(state, 0x15, 0xbe, 0x03);
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}
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break;
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case 7:
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@ -887,22 +933,35 @@ static void BandSettingIT(struct cxd_state *state, u32 iffreq)
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writeregst(state, 0x10, 0x9F, TR_data, sizeof(TR_data));
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writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data));
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writeregt(state, 0x10, 0xD7, 0x02);
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writebitst(state, 0x10, 0xD7, 0x02, 0x07);
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/*static u8 CL_data[] = { 0x1A, 0xFA };*/
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writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data));
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writebitst(state, 0x12, 0x71, 0x03, 0x07);
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writeregt(state, 0x15, 0xbe, 0x02);
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}
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break;
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case 6:
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{
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u8 TR_data[] = { 0x14, 0x2E, 0x00, 0x00, 0x00 };
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u8 CL_data[] = { 0x1F, 0xEC };
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/*u8 TR_data[] = { 0x17, 0xA0, 0x00, 0x00, 0x00 }; */
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/*u8 CL_data[] = { 0x1F, 0x79 }; */
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writeregst(state, 0x10, 0x9F, TR_data, sizeof(TR_data));
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writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data));
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writeregt(state, 0x10, 0xD7, 0x04);
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writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data));
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writebitst(state, 0x10, 0xD7, 0x04, 0x07);
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if (state->is2k14) {
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u8 CL_data[] = { 0x1a, 0xe2 };
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writeregst(state, 0x10, 0xDd9, CL_data, sizeof(CL_data));
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} else {
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u8 CL_data[] = { 0x1F, 0xec };
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writeregst(state, 0x10, 0xd9, CL_data, sizeof(CL_data));
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}
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writebitst(state, 0x12, 0x71, 0x07, 0x07);
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writeregt(state, 0x15, 0xbe, 0x02);
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}
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break;
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}
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@ -919,8 +978,13 @@ static void Sleep_to_ActiveIT(struct cxd_state *state, u32 iffreq)
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ConfigureTS(state, ActiveIT);
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/* writeregx(state, 0x00,0x17,0x01); */ /* 2838 has only one Mode */
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if (state->is2k14)
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writeregx(state, 0x00, 0x17, 0x06);
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writeregt(state, 0x00, 0x2C, 0x01); /* Demod Clock */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor */
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if (state->is2k14) {
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writeregt(state, 0x00, 0x59, 0x00); /* Disable RF Monitor ADC */
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writeregt(state, 0x00, 0x2F, 0x00); /* Disable RF Monitor Clock */
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}
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writeregt(state, 0x00, 0x30, 0x00); /* Enable ADC Clock */
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writeregt(state, 0x00, 0x41, 0x1A); /* Enable ADC1 */
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@ -932,13 +996,43 @@ static void Sleep_to_ActiveIT(struct cxd_state *state, u32 iffreq)
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}
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writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */
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writeregst(state, 0x60, 0xA8, data2, sizeof(data2));
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if (state->is2k14) {
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writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */
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writebitst(state, 0x18, 0x30, 0x01, 0x01);
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writebitst(state, 0x18, 0x31, 0x00, 0x01);
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writebitst(state, 0x00, 0xce, 0x00, 0x01);
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writebitst(state, 0x00, 0xcf, 0x00, 0x01);
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writebitst(state, 0x10, 0x69, 0x04, 0x07);
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writebitst(state, 0x10, 0x6b, 0x03, 0x07);
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writebitst(state, 0x10, 0x9d, 0x50, 0xff);
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writebitst(state, 0x10, 0xd3, 0x06, 0x1f);
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writebitst(state, 0x10, 0xed, 0x00, 0x01);
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writebitst(state, 0x10, 0xe2, 0xce, 0x80);
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writebitst(state, 0x10, 0xf2, 0x13, 0x10);
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writebitst(state, 0x10, 0xde, 0x2e, 0x3f);
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writebitst(state, 0x15, 0xde, 0x02, 0x03);
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writebitst(state, 0x1e, 0x73, 0x68, 0xff);
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writebitst(state, 0x63, 0x81, 0x00, 0x01);
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}
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//if( m_is24MHz )
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//{
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// static BYTE TSIF_data[2] = { 0x60,0x00 } ; // 24 MHz
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// CHK_ERROR(WriteRegT(0x10,0xBF,TSIF_data,sizeof(TSIF_data)));
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// static BYTE data[3] = { 0xB7,0x1B,0x00 }; // 24 MHz
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// CHK_ERROR(WriteRegT(0x60,0xA8,data,sizeof(data)));
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//}
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//else
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writeregst(state, 0x10, 0xBF, TSIF_data, sizeof(TSIF_data));
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writeregt(state, 0x10, 0xE2, 0xCE); /* OREG_PNC_DISABLE */
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writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */
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writeregst(state, 0x60, 0xa8, data2, sizeof(data2));
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if (!state->is2k14) {
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writeregt(state, 0x10, 0xE2, 0xCE); /* OREG_PNC_DISABLE */
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writebitst(state, 0x10, 0xA5, 0x00, 0x01); /* ASCOT Off */
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}
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BandSettingIT(state, iffreq);
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writeregt(state, 0x00, 0x80, 0x28); /* Disable HiZ Setting 1 */
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@ -1046,6 +1140,9 @@ static void ShutDown(struct cxd_state *state)
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case ActiveC2:
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ActiveC2_to_Sleep(state);
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break;
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case ActiveIT:
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ActiveIT_to_Sleep(state);
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break;
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default:
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Active_to_Sleep(state);
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break;
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@ -1105,12 +1202,14 @@ static int Start(struct cxd_state *state, u32 IntermediateFrequency)
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newDemodState = ActiveC;
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break;
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case OM_DVBC2:
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if (state->type != CXD2843)
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if (state->type != CXD2843 && state->type != CXD2854)
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return -EINVAL;
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newDemodState = ActiveC2;
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break;
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case OM_ISDBT:
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if (state->type != CXD2838)
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if (state->type != CXD2838 && state->type != CXD2854)
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return -EINVAL;
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if (state->type == CXD2854 && !state->is24MHz && state->bw != 6)
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return -EINVAL;
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newDemodState = ActiveIT;
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break;
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@ -1123,7 +1222,7 @@ static int Start(struct cxd_state *state, u32 IntermediateFrequency)
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state->L1PostTimeout = 0;
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state->last_status = 0;
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state->FirstTimeLock = 1;
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state->LastBERNominator = 0;
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state->LastBERNumerator = 0;
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state->LastBERDenominator = 1;
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state->BERScaleMax = 19;
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@ -1165,6 +1264,9 @@ static int Start(struct cxd_state *state, u32 IntermediateFrequency)
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case ActiveC2:
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ActiveC2_to_Sleep(state);
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break;
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case ActiveIT:
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ActiveIT_to_Sleep(state);
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break;
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default:
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Active_to_Sleep(state);
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break;
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@ -1474,16 +1576,16 @@ static int get_ber_t(struct cxd_state *state, u32 *n, u32 *d)
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Scale &= 0x1F;
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if (BERRegs[0] & 0x80) {
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state->LastBERNominator = (((u32) BERRegs[0] & 0x3F) << 16) |
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state->LastBERNumerator = (((u32) BERRegs[0] & 0x3F) << 16) |
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(((u32) BERRegs[1]) << 8) | BERRegs[2];
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state->LastBERDenominator = 1632 << Scale;
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if (state->LastBERNominator < 256 &&
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if (state->LastBERNumerator < 256 &&
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Scale < state->BERScaleMax) {
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writebitst(state, 0x10, 0x60, Scale + 1, 0x1F);
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} else if (state->LastBERNominator > 512 && Scale > 11)
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} else if (state->LastBERNumerator > 512 && Scale > 11)
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writebitst(state, 0x10, 0x60, Scale - 1, 0x1F);
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}
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*n = state->LastBERNominator;
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*n = state->LastBERNumerator;
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*d = state->LastBERDenominator;
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return 0;
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@ -1518,16 +1620,16 @@ static int get_ber_t2(struct cxd_state *state, u32 *n, u32 *d)
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readregst(state, 0x20, 0x72, &Scale, 1);
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Scale &= 0x0F;
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if (BERRegs[0] & 0x01) {
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state->LastBERNominator = (((u32) BERRegs[1] & 0x3F) << 16) |
|
||||
state->LastBERNumerator = (((u32) BERRegs[1] & 0x3F) << 16) |
|
||||
(((u32) BERRegs[2]) << 8) | BERRegs[3];
|
||||
state->LastBERDenominator = nBCHBitsLookup[FECType][CodeRate] << Scale;
|
||||
if (state->LastBERNominator < 256 &&
|
||||
if (state->LastBERNumerator < 256 &&
|
||||
Scale < state->BERScaleMax) {
|
||||
writebitst(state, 0x20, 0x72, Scale + 1, 0x0F);
|
||||
} else if (state->LastBERNominator > 512 && Scale > 8)
|
||||
} else if (state->LastBERNumerator > 512 && Scale > 8)
|
||||
writebitst(state, 0x20, 0x72, Scale - 1, 0x0F);
|
||||
}
|
||||
*n = state->LastBERNominator;
|
||||
*n = state->LastBERNumerator;
|
||||
*d = state->LastBERDenominator;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1545,16 +1647,16 @@ static int get_ber_c(struct cxd_state *state, u32 *n, u32 *d)
|
|||
Scale &= 0x1F;
|
||||
|
||||
if (BERRegs[0] & 0x80) {
|
||||
state->LastBERNominator = (((u32) BERRegs[0] & 0x3F) << 16) |
|
||||
state->LastBERNumerator = (((u32) BERRegs[0] & 0x3F) << 16) |
|
||||
(((u32) BERRegs[1]) << 8) | BERRegs[2];
|
||||
state->LastBERDenominator = 1632 << Scale;
|
||||
if (state->LastBERNominator < 256 &&
|
||||
if (state->LastBERNumerator < 256 &&
|
||||
Scale < state->BERScaleMax) {
|
||||
writebitst(state, 0x40, 0x60, Scale + 1, 0x1F);
|
||||
} else if (state->LastBERNominator > 512 && Scale > 11)
|
||||
} else if (state->LastBERNumerator > 512 && Scale > 11)
|
||||
writebitst(state, 0x40, 0x60, Scale - 1, 0x1F);
|
||||
}
|
||||
*n = state->LastBERNominator;
|
||||
*n = state->LastBERNumerator;
|
||||
*d = state->LastBERDenominator;
|
||||
|
||||
return 0;
|
||||
|
|
@ -2152,6 +2254,39 @@ static int get_frontend(struct dvb_frontend *fe)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct dvb_frontend_ops common_ops_2854 = {
|
||||
.delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2, SYS_DVBC2, SYS_ISDBT },
|
||||
.info = {
|
||||
.name = "CXD2854 DVB-C/C2 DVB-T/T2 ISDB-T",
|
||||
.frequency_stepsize = 166667, /* DVB-T only */
|
||||
.frequency_min = 47000000, /* DVB-T: 47125000 */
|
||||
.frequency_max = 865000000, /* DVB-C: 862000000 */
|
||||
.symbol_rate_min = 870000,
|
||||
.symbol_rate_max = 11700000,
|
||||
.caps = FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 |
|
||||
FE_CAN_QAM_64 | FE_CAN_QAM_128 | FE_CAN_QAM_256 |
|
||||
FE_CAN_QAM_AUTO |
|
||||
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
||||
FE_CAN_FEC_4_5 |
|
||||
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
|
||||
FE_CAN_TRANSMISSION_MODE_AUTO |
|
||||
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO |
|
||||
FE_CAN_RECOVER | FE_CAN_MUTE_TS | FE_CAN_2G_MODULATION
|
||||
},
|
||||
.release = release,
|
||||
.sleep = sleep,
|
||||
.i2c_gate_ctrl = gate_ctrl,
|
||||
.set_frontend = set_parameters,
|
||||
|
||||
.get_tune_settings = get_tune_settings,
|
||||
.read_status = read_status,
|
||||
.read_ber = read_ber,
|
||||
.read_signal_strength = read_signal_strength,
|
||||
.read_snr = read_snr,
|
||||
.read_ucblocks = read_ucblocks,
|
||||
.get_frontend = get_frontend,
|
||||
};
|
||||
|
||||
static struct dvb_frontend_ops common_ops_2843 = {
|
||||
.delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2, SYS_DVBC2 },
|
||||
.info = {
|
||||
|
|
@ -2292,6 +2427,12 @@ static int probe(struct cxd_state *state)
|
|||
memcpy(&state->frontend.ops, &common_ops_2838,
|
||||
sizeof(struct dvb_frontend_ops));
|
||||
break;
|
||||
case 0xc1:
|
||||
state->type = CXD2854;
|
||||
memcpy(&state->frontend.ops, &common_ops_2854,
|
||||
sizeof(struct dvb_frontend_ops));
|
||||
state->is2k14 = 1;
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue