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https://github.com/DigitalDevices/dddvb.git
synced 2023-10-10 13:37:43 +02:00
add IQ output rate property
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parent
83344e1349
commit
4196458803
@ -1477,12 +1477,46 @@ static int mod3_set_ari(struct ddb_mod *mod, u32 rate)
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}
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static int mod3_set_sample_rate(struct ddb_mod *mod, u32 rate)
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{
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u32 cic, inc;
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switch (rate) {
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case SYS_DVBT_6:
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inc = 1917396114;
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cic = 8;
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break;
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case SYS_DVBT_7:
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inc = 1957341867;
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cic = 7;
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break;
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case SYS_DVBT_8:
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//rate = 8126984;
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inc = 1917396114;
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cic = 6;
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break;
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case SYS_ISDBT_6:
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inc = 1988410754;
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cic = 7;
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break;
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default:
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return -EINVAL;
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}
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ddbwritel(mod->port->dev, inc, SDR_CHANNEL_ARICW(mod->port->nr));
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ddbwritel(mod->port->dev, cic << 8, SDR_CHANNEL_CONFIG(mod->port->nr));
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return 0;
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}
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static int mod3_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
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{
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switch (tvp->cmd) {
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case MODULATOR_OUTPUT_ARI:
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return mod3_set_ari(mod, tvp->u.data);
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case MODULATOR_OUTPUT_RATE:
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return mod3_set_sample_rate(mod, tvp->u.data);
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case MODULATOR_FREQUENCY:
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return mod3_set_frequency(mod, tvp->u.data);
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@ -1550,6 +1584,9 @@ static int mod_prop_get3(struct ddb_mod *mod, struct dtv_property *tvp)
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case MODULATOR_INFO:
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tvp->u.data = dev->link[0].info->version;
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return 0;
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case MODULATOR_GAIN:
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tvp->u.data = 0xff & ddbreadl(dev, RF_VGA);
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return 0;
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default:
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return -1;
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}
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@ -1569,7 +1606,7 @@ static int mod_prop_get(struct ddb_mod *mod, struct dtv_property *tvp)
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return 0;
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case MODULATOR_GAIN:
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tvp->u.data = 0xff & ddbreadl(dev, RF_VGA);;
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tvp->u.data = 0xff & ddbreadl(dev, RF_VGA);
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return 0;
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case MODULATOR_ATTENUATOR:
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