mirror of
https://github.com/DigitalDevices/dddvb.git
synced 2023-10-10 13:37:43 +02:00
change lnb and ci bases to be configurable
This commit is contained in:
parent
a233c8a6f8
commit
4d087a3b8c
@ -32,7 +32,7 @@ static int wait_ci_ready(struct ddb_ci *ci)
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ndelay(500);
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do {
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if (ddbreadl(ci->port->dev,
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CI_CONTROL(ci->nr)) & CI_READY)
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CI_CONTROL(ci)) & CI_READY)
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break;
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usleep_range(1, 2);
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if ((--count) == 0)
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@ -50,7 +50,7 @@ static int read_attribute_mem(struct dvb_ca_en50221 *ca,
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if (address > CI_BUFFER_SIZE)
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return -1;
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ddbwritel(ci->port->dev, CI_READ_CMD | (1 << 16) | address,
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CI_DO_READ_ATTRIBUTES(ci->nr));
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CI_DO_READ_ATTRIBUTES(ci));
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wait_ci_ready(ci);
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val = 0xff & ddbreadl(ci->port->dev, CI_BUFFER(ci->nr) + off);
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return val;
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@ -62,7 +62,7 @@ static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
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struct ddb_ci *ci = ca->data;
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ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address,
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CI_DO_ATTRIBUTE_RW(ci->nr));
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CI_DO_ATTRIBUTE_RW(ci));
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wait_ci_ready(ci);
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return 0;
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}
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@ -75,10 +75,10 @@ static int read_cam_control(struct dvb_ca_en50221 *ca,
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u32 res;
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ddbwritel(ci->port->dev, CI_READ_CMD | address,
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CI_DO_IO_RW(ci->nr));
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CI_DO_IO_RW(ci));
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ndelay(500);
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do {
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res = ddbreadl(ci->port->dev, CI_READDATA(ci->nr));
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res = ddbreadl(ci->port->dev, CI_READDATA(ci));
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if (res & CI_READY)
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break;
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usleep_range(1, 2);
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@ -94,7 +94,7 @@ static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
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struct ddb_ci *ci = ca->data;
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ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address,
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CI_DO_IO_RW(ci->nr));
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CI_DO_IO_RW(ci));
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wait_ci_ready(ci);
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return 0;
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}
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@ -104,15 +104,15 @@ static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
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struct ddb_ci *ci = ca->data;
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ddbwritel(ci->port->dev, CI_POWER_ON,
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CI_CONTROL(ci->nr));
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CI_CONTROL(ci));
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msleep(300);
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ddbwritel(ci->port->dev, CI_POWER_ON | CI_RESET_CAM,
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CI_CONTROL(ci->nr));
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CI_CONTROL(ci));
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ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON | CI_RESET_CAM,
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CI_CONTROL(ci->nr));
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CI_CONTROL(ci));
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usleep_range(20, 25);
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ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON,
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CI_CONTROL(ci->nr));
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CI_CONTROL(ci));
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return 0;
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}
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@ -120,7 +120,7 @@ static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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ddbwritel(ci->port->dev, 0, CI_CONTROL(ci->nr));
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ddbwritel(ci->port->dev, 0, CI_CONTROL(ci));
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msleep(300);
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return 0;
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}
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@ -128,17 +128,17 @@ static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
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static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr));
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u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci));
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ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE,
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CI_CONTROL(ci->nr));
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CI_CONTROL(ci));
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return 0;
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}
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static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
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{
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struct ddb_ci *ci = ca->data;
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u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr));
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u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci));
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int stat = 0;
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if (val & CI_CAM_DETECT)
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@ -162,6 +162,8 @@ static struct dvb_ca_en50221 en_templ = {
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static void ci_attach(struct ddb_port *port)
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{
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struct ddb_ci *ci;
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const struct ddb_info *info = port->dev->link[port->lnr].info;
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u32 off = info->ci_base ? info->ci_base : 0x400;
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ci = kzalloc(sizeof(*ci), GFP_KERNEL);
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if (!ci)
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@ -171,6 +173,7 @@ static void ci_attach(struct ddb_port *port)
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port->en = &ci->en;
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ci->port = port;
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ci->nr = port->nr - 2;
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ci->regs = DDB_LINK_TAG(port->lnr) | (off + 32 * ci->nr);
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}
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/* DuoFlex Dual CI support */
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@ -467,7 +467,7 @@ static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
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gap = output->port->gap;
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max_bitrate = 0;
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}
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if (dev->link[0].info->type == DDB_OCTOPUS_CI && output->port->nr > 1) {
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if (dev->link[0].info->ci_mask && output->port->nr > 1) {
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*con = 0x10c;
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if (dev->link[0].ids.regmapid >= 0x10003 && !(flags & 1)) {
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if (!(flags & 2)) {
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@ -1596,8 +1596,7 @@ static int dvb_register_adapters(struct ddb *dev)
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}
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if (adapter_alloc >= 3 || dev->link[0].info->type == DDB_MOD ||
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dev->link[0].info->type == DDB_OCTONET ||
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dev->link[0].info->type == DDB_OCTOPRO) {
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dev->link[0].info->type == DDB_OCTONET) {
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port = &dev->port[0];
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adap = port->dvb[0].adap;
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ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
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@ -2102,7 +2101,7 @@ static void ddb_port_probe(struct ddb_port *port)
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return;
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}
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if (port->nr == 1 && link->info->type == DDB_OCTOPUS_CI &&
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if (port->nr == 1 && link->info->ci_mask &&
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link->info->i2c_mask == 1) {
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port->name = "NO TAB";
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port->class = DDB_PORT_NONE;
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@ -2130,15 +2129,16 @@ static void ddb_port_probe(struct ddb_port *port)
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port->name = "DUAL MCI";
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port->type_name = "MCI";
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port->class = DDB_PORT_TUNER;
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port->type = DDB_TUNER_MCI + link->info->mci_type;
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port->type = link->info->mci_type;
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return;
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}
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if (port->nr > 1 && link->info->type == DDB_OCTOPUS_CI) {
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if (port->nr > 1 && (link->info->ci_mask & (1 << port->nr))) {
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port->name = "CI internal";
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port->type_name = "INTERNAL";
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port->class = DDB_PORT_CI;
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port->type = DDB_CI_INTERNAL;
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return;
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}
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if (!port->i2c)
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@ -2716,24 +2716,28 @@ static void ddb_ports_init(struct ddb *dev)
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continue;
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switch (info->type) {
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case DDB_OCTOPUS_CI:
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if (i >= 2) {
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case DDB_OCTONET:
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case DDB_OCTOPUS:
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if (info->ci_mask & (1 << i)) {
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ddb_input_init(port, 2 + i, 0, 2 + i);
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ddb_input_init(port, 4 + i, 1, 4 + i);
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ddb_output_init(port, i);
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break;
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}
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fallthrough;
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case DDB_OCTONET:
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case DDB_OCTOPUS:
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case DDB_OCTOPRO:
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ddb_input_init(port, 2 * i, 0, 2 * i);
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ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1);
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ddb_output_init(port, i);
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ddb_input_init(port, 2 * i, 0, 2 * p);
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ddb_input_init(port, 2 * i + 1, 1, 2 * p + 1);
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ddb_output_init(port, i);
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break;
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case DDB_OCTOPUS_MAX:
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case DDB_OCTOPUS_MAX_CT:
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case DDB_OCTOPUS_MCI:
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if (info->ci_mask & (1 << i)) {
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ddb_input_init(port, 2 + i, 0, 2 + i);
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ddb_input_init(port, 4 + i, 1, 4 + i);
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ddb_output_init(port, i);
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break;
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}
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ddb_input_init(port, 2 * i, 0, 2 * p);
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ddb_input_init(port, 2 * i + 1, 1, 2 * p + 1);
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break;
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@ -246,7 +246,6 @@ static const struct ddb_regmap octopus_map = {
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.odma = &octopus_odma,
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.odma_buf = &octopus_odma_buf,
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.input = &octopus_input,
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.output = &octopus_output,
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};
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@ -463,23 +462,25 @@ static const struct ddb_info ddb_satixs2v3 = {
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};
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static const struct ddb_info ddb_ci = {
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.type = DDB_OCTOPUS_CI,
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.type = DDB_OCTOPUS,
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.name = "Digital Devices Octopus CI",
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.regmap = &octopus_map,
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.port_num = 4,
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.i2c_mask = 0x03,
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.ci_mask = 0x0c,
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};
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static const struct ddb_info ddb_cis = {
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.type = DDB_OCTOPUS_CI,
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.type = DDB_OCTOPUS,
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.name = "Digital Devices Octopus CI single",
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.regmap = &octopus_map,
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.port_num = 3,
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.i2c_mask = 0x03,
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.ci_mask = 0x04,
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};
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static const struct ddb_info ddb_ci_s2_pro = {
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.type = DDB_OCTOPUS_CI,
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.type = DDB_OCTOPUS,
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.name = "Digital Devices Octopus CI S2 Pro",
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.regmap = &octopus_map,
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.port_num = 4,
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@ -487,10 +488,11 @@ static const struct ddb_info ddb_ci_s2_pro = {
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.board_control = 2,
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.board_control_2 = 4,
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.hw_min = 0x010007,
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.ci_mask = 0x0c,
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};
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static const struct ddb_info ddb_ci_s2_pro_a = {
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.type = DDB_OCTOPUS_CI,
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.type = DDB_OCTOPUS,
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.name = "Digital Devices Octopus CI S2 Pro Advanced",
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.regmap = &octopus_map,
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.port_num = 4,
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@ -498,6 +500,7 @@ static const struct ddb_info ddb_ci_s2_pro_a = {
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.board_control = 2,
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.board_control_2 = 4,
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.hw_min = 0x010007,
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.ci_mask = 0x0c,
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};
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static const struct ddb_info ddb_dvbct = {
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@ -621,24 +624,6 @@ static const struct ddb_info ddb_sdr_dvbt = {
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.tempmon_irq = 8,
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};
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static const struct ddb_info ddb_octopro_hdin = {
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.type = DDB_OCTOPRO_HDIN,
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.name = "Digital Devices OctopusNet Pro HDIN",
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.regmap = &octopro_hdin_map,
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.port_num = 10,
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.i2c_mask = 0x3ff,
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.mdio_base = 0x10020,
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};
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static const struct ddb_info ddb_octopro = {
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.type = DDB_OCTOPRO,
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.name = "Digital Devices OctopusNet Pro",
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.regmap = &octopro_map,
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.port_num = 10,
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.i2c_mask = 0x3ff,
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.mdio_base = 0x10020,
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};
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static const struct ddb_info ddb_s2_48 = {
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.type = DDB_OCTOPUS_MAX,
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.name = "Digital Devices MAX S8 4/8",
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@ -647,6 +632,7 @@ static const struct ddb_info ddb_s2_48 = {
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.i2c_mask = 0x01,
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.board_control = 1,
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.tempmon_irq = 24,
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.lnb_base = 0x400,
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};
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static const struct ddb_info ddb_ct2_8 = {
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@ -719,8 +705,9 @@ static const struct ddb_info ddb_s2x_48 = {
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.i2c_mask = 0x00,
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.tempmon_irq = 24,
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.mci_ports = 4,
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.mci_type = 0,
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.mci_type = DDB_TUNER_MCI_SX8,
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.temp_num = 1,
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.lnb_base = 0x400,
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};
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static const struct ddb_info ddb_s2x_48_b = {
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@ -731,8 +718,9 @@ static const struct ddb_info ddb_s2x_48_b = {
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.i2c_mask = 0x00,
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.tempmon_irq = 24,
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.mci_ports = 4,
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.mci_type = 0,
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.mci_type = DDB_TUNER_MCI_SX8,
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.temp_num = 1,
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.lnb_base = 0x400,
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};
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static const struct ddb_info ddb_m4 = {
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@ -49,11 +49,12 @@ MODULE_PARM_DESC(no_voltage, "Do not enable voltage on LNBH (will also disable 2
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static int lnb_command(struct ddb *dev, u32 link, u32 lnb, u32 cmd)
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{
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u32 c, v = 0, tag = DDB_LINK_TAG(link);
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u32 base = dev->link[link].info->lnb_base;
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v = LNB_TONE & (dev->link[link].lnb.tone << (15 - lnb));
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ddbwritel(dev, cmd | v, tag | LNB_CONTROL(lnb));
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ddbwritel(dev, cmd | v, tag | base | LNB_CONTROL(lnb));
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for (c = 0; c < 10; c++) {
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v = ddbreadl(dev, tag | LNB_CONTROL(lnb));
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v = ddbreadl(dev, tag | base | LNB_CONTROL(lnb));
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if ((v & LNB_BUSY) == 0)
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break;
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msleep(20);
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@ -91,6 +92,7 @@ static int max_send_master_cmd(struct dvb_frontend *fe,
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struct ddb *dev = port->dev;
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struct ddb_dvb *dvb = &port->dvb[input->nr & 1];
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u32 tag = DDB_LINK_TAG(port->lnr);
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u32 base = dev->link[port->lnr].info->lnb_base;
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int i;
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u32 fmode = dev->link[port->lnr].lnb.fmode;
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@ -105,9 +107,9 @@ static int max_send_master_cmd(struct dvb_frontend *fe,
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dvb->diseqc_send_master_cmd(fe, cmd);
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mutex_lock(&dev->link[port->lnr].lnb.lock);
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ddbwritel(dev, 0, tag | LNB_BUF_LEVEL(dvb->input));
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ddbwritel(dev, 0, tag | base | LNB_BUF_LEVEL(dvb->input));
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for (i = 0; i < cmd->msg_len; i++)
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ddbwritel(dev, cmd->msg[i], tag | LNB_BUF_WRITE(dvb->input));
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ddbwritel(dev, cmd->msg[i], tag | base | LNB_BUF_WRITE(dvb->input));
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lnb_command(dev, port->lnr, dvb->input, LNB_CMD_DISEQC);
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mutex_unlock(&dev->link[port->lnr].lnb.lock);
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return 0;
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@ -117,11 +119,12 @@ static int lnb_send_diseqc(struct ddb *dev, u32 link, u32 input,
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struct dvb_diseqc_master_cmd *cmd)
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{
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u32 tag = DDB_LINK_TAG(link);
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u32 base = dev->link[link].info->lnb_base;
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int i;
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ddbwritel(dev, 0, tag | LNB_BUF_LEVEL(input));
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ddbwritel(dev, 0, tag | base | LNB_BUF_LEVEL(input));
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for (i = 0; i < cmd->msg_len; i++)
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ddbwritel(dev, cmd->msg[i], tag | LNB_BUF_WRITE(input));
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ddbwritel(dev, cmd->msg[i], tag | base | LNB_BUF_WRITE(input));
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lnb_command(dev, link, input, LNB_CMD_DISEQC);
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return 0;
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}
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@ -369,6 +372,7 @@ static int max_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
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struct ddb_port *port = input->port;
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struct ddb *dev = port->dev;
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u32 tag = DDB_LINK_TAG(port->lnr);
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u32 base = dev->link[port->lnr].info->lnb_base;
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struct ddb_dvb *dvb = &port->dvb[input->nr & 1];
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u32 fmode = dev->link[port->lnr].lnb.fmode;
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@ -377,14 +381,14 @@ static int max_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
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default:
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case 0:
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case 3:
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ddbwritel(dev, arg ? 0x34 : 0x01, tag | LNB_CONTROL(dvb->input));
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ddbwritel(dev, arg ? 0x34 : 0x01, tag | base | LNB_CONTROL(dvb->input));
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break;
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case 1:
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case 2:
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ddbwritel(dev, arg ? 0x34 : 0x01, tag | LNB_CONTROL(0));
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ddbwritel(dev, arg ? 0x34 : 0x01, tag | LNB_CONTROL(1));
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ddbwritel(dev, arg ? 0x34 : 0x01, tag | LNB_CONTROL(2));
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ddbwritel(dev, arg ? 0x34 : 0x01, tag | LNB_CONTROL(3));
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ddbwritel(dev, arg ? 0x34 : 0x01, tag | base | LNB_CONTROL(0));
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ddbwritel(dev, arg ? 0x34 : 0x01, tag | base | LNB_CONTROL(1));
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ddbwritel(dev, arg ? 0x34 : 0x01, tag | base | LNB_CONTROL(2));
|
||||
ddbwritel(dev, arg ? 0x34 : 0x01, tag | base | LNB_CONTROL(3));
|
||||
break;
|
||||
}
|
||||
mutex_unlock(&dev->link[port->lnr].lnb.lock);
|
||||
|
@ -248,8 +248,7 @@
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define LNB_BASE (0x400)
|
||||
#define LNB_CONTROL(i) (LNB_BASE + (i) * 0x20 + 0x00)
|
||||
#define LNB_CONTROL(i) ((i) * 0x20 + 0x00)
|
||||
#define LNB_CMD (7ULL << 0)
|
||||
#define LNB_CMD_NOP 0
|
||||
#define LNB_CMD_INIT 1
|
||||
@ -265,27 +264,26 @@
|
||||
|
||||
#define LNB_INTERRUPT_BASE 4
|
||||
|
||||
#define LNB_STATUS(i) (LNB_BASE + (i) * 0x20 + 0x04)
|
||||
#define LNB_VOLTAGE(i) (LNB_BASE + (i) * 0x20 + 0x08)
|
||||
#define LNB_CONFIG(i) (LNB_BASE + (i) * 0x20 + 0x0c)
|
||||
#define LNB_BUF_LEVEL(i) (LNB_BASE + (i) * 0x20 + 0x10)
|
||||
#define LNB_BUF_WRITE(i) (LNB_BASE + (i) * 0x20 + 0x14)
|
||||
#define LNB_STATUS(i) ((i) * 0x20 + 0x04)
|
||||
#define LNB_VOLTAGE(i) ((i) * 0x20 + 0x08)
|
||||
#define LNB_CONFIG(i) ((i) * 0x20 + 0x0c)
|
||||
#define LNB_BUF_LEVEL(i) ((i) * 0x20 + 0x10)
|
||||
#define LNB_BUF_WRITE(i) ((i) * 0x20 + 0x14)
|
||||
|
||||
#define LNB_SETTING(i) (LNB_BASE + (i) * 0x20 + 0x0c)
|
||||
#define LNB_FIFO_LEVEL(i) (LNB_BASE + (i) * 0x20 + 0x10)
|
||||
#define LNB_RESET_FIFO(i) (LNB_BASE + (i) * 0x20 + 0x10)
|
||||
#define LNB_WRITE_FIFO(i) (LNB_BASE + (i) * 0x20 + 0x14)
|
||||
#define LNB_SETTING(i) ((i) * 0x20 + 0x0c)
|
||||
#define LNB_FIFO_LEVEL(i) ((i) * 0x20 + 0x10)
|
||||
#define LNB_RESET_FIFO(i) ((i) * 0x20 + 0x10)
|
||||
#define LNB_WRITE_FIFO(i) ((i) * 0x20 + 0x14)
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* CI Interface (only CI-Bridge) */
|
||||
|
||||
#define CI_BASE (0x400)
|
||||
#define CI_CONTROL(i) (CI_BASE + (i) * 32 + 0x00)
|
||||
#define CI_CONTROL(_ci) ((_ci)->regs + 0x00)
|
||||
|
||||
#define CI_DO_ATTRIBUTE_RW(i) (CI_BASE + (i) * 32 + 0x04)
|
||||
#define CI_DO_IO_RW(i) (CI_BASE + (i) * 32 + 0x08)
|
||||
#define CI_READDATA(i) (CI_BASE + (i) * 32 + 0x0c)
|
||||
#define CI_DO_READ_ATTRIBUTES(i) (CI_BASE + (i) * 32 + 0x10)
|
||||
#define CI_DO_ATTRIBUTE_RW(_ci) ((_ci)->regs + 0x04)
|
||||
#define CI_DO_IO_RW(_ci) ((_ci)->regs + 0x08)
|
||||
#define CI_READDATA(_ci) ((_ci)->regs + 0x0c)
|
||||
#define CI_DO_READ_ATTRIBUTES(_ci) ((_ci)->regs + 0x10)
|
||||
|
||||
#define CI_RESET_CAM (0x00000001)
|
||||
#define CI_POWER_ON (0x00000002)
|
||||
@ -305,8 +303,8 @@
|
||||
#define CI_READ_CMD (0x40000000)
|
||||
#define CI_WRITE_CMD (0x80000000)
|
||||
|
||||
#define CI_BLOCKIO_SEND(i) (CI_BASE + (i) * 32 + 0x14)
|
||||
#define CI_BLOCKIO_RECEIVE(i) (CI_BASE + (i) * 32 + 0x18)
|
||||
#define CI_BLOCKIO_SEND(_ci) ((_ci)->regs + 0x14)
|
||||
#define CI_BLOCKIO_RECEIVE(_ci) ((_ci)->regs + 0x18)
|
||||
|
||||
#define CI_BLOCKIO_SEND_COMMAND (0x80000000)
|
||||
#define CI_BLOCKIO_SEND_COMPLETE_ACK (0x40000000)
|
||||
|
@ -147,13 +147,10 @@ struct ddb_info {
|
||||
u32 type;
|
||||
#define DDB_NONE 0
|
||||
#define DDB_OCTOPUS 1
|
||||
#define DDB_OCTOPUS_CI 2
|
||||
#define DDB_MOD 3
|
||||
#define DDB_OCTONET 4
|
||||
#define DDB_OCTOPUS_MAX 5
|
||||
#define DDB_OCTOPUS_MAX_CT 6
|
||||
#define DDB_OCTOPRO 7
|
||||
#define DDB_OCTOPRO_HDIN 8
|
||||
#define DDB_OCTOPUS_MCI 9
|
||||
u32 version;
|
||||
char *name;
|
||||
@ -175,11 +172,14 @@ struct ddb_info {
|
||||
#define TS_QUIRK_ALT_OSC 8
|
||||
u8 mci_ports;
|
||||
u8 mci_type;
|
||||
u8 ci_mask;
|
||||
|
||||
u32 tempmon_irq;
|
||||
u32 lostlock_irq;
|
||||
u32 mdio_base;
|
||||
u32 hw_min;
|
||||
u32 ci_base;
|
||||
u32 lnb_base;
|
||||
const struct ddb_regmap *regmap;
|
||||
};
|
||||
|
||||
@ -247,6 +247,7 @@ struct ddb_ci {
|
||||
struct dvb_ca_en50221 en;
|
||||
struct ddb_port *port;
|
||||
u32 nr;
|
||||
u32 regs;
|
||||
};
|
||||
|
||||
struct ddb_io {
|
||||
|
Loading…
Reference in New Issue
Block a user