mirror of
https://github.com/DigitalDevices/dddvb.git
synced 2023-10-10 13:37:43 +02:00
change output functions from pr_ to dev_
This commit is contained in:
Ralph Metzler
parent
df4f23384b
commit
5074e28e10
@ -151,7 +151,6 @@ static int ddb_unredirect(struct ddb_port *port)
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struct ddb_input *oredi, *iredi = 0;
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struct ddb_output *iredo = 0;
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/*pr_info("DDBridge: unredirect %d.%d\n", port->dev->nr, port->nr);*/
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mutex_lock(&redirect_lock);
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if (port->output->dma->running) {
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mutex_unlock(&redirect_lock);
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@ -445,7 +444,6 @@ static void ddb_output_start(struct ddb_output *output)
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struct ddb *dev = output->port->dev;
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u32 con = 0x11c, con2 = 0;
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pr_info("Channel Base = %08x\n", output->regs);
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if (output->dma) {
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spin_lock_irq(&output->dma->lock);
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output->dma->cbuf = 0;
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@ -781,7 +779,7 @@ static u32 ddb_input_avail(struct ddb_input *input)
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off = (stat & 0x7ff) << 7;
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if (ctrl & 4) {
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pr_err("DDBridge: IA %d %d %08x\n", idx, off, ctrl);
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dev_err(dev->dev, "IA %d %d %08x\n", idx, off, ctrl);
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ddbwritel(dev, stat, DMA_BUFFER_ACK(input->dma));
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return 0;
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}
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@ -1061,7 +1059,8 @@ static int demod_attach_drxk(struct ddb_input *input)
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i2c, 0x29 + (input->nr & 1),
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&dvb->fe2);
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if (!fe) {
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pr_err("DDBridge: No DRXK found!\n");
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dev_err(input->port->dev->dev,
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"No DRXK found!\n");
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return -ENODEV;
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}
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fe->sec_priv = input;
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@ -1085,7 +1084,8 @@ static int demod_attach_cxd2843(struct ddb_input *input, int par, int osc24)
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fe = dvb->fe = dvb_attach(cxd2843_attach, i2c, &cfg);
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if (!dvb->fe) {
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pr_err("DDBridge: No cxd2837/38/43/54 found!\n");
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dev_err(input->port->dev->dev,
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"No cxd2837/38/43/54 found!\n");
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return -ENODEV;
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}
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fe->sec_priv = input;
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@ -1108,7 +1108,8 @@ static int demod_attach_stv0367dd(struct ddb_input *input)
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&cfg,
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&dvb->fe2);
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if (!dvb->fe) {
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pr_err("DDBridge: No stv0367 found!\n");
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dev_err(input->port->dev->dev,
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"No stv0367 found!\n");
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return -ENODEV;
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}
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fe->sec_priv = input;
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@ -1129,7 +1130,8 @@ static int tuner_attach_tda18271(struct ddb_input *input)
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if (dvb->fe->ops.i2c_gate_ctrl)
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dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 0);
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if (!fe) {
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pr_err("DDBridge: No TDA18271 found!\n");
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dev_err(input->port->dev->dev,
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"No TDA18271 found!\n");
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return -ENODEV;
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}
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return 0;
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@ -1144,7 +1146,8 @@ static int tuner_attach_tda18212dd(struct ddb_input *input)
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fe = dvb_attach(tda18212dd_attach, dvb->fe, i2c,
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(input->nr & 1) ? 0x63 : 0x60);
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if (!fe) {
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pr_err("DDBridge: No TDA18212 found!\n");
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dev_err(input->port->dev->dev,
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"No TDA18212 found!\n");
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return -ENODEV;
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}
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return 0;
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@ -1169,7 +1172,8 @@ static int tuner_attach_tda18212(struct ddb_input *input)
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cfg = (input->nr & 1) ? &tda18212_1 : &tda18212_0;
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fe = dvb_attach(tda18212_attach, dvb->fe, i2c, cfg);
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if (!fe) {
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pr_err("DDBridge: No TDA18212 found!\n");
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dev_err(input->port->dev->dev,
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"No TDA18212 found!\n");
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return -ENODEV;
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}
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return 0;
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@ -1246,13 +1250,15 @@ static int demod_attach_stv0900(struct ddb_input *input, int type)
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(input->nr & 1) ? STV090x_DEMODULATOR_1
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: STV090x_DEMODULATOR_0);
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if (!dvb->fe) {
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pr_err("DDBridge: No STV0900 found!\n");
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dev_err(input->port->dev->dev,
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"No STV0900 found!\n");
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return -ENODEV;
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}
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if (!dvb_attach(lnbh24_attach, dvb->fe, i2c, 0,
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0, (input->nr & 1) ?
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(0x09 - type) : (0x0b - type))) {
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pr_err("DDBridge: No LNBH24 found!\n");
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dev_err(input->port->dev->dev,
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"No LNBH24 found!\n");
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return -ENODEV;
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}
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return 0;
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@ -1269,11 +1275,13 @@ static int tuner_attach_stv6110(struct ddb_input *input, int type)
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ctl = dvb_attach(stv6110x_attach, dvb->fe, tunerconf, i2c);
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if (!ctl) {
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pr_err("DDBridge: No STV6110X found!\n");
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dev_err(input->port->dev->dev,
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"No STV6110X found!\n");
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return -ENODEV;
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}
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pr_info("DDBridge: attach tuner input %d adr %02x\n",
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input->nr, tunerconf->addr);
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dev_info(input->port->dev->dev,
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"attach tuner input %d adr %02x\n",
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input->nr, tunerconf->addr);
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feconf->tuner_init = ctl->tuner_init;
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feconf->tuner_sleep = ctl->tuner_sleep;
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@ -1314,14 +1322,16 @@ static int demod_attach_stv0910(struct ddb_input *input, int type)
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&cfg, (input->nr & 1));
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}
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if (!dvb->fe) {
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pr_err("DDBridge: No STV0910 found!\n");
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dev_err(input->port->dev->dev,
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"No STV0910 found!\n");
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return -ENODEV;
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}
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if (!dvb_attach(lnbh25_attach, dvb->fe, i2c,
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((input->nr & 1) ? 0x0d : 0x0c))) {
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if (!dvb_attach(lnbh25_attach, dvb->fe, i2c,
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((input->nr & 1) ? 0x09 : 0x08))) {
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pr_err("DDBridge: No LNBH25 found!\n");
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dev_err(input->port->dev->dev,
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"No LNBH25 found!\n");
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return -ENODEV;
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}
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}
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@ -1339,7 +1349,8 @@ static int tuner_attach_stv6111(struct ddb_input *input, int type)
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if (!fe) {
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fe = dvb_attach(stv6111_attach, dvb->fe, i2c, adr & ~4);
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if (!fe) {
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pr_err("DDBridge: No STV6111 found at 0x%02x!\n", adr);
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dev_err(input->port->dev->dev,
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"No STV6111 found at 0x%02x!\n", adr);
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return -ENODEV;
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}
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}
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@ -1351,18 +1362,17 @@ static int lnb_command(struct ddb *dev, u32 link, u32 lnb, u32 cmd)
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u32 c, v = 0, tag = DDB_LINK_TAG(link);
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v = LNB_TONE & (dev->link[link].lnb.tone << (15 - lnb));
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/*pr_info("lnb_control[%u] = %08x\n", lnb, cmd | v);*/
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ddbwritel(dev, cmd | v, tag | LNB_CONTROL(lnb));
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for (c = 0; c < 10; c++) {
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v = ddbreadl(dev, tag | LNB_CONTROL(lnb));
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/*pr_info("ctrl = %08x\n", v);*/
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if ((v & LNB_BUSY) == 0)
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break;
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msleep(20);
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}
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if (c == 10)
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pr_info("DDBridge: lnb_command lnb = %08x cmd = %08x\n",
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lnb, cmd);
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dev_info(dev->dev,
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"lnb_command lnb = %08x cmd = %08x\n",
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lnb, cmd);
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return 0;
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}
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@ -1654,7 +1664,8 @@ static int mxl_fw_read(void *priv, u8 *buf, u32 len)
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struct ddb_link *link = priv;
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struct ddb *dev = link->dev;
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pr_info("DDBridge: Read mxl_fw from link %u\n", link->nr);
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dev_info(dev->dev,
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"Read mxl_fw from link %u\n", link->nr);
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return ddbridge_flashread(dev, link->nr, buf, 0xc0000, len);
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}
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@ -1665,7 +1676,7 @@ static int lnb_init_fmode(struct ddb *dev, struct ddb_link *link, u32 fm)
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if (link->lnb.fmode == fm)
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return 0;
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pr_info("DDBridge: Set fmode link %u = %u\n", l, fm);
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dev_info(dev->dev, "Set fmode link %u = %u\n", l, fm);
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mutex_lock(&link->lnb.lock);
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if (fm == 2 || fm == 1) {
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if (fmode_sat >= 0) {
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@ -1724,7 +1735,7 @@ static int fe_attach_mxl5xx(struct ddb_input *input)
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tuner = 0;
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dvb->fe = dvb_attach(mxl5xx_attach, i2c, &cfg, demod, tuner);
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if (!dvb->fe) {
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pr_err("DDBridge: No MXL5XX found!\n");
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dev_err(dev->dev, "No MXL5XX found!\n");
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return -ENODEV;
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}
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if (input->nr < 4) {
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@ -2091,7 +2102,8 @@ static int port_has_encti(struct ddb_port *port)
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int ret = i2c_read_reg(&port->i2c->adap, 0x20, 0, &val);
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if (!ret)
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pr_info("DDBridge: [0x20]=0x%02x\n", val);
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dev_info(port->dev->dev,
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"[0x20]=0x%02x\n", val);
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return ret ? 0 : 1;
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}
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@ -2187,7 +2199,7 @@ static int init_xo2(struct ddb_port *port)
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return res;
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if (data[0] != 0x01) {
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pr_info("DDBridge: Port %d: invalid XO2\n", port->nr);
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dev_info(dev->dev, "Port %d: invalid XO2\n", port->nr);
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return -1;
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}
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@ -2206,7 +2218,7 @@ static int init_xo2(struct ddb_port *port)
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i2c_write_reg(i2c, 0x10, 0x09, xo2_speed);
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if (dev->link[port->lnr].info->con_clock) {
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pr_info("DDBridge: Setting continuous clock for XO2\n");
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dev_info(dev->dev, "Setting continuous clock for XO2\n");
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i2c_write_reg(i2c, 0x10, 0x0a, 0x03);
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i2c_write_reg(i2c, 0x10, 0x0b, 0x03);
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} else {
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@ -2233,12 +2245,12 @@ static int init_xo2_ci(struct ddb_port *port)
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return res;
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if (data[0] > 1) {
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pr_info("DDBridge: Port %d: invalid XO2 CI %02x\n",
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port->nr, data[0]);
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dev_info(dev->dev, "Port %d: invalid XO2 CI %02x\n",
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port->nr, data[0]);
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return -1;
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}
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pr_info("DDBridge: Port %d: DuoFlex CI %u.%u\n",
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port->nr, data[0], data[1]);
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dev_info(dev->dev, "Port %d: DuoFlex CI %u.%u\n",
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port->nr, data[0], data[1]);
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i2c_read_reg(i2c, 0x10, 0x08, &val);
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if (val != 0) {
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@ -2257,7 +2269,7 @@ static int init_xo2_ci(struct ddb_port *port)
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usleep_range(2000, 3000);
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if (dev->link[port->lnr].info->con_clock) {
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pr_info("DDBridge: Setting continuous clock for DuoFLex CI\n");
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dev_info(dev->dev, "Setting continuous clock for DuoFLex CI\n");
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i2c_write_reg(i2c, 0x10, 0x0a, 0x03);
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i2c_write_reg(i2c, 0x10, 0x0b, 0x03);
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} else {
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@ -2366,13 +2378,13 @@ static void ddb_port_probe(struct ddb_port *port)
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ddbwritel(dev, I2C_SPEED_400,
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port->i2c->regs + I2C_TIMING);
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} else {
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pr_info("DDBridge: Port %d: Uninitialized DuoFlex\n",
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port->nr);
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dev_info(dev->dev, "Port %d: Uninitialized DuoFlex\n",
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port->nr);
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return;
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}
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} else if (port_has_xo2(port, &type, &id)) {
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ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
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pr_info("DDBridge: XO2 ID %02x\n", id);
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dev_info(dev->dev, "XO2 ID %02x\n", id);
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if (type == 2) {
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port->name = "DuoFlex CI";
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port->class = DDB_PORT_CI;
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@ -2674,7 +2686,6 @@ static int slot_reset_xo2(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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pr_info("DDBridge: %s\n", __func__);
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write_creg(ci, 0x01, 0x01);
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write_creg(ci, 0x04, 0x04);
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msleep(20);
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@ -2688,7 +2699,6 @@ static int slot_shutdown_xo2(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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pr_info("DDBridge: %s\n", __func__);
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/*i2c_write_reg(i2c, adr, 0x03, 0x60);*/
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/*i2c_write_reg(i2c, adr, 0x00, 0xc0);*/
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write_creg(ci, 0x10, 0xff);
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@ -2700,7 +2710,6 @@ static int slot_ts_enable_xo2(struct dvb_ca_en50221 *ca, int slot)
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{
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struct ddb_ci *ci = ca->data;
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pr_info("DDBridge: %s\n", __func__);
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write_creg(ci, 0x00, 0x10);
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return 0;
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}
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@ -2830,7 +2839,7 @@ static int ddb_port_attach(struct ddb_port *port)
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break;
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}
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if (ret < 0)
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pr_err("DDBridge: port_attach on port %d failed\n", port->nr);
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dev_err(port->dev->dev, "port_attach on port %d failed\n", port->nr);
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return ret;
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}
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@ -2842,12 +2851,12 @@ static int ddb_ports_attach(struct ddb *dev)
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dev->ns_num = dev->link[0].info->ns_num;
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for (i = 0; i < dev->ns_num; i++)
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dev->ns[i].nr = i;
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pr_info("DDBridge: %d netstream channels\n", dev->ns_num);
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dev_info(dev->dev, "%d netstream channels\n", dev->ns_num);
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if (dev->port_num) {
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ret = dvb_register_adapters(dev);
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if (ret < 0) {
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pr_err("DDBridge: Registering adapters failed. Check DVB_MAX_ADAPTERS in config.\n");
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dev_err(dev->dev, "Registering adapters failed. Check DVB_MAX_ADAPTERS in config.\n");
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return ret;
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}
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}
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@ -2932,16 +2941,16 @@ static void input_write_dvb(struct ddb_input *input,
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while (dma->cbuf != ((dma->stat >> 11) & 0x1f)
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|| (4 & dma->ctrl)) {
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if (4 & dma->ctrl) {
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/*pr_err("DDBridge: Overflow dma %d\n", dma->nr);*/
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/*dev_err(dev->dev, "Overflow dma %d\n", dma->nr);*/
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ack = 1;
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}
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if (alt_dma)
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dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf],
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dma2->size, DMA_FROM_DEVICE);
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#if 0
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pr_info("DDBridge: %02x %02x %02x %02x\n",
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dma2->vbuf[dma->cbuf][0], dma2->vbuf[dma->cbuf][1],
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dma2->vbuf[dma->cbuf][2], dma2->vbuf[dma->cbuf][3]);
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dev_info(dev->dev, "%02x %02x %02x %02x\n",
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dma2->vbuf[dma->cbuf][0], dma2->vbuf[dma->cbuf][1],
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dma2->vbuf[dma->cbuf][2], dma2->vbuf[dma->cbuf][3]);
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#endif
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dvb_dmx_swfilter_packets(&dvb->demux,
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dma2->vbuf[dma->cbuf],
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@ -2979,7 +2988,7 @@ static void input_tasklet(unsigned long data)
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#if 0
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if (4 & dma->ctrl)
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pr_err("DDBridge: Overflow dma %d\n", dma->nr);
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dev_err(dev->dev, "Overflow dma %d\n", dma->nr);
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#endif
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if (input->redi)
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input_write_dvb(input, input->redi);
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@ -3085,8 +3094,8 @@ static void ddb_dma_init(struct ddb_io *io, int nr, int out)
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dma->div = INPUT_DMA_IRQ_DIV;
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}
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ddbwritel(io->port->dev, 0, DMA_BUFFER_ACK(dma));
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pr_info("DDBridge: init link %u, io %u, dma %u, dmaregs %08x bufregs %08x\n",
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io->port->lnr, io->nr, nr, dma->regs, dma->bufregs);
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dev_info(io->port->dev->dev, "init link %u, io %u, dma %u, dmaregs %08x bufregs %08x\n",
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io->port->lnr, io->nr, nr, dma->regs, dma->bufregs);
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}
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static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
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@ -3101,7 +3110,7 @@ static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
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rm = io_regmap(input, 1);
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input->regs = DDB_LINK_TAG(port->lnr) |
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(rm->input->base + rm->input->size * nr);
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pr_info("DDBridge: init link %u, input %u, regs %08x\n",
|
||||
dev_info(dev->dev, "init link %u, input %u, regs %08x\n",
|
||||
port->lnr, nr, input->regs);
|
||||
if (dev->has_dma) {
|
||||
struct ddb_regmap *rm0 = io_regmap(input, 0);
|
||||
@ -3111,7 +3120,7 @@ static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
|
||||
if (port->lnr)
|
||||
dma_nr += 32 + (port->lnr - 1) * 8;
|
||||
|
||||
pr_info("DDBridge: init link %u, input %u, handler %u\n",
|
||||
dev_info(dev->dev, "init link %u, input %u, handler %u\n",
|
||||
port->lnr, nr, dma_nr + base);
|
||||
dev->handler[0][dma_nr + base] = input_handler;
|
||||
dev->handler_data[0][dma_nr + base] = (unsigned long) input;
|
||||
@ -3131,7 +3140,7 @@ static void ddb_output_init(struct ddb_port *port, int nr)
|
||||
rm = io_regmap(output, 1);
|
||||
output->regs = DDB_LINK_TAG(port->lnr) |
|
||||
(rm->output->base + rm->output->size * nr);
|
||||
pr_info("DDBridge: init link %u, output %u, regs %08x\n",
|
||||
dev_info(dev->dev, "init link %u, output %u, regs %08x\n",
|
||||
port->lnr, nr, output->regs);
|
||||
if (dev->has_dma) {
|
||||
struct ddb_regmap *rm0 = io_regmap(output, 0);
|
||||
@ -3210,9 +3219,9 @@ static void ddb_ports_init(struct ddb *dev)
|
||||
port->name = "DuoFlex CI_B";
|
||||
port->i2c = dev->port[p - 1].i2c;
|
||||
}
|
||||
pr_info("DDBridge: Port %u: Link %u, Link Port %u (TAB %u): %s\n",
|
||||
port->pnr, port->lnr, port->nr,
|
||||
port->nr + 1, port->name);
|
||||
dev_info(dev->dev, "Port %u: Link %u, Link Port %u (TAB %u): %s\n",
|
||||
port->pnr, port->lnr, port->nr,
|
||||
port->nr + 1, port->name);
|
||||
|
||||
if (port->class == DDB_PORT_CI &&
|
||||
port->type == DDB_CI_EXTERNAL_XO2) {
|
||||
@ -3507,8 +3516,6 @@ static irqreturn_t irq_thread(int irq, void *dev_id)
|
||||
{
|
||||
/* struct ddb *dev = (struct ddb *) dev_id; */
|
||||
|
||||
/*pr_info("DDBridge: %s\n", __func__);*/
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
#endif
|
||||
@ -3576,7 +3583,7 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
((ts->filter_mask & 3) << 2);
|
||||
|
||||
if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) {
|
||||
pr_info("DDBridge: ts capture busy\n");
|
||||
dev_info(dev->dev, "ts capture busy\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
ddb_dvb_ns_input_start(input);
|
||||
@ -3609,10 +3616,8 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
|
||||
if (ctrl & 1)
|
||||
return -EBUSY;
|
||||
if (ctrl & (1 << 14)) {
|
||||
/*pr_info("DDBridge: ts capture timeout\n");*/
|
||||
if (ctrl & (1 << 14))
|
||||
return -EAGAIN;
|
||||
}
|
||||
ddbcpyfrom(dev, dev->tsbuf, TS_CAPTURE_MEMORY,
|
||||
TS_CAPTURE_LEN);
|
||||
ts->len = ddbreadl(dev, TS_CAPTURE_RECEIVED) & 0x1fff;
|
||||
@ -3624,10 +3629,8 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
{
|
||||
u32 ctrl = 0;
|
||||
|
||||
/*pr_info("DDBridge: cancel ts capture: 0x%x\n", ctrl);*/
|
||||
ddbwritel(dev, ctrl, TS_CAPTURE_CONTROL);
|
||||
ctrl = ddbreadl(dev, TS_CAPTURE_CONTROL);
|
||||
/*pr_info("DDBridge: control register is 0x%x\n", ctrl);*/
|
||||
break;
|
||||
}
|
||||
case NSD_STOP_GET_TS:
|
||||
@ -3639,10 +3642,10 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
if (!input)
|
||||
return -EINVAL;
|
||||
if (ctrl & 1) {
|
||||
pr_info("DDBridge: cannot stop ts capture, while it was neither finished nor canceled\n");
|
||||
dev_info(dev->dev,
|
||||
"cannot stop ts capture, while it was neither finished nor canceled\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
/*pr_info("DDBridge: ts capture stopped\n");*/
|
||||
ddb_dvb_ns_input_stop(input);
|
||||
break;
|
||||
}
|
||||
@ -4451,7 +4454,7 @@ static ssize_t redirect_store(struct device *device,
|
||||
res = ddb_redirect(i, p);
|
||||
if (res < 0)
|
||||
return res;
|
||||
pr_info("DDBridge: redirect: %02x, %02x\n", i, p);
|
||||
dev_info(device, "redirect: %02x, %02x\n", i, p);
|
||||
return count;
|
||||
}
|
||||
|
||||
@ -4476,7 +4479,7 @@ static ssize_t redirect2_store(struct device *device,
|
||||
res = ddb_redirect(i, p);
|
||||
if (res < 0)
|
||||
return res;
|
||||
pr_info("DDBridge: redirect: %02x, %02x\n", i, p);
|
||||
dev_info(device, "redirect: %02x, %02x\n", i, p);
|
||||
return count;
|
||||
}
|
||||
#endif
|
||||
@ -4799,7 +4802,7 @@ static int ddb_device_create(struct ddb *dev)
|
||||
dev, "ddbridge%d", dev->nr);
|
||||
if (IS_ERR(dev->ddb_dev)) {
|
||||
res = PTR_ERR(dev->ddb_dev);
|
||||
pr_info("DDBridge: Could not create ddbridge%d\n", dev->nr);
|
||||
dev_info(dev->dev, "Could not create ddbridge%d\n", dev->nr);
|
||||
goto fail;
|
||||
}
|
||||
res = ddb_device_attrs_add(dev);
|
||||
@ -4833,8 +4836,8 @@ static void gtl_link_handler(unsigned long priv)
|
||||
struct ddb *dev = (struct ddb *) priv;
|
||||
u32 regs = dev->link[0].info->regmap->gtl->base;
|
||||
|
||||
pr_info("DDBridge: GT link change: %u\n",
|
||||
(1 & ddbreadl(dev, regs)));
|
||||
dev_info(dev->dev, "GT link change: %u\n",
|
||||
(1 & ddbreadl(dev, regs)));
|
||||
}
|
||||
|
||||
static void link_tasklet(unsigned long data)
|
||||
@ -4845,7 +4848,7 @@ static void link_tasklet(unsigned long data)
|
||||
u32 l = link->nr;
|
||||
|
||||
s = ddbreadl(dev, tag | INTERRUPT_STATUS);
|
||||
pr_info("DDBridge: gtl_irq %08x = %08x\n", tag | INTERRUPT_STATUS, s);
|
||||
dev_info(dev->dev, "gtl_irq %08x = %08x\n", tag | INTERRUPT_STATUS, s);
|
||||
|
||||
if (!s)
|
||||
return;
|
||||
@ -4866,7 +4869,6 @@ static void gtl_irq_handler(unsigned long priv)
|
||||
|
||||
while ((s = ddbreadl(dev, tag | INTERRUPT_STATUS))) {
|
||||
ddbwritel(dev, s, tag | INTERRUPT_ACK);
|
||||
//pr_info("DDBridge: gtlirq %08x\n", s);
|
||||
LINK_IRQ_HANDLE(l, 0);
|
||||
LINK_IRQ_HANDLE(l, 1);
|
||||
LINK_IRQ_HANDLE(l, 2);
|
||||
@ -4885,7 +4887,7 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
|
||||
(l - 1) * dev->link[0].info->regmap->gtl->size;
|
||||
u32 id, subid, base = dev->link[0].info->regmap->irq_base_gtl;
|
||||
|
||||
pr_info("DDBridge: Checking GT link %u: regs = %08x\n", l, regs);
|
||||
dev_info(dev->dev, "Checking GT link %u: regs = %08x\n", l, regs);
|
||||
|
||||
spin_lock_init(&link->lock);
|
||||
mutex_init(&link->lnb.lock);
|
||||
@ -4916,7 +4918,8 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
|
||||
subid & 0xffff, subid >> 16);
|
||||
if (link->info->type != DDB_OCTOPUS_MAX_CT &&
|
||||
link->info->type != DDB_OCTOPUS_MAX) {
|
||||
pr_info("DDBridge: Detected GT link but found invalid ID %08x. You might have to update (flash) the add-on card first.",
|
||||
dev_info(dev->dev,
|
||||
"Detected GT link but found invalid ID %08x. You might have to update (flash) the add-on card first.",
|
||||
id);
|
||||
return -1;
|
||||
}
|
||||
@ -4934,13 +4937,13 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
|
||||
dev->link[l].ids.subvendor = subid & 0xffff;
|
||||
dev->link[l].ids.subdevice = subid >> 16;
|
||||
|
||||
pr_info("DDBridge: GTL %s\n", dev->link[l].info->name);
|
||||
dev_info(dev->dev, "GTL %s\n", dev->link[l].info->name);
|
||||
|
||||
pr_info("DDBridge: GTL HW %08x REGMAP %08x\n",
|
||||
dev->link[l].ids.hwid,
|
||||
dev->link[l].ids.regmapid);
|
||||
pr_info("DDBridge: GTL ID %08x\n",
|
||||
ddbreadl(dev, DDB_LINK_TAG(l) | 8));
|
||||
dev_info(dev->dev, "GTL HW %08x REGMAP %08x\n",
|
||||
dev->link[l].ids.hwid,
|
||||
dev->link[l].ids.regmapid);
|
||||
dev_info(dev->dev, "GTL ID %08x\n",
|
||||
ddbreadl(dev, DDB_LINK_TAG(l) | 8));
|
||||
|
||||
tasklet_init(&link->tasklet, link_tasklet, (unsigned long) link);
|
||||
ddbwritel(dev, 0xffffffff, DDB_LINK_TAG(l) | INTERRUPT_ACK);
|
||||
@ -4970,7 +4973,7 @@ static void tempmon_setfan(struct ddb_link *link)
|
||||
|
||||
if ((ddblreadl(link, TEMPMON_CONTROL) &
|
||||
TEMPMON_CONTROL_OVERTEMP) != 0) {
|
||||
pr_info("DDBridge: Over temperature condition\n");
|
||||
dev_info(link->dev->dev, "Over temperature condition\n");
|
||||
link->OverTemperatureError = 1;
|
||||
}
|
||||
temp = (ddblreadl(link, TEMPMON_SENSOR0) >> 8) & 0xFF;
|
||||
@ -5031,7 +5034,7 @@ static int tempmon_init(struct ddb_link *link, int FirstTime)
|
||||
((ddblreadl(link, TEMPMON_CONTROL) &
|
||||
TEMPMON_CONTROL_OVERTEMP) != 0);
|
||||
if (link->OverTemperatureError) {
|
||||
pr_info("DDBridge: Over temperature condition\n");
|
||||
dev_info(dev->dev, "Over temperature condition\n");
|
||||
status = -1;
|
||||
}
|
||||
tempmon_setfan(link);
|
||||
@ -5068,10 +5071,11 @@ static int ddb_init_boards(struct ddb *dev)
|
||||
info = link->info;
|
||||
if (!info)
|
||||
continue;
|
||||
pr_info("DDBridge: link %u vendor %04x device %04x subvendor %04x subdevice %04x\n",
|
||||
l,
|
||||
dev->link[l].ids.vendor, dev->link[l].ids.device,
|
||||
dev->link[l].ids.subvendor, dev->link[l].ids.subdevice);
|
||||
dev_info(dev->dev,
|
||||
"link %u vendor %04x device %04x subvendor %04x subdevice %04x\n",
|
||||
l,
|
||||
dev->link[l].ids.vendor, dev->link[l].ids.device,
|
||||
dev->link[l].ids.subvendor, dev->link[l].ids.subdevice);
|
||||
|
||||
if (info->board_control) {
|
||||
ddbwritel(dev, 0, DDB_LINK_TAG(l) | BOARD_CONTROL);
|
||||
@ -5112,7 +5116,8 @@ int ddb_init(struct ddb *dev)
|
||||
goto fail;
|
||||
ddb_ports_init(dev);
|
||||
if (ddb_buffers_alloc(dev) < 0) {
|
||||
pr_info("DDBridge: Could not allocate buffer memory\n");
|
||||
dev_info(dev->dev,
|
||||
"Could not allocate buffer memory\n");
|
||||
goto fail2;
|
||||
}
|
||||
if (ddb_ports_attach(dev) < 0)
|
||||
@ -5131,14 +5136,14 @@ int ddb_init(struct ddb *dev)
|
||||
|
||||
fail3:
|
||||
ddb_ports_detach(dev);
|
||||
pr_err("DDBridge: fail3\n");
|
||||
dev_err(dev->dev, "fail3\n");
|
||||
ddb_ports_release(dev);
|
||||
fail2:
|
||||
pr_err("DDBridge: fail2\n");
|
||||
dev_err(dev->dev, "fail2\n");
|
||||
ddb_buffers_free(dev);
|
||||
ddb_i2c_release(dev);
|
||||
fail:
|
||||
pr_err("DDBridge: fail1\n");
|
||||
dev_err(dev->dev, "fail1\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
@ -36,8 +36,8 @@ static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
|
||||
stat = wait_for_completion_timeout(&i2c->completion, HZ);
|
||||
val = ddbreadl(dev, i2c->regs + I2C_COMMAND);
|
||||
if (stat == 0) {
|
||||
pr_err("DDBridge: I2C timeout, card %d, port %d, link %u\n",
|
||||
dev->nr, i2c->nr, i2c->link);
|
||||
dev_err(dev->dev, "I2C timeout, card %d, port %d, link %u\n",
|
||||
dev->nr, i2c->nr, i2c->link);
|
||||
#if 1
|
||||
{
|
||||
u32 istat = ddbreadl(dev, INTERRUPT_STATUS);
|
||||
|
||||
@ -107,22 +107,22 @@ static int __devinit ddb_irq_msi(struct ddb *dev, int nr)
|
||||
#endif
|
||||
if (stat >= 1) {
|
||||
dev->msi = stat;
|
||||
pr_info("DDBridge: using %d MSI interrupt(s)\n",
|
||||
dev->msi);
|
||||
dev_info(dev->dev, "using %d MSI interrupt(s)\n",
|
||||
dev->msi);
|
||||
} else
|
||||
pr_info("DDBridge: MSI not available.\n");
|
||||
dev_info(dev->dev, "MSI not available.\n");
|
||||
|
||||
#else
|
||||
stat = pci_enable_msi_block(dev->pdev, nr);
|
||||
if (stat == 0) {
|
||||
dev->msi = nr;
|
||||
pr_info("DDBridge: using %d MSI interrupts\n", nr);
|
||||
dev_info(dev->dev, "using %d MSI interrupts\n", nr);
|
||||
} else if (stat == 1) {
|
||||
stat = pci_enable_msi(dev->pdev);
|
||||
dev->msi = 1;
|
||||
}
|
||||
if (stat < 0)
|
||||
pr_info("DDBridge: MSI not available.\n");
|
||||
dev_info(dev->dev, "MSI not available.\n");
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
@ -134,7 +134,7 @@ static int __devinit ddb_irq_init2(struct ddb *dev)
|
||||
int stat;
|
||||
int irq_flag = IRQF_SHARED;
|
||||
|
||||
pr_info("DDBridge: init type 2 IRQ hardware block\n");
|
||||
dev_info(dev->dev, "init type 2 IRQ hardware block\n");
|
||||
|
||||
ddbwritel(dev, 0x00000000, INTERRUPT_V2_CONTROL);
|
||||
ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_1);
|
||||
@ -254,19 +254,19 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
|
||||
dev->link[0].dev = dev;
|
||||
dev->link[0].info = get_ddb_info(id->vendor, id->device,
|
||||
id->subvendor, pdev->subsystem_device);
|
||||
pr_info("DDBridge: device name: %s\n", dev->link[0].info->name);
|
||||
dev_info(dev->dev, "device name: %s\n", dev->link[0].info->name);
|
||||
|
||||
dev->regs_len = pci_resource_len(dev->pdev, 0);
|
||||
dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
|
||||
pci_resource_len(dev->pdev, 0));
|
||||
|
||||
if (!dev->regs) {
|
||||
pr_err("DDBridge: not enough memory for register map\n");
|
||||
dev_err(dev->dev, "not enough memory for register map\n");
|
||||
stat = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
if (ddbreadl(dev, 0) == 0xffffffff) {
|
||||
pr_err("DDBridge: cannot read registers\n");
|
||||
dev_err(dev->dev, "cannot read registers\n");
|
||||
stat = -ENODEV;
|
||||
goto fail;
|
||||
}
|
||||
@ -274,8 +274,8 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
|
||||
dev->link[0].ids.hwid = ddbreadl(dev, 0);
|
||||
dev->link[0].ids.regmapid = ddbreadl(dev, 4);
|
||||
|
||||
pr_info("DDBridge: HW %08x REGMAP %08x\n",
|
||||
dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
|
||||
dev_info(dev->dev, "HW %08x REGMAP %08x\n",
|
||||
dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
|
||||
|
||||
if (dev->link[0].info->ns_num) {
|
||||
ddbwritel(dev, 0, ETHER_CONTROL);
|
||||
@ -300,11 +300,11 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
|
||||
|
||||
ddb_irq_exit(dev);
|
||||
fail0:
|
||||
pr_err("DDBridge: fail0\n");
|
||||
dev_err(dev->dev, "fail0\n");
|
||||
if (dev->msi)
|
||||
pci_disable_msi(dev->pdev);
|
||||
fail:
|
||||
pr_err("DDBridge: fail\n");
|
||||
dev_err(dev->dev, "fail\n");
|
||||
|
||||
ddb_unmap(dev);
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
@ -353,7 +353,7 @@ static __init int module_init_ddbridge(void)
|
||||
{
|
||||
int stat = -1;
|
||||
|
||||
pr_info("DDBridge: Digital Devices PCIE bridge driver "
|
||||
pr_info("Digital Devices PCIE bridge driver "
|
||||
DDBRIDGE_VERSION
|
||||
", Copyright (C) 2010-17 Digital Devices GmbH\n");
|
||||
if (ddb_class_create() < 0)
|
||||
|
||||
@ -188,7 +188,7 @@ void ddbridge_mod_output_stop(struct ddb_output *output)
|
||||
ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
|
||||
#endif
|
||||
mod_busy(dev, output->nr);
|
||||
pr_info("DDBridge: mod_output_stop %d.%d\n", dev->nr, output->nr);
|
||||
dev_info(dev->dev, "mod_output_stop %d.%d\n", dev->nr, output->nr);
|
||||
}
|
||||
|
||||
static void mod_set_incs(struct ddb_output *output)
|
||||
@ -223,8 +223,10 @@ static void mod_calc_rateinc(struct ddb_mod *mod)
|
||||
{
|
||||
u32 ri;
|
||||
|
||||
pr_info("DDBridge: ibitrate %llu\n", mod->ibitrate);
|
||||
pr_info("DDBridge: obitrate %llu\n", mod->obitrate);
|
||||
dev_info(mod->port->dev->dev,
|
||||
"ibitrate %llu\n", mod->ibitrate);
|
||||
dev_info(mod->port->dev->dev,
|
||||
"obitrate %llu\n", mod->obitrate);
|
||||
|
||||
if (mod->ibitrate != 0) {
|
||||
u64 d = mod->obitrate - mod->ibitrate;
|
||||
@ -237,8 +239,9 @@ static void mod_calc_rateinc(struct ddb_mod *mod)
|
||||
} else
|
||||
ri = 0;
|
||||
mod->rate_inc = ri;
|
||||
pr_info("DDBridge: ibr=%llu, obr=%llu, ri=0x%06x\n",
|
||||
mod->ibitrate >> 32, mod->obitrate >> 32, ri);
|
||||
dev_info(mod->port->dev->dev,
|
||||
"ibr=%llu, obr=%llu, ri=0x%06x\n",
|
||||
mod->ibitrate >> 32, mod->obitrate >> 32, ri);
|
||||
}
|
||||
|
||||
static int mod_calc_obitrate(struct ddb_mod *mod)
|
||||
@ -369,8 +372,8 @@ int ddbridge_mod_output_start(struct ddb_output *output)
|
||||
if (checkLF <= 1)
|
||||
return -EINVAL;
|
||||
|
||||
pr_info("DDBridge: KF=%u LF=%u Output=%u mod=%u\n",
|
||||
KF, LF, Output, mod->modulation);
|
||||
dev_info(dev->dev, "KF=%u LF=%u Output=%u mod=%u\n",
|
||||
KF, LF, Output, mod->modulation);
|
||||
ddbwritel(dev, KF, CHANNEL_KF(Channel));
|
||||
ddbwritel(dev, LF, CHANNEL_LF(Channel));
|
||||
|
||||
@ -400,8 +403,8 @@ int ddbridge_mod_output_start(struct ddb_output *output)
|
||||
if (mod_SendChannelCommand(dev, Channel,
|
||||
CHANNEL_CONTROL_CMD_UNMUTE))
|
||||
return -EINVAL;
|
||||
pr_info("DDBridge: mod_output_start %d.%d ctrl=%08x\n",
|
||||
dev->nr, output->nr, mod->Control);
|
||||
dev_info(dev->dev, "mod_output_start %d.%d ctrl=%08x\n",
|
||||
dev->nr, output->nr, mod->Control);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -500,7 +503,7 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan,
|
||||
if (MaxUsedChannels == 0)
|
||||
MaxUsedChannels = (Capacity & FSM_CAPACITY_CUR) >> 16;
|
||||
|
||||
pr_info("DDBridge: max used chan = %u\n", MaxUsedChannels);
|
||||
dev_info(dev->dev, "max used chan = %u\n", MaxUsedChannels);
|
||||
if (MaxUsedChannels <= 1)
|
||||
ddbwritel(dev, FSM_GAIN_N1, FSM_GAIN);
|
||||
else if (MaxUsedChannels <= 2)
|
||||
@ -680,8 +683,8 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
|
||||
mod_si598_readreg(dev, 11, &Data[4]);
|
||||
mod_si598_readreg(dev, 12, &Data[5]);
|
||||
|
||||
pr_info("DDBridge: Data = %02x %02x %02x %02x %02x %02x\n",
|
||||
Data[0], Data[1], Data[2], Data[3], Data[4], Data[5]);
|
||||
dev_info(dev->dev, "Data = %02x %02x %02x %02x %02x %02x\n",
|
||||
Data[0], Data[1], Data[2], Data[3], Data[4], Data[5]);
|
||||
RFreq = (((u64)Data[1] & 0x3F) << 32) | ((u64)Data[2] << 24) |
|
||||
((u64)Data[3] << 16) | ((u64)Data[4] << 8) |
|
||||
((u64)Data[5]);
|
||||
@ -694,14 +697,14 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
|
||||
((u32)(Data[1] & 0xE0) >> 6)) + 1;
|
||||
fDCO = fOut * (u64)(HSDiv * N);
|
||||
m_fXtal = fDCO << 28;
|
||||
pr_info("DDBridge: fxtal %016llx rfreq %016llx\n",
|
||||
m_fXtal, RFreq);
|
||||
dev_info(dev->dev, "fxtal %016llx rfreq %016llx\n",
|
||||
m_fXtal, RFreq);
|
||||
|
||||
m_fXtal += RFreq >> 1;
|
||||
m_fXtal = div64_u64(m_fXtal, RFreq);
|
||||
|
||||
pr_info("DDBridge: fOut = %d fXtal = %d fDCO = %d HDIV = %2d, N = %3d\n",
|
||||
(u32) fOut, (u32) m_fXtal, (u32) fDCO, (u32) HSDiv, N);
|
||||
dev_info(dev->dev, "fOut = %d fXtal = %d fDCO = %d HDIV = %2d, N = %3d\n",
|
||||
(u32) fOut, (u32) m_fXtal, (u32) fDCO, (u32) HSDiv, N);
|
||||
}
|
||||
|
||||
fOut = freq;
|
||||
@ -711,8 +714,8 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
|
||||
|
||||
if (Div < MinDiv)
|
||||
Div = Div + 1;
|
||||
pr_info("DDBridge: fOut = %u MinDiv = %llu MaxDiv = %llu StartDiv = %llu\n",
|
||||
fOut, MinDiv, MaxDiv, Div);
|
||||
dev_info(dev->dev, "fOut = %u MinDiv = %llu MaxDiv = %llu StartDiv = %llu\n",
|
||||
fOut, MinDiv, MaxDiv, Div);
|
||||
|
||||
if (Div <= 11) {
|
||||
N = 1;
|
||||
@ -730,8 +733,8 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
|
||||
if (N > 128)
|
||||
break;
|
||||
}
|
||||
pr_info("DDBridge: %3d: %llu %llu %llu %u\n",
|
||||
retry, Div, HSDiv * N, HSDiv, N);
|
||||
dev_info(dev->dev, "%3d: %llu %llu %llu %u\n",
|
||||
retry, Div, HSDiv * N, HSDiv, N);
|
||||
if (HSDiv * N < MinDiv)
|
||||
Div = Div + 2;
|
||||
else if (HSDiv * N > MaxDiv)
|
||||
@ -741,7 +744,7 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
|
||||
retry = retry - 1;
|
||||
}
|
||||
if (retry == 0) {
|
||||
pr_err("DDBridge: FAIL\n");
|
||||
dev_err(dev->dev, "FAIL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
@ -756,17 +759,17 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
|
||||
|
||||
|
||||
fDCO = (u64)fOut * (u64)N * (u64)HSDiv;
|
||||
pr_info("DDBridge: fdco %16llx\n", fDCO);
|
||||
dev_info(dev->dev, "fdco %16llx\n", fDCO);
|
||||
RFreq = fDCO<<28;
|
||||
pr_info("DDBridge: %16llx %16llx\n", fDCO, RFreq);
|
||||
dev_info(dev->dev, "%16llx %16llx\n", fDCO, RFreq);
|
||||
|
||||
fxtal = m_fXtal;
|
||||
do_div(RFreq, fxtal);
|
||||
pr_info("DDBridge: %16llx %d\n", RFreq, fxtal);
|
||||
dev_info(dev->dev, "%16llx %d\n", RFreq, fxtal);
|
||||
RF = RFreq;
|
||||
|
||||
pr_info("DDBridge: fOut = %u fXtal = %llu fDCO = %llu HSDIV = %llu, N = %u, RFreq = %llu\n",
|
||||
fOut, m_fXtal, fDCO, HSDiv, N, RFreq);
|
||||
dev_info(dev->dev, "fOut = %u fXtal = %llu fDCO = %llu HSDIV = %llu, N = %u, RFreq = %llu\n",
|
||||
fOut, m_fXtal, fDCO, HSDiv, N, RFreq);
|
||||
|
||||
Data[0] = (u8)(((HSDiv - 4) << 5) | ((N - 1) >> 2));
|
||||
Data[1] = (u8)((((N - 1) & 0x03) << 6) | ((RF >> 32) & 0x3F));
|
||||
@ -775,8 +778,8 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
|
||||
Data[4] = (u8)((RF >> 8) & 0xFF);
|
||||
Data[5] = (u8)((RF) & 0xFF);
|
||||
|
||||
pr_info("DDBridge: Data = %02x %02x %02x %02x %02x %02x\n",
|
||||
Data[0], Data[1], Data[2], Data[3], Data[4], Data[5]);
|
||||
dev_info(dev->dev, "Data = %02x %02x %02x %02x %02x %02x\n",
|
||||
Data[0], Data[1], Data[2], Data[3], Data[4], Data[5]);
|
||||
mod_si598_writereg(dev, 7, Data[0]);
|
||||
mod_si598_writereg(dev, 8, Data[1]);
|
||||
mod_si598_writereg(dev, 9, Data[2]);
|
||||
@ -909,11 +912,11 @@ static int mod_init_dac_input(struct ddb *dev)
|
||||
}
|
||||
|
||||
if (Sample1 == 0xFF || Sample2 == 0xFF) {
|
||||
pr_err("DDBridge: No valid window found\n");
|
||||
dev_err(dev->dev, "No valid window found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pr_err("DDBridge: Window = %d - %d\n", Sample1, Sample2);
|
||||
dev_err(dev->dev, "Window = %d - %d\n", Sample1, Sample2);
|
||||
|
||||
for (Sample = Sample1; Sample < Sample2; Sample += 1) {
|
||||
if (SetTable[Sample] < HldTable[Sample]) {
|
||||
@ -924,15 +927,15 @@ static int mod_init_dac_input(struct ddb *dev)
|
||||
}
|
||||
}
|
||||
|
||||
pr_info("DDBridge: Select Sample %d\n", SelectSample);
|
||||
dev_info(dev->dev, "Select Sample %d\n", SelectSample);
|
||||
|
||||
if (SelectSample == 0xFF) {
|
||||
pr_err("DDBridge: No valid sample found\n");
|
||||
dev_err(dev->dev, "No valid sample found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (HldTable[SelectSample] + SetTable[SelectSample] < 8) {
|
||||
pr_err("DDBridge: Too high jitter\n");
|
||||
dev_err(dev->dev, "Too high jitter\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -947,10 +950,10 @@ static int mod_init_dac_input(struct ddb *dev)
|
||||
mod_read_dac_register(dev, 0x06, &ReadSeek);
|
||||
Seek &= ReadSeek;
|
||||
if ((Seek & 0x01) == 0) {
|
||||
pr_err("DDBridge: Insufficient timing margin\n");
|
||||
dev_err(dev->dev, "Insufficient timing margin\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
pr_info("DDBridge: Done\n");
|
||||
dev_info(dev->dev, "Done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1007,7 +1010,7 @@ static int mod_set_dac_clock(struct ddb *dev, u32 Frequency)
|
||||
ddbwritel(dev, DAC_CONTROL_RESET, DAC_CONTROL);
|
||||
msleep(20);
|
||||
if (mod_set_si598(dev, Frequency)) {
|
||||
pr_err("DDBridge: mod_set_si598 failed\n");
|
||||
dev_err(dev->dev, "mod_set_si598 failed\n");
|
||||
return -1;
|
||||
}
|
||||
msleep(50);
|
||||
@ -1022,7 +1025,7 @@ static int mod_set_dac_clock(struct ddb *dev, u32 Frequency)
|
||||
break;
|
||||
msleep(100);
|
||||
}
|
||||
pr_info("DDBridge: mod_set_dac_clock OK\n");
|
||||
dev_info(dev->dev, "mod_set_dac_clock OK\n");
|
||||
return hr;
|
||||
}
|
||||
|
||||
@ -1128,18 +1131,18 @@ static int set_base_frequency(struct ddb *dev, u32 freq)
|
||||
u32 UP2Frequency = 1896;
|
||||
u32 down, freq10;
|
||||
|
||||
pr_info("DDBridge: set base to %u\n", freq);
|
||||
dev_info(dev->dev, "set base to %u\n", freq);
|
||||
dev->mod_base.frequency = freq;
|
||||
freq /= 1000000;
|
||||
freq10 = dev->mod_base.flat_start + 4;
|
||||
down = freq + 9 * 8 + freq10 + UP1Frequency + UP2Frequency;
|
||||
|
||||
if ((freq10 + 9 * 8) > (dev->mod_base.flat_end - 4)) {
|
||||
pr_err("DDBridge: Frequency out of range %d\n", freq10);
|
||||
dev_err(dev->dev, "Frequency out of range %d\n", freq10);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (down % 8) {
|
||||
pr_err("DDBridge: Invalid Frequency %d\n", down);
|
||||
dev_err(dev->dev, "Invalid Frequency %d\n", down);
|
||||
return -EINVAL;
|
||||
}
|
||||
return mod_set_down(dev, down, 8, Ext);
|
||||
@ -1168,12 +1171,12 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)
|
||||
stat = -EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
pr_info("DDBridge: srate = %d\n", flash->DataSet[0].Symbolrate * 1000);
|
||||
dev_info(dev->dev, "srate = %d\n", flash->DataSet[0].Symbolrate * 1000);
|
||||
|
||||
mod_output_enable(dev, 0);
|
||||
stat = mod_set_dac_clock(dev, flash->DataSet[0].DACFrequency * 1000);
|
||||
if (stat < 0) {
|
||||
pr_err("DDBridge: setting DAC clock failed\n");
|
||||
dev_err(dev->dev, "setting DAC clock failed\n");
|
||||
goto fail;
|
||||
}
|
||||
mod_set_dac_current(dev, 512, 512);
|
||||
@ -1190,17 +1193,17 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)
|
||||
FrequencyCH10 = flash->DataSet[0].FlatStart + 4;
|
||||
DownFrequency = Frequency + 9 * 8 + FrequencyCH10 +
|
||||
UP1Frequency + UP2Frequency;
|
||||
pr_info("DDBridge: CH10 = %d, Down = %d\n",
|
||||
FrequencyCH10, DownFrequency);
|
||||
dev_info(dev->dev, "CH10 = %d, Down = %d\n",
|
||||
FrequencyCH10, DownFrequency);
|
||||
|
||||
if ((FrequencyCH10 + 9 * 8) > (flash->DataSet[0].FlatEnd - 4)) {
|
||||
pr_err("DDBridge: Frequency out of range %d\n", FrequencyCH10);
|
||||
dev_err(dev->dev, "Frequency out of range %d\n", FrequencyCH10);
|
||||
stat = -EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (DownFrequency % 8 != 0) {
|
||||
pr_err("DDBridge: Invalid Frequency %d\n", DownFrequency);
|
||||
dev_err(dev->dev, "Invalid Frequency %d\n", DownFrequency);
|
||||
stat = -EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
@ -1229,7 +1232,7 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)
|
||||
flash->DataSet[0].PostScaleQ);
|
||||
mod_pre_eq_gain(dev, flash->DataSet[0].PreScale);
|
||||
/*mod_pre_eq_gain(dev, 0x0680);*/
|
||||
pr_info("DDBridge: prescaler %04x\n", flash->DataSet[0].PreScale);
|
||||
dev_info(dev->dev, "prescaler %04x\n", flash->DataSet[0].PreScale);
|
||||
mod_set_channelsumshift(dev, 2);
|
||||
mod_output_enable(dev, 1);
|
||||
|
||||
@ -1353,8 +1356,8 @@ void ddbridge_mod_rate_handler(unsigned long data)
|
||||
|
||||
case CM_ADJUST:
|
||||
if (InPacketDiff < mod->MinInputPackets) {
|
||||
pr_info("DDBridge: PCR Adjust reset IN: %u Min: %u\n",
|
||||
InPacketDiff, mod->MinInputPackets);
|
||||
dev_info(dev->dev, "PCR Adjust reset IN: %u Min: %u\n",
|
||||
InPacketDiff, mod->MinInputPackets);
|
||||
mod->InPacketsSum = 0;
|
||||
mod->OutPacketsSum = 0;
|
||||
mod->PCRAdjustSum = 0;
|
||||
@ -1394,7 +1397,7 @@ void ddbridge_mod_rate_handler(unsigned long data)
|
||||
|
||||
mod->PCRIncrement += PCRIncrementDiff;
|
||||
pcr = ConvertPCR(mod->PCRIncrement);
|
||||
pr_info("DDBridge: outl %016llx\n", pcr);
|
||||
dev_info(dev->dev, "outl %016llx\n", pcr);
|
||||
ddbwritel(dev, pcr & 0xffffffff,
|
||||
CHANNEL_PCR_ADJUST_OUTL(output->nr));
|
||||
ddbwritel(dev, (pcr >> 32) & 0xffffffff,
|
||||
@ -1421,11 +1424,11 @@ void ddbridge_mod_rate_handler(unsigned long data)
|
||||
|
||||
spin_unlock(&dma->lock);
|
||||
|
||||
pr_info("DDBridge: chan %d out %016llx in %016llx indiff %08x\n",
|
||||
chan, OutPackets, InPackets, InPacketDiff);
|
||||
pr_info("DDBridge: cnt %d pcra %016llx pcraext %08x pcraextfrac %08x pcrcorr %08x pcri %016llx\n",
|
||||
mod->StateCounter, PCRAdjust, PCRAdjustExt,
|
||||
PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement);
|
||||
dev_info(dev->dev, "chan %d out %016llx in %016llx indiff %08x\n",
|
||||
chan, OutPackets, InPackets, InPacketDiff);
|
||||
dev_info(dev->dev, "cnt %d pcra %016llx pcraext %08x pcraextfrac %08x pcrcorr %08x pcri %016llx\n",
|
||||
mod->StateCounter, PCRAdjust, PCRAdjustExt,
|
||||
PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement);
|
||||
}
|
||||
|
||||
static int mod3_set_base_frequency(struct ddb *dev, u32 frequency)
|
||||
@ -1440,7 +1443,7 @@ static int mod3_set_base_frequency(struct ddb *dev, u32 frequency)
|
||||
tmp = frequency;
|
||||
tmp <<= 33;
|
||||
tmp = div64_s64(tmp, 4915200000);
|
||||
pr_info("set base frequency = %u regs = 0x%08llx\n", frequency, tmp);
|
||||
dev_info(dev->dev, "set base frequency = %u regs = 0x%08llx\n", frequency, tmp);
|
||||
ddbwritel(dev, (u32) tmp, RFDAC_FCW);
|
||||
return 0;
|
||||
}
|
||||
@ -1456,7 +1459,7 @@ static void mod3_set_cfcw(struct ddb_mod *mod, u32 f)
|
||||
tmp = ((s64) (freq - dcf)) << 32;
|
||||
tmp = div64_s64(tmp, srdac);
|
||||
cfcw = (u32) tmp;
|
||||
pr_info("f=%u cfcw = %08x nr = %u\n", f, cfcw, mod->port->nr);
|
||||
dev_info(dev->dev, "f=%u cfcw = %08x nr = %u\n", f, cfcw, mod->port->nr);
|
||||
ddbwritel(dev, cfcw, SDR_CHANNEL_CFCW(mod->port->nr));
|
||||
}
|
||||
|
||||
@ -1634,7 +1637,7 @@ static int mod_init_2(struct ddb *dev, u32 Frequency)
|
||||
status = mod_fsm_setup(dev, 0, 0);
|
||||
|
||||
if (status) {
|
||||
pr_err("FSM setup failed!\n");
|
||||
dev_err(dev->dev, "FSM setup failed!\n");
|
||||
return -1;
|
||||
}
|
||||
for (i = 0; i < streams; i++) {
|
||||
@ -1709,7 +1712,7 @@ static int rfdac_init(struct ddb *dev)
|
||||
}
|
||||
if (tmp & 0x80)
|
||||
return -1;
|
||||
pr_info("sync %d:%08x\n", i, tmp);
|
||||
dev_info(dev->dev, "sync %d:%08x\n", i, tmp);
|
||||
ddbwritel(dev, RFDAC_CMD_RESET, RFDAC_CONTROL);
|
||||
for (i = 0; i < 10; i++) {
|
||||
msleep(20);
|
||||
@ -1719,7 +1722,7 @@ static int rfdac_init(struct ddb *dev)
|
||||
}
|
||||
if (tmp & 0x80)
|
||||
return -1;
|
||||
pr_info("sync %d:%08x\n", i, tmp);
|
||||
dev_info(dev->dev, "sync %d:%08x\n", i, tmp);
|
||||
ddbwritel(dev, RFDAC_CMD_SETUP, RFDAC_CONTROL);
|
||||
for (i = 0; i < 10; i++) {
|
||||
msleep(20);
|
||||
@ -1729,7 +1732,7 @@ static int rfdac_init(struct ddb *dev)
|
||||
}
|
||||
if (tmp & 0x80)
|
||||
return -1;
|
||||
pr_info("sync %d:%08x\n", i, tmp);
|
||||
dev_info(dev->dev, "sync %d:%08x\n", i, tmp);
|
||||
ddbwritel(dev, 0x01, JESD204B_BASE);
|
||||
for (i = 0; i < 400; i++) {
|
||||
msleep(20);
|
||||
@ -1737,7 +1740,7 @@ static int rfdac_init(struct ddb *dev)
|
||||
if ((tmp & 0xc0000000) == 0xc0000000)
|
||||
break;
|
||||
}
|
||||
pr_info("sync %d:%08x\n", i, tmp);
|
||||
dev_info(dev->dev, "sync %d:%08x\n", i, tmp);
|
||||
if ((tmp & 0xc0000000) != 0xc0000000)
|
||||
return -1;
|
||||
return 0;
|
||||
@ -1750,12 +1753,12 @@ static int mod_init_3(struct ddb *dev, u32 Frequency)
|
||||
|
||||
ret = mod_setup_max2871(dev, max2871_sdr);
|
||||
if (ret)
|
||||
pr_err("DDBridge: PLL setup failed\n");
|
||||
dev_err(dev->dev, "PLL setup failed\n");
|
||||
ret = rfdac_init(dev);
|
||||
if (ret)
|
||||
ret = rfdac_init(dev);
|
||||
if (ret)
|
||||
pr_err("DDBridge: RFDAC setup failed\n");
|
||||
dev_err(dev->dev, "RFDAC setup failed\n");
|
||||
|
||||
for (i = 0; i < streams; i++) {
|
||||
struct ddb_mod *mod = &dev->mod[i];
|
||||
|
||||
@ -197,8 +197,8 @@ static int ns_set_ci(struct dvbnss *nss, u8 ci)
|
||||
if (ciport < 0)
|
||||
return -EINVAL;
|
||||
|
||||
pr_info("DDBridge: input %d.%d to ci %d at port %d\n",
|
||||
input->port->lnr, input->nr, ci, ciport);
|
||||
dev_info(dev->dev, "DDBridge: input %d.%d to ci %d at port %d\n",
|
||||
input->port->lnr, input->nr, ci, ciport);
|
||||
ddbwritel(dev, (input->port->lnr << 21) | (input->nr << 16) | 0x1c,
|
||||
TS_CONTROL(dev->port[ciport].output));
|
||||
usleep_range(1, 5);
|
||||
|
||||
@ -100,10 +100,10 @@ static int __init octonet_probe(struct platform_device *pdev)
|
||||
dev->link[0].ids.device,
|
||||
0xdd01, 0xffff);
|
||||
#endif
|
||||
pr_info("DDBridge: HW %08x REGMAP %08x\n",
|
||||
dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
|
||||
pr_info("DDBridge: MAC %08x DEVID %08x\n",
|
||||
dev->link[0].ids.mac, dev->link[0].ids.devid);
|
||||
dev_info(dev->dev, "DDBridge: HW %08x REGMAP %08x\n",
|
||||
dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
|
||||
dev_info(dev->dev, "DDBridge: MAC %08x DEVID %08x\n",
|
||||
dev->link[0].ids.mac, dev->link[0].ids.devid);
|
||||
|
||||
ddbwritel(dev, 0, ETHER_CONTROL);
|
||||
ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user