diff --git a/ddbridge/ddbridge-core.c b/ddbridge/ddbridge-core.c index 071ab7d..50200da 100644 --- a/ddbridge/ddbridge-core.c +++ b/ddbridge/ddbridge-core.c @@ -122,6 +122,12 @@ static struct ddb_regset octopus_mod_2_channel = { .size = 0x40, }; +static struct ddb_regset octopus_sdr_output = { + .base = 0x240, + .num = 0x14, + .size = 0x10, +}; + /****************************************************************************/ static struct ddb_regset octopus_input = { @@ -303,7 +309,7 @@ static struct ddb_regmap octopus_sdr_map = { .irq_version = 2, .irq_base_odma = 64, .irq_base_rate = 32, - .output = &octopus_output, + .output = &octopus_sdr_output, .odma = &octopus_mod_2_odma, .odma_buf = &octopus_mod_2_odma_buf, .channel = &octopus_mod_2_channel, @@ -734,6 +740,7 @@ static void ddb_output_start(struct ddb_output *output) struct ddb *dev = output->port->dev; u32 con = 0x11c, con2 = 0; + printk("Channel Base = %08x\n", output->regs); if (output->dma) { spin_lock_irq(&output->dma->lock); output->dma->cbuf = 0; @@ -4468,8 +4475,8 @@ static ssize_t temp_show(struct device *device, int i; u8 tmp[2]; - if (dev->link[0].info->type == DDB_MOD) { - if (dev->link[0].info->version >= 2) { + if (link->info->type == DDB_MOD) { + if (link->info->version >= 2) { temp = 0xffff & ddbreadl(dev, TEMPMON2_BOARD); temp = (temp * 1000) >> 8; @@ -4498,14 +4505,14 @@ static ssize_t temp_show(struct device *device, } return sprintf(buf, "%d %d\n", temp, temp2); } - if (!dev->link[0].info->temp_num) + if (!link->info->temp_num) return sprintf(buf, "no sensor\n"); - adap = &dev->i2c[dev->link[0].info->temp_bus].adap; + adap = &dev->i2c[link->info->temp_bus].adap; if (i2c_read_regs(adap, 0x48, 0, tmp, 2) < 0) return sprintf(buf, "read_error\n"); temp = (tmp[0] << 3) | (tmp[1] >> 5); temp *= 125; - if (dev->link[0].info->temp_num == 2) { + if (link->info->temp_num == 2) { if (i2c_read_regs(adap, 0x49, 0, tmp, 2) < 0) return sprintf(buf, "read_error\n"); temp2 = (tmp[0] << 3) | (tmp[1] >> 5); @@ -5298,17 +5305,16 @@ static int tempmon_init(struct ddb_link *link, int FirstTime) static int ddb_init_tempmon(struct ddb_link *link) { - struct ddb *dev = link->dev; struct ddb_info *info = link->info; if (!info->tempmon_irq) - return; + return 0; if (info->type == DDB_OCTOPUS_MAX || info->type == DDB_OCTOPUS_MAX_CT) if (link->ids.regmapid < 0x00010002) - return; + return 0; spin_lock_init(&link->temp_lock); - tempmon_init(link, 1); + return tempmon_init(link, 1); } /****************************************************************************/ @@ -5373,12 +5379,8 @@ static int ddb_init(struct ddb *dev) pr_info("DDBridge: Could not allocate buffer memory\n"); goto fail2; } -#if 0 if (ddb_ports_attach(dev) < 0) goto fail3; -#else - ddb_ports_attach(dev); -#endif ddb_nsd_attach(dev); ddb_device_create(dev); diff --git a/ddbridge/ddbridge-mod.c b/ddbridge/ddbridge-mod.c index 799c8a5..b12c20f 100644 --- a/ddbridge/ddbridge-mod.c +++ b/ddbridge/ddbridge-mod.c @@ -237,7 +237,6 @@ static void mod_calc_rateinc(struct ddb_mod *mod) static int mod_calc_obitrate(struct ddb_mod *mod) { - struct ddb *dev = mod->port->dev; u64 ofac; ofac = (((u64) mod->symbolrate) << 32) * 188; @@ -249,7 +248,6 @@ static int mod_calc_obitrate(struct ddb_mod *mod) static int mod_set_symbolrate(struct ddb_mod *mod, u32 srate) { struct ddb *dev = mod->port->dev; - u64 ofac; if (dev->link[0].info->version < 2) { if (srate != 6900000) @@ -268,7 +266,6 @@ static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 }; static int mod_set_modulation(struct ddb_mod *mod, enum fe_modulation modulation) { struct ddb *dev = mod->port->dev; - u64 ofac; if (modulation > QAM_256 || modulation < QAM_16) return -EINVAL; @@ -308,8 +305,7 @@ int ddbridge_mod_output_start(struct ddb_output *output) u32 Channel = output->nr; struct ddb_mod *mod = &dev->mod[output->nr]; u32 Symbolrate = mod->symbolrate; - u32 ctrl; - + if (dev->link[0].info->version < 3) mod_calc_rateinc(mod); @@ -339,8 +335,8 @@ int ddbridge_mod_output_start(struct ddb_output *output) udelay(10); ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr)); - pr_info("DDBridge: CHANNEL_BASE = %08x\n", CHANNEL_BASE); - pr_info("DDBridge: CHANNEL_CONTROL = %08x\n", CHANNEL_CONTROL(Channel)); + //pr_info("DDBridge: CHANNEL_BASE = %08x\n", CHANNEL_BASE); + ///pr_info("DDBridge: CHANNEL_CONTROL = %08x\n", CHANNEL_CONTROL(Channel)); if (dev->link[0].info->version == 2) { //u32 Output = ((dev->mod_base.frequency - 114000000)/8000000 + Channel) % 96; u32 Output = (mod->frequency - 114000000) / 8000000; @@ -422,7 +418,7 @@ static u32 max2871_sdr[6] = { 0x007A8098, 0x600080C9, 0x510061C2, 0x010000CB, 0x6199003C, 0x60440005 }; -static int mod_setup_max2871_2(struct ddb *dev, u32 *reg) +static int mod_setup_max2871(struct ddb *dev, u32 *reg) { int status = 0; int i, j; @@ -456,46 +452,6 @@ static int mod_setup_max2871_2(struct ddb *dev, u32 *reg) return status; } -static int mod_setup_max2871(struct ddb *dev) -{ - int status = 0; - int i; - - ddbwritel(dev, MAX2871_CONTROL_CE, MAX2871_CONTROL); - msleep(30); - for (i = 0; i < 2; i++) { - status = mod_write_max2871(dev, 0x00440005); - if (status) - break; - status = mod_write_max2871(dev, 0x6199003C); - if (status) - break; - status = mod_write_max2871(dev, 0x000000CB); - if (status) - break; - status = mod_write_max2871(dev, 0x510061C2); - if (status) - break; - status = mod_write_max2871(dev, 0x600080A1); - if (status) - break; - status = mod_write_max2871(dev, 0x00730040); - if (status) - break; - msleep(30); - } - - if (status == 0) { - u32 ControlReg = ddbreadl(dev, MAX2871_CONTROL); - - if ((ControlReg & MAX2871_CONTROL_LOCK) == 0) - status = -EIO; - } - - return status; -} - - static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels) { int status = 0; @@ -503,7 +459,7 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels u32 tmp = ddbreadl(dev, FSM_STATUS); if ((tmp & FSM_STATUS_READY) == 0) { - status = mod_setup_max2871_2(dev, max2871_fsm); + status = mod_setup_max2871(dev, max2871_fsm); if (status) return status; ddbwritel(dev, FSM_CMD_RESET, FSM_CONTROL); @@ -557,12 +513,13 @@ static int mod_set_vga(struct ddb *dev, u32 Gain) return 0; } +#if 0 static int mod_get_vga(struct ddb *dev, u32 *pGain) { *pGain = ddbreadl(dev, RF_VGA); return 0; } -#if 0 + static void TemperatureMonitorSetFan(struct ddb *dev) { u32 tqam, pwm; @@ -1663,10 +1620,10 @@ static int mod_init_2(struct ddb *dev, u32 Frequency) static int mod_init_3(struct ddb *dev, u32 Frequency) { - int status, i, ret = 0; + int ret = 0; mod_set_vga(dev, 64); - ret = mod_setup_max2871_2(dev, max2871_sdr); + ret = mod_setup_max2871(dev, max2871_sdr); if (ret) pr_err("DDBridge: PLL setup failed\n"); return ret; diff --git a/ddbridge/ddbridge-regs.h b/ddbridge/ddbridge-regs.h index 22ba6f3..8840af1 100644 --- a/ddbridge/ddbridge-regs.h +++ b/ddbridge/ddbridge-regs.h @@ -25,6 +25,7 @@ #define CUR_REGISTERMAP_VERSION_V1 0x00010001 #define CUR_REGISTERMAP_VERSION_V2 0x00020000 +#define CUR_REGISTERMAP_VERSION_022X 0x00020001 #define HARDWARE_VERSION 0x00000000 #define REGISTERMAP_VERSION 0x00000004 @@ -179,6 +180,7 @@ #define TEMPMON2_BOARD (TEMPMON_SENSOR0) // SHORT Temperature in °C x 256 (ADM1032 int) #define TEMPMON2_FPGACORE (TEMPMON_SENSOR1) // SHORT Temperature in °C x 256 (ADM1032 ext) #define TEMPMON2_QAMCORE (TEMPMON_SENSOR2) // SHORT Temperature in °C x 256 (ADM1032 ext) +#define TEMPMON2_DACCORE (TEMPMON_SENSOR2) // SHORT Temperature in °C x 256 (ADM1032 ext) /* ------------------------------------------------------------------------- */ /* I2C Master Controller */ @@ -552,3 +554,77 @@ +// V2 + +// MAX2871 same as DVB Modulator V2 + +#define RFDAC_BASE (0x200) +#define RFDAC_CONTROL (RFDAC_BASE + 0x00) + +#define RFDAC_CMD_MASK (0x00000087) +#define RFDAC_CMD_STATUS (0x00000080) +#define RFDAC_CMD_RESET (0x00000080) +#define RFDAC_CMD_POWERDOWN (0x00000081) +#define RFDAC_CMD_SETUP (0x00000082) + +#define RFDAC_STATUS (RFDAC_BASE + 0x00) +#define RFDAC_STATUS_READY (0x00010000) +#define RFDAC_STATUS_DACREADY (0x00020000) + +#define RFDAC_FCW (RFDAC_BASE + 0x10) + +// +// -------------------------------------------------------------------------- +// + +#define JESD204B_BASE (0x280) + +// Additional Status Bits + +#define DMA_PCIE_LANES_MASK ( 0x00070000 ) + + +// -------------------------------------------------------------------------- +// Modulator Channels, partially compatible to DVB Modulator V1 + +#define SDR_CHANNEL_BASE (0x800) + +#define SDR_CHANNEL_CONTROL(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x00) +#define SDR_CHANNEL_CONFIG(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x04) +#define SDR_CHANNEL_CFCW(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x08) +#define SDR_CHANNEL_ARICW(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x0C) +#define SDR_CHANNEL_RGAIN(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x10) +#define SDR_CHANNEL_SETFIR(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x14) + +#define SDR_CHANNEL_FMDCW(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x20) +#define SDR_CHANNEL_FM1FCW(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x24) +#define SDR_CHANNEL_FM2FCW(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x28) +#define SDR_CHANNEL_FM1GAIN(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x2C) +#define SDR_CHANNEL_FM2GAIN(i) ((SDR_CHANNEL_BASE) + (i) * 64 + 0x30) + +// Control and status bits +#define SDR_CONTROL_ENABLE_CHANNEL (0x00000004) +#define SDR_CONTROL_ENABLE_DMA (0x00000008) +#define SDR_STATUS_DMA_UNDERRUN (0x00010000) + +// Config +#define SDR_CONFIG_ENABLE_FM1 (0x00000002) +#define SDR_CONFIG_ENABLE_FM2 (0x00000004) +#define SDR_CONFIG_DISABLE_ARI (0x00000010) +#define SDR_CONFIG_DISABLE_VSB (0x00000020) + +// SET FIR +#define SDR_FIR_COEFF_MASK (0x00000FFF) +#define SDR_FIR_TAP_MASK (0x001F0000) +#define SDR_FIR_SELECT_MASK (0x00C00000) +#define SDR_VSB_LENGTH_MASK (0x01000000) + +#define SDR_SET_FIR(select,tap,coeff,vsblen) \ + (\ +(((select)<<22)&SDR_FIR_SELECT_MASK)| \ +(((tap)<<16)&SDR_FIR_TAP_MASK)| \ +((coeff)&SDR_FIR_COEFF_MASK)| \ +(((vsblen)<<24)&SDR_VSB_LENGTH_MASK)| \ +0 \ +) +