diff --git a/frontends/drxk.h b/frontends/drxk.h index 7d43cbb..9b517c6 100644 --- a/frontends/drxk.h +++ b/frontends/drxk.h @@ -1,10 +1,10 @@ -#ifndef _DRXK_H_ -#define _DRXK_H_ - -#include -#include - -extern struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, - u8 adr, - struct dvb_frontend **fe_t); -#endif +#ifndef _DRXK_H_ +#define _DRXK_H_ + +#include +#include + +extern struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, + u8 adr, + struct dvb_frontend **fe_t); +#endif diff --git a/frontends/drxk_hard.c b/frontends/drxk_hard.c index 53cb65b..85fc35e 100644 --- a/frontends/drxk_hard.c +++ b/frontends/drxk_hard.c @@ -1,5097 +1,5097 @@ -/* - * drxk_hard: DRX-K DVB-C/T demodulator driver - * - * Copyright (C) 2010-2011 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_frontend.h" -#include "drxk.h" -#include "drxk_hard.h" - -static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); -static int PowerDownQAM(struct drxk_state *state); -static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); -static int SetQAMStandard(struct drxk_state *state,enum OperationMode oMode); -static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, - s32 tunerFreqOffset); -static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); -static int DVBTStart(struct drxk_state *state); -static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, - s32 tunerFreqOffset); -static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); -static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); -static int SwitchAntennaToQAM(struct drxk_state *state); -static int SwitchAntennaToDVBT(struct drxk_state *state); - -static bool IsDVBT(struct drxk_state *state) -{ - return state->m_OperationMode == OM_DVBT; -} - -static bool IsQAM(struct drxk_state *state) -{ - return state->m_OperationMode == OM_QAM_ITU_A || - state->m_OperationMode == OM_QAM_ITU_B || - state->m_OperationMode == OM_QAM_ITU_C; -} - -bool IsA1WithPatchCode(struct drxk_state *state) -{ - return state->m_DRXK_A1_PATCH_CODE; -} - -bool IsA1WithRomCode(struct drxk_state *state) -{ - return state->m_DRXK_A1_ROM_CODE; -} - -#define NOA1ROM 0 - -#ifndef CHK_ERROR - #define CHK_ERROR(s) if ((status = s) < 0) break -#endif - -#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) -#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) - -#define DEFAULT_MER_83 165 -#define DEFAULT_MER_93 250 - -#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH -#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) -#endif - -#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH -#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) -#endif - -#ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH -#define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06) -#endif - -#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 -#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 - -#ifndef DRXK_KI_RAGC_ATV -#define DRXK_KI_RAGC_ATV 4 -#endif -#ifndef DRXK_KI_IAGC_ATV -#define DRXK_KI_IAGC_ATV 6 -#endif -#ifndef DRXK_KI_DAGC_ATV -#define DRXK_KI_DAGC_ATV 7 -#endif - -#ifndef DRXK_KI_RAGC_QAM -#define DRXK_KI_RAGC_QAM 3 -#endif -#ifndef DRXK_KI_IAGC_QAM -#define DRXK_KI_IAGC_QAM 4 -#endif -#ifndef DRXK_KI_DAGC_QAM -#define DRXK_KI_DAGC_QAM 7 -#endif -#ifndef DRXK_KI_RAGC_DVBT -#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) -#endif -#ifndef DRXK_KI_IAGC_DVBT -#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) -#endif -#ifndef DRXK_KI_DAGC_DVBT -#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) -#endif - -#ifndef DRXK_AGC_DAC_OFFSET -#define DRXK_AGC_DAC_OFFSET (0x800) -#endif - -#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ -#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) -#endif - -#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ -#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) -#endif - -#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ -#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) -#endif - -#ifndef DRXK_QAM_SYMBOLRATE_MAX -#define DRXK_QAM_SYMBOLRATE_MAX (7233000) -#endif - -#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 -#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 -#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 -#define DRXK_BL_ROM_OFFSET_TAPS_BG 24 -#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 -#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 -#define DRXK_BL_ROM_OFFSET_TAPS_FM 48 -#define DRXK_BL_ROM_OFFSET_UCODE 0 - -#define DRXK_BLC_TIMEOUT 100 - -#define DRXK_BLCC_NR_ELEMENTS_TAPS 2 -#define DRXK_BLCC_NR_ELEMENTS_UCODE 6 - -#define DRXK_BLDC_NR_ELEMENTS_TAPS 28 - -#ifndef DRXK_OFDM_NE_NOTCH_WIDTH -#define DRXK_OFDM_NE_NOTCH_WIDTH (4) -#endif - -#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) -#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) -#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) -#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) -#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) - -static inline u32 MulDiv32(u32 a, u32 b, u32 c) -{ - u64 tmp64; - - tmp64 = (u64)a * (u64)b; - do_div(tmp64, c); - - return (u32) tmp64; -} - -inline u32 Frac28a(u32 a, u32 c) -{ - int i = 0; - u32 Q1 = 0; - u32 R0 = 0; - - R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ - Q1 = a / c; /* integer part, only the 4 least significant bits - will be visible in the result */ - - /* division using radix 16, 7 nibbles in the result */ - for (i = 0; i < 7; i++) { - Q1 = (Q1 << 4) | (R0 / c); - R0 = (R0 % c) << 4; - } - /* rounding */ - if ((R0 >> 3) >= c) - Q1++; - - return Q1; -} - -static u32 Log10Times100(u32 x) -{ - static const u8 scale = 15; - static const u8 indexWidth = 5; - u8 i = 0; - u32 y = 0; - u32 d = 0; - u32 k = 0; - u32 r = 0; - /* - log2lut[n] = (1< 0; k--) { - if (x & (((u32)1) << scale)) - break; - x <<= 1; - } - } else { - for (k = scale; k < 31 ; k++) { - if ((x & (((u32)(-1)) << (scale+1))) == 0) - break; - x >>= 1; - } - } - /* - Now x has binary point between bit[scale] and bit[scale-1] - and 1.0 <= x < 2.0 */ - - /* correction for divison: log(x) = log(x/y)+log(y) */ - y = k * ((((u32)1) << scale) * 200); - - /* remove integer part */ - x &= ((((u32)1) << scale)-1); - /* get index */ - i = (u8) (x >> (scale - indexWidth)); - /* compute delta (x - a) */ - d = x & ((((u32)1) << (scale - indexWidth)) - 1); - /* compute log, multiplication (d* (..)) must be within range ! */ - y += log2lut[i] + - ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); - /* Conver to log10() */ - y /= 108853; /* (log2(10) << scale) */ - r = (y >> 1); - /* rounding */ - if (y & ((u32)1)) - r++; - return (r); -} - -/****************************************************************************/ -/* I2C **********************************************************************/ -/****************************************************************************/ - -static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val) -{ - struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1 }}; - return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; -} - -static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -{ - struct i2c_msg msg = - {.addr = adr, .flags = 0, .buf = data, .len = len}; - - if (i2c_transfer(adap, &msg, 1) != 1) { - printk("i2c_write error\n"); - return -1; - } - return 0; -} - -static int i2c_read(struct i2c_adapter *adap, - u8 adr, u8 *msg, int len, u8 *answ, int alen) -{ - struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, - .buf = msg, .len = len}, - { .addr = adr, .flags = I2C_M_RD, - .buf = answ, .len = alen } }; - if (i2c_transfer(adap, msgs, 2) != 2) { - printk("i2c_read error\n"); - return -1; - } - return 0; -} - -static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags) -{ - u8 adr=state->demod_address, mm1[4], mm2[2], len; -#ifdef I2C_LONG_ADR - flags |= 0xC0; -#endif - if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { - mm1[0] = (((reg << 1) & 0xFF) | 0x01); - mm1[1] = ((reg >> 16) & 0xFF); - mm1[2] = ((reg >> 24) & 0xFF) | flags; - mm1[3] = ((reg >> 7) & 0xFF); - len = 4; - } else { - mm1[0] = ((reg << 1) & 0xFF); - mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); - len = 2; - } - if (i2c_read(state->i2c, adr, mm1, len, mm2, 2) < 0) - return -1; - if (data) - *data = mm2[0] | (mm2[1] << 8); - return 0; -} - -static int Read16_0(struct drxk_state *state, u32 reg, u16 *data) -{ - return Read16(state, reg, data, 0); -} - -static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags) -{ - u8 adr = state->demod_address, mm1[4], mm2[4], len; -#ifdef I2C_LONG_ADR - flags |= 0xC0; -#endif - if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { - mm1[0] = (((reg << 1) & 0xFF) | 0x01); - mm1[1] = ((reg >> 16) & 0xFF); - mm1[2] = ((reg >> 24) & 0xFF) | flags; - mm1[3] = ((reg >> 7) & 0xFF); - len = 4; - } else { - mm1[0] = ((reg << 1) & 0xFF); - mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); - len = 2; - } - if (i2c_read(state->i2c, adr, mm1, len, mm2, 4) < 0) - return -1; - if (data) - *data = mm2[0] | (mm2[1] << 8) | - (mm2[2] << 16) | (mm2[3] << 24); - return 0; -} - -static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags) -{ - u8 adr = state->demod_address, mm[6], len; -#ifdef I2C_LONG_ADR - flags |= 0xC0; -#endif - if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { - mm[0] = (((reg << 1) & 0xFF) | 0x01); - mm[1] = ((reg >> 16) & 0xFF); - mm[2] = ((reg >> 24) & 0xFF) | flags; - mm[3] = ((reg >> 7) & 0xFF); - len = 4; - } else { - mm[0] = ((reg << 1) & 0xFF); - mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); - len = 2; - } - mm[len] = data & 0xff; - mm[len+1] = (data >>8) & 0xff; - if (i2c_write(state->i2c, adr, mm, len + 2) < 0) - return -1; - return 0; -} - -static int Write16_0(struct drxk_state *state, u32 reg, u16 data) -{ - return Write16(state, reg, data, 0); -} - -static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags) -{ - u8 adr = state->demod_address, mm[8], len; -#ifdef I2C_LONG_ADR - flags |= 0xC0; -#endif - if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { - mm[0] = (((reg << 1) & 0xFF) | 0x01); - mm[1] = ((reg >> 16) & 0xFF); - mm[2] = ((reg >> 24) & 0xFF) | flags; - mm[3] = ((reg >> 7) & 0xFF); - len = 4; - } else { - mm[0] = ((reg << 1) & 0xFF); - mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); - len = 2; - } - mm[len] = data & 0xff; - mm[len+1] = (data >> 8) & 0xff; - mm[len+2] = (data >> 16) & 0xff; - mm[len+3] = (data >> 24) & 0xff; - if (i2c_write(state->i2c, adr, mm, len+4) < 0) - return -1; - return 0; -} - -static int WriteBlock(struct drxk_state *state, u32 Address, - const int BlockSize, const u8 pBlock[], u8 Flags) -{ - int status = 0, BlkSize = BlockSize; -#ifdef I2C_LONG_ADR - Flags |= 0xC0; -#endif - while (BlkSize > 0) { - int Chunk = BlkSize > state->m_ChunkSize ? - state->m_ChunkSize : BlkSize ; - u8 *AdrBuf = &state->Chunk[0]; - u32 AdrLength = 0; - - if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { - AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); - AdrBuf[1] = ((Address >> 16) & 0xFF); - AdrBuf[2] = ((Address >> 24) & 0xFF); - AdrBuf[3] = ((Address >> 7) & 0xFF); - AdrBuf[2] |= Flags; - AdrLength = 4; - if (Chunk == state->m_ChunkSize) - Chunk -= 2; - } else { - AdrBuf[0] = ((Address << 1) & 0xFF); - AdrBuf[1] = (((Address >> 16) & 0x0F) | - ((Address >> 18) & 0xF0)); - AdrLength = 2; - } - memcpy(&state->Chunk[AdrLength], pBlock, Chunk); - status = i2c_write(state->i2c, state->demod_address, - &state->Chunk[0], Chunk+AdrLength); - if (status<0) { - printk("I2C Write error\n"); - break; - } - pBlock += Chunk; - Address += (Chunk >> 1); - BlkSize -= Chunk; - } - return status; -} - -#ifndef DRXK_MAX_RETRIES_POWERUP -#define DRXK_MAX_RETRIES_POWERUP 20 -#endif - -int PowerUpDevice(struct drxk_state *state) -{ - int status; - u8 data = 0; - u16 retryCount = 0; - - status = i2c_read1(state->i2c, state->demod_address, &data); - if (status<0) - do { - data = 0; - if (i2c_write(state->i2c, - state->demod_address, &data, 1) < 0) - printk("powerup failed\n"); - msleep(10); - retryCount++ ; - } while (i2c_read1(state->i2c, - state->demod_address, &data) < 0 && - (retryCount < DRXK_MAX_RETRIES_POWERUP)); - if (retryCount >= DRXK_MAX_RETRIES_POWERUP) - return -1; - do { - /* Make sure all clk domains are active */ - CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, - SIO_CC_PWD_MODE_LEVEL_NONE)); - CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, - SIO_CC_UPDATE_KEY)); - /* Enable pll lock tests */ - CHK_ERROR(Write16_0(state, SIO_CC_PLL_LOCK__A, 1)); - state->m_currentPowerMode = DRX_POWER_UP; - } while (0); - return status; -} - - -static int init_state(struct drxk_state *state) -{ - u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; - u32 ulVSBIfAgcOutputLevel = 0; - u32 ulVSBIfAgcMinLevel = 0; - u32 ulVSBIfAgcMaxLevel = 0x7FFF; - u32 ulVSBIfAgcSpeed = 3; - - u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; - u32 ulVSBRfAgcOutputLevel = 0; - u32 ulVSBRfAgcMinLevel = 0; - u32 ulVSBRfAgcMaxLevel = 0x7FFF; - u32 ulVSBRfAgcSpeed = 3; - u32 ulVSBRfAgcTop = 9500; - u32 ulVSBRfAgcCutOffCurrent = 4000; - - u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; - u32 ulATVIfAgcOutputLevel = 0; - u32 ulATVIfAgcMinLevel = 0; - u32 ulATVIfAgcMaxLevel = 0; - u32 ulATVIfAgcSpeed = 3; - - u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; - u32 ulATVRfAgcOutputLevel = 0; - u32 ulATVRfAgcMinLevel = 0; - u32 ulATVRfAgcMaxLevel = 0; - u32 ulATVRfAgcTop = 9500; - u32 ulATVRfAgcCutOffCurrent = 4000; - u32 ulATVRfAgcSpeed = 3; - - u32 ulQual83 = DEFAULT_MER_83; - u32 ulQual93 = DEFAULT_MER_93; - - u32 ulDVBTStaticTSClock = 1; - u32 ulDVBCStaticTSClock = 1; - - u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; - u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; - - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - u32 ulGPIOCfg = 0x0113; - u32 ulGPIO = 0; - u32 ulSerialMode = 1; - u32 ulInvertTSClock = 0; - u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; - u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH; - u32 ulDVBTBitrate = 50000000; - u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; - - u32 ulInsertRSByte = 0; - - u32 ulRfMirror = 1; - u32 ulPowerDown = 0; - - u32 ulAntennaDVBT = 1; - u32 ulAntennaDVBC = 0; - u32 ulAntennaSwitchDVBTDVBC = 0; - - state->m_hasLNA = false; - state->m_hasDVBT= false; - state->m_hasDVBC= false; - state->m_hasATV= false; - state->m_hasOOB = false; - state->m_hasAudio = false; - - state->m_ChunkSize = 124; - - state->m_oscClockFreq = 0; - state->m_smartAntInverted = false; - state->m_bPDownOpenBridge = false; - - /* real system clock frequency in kHz */ - state->m_sysClockFreq = 151875; - /* Timing div, 250ns/Psys */ - /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ - state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * - HI_I2C_DELAY) / 1000; - /* Clipping */ - if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) - state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; - state->m_HICfgWakeUpKey = (state->demod_address << 1); - /* port/bridge/power down ctrl */ - state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; - - state->m_bPowerDown = (ulPowerDown != 0); - - state->m_DRXK_A1_PATCH_CODE = false; - state->m_DRXK_A1_ROM_CODE = false; - state->m_DRXK_A2_ROM_CODE = false; - state->m_DRXK_A3_ROM_CODE = false; - state->m_DRXK_A2_PATCH_CODE = false; - state->m_DRXK_A3_PATCH_CODE = false; - - /* Init AGC and PGA parameters */ - /* VSB IF */ - state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); - state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); - state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); - state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); - state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); - state->m_vsbPgaCfg = 140; - - /* VSB RF */ - state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); - state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); - state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); - state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); - state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); - state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); - state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); - state->m_vsbPreSawCfg.reference = 0x07; - state->m_vsbPreSawCfg.usePreSaw = true; - - state->m_Quality83percent = DEFAULT_MER_83; - state->m_Quality93percent = DEFAULT_MER_93; - if (ulQual93 <= 500 && ulQual83 < ulQual93) { - state->m_Quality83percent = ulQual83; - state->m_Quality93percent = ulQual93; - } - - /* ATV IF */ - state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); - state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); - state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); - state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); - state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); - - /* ATV RF */ - state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); - state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); - state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); - state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); - state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); - state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); - state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); - state->m_atvPreSawCfg.reference = 0x04; - state->m_atvPreSawCfg.usePreSaw = true; - - - /* DVBT RF */ - state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; - state->m_dvbtRfAgcCfg.outputLevel = 0; - state->m_dvbtRfAgcCfg.minOutputLevel = 0; - state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; - state->m_dvbtRfAgcCfg.top = 0x2100; - state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; - state->m_dvbtRfAgcCfg.speed = 1; - - - /* DVBT IF */ - state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; - state->m_dvbtIfAgcCfg.outputLevel = 0; - state->m_dvbtIfAgcCfg.minOutputLevel = 0; - state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; - state->m_dvbtIfAgcCfg.top = 13424; - state->m_dvbtIfAgcCfg.cutOffCurrent = 0; - state->m_dvbtIfAgcCfg.speed = 3; - state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; - state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; - // state->m_dvbtPgaCfg = 140; - - state->m_dvbtPreSawCfg.reference = 4; - state->m_dvbtPreSawCfg.usePreSaw = false; - - /* QAM RF */ - state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; - state->m_qamRfAgcCfg.outputLevel = 0; - state->m_qamRfAgcCfg.minOutputLevel = 6023; - state->m_qamRfAgcCfg.maxOutputLevel = 27000; - state->m_qamRfAgcCfg.top = 0x2380; - state->m_qamRfAgcCfg.cutOffCurrent = 4000; - state->m_qamRfAgcCfg.speed = 3; - - /* QAM IF */ - state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; - state->m_qamIfAgcCfg.outputLevel = 0; - state->m_qamIfAgcCfg.minOutputLevel = 0; - state->m_qamIfAgcCfg.maxOutputLevel = 9000; - state->m_qamIfAgcCfg.top = 0x0511; - state->m_qamIfAgcCfg.cutOffCurrent = 0; - state->m_qamIfAgcCfg.speed = 3; - state->m_qamIfAgcCfg.IngainTgtMax = 5119; - state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; - - state->m_qamPgaCfg = 140; - state->m_qamPreSawCfg.reference = 4; - state->m_qamPreSawCfg.usePreSaw = false; - - state->m_OperationMode = OM_NONE; - state->m_DrxkState = DRXK_UNINITIALIZED; - - /* MPEG output configuration */ - state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ - state->m_insertRSByte = false; /* If TRUE; insert RS byte */ - state->m_enableParallel = true; /* If TRUE; - parallel out otherwise serial */ - state->m_invertDATA = false; /* If TRUE; invert DATA signals */ - state->m_invertERR = false; /* If TRUE; invert ERR signal */ - state->m_invertSTR = false; /* If TRUE; invert STR signals */ - state->m_invertVAL = false; /* If TRUE; invert VAL signals */ - state->m_invertCLK = - (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ - state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0); - state->m_DVBCStaticCLK = - (ulDVBCStaticTSClock != 0); - /* If TRUE; static MPEG clockrate will be used; - otherwise clockrate will adapt to the bitrate of the TS */ - - state->m_DVBTBitrate = ulDVBTBitrate; - state->m_DVBCBitrate = ulDVBCBitrate; - - state->m_TSDataStrength = (ulTSDataStrength & 0x07); - state->m_TSClockkStrength = (ulTSClockkStrength & 0x07); - - /* Maximum bitrate in b/s in case static clockrate is selected */ - state->m_mpegTsStaticBitrate = 19392658; - state->m_disableTEIhandling = false; - - if (ulInsertRSByte) - state->m_insertRSByte = true; - - state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; - if (ulMpegLockTimeOut < 10000) - state->m_MpegLockTimeOut = ulMpegLockTimeOut; - state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; - if (ulDemodLockTimeOut < 10000) - state->m_DemodLockTimeOut = ulDemodLockTimeOut; - - // QAM defaults - state->m_Constellation = DRX_CONSTELLATION_AUTO; - state->m_qamInterleaveMode = DRXK_QAM_I12_J17; - state->m_fecRsPlen = 204*8; /* fecRsPlen annex A*/ - state->m_fecRsPrescale = 1; - - state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; - state->m_agcFastClipCtrlDelay = 0; - - state->m_GPIOCfg = (ulGPIOCfg); - state->m_GPIO = (ulGPIO == 0 ? 0 : 1); - - state->m_AntennaDVBT = (ulAntennaDVBT == 0 ? 0 : 1); - state->m_AntennaDVBC = (ulAntennaDVBC == 0 ? 0 : 1); - state->m_AntennaSwitchDVBTDVBC = - (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1); - - state->m_bPowerDown = false; - state->m_currentPowerMode = DRX_POWER_DOWN; - - state->m_enableParallel = (ulSerialMode == 0); - - state->m_rfmirror = (ulRfMirror == 0); - state->m_IfAgcPol = false; - return 0; -} - -static int DRXX_Open(struct drxk_state *state) -{ - int status = 0; - u32 jtag = 0; - u16 bid = 0; - u16 key = 0; - - do { - /* stop lock indicator process */ - CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, - SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - /* Check device id */ - CHK_ERROR(Read16(state, SIO_TOP_COMM_KEY__A, &key, 0)); - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, - SIO_TOP_COMM_KEY_KEY)); - CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0)); - CHK_ERROR(Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0)); - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, key)); - } while(0); - return status; -} - -static int GetDeviceCapabilities(struct drxk_state *state) -{ - u16 sioPdrOhwCfg = 0; - u32 sioTopJtagidLo = 0; - int status; - - do { - /* driver 0.9.0 */ - /* stop lock indicator process */ - CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, - SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); - CHK_ERROR(Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0)); - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); - - switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { - case 0: - /* ignore (bypass ?) */ - break; - case 1: - /* 27 MHz */ - state->m_oscClockFreq = 27000; - break; - case 2: - /* 20.25 MHz */ - state->m_oscClockFreq = 20250; - break; - case 3: - /* 4 MHz */ - state->m_oscClockFreq = 20250; - break; - default: - return -1; - } - /* - Determine device capabilities - Based on pinning v14 - */ - CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, - &sioTopJtagidLo, 0)); - /* driver 0.9.0 */ - switch((sioTopJtagidLo >> 29) & 0xF) { - case 0: - state->m_deviceSpin = DRXK_SPIN_A1; - break; - case 2: - state->m_deviceSpin = DRXK_SPIN_A2; - break; - case 3: - state->m_deviceSpin = DRXK_SPIN_A3; - break; - default: - state->m_deviceSpin = DRXK_SPIN_UNKNOWN; - status = -1; - break; - } - switch ((sioTopJtagidLo>>12)&0xFF) { - case 0x13: - /* typeId = DRX3913K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = false; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = false; - state->m_hasGPIO1 = false; - state->m_hasIRQN = false; - break; - case 0x15: - /* typeId = DRX3915K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = false; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x16: - /* typeId = DRX3916K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = false; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x18: - /* typeId = DRX3918K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = false; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x21: - /* typeId = DRX3921K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x23: - /* typeId = DRX3923K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x25: - /* typeId = DRX3925K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x26: - /* typeId = DRX3926K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - default: - printk("DeviceID not supported = %02x\n", - ((sioTopJtagidLo>>12)&0xFF)); - status = -1; - break; - } - } while(0); - return status; -} - -static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) -{ - int status; - bool powerdown_cmd; - - //printk("%s\n", __FUNCTION__); - - /* Write command */ - status = Write16_0(state, SIO_HI_RA_RAM_CMD__A, cmd); - if (status < 0) - return status; - if (cmd == SIO_HI_RA_RAM_CMD_RESET) - msleep(1); - - powerdown_cmd = - (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && - ((state->m_HICfgCtrl) & - SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == - SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); - if (powerdown_cmd == false) { - /* Wait until command rdy */ - u32 retryCount = 0; - u16 waitCmd; - - do { - msleep(1); - retryCount += 1; - status = Read16(state, SIO_HI_RA_RAM_CMD__A, - &waitCmd, 0); - } while ((status < 0) && - (retryCount < DRXK_MAX_RETRIES) && (waitCmd != 0)); - - if (status == 0) - status = Read16(state, SIO_HI_RA_RAM_RES__A, - pResult, 0); - } - return status; -} - -static int HI_CfgCommand(struct drxk_state *state) -{ - int status; - - mutex_lock(&state->mutex); - do { - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_6__A, - state->m_HICfgTimeout)); - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_5__A, - state->m_HICfgCtrl)); - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_4__A, - state->m_HICfgWakeUpKey)); - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_3__A, - state->m_HICfgBridgeDelay)); - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_2__A, - state->m_HICfgTimingDiv)); - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_1__A, - SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); - CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0)); - - state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - } while(0); - mutex_unlock(&state->mutex); - return status; -} - -static int InitHI(struct drxk_state *state) -{ - state->m_HICfgWakeUpKey = (state->demod_address<<1); - state->m_HICfgTimeout = 0x96FF; - /* port/bridge/power down ctrl */ - state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; - return HI_CfgCommand(state); -} - -static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) -{ - int status = -1; - u16 sioPdrMclkCfg = 0; - u16 sioPdrMdxCfg = 0; - - do { - /* stop lock indicator process */ - CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, - SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - - /* MPEG TS pad configuration */ - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); - - if (mpegEnable == false) { - /* Set MPEG TS pads to inputmode */ - CHK_ERROR(Write16_0(state, - SIO_PDR_MSTRT_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, - SIO_PDR_MERR_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, - SIO_PDR_MCLK_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, - SIO_PDR_MVAL_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000)); - } else { - /* Enable MPEG output */ - sioPdrMdxCfg = - ((state->m_TSDataStrength << - SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); - sioPdrMclkCfg = ((state->m_TSClockkStrength << - SIO_PDR_MCLK_CFG_DRIVE__B) | 0x0003); - - CHK_ERROR(Write16_0(state, SIO_PDR_MSTRT_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MERR_CFG__A, - 0x0000)); // Disable - CHK_ERROR(Write16_0(state, SIO_PDR_MVAL_CFG__A, - 0x0000)); // Disable - if (state->m_enableParallel == true) { - /* paralel -> enable MD1 to MD7 */ - CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, - sioPdrMdxCfg)); - } else { - sioPdrMdxCfg = ((state->m_TSDataStrength << - SIO_PDR_MD0_CFG_DRIVE__B) | - 0x0003); - /* serial -> disable MD1 to MD7 */ - CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, - 0x0000)); - } - CHK_ERROR(Write16_0(state, SIO_PDR_MCLK_CFG__A, - sioPdrMclkCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, - sioPdrMdxCfg)); - } - /* Enable MB output over MPEG pads and ctl input */ - CHK_ERROR(Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000)); - /* Write nomagic word to enable pdr reg write */ - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); - } while(0); - return status; -} - -static int MPEGTSDisable(struct drxk_state *state) -{ - return MPEGTSConfigurePins(state, false); -} - -static int BLChainCmd(struct drxk_state *state, - u16 romOffset, u16 nrOfElements, u32 timeOut) -{ - u16 blStatus = 0; - int status; - unsigned long end; - - mutex_lock(&state->mutex); - do { - CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, - SIO_BL_MODE_CHAIN)); - CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_ADDR__A, - romOffset)); - CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_LEN__A, - nrOfElements)); - CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, - SIO_BL_ENABLE_ON)); - end=jiffies+msecs_to_jiffies(timeOut); - - do { - msleep(1); - CHK_ERROR(Read16(state, SIO_BL_STATUS__A, - &blStatus, 0)); - } while ((blStatus == 0x1) && - ((time_is_after_jiffies(end)))); - if (blStatus == 0x1) { - printk("SIO not ready\n"); - mutex_unlock(&state->mutex); - return -1; - } - } while(0); - mutex_unlock(&state->mutex); - return status; -} - - -static int DownloadMicrocode(struct drxk_state *state, - const u8 pMCImage[], - u32 Length) -{ - const u8 *pSrc = pMCImage; - u16 Flags; - u16 Drain; - u32 Address; - u16 nBlocks; - u16 BlockSize; - u16 BlockCRC; - u32 offset = 0; - u32 i; - int status; - - /* down the drain (we don care about MAGIC_WORD) */ - Drain = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); - nBlocks = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); - - for (i = 0; i < nBlocks; i += 1) { - Address = (pSrc[0] << 24) | (pSrc[1] << 16) | - (pSrc[2] << 8) | pSrc[3]; - pSrc += sizeof(u32); offset += sizeof(u32); - - BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); - pSrc += sizeof(u16); offset += sizeof(u16); - - Flags = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); - - BlockCRC = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); - status = WriteBlock(state, Address, BlockSize, pSrc, 0); - if (status<0) - break; - pSrc += BlockSize; - offset += BlockSize; - } - return status; -} - -static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) -{ - int status; - u16 data = 0; - u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; - u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; - unsigned long end; - - if (enable == false) { - desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; - desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; - } - - status = (Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); - - if (data == desiredStatus) { - /* tokenring already has correct status */ - return status; - } - /* Disable/enable dvbt tokenring bridge */ - status = Write16_0(state,SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); - - end=jiffies+msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); - do - CHK_ERROR(Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); - while ((data != desiredStatus) && - ((time_is_after_jiffies(end)))); - if (data != desiredStatus) { - printk("SIO not ready\n"); - return -1; - } - return status; -} - -static int MPEGTSStop(struct drxk_state *state) -{ - int status = 0; - u16 fecOcSncMode = 0; - u16 fecOcIprMode = 0; - - do { - /* Gracefull shutdown (byte boundaries) */ - CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); - fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; - CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); - - /* Suppress MCLK during absence of data */ - CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcIprMode)); - fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; - CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, fecOcIprMode)); - } while (0); - return status; -} - -static int scu_command(struct drxk_state *state, - u16 cmd, u8 parameterLen, - u16 * parameter, u8 resultLen, u16 * result) -{ -#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 -#error DRXK register mapping no longer compatible with this routine! -#endif - u16 curCmd = 0; - int status; - unsigned long end; - - if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || - ((resultLen > 0) && (result == NULL))) - return -1; - - mutex_lock(&state->mutex); - do { - /* assume that the command register is ready - since it is checked afterwards */ - u8 buffer[34]; - int cnt = 0, ii; - - for (ii=parameterLen-1; ii >= 0; ii -= 1) { - buffer[cnt++] = (parameter[ii] & 0xFF); - buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); - } - buffer[cnt++] = (cmd & 0xFF); - buffer[cnt++] = ((cmd >> 8) & 0xFF); - - WriteBlock(state, SCU_RAM_PARAM_0__A - - (parameterLen-1), cnt, buffer, 0x00); - /* Wait until SCU has processed command */ - end=jiffies+msecs_to_jiffies(DRXK_MAX_WAITTIME); - do { - msleep(1); - CHK_ERROR(Read16_0(state, SCU_RAM_COMMAND__A, &curCmd)); - } while (! (curCmd == DRX_SCU_READY) && - (time_is_after_jiffies(end))); - if (curCmd != DRX_SCU_READY) { - printk("SCU not ready\n"); - mutex_unlock(&state->mutex); - return -1; - } - /* read results */ - if ((resultLen > 0) && (result != NULL)) { - s16 err; - int ii; - - for(ii=resultLen-1; ii >= 0; ii -= 1) { - CHK_ERROR(Read16_0(state, - SCU_RAM_PARAM_0__A - ii, - &result[ii])); - } - - /* Check if an error was reported by SCU */ - err = (s16)result[0]; - - /* check a few fixed error codes */ - if (err == SCU_RESULT_UNKSTD) { - printk("SCU_RESULT_UNKSTD\n"); - mutex_unlock(&state->mutex); - return -1; - } else if (err == SCU_RESULT_UNKCMD) { - printk("SCU_RESULT_UNKCMD\n"); - mutex_unlock(&state->mutex); - return -1; - } - /* here it is assumed that negative means error, - and positive no error */ - else if (err < 0) { - printk("%s ERROR\n", __FUNCTION__); - mutex_unlock(&state->mutex); - return -1; - } - } - } while(0); - mutex_unlock(&state->mutex); - if (status<0) - { - printk("%s: status = %d\n", __FUNCTION__, status); - } - - return status; -} - -static int SetIqmAf(struct drxk_state *state, bool active) -{ - u16 data = 0; - int status; - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",active)); - //printk("%s\n", __FUNCTION__); - - do - { - /* Configure IQM */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));; - if (!active) { - data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY - | IQM_AF_STDBY_STDBY_AMP_STANDBY - | IQM_AF_STDBY_STDBY_PD_STANDBY - | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY - | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY - ); - // break; - //default: - // break; - //} - } else /* active */ { - data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) - & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) - & (~IQM_AF_STDBY_STDBY_PD_STANDBY) - & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) - & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) - ); - // break; - //default: - // break; - //} - } - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); - }while(0); - return status; -} - -static int CtrlPowerMode(struct drxk_state *state, - pDRXPowerMode_t mode) -{ - int status = 0; - u16 sioCcPwdMode = 0; - - //printk("%s\n", __FUNCTION__); - /* Check arguments */ - if (mode == NULL) - return -1; - - switch (*mode) { - case DRX_POWER_UP: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; - break; - case DRXK_POWER_DOWN_OFDM: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; - break; - case DRXK_POWER_DOWN_CORE: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; - break; - case DRXK_POWER_DOWN_PLL: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; - break; - case DRX_POWER_DOWN: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; - break; - default: - /* Unknow sleep mode */ - return -1; - break; - } - - /* If already in requested power mode, do nothing */ - if (state->m_currentPowerMode == *mode) - return 0; - - /* For next steps make sure to start from DRX_POWER_UP mode */ - if (state->m_currentPowerMode != DRX_POWER_UP) - { - do { - CHK_ERROR(PowerUpDevice(state)); - CHK_ERROR(DVBTEnableOFDMTokenRing(state, true)); - } while(0); - } - - if (*mode == DRX_POWER_UP) { - /* Restore analog & pin configuartion */ - } else { - /* Power down to requested mode */ - /* Backup some register settings */ - /* Set pins with possible pull-ups connected - to them in input mode */ - /* Analog power down */ - /* ADC power down */ - /* Power down device */ - /* stop all comm_exec */ - /* Stop and power down previous standard */ - do { - switch (state->m_OperationMode) { - case OM_DVBT: - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(PowerDownDVBT(state, false)); - break; - case OM_QAM_ITU_A: - case OM_QAM_ITU_C: - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(PowerDownQAM(state)); - break; - default: - break; - } - CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); - CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, - sioCcPwdMode)); - CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, - SIO_CC_UPDATE_KEY)); - - if (*mode != DRXK_POWER_DOWN_OFDM) { - state->m_HICfgCtrl |= - SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - CHK_ERROR(HI_CfgCommand(state)); - } - } while(0); - } - state->m_currentPowerMode = *mode; - return (status); -} - -static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) -{ - DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; - u16 cmdResult = 0; - u16 data = 0; - int status; - - do { - CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); - if (data == SCU_COMM_EXEC_ACTIVE) { - /* Send OFDM stop command */ - CHK_ERROR(scu_command(state, - SCU_RAM_COMMAND_STANDARD_OFDM | - SCU_RAM_COMMAND_CMD_DEMOD_STOP, - 0, NULL, 1, &cmdResult)); - /* Send OFDM reset command */ - CHK_ERROR(scu_command(state, - SCU_RAM_COMMAND_STANDARD_OFDM | - SCU_RAM_COMMAND_CMD_DEMOD_RESET, - 0, NULL, 1, &cmdResult)); - } - - /* Reset datapath for OFDM, processors first */ - CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, - OFDM_SC_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, - OFDM_LC_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, - IQM_COMM_EXEC_B_STOP)); - - /* powerdown AFE */ - CHK_ERROR(SetIqmAf(state,false)); - - /* powerdown to OFDM mode */ - if (setPowerMode) { - CHK_ERROR(CtrlPowerMode(state,&powerMode)); - } - } while(0); - return status; -} - -static int SetOperationMode(struct drxk_state *state, enum OperationMode oMode) -{ - int status = 0; - - /* - Stop and power down previous standard - TODO investigate total power down instead of partial - power down depending on "previous" standard. - */ - do { - /* disable HW lock indicator */ - CHK_ERROR (Write16_0(state, SCU_RAM_GPIO__A, - SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - - if (state->m_OperationMode != oMode) { - switch (state->m_OperationMode) { - // OM_NONE was added for start up - case OM_NONE: - break; - case OM_DVBT: - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(PowerDownDVBT(state,true)); - state->m_OperationMode = OM_NONE; - break; - case OM_QAM_ITU_B: - status = -1; - break; - case OM_QAM_ITU_A: /* fallthrough */ - case OM_QAM_ITU_C: - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(PowerDownQAM(state)); - state->m_OperationMode = OM_NONE; - break; - default: - status = -1; - } - CHK_ERROR(status); - - /* - Power up new standard - */ - switch (oMode) - { - case OM_DVBT: - state->m_OperationMode = oMode; - CHK_ERROR(SetDVBTStandard(state, oMode)); - break; - case OM_QAM_ITU_B: - status = -1; - break; - case OM_QAM_ITU_A: /* fallthrough */ - case OM_QAM_ITU_C: - state->m_OperationMode = oMode; - CHK_ERROR(SetQAMStandard(state,oMode)); - break; - default: - status = -1; - } - } - CHK_ERROR(status); - } while(0); - return 0; -} - -static int Start(struct drxk_state *state, s32 offsetFreq, - s32 IntermediateFrequency) -{ - int status; - - do { - u16 IFreqkHz; - s32 OffsetkHz = offsetFreq / 1000; - - if (state->m_DrxkState != DRXK_STOPPED && - state->m_DrxkState != DRXK_DTV_STARTED) { - status = -1; - break; - } - state->m_bMirrorFreqSpect = -#ifndef USE_API3 - (state->props.inversion == INVERSION_ON); -#else - (state->param.inversion == INVERSION_ON); -#endif - if (IntermediateFrequency < 0) { - state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; - IntermediateFrequency = -IntermediateFrequency; - } - - switch(state->m_OperationMode) { - case OM_QAM_ITU_A: - case OM_QAM_ITU_C: - IFreqkHz = (IntermediateFrequency / 1000); - CHK_ERROR(SetQAM(state,IFreqkHz, OffsetkHz)); - state->m_DrxkState = DRXK_DTV_STARTED; - break; - case OM_DVBT: - IFreqkHz = (IntermediateFrequency / 1000); - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(SetDVBT(state,IFreqkHz, OffsetkHz)); - CHK_ERROR(DVBTStart(state)); - state->m_DrxkState = DRXK_DTV_STARTED; - break; - default: - break; - } - } while(0); - return status; -} - -static int ShutDown(struct drxk_state *state) -{ - MPEGTSStop(state); - return 0; -} - -static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, u32 Time) -{ - int status; - - if (pLockStatus == NULL) - return -1; - - *pLockStatus = NOT_LOCKED; - - /* define the SCU command code */ - switch (state->m_OperationMode) { - case OM_QAM_ITU_A: - case OM_QAM_ITU_B: - case OM_QAM_ITU_C: - status = GetQAMLockStatus(state, pLockStatus); - break; - case OM_DVBT: - status = GetDVBTLockStatus(state, pLockStatus); - break; - default: - break; - } - return status; -} - -static int MPEGTSStart(struct drxk_state *state) -{ - int status = 0; - - u16 fecOcSncMode = 0; - - do { - /* Allow OC to sync again */ - CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); - fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; - CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); - CHK_ERROR(Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1)); - } while (0); - return status; -} - -static int MPEGTSDtoInit(struct drxk_state *state) -{ - int status = -1; - - do { - /* Rate integration settings */ - CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000)); - CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C)); - CHK_ERROR(Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A)); - CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008)); - CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006)); - CHK_ERROR(Write16_0(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680)); - CHK_ERROR(Write16_0(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080)); - CHK_ERROR(Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4)); - - /* Additional configuration */ - CHK_ERROR(Write16_0(state, FEC_OC_OCR_INVERT__A, 0)); - CHK_ERROR(Write16_0(state, FEC_OC_SNC_LWM__A, 2)); - CHK_ERROR(Write16_0(state, FEC_OC_SNC_HWM__A, 12)); - } while (0); - return status; -} - -static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode) -{ - int status = -1; - - u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ - u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ - u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ - u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ - u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ - u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ - u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ - u16 fecOcTmdMode = 0; - u16 fecOcTmdIntUpdRate = 0; - u32 maxBitRate = 0; - bool staticCLK = false; - - do { - /* Check insertion of the Reed-Solomon parity bytes */ - CHK_ERROR(Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode)); - CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, - &fecOcRegIprMode)); - fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); - fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); - if (state->m_insertRSByte == true) { - /* enable parity symbol forward */ - fecOcRegMode |= FEC_OC_MODE_PARITY__M; - /* MVAL disable during parity bytes */ - fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; - /* TS burst length to 204 */ - fecOcDtoBurstLen = 204 ; - } - - /* Check serial or parrallel output */ - fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); - if (state->m_enableParallel == false) { - /* MPEG data output is serial -> set ipr_mode[0] */ - fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; - } - - switch (oMode) { - case OM_DVBT: - maxBitRate = state->m_DVBTBitrate; - fecOcTmdMode = 3; - fecOcRcnCtlRate = 0xC00000; - staticCLK = state->m_DVBTStaticCLK; - break; - case OM_QAM_ITU_A: /* fallthrough */ - case OM_QAM_ITU_C: - fecOcTmdMode = 0x0004; - fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ - maxBitRate = state->m_DVBCBitrate; - staticCLK = state->m_DVBCStaticCLK; - break; - default: - status = -1; - } /* switch (standard) */ - CHK_ERROR(status); - - /* Configure DTO's */ - if (staticCLK ) { - u32 bitRate = 0; - - /* Rational DTO for MCLK source (static MCLK rate), - Dynamic DTO for optimal grouping - (avoid intra-packet gaps), - DTO offset enable to sync TS burst with MSTRT */ - fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | - FEC_OC_DTO_MODE_OFFSET_ENABLE__M); - fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | - FEC_OC_FCT_MODE_VIRT_ENA__M); - - /* Check user defined bitrate */ - bitRate = maxBitRate; - if (bitRate > 75900000UL) - { /* max is 75.9 Mb/s */ - bitRate = 75900000UL; - } - /* Rational DTO period: - dto_period = (Fsys / bitrate) - 2 - - Result should be floored, - to make sure >= requested bitrate - */ - fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) - * 1000) / bitRate); - if (fecOcDtoPeriod <= 2) - fecOcDtoPeriod = 0; - else - fecOcDtoPeriod -= 2; - fecOcTmdIntUpdRate = 8; - } else { - /* (commonAttr->staticCLK == false) => dynamic mode */ - fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; - fecOcFctMode = FEC_OC_FCT_MODE__PRE; - fecOcTmdIntUpdRate = 5; - } - - /* Write appropriate registers with requested configuration */ - CHK_ERROR(Write16_0(state, FEC_OC_DTO_BURST_LEN__A, - fecOcDtoBurstLen)); - CHK_ERROR(Write16_0(state, FEC_OC_DTO_PERIOD__A, - fecOcDtoPeriod)); - CHK_ERROR(Write16_0(state, FEC_OC_DTO_MODE__A, - fecOcDtoMode)); - CHK_ERROR(Write16_0(state, FEC_OC_FCT_MODE__A, - fecOcFctMode)); - CHK_ERROR(Write16_0(state, FEC_OC_MODE__A, - fecOcRegMode)); - CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, - fecOcRegIprMode)); - - /* Rate integration settings */ - CHK_ERROR(Write32(state, FEC_OC_RCN_CTL_RATE_LO__A, - fecOcRcnCtlRate ,0)); - CHK_ERROR(Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A, - fecOcTmdIntUpdRate)); - CHK_ERROR(Write16_0(state, FEC_OC_TMD_MODE__A, - fecOcTmdMode)); - } while (0); - return status; -} - -static int MPEGTSConfigurePolarity(struct drxk_state *state) -{ - int status; - u16 fecOcRegIprInvert = 0; - - /* Data mask for the output data byte */ - u16 InvertDataMask = - FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | - FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | - FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | - FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; - - /* Control selective inversion of output bits */ - fecOcRegIprInvert &= (~(InvertDataMask)); - if (state->m_invertDATA == true) - fecOcRegIprInvert |= InvertDataMask; - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); - if (state->m_invertERR == true) - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); - if (state->m_invertSTR == true) - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); - if (state->m_invertVAL == true) - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); - if (state->m_invertCLK == true) - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; - status = Write16_0(state,FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); - return status; -} - -#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 - -static int SetAgcRf(struct drxk_state *state, - struct SCfgAgc *pAgcCfg, bool isDTV) -{ - int status = 0; - struct SCfgAgc *pIfAgcSettings; - - if (pAgcCfg == NULL) - return -1; - - do { - u16 data = 0; - - switch (pAgcCfg->ctrlMode) { - case DRXK_AGC_CTRL_AUTO: - - /* Enable RF AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); - data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); - - CHK_ERROR(Read16(state, SCU_RAM_AGC_CONFIG__A, - &data, 0)); - - /* Enable SCU RF AGC loop */ - data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; - - /* Polarity */ - if (state->m_RfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_CONFIG__A, data)); - - /* Set speed (using complementary reduction value) */ - CHK_ERROR(Read16(state, SCU_RAM_AGC_KI_RED__A, - &data, 0)); - - data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; - data |= (~(pAgcCfg->speed << - SCU_RAM_AGC_KI_RED_RAGC_RED__B) - & SCU_RAM_AGC_KI_RED_RAGC_RED__M); - - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_KI_RED__A, data)); - - if (IsDVBT(state)) - pIfAgcSettings = &state->m_dvbtIfAgcCfg; - else if (IsQAM(state)) - pIfAgcSettings = &state->m_qamIfAgcCfg; - else - pIfAgcSettings = &state->m_atvIfAgcCfg; - if (pIfAgcSettings == NULL) - return -1; - - /* Set TOP, only if IF-AGC is in AUTO mode */ - if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - pAgcCfg->top)); - - /* Cut-Off current */ - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_RF_IACCU_HI_CO__A, - pAgcCfg->cutOffCurrent)); - - /* Max. output level */ - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_MAX__A, - pAgcCfg->maxOutputLevel)); - - break; - - case DRXK_AGC_CTRL_USER: - /* Enable RF AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); - data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); - - /* Disable SCU RF AGC loop */ - CHK_ERROR(Read16_0(state, - SCU_RAM_AGC_CONFIG__A, &data)); - data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; - if (state->m_RfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CONFIG__A, - data)); - - /* SCU c.o.c. to 0, enabling full control range */ - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, - 0)); - - /* Write value to output pin */ - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, - pAgcCfg->outputLevel)); - break; - - case DRXK_AGC_CTRL_OFF: - /* Disable RF AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); - data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); - - /* Disable SCU RF AGC loop */ - CHK_ERROR(Read16_0(state, - SCU_RAM_AGC_CONFIG__A, &data)); - data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_CONFIG__A, data)); - break; - - default: - return -1; - - } /* switch (agcsettings->ctrlMode) */ - } while(0); - return status; -} - -#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 - -static int SetAgcIf (struct drxk_state *state, - struct SCfgAgc *pAgcCfg, bool isDTV) -{ - u16 data = 0; - int status = 0; - struct SCfgAgc *pRfAgcSettings; - - do { - switch (pAgcCfg->ctrlMode) { - case DRXK_AGC_CTRL_AUTO: - - /* Enable IF AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); - data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); - - CHK_ERROR(Read16_0(state, SCU_RAM_AGC_CONFIG__A, - &data)); - - /* Enable SCU IF AGC loop */ - data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; - - /* Polarity */ - if (state->m_IfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_CONFIG__A, data)); - - /* Set speed (using complementary reduction value) */ - CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI_RED__A, - &data)); - data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; - data |= (~(pAgcCfg->speed << - SCU_RAM_AGC_KI_RED_IAGC_RED__B) - & SCU_RAM_AGC_KI_RED_IAGC_RED__M); - - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_RED__A , - data)); - - if (IsQAM(state)) - pRfAgcSettings = &state->m_qamRfAgcCfg; - else - pRfAgcSettings = &state->m_atvRfAgcCfg; - if (pRfAgcSettings == NULL) - return -1; - /* Restore TOP */ - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - pRfAgcSettings->top)); - break; - - case DRXK_AGC_CTRL_USER: - - /* Enable IF AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); - data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); - - CHK_ERROR(Read16_0(state, - SCU_RAM_AGC_CONFIG__A, &data)); - - /* Disable SCU IF AGC loop */ - data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; - - /* Polarity */ - if (state->m_IfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_CONFIG__A, data)); - - /* Write value to output pin */ - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - pAgcCfg->outputLevel)); - break; - - case DRXK_AGC_CTRL_OFF: - - /* Disable If AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); - data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); - - /* Disable SCU IF AGC loop */ - CHK_ERROR(Read16_0(state, - SCU_RAM_AGC_CONFIG__A, &data)); - data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_CONFIG__A, data)); - break; - } /* switch (agcSettingsIf->ctrlMode) */ - - /* always set the top to support - configurations without if-loop */ - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, - pAgcCfg->top)); - - - } while(0); - return status; -} - -static int ReadIFAgc(struct drxk_state *state, u32 *pValue) -{ - u16 agcDacLvl; - int status = Read16_0(state, IQM_AF_AGC_IF__A, &agcDacLvl); - - *pValue = 0; - - if (status==0) { - u16 Level = 0; - if (agcDacLvl > DRXK_AGC_DAC_OFFSET) - Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; - if (Level < 14000) - *pValue = (14000 - Level) / 4 ; - else - *pValue = 0; - } - return status; -} - -static int GetQAMSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) -{ - int status = 0; - - do { - /* MER calculation */ - u16 qamSlErrPower = 0; /* accum. error between - raw and sliced symbols */ - u32 qamSlSigPower = 0; /* used for MER, depends of - QAM constellation */ - u32 qamSlMer = 0; /* QAM MER */ - - /* get the register value needed for MER */ - CHK_ERROR(Read16_0(state,QAM_SL_ERR_POWER__A, &qamSlErrPower)); - -#ifndef USE_API3 - switch(state->props.modulation) { -#else - switch(state->param.u.qam.modulation) { -#endif - case QAM_16: - qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; - break; - case QAM_32: - qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; - break; - case QAM_64: - qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; - break; - case QAM_128: - qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; - break; - default: - case QAM_256: - qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; - break; - } - - if (qamSlErrPower > 0) { - qamSlMer = Log10Times100(qamSlSigPower) - - Log10Times100((u32) qamSlErrPower); - } - *pSignalToNoise = qamSlMer; - } while(0); - return status; -} - -static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) -{ - int status = 0; - - u16 regData = 0; - u32 EqRegTdSqrErrI = 0; - u32 EqRegTdSqrErrQ = 0; - u16 EqRegTdSqrErrExp = 0; - u16 EqRegTdTpsPwrOfs = 0; - u16 EqRegTdReqSmbCnt = 0; - u32 tpsCnt = 0; - u32 SqrErrIQ = 0; - u32 a = 0; - u32 b = 0; - u32 c = 0; - u32 iMER = 0; - u16 transmissionParams = 0; - - do { - CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, - &EqRegTdTpsPwrOfs)); - CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, - &EqRegTdReqSmbCnt)); - CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, - &EqRegTdSqrErrExp)); - CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, - ®Data)); - /* Extend SQR_ERR_I operational range */ - EqRegTdSqrErrI = (u32) regData; - if ((EqRegTdSqrErrExp > 11) && - (EqRegTdSqrErrI < 0x00000FFFUL)) { - EqRegTdSqrErrI += 0x00010000UL; - } - CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A, - ®Data)); - /* Extend SQR_ERR_Q operational range */ - EqRegTdSqrErrQ = (u32)regData; - if ((EqRegTdSqrErrExp > 11) && - (EqRegTdSqrErrQ < 0x00000FFFUL)) - EqRegTdSqrErrQ += 0x00010000UL; - - CHK_ERROR(Read16_0(state,OFDM_SC_RA_RAM_OP_PARAM__A, - &transmissionParams)); - - /* Check input data for MER */ - - /* MER calculation (in 0.1 dB) without math.h */ - if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) - iMER = 0; - else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { - /* No error at all, this must be the HW reset value - * Apparently no first measurement yet - * Set MER to 0.0 */ - iMER = 0; - } else { - SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << - EqRegTdSqrErrExp; - if ((transmissionParams & - OFDM_SC_RA_RAM_OP_PARAM_MODE__M) - == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) - tpsCnt = 17; - else - tpsCnt = 68; - - /* IMER = 100 * log10 (x) - where x = (EqRegTdTpsPwrOfs^2 * - EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ - - => IMER = a + b -c - where a = 100 * log10 (EqRegTdTpsPwrOfs^2) - b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) - c = 100 * log10 (SqrErrIQ) - */ - - /* log(x) x = 9bits * 9bits->18 bits */ - a = Log10Times100(EqRegTdTpsPwrOfs*EqRegTdTpsPwrOfs); - /* log(x) x = 16bits * 7bits->23 bits */ - b = Log10Times100(EqRegTdReqSmbCnt*tpsCnt); - /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ - c = Log10Times100(SqrErrIQ); - - iMER = a + b; - /* No negative MER, clip to zero */ - if (iMER > c) - iMER -= c; - else - iMER = 0; - } - *pSignalToNoise = iMER; - } while(0); - - return status; -} - -static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) -{ - *pSignalToNoise = 0; - switch(state->m_OperationMode) { - case OM_DVBT: - return GetDVBTSignalToNoise(state, pSignalToNoise); - case OM_QAM_ITU_A: - case OM_QAM_ITU_C: - return GetQAMSignalToNoise(state, pSignalToNoise); - default: - break; - } - return 0; -} - -#if 0 -static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) -{ - /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ - int status = 0; - - static s32 QE_SN[] = - { - 51, // QPSK 1/2 - 69, // QPSK 2/3 - 79, // QPSK 3/4 - 89, // QPSK 5/6 - 97, // QPSK 7/8 - 108, // 16-QAM 1/2 - 131, // 16-QAM 2/3 - 146, // 16-QAM 3/4 - 156, // 16-QAM 5/6 - 160, // 16-QAM 7/8 - 165, // 64-QAM 1/2 - 187, // 64-QAM 2/3 - 202, // 64-QAM 3/4 - 216, // 64-QAM 5/6 - 225, // 64-QAM 7/8 - }; - - *pQuality = 0; - - do { - s32 SignalToNoise = 0; - u16 Constellation = 0; - u16 CodeRate = 0; - u32 SignalToNoiseRel; - u32 BERQuality; - - CHK_ERROR(GetDVBTSignalToNoise(state,&SignalToNoise)); - CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CONST__A, - &Constellation)); - Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; - - CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CODE_HP__A, - &CodeRate)); - CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; - - if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || - CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) - break; - SignalToNoiseRel = SignalToNoise - - QE_SN[Constellation * 5 + CodeRate]; - BERQuality = 100; - - if (SignalToNoiseRel < -70) *pQuality = 0; - else if (SignalToNoiseRel < 30) - *pQuality = ((SignalToNoiseRel + 70) * - BERQuality) / 100; - else - *pQuality = BERQuality; - } while(0); - return 0; -}; - -static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) -{ - int status = 0; - *pQuality = 0; - - do { - u32 SignalToNoise = 0; - u32 BERQuality = 100; - u32 SignalToNoiseRel = 0; - - CHK_ERROR(GetQAMSignalToNoise(state, &SignalToNoise)); - -#ifndef USE_API3 - switch(state->props.modulation) { -#else - switch(state->param.u.qam.modulation) { -#endif - case QAM_16: - SignalToNoiseRel = SignalToNoise - 200; - break; - case QAM_32: - SignalToNoiseRel = SignalToNoise - 230; - break; /* Not in NorDig */ - case QAM_64: - SignalToNoiseRel = SignalToNoise - 260; - break; - case QAM_128: - SignalToNoiseRel = SignalToNoise - 290; - break; - default: - case QAM_256: - SignalToNoiseRel = SignalToNoise - 320; - break; - } - - if (SignalToNoiseRel < -70) - *pQuality = 0; - else if (SignalToNoiseRel < 30) - *pQuality = ((SignalToNoiseRel + 70) * - BERQuality) / 100; - else - *pQuality = BERQuality; - } while(0); - - return status; -} - -static int GetQuality(struct drxk_state *state, s32 *pQuality) -{ - switch(state->m_OperationMode) { - case OM_DVBT: - return GetDVBTQuality(state, pQuality); - case OM_QAM_ITU_A: - return GetDVBCQuality(state, pQuality); - default: - break; - } - - return 0; -} -#endif - -/* Free data ram in SIO HI */ -#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 -#define SIO_HI_RA_RAM_USR_END__A 0x420060 - -#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) -#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) -#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ -#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE - -#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) -#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) -#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) - -static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) -{ - int status; - - if (state->m_DrxkState == DRXK_UNINITIALIZED) - return -1; - if (state->m_DrxkState == DRXK_POWERED_DOWN) - return -1; - - do { - CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, - SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); - if (bEnableBridge) { - CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, - SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED)); - } else { - CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, - SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN)); - } - - CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL,0)); - } while(0); - return status; -} - -static int SetPreSaw(struct drxk_state *state, struct SCfgPreSaw *pPreSawCfg) -{ - int status; - - if ((pPreSawCfg == NULL) || (pPreSawCfg->reference>IQM_AF_PDREF__M)) - return -1; - - status = Write16_0(state, IQM_AF_PDREF__A, pPreSawCfg->reference); - return status; -} - -static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, - u16 romOffset, u16 nrOfElements, u32 timeOut) -{ - u16 blStatus = 0; - u16 offset = (u16)((targetAddr >> 0) & 0x00FFFF); - u16 blockbank = (u16)((targetAddr >> 16) & 0x000FFF); - int status ; - unsigned long end; - - mutex_lock(&state->mutex); - do { - CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT)); - CHK_ERROR(Write16_0(state, SIO_BL_TGT_HDR__A, blockbank)); - CHK_ERROR(Write16_0(state, SIO_BL_TGT_ADDR__A, offset)); - CHK_ERROR(Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset)); - CHK_ERROR(Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements)); - CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON)); - - end=jiffies+msecs_to_jiffies(timeOut); - do { - CHK_ERROR(Read16_0(state, SIO_BL_STATUS__A, &blStatus)); - } while ((blStatus == 0x1) && - time_is_after_jiffies(end)); - if (blStatus == 0x1) { - printk("SIO not ready\n"); - mutex_unlock(&state->mutex); - return -1; - } - } while(0); - mutex_unlock(&state->mutex); - return status; - -} - -static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) -{ - u16 data = 0; - int status; - - do { - /* Start measurement */ - CHK_ERROR(Write16_0(state, IQM_AF_COMM_EXEC__A, - IQM_AF_COMM_EXEC_ACTIVE)); - CHK_ERROR(Write16_0(state,IQM_AF_START_LOCK__A, 1)); - - *count = 0; - CHK_ERROR(Read16_0(state,IQM_AF_PHASE0__A, &data)); - if (data == 127) - *count = *count+1; - CHK_ERROR(Read16_0(state,IQM_AF_PHASE1__A, &data)); - if (data == 127) - *count = *count+1; - CHK_ERROR(Read16_0(state,IQM_AF_PHASE2__A, &data)); - if (data == 127) - *count = *count+1; - } while(0); - return status; -} - -static int ADCSynchronization(struct drxk_state *state) -{ - u16 count = 0; - int status; - - do { - CHK_ERROR(ADCSyncMeasurement(state, &count)); - - if (count==1) { - /* Try sampling on a diffrent edge */ - u16 clkNeg = 0; - - CHK_ERROR(Read16_0(state, IQM_AF_CLKNEG__A, &clkNeg)); - if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == - IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { - clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); - clkNeg |= - IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; - } else { - clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); - clkNeg |= - IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; - } - CHK_ERROR(Write16_0(state, IQM_AF_CLKNEG__A, clkNeg)); - CHK_ERROR(ADCSyncMeasurement(state, &count)); - } - - if (count < 2) - status = -1; - } while (0); - return status; -} - -static int SetFrequencyShifter(struct drxk_state *state, - u16 intermediateFreqkHz, - s32 tunerFreqOffset, - bool isDTV) -{ - bool selectPosImage = false; - u32 rfFreqResidual = tunerFreqOffset; - u32 fmFrequencyShift = 0; - bool tunerMirror = !state->m_bMirrorFreqSpect; - u32 adcFreq; - bool adcFlip; - int status; - u32 ifFreqActual; - u32 samplingFrequency = (u32)(state->m_sysClockFreq / 3); - u32 frequencyShift; - bool imageToSelect; - - /* - Program frequency shifter - No need to account for mirroring on RF - */ - if (isDTV) { - if ((state->m_OperationMode == OM_QAM_ITU_A) || - (state->m_OperationMode == OM_QAM_ITU_C) || - (state->m_OperationMode == OM_DVBT)) - selectPosImage = true; - else - selectPosImage = false; - } - if (tunerMirror) - /* tuner doesn't mirror */ - ifFreqActual = intermediateFreqkHz + - rfFreqResidual + fmFrequencyShift; - else - /* tuner mirrors */ - ifFreqActual = intermediateFreqkHz - - rfFreqResidual - fmFrequencyShift; - if (ifFreqActual > samplingFrequency / 2) { - /* adc mirrors */ - adcFreq = samplingFrequency - ifFreqActual; - adcFlip = true; - } else { - /* adc doesn't mirror */ - adcFreq = ifFreqActual; - adcFlip = false; - } - - frequencyShift = adcFreq; - imageToSelect = state->m_rfmirror ^ tunerMirror ^ - adcFlip ^ selectPosImage; - state->m_IqmFsRateOfs = Frac28a((frequencyShift), samplingFrequency); - - if (imageToSelect) - state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; - - /* Program frequency shifter with tuner offset compensation */ - /* frequencyShift += tunerFreqOffset; TODO */ - status = Write32(state, IQM_FS_RATE_OFS_LO__A , - state->m_IqmFsRateOfs, 0); - return status; -} - -static int InitAGC(struct drxk_state *state, bool isDTV) -{ - u16 ingainTgt = 0; - u16 ingainTgtMin = 0; - u16 ingainTgtMax = 0; - u16 clpCyclen = 0; - u16 clpSumMin = 0; - u16 clpDirTo = 0; - u16 snsSumMin = 0; - u16 snsSumMax = 0; - u16 clpSumMax = 0; - u16 snsDirTo = 0; - u16 kiInnergainMin = 0; - u16 ifIaccuHiTgt = 0; - u16 ifIaccuHiTgtMin = 0; - u16 ifIaccuHiTgtMax = 0; - u16 data = 0; - u16 fastClpCtrlDelay = 0; - u16 clpCtrlMode = 0; - int status = 0; - - do { - /* Common settings */ - snsSumMax = 1023; - ifIaccuHiTgtMin = 2047; - clpCyclen = 500; - clpSumMax = 1023; - - if (IsQAM(state)) { - /* Standard specific settings */ - clpSumMin = 8; - clpDirTo = (u16) - 9; - clpCtrlMode = 0; - snsSumMin = 8; - snsDirTo = (u16) - 9; - kiInnergainMin = (u16) - 1030; - } else - status = -1; - CHK_ERROR((status)); - if (IsQAM(state)) { - ifIaccuHiTgtMax = 0x2380; - ifIaccuHiTgt = 0x2380; - ingainTgtMin = 0x0511; - ingainTgt = 0x0511; - ingainTgtMax = 5119; - fastClpCtrlDelay = - state->m_qamIfAgcCfg.FastClipCtrlDelay; - } else { - ifIaccuHiTgtMax = 0x1200; - ifIaccuHiTgt = 0x1200; - ingainTgtMin = 13424; - ingainTgt = 13424; - ingainTgtMax = 30000; - fastClpCtrlDelay = - state->m_dvbtIfAgcCfg.FastClipCtrlDelay; - } - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, - fastClpCtrlDelay)); - - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, - clpCtrlMode)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT__A, - ingainTgt)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, - ingainTgtMin)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, - ingainTgtMax)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, - ifIaccuHiTgtMin)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - ifIaccuHiTgtMax)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MAX__A, - clpSumMax)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MAX__A, - snsSumMax)); - - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, - kiInnergainMin)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, - ifIaccuHiTgt)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCLEN__A, - clpCyclen)); - - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, - 1023)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, - (u16) -1023)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, - 50)); - - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, - 20)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MIN__A, - clpSumMin)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MIN__A, - snsSumMin)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_TO__A, - clpDirTo)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A, - snsDirTo)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500)); - - /* Initialize inner-loop KI gain factors */ - CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI__A, &data)); - if (IsQAM(state)) { - data = 0x0657; - data &= ~SCU_RAM_AGC_KI_RF__M; - data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); - data &= ~SCU_RAM_AGC_KI_IF__M; - data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); - } - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI__A, data)); - } while(0); - return status; -} - -static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 * packetErr) -{ - int status; - - do { - if (packetErr == NULL) { - CHK_ERROR(Write16_0(state, - SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, - 0)); - } else { - CHK_ERROR(Read16_0(state, - SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, - packetErr)); - } - } while (0); - return status; -} - -static int DVBTScCommand(struct drxk_state *state, - u16 cmd, u16 subcmd, - u16 param0, u16 param1, u16 param2, - u16 param3, u16 param4) -{ - u16 curCmd = 0; - u16 errCode = 0; - u16 retryCnt = 0; - u16 scExec = 0; - int status; - - status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &scExec); - if (scExec != 1) { - /* SC is not running */ - return -1; - } - - /* Wait until sc is ready to receive command */ - retryCnt =0; - do { - msleep(1); - status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); - retryCnt++; - } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); - if (retryCnt >= DRXK_MAX_RETRIES) - return -1; - /* Write sub-command */ - switch (cmd) { - /* All commands using sub-cmd */ - case OFDM_SC_RA_RAM_CMD_PROC_START: - case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: - case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: - status = Write16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); - break; - default: - /* Do nothing */ - break; - } /* switch (cmd->cmd) */ - - /* Write needed parameters and the command */ - switch (cmd) { - /* All commands using 5 parameters */ - /* All commands using 4 parameters */ - /* All commands using 3 parameters */ - /* All commands using 2 parameters */ - case OFDM_SC_RA_RAM_CMD_PROC_START: - case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: - case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: - status = Write16_0(state, OFDM_SC_RA_RAM_PARAM1__A, param1); - /* All commands using 1 parameters */ - case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: - case OFDM_SC_RA_RAM_CMD_USER_IO: - status = Write16_0(state, OFDM_SC_RA_RAM_PARAM0__A, param0); - /* All commands using 0 parameters */ - case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: - case OFDM_SC_RA_RAM_CMD_NULL: - /* Write command */ - status = Write16_0(state, OFDM_SC_RA_RAM_CMD__A, cmd); - break; - default: - /* Unknown command */ - return -EINVAL; - } /* switch (cmd->cmd) */ - - /* Wait until sc is ready processing command */ - retryCnt = 0; - do{ - msleep(1); - status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); - retryCnt++; - } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); - if (retryCnt >= DRXK_MAX_RETRIES) - return -1; - - /* Check for illegal cmd */ - status = Read16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); - if (errCode == 0xFFFF) - { - /* illegal command */ - return -EINVAL; - } - - /* Retreive results parameters from SC */ - switch (cmd) { - /* All commands yielding 5 results */ - /* All commands yielding 4 results */ - /* All commands yielding 3 results */ - /* All commands yielding 2 results */ - /* All commands yielding 1 result */ - case OFDM_SC_RA_RAM_CMD_USER_IO: - case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: - status = Read16_0(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); - /* All commands yielding 0 results */ - case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: - case OFDM_SC_RA_RAM_CMD_SET_TIMER: - case OFDM_SC_RA_RAM_CMD_PROC_START: - case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: - case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: - case OFDM_SC_RA_RAM_CMD_NULL: - break; - default: - /* Unknown command */ - return -EINVAL; - break; - } /* switch (cmd->cmd) */ - return status; -} - -static int PowerUpDVBT (struct drxk_state *state) -{ - DRXPowerMode_t powerMode = DRX_POWER_UP; - int status; - - do { - CHK_ERROR(CtrlPowerMode(state, &powerMode)); - } while (0); - return status; -} - -static int DVBTCtrlSetIncEnable (struct drxk_state *state, bool* enabled) -{ - int status; - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - if (*enabled == true) - { - status = Write16_0(state, IQM_CF_BYPASSDET__A, 0); - } - else - { - status = Write16_0(state, IQM_CF_BYPASSDET__A, 1); - } - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - - return status; -} - #define DEFAULT_FR_THRES_8K 4000 -static int DVBTCtrlSetFrEnable (struct drxk_state *state, bool* enabled) -{ - - int status; - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - - if (*enabled == true) - { - /* write mask to 1 */ - status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, - DEFAULT_FR_THRES_8K); - } - else - { - /* write mask to 0 */ - status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); - } - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - - return status; -} - -static int DVBTCtrlSetEchoThreshold (struct drxk_state *state, - struct DRXKCfgDvbtEchoThres_t* echoThres) -{ - u16 data = 0; - int status; - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - - do { - CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data)); - - switch (echoThres->fftMode) - { - case DRX_FFTMODE_2K: - data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_2K__M; - data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_2K__B) & - (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); - break; - case DRX_FFTMODE_8K: - data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_8K__M; - data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_8K__B) & - (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); - break; - default: - return -1; - break; - } - - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data)); - } while (0); - - if (status<0) - { - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); - } - - return status; -} - -static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, - enum DRXKCfgDvbtSqiSpeed* speed) -{ - int status; - - switch (*speed) { - case DRXK_DVBT_SQI_SPEED_FAST: - case DRXK_DVBT_SQI_SPEED_MEDIUM: - case DRXK_DVBT_SQI_SPEED_SLOW: - break; - default: - return -EINVAL; - } - status = Write16_0 (state,SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, - (u16) *speed); - return status; -} - -/*============================================================================*/ - -/** -* \brief Activate DVBT specific presets -* \param demod instance of demodulator. -* \return DRXStatus_t. -* -* Called in DVBTSetStandard -* -*/ -static int DVBTActivatePresets (struct drxk_state *state) -{ - int status; - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - - struct DRXKCfgDvbtEchoThres_t echoThres2k = {0, DRX_FFTMODE_2K}; - struct DRXKCfgDvbtEchoThres_t echoThres8k = {0, DRX_FFTMODE_8K}; - - do { - bool setincenable = false; - bool setfrenable = true; - CHK_ERROR(DVBTCtrlSetIncEnable (state, &setincenable)); - CHK_ERROR(DVBTCtrlSetFrEnable (state, &setfrenable)); - CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres2k)); - CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres8k)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, - state->m_dvbtIfAgcCfg.IngainTgtMax)); - } while (0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - - return status; -} -/*============================================================================*/ - -/** -* \brief Initialize channelswitch-independent settings for DVBT. -* \param demod instance of demodulator. -* \return DRXStatus_t. -* -* For ROM code channel filter taps are loaded from the bootloader. For microcode -* the DVB-T taps from the drxk_filters.h are used. -*/ -static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode) -{ - u16 cmdResult = 0; - u16 data = 0; - int status; - - //printk("%s\n", __FUNCTION__); - - PowerUpDVBT(state); - - do { - /* added antenna switch */ - SwitchAntennaToDVBT(state); - /* send OFDM reset command */ - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); - - /* send OFDM setenv command */ - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,0,NULL,1,&cmdResult)); - - /* reset datapath for OFDM, processors first */ - CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP )); - - /* IQM setup */ - /* synchronize on ofdstate->m_festart */ - CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 1)); - /* window size for clipping ADC detection */ - CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); - /* window size for for sense pre-SAW detection */ - CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); - /* sense threshold for sense pre-SAW detection */ - CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); - CHK_ERROR(SetIqmAf(state,true)); - - CHK_ERROR(Write16_0(state, IQM_AF_AGC_RF__A, 0)); - - /* Impulse noise cruncher setup */ - CHK_ERROR(Write16_0(state, IQM_AF_INC_LCT__A, 0)); /* crunch in IQM_CF */ - CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); /* detect in IQM_CF */ - CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 3)); /* peak detector window length */ - - CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 16)); - CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 0x4)); /* enable output 2 */ - CHK_ERROR(Write16_0(state, IQM_CF_DS_ENA__A, 0x4)); /* decimate output 2 */ - CHK_ERROR(Write16_0(state, IQM_CF_SCALE__A, 1600)); - CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, 0)); - - /* virtual clipping threshold for clipping ADC detection */ - CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); - CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 495)); /* crunching threshold */ - - CHK_ERROR(BLChainCmd(state, - DRXK_BL_ROM_OFFSET_TAPS_DVBT, - DRXK_BLCC_NR_ELEMENTS_TAPS, - DRXK_BLC_TIMEOUT)); - - CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 2)); /* peak detector threshold */ - CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2)); - /* enable power measurement interrupt */ - CHK_ERROR(Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1)); - CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); - - /* IQM will not be reset from here, sync ADC and update/init AGC */ - CHK_ERROR(ADCSynchronization(state)); - CHK_ERROR(SetPreSaw(state, &state->m_dvbtPreSawCfg)); - - /* Halt SCU to enable safe non-atomic accesses */ - CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); - - CHK_ERROR(SetAgcRf(state, &state->m_dvbtRfAgcCfg, true)) ; - CHK_ERROR(SetAgcIf (state, &state->m_dvbtIfAgcCfg, true)); - - /* Set Noise Estimation notch width and enable DC fix */ - CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_CONFIG__A, &data)); - data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_CONFIG__A, data)); - - /* Activate SCU to enable SCU commands */ - CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); - - if (!state->m_DRXK_A3_ROM_CODE) - { - /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, - state->m_dvbtIfAgcCfg.FastClipCtrlDelay)); - } - - /* OFDM_SC setup */ -#ifdef COMPILE_FOR_NONRT - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2)); -#endif - - /* FEC setup */ - CHK_ERROR(Write16_0(state, FEC_DI_INPUT_CTL__A, 1)); /* OFDM input */ - - -#ifdef COMPILE_FOR_NONRT - CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x400)); -#else - CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x1000)); -#endif - CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A , 0x0001)); - - /* Setup MPEG bus */ - CHK_ERROR(MPEGTSDtoSetup (state,OM_DVBT)); - /* Set DVBT Presets */ - CHK_ERROR (DVBTActivatePresets (state)); - - } while (0); - - if (status<0) - { - printk("%s status - %08x\n",__FUNCTION__,status); - } - - return status; -} - -/*============================================================================*/ -/** -* \brief Start dvbt demodulating for channel. -* \param demod instance of demodulator. -* \return DRXStatus_t. -*/ -static int DVBTStart(struct drxk_state *state) -{ - u16 param1; - - int status; -// DRXKOfdmScCmd_t scCmd; - - //printk("%s\n",__FUNCTION__); - /* Start correct processes to get in lock */ - /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ - do { - param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; - CHK_ERROR(DVBTScCommand(state,OFDM_SC_RA_RAM_CMD_PROC_START,0,OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M,param1,0,0,0)); - /* Start FEC OC */ - CHK_ERROR(MPEGTSStart(state)); - CHK_ERROR(Write16_0(state,FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); - } while (0); - return (status); -} - - -/*============================================================================*/ - -/** -* \brief Set up dvbt demodulator for channel. -* \param demod instance of demodulator. -* \return DRXStatus_t. -* // original DVBTSetChannel() -*/ -static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) -{ - u16 cmdResult = 0; - u16 transmissionParams = 0; - u16 operationMode = 0; - u32 iqmRcRateOfs = 0; - u32 bandwidth = 0; - u16 param1; - int status; - - //printk("%s IF =%d, TFO = %d\n",__FUNCTION__,IntermediateFreqkHz,tunerFreqOffset); - do { - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | - SCU_RAM_COMMAND_CMD_DEMOD_STOP, - 0,NULL,1,&cmdResult)); - - /* Halt SCU to enable safe non-atomic accesses */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); - - /* Stop processors */ - CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); - - /* Mandatory fix, always stop CP, required to set spl offset back to - hardware default (is set to 0 by ucode during pilot detection */ - CHK_ERROR(Write16_0(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP)); - - /*== Write channel settings to device =====================================*/ - - /* mode */ -#ifndef USE_API3 - switch(state->props.transmission_mode) { -#else - switch(state->param.u.ofdm.transmission_mode) { -#endif - case TRANSMISSION_MODE_AUTO: - default: - operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; - /* fall through , try first guess DRX_FFTMODE_8K */ - case TRANSMISSION_MODE_8K: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; - break; - case TRANSMISSION_MODE_2K: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; - break; - } - - /* guard */ -#ifndef USE_API3 - switch(state->props.guard_interval) { -#else - switch(state->param.u.ofdm.guard_interval) { -#endif - default: - case GUARD_INTERVAL_AUTO: - operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; - /* fall through , try first guess DRX_GUARD_1DIV4 */ - case GUARD_INTERVAL_1_4: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; - break; - case GUARD_INTERVAL_1_32: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; - break; - case GUARD_INTERVAL_1_16: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; - break; - case GUARD_INTERVAL_1_8: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; - break; - } - - /* hierarchy */ -#ifndef USE_API3 - switch(state->props.hierarchy) { -#else - switch(state->param.u.ofdm.hierarchy_information) { -#endif - case HIERARCHY_AUTO: - case HIERARCHY_NONE: - default: - operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; - /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ - // transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; - //break; - case HIERARCHY_1: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; - break; - case HIERARCHY_2: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; - break; - case HIERARCHY_4: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; - break; - } - - - /* constellation */ -#ifndef USE_API3 - switch(state->props.modulation) { -#else - switch(state->param.u.ofdm.constellation) { -#endif - case QAM_AUTO: - default: - operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; - /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ - case QAM_64: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; - break; - case QPSK: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; - break; - case QAM_16: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; - break; - } -#if 0 - // No hierachical channels support in BDA - /* Priority (only for hierarchical channels) */ - switch (channel->priority) { - case DRX_PRIORITY_LOW : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; - WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_LO); - break; - case DRX_PRIORITY_HIGH : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; - WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); - break; - case DRX_PRIORITY_UNKNOWN : /* fall through */ - default: - return (DRX_STS_INVALID_ARG); - break; - } -#else - // Set Priorty high - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; - CHK_ERROR(Write16_0(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); -#endif - - /* coderate */ -#ifndef USE_API3 - switch(state->props.code_rate_HP) { -#else - switch(state->param.u.ofdm.code_rate_HP) { -#endif - case FEC_AUTO: - default: - operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; - /* fall through , try first guess DRX_CODERATE_2DIV3 */ - case FEC_2_3 : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; - break; - case FEC_1_2 : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; - break; - case FEC_3_4 : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; - break; - case FEC_5_6 : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; - break; - case FEC_7_8 : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; - break; - } - - /* SAW filter selection: normaly not necesarry, but if wanted - the application can select a SAW filter via the driver by using UIOs */ - /* First determine real bandwidth (Hz) */ - /* Also set delay for impulse noise cruncher */ - /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed - by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC - functions */ -#ifndef USE_API3 - switch(state->props.bandwidth_hz) { -#else - switch(state->param.u.ofdm.bandwidth) { -#endif -#ifndef USE_API3 - case 0: - case 8000000: -#else - case BANDWIDTH_AUTO: - case BANDWIDTH_8_MHZ: -#endif - bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052)); - /* cochannel protection for PAL 8 MHz */ - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); - break; -#ifndef USE_API3 - case 7000000: -#else - case BANDWIDTH_7_MHZ: -#endif - bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491)); - /* cochannel protection for PAL 7 MHz */ - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); - break; -#ifndef USE_API3 - case 6000000: -#else - case BANDWIDTH_6_MHZ: -#endif - bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073)); - /* cochannel protection for NTSC 6 MHz */ - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); - break; - } - - if (iqmRcRateOfs == 0) - { - /* Now compute IQM_RC_RATE_OFS - (((SysFreq/BandWidth)/2)/2) -1) * 2^23) - => - ((SysFreq / BandWidth) * (2^21)) - (2^23) - */ - /* (SysFreq / BandWidth) * (2^28) */ - /* assert (MAX(sysClk)/MIN(bandwidth) < 16) - => assert(MAX(sysClk) < 16*MIN(bandwidth)) - => assert(109714272 > 48000000) = true so Frac 28 can be used */ - iqmRcRateOfs = Frac28a((u32)((state->m_sysClockFreq * 1000)/3), bandwidth); - /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ - if ((iqmRcRateOfs & 0x7fL) >= 0x40) - { - iqmRcRateOfs += 0x80L; - } - iqmRcRateOfs = iqmRcRateOfs >> 7 ; - /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ - iqmRcRateOfs = iqmRcRateOfs - (1<<23); - } - - iqmRcRateOfs &= ((((u32)IQM_RC_RATE_OFS_HI__M)<m_DRXK_A3_ROM_CODE) - CHK_ERROR (DVBTCtrlSetSqiSpeed(state,&state->m_sqiSpeed)); - - } while(0); - if (status<0) { - //printk("%s status - %08x\n",__FUNCTION__,status); - } - - return status; -} - - -/*============================================================================*/ - -/** -* \brief Retreive lock status . -* \param demod Pointer to demodulator instance. -* \param lockStat Pointer to lock status structure. -* \return DRXStatus_t. -* -*/ -static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) -{ - int status; - const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | - OFDM_SC_RA_RAM_LOCK_FEC__M ); - const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); - const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M ; - - u16 ScRaRamLock = 0; - u16 ScCommExec = 0; - - /* driver 0.9.0 */ - /* Check if SC is running */ - status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); - if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) - { - /* SC not active; return DRX_NOT_LOCKED */ - *pLockStatus = NOT_LOCKED; - return status; - } - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - - status = Read16_0(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "RamLock: %04X\n",ScRaRamLock)); - - if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { - *pLockStatus = MPEG_LOCK; - } else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) { - *pLockStatus = FEC_LOCK; - } else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) { - *pLockStatus = DEMOD_LOCK; - } else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) { - *pLockStatus = NEVER_LOCK; - } else { - *pLockStatus = NOT_LOCKED; - } - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - - return status; -} - -static int PowerUpQAM (struct drxk_state *state) -{ - DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; - - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - CHK_ERROR(CtrlPowerMode(state, &powerMode)); - - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - - -/// Power Down QAM -static int PowerDownQAM(struct drxk_state *state) -{ - u16 data = 0; - u16 cmdResult; - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); - if (data == SCU_COMM_EXEC_ACTIVE) - { - /* - STOP demodulator - QAM and HW blocks - */ - /* stop all comstate->m_exec */ - CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP,0,NULL,1,&cmdResult)); - } - /* powerdown AFE */ - CHK_ERROR(SetIqmAf(state, false)); - } - while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} -/*============================================================================*/ - -/** -* \brief Setup of the QAM Measurement intervals for signal quality -* \param demod instance of demod. -* \param constellation current constellation. -* \return DRXStatus_t. -* -* NOTE: -* Take into account that for certain settings the errorcounters can overflow. -* The implementation does not check this. -* -*/ -static int SetQAMMeasurement(struct drxk_state *state, - enum EDrxkConstellation constellation, - u32 symbolRate) -{ - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ "(%d,%d) om = %d\n", constellation, symbolRate,state->m_OperationMode)); - - u32 fecBitsDesired = 0; /* BER accounting period */ - u32 fecRsPeriodTotal = 0; /* Total period */ - u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ - u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ - int status = 0; - - fecRsPrescale = 1; - - do { - - /* fecBitsDesired = symbolRate [kHz] * - FrameLenght [ms] * - (constellation + 1) * - SyncLoss (== 1) * - ViterbiLoss (==1) - */ - switch (constellation) - { - case DRX_CONSTELLATION_QAM16: - fecBitsDesired = 4 * symbolRate; - break; - case DRX_CONSTELLATION_QAM32: - fecBitsDesired = 5 * symbolRate; - break; - case DRX_CONSTELLATION_QAM64: - fecBitsDesired = 6 * symbolRate; - break; - case DRX_CONSTELLATION_QAM128: - fecBitsDesired = 7 * symbolRate; - break; - case DRX_CONSTELLATION_QAM256: - fecBitsDesired = 8 * symbolRate; - break; - default: - status = -EINVAL; - } - CHK_ERROR(status); - - fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ - fecBitsDesired *= 500; /* meas. period [ms] */ - - /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ - /* fecRsPeriodTotal = fecBitsDesired / 1632 */ - fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil*/ - - /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ - fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); - if (fecRsPrescale == 0) { - /* Divide by zero (though impossible) */ - status = -1; - } - CHK_ERROR(status); - fecRsPeriod = ((u16) fecRsPeriodTotal + (fecRsPrescale >> 1)) / - fecRsPrescale; - - /* write corresponding registers */ - CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod)); - CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale)); - CHK_ERROR(Write16_0(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod)); - - } while (0); - - if (status<0) { - printk("%s: status - %08x\n",__FUNCTION__,status); - } - return status; -} - -static int SetQAM16 (struct drxk_state *state) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - /* QAM Equalizer Setup */ - /* Equalizer */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517)); - /* Decision Feedback Equalizer */ - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); - - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); - - /* QAM Slicer Settings */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16)); - - /* QAM Loop Controller Coeficients */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); - - - /* QAM State Machine (FSM) Thresholds */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24)); - - - /* QAM FSM Tracking Parameters */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)-127)); - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - -/*============================================================================*/ - -/** -* \brief QAM32 specific setup -* \param demod instance of demod. -* \return DRXStatus_t. -*/ -static int SetQAM32 (struct drxk_state *state) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - /* QAM Equalizer Setup */ - /* Equalizer */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707)); - - /* Decision Feedback Equalizer */ - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); - - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); - - /* QAM Slicer Settings */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32)); - - - /* QAM Loop Controller Coeficients */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); - - - /* QAM State Machine (FSM) Thresholds */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10)); - - - /* QAM FSM Tracking Parameters */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86)); - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - -/*============================================================================*/ - -/** -* \brief QAM64 specific setup -* \param demod instance of demod. -* \return DRXStatus_t. -*/ -static int SetQAM64 (struct drxk_state *state) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - /* QAM Equalizer Setup */ - /* Equalizer */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609)); - - /* Decision Feedback Equalizer */ - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); - - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); - - /* QAM Slicer Settings */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64)); - - - /* QAM Loop Controller Coeficients */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); - - - /* QAM State Machine (FSM) Thresholds */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15)); - - - /* QAM FSM Tracking Parameters */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80)); - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - -/*============================================================================*/ - -/** -* \brief QAM128 specific setup -* \param demod: instance of demod. -* \return DRXStatus_t. -*/ -static int SetQAM128(struct drxk_state *state) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - /* QAM Equalizer Setup */ - /* Equalizer */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238)); - - /* Decision Feedback Equalizer */ - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); - - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); - - - /* QAM Slicer Settings */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM128)); - - - /* QAM Loop Controller Coeficients */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); - - - /* QAM State Machine (FSM) Thresholds */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); - - /* QAM FSM Tracking Parameters */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23)); - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - -/*============================================================================*/ - -/** -* \brief QAM256 specific setup -* \param demod: instance of demod. -* \return DRXStatus_t. -*/ -static int SetQAM256(struct drxk_state *state) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - /* QAM Equalizer Setup */ - /* Equalizer */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385)); - - /* Decision Feedback Equalizer */ - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); - - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); - - /* QAM Slicer Settings */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM256)); - - - /* QAM Loop Controller Coeficients */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); - - - /* QAM State Machine (FSM) Thresholds */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); - - - /* QAM FSM Tracking Parameters */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8)); - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - - -/*============================================================================*/ -/** -* \brief Reset QAM block. -* \param demod: instance of demod. -* \param channel: pointer to channel data. -* \return DRXStatus_t. -*/ -static int QAMResetQAM(struct drxk_state *state) -{ - int status; - u16 cmdResult; - - //printk("%s\n", __FUNCTION__); - do - { - /* Stop QAM comstate->m_exec */ - CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); - - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); - } while (0); - - /* All done, all OK */ - return status; -} - -/*============================================================================*/ - -/** -* \brief Set QAM symbolrate. -* \param demod: instance of demod. -* \param channel: pointer to channel data. -* \return DRXStatus_t. -*/ -static int QAMSetSymbolrate(struct drxk_state *state) -{ - u32 adcFrequency = 0; - u32 symbFreq = 0; - u32 iqmRcRate = 0; - u16 ratesel = 0; - u32 lcSymbRate = 0; - int status; - u32 srate = -#ifndef USE_API3 - state->props.symbol_rate; -#else - state->param.u.qam.symbol_rate; -#endif - - do - { - /* Select & calculate correct IQM rate */ - adcFrequency = (state->m_sysClockFreq * 1000) / 3; - ratesel = 0; - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " state->m_SymbolRate = %d\n",state->m_SymbolRate)); - //printk("SR %d\n", state->param.u.qam.symbol_rate); - if (srate <= 1188750) - { - ratesel = 3; - } - else if (srate <= 2377500) - { - ratesel = 2; - } - else if (srate <= 4755000) - { - ratesel = 1; - } - CHK_ERROR(Write16_0(state,IQM_FD_RATESEL__A, ratesel)); - - /* - IqmRcRate = ((Fadc / (symbolrate * (4<> 7) - - (1 << 23); - CHK_ERROR(Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate,0)); - state->m_iqmRcRate = iqmRcRate; - /* - LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) - */ - symbFreq = srate; - if (adcFrequency == 0) - { - /* Divide by zero */ - return -1; - } - lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + - (Frac28a((symbFreq % adcFrequency), adcFrequency) >> 16); - if (lcSymbRate > 511) - { - lcSymbRate = 511; - } - CHK_ERROR(Write16_0(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate)); - } while (0); - - return status; -} - -/*============================================================================*/ - -/** -* \brief Get QAM lock status. -* \param demod: instance of demod. -* \param channel: pointer to channel data. -* \return DRXStatus_t. -*/ - -static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) -{ - int status; - u16 Result[2] = {0,0}; - - status = scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM|SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, Result); - if (status<0) - { - printk("%s status = %08x\n",__FUNCTION__,status); - } - if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) - { - /* 0x0000 NOT LOCKED */ - *pLockStatus = NOT_LOCKED; - } - else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) - { - /* 0x4000 DEMOD LOCKED */ - *pLockStatus = DEMOD_LOCK; - } - else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) - { - /* 0x8000 DEMOD + FEC LOCKED (system lock) */ - *pLockStatus = MPEG_LOCK; - } - else - { - /* 0xC000 NEVER LOCKED */ - /* (system will never be able to lock to the signal) */ - /* TODO: check this, intermediate & standard specific lock states are not - taken into account here */ - *pLockStatus = NEVER_LOCK; - } - return status; -} - -#define QAM_MIRROR__M 0x03 -#define QAM_MIRROR_NORMAL 0x00 -#define QAM_MIRRORED 0x01 -#define QAM_MIRROR_AUTO_ON 0x02 -#define QAM_LOCKRANGE__M 0x10 -#define QAM_LOCKRANGE_NORMAL 0x10 - -static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - u8 parameterLen; - u16 setEnvParameters[5]; - u16 setParamParameters[4]={0,0,0,0}; - u16 cmdResult; - - //printk("%s\n", __FUNCTION__); - - do { - /* - STEP 1: reset demodulator - resets FEC DI and FEC RS - resets QAM block - resets SCU variables - */ - CHK_ERROR(Write16_0(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP)); - CHK_ERROR(QAMResetQAM(state)); - - /* - STEP 2: configure demodulator - -set env - -set params; resets IQM,QAM,FEC HW; initializes some SCU variables - */ - CHK_ERROR(QAMSetSymbolrate(state)); - - /* Env parameters */ - setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */ - if (state->m_OperationMode == OM_QAM_ITU_C) - { - setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */ - } - setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); -// check for LOCKRANGE Extented - // setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; - parameterLen = 4; - - /* Set params */ -#ifndef USE_API3 - switch(state->props.modulation) -#else - switch(state->param.u.qam.modulation) -#endif - { - case QAM_256: - state->m_Constellation = DRX_CONSTELLATION_QAM256; - break; - case QAM_AUTO: - case QAM_64: - state->m_Constellation = DRX_CONSTELLATION_QAM64; - break; - case QAM_16: - state->m_Constellation = DRX_CONSTELLATION_QAM16; - break; - case QAM_32: - state->m_Constellation = DRX_CONSTELLATION_QAM32; - break; - case QAM_128: - state->m_Constellation = DRX_CONSTELLATION_QAM128; - break; - default: - status = -EINVAL; - break; - } - CHK_ERROR(status); - setParamParameters[0] = state->m_Constellation; /* constellation */ - setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ - - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,4,setParamParameters,1,&cmdResult)); - - - /* STEP 3: enable the system in a mode where the ADC provides valid signal - setup constellation independent registers */ -// CHK_ERROR (SetFrequency (channel, tunerFreqOffset)); - CHK_ERROR (SetFrequencyShifter (state, IntermediateFreqkHz, tunerFreqOffset, true)); - - /* Setup BER measurement */ - CHK_ERROR(SetQAMMeasurement (state, - state->m_Constellation, -#ifndef USE_API3 - state->props.symbol_rate)); -#else - state->param.u.qam.symbol_rate)); -#endif - - /* Reset default values */ - CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE)); - CHK_ERROR(Write16_0(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE)); - - /* Reset default LC values */ - CHK_ERROR(Write16_0(state, QAM_LC_RATE_LIMIT__A, 3)); - CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORP__A, 4)); - CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORI__A, 4)); - CHK_ERROR(Write16_0(state, QAM_LC_MODE__A, 7)); - - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB0__A, 1)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB1__A, 1)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB2__A, 1)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB3__A, 1)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB4__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB5__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB6__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB8__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB9__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB10__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB12__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB15__A, 3)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB16__A, 3)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB20__A, 4)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB25__A, 4)); - - /* Mirroring, QAM-block starting point not inverted */ - CHK_ERROR(Write16_0(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS)); - - /* Halt SCU to enable safe non-atomic accesses */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); - - /* STEP 4: constellation specific setup */ -#ifndef USE_API3 - switch (state->props.modulation) -#else - switch (state->param.u.qam.modulation) -#endif - { - case QAM_16: - CHK_ERROR(SetQAM16(state)); - break; - case QAM_32: - CHK_ERROR(SetQAM32(state)); - break; - case QAM_AUTO: - case QAM_64: - CHK_ERROR(SetQAM64(state)); - break; - case QAM_128: - CHK_ERROR(SetQAM128(state)); - break; - case QAM_256: - //printk("SETQAM256\n"); - CHK_ERROR(SetQAM256(state)); - break; - default: - return -1; - break; - } /* switch */ - /* Activate SCU to enable SCU commands */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); - - - /* Re-configure MPEG output, requires knowledge of channel bitrate */ -// extAttr->currentChannel.constellation = channel->constellation; -// extAttr->currentChannel.symbolrate = channel->symbolrate; - CHK_ERROR(MPEGTSDtoSetup(state, state->m_OperationMode)); - - /* Start processes */ - CHK_ERROR(MPEGTSStart(state)); - CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); - CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE)); - CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); - - /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_START,0, - NULL,1,&cmdResult)); - - /* update global DRXK data container */ -//? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; - - /* All done, all OK */ - } while(0); - - if (status<0) { - printk("%s %d\n", __FUNCTION__, status); - } - return status; -} - -static int SetQAMStandard(struct drxk_state *state, enum OperationMode oMode) -{ -#ifdef DRXK_QAM_TAPS -#define DRXK_QAMA_TAPS_SELECT -#include "drxk_filters.h" -#undef DRXK_QAMA_TAPS_SELECT -#else - int status; -#endif - - //printk("%s\n", __FUNCTION__); - do - { - /* added antenna switch */ - SwitchAntennaToQAM(state); - - /* Ensure correct power-up mode */ - CHK_ERROR(PowerUpQAM(state)); - /* Reset QAM block */ - CHK_ERROR(QAMResetQAM(state)); - - /* Setup IQM */ - - CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP)); - CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); - - /* Upload IQM Channel Filter settings by - boot loader from ROM table */ - switch (oMode) - { - case OM_QAM_ITU_A: - CHK_ERROR(BLChainCmd(state, - DRXK_BL_ROM_OFFSET_TAPS_ITU_A, - DRXK_BLCC_NR_ELEMENTS_TAPS, - DRXK_BLC_TIMEOUT)); - break; - case OM_QAM_ITU_C: - CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_RE0__A, - DRXK_BL_ROM_OFFSET_TAPS_ITU_C, - DRXK_BLDC_NR_ELEMENTS_TAPS, - DRXK_BLC_TIMEOUT)); - CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_IM0__A, - DRXK_BL_ROM_OFFSET_TAPS_ITU_C, - DRXK_BLDC_NR_ELEMENTS_TAPS, - DRXK_BLC_TIMEOUT)); - break; - default: - status=-EINVAL; - } - CHK_ERROR (status); - - CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, - (1 << IQM_CF_OUT_ENA_QAM__B))); - CHK_ERROR(Write16_0(state, IQM_CF_SYMMETRIC__A, 0)); - CHK_ERROR(Write16_0(state, IQM_CF_MIDTAP__A, - ((1 << IQM_CF_MIDTAP_RE__B) | - (1 << IQM_CF_MIDTAP_IM__B)))); - - CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 21)); - CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); - CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); - CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); - CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0)); - - CHK_ERROR(Write16_0(state, IQM_FS_ADJ_SEL__A, 1)); - CHK_ERROR(Write16_0(state, IQM_RC_ADJ_SEL__A, 1)); - CHK_ERROR(Write16_0(state, IQM_CF_ADJ_SEL__A, 1)); - CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 0)); - - /* IQM Impulse Noise Processing Unit */ - CHK_ERROR(Write16_0(state, IQM_CF_CLP_VAL__A, 500)); - CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 1000)); - CHK_ERROR(Write16_0(state, IQM_CF_BYPASSDET__A, 1)); - CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); - CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 1)); - CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 1)); - CHK_ERROR(Write16_0(state, IQM_AF_INC_BYPASS__A, 1)); - - /* turn on IQMAF. Must be done before setAgc**() */ - CHK_ERROR(SetIqmAf(state, true)); - CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 0x01)); - - /* IQM will not be reset from here, sync ADC and update/init AGC */ - CHK_ERROR(ADCSynchronization (state)); - - /* Set the FSM step period */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000)); - - /* Halt SCU to enable safe non-atomic accesses */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); - - /* No more resets of the IQM, current standard correctly set => - now AGCs can be configured. */ - - CHK_ERROR(InitAGC(state,true)); - CHK_ERROR(SetPreSaw(state, &(state->m_qamPreSawCfg))); - - /* Configure AGC's */ - CHK_ERROR(SetAgcRf(state, &(state->m_qamRfAgcCfg), true)); - CHK_ERROR(SetAgcIf (state, &(state->m_qamIfAgcCfg), true)); - - /* Activate SCU to enable SCU commands */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); - } while (0); - return status; -} - -static int WriteGPIO(struct drxk_state *state) -{ - int status; - u16 value = 0; - - do { - /* stop lock indicator process */ - CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, - SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - - /* Write magic word to enable pdr reg write */ - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, - SIO_TOP_COMM_KEY_KEY)); - - if (state->m_hasSAWSW) { - /* write to io pad configuration register - output mode */ - CHK_ERROR(Write16_0(state, SIO_PDR_SMA_TX_CFG__A, - state->m_GPIOCfg)); - - /* use corresponding bit in io data output registar */ - CHK_ERROR(Read16_0(state, SIO_PDR_UIO_OUT_LO__A, &value)); - if (state->m_GPIO == 0) { - value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ - } else { - value |= 0x8000; /* write one to 15th bit - 1st UIO */ - } - /* write back to io data output register */ - CHK_ERROR(Write16_0(state, SIO_PDR_UIO_OUT_LO__A, value)); - - } - /* Write magic word to disable pdr reg write */ - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); - } while (0); - return status; -} - -static int SwitchAntennaToQAM(struct drxk_state *state) -{ - int status = -1; - - if (state->m_AntennaSwitchDVBTDVBC != 0) { - if (state->m_GPIO != state->m_AntennaDVBC) { - state->m_GPIO = state->m_AntennaDVBC; - status = WriteGPIO(state); - } - } - return status; -} - -static int SwitchAntennaToDVBT(struct drxk_state *state) -{ - int status = -1; - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - if (state->m_AntennaSwitchDVBTDVBC != 0) { - if (state->m_GPIO != state->m_AntennaDVBT) { - state->m_GPIO = state->m_AntennaDVBT; - status = WriteGPIO(state); - } - } - return status; -} - - -static int PowerDownDevice(struct drxk_state *state) -{ - /* Power down to requested mode */ - /* Backup some register settings */ - /* Set pins with possible pull-ups connected to them in input mode */ - /* Analog power down */ - /* ADC power down */ - /* Power down device */ - int status; - do { - if (state->m_bPDownOpenBridge) { - // Open I2C bridge before power down of DRXK - CHK_ERROR(ConfigureI2CBridge(state, true)); - } - // driver 0.9.0 - CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); - - CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK)); - CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY)); - state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - CHK_ERROR(HI_CfgCommand(state)); - } - while(0); - - if (status<0) { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - return -1; - } - return 0; -} - -static int load_microcode(struct drxk_state *state, char *mc_name) -{ - const struct firmware *fw = NULL; - int err=0; - - err = request_firmware(&fw, mc_name, state->i2c->dev.parent); - if (err < 0) { - printk(KERN_ERR - ": Could not load firmware file %s.\n", mc_name); - printk(KERN_INFO - ": Copy %s to your hotplug directory!\n", mc_name); - return err; - } - err=DownloadMicrocode(state, fw->data, fw->size); - release_firmware(fw); - return err; -} - -static int init_drxk(struct drxk_state *state) -{ - int status; - DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; - u16 driverVersion; - - //printk("init_drxk\n"); - if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { - do { - CHK_ERROR(PowerUpDevice(state)); - CHK_ERROR (DRXX_Open(state)); - /* Soft reset of OFDM-, sys- and osc-clockdomain */ - CHK_ERROR(Write16_0(state, SIO_CC_SOFT_RST__A, - SIO_CC_SOFT_RST_OFDM__M | - SIO_CC_SOFT_RST_SYS__M | - SIO_CC_SOFT_RST_OSC__M)); - CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY)); - /* TODO is this needed, if yes how much delay in worst case scenario */ - msleep(1); - state->m_DRXK_A3_PATCH_CODE = true; - CHK_ERROR(GetDeviceCapabilities(state)); - - /* Bridge delay, uses oscilator clock */ - /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ - /* SDA brdige delay */ - state->m_HICfgBridgeDelay = (u16)((state->m_oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000; - /* Clipping */ - if (state->m_HICfgBridgeDelay > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) - { - state->m_HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; - } - /* SCL bridge delay, same as SDA for now */ - state->m_HICfgBridgeDelay += state->m_HICfgBridgeDelay << SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; - - CHK_ERROR(InitHI(state)); - /* disable various processes */ -#if NOA1ROM - if (!(state->m_DRXK_A1_ROM_CODE) && !(state->m_DRXK_A2_ROM_CODE) ) -#endif - { - CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - } - - /* disable MPEG port */ - CHK_ERROR(MPEGTSDisable(state)); - - /* Stop AUD and SCU */ - CHK_ERROR(Write16_0(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP)); - - /* enable token-ring bus through OFDM block for possible ucode upload */ - CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON)); - - /* include boot loader section */ - CHK_ERROR(Write16_0(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE)); - CHK_ERROR(BLChainCmd(state, 0, 6, 100)); - -#if 0 - if (state->m_DRXK_A3_PATCH_CODE) - CHK_ERROR(DownloadMicrocode(state, - DRXK_A3_microcode, - DRXK_A3_microcode_length)); -#else - load_microcode(state, "drxk_a3.mc"); -#endif -#if NOA1ROM - if (state->m_DRXK_A2_PATCH_CODE) - CHK_ERROR(DownloadMicrocode(state, - DRXK_A2_microcode, - DRXK_A2_microcode_length)); -#endif - /* disable token-ring bus through OFDM block for possible ucode upload */ - CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF)); - - /* Run SCU for a little while to initialize microcode version numbers */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); - CHK_ERROR (DRXX_Open(state)); - // added for test - msleep(30); - - powerMode = DRXK_POWER_DOWN_OFDM; - CHK_ERROR(CtrlPowerMode(state, &powerMode)); - - /* Stamp driver version number in SCU data RAM in BCD code - Done to enable field application engineers to retreive drxdriver version - via I2C from SCU RAM. - Not using SCU command interface for SCU register access since no - microcode may be present. - */ - driverVersion = (((DRXK_VERSION_MAJOR/100) % 10) << 12) + - (((DRXK_VERSION_MAJOR/10) % 10) << 8) + - ((DRXK_VERSION_MAJOR%10) << 4) + - (DRXK_VERSION_MINOR%10); - CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion )); - driverVersion = (((DRXK_VERSION_PATCH/1000) % 10) << 12) + - (((DRXK_VERSION_PATCH/100) % 10) << 8) + - (((DRXK_VERSION_PATCH/10) % 10) << 4) + - (DRXK_VERSION_PATCH%10); - CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion )); - - printk("DRXK driver version:%d.%d.%d\n", - DRXK_VERSION_MAJOR,DRXK_VERSION_MINOR,DRXK_VERSION_PATCH); - - /* Dirty fix of default values for ROM/PATCH microcode - Dirty because this fix makes it impossible to setup suitable values - before calling DRX_Open. This solution requires changes to RF AGC speed - to be done via the CTRL function after calling DRX_Open */ - - // m_dvbtRfAgcCfg.speed=3; - - /* Reset driver debug flags to 0 */ - CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_DEBUG__A, 0)); - /* driver 0.9.0 */ - /* Setup FEC OC: - NOTE: No more full FEC resets allowed afterwards!! */ - CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP)); - // MPEGTS functions are still the same - CHK_ERROR(MPEGTSDtoInit(state)); - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(MPEGTSConfigurePolarity(state)); - CHK_ERROR(MPEGTSConfigurePins(state, state->m_enableMPEGOutput)); - // added: configure GPIO - CHK_ERROR(WriteGPIO(state)); - - state->m_DrxkState = DRXK_STOPPED; - - if (state->m_bPowerDown) { - CHK_ERROR(PowerDownDevice(state)); - state->m_DrxkState = DRXK_POWERED_DOWN; - } - else - state->m_DrxkState = DRXK_STOPPED; - } while(0); - //printk("%s=%d\n", __FUNCTION__, status); - } - else - { - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " - Init already done\n")); - } - - return 0; -} - -static void drxk_c_release(struct dvb_frontend* fe) -{ - struct drxk_state *state=fe->demodulator_priv; - printk("%s\n", __FUNCTION__); - kfree(state); -} - -static int drxk_c_init (struct dvb_frontend *fe) -{ - struct drxk_state *state=fe->demodulator_priv; - - if (mutex_trylock(&state->ctlock)==0) - return -EBUSY; - SetOperationMode(state, OM_QAM_ITU_A); - return 0; -} - -static int drxk_c_sleep(struct dvb_frontend* fe) -{ - struct drxk_state *state=fe->demodulator_priv; - - ShutDown(state); - mutex_unlock(&state->ctlock); - return 0; -} - -static int drxk_gate_ctrl(struct dvb_frontend* fe, int enable) -{ - struct drxk_state *state = fe->demodulator_priv; - - //printk("drxk_gate %d\n", enable); - return ConfigureI2CBridge(state, enable ? true : false); -} - -#ifndef USE_API3 -static int drxk_set_parameters (struct dvb_frontend *fe) -#else -static int drxk_set_parameters (struct dvb_frontend *fe, - struct dvb_frontend_parameters *p) -#endif -{ -#ifndef USE_API3 - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - u32 delsys = p->delivery_system, old_delsys; -#endif - struct drxk_state *state = fe->demodulator_priv; - u32 IF; - - //printk("%s\n", __FUNCTION__); - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - if (fe->ops.tuner_ops.set_params) -#ifndef USE_API3 - fe->ops.tuner_ops.set_params(fe); -#else - fe->ops.tuner_ops.set_params(fe, p); -#endif - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); -#ifndef USE_API3 -#else - state->param=*p; -#endif - fe->ops.tuner_ops.get_if_frequency(fe, &IF); /* WTF is a frequency frequency? */ - Start(state, 0, IF); - - //printk("%s IF=%d done\n", __FUNCTION__, IF); - return 0; -} - -static int drxk_c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -{ - //struct drxk_state *state = fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - return 0; -} - -static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct drxk_state *state = fe->demodulator_priv; - u32 stat; - - *status=0; - GetLockStatus(state, &stat, 0); - if (stat==MPEG_LOCK) - *status|=0x1f; - if (stat==FEC_LOCK) - *status|=0x0f; - if (stat==DEMOD_LOCK) - *status|=0x07; - return 0; -} - -static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber) -{ - //struct drxk_state *state = fe->demodulator_priv; - *ber=0; - return 0; -} - -static int drxk_read_signal_strength(struct dvb_frontend *fe, u16 *strength) -{ - struct drxk_state *state = fe->demodulator_priv; - u32 val; - - ReadIFAgc(state, &val); - *strength = val & 0xffff;; - return 0; -} - -static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct drxk_state *state = fe->demodulator_priv; - s32 snr2; - - GetSignalToNoise(state, &snr2); - *snr = snr2&0xffff; - return 0; -} - -static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct drxk_state *state = fe->demodulator_priv; - u16 err; - - DVBTQAMGetAccPktErr(state, &err); - *ucblocks = (u32) err; - return 0; -} - -static int drxk_c_get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *sets) -{ - sets->min_delay_ms=3000; - sets->max_drift=0; - sets->step_size=0; - return 0; -} - -static void drxk_t_release(struct dvb_frontend* fe) -{ - //struct drxk_state *state=fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - //kfree(state); -} - -static int drxk_t_init (struct dvb_frontend *fe) -{ - struct drxk_state *state=fe->demodulator_priv; - if (mutex_trylock(&state->ctlock)==0) - return -EBUSY; - //printk("%s\n", __FUNCTION__); - SetOperationMode(state, OM_DVBT); - //printk("%s done\n", __FUNCTION__); - return 0; -} - -static int drxk_t_sleep(struct dvb_frontend* fe) -{ - struct drxk_state *state=fe->demodulator_priv; - mutex_unlock(&state->ctlock); - return 0; -} - -static int drxk_t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -{ - //struct drxk_state *state = fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - return 0; -} - -static struct dvb_frontend_ops drxk_c_ops = { - .info = { - .name = "DRXK DVB-C", - .type = FE_QAM, - .frequency_stepsize = 62500, - .frequency_min = 47000000, - .frequency_max = 862000000, - .symbol_rate_min = 870000, - .symbol_rate_max = 11700000, - .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | - FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO - }, - .release = drxk_c_release, - .init = drxk_c_init, - .sleep = drxk_c_sleep, - .i2c_gate_ctrl = drxk_gate_ctrl, - - .set_frontend = drxk_set_parameters, - .get_frontend = drxk_c_get_frontend, - .get_tune_settings = drxk_c_get_tune_settings, - - .read_status = drxk_read_status, - .read_ber = drxk_read_ber, - .read_signal_strength = drxk_read_signal_strength, - .read_snr = drxk_read_snr, - .read_ucblocks = drxk_read_ucblocks, -}; - -static struct dvb_frontend_ops drxk_t_ops = { - .info = { - .name = "DRXK DVB-T", - .type = FE_OFDM, - .frequency_min = 47125000, - .frequency_max = 865000000, - .frequency_stepsize = 166667, - .frequency_tolerance = 0, - .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | - FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | - FE_CAN_FEC_AUTO | - FE_CAN_QAM_16 | FE_CAN_QAM_64 | - FE_CAN_QAM_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | - FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | - FE_CAN_MUTE_TS - }, - .release = drxk_t_release, - .init = drxk_t_init, - .sleep = drxk_t_sleep, - .i2c_gate_ctrl = drxk_gate_ctrl, - - .set_frontend = drxk_set_parameters, - .get_frontend = drxk_t_get_frontend, - - .read_status = drxk_read_status, - .read_ber = drxk_read_ber, - .read_signal_strength = drxk_read_signal_strength, - .read_snr = drxk_read_snr, - .read_ucblocks = drxk_read_ucblocks, -}; - -struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, u8 adr, - struct dvb_frontend **fe_t) -{ - struct drxk_state *state = NULL; - - state=kzalloc(sizeof(struct drxk_state), GFP_KERNEL); - if (!state) - return NULL; - - state->i2c=i2c; - state->demod_address=adr; - - mutex_init(&state->mutex); - mutex_init(&state->ctlock); - - memcpy(&state->c_frontend.ops, &drxk_c_ops, sizeof(struct dvb_frontend_ops)); - memcpy(&state->t_frontend.ops, &drxk_t_ops, sizeof(struct dvb_frontend_ops)); - state->c_frontend.demodulator_priv=state; - state->t_frontend.demodulator_priv=state; - - init_state(state); - if (init_drxk(state)<0) - goto error; - *fe_t = &state->t_frontend; - return &state->c_frontend; - -error: - printk("drxk: not found\n"); - kfree(state); - return NULL; -} - -MODULE_DESCRIPTION("DRX-K driver"); -MODULE_AUTHOR("Ralph Metzler"); -MODULE_LICENSE("GPL"); - -EXPORT_SYMBOL(drxk_attach); +/* + * drxk_hard: DRX-K DVB-C/T demodulator driver + * + * Copyright (C) 2010-2011 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "drxk.h" +#include "drxk_hard.h" + +static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); +static int PowerDownQAM(struct drxk_state *state); +static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); +static int SetQAMStandard(struct drxk_state *state,enum OperationMode oMode); +static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, + s32 tunerFreqOffset); +static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); +static int DVBTStart(struct drxk_state *state); +static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, + s32 tunerFreqOffset); +static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); +static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); +static int SwitchAntennaToQAM(struct drxk_state *state); +static int SwitchAntennaToDVBT(struct drxk_state *state); + +static bool IsDVBT(struct drxk_state *state) +{ + return state->m_OperationMode == OM_DVBT; +} + +static bool IsQAM(struct drxk_state *state) +{ + return state->m_OperationMode == OM_QAM_ITU_A || + state->m_OperationMode == OM_QAM_ITU_B || + state->m_OperationMode == OM_QAM_ITU_C; +} + +bool IsA1WithPatchCode(struct drxk_state *state) +{ + return state->m_DRXK_A1_PATCH_CODE; +} + +bool IsA1WithRomCode(struct drxk_state *state) +{ + return state->m_DRXK_A1_ROM_CODE; +} + +#define NOA1ROM 0 + +#ifndef CHK_ERROR + #define CHK_ERROR(s) if ((status = s) < 0) break +#endif + +#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) +#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) + +#define DEFAULT_MER_83 165 +#define DEFAULT_MER_93 250 + +#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH +#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) +#endif + +#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH +#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) +#endif + +#ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH +#define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06) +#endif + +#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 +#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 + +#ifndef DRXK_KI_RAGC_ATV +#define DRXK_KI_RAGC_ATV 4 +#endif +#ifndef DRXK_KI_IAGC_ATV +#define DRXK_KI_IAGC_ATV 6 +#endif +#ifndef DRXK_KI_DAGC_ATV +#define DRXK_KI_DAGC_ATV 7 +#endif + +#ifndef DRXK_KI_RAGC_QAM +#define DRXK_KI_RAGC_QAM 3 +#endif +#ifndef DRXK_KI_IAGC_QAM +#define DRXK_KI_IAGC_QAM 4 +#endif +#ifndef DRXK_KI_DAGC_QAM +#define DRXK_KI_DAGC_QAM 7 +#endif +#ifndef DRXK_KI_RAGC_DVBT +#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) +#endif +#ifndef DRXK_KI_IAGC_DVBT +#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) +#endif +#ifndef DRXK_KI_DAGC_DVBT +#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) +#endif + +#ifndef DRXK_AGC_DAC_OFFSET +#define DRXK_AGC_DAC_OFFSET (0x800) +#endif + +#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ +#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) +#endif + +#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ +#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) +#endif + +#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ +#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) +#endif + +#ifndef DRXK_QAM_SYMBOLRATE_MAX +#define DRXK_QAM_SYMBOLRATE_MAX (7233000) +#endif + +#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 +#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 +#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 +#define DRXK_BL_ROM_OFFSET_TAPS_BG 24 +#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 +#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 +#define DRXK_BL_ROM_OFFSET_TAPS_FM 48 +#define DRXK_BL_ROM_OFFSET_UCODE 0 + +#define DRXK_BLC_TIMEOUT 100 + +#define DRXK_BLCC_NR_ELEMENTS_TAPS 2 +#define DRXK_BLCC_NR_ELEMENTS_UCODE 6 + +#define DRXK_BLDC_NR_ELEMENTS_TAPS 28 + +#ifndef DRXK_OFDM_NE_NOTCH_WIDTH +#define DRXK_OFDM_NE_NOTCH_WIDTH (4) +#endif + +#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) +#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) +#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) +#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) +#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) + +static inline u32 MulDiv32(u32 a, u32 b, u32 c) +{ + u64 tmp64; + + tmp64 = (u64)a * (u64)b; + do_div(tmp64, c); + + return (u32) tmp64; +} + +inline u32 Frac28a(u32 a, u32 c) +{ + int i = 0; + u32 Q1 = 0; + u32 R0 = 0; + + R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ + Q1 = a / c; /* integer part, only the 4 least significant bits + will be visible in the result */ + + /* division using radix 16, 7 nibbles in the result */ + for (i = 0; i < 7; i++) { + Q1 = (Q1 << 4) | (R0 / c); + R0 = (R0 % c) << 4; + } + /* rounding */ + if ((R0 >> 3) >= c) + Q1++; + + return Q1; +} + +static u32 Log10Times100(u32 x) +{ + static const u8 scale = 15; + static const u8 indexWidth = 5; + u8 i = 0; + u32 y = 0; + u32 d = 0; + u32 k = 0; + u32 r = 0; + /* + log2lut[n] = (1< 0; k--) { + if (x & (((u32)1) << scale)) + break; + x <<= 1; + } + } else { + for (k = scale; k < 31 ; k++) { + if ((x & (((u32)(-1)) << (scale+1))) == 0) + break; + x >>= 1; + } + } + /* + Now x has binary point between bit[scale] and bit[scale-1] + and 1.0 <= x < 2.0 */ + + /* correction for divison: log(x) = log(x/y)+log(y) */ + y = k * ((((u32)1) << scale) * 200); + + /* remove integer part */ + x &= ((((u32)1) << scale)-1); + /* get index */ + i = (u8) (x >> (scale - indexWidth)); + /* compute delta (x - a) */ + d = x & ((((u32)1) << (scale - indexWidth)) - 1); + /* compute log, multiplication (d* (..)) must be within range ! */ + y += log2lut[i] + + ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); + /* Conver to log10() */ + y /= 108853; /* (log2(10) << scale) */ + r = (y >> 1); + /* rounding */ + if (y & ((u32)1)) + r++; + return (r); +} + +/****************************************************************************/ +/* I2C **********************************************************************/ +/****************************************************************************/ + +static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val) +{ + struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = 1 }}; + return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; +} + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = + {.addr = adr, .flags = 0, .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { + printk("i2c_write error\n"); + return -1; + } + return 0; +} + +static int i2c_read(struct i2c_adapter *adap, + u8 adr, u8 *msg, int len, u8 *answ, int alen) +{ + struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, + .buf = msg, .len = len}, + { .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) { + printk("i2c_read error\n"); + return -1; + } + return 0; +} + +static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags) +{ + u8 adr=state->demod_address, mm1[4], mm2[2], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm1[0] = (((reg << 1) & 0xFF) | 0x01); + mm1[1] = ((reg >> 16) & 0xFF); + mm1[2] = ((reg >> 24) & 0xFF) | flags; + mm1[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm1[0] = ((reg << 1) & 0xFF); + mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + if (i2c_read(state->i2c, adr, mm1, len, mm2, 2) < 0) + return -1; + if (data) + *data = mm2[0] | (mm2[1] << 8); + return 0; +} + +static int Read16_0(struct drxk_state *state, u32 reg, u16 *data) +{ + return Read16(state, reg, data, 0); +} + +static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags) +{ + u8 adr = state->demod_address, mm1[4], mm2[4], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm1[0] = (((reg << 1) & 0xFF) | 0x01); + mm1[1] = ((reg >> 16) & 0xFF); + mm1[2] = ((reg >> 24) & 0xFF) | flags; + mm1[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm1[0] = ((reg << 1) & 0xFF); + mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + if (i2c_read(state->i2c, adr, mm1, len, mm2, 4) < 0) + return -1; + if (data) + *data = mm2[0] | (mm2[1] << 8) | + (mm2[2] << 16) | (mm2[3] << 24); + return 0; +} + +static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags) +{ + u8 adr = state->demod_address, mm[6], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm[0] = (((reg << 1) & 0xFF) | 0x01); + mm[1] = ((reg >> 16) & 0xFF); + mm[2] = ((reg >> 24) & 0xFF) | flags; + mm[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm[0] = ((reg << 1) & 0xFF); + mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + mm[len] = data & 0xff; + mm[len+1] = (data >>8) & 0xff; + if (i2c_write(state->i2c, adr, mm, len + 2) < 0) + return -1; + return 0; +} + +static int Write16_0(struct drxk_state *state, u32 reg, u16 data) +{ + return Write16(state, reg, data, 0); +} + +static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags) +{ + u8 adr = state->demod_address, mm[8], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm[0] = (((reg << 1) & 0xFF) | 0x01); + mm[1] = ((reg >> 16) & 0xFF); + mm[2] = ((reg >> 24) & 0xFF) | flags; + mm[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm[0] = ((reg << 1) & 0xFF); + mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + mm[len] = data & 0xff; + mm[len+1] = (data >> 8) & 0xff; + mm[len+2] = (data >> 16) & 0xff; + mm[len+3] = (data >> 24) & 0xff; + if (i2c_write(state->i2c, adr, mm, len+4) < 0) + return -1; + return 0; +} + +static int WriteBlock(struct drxk_state *state, u32 Address, + const int BlockSize, const u8 pBlock[], u8 Flags) +{ + int status = 0, BlkSize = BlockSize; +#ifdef I2C_LONG_ADR + Flags |= 0xC0; +#endif + while (BlkSize > 0) { + int Chunk = BlkSize > state->m_ChunkSize ? + state->m_ChunkSize : BlkSize ; + u8 *AdrBuf = &state->Chunk[0]; + u32 AdrLength = 0; + + if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { + AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); + AdrBuf[1] = ((Address >> 16) & 0xFF); + AdrBuf[2] = ((Address >> 24) & 0xFF); + AdrBuf[3] = ((Address >> 7) & 0xFF); + AdrBuf[2] |= Flags; + AdrLength = 4; + if (Chunk == state->m_ChunkSize) + Chunk -= 2; + } else { + AdrBuf[0] = ((Address << 1) & 0xFF); + AdrBuf[1] = (((Address >> 16) & 0x0F) | + ((Address >> 18) & 0xF0)); + AdrLength = 2; + } + memcpy(&state->Chunk[AdrLength], pBlock, Chunk); + status = i2c_write(state->i2c, state->demod_address, + &state->Chunk[0], Chunk+AdrLength); + if (status<0) { + printk("I2C Write error\n"); + break; + } + pBlock += Chunk; + Address += (Chunk >> 1); + BlkSize -= Chunk; + } + return status; +} + +#ifndef DRXK_MAX_RETRIES_POWERUP +#define DRXK_MAX_RETRIES_POWERUP 20 +#endif + +int PowerUpDevice(struct drxk_state *state) +{ + int status; + u8 data = 0; + u16 retryCount = 0; + + status = i2c_read1(state->i2c, state->demod_address, &data); + if (status<0) + do { + data = 0; + if (i2c_write(state->i2c, + state->demod_address, &data, 1) < 0) + printk("powerup failed\n"); + msleep(10); + retryCount++ ; + } while (i2c_read1(state->i2c, + state->demod_address, &data) < 0 && + (retryCount < DRXK_MAX_RETRIES_POWERUP)); + if (retryCount >= DRXK_MAX_RETRIES_POWERUP) + return -1; + do { + /* Make sure all clk domains are active */ + CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, + SIO_CC_PWD_MODE_LEVEL_NONE)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, + SIO_CC_UPDATE_KEY)); + /* Enable pll lock tests */ + CHK_ERROR(Write16_0(state, SIO_CC_PLL_LOCK__A, 1)); + state->m_currentPowerMode = DRX_POWER_UP; + } while (0); + return status; +} + + +static int init_state(struct drxk_state *state) +{ + u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; + u32 ulVSBIfAgcOutputLevel = 0; + u32 ulVSBIfAgcMinLevel = 0; + u32 ulVSBIfAgcMaxLevel = 0x7FFF; + u32 ulVSBIfAgcSpeed = 3; + + u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; + u32 ulVSBRfAgcOutputLevel = 0; + u32 ulVSBRfAgcMinLevel = 0; + u32 ulVSBRfAgcMaxLevel = 0x7FFF; + u32 ulVSBRfAgcSpeed = 3; + u32 ulVSBRfAgcTop = 9500; + u32 ulVSBRfAgcCutOffCurrent = 4000; + + u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; + u32 ulATVIfAgcOutputLevel = 0; + u32 ulATVIfAgcMinLevel = 0; + u32 ulATVIfAgcMaxLevel = 0; + u32 ulATVIfAgcSpeed = 3; + + u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; + u32 ulATVRfAgcOutputLevel = 0; + u32 ulATVRfAgcMinLevel = 0; + u32 ulATVRfAgcMaxLevel = 0; + u32 ulATVRfAgcTop = 9500; + u32 ulATVRfAgcCutOffCurrent = 4000; + u32 ulATVRfAgcSpeed = 3; + + u32 ulQual83 = DEFAULT_MER_83; + u32 ulQual93 = DEFAULT_MER_93; + + u32 ulDVBTStaticTSClock = 1; + u32 ulDVBCStaticTSClock = 1; + + u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; + u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; + + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + u32 ulGPIOCfg = 0x0113; + u32 ulGPIO = 0; + u32 ulSerialMode = 1; + u32 ulInvertTSClock = 0; + u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; + u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH; + u32 ulDVBTBitrate = 50000000; + u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; + + u32 ulInsertRSByte = 0; + + u32 ulRfMirror = 1; + u32 ulPowerDown = 0; + + u32 ulAntennaDVBT = 1; + u32 ulAntennaDVBC = 0; + u32 ulAntennaSwitchDVBTDVBC = 0; + + state->m_hasLNA = false; + state->m_hasDVBT= false; + state->m_hasDVBC= false; + state->m_hasATV= false; + state->m_hasOOB = false; + state->m_hasAudio = false; + + state->m_ChunkSize = 124; + + state->m_oscClockFreq = 0; + state->m_smartAntInverted = false; + state->m_bPDownOpenBridge = false; + + /* real system clock frequency in kHz */ + state->m_sysClockFreq = 151875; + /* Timing div, 250ns/Psys */ + /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ + state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * + HI_I2C_DELAY) / 1000; + /* Clipping */ + if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) + state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; + state->m_HICfgWakeUpKey = (state->demod_address << 1); + /* port/bridge/power down ctrl */ + state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; + + state->m_bPowerDown = (ulPowerDown != 0); + + state->m_DRXK_A1_PATCH_CODE = false; + state->m_DRXK_A1_ROM_CODE = false; + state->m_DRXK_A2_ROM_CODE = false; + state->m_DRXK_A3_ROM_CODE = false; + state->m_DRXK_A2_PATCH_CODE = false; + state->m_DRXK_A3_PATCH_CODE = false; + + /* Init AGC and PGA parameters */ + /* VSB IF */ + state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); + state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); + state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); + state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); + state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); + state->m_vsbPgaCfg = 140; + + /* VSB RF */ + state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); + state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); + state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); + state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); + state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); + state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); + state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); + state->m_vsbPreSawCfg.reference = 0x07; + state->m_vsbPreSawCfg.usePreSaw = true; + + state->m_Quality83percent = DEFAULT_MER_83; + state->m_Quality93percent = DEFAULT_MER_93; + if (ulQual93 <= 500 && ulQual83 < ulQual93) { + state->m_Quality83percent = ulQual83; + state->m_Quality93percent = ulQual93; + } + + /* ATV IF */ + state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); + state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); + state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); + state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); + state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); + + /* ATV RF */ + state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); + state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); + state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); + state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); + state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); + state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); + state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); + state->m_atvPreSawCfg.reference = 0x04; + state->m_atvPreSawCfg.usePreSaw = true; + + + /* DVBT RF */ + state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; + state->m_dvbtRfAgcCfg.outputLevel = 0; + state->m_dvbtRfAgcCfg.minOutputLevel = 0; + state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; + state->m_dvbtRfAgcCfg.top = 0x2100; + state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; + state->m_dvbtRfAgcCfg.speed = 1; + + + /* DVBT IF */ + state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; + state->m_dvbtIfAgcCfg.outputLevel = 0; + state->m_dvbtIfAgcCfg.minOutputLevel = 0; + state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; + state->m_dvbtIfAgcCfg.top = 13424; + state->m_dvbtIfAgcCfg.cutOffCurrent = 0; + state->m_dvbtIfAgcCfg.speed = 3; + state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; + state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; + // state->m_dvbtPgaCfg = 140; + + state->m_dvbtPreSawCfg.reference = 4; + state->m_dvbtPreSawCfg.usePreSaw = false; + + /* QAM RF */ + state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; + state->m_qamRfAgcCfg.outputLevel = 0; + state->m_qamRfAgcCfg.minOutputLevel = 6023; + state->m_qamRfAgcCfg.maxOutputLevel = 27000; + state->m_qamRfAgcCfg.top = 0x2380; + state->m_qamRfAgcCfg.cutOffCurrent = 4000; + state->m_qamRfAgcCfg.speed = 3; + + /* QAM IF */ + state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; + state->m_qamIfAgcCfg.outputLevel = 0; + state->m_qamIfAgcCfg.minOutputLevel = 0; + state->m_qamIfAgcCfg.maxOutputLevel = 9000; + state->m_qamIfAgcCfg.top = 0x0511; + state->m_qamIfAgcCfg.cutOffCurrent = 0; + state->m_qamIfAgcCfg.speed = 3; + state->m_qamIfAgcCfg.IngainTgtMax = 5119; + state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; + + state->m_qamPgaCfg = 140; + state->m_qamPreSawCfg.reference = 4; + state->m_qamPreSawCfg.usePreSaw = false; + + state->m_OperationMode = OM_NONE; + state->m_DrxkState = DRXK_UNINITIALIZED; + + /* MPEG output configuration */ + state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ + state->m_insertRSByte = false; /* If TRUE; insert RS byte */ + state->m_enableParallel = true; /* If TRUE; + parallel out otherwise serial */ + state->m_invertDATA = false; /* If TRUE; invert DATA signals */ + state->m_invertERR = false; /* If TRUE; invert ERR signal */ + state->m_invertSTR = false; /* If TRUE; invert STR signals */ + state->m_invertVAL = false; /* If TRUE; invert VAL signals */ + state->m_invertCLK = + (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ + state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0); + state->m_DVBCStaticCLK = + (ulDVBCStaticTSClock != 0); + /* If TRUE; static MPEG clockrate will be used; + otherwise clockrate will adapt to the bitrate of the TS */ + + state->m_DVBTBitrate = ulDVBTBitrate; + state->m_DVBCBitrate = ulDVBCBitrate; + + state->m_TSDataStrength = (ulTSDataStrength & 0x07); + state->m_TSClockkStrength = (ulTSClockkStrength & 0x07); + + /* Maximum bitrate in b/s in case static clockrate is selected */ + state->m_mpegTsStaticBitrate = 19392658; + state->m_disableTEIhandling = false; + + if (ulInsertRSByte) + state->m_insertRSByte = true; + + state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; + if (ulMpegLockTimeOut < 10000) + state->m_MpegLockTimeOut = ulMpegLockTimeOut; + state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; + if (ulDemodLockTimeOut < 10000) + state->m_DemodLockTimeOut = ulDemodLockTimeOut; + + // QAM defaults + state->m_Constellation = DRX_CONSTELLATION_AUTO; + state->m_qamInterleaveMode = DRXK_QAM_I12_J17; + state->m_fecRsPlen = 204*8; /* fecRsPlen annex A*/ + state->m_fecRsPrescale = 1; + + state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; + state->m_agcFastClipCtrlDelay = 0; + + state->m_GPIOCfg = (ulGPIOCfg); + state->m_GPIO = (ulGPIO == 0 ? 0 : 1); + + state->m_AntennaDVBT = (ulAntennaDVBT == 0 ? 0 : 1); + state->m_AntennaDVBC = (ulAntennaDVBC == 0 ? 0 : 1); + state->m_AntennaSwitchDVBTDVBC = + (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1); + + state->m_bPowerDown = false; + state->m_currentPowerMode = DRX_POWER_DOWN; + + state->m_enableParallel = (ulSerialMode == 0); + + state->m_rfmirror = (ulRfMirror == 0); + state->m_IfAgcPol = false; + return 0; +} + +static int DRXX_Open(struct drxk_state *state) +{ + int status = 0; + u32 jtag = 0; + u16 bid = 0; + u16 key = 0; + + do { + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + /* Check device id */ + CHK_ERROR(Read16(state, SIO_TOP_COMM_KEY__A, &key, 0)); + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, + SIO_TOP_COMM_KEY_KEY)); + CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0)); + CHK_ERROR(Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0)); + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, key)); + } while(0); + return status; +} + +static int GetDeviceCapabilities(struct drxk_state *state) +{ + u16 sioPdrOhwCfg = 0; + u32 sioTopJtagidLo = 0; + int status; + + do { + /* driver 0.9.0 */ + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); + CHK_ERROR(Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0)); + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); + + switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { + case 0: + /* ignore (bypass ?) */ + break; + case 1: + /* 27 MHz */ + state->m_oscClockFreq = 27000; + break; + case 2: + /* 20.25 MHz */ + state->m_oscClockFreq = 20250; + break; + case 3: + /* 4 MHz */ + state->m_oscClockFreq = 20250; + break; + default: + return -1; + } + /* + Determine device capabilities + Based on pinning v14 + */ + CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, + &sioTopJtagidLo, 0)); + /* driver 0.9.0 */ + switch((sioTopJtagidLo >> 29) & 0xF) { + case 0: + state->m_deviceSpin = DRXK_SPIN_A1; + break; + case 2: + state->m_deviceSpin = DRXK_SPIN_A2; + break; + case 3: + state->m_deviceSpin = DRXK_SPIN_A3; + break; + default: + state->m_deviceSpin = DRXK_SPIN_UNKNOWN; + status = -1; + break; + } + switch ((sioTopJtagidLo>>12)&0xFF) { + case 0x13: + /* typeId = DRX3913K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = false; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = false; + state->m_hasGPIO1 = false; + state->m_hasIRQN = false; + break; + case 0x15: + /* typeId = DRX3915K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x16: + /* typeId = DRX3916K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x18: + /* typeId = DRX3918K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x21: + /* typeId = DRX3921K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x23: + /* typeId = DRX3923K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x25: + /* typeId = DRX3925K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x26: + /* typeId = DRX3926K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + default: + printk("DeviceID not supported = %02x\n", + ((sioTopJtagidLo>>12)&0xFF)); + status = -1; + break; + } + } while(0); + return status; +} + +static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) +{ + int status; + bool powerdown_cmd; + + //printk("%s\n", __FUNCTION__); + + /* Write command */ + status = Write16_0(state, SIO_HI_RA_RAM_CMD__A, cmd); + if (status < 0) + return status; + if (cmd == SIO_HI_RA_RAM_CMD_RESET) + msleep(1); + + powerdown_cmd = + (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && + ((state->m_HICfgCtrl) & + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); + if (powerdown_cmd == false) { + /* Wait until command rdy */ + u32 retryCount = 0; + u16 waitCmd; + + do { + msleep(1); + retryCount += 1; + status = Read16(state, SIO_HI_RA_RAM_CMD__A, + &waitCmd, 0); + } while ((status < 0) && + (retryCount < DRXK_MAX_RETRIES) && (waitCmd != 0)); + + if (status == 0) + status = Read16(state, SIO_HI_RA_RAM_RES__A, + pResult, 0); + } + return status; +} + +static int HI_CfgCommand(struct drxk_state *state) +{ + int status; + + mutex_lock(&state->mutex); + do { + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_6__A, + state->m_HICfgTimeout)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_5__A, + state->m_HICfgCtrl)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_4__A, + state->m_HICfgWakeUpKey)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_3__A, + state->m_HICfgBridgeDelay)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_2__A, + state->m_HICfgTimingDiv)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_1__A, + SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); + CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0)); + + state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + } while(0); + mutex_unlock(&state->mutex); + return status; +} + +static int InitHI(struct drxk_state *state) +{ + state->m_HICfgWakeUpKey = (state->demod_address<<1); + state->m_HICfgTimeout = 0x96FF; + /* port/bridge/power down ctrl */ + state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; + return HI_CfgCommand(state); +} + +static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) +{ + int status = -1; + u16 sioPdrMclkCfg = 0; + u16 sioPdrMdxCfg = 0; + + do { + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + /* MPEG TS pad configuration */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); + + if (mpegEnable == false) { + /* Set MPEG TS pads to inputmode */ + CHK_ERROR(Write16_0(state, + SIO_PDR_MSTRT_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, + SIO_PDR_MERR_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, + SIO_PDR_MCLK_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, + SIO_PDR_MVAL_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000)); + } else { + /* Enable MPEG output */ + sioPdrMdxCfg = + ((state->m_TSDataStrength << + SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); + sioPdrMclkCfg = ((state->m_TSClockkStrength << + SIO_PDR_MCLK_CFG_DRIVE__B) | 0x0003); + + CHK_ERROR(Write16_0(state, SIO_PDR_MSTRT_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MERR_CFG__A, + 0x0000)); // Disable + CHK_ERROR(Write16_0(state, SIO_PDR_MVAL_CFG__A, + 0x0000)); // Disable + if (state->m_enableParallel == true) { + /* paralel -> enable MD1 to MD7 */ + CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, + sioPdrMdxCfg)); + } else { + sioPdrMdxCfg = ((state->m_TSDataStrength << + SIO_PDR_MD0_CFG_DRIVE__B) | + 0x0003); + /* serial -> disable MD1 to MD7 */ + CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, + 0x0000)); + } + CHK_ERROR(Write16_0(state, SIO_PDR_MCLK_CFG__A, + sioPdrMclkCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, + sioPdrMdxCfg)); + } + /* Enable MB output over MPEG pads and ctl input */ + CHK_ERROR(Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000)); + /* Write nomagic word to enable pdr reg write */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); + } while(0); + return status; +} + +static int MPEGTSDisable(struct drxk_state *state) +{ + return MPEGTSConfigurePins(state, false); +} + +static int BLChainCmd(struct drxk_state *state, + u16 romOffset, u16 nrOfElements, u32 timeOut) +{ + u16 blStatus = 0; + int status; + unsigned long end; + + mutex_lock(&state->mutex); + do { + CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, + SIO_BL_MODE_CHAIN)); + CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_ADDR__A, + romOffset)); + CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_LEN__A, + nrOfElements)); + CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, + SIO_BL_ENABLE_ON)); + end=jiffies+msecs_to_jiffies(timeOut); + + do { + msleep(1); + CHK_ERROR(Read16(state, SIO_BL_STATUS__A, + &blStatus, 0)); + } while ((blStatus == 0x1) && + ((time_is_after_jiffies(end)))); + if (blStatus == 0x1) { + printk("SIO not ready\n"); + mutex_unlock(&state->mutex); + return -1; + } + } while(0); + mutex_unlock(&state->mutex); + return status; +} + + +static int DownloadMicrocode(struct drxk_state *state, + const u8 pMCImage[], + u32 Length) +{ + const u8 *pSrc = pMCImage; + u16 Flags; + u16 Drain; + u32 Address; + u16 nBlocks; + u16 BlockSize; + u16 BlockCRC; + u32 offset = 0; + u32 i; + int status; + + /* down the drain (we don care about MAGIC_WORD) */ + Drain = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + nBlocks = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + + for (i = 0; i < nBlocks; i += 1) { + Address = (pSrc[0] << 24) | (pSrc[1] << 16) | + (pSrc[2] << 8) | pSrc[3]; + pSrc += sizeof(u32); offset += sizeof(u32); + + BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); + pSrc += sizeof(u16); offset += sizeof(u16); + + Flags = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + + BlockCRC = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + status = WriteBlock(state, Address, BlockSize, pSrc, 0); + if (status<0) + break; + pSrc += BlockSize; + offset += BlockSize; + } + return status; +} + +static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) +{ + int status; + u16 data = 0; + u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; + u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; + unsigned long end; + + if (enable == false) { + desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; + desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; + } + + status = (Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); + + if (data == desiredStatus) { + /* tokenring already has correct status */ + return status; + } + /* Disable/enable dvbt tokenring bridge */ + status = Write16_0(state,SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); + + end=jiffies+msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); + do + CHK_ERROR(Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); + while ((data != desiredStatus) && + ((time_is_after_jiffies(end)))); + if (data != desiredStatus) { + printk("SIO not ready\n"); + return -1; + } + return status; +} + +static int MPEGTSStop(struct drxk_state *state) +{ + int status = 0; + u16 fecOcSncMode = 0; + u16 fecOcIprMode = 0; + + do { + /* Gracefull shutdown (byte boundaries) */ + CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); + fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; + CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); + + /* Suppress MCLK during absence of data */ + CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcIprMode)); + fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; + CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, fecOcIprMode)); + } while (0); + return status; +} + +static int scu_command(struct drxk_state *state, + u16 cmd, u8 parameterLen, + u16 * parameter, u8 resultLen, u16 * result) +{ +#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 +#error DRXK register mapping no longer compatible with this routine! +#endif + u16 curCmd = 0; + int status; + unsigned long end; + + if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || + ((resultLen > 0) && (result == NULL))) + return -1; + + mutex_lock(&state->mutex); + do { + /* assume that the command register is ready + since it is checked afterwards */ + u8 buffer[34]; + int cnt = 0, ii; + + for (ii=parameterLen-1; ii >= 0; ii -= 1) { + buffer[cnt++] = (parameter[ii] & 0xFF); + buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); + } + buffer[cnt++] = (cmd & 0xFF); + buffer[cnt++] = ((cmd >> 8) & 0xFF); + + WriteBlock(state, SCU_RAM_PARAM_0__A - + (parameterLen-1), cnt, buffer, 0x00); + /* Wait until SCU has processed command */ + end=jiffies+msecs_to_jiffies(DRXK_MAX_WAITTIME); + do { + msleep(1); + CHK_ERROR(Read16_0(state, SCU_RAM_COMMAND__A, &curCmd)); + } while (! (curCmd == DRX_SCU_READY) && + (time_is_after_jiffies(end))); + if (curCmd != DRX_SCU_READY) { + printk("SCU not ready\n"); + mutex_unlock(&state->mutex); + return -1; + } + /* read results */ + if ((resultLen > 0) && (result != NULL)) { + s16 err; + int ii; + + for(ii=resultLen-1; ii >= 0; ii -= 1) { + CHK_ERROR(Read16_0(state, + SCU_RAM_PARAM_0__A - ii, + &result[ii])); + } + + /* Check if an error was reported by SCU */ + err = (s16)result[0]; + + /* check a few fixed error codes */ + if (err == SCU_RESULT_UNKSTD) { + printk("SCU_RESULT_UNKSTD\n"); + mutex_unlock(&state->mutex); + return -1; + } else if (err == SCU_RESULT_UNKCMD) { + printk("SCU_RESULT_UNKCMD\n"); + mutex_unlock(&state->mutex); + return -1; + } + /* here it is assumed that negative means error, + and positive no error */ + else if (err < 0) { + printk("%s ERROR\n", __FUNCTION__); + mutex_unlock(&state->mutex); + return -1; + } + } + } while(0); + mutex_unlock(&state->mutex); + if (status<0) + { + printk("%s: status = %d\n", __FUNCTION__, status); + } + + return status; +} + +static int SetIqmAf(struct drxk_state *state, bool active) +{ + u16 data = 0; + int status; + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",active)); + //printk("%s\n", __FUNCTION__); + + do + { + /* Configure IQM */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));; + if (!active) { + data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY + | IQM_AF_STDBY_STDBY_AMP_STANDBY + | IQM_AF_STDBY_STDBY_PD_STANDBY + | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY + | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY + ); + // break; + //default: + // break; + //} + } else /* active */ { + data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) + & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) + & (~IQM_AF_STDBY_STDBY_PD_STANDBY) + & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) + & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) + ); + // break; + //default: + // break; + //} + } + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + }while(0); + return status; +} + +static int CtrlPowerMode(struct drxk_state *state, + pDRXPowerMode_t mode) +{ + int status = 0; + u16 sioCcPwdMode = 0; + + //printk("%s\n", __FUNCTION__); + /* Check arguments */ + if (mode == NULL) + return -1; + + switch (*mode) { + case DRX_POWER_UP: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; + break; + case DRXK_POWER_DOWN_OFDM: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; + break; + case DRXK_POWER_DOWN_CORE: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; + break; + case DRXK_POWER_DOWN_PLL: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; + break; + case DRX_POWER_DOWN: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; + break; + default: + /* Unknow sleep mode */ + return -1; + break; + } + + /* If already in requested power mode, do nothing */ + if (state->m_currentPowerMode == *mode) + return 0; + + /* For next steps make sure to start from DRX_POWER_UP mode */ + if (state->m_currentPowerMode != DRX_POWER_UP) + { + do { + CHK_ERROR(PowerUpDevice(state)); + CHK_ERROR(DVBTEnableOFDMTokenRing(state, true)); + } while(0); + } + + if (*mode == DRX_POWER_UP) { + /* Restore analog & pin configuartion */ + } else { + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected + to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + /* stop all comm_exec */ + /* Stop and power down previous standard */ + do { + switch (state->m_OperationMode) { + case OM_DVBT: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownDVBT(state, false)); + break; + case OM_QAM_ITU_A: + case OM_QAM_ITU_C: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownQAM(state)); + break; + default: + break; + } + CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); + CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, + sioCcPwdMode)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, + SIO_CC_UPDATE_KEY)); + + if (*mode != DRXK_POWER_DOWN_OFDM) { + state->m_HICfgCtrl |= + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + CHK_ERROR(HI_CfgCommand(state)); + } + } while(0); + } + state->m_currentPowerMode = *mode; + return (status); +} + +static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) +{ + DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; + u16 cmdResult = 0; + u16 data = 0; + int status; + + do { + CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); + if (data == SCU_COMM_EXEC_ACTIVE) { + /* Send OFDM stop command */ + CHK_ERROR(scu_command(state, + SCU_RAM_COMMAND_STANDARD_OFDM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP, + 0, NULL, 1, &cmdResult)); + /* Send OFDM reset command */ + CHK_ERROR(scu_command(state, + SCU_RAM_COMMAND_STANDARD_OFDM | + SCU_RAM_COMMAND_CMD_DEMOD_RESET, + 0, NULL, 1, &cmdResult)); + } + + /* Reset datapath for OFDM, processors first */ + CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, + OFDM_SC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, + OFDM_LC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, + IQM_COMM_EXEC_B_STOP)); + + /* powerdown AFE */ + CHK_ERROR(SetIqmAf(state,false)); + + /* powerdown to OFDM mode */ + if (setPowerMode) { + CHK_ERROR(CtrlPowerMode(state,&powerMode)); + } + } while(0); + return status; +} + +static int SetOperationMode(struct drxk_state *state, enum OperationMode oMode) +{ + int status = 0; + + /* + Stop and power down previous standard + TODO investigate total power down instead of partial + power down depending on "previous" standard. + */ + do { + /* disable HW lock indicator */ + CHK_ERROR (Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + if (state->m_OperationMode != oMode) { + switch (state->m_OperationMode) { + // OM_NONE was added for start up + case OM_NONE: + break; + case OM_DVBT: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownDVBT(state,true)); + state->m_OperationMode = OM_NONE; + break; + case OM_QAM_ITU_B: + status = -1; + break; + case OM_QAM_ITU_A: /* fallthrough */ + case OM_QAM_ITU_C: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownQAM(state)); + state->m_OperationMode = OM_NONE; + break; + default: + status = -1; + } + CHK_ERROR(status); + + /* + Power up new standard + */ + switch (oMode) + { + case OM_DVBT: + state->m_OperationMode = oMode; + CHK_ERROR(SetDVBTStandard(state, oMode)); + break; + case OM_QAM_ITU_B: + status = -1; + break; + case OM_QAM_ITU_A: /* fallthrough */ + case OM_QAM_ITU_C: + state->m_OperationMode = oMode; + CHK_ERROR(SetQAMStandard(state,oMode)); + break; + default: + status = -1; + } + } + CHK_ERROR(status); + } while(0); + return 0; +} + +static int Start(struct drxk_state *state, s32 offsetFreq, + s32 IntermediateFrequency) +{ + int status; + + do { + u16 IFreqkHz; + s32 OffsetkHz = offsetFreq / 1000; + + if (state->m_DrxkState != DRXK_STOPPED && + state->m_DrxkState != DRXK_DTV_STARTED) { + status = -1; + break; + } + state->m_bMirrorFreqSpect = +#ifndef USE_API3 + (state->props.inversion == INVERSION_ON); +#else + (state->param.inversion == INVERSION_ON); +#endif + if (IntermediateFrequency < 0) { + state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; + IntermediateFrequency = -IntermediateFrequency; + } + + switch(state->m_OperationMode) { + case OM_QAM_ITU_A: + case OM_QAM_ITU_C: + IFreqkHz = (IntermediateFrequency / 1000); + CHK_ERROR(SetQAM(state,IFreqkHz, OffsetkHz)); + state->m_DrxkState = DRXK_DTV_STARTED; + break; + case OM_DVBT: + IFreqkHz = (IntermediateFrequency / 1000); + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(SetDVBT(state,IFreqkHz, OffsetkHz)); + CHK_ERROR(DVBTStart(state)); + state->m_DrxkState = DRXK_DTV_STARTED; + break; + default: + break; + } + } while(0); + return status; +} + +static int ShutDown(struct drxk_state *state) +{ + MPEGTSStop(state); + return 0; +} + +static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, u32 Time) +{ + int status; + + if (pLockStatus == NULL) + return -1; + + *pLockStatus = NOT_LOCKED; + + /* define the SCU command code */ + switch (state->m_OperationMode) { + case OM_QAM_ITU_A: + case OM_QAM_ITU_B: + case OM_QAM_ITU_C: + status = GetQAMLockStatus(state, pLockStatus); + break; + case OM_DVBT: + status = GetDVBTLockStatus(state, pLockStatus); + break; + default: + break; + } + return status; +} + +static int MPEGTSStart(struct drxk_state *state) +{ + int status = 0; + + u16 fecOcSncMode = 0; + + do { + /* Allow OC to sync again */ + CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); + fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; + CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1)); + } while (0); + return status; +} + +static int MPEGTSDtoInit(struct drxk_state *state) +{ + int status = -1; + + do { + /* Rate integration settings */ + CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000)); + CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C)); + CHK_ERROR(Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A)); + CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008)); + CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4)); + + /* Additional configuration */ + CHK_ERROR(Write16_0(state, FEC_OC_OCR_INVERT__A, 0)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_LWM__A, 2)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_HWM__A, 12)); + } while (0); + return status; +} + +static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode) +{ + int status = -1; + + u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ + u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ + u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ + u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcTmdMode = 0; + u16 fecOcTmdIntUpdRate = 0; + u32 maxBitRate = 0; + bool staticCLK = false; + + do { + /* Check insertion of the Reed-Solomon parity bytes */ + CHK_ERROR(Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode)); + CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, + &fecOcRegIprMode)); + fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); + fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); + if (state->m_insertRSByte == true) { + /* enable parity symbol forward */ + fecOcRegMode |= FEC_OC_MODE_PARITY__M; + /* MVAL disable during parity bytes */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; + /* TS burst length to 204 */ + fecOcDtoBurstLen = 204 ; + } + + /* Check serial or parrallel output */ + fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); + if (state->m_enableParallel == false) { + /* MPEG data output is serial -> set ipr_mode[0] */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; + } + + switch (oMode) { + case OM_DVBT: + maxBitRate = state->m_DVBTBitrate; + fecOcTmdMode = 3; + fecOcRcnCtlRate = 0xC00000; + staticCLK = state->m_DVBTStaticCLK; + break; + case OM_QAM_ITU_A: /* fallthrough */ + case OM_QAM_ITU_C: + fecOcTmdMode = 0x0004; + fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ + maxBitRate = state->m_DVBCBitrate; + staticCLK = state->m_DVBCStaticCLK; + break; + default: + status = -1; + } /* switch (standard) */ + CHK_ERROR(status); + + /* Configure DTO's */ + if (staticCLK ) { + u32 bitRate = 0; + + /* Rational DTO for MCLK source (static MCLK rate), + Dynamic DTO for optimal grouping + (avoid intra-packet gaps), + DTO offset enable to sync TS burst with MSTRT */ + fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | + FEC_OC_DTO_MODE_OFFSET_ENABLE__M); + fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | + FEC_OC_FCT_MODE_VIRT_ENA__M); + + /* Check user defined bitrate */ + bitRate = maxBitRate; + if (bitRate > 75900000UL) + { /* max is 75.9 Mb/s */ + bitRate = 75900000UL; + } + /* Rational DTO period: + dto_period = (Fsys / bitrate) - 2 + + Result should be floored, + to make sure >= requested bitrate + */ + fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) + * 1000) / bitRate); + if (fecOcDtoPeriod <= 2) + fecOcDtoPeriod = 0; + else + fecOcDtoPeriod -= 2; + fecOcTmdIntUpdRate = 8; + } else { + /* (commonAttr->staticCLK == false) => dynamic mode */ + fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; + fecOcFctMode = FEC_OC_FCT_MODE__PRE; + fecOcTmdIntUpdRate = 5; + } + + /* Write appropriate registers with requested configuration */ + CHK_ERROR(Write16_0(state, FEC_OC_DTO_BURST_LEN__A, + fecOcDtoBurstLen)); + CHK_ERROR(Write16_0(state, FEC_OC_DTO_PERIOD__A, + fecOcDtoPeriod)); + CHK_ERROR(Write16_0(state, FEC_OC_DTO_MODE__A, + fecOcDtoMode)); + CHK_ERROR(Write16_0(state, FEC_OC_FCT_MODE__A, + fecOcFctMode)); + CHK_ERROR(Write16_0(state, FEC_OC_MODE__A, + fecOcRegMode)); + CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, + fecOcRegIprMode)); + + /* Rate integration settings */ + CHK_ERROR(Write32(state, FEC_OC_RCN_CTL_RATE_LO__A, + fecOcRcnCtlRate ,0)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A, + fecOcTmdIntUpdRate)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_MODE__A, + fecOcTmdMode)); + } while (0); + return status; +} + +static int MPEGTSConfigurePolarity(struct drxk_state *state) +{ + int status; + u16 fecOcRegIprInvert = 0; + + /* Data mask for the output data byte */ + u16 InvertDataMask = + FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | + FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | + FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | + FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; + + /* Control selective inversion of output bits */ + fecOcRegIprInvert &= (~(InvertDataMask)); + if (state->m_invertDATA == true) + fecOcRegIprInvert |= InvertDataMask; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); + if (state->m_invertERR == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); + if (state->m_invertSTR == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); + if (state->m_invertVAL == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); + if (state->m_invertCLK == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; + status = Write16_0(state,FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); + return status; +} + +#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 + +static int SetAgcRf(struct drxk_state *state, + struct SCfgAgc *pAgcCfg, bool isDTV) +{ + int status = 0; + struct SCfgAgc *pIfAgcSettings; + + if (pAgcCfg == NULL) + return -1; + + do { + u16 data = 0; + + switch (pAgcCfg->ctrlMode) { + case DRXK_AGC_CTRL_AUTO: + + /* Enable RF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); + + CHK_ERROR(Read16(state, SCU_RAM_AGC_CONFIG__A, + &data, 0)); + + /* Enable SCU RF AGC loop */ + data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; + + /* Polarity */ + if (state->m_RfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + + /* Set speed (using complementary reduction value) */ + CHK_ERROR(Read16(state, SCU_RAM_AGC_KI_RED__A, + &data, 0)); + + data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; + data |= (~(pAgcCfg->speed << + SCU_RAM_AGC_KI_RED_RAGC_RED__B) + & SCU_RAM_AGC_KI_RED_RAGC_RED__M); + + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_KI_RED__A, data)); + + if (IsDVBT(state)) + pIfAgcSettings = &state->m_dvbtIfAgcCfg; + else if (IsQAM(state)) + pIfAgcSettings = &state->m_qamIfAgcCfg; + else + pIfAgcSettings = &state->m_atvIfAgcCfg; + if (pIfAgcSettings == NULL) + return -1; + + /* Set TOP, only if IF-AGC is in AUTO mode */ + if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pAgcCfg->top)); + + /* Cut-Off current */ + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_RF_IACCU_HI_CO__A, + pAgcCfg->cutOffCurrent)); + + /* Max. output level */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_MAX__A, + pAgcCfg->maxOutputLevel)); + + break; + + case DRXK_AGC_CTRL_USER: + /* Enable RF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); + + /* Disable SCU RF AGC loop */ + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; + if (state->m_RfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CONFIG__A, + data)); + + /* SCU c.o.c. to 0, enabling full control range */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, + 0)); + + /* Write value to output pin */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, + pAgcCfg->outputLevel)); + break; + + case DRXK_AGC_CTRL_OFF: + /* Disable RF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + /* Disable SCU RF AGC loop */ + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + break; + + default: + return -1; + + } /* switch (agcsettings->ctrlMode) */ + } while(0); + return status; +} + +#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 + +static int SetAgcIf (struct drxk_state *state, + struct SCfgAgc *pAgcCfg, bool isDTV) +{ + u16 data = 0; + int status = 0; + struct SCfgAgc *pRfAgcSettings; + + do { + switch (pAgcCfg->ctrlMode) { + case DRXK_AGC_CTRL_AUTO: + + /* Enable IF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + CHK_ERROR(Read16_0(state, SCU_RAM_AGC_CONFIG__A, + &data)); + + /* Enable SCU IF AGC loop */ + data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; + + /* Polarity */ + if (state->m_IfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + + /* Set speed (using complementary reduction value) */ + CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI_RED__A, + &data)); + data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; + data |= (~(pAgcCfg->speed << + SCU_RAM_AGC_KI_RED_IAGC_RED__B) + & SCU_RAM_AGC_KI_RED_IAGC_RED__M); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_RED__A , + data)); + + if (IsQAM(state)) + pRfAgcSettings = &state->m_qamRfAgcCfg; + else + pRfAgcSettings = &state->m_atvRfAgcCfg; + if (pRfAgcSettings == NULL) + return -1; + /* Restore TOP */ + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pRfAgcSettings->top)); + break; + + case DRXK_AGC_CTRL_USER: + + /* Enable IF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + + /* Disable SCU IF AGC loop */ + data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; + + /* Polarity */ + if (state->m_IfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + + /* Write value to output pin */ + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pAgcCfg->outputLevel)); + break; + + case DRXK_AGC_CTRL_OFF: + + /* Disable If AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + /* Disable SCU IF AGC loop */ + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + break; + } /* switch (agcSettingsIf->ctrlMode) */ + + /* always set the top to support + configurations without if-loop */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, + pAgcCfg->top)); + + + } while(0); + return status; +} + +static int ReadIFAgc(struct drxk_state *state, u32 *pValue) +{ + u16 agcDacLvl; + int status = Read16_0(state, IQM_AF_AGC_IF__A, &agcDacLvl); + + *pValue = 0; + + if (status==0) { + u16 Level = 0; + if (agcDacLvl > DRXK_AGC_DAC_OFFSET) + Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; + if (Level < 14000) + *pValue = (14000 - Level) / 4 ; + else + *pValue = 0; + } + return status; +} + +static int GetQAMSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +{ + int status = 0; + + do { + /* MER calculation */ + u16 qamSlErrPower = 0; /* accum. error between + raw and sliced symbols */ + u32 qamSlSigPower = 0; /* used for MER, depends of + QAM constellation */ + u32 qamSlMer = 0; /* QAM MER */ + + /* get the register value needed for MER */ + CHK_ERROR(Read16_0(state,QAM_SL_ERR_POWER__A, &qamSlErrPower)); + +#ifndef USE_API3 + switch(state->props.modulation) { +#else + switch(state->param.u.qam.modulation) { +#endif + case QAM_16: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; + break; + case QAM_32: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; + break; + case QAM_64: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; + break; + case QAM_128: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; + break; + default: + case QAM_256: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; + break; + } + + if (qamSlErrPower > 0) { + qamSlMer = Log10Times100(qamSlSigPower) - + Log10Times100((u32) qamSlErrPower); + } + *pSignalToNoise = qamSlMer; + } while(0); + return status; +} + +static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +{ + int status = 0; + + u16 regData = 0; + u32 EqRegTdSqrErrI = 0; + u32 EqRegTdSqrErrQ = 0; + u16 EqRegTdSqrErrExp = 0; + u16 EqRegTdTpsPwrOfs = 0; + u16 EqRegTdReqSmbCnt = 0; + u32 tpsCnt = 0; + u32 SqrErrIQ = 0; + u32 a = 0; + u32 b = 0; + u32 c = 0; + u32 iMER = 0; + u16 transmissionParams = 0; + + do { + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, + &EqRegTdTpsPwrOfs)); + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, + &EqRegTdReqSmbCnt)); + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, + &EqRegTdSqrErrExp)); + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, + ®Data)); + /* Extend SQR_ERR_I operational range */ + EqRegTdSqrErrI = (u32) regData; + if ((EqRegTdSqrErrExp > 11) && + (EqRegTdSqrErrI < 0x00000FFFUL)) { + EqRegTdSqrErrI += 0x00010000UL; + } + CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A, + ®Data)); + /* Extend SQR_ERR_Q operational range */ + EqRegTdSqrErrQ = (u32)regData; + if ((EqRegTdSqrErrExp > 11) && + (EqRegTdSqrErrQ < 0x00000FFFUL)) + EqRegTdSqrErrQ += 0x00010000UL; + + CHK_ERROR(Read16_0(state,OFDM_SC_RA_RAM_OP_PARAM__A, + &transmissionParams)); + + /* Check input data for MER */ + + /* MER calculation (in 0.1 dB) without math.h */ + if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) + iMER = 0; + else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { + /* No error at all, this must be the HW reset value + * Apparently no first measurement yet + * Set MER to 0.0 */ + iMER = 0; + } else { + SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << + EqRegTdSqrErrExp; + if ((transmissionParams & + OFDM_SC_RA_RAM_OP_PARAM_MODE__M) + == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) + tpsCnt = 17; + else + tpsCnt = 68; + + /* IMER = 100 * log10 (x) + where x = (EqRegTdTpsPwrOfs^2 * + EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ + + => IMER = a + b -c + where a = 100 * log10 (EqRegTdTpsPwrOfs^2) + b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) + c = 100 * log10 (SqrErrIQ) + */ + + /* log(x) x = 9bits * 9bits->18 bits */ + a = Log10Times100(EqRegTdTpsPwrOfs*EqRegTdTpsPwrOfs); + /* log(x) x = 16bits * 7bits->23 bits */ + b = Log10Times100(EqRegTdReqSmbCnt*tpsCnt); + /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ + c = Log10Times100(SqrErrIQ); + + iMER = a + b; + /* No negative MER, clip to zero */ + if (iMER > c) + iMER -= c; + else + iMER = 0; + } + *pSignalToNoise = iMER; + } while(0); + + return status; +} + +static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +{ + *pSignalToNoise = 0; + switch(state->m_OperationMode) { + case OM_DVBT: + return GetDVBTSignalToNoise(state, pSignalToNoise); + case OM_QAM_ITU_A: + case OM_QAM_ITU_C: + return GetQAMSignalToNoise(state, pSignalToNoise); + default: + break; + } + return 0; +} + +#if 0 +static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) +{ + /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ + int status = 0; + + static s32 QE_SN[] = + { + 51, // QPSK 1/2 + 69, // QPSK 2/3 + 79, // QPSK 3/4 + 89, // QPSK 5/6 + 97, // QPSK 7/8 + 108, // 16-QAM 1/2 + 131, // 16-QAM 2/3 + 146, // 16-QAM 3/4 + 156, // 16-QAM 5/6 + 160, // 16-QAM 7/8 + 165, // 64-QAM 1/2 + 187, // 64-QAM 2/3 + 202, // 64-QAM 3/4 + 216, // 64-QAM 5/6 + 225, // 64-QAM 7/8 + }; + + *pQuality = 0; + + do { + s32 SignalToNoise = 0; + u16 Constellation = 0; + u16 CodeRate = 0; + u32 SignalToNoiseRel; + u32 BERQuality; + + CHK_ERROR(GetDVBTSignalToNoise(state,&SignalToNoise)); + CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CONST__A, + &Constellation)); + Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; + + CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CODE_HP__A, + &CodeRate)); + CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; + + if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || + CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) + break; + SignalToNoiseRel = SignalToNoise - + QE_SN[Constellation * 5 + CodeRate]; + BERQuality = 100; + + if (SignalToNoiseRel < -70) *pQuality = 0; + else if (SignalToNoiseRel < 30) + *pQuality = ((SignalToNoiseRel + 70) * + BERQuality) / 100; + else + *pQuality = BERQuality; + } while(0); + return 0; +}; + +static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) +{ + int status = 0; + *pQuality = 0; + + do { + u32 SignalToNoise = 0; + u32 BERQuality = 100; + u32 SignalToNoiseRel = 0; + + CHK_ERROR(GetQAMSignalToNoise(state, &SignalToNoise)); + +#ifndef USE_API3 + switch(state->props.modulation) { +#else + switch(state->param.u.qam.modulation) { +#endif + case QAM_16: + SignalToNoiseRel = SignalToNoise - 200; + break; + case QAM_32: + SignalToNoiseRel = SignalToNoise - 230; + break; /* Not in NorDig */ + case QAM_64: + SignalToNoiseRel = SignalToNoise - 260; + break; + case QAM_128: + SignalToNoiseRel = SignalToNoise - 290; + break; + default: + case QAM_256: + SignalToNoiseRel = SignalToNoise - 320; + break; + } + + if (SignalToNoiseRel < -70) + *pQuality = 0; + else if (SignalToNoiseRel < 30) + *pQuality = ((SignalToNoiseRel + 70) * + BERQuality) / 100; + else + *pQuality = BERQuality; + } while(0); + + return status; +} + +static int GetQuality(struct drxk_state *state, s32 *pQuality) +{ + switch(state->m_OperationMode) { + case OM_DVBT: + return GetDVBTQuality(state, pQuality); + case OM_QAM_ITU_A: + return GetDVBCQuality(state, pQuality); + default: + break; + } + + return 0; +} +#endif + +/* Free data ram in SIO HI */ +#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 +#define SIO_HI_RA_RAM_USR_END__A 0x420060 + +#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) +#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) +#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ +#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE + +#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) +#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) +#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) + +static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) +{ + int status; + + if (state->m_DrxkState == DRXK_UNINITIALIZED) + return -1; + if (state->m_DrxkState == DRXK_POWERED_DOWN) + return -1; + + do { + CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, + SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); + if (bEnableBridge) { + CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, + SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED)); + } else { + CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, + SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN)); + } + + CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL,0)); + } while(0); + return status; +} + +static int SetPreSaw(struct drxk_state *state, struct SCfgPreSaw *pPreSawCfg) +{ + int status; + + if ((pPreSawCfg == NULL) || (pPreSawCfg->reference>IQM_AF_PDREF__M)) + return -1; + + status = Write16_0(state, IQM_AF_PDREF__A, pPreSawCfg->reference); + return status; +} + +static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, + u16 romOffset, u16 nrOfElements, u32 timeOut) +{ + u16 blStatus = 0; + u16 offset = (u16)((targetAddr >> 0) & 0x00FFFF); + u16 blockbank = (u16)((targetAddr >> 16) & 0x000FFF); + int status ; + unsigned long end; + + mutex_lock(&state->mutex); + do { + CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT)); + CHK_ERROR(Write16_0(state, SIO_BL_TGT_HDR__A, blockbank)); + CHK_ERROR(Write16_0(state, SIO_BL_TGT_ADDR__A, offset)); + CHK_ERROR(Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset)); + CHK_ERROR(Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements)); + CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON)); + + end=jiffies+msecs_to_jiffies(timeOut); + do { + CHK_ERROR(Read16_0(state, SIO_BL_STATUS__A, &blStatus)); + } while ((blStatus == 0x1) && + time_is_after_jiffies(end)); + if (blStatus == 0x1) { + printk("SIO not ready\n"); + mutex_unlock(&state->mutex); + return -1; + } + } while(0); + mutex_unlock(&state->mutex); + return status; + +} + +static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) +{ + u16 data = 0; + int status; + + do { + /* Start measurement */ + CHK_ERROR(Write16_0(state, IQM_AF_COMM_EXEC__A, + IQM_AF_COMM_EXEC_ACTIVE)); + CHK_ERROR(Write16_0(state,IQM_AF_START_LOCK__A, 1)); + + *count = 0; + CHK_ERROR(Read16_0(state,IQM_AF_PHASE0__A, &data)); + if (data == 127) + *count = *count+1; + CHK_ERROR(Read16_0(state,IQM_AF_PHASE1__A, &data)); + if (data == 127) + *count = *count+1; + CHK_ERROR(Read16_0(state,IQM_AF_PHASE2__A, &data)); + if (data == 127) + *count = *count+1; + } while(0); + return status; +} + +static int ADCSynchronization(struct drxk_state *state) +{ + u16 count = 0; + int status; + + do { + CHK_ERROR(ADCSyncMeasurement(state, &count)); + + if (count==1) { + /* Try sampling on a diffrent edge */ + u16 clkNeg = 0; + + CHK_ERROR(Read16_0(state, IQM_AF_CLKNEG__A, &clkNeg)); + if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == + IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { + clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); + clkNeg |= + IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; + } else { + clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); + clkNeg |= + IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; + } + CHK_ERROR(Write16_0(state, IQM_AF_CLKNEG__A, clkNeg)); + CHK_ERROR(ADCSyncMeasurement(state, &count)); + } + + if (count < 2) + status = -1; + } while (0); + return status; +} + +static int SetFrequencyShifter(struct drxk_state *state, + u16 intermediateFreqkHz, + s32 tunerFreqOffset, + bool isDTV) +{ + bool selectPosImage = false; + u32 rfFreqResidual = tunerFreqOffset; + u32 fmFrequencyShift = 0; + bool tunerMirror = !state->m_bMirrorFreqSpect; + u32 adcFreq; + bool adcFlip; + int status; + u32 ifFreqActual; + u32 samplingFrequency = (u32)(state->m_sysClockFreq / 3); + u32 frequencyShift; + bool imageToSelect; + + /* + Program frequency shifter + No need to account for mirroring on RF + */ + if (isDTV) { + if ((state->m_OperationMode == OM_QAM_ITU_A) || + (state->m_OperationMode == OM_QAM_ITU_C) || + (state->m_OperationMode == OM_DVBT)) + selectPosImage = true; + else + selectPosImage = false; + } + if (tunerMirror) + /* tuner doesn't mirror */ + ifFreqActual = intermediateFreqkHz + + rfFreqResidual + fmFrequencyShift; + else + /* tuner mirrors */ + ifFreqActual = intermediateFreqkHz - + rfFreqResidual - fmFrequencyShift; + if (ifFreqActual > samplingFrequency / 2) { + /* adc mirrors */ + adcFreq = samplingFrequency - ifFreqActual; + adcFlip = true; + } else { + /* adc doesn't mirror */ + adcFreq = ifFreqActual; + adcFlip = false; + } + + frequencyShift = adcFreq; + imageToSelect = state->m_rfmirror ^ tunerMirror ^ + adcFlip ^ selectPosImage; + state->m_IqmFsRateOfs = Frac28a((frequencyShift), samplingFrequency); + + if (imageToSelect) + state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; + + /* Program frequency shifter with tuner offset compensation */ + /* frequencyShift += tunerFreqOffset; TODO */ + status = Write32(state, IQM_FS_RATE_OFS_LO__A , + state->m_IqmFsRateOfs, 0); + return status; +} + +static int InitAGC(struct drxk_state *state, bool isDTV) +{ + u16 ingainTgt = 0; + u16 ingainTgtMin = 0; + u16 ingainTgtMax = 0; + u16 clpCyclen = 0; + u16 clpSumMin = 0; + u16 clpDirTo = 0; + u16 snsSumMin = 0; + u16 snsSumMax = 0; + u16 clpSumMax = 0; + u16 snsDirTo = 0; + u16 kiInnergainMin = 0; + u16 ifIaccuHiTgt = 0; + u16 ifIaccuHiTgtMin = 0; + u16 ifIaccuHiTgtMax = 0; + u16 data = 0; + u16 fastClpCtrlDelay = 0; + u16 clpCtrlMode = 0; + int status = 0; + + do { + /* Common settings */ + snsSumMax = 1023; + ifIaccuHiTgtMin = 2047; + clpCyclen = 500; + clpSumMax = 1023; + + if (IsQAM(state)) { + /* Standard specific settings */ + clpSumMin = 8; + clpDirTo = (u16) - 9; + clpCtrlMode = 0; + snsSumMin = 8; + snsDirTo = (u16) - 9; + kiInnergainMin = (u16) - 1030; + } else + status = -1; + CHK_ERROR((status)); + if (IsQAM(state)) { + ifIaccuHiTgtMax = 0x2380; + ifIaccuHiTgt = 0x2380; + ingainTgtMin = 0x0511; + ingainTgt = 0x0511; + ingainTgtMax = 5119; + fastClpCtrlDelay = + state->m_qamIfAgcCfg.FastClipCtrlDelay; + } else { + ifIaccuHiTgtMax = 0x1200; + ifIaccuHiTgt = 0x1200; + ingainTgtMin = 13424; + ingainTgt = 13424; + ingainTgtMax = 30000; + fastClpCtrlDelay = + state->m_dvbtIfAgcCfg.FastClipCtrlDelay; + } + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, + fastClpCtrlDelay)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, + clpCtrlMode)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT__A, + ingainTgt)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, + ingainTgtMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, + ingainTgtMax)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, + ifIaccuHiTgtMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + ifIaccuHiTgtMax)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MAX__A, + clpSumMax)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MAX__A, + snsSumMax)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, + kiInnergainMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, + ifIaccuHiTgt)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCLEN__A, + clpCyclen)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, + 1023)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, + (u16) -1023)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, + 50)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, + 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MIN__A, + clpSumMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MIN__A, + snsSumMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_TO__A, + clpDirTo)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A, + snsDirTo)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500)); + + /* Initialize inner-loop KI gain factors */ + CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI__A, &data)); + if (IsQAM(state)) { + data = 0x0657; + data &= ~SCU_RAM_AGC_KI_RF__M; + data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); + data &= ~SCU_RAM_AGC_KI_IF__M; + data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); + } + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI__A, data)); + } while(0); + return status; +} + +static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 * packetErr) +{ + int status; + + do { + if (packetErr == NULL) { + CHK_ERROR(Write16_0(state, + SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, + 0)); + } else { + CHK_ERROR(Read16_0(state, + SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, + packetErr)); + } + } while (0); + return status; +} + +static int DVBTScCommand(struct drxk_state *state, + u16 cmd, u16 subcmd, + u16 param0, u16 param1, u16 param2, + u16 param3, u16 param4) +{ + u16 curCmd = 0; + u16 errCode = 0; + u16 retryCnt = 0; + u16 scExec = 0; + int status; + + status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &scExec); + if (scExec != 1) { + /* SC is not running */ + return -1; + } + + /* Wait until sc is ready to receive command */ + retryCnt =0; + do { + msleep(1); + status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); + retryCnt++; + } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); + if (retryCnt >= DRXK_MAX_RETRIES) + return -1; + /* Write sub-command */ + switch (cmd) { + /* All commands using sub-cmd */ + case OFDM_SC_RA_RAM_CMD_PROC_START: + case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: + case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: + status = Write16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); + break; + default: + /* Do nothing */ + break; + } /* switch (cmd->cmd) */ + + /* Write needed parameters and the command */ + switch (cmd) { + /* All commands using 5 parameters */ + /* All commands using 4 parameters */ + /* All commands using 3 parameters */ + /* All commands using 2 parameters */ + case OFDM_SC_RA_RAM_CMD_PROC_START: + case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: + case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: + status = Write16_0(state, OFDM_SC_RA_RAM_PARAM1__A, param1); + /* All commands using 1 parameters */ + case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: + case OFDM_SC_RA_RAM_CMD_USER_IO: + status = Write16_0(state, OFDM_SC_RA_RAM_PARAM0__A, param0); + /* All commands using 0 parameters */ + case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: + case OFDM_SC_RA_RAM_CMD_NULL: + /* Write command */ + status = Write16_0(state, OFDM_SC_RA_RAM_CMD__A, cmd); + break; + default: + /* Unknown command */ + return -EINVAL; + } /* switch (cmd->cmd) */ + + /* Wait until sc is ready processing command */ + retryCnt = 0; + do{ + msleep(1); + status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); + retryCnt++; + } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); + if (retryCnt >= DRXK_MAX_RETRIES) + return -1; + + /* Check for illegal cmd */ + status = Read16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); + if (errCode == 0xFFFF) + { + /* illegal command */ + return -EINVAL; + } + + /* Retreive results parameters from SC */ + switch (cmd) { + /* All commands yielding 5 results */ + /* All commands yielding 4 results */ + /* All commands yielding 3 results */ + /* All commands yielding 2 results */ + /* All commands yielding 1 result */ + case OFDM_SC_RA_RAM_CMD_USER_IO: + case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: + status = Read16_0(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); + /* All commands yielding 0 results */ + case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: + case OFDM_SC_RA_RAM_CMD_SET_TIMER: + case OFDM_SC_RA_RAM_CMD_PROC_START: + case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: + case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: + case OFDM_SC_RA_RAM_CMD_NULL: + break; + default: + /* Unknown command */ + return -EINVAL; + break; + } /* switch (cmd->cmd) */ + return status; +} + +static int PowerUpDVBT (struct drxk_state *state) +{ + DRXPowerMode_t powerMode = DRX_POWER_UP; + int status; + + do { + CHK_ERROR(CtrlPowerMode(state, &powerMode)); + } while (0); + return status; +} + +static int DVBTCtrlSetIncEnable (struct drxk_state *state, bool* enabled) +{ + int status; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + if (*enabled == true) + { + status = Write16_0(state, IQM_CF_BYPASSDET__A, 0); + } + else + { + status = Write16_0(state, IQM_CF_BYPASSDET__A, 1); + } + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + #define DEFAULT_FR_THRES_8K 4000 +static int DVBTCtrlSetFrEnable (struct drxk_state *state, bool* enabled) +{ + + int status; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + if (*enabled == true) + { + /* write mask to 1 */ + status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, + DEFAULT_FR_THRES_8K); + } + else + { + /* write mask to 0 */ + status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); + } + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + +static int DVBTCtrlSetEchoThreshold (struct drxk_state *state, + struct DRXKCfgDvbtEchoThres_t* echoThres) +{ + u16 data = 0; + int status; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + do { + CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data)); + + switch (echoThres->fftMode) + { + case DRX_FFTMODE_2K: + data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_2K__M; + data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_2K__B) & + (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); + break; + case DRX_FFTMODE_8K: + data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_8K__M; + data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_8K__B) & + (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); + break; + default: + return -1; + break; + } + + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data)); + } while (0); + + if (status<0) + { + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + +static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, + enum DRXKCfgDvbtSqiSpeed* speed) +{ + int status; + + switch (*speed) { + case DRXK_DVBT_SQI_SPEED_FAST: + case DRXK_DVBT_SQI_SPEED_MEDIUM: + case DRXK_DVBT_SQI_SPEED_SLOW: + break; + default: + return -EINVAL; + } + status = Write16_0 (state,SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, + (u16) *speed); + return status; +} + +/*============================================================================*/ + +/** +* \brief Activate DVBT specific presets +* \param demod instance of demodulator. +* \return DRXStatus_t. +* +* Called in DVBTSetStandard +* +*/ +static int DVBTActivatePresets (struct drxk_state *state) +{ + int status; + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + struct DRXKCfgDvbtEchoThres_t echoThres2k = {0, DRX_FFTMODE_2K}; + struct DRXKCfgDvbtEchoThres_t echoThres8k = {0, DRX_FFTMODE_8K}; + + do { + bool setincenable = false; + bool setfrenable = true; + CHK_ERROR(DVBTCtrlSetIncEnable (state, &setincenable)); + CHK_ERROR(DVBTCtrlSetFrEnable (state, &setfrenable)); + CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres2k)); + CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres8k)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, + state->m_dvbtIfAgcCfg.IngainTgtMax)); + } while (0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} +/*============================================================================*/ + +/** +* \brief Initialize channelswitch-independent settings for DVBT. +* \param demod instance of demodulator. +* \return DRXStatus_t. +* +* For ROM code channel filter taps are loaded from the bootloader. For microcode +* the DVB-T taps from the drxk_filters.h are used. +*/ +static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode) +{ + u16 cmdResult = 0; + u16 data = 0; + int status; + + //printk("%s\n", __FUNCTION__); + + PowerUpDVBT(state); + + do { + /* added antenna switch */ + SwitchAntennaToDVBT(state); + /* send OFDM reset command */ + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); + + /* send OFDM setenv command */ + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,0,NULL,1,&cmdResult)); + + /* reset datapath for OFDM, processors first */ + CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP )); + + /* IQM setup */ + /* synchronize on ofdstate->m_festart */ + CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 1)); + /* window size for clipping ADC detection */ + CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); + /* window size for for sense pre-SAW detection */ + CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); + /* sense threshold for sense pre-SAW detection */ + CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); + CHK_ERROR(SetIqmAf(state,true)); + + CHK_ERROR(Write16_0(state, IQM_AF_AGC_RF__A, 0)); + + /* Impulse noise cruncher setup */ + CHK_ERROR(Write16_0(state, IQM_AF_INC_LCT__A, 0)); /* crunch in IQM_CF */ + CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); /* detect in IQM_CF */ + CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 3)); /* peak detector window length */ + + CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 16)); + CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 0x4)); /* enable output 2 */ + CHK_ERROR(Write16_0(state, IQM_CF_DS_ENA__A, 0x4)); /* decimate output 2 */ + CHK_ERROR(Write16_0(state, IQM_CF_SCALE__A, 1600)); + CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, 0)); + + /* virtual clipping threshold for clipping ADC detection */ + CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); + CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 495)); /* crunching threshold */ + + CHK_ERROR(BLChainCmd(state, + DRXK_BL_ROM_OFFSET_TAPS_DVBT, + DRXK_BLCC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + + CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 2)); /* peak detector threshold */ + CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2)); + /* enable power measurement interrupt */ + CHK_ERROR(Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); + + /* IQM will not be reset from here, sync ADC and update/init AGC */ + CHK_ERROR(ADCSynchronization(state)); + CHK_ERROR(SetPreSaw(state, &state->m_dvbtPreSawCfg)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + CHK_ERROR(SetAgcRf(state, &state->m_dvbtRfAgcCfg, true)) ; + CHK_ERROR(SetAgcIf (state, &state->m_dvbtIfAgcCfg, true)); + + /* Set Noise Estimation notch width and enable DC fix */ + CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_CONFIG__A, &data)); + data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_CONFIG__A, data)); + + /* Activate SCU to enable SCU commands */ + CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + + if (!state->m_DRXK_A3_ROM_CODE) + { + /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, + state->m_dvbtIfAgcCfg.FastClipCtrlDelay)); + } + + /* OFDM_SC setup */ +#ifdef COMPILE_FOR_NONRT + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2)); +#endif + + /* FEC setup */ + CHK_ERROR(Write16_0(state, FEC_DI_INPUT_CTL__A, 1)); /* OFDM input */ + + +#ifdef COMPILE_FOR_NONRT + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x400)); +#else + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x1000)); +#endif + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A , 0x0001)); + + /* Setup MPEG bus */ + CHK_ERROR(MPEGTSDtoSetup (state,OM_DVBT)); + /* Set DVBT Presets */ + CHK_ERROR (DVBTActivatePresets (state)); + + } while (0); + + if (status<0) + { + printk("%s status - %08x\n",__FUNCTION__,status); + } + + return status; +} + +/*============================================================================*/ +/** +* \brief Start dvbt demodulating for channel. +* \param demod instance of demodulator. +* \return DRXStatus_t. +*/ +static int DVBTStart(struct drxk_state *state) +{ + u16 param1; + + int status; +// DRXKOfdmScCmd_t scCmd; + + //printk("%s\n",__FUNCTION__); + /* Start correct processes to get in lock */ + /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ + do { + param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; + CHK_ERROR(DVBTScCommand(state,OFDM_SC_RA_RAM_CMD_PROC_START,0,OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M,param1,0,0,0)); + /* Start FEC OC */ + CHK_ERROR(MPEGTSStart(state)); + CHK_ERROR(Write16_0(state,FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); + } while (0); + return (status); +} + + +/*============================================================================*/ + +/** +* \brief Set up dvbt demodulator for channel. +* \param demod instance of demodulator. +* \return DRXStatus_t. +* // original DVBTSetChannel() +*/ +static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) +{ + u16 cmdResult = 0; + u16 transmissionParams = 0; + u16 operationMode = 0; + u32 iqmRcRateOfs = 0; + u32 bandwidth = 0; + u16 param1; + int status; + + //printk("%s IF =%d, TFO = %d\n",__FUNCTION__,IntermediateFreqkHz,tunerFreqOffset); + do { + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP, + 0,NULL,1,&cmdResult)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + /* Stop processors */ + CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); + + /* Mandatory fix, always stop CP, required to set spl offset back to + hardware default (is set to 0 by ucode during pilot detection */ + CHK_ERROR(Write16_0(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP)); + + /*== Write channel settings to device =====================================*/ + + /* mode */ +#ifndef USE_API3 + switch(state->props.transmission_mode) { +#else + switch(state->param.u.ofdm.transmission_mode) { +#endif + case TRANSMISSION_MODE_AUTO: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; + /* fall through , try first guess DRX_FFTMODE_8K */ + case TRANSMISSION_MODE_8K: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; + break; + case TRANSMISSION_MODE_2K: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; + break; + } + + /* guard */ +#ifndef USE_API3 + switch(state->props.guard_interval) { +#else + switch(state->param.u.ofdm.guard_interval) { +#endif + default: + case GUARD_INTERVAL_AUTO: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; + /* fall through , try first guess DRX_GUARD_1DIV4 */ + case GUARD_INTERVAL_1_4: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; + break; + case GUARD_INTERVAL_1_32: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; + break; + case GUARD_INTERVAL_1_16: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; + break; + case GUARD_INTERVAL_1_8: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; + break; + } + + /* hierarchy */ +#ifndef USE_API3 + switch(state->props.hierarchy) { +#else + switch(state->param.u.ofdm.hierarchy_information) { +#endif + case HIERARCHY_AUTO: + case HIERARCHY_NONE: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; + /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ + // transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; + //break; + case HIERARCHY_1: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; + break; + case HIERARCHY_2: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; + break; + case HIERARCHY_4: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; + break; + } + + + /* constellation */ +#ifndef USE_API3 + switch(state->props.modulation) { +#else + switch(state->param.u.ofdm.constellation) { +#endif + case QAM_AUTO: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; + /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ + case QAM_64: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; + break; + case QPSK: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; + break; + case QAM_16: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; + break; + } +#if 0 + // No hierachical channels support in BDA + /* Priority (only for hierarchical channels) */ + switch (channel->priority) { + case DRX_PRIORITY_LOW : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; + WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_LO); + break; + case DRX_PRIORITY_HIGH : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; + WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); + break; + case DRX_PRIORITY_UNKNOWN : /* fall through */ + default: + return (DRX_STS_INVALID_ARG); + break; + } +#else + // Set Priorty high + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; + CHK_ERROR(Write16_0(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); +#endif + + /* coderate */ +#ifndef USE_API3 + switch(state->props.code_rate_HP) { +#else + switch(state->param.u.ofdm.code_rate_HP) { +#endif + case FEC_AUTO: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; + /* fall through , try first guess DRX_CODERATE_2DIV3 */ + case FEC_2_3 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; + break; + case FEC_1_2 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; + break; + case FEC_3_4 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; + break; + case FEC_5_6 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; + break; + case FEC_7_8 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; + break; + } + + /* SAW filter selection: normaly not necesarry, but if wanted + the application can select a SAW filter via the driver by using UIOs */ + /* First determine real bandwidth (Hz) */ + /* Also set delay for impulse noise cruncher */ + /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed + by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC + functions */ +#ifndef USE_API3 + switch(state->props.bandwidth_hz) { +#else + switch(state->param.u.ofdm.bandwidth) { +#endif +#ifndef USE_API3 + case 0: + case 8000000: +#else + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: +#endif + bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052)); + /* cochannel protection for PAL 8 MHz */ + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); + break; +#ifndef USE_API3 + case 7000000: +#else + case BANDWIDTH_7_MHZ: +#endif + bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491)); + /* cochannel protection for PAL 7 MHz */ + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); + break; +#ifndef USE_API3 + case 6000000: +#else + case BANDWIDTH_6_MHZ: +#endif + bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073)); + /* cochannel protection for NTSC 6 MHz */ + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); + break; + } + + if (iqmRcRateOfs == 0) + { + /* Now compute IQM_RC_RATE_OFS + (((SysFreq/BandWidth)/2)/2) -1) * 2^23) + => + ((SysFreq / BandWidth) * (2^21)) - (2^23) + */ + /* (SysFreq / BandWidth) * (2^28) */ + /* assert (MAX(sysClk)/MIN(bandwidth) < 16) + => assert(MAX(sysClk) < 16*MIN(bandwidth)) + => assert(109714272 > 48000000) = true so Frac 28 can be used */ + iqmRcRateOfs = Frac28a((u32)((state->m_sysClockFreq * 1000)/3), bandwidth); + /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ + if ((iqmRcRateOfs & 0x7fL) >= 0x40) + { + iqmRcRateOfs += 0x80L; + } + iqmRcRateOfs = iqmRcRateOfs >> 7 ; + /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ + iqmRcRateOfs = iqmRcRateOfs - (1<<23); + } + + iqmRcRateOfs &= ((((u32)IQM_RC_RATE_OFS_HI__M)<m_DRXK_A3_ROM_CODE) + CHK_ERROR (DVBTCtrlSetSqiSpeed(state,&state->m_sqiSpeed)); + + } while(0); + if (status<0) { + //printk("%s status - %08x\n",__FUNCTION__,status); + } + + return status; +} + + +/*============================================================================*/ + +/** +* \brief Retreive lock status . +* \param demod Pointer to demodulator instance. +* \param lockStat Pointer to lock status structure. +* \return DRXStatus_t. +* +*/ +static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) +{ + int status; + const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | + OFDM_SC_RA_RAM_LOCK_FEC__M ); + const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); + const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M ; + + u16 ScRaRamLock = 0; + u16 ScCommExec = 0; + + /* driver 0.9.0 */ + /* Check if SC is running */ + status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); + if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) + { + /* SC not active; return DRX_NOT_LOCKED */ + *pLockStatus = NOT_LOCKED; + return status; + } + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + status = Read16_0(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "RamLock: %04X\n",ScRaRamLock)); + + if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { + *pLockStatus = MPEG_LOCK; + } else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) { + *pLockStatus = FEC_LOCK; + } else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) { + *pLockStatus = DEMOD_LOCK; + } else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) { + *pLockStatus = NEVER_LOCK; + } else { + *pLockStatus = NOT_LOCKED; + } + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + +static int PowerUpQAM (struct drxk_state *state) +{ + DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; + + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + CHK_ERROR(CtrlPowerMode(state, &powerMode)); + + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + + +/// Power Down QAM +static int PowerDownQAM(struct drxk_state *state) +{ + u16 data = 0; + u16 cmdResult; + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); + if (data == SCU_COMM_EXEC_ACTIVE) + { + /* + STOP demodulator + QAM and HW blocks + */ + /* stop all comstate->m_exec */ + CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP,0,NULL,1,&cmdResult)); + } + /* powerdown AFE */ + CHK_ERROR(SetIqmAf(state, false)); + } + while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} +/*============================================================================*/ + +/** +* \brief Setup of the QAM Measurement intervals for signal quality +* \param demod instance of demod. +* \param constellation current constellation. +* \return DRXStatus_t. +* +* NOTE: +* Take into account that for certain settings the errorcounters can overflow. +* The implementation does not check this. +* +*/ +static int SetQAMMeasurement(struct drxk_state *state, + enum EDrxkConstellation constellation, + u32 symbolRate) +{ + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ "(%d,%d) om = %d\n", constellation, symbolRate,state->m_OperationMode)); + + u32 fecBitsDesired = 0; /* BER accounting period */ + u32 fecRsPeriodTotal = 0; /* Total period */ + u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ + int status = 0; + + fecRsPrescale = 1; + + do { + + /* fecBitsDesired = symbolRate [kHz] * + FrameLenght [ms] * + (constellation + 1) * + SyncLoss (== 1) * + ViterbiLoss (==1) + */ + switch (constellation) + { + case DRX_CONSTELLATION_QAM16: + fecBitsDesired = 4 * symbolRate; + break; + case DRX_CONSTELLATION_QAM32: + fecBitsDesired = 5 * symbolRate; + break; + case DRX_CONSTELLATION_QAM64: + fecBitsDesired = 6 * symbolRate; + break; + case DRX_CONSTELLATION_QAM128: + fecBitsDesired = 7 * symbolRate; + break; + case DRX_CONSTELLATION_QAM256: + fecBitsDesired = 8 * symbolRate; + break; + default: + status = -EINVAL; + } + CHK_ERROR(status); + + fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ + fecBitsDesired *= 500; /* meas. period [ms] */ + + /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ + /* fecRsPeriodTotal = fecBitsDesired / 1632 */ + fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil*/ + + /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ + fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); + if (fecRsPrescale == 0) { + /* Divide by zero (though impossible) */ + status = -1; + } + CHK_ERROR(status); + fecRsPeriod = ((u16) fecRsPeriodTotal + (fecRsPrescale >> 1)) / + fecRsPrescale; + + /* write corresponding registers */ + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod)); + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod)); + + } while (0); + + if (status<0) { + printk("%s: status - %08x\n",__FUNCTION__,status); + } + return status; +} + +static int SetQAM16 (struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517)); + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16)); + + /* QAM Loop Controller Coeficients */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)-127)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM32 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM32 (struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM64 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM64 (struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM128 specific setup +* \param demod: instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM128(struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + + /* QAM Slicer Settings */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM128)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM256 specific setup +* \param demod: instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM256(struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM256)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + + +/*============================================================================*/ +/** +* \brief Reset QAM block. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ +static int QAMResetQAM(struct drxk_state *state) +{ + int status; + u16 cmdResult; + + //printk("%s\n", __FUNCTION__); + do + { + /* Stop QAM comstate->m_exec */ + CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); + + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); + } while (0); + + /* All done, all OK */ + return status; +} + +/*============================================================================*/ + +/** +* \brief Set QAM symbolrate. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ +static int QAMSetSymbolrate(struct drxk_state *state) +{ + u32 adcFrequency = 0; + u32 symbFreq = 0; + u32 iqmRcRate = 0; + u16 ratesel = 0; + u32 lcSymbRate = 0; + int status; + u32 srate = +#ifndef USE_API3 + state->props.symbol_rate; +#else + state->param.u.qam.symbol_rate; +#endif + + do + { + /* Select & calculate correct IQM rate */ + adcFrequency = (state->m_sysClockFreq * 1000) / 3; + ratesel = 0; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " state->m_SymbolRate = %d\n",state->m_SymbolRate)); + //printk("SR %d\n", state->param.u.qam.symbol_rate); + if (srate <= 1188750) + { + ratesel = 3; + } + else if (srate <= 2377500) + { + ratesel = 2; + } + else if (srate <= 4755000) + { + ratesel = 1; + } + CHK_ERROR(Write16_0(state,IQM_FD_RATESEL__A, ratesel)); + + /* + IqmRcRate = ((Fadc / (symbolrate * (4<> 7) - + (1 << 23); + CHK_ERROR(Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate,0)); + state->m_iqmRcRate = iqmRcRate; + /* + LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) + */ + symbFreq = srate; + if (adcFrequency == 0) + { + /* Divide by zero */ + return -1; + } + lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + + (Frac28a((symbFreq % adcFrequency), adcFrequency) >> 16); + if (lcSymbRate > 511) + { + lcSymbRate = 511; + } + CHK_ERROR(Write16_0(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate)); + } while (0); + + return status; +} + +/*============================================================================*/ + +/** +* \brief Get QAM lock status. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ + +static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) +{ + int status; + u16 Result[2] = {0,0}; + + status = scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM|SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, Result); + if (status<0) + { + printk("%s status = %08x\n",__FUNCTION__,status); + } + if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) + { + /* 0x0000 NOT LOCKED */ + *pLockStatus = NOT_LOCKED; + } + else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) + { + /* 0x4000 DEMOD LOCKED */ + *pLockStatus = DEMOD_LOCK; + } + else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) + { + /* 0x8000 DEMOD + FEC LOCKED (system lock) */ + *pLockStatus = MPEG_LOCK; + } + else + { + /* 0xC000 NEVER LOCKED */ + /* (system will never be able to lock to the signal) */ + /* TODO: check this, intermediate & standard specific lock states are not + taken into account here */ + *pLockStatus = NEVER_LOCK; + } + return status; +} + +#define QAM_MIRROR__M 0x03 +#define QAM_MIRROR_NORMAL 0x00 +#define QAM_MIRRORED 0x01 +#define QAM_MIRROR_AUTO_ON 0x02 +#define QAM_LOCKRANGE__M 0x10 +#define QAM_LOCKRANGE_NORMAL 0x10 + +static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + u8 parameterLen; + u16 setEnvParameters[5]; + u16 setParamParameters[4]={0,0,0,0}; + u16 cmdResult; + + //printk("%s\n", __FUNCTION__); + + do { + /* + STEP 1: reset demodulator + resets FEC DI and FEC RS + resets QAM block + resets SCU variables + */ + CHK_ERROR(Write16_0(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP)); + CHK_ERROR(QAMResetQAM(state)); + + /* + STEP 2: configure demodulator + -set env + -set params; resets IQM,QAM,FEC HW; initializes some SCU variables + */ + CHK_ERROR(QAMSetSymbolrate(state)); + + /* Env parameters */ + setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */ + if (state->m_OperationMode == OM_QAM_ITU_C) + { + setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */ + } + setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); +// check for LOCKRANGE Extented + // setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; + parameterLen = 4; + + /* Set params */ +#ifndef USE_API3 + switch(state->props.modulation) +#else + switch(state->param.u.qam.modulation) +#endif + { + case QAM_256: + state->m_Constellation = DRX_CONSTELLATION_QAM256; + break; + case QAM_AUTO: + case QAM_64: + state->m_Constellation = DRX_CONSTELLATION_QAM64; + break; + case QAM_16: + state->m_Constellation = DRX_CONSTELLATION_QAM16; + break; + case QAM_32: + state->m_Constellation = DRX_CONSTELLATION_QAM32; + break; + case QAM_128: + state->m_Constellation = DRX_CONSTELLATION_QAM128; + break; + default: + status = -EINVAL; + break; + } + CHK_ERROR(status); + setParamParameters[0] = state->m_Constellation; /* constellation */ + setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ + + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,4,setParamParameters,1,&cmdResult)); + + + /* STEP 3: enable the system in a mode where the ADC provides valid signal + setup constellation independent registers */ +// CHK_ERROR (SetFrequency (channel, tunerFreqOffset)); + CHK_ERROR (SetFrequencyShifter (state, IntermediateFreqkHz, tunerFreqOffset, true)); + + /* Setup BER measurement */ + CHK_ERROR(SetQAMMeasurement (state, + state->m_Constellation, +#ifndef USE_API3 + state->props.symbol_rate)); +#else + state->param.u.qam.symbol_rate)); +#endif + + /* Reset default values */ + CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE)); + CHK_ERROR(Write16_0(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE)); + + /* Reset default LC values */ + CHK_ERROR(Write16_0(state, QAM_LC_RATE_LIMIT__A, 3)); + CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORP__A, 4)); + CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORI__A, 4)); + CHK_ERROR(Write16_0(state, QAM_LC_MODE__A, 7)); + + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB0__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB1__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB2__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB3__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB4__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB5__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB6__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB8__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB9__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB10__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB12__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB15__A, 3)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB16__A, 3)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB20__A, 4)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB25__A, 4)); + + /* Mirroring, QAM-block starting point not inverted */ + CHK_ERROR(Write16_0(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + /* STEP 4: constellation specific setup */ +#ifndef USE_API3 + switch (state->props.modulation) +#else + switch (state->param.u.qam.modulation) +#endif + { + case QAM_16: + CHK_ERROR(SetQAM16(state)); + break; + case QAM_32: + CHK_ERROR(SetQAM32(state)); + break; + case QAM_AUTO: + case QAM_64: + CHK_ERROR(SetQAM64(state)); + break; + case QAM_128: + CHK_ERROR(SetQAM128(state)); + break; + case QAM_256: + //printk("SETQAM256\n"); + CHK_ERROR(SetQAM256(state)); + break; + default: + return -1; + break; + } /* switch */ + /* Activate SCU to enable SCU commands */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + + + /* Re-configure MPEG output, requires knowledge of channel bitrate */ +// extAttr->currentChannel.constellation = channel->constellation; +// extAttr->currentChannel.symbolrate = channel->symbolrate; + CHK_ERROR(MPEGTSDtoSetup(state, state->m_OperationMode)); + + /* Start processes */ + CHK_ERROR(MPEGTSStart(state)); + CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); + CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); + + /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_START,0, + NULL,1,&cmdResult)); + + /* update global DRXK data container */ +//? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; + + /* All done, all OK */ + } while(0); + + if (status<0) { + printk("%s %d\n", __FUNCTION__, status); + } + return status; +} + +static int SetQAMStandard(struct drxk_state *state, enum OperationMode oMode) +{ +#ifdef DRXK_QAM_TAPS +#define DRXK_QAMA_TAPS_SELECT +#include "drxk_filters.h" +#undef DRXK_QAMA_TAPS_SELECT +#else + int status; +#endif + + //printk("%s\n", __FUNCTION__); + do + { + /* added antenna switch */ + SwitchAntennaToQAM(state); + + /* Ensure correct power-up mode */ + CHK_ERROR(PowerUpQAM(state)); + /* Reset QAM block */ + CHK_ERROR(QAMResetQAM(state)); + + /* Setup IQM */ + + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP)); + CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); + + /* Upload IQM Channel Filter settings by + boot loader from ROM table */ + switch (oMode) + { + case OM_QAM_ITU_A: + CHK_ERROR(BLChainCmd(state, + DRXK_BL_ROM_OFFSET_TAPS_ITU_A, + DRXK_BLCC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + break; + case OM_QAM_ITU_C: + CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_RE0__A, + DRXK_BL_ROM_OFFSET_TAPS_ITU_C, + DRXK_BLDC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_IM0__A, + DRXK_BL_ROM_OFFSET_TAPS_ITU_C, + DRXK_BLDC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + break; + default: + status=-EINVAL; + } + CHK_ERROR (status); + + CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, + (1 << IQM_CF_OUT_ENA_QAM__B))); + CHK_ERROR(Write16_0(state, IQM_CF_SYMMETRIC__A, 0)); + CHK_ERROR(Write16_0(state, IQM_CF_MIDTAP__A, + ((1 << IQM_CF_MIDTAP_RE__B) | + (1 << IQM_CF_MIDTAP_IM__B)))); + + CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 21)); + CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); + CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); + CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); + CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0)); + + CHK_ERROR(Write16_0(state, IQM_FS_ADJ_SEL__A, 1)); + CHK_ERROR(Write16_0(state, IQM_RC_ADJ_SEL__A, 1)); + CHK_ERROR(Write16_0(state, IQM_CF_ADJ_SEL__A, 1)); + CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 0)); + + /* IQM Impulse Noise Processing Unit */ + CHK_ERROR(Write16_0(state, IQM_CF_CLP_VAL__A, 500)); + CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 1000)); + CHK_ERROR(Write16_0(state, IQM_CF_BYPASSDET__A, 1)); + CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); + CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 1)); + CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 1)); + CHK_ERROR(Write16_0(state, IQM_AF_INC_BYPASS__A, 1)); + + /* turn on IQMAF. Must be done before setAgc**() */ + CHK_ERROR(SetIqmAf(state, true)); + CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 0x01)); + + /* IQM will not be reset from here, sync ADC and update/init AGC */ + CHK_ERROR(ADCSynchronization (state)); + + /* Set the FSM step period */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + /* No more resets of the IQM, current standard correctly set => + now AGCs can be configured. */ + + CHK_ERROR(InitAGC(state,true)); + CHK_ERROR(SetPreSaw(state, &(state->m_qamPreSawCfg))); + + /* Configure AGC's */ + CHK_ERROR(SetAgcRf(state, &(state->m_qamRfAgcCfg), true)); + CHK_ERROR(SetAgcIf (state, &(state->m_qamIfAgcCfg), true)); + + /* Activate SCU to enable SCU commands */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + } while (0); + return status; +} + +static int WriteGPIO(struct drxk_state *state) +{ + int status; + u16 value = 0; + + do { + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + /* Write magic word to enable pdr reg write */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, + SIO_TOP_COMM_KEY_KEY)); + + if (state->m_hasSAWSW) { + /* write to io pad configuration register - output mode */ + CHK_ERROR(Write16_0(state, SIO_PDR_SMA_TX_CFG__A, + state->m_GPIOCfg)); + + /* use corresponding bit in io data output registar */ + CHK_ERROR(Read16_0(state, SIO_PDR_UIO_OUT_LO__A, &value)); + if (state->m_GPIO == 0) { + value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ + } else { + value |= 0x8000; /* write one to 15th bit - 1st UIO */ + } + /* write back to io data output register */ + CHK_ERROR(Write16_0(state, SIO_PDR_UIO_OUT_LO__A, value)); + + } + /* Write magic word to disable pdr reg write */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); + } while (0); + return status; +} + +static int SwitchAntennaToQAM(struct drxk_state *state) +{ + int status = -1; + + if (state->m_AntennaSwitchDVBTDVBC != 0) { + if (state->m_GPIO != state->m_AntennaDVBC) { + state->m_GPIO = state->m_AntennaDVBC; + status = WriteGPIO(state); + } + } + return status; +} + +static int SwitchAntennaToDVBT(struct drxk_state *state) +{ + int status = -1; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + if (state->m_AntennaSwitchDVBTDVBC != 0) { + if (state->m_GPIO != state->m_AntennaDVBT) { + state->m_GPIO = state->m_AntennaDVBT; + status = WriteGPIO(state); + } + } + return status; +} + + +static int PowerDownDevice(struct drxk_state *state) +{ + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + int status; + do { + if (state->m_bPDownOpenBridge) { + // Open I2C bridge before power down of DRXK + CHK_ERROR(ConfigureI2CBridge(state, true)); + } + // driver 0.9.0 + CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); + + CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY)); + state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + CHK_ERROR(HI_CfgCommand(state)); + } + while(0); + + if (status<0) { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + return -1; + } + return 0; +} + +static int load_microcode(struct drxk_state *state, char *mc_name) +{ + const struct firmware *fw = NULL; + int err=0; + + err = request_firmware(&fw, mc_name, state->i2c->dev.parent); + if (err < 0) { + printk(KERN_ERR + ": Could not load firmware file %s.\n", mc_name); + printk(KERN_INFO + ": Copy %s to your hotplug directory!\n", mc_name); + return err; + } + err=DownloadMicrocode(state, fw->data, fw->size); + release_firmware(fw); + return err; +} + +static int init_drxk(struct drxk_state *state) +{ + int status; + DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; + u16 driverVersion; + + //printk("init_drxk\n"); + if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { + do { + CHK_ERROR(PowerUpDevice(state)); + CHK_ERROR (DRXX_Open(state)); + /* Soft reset of OFDM-, sys- and osc-clockdomain */ + CHK_ERROR(Write16_0(state, SIO_CC_SOFT_RST__A, + SIO_CC_SOFT_RST_OFDM__M | + SIO_CC_SOFT_RST_SYS__M | + SIO_CC_SOFT_RST_OSC__M)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY)); + /* TODO is this needed, if yes how much delay in worst case scenario */ + msleep(1); + state->m_DRXK_A3_PATCH_CODE = true; + CHK_ERROR(GetDeviceCapabilities(state)); + + /* Bridge delay, uses oscilator clock */ + /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ + /* SDA brdige delay */ + state->m_HICfgBridgeDelay = (u16)((state->m_oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000; + /* Clipping */ + if (state->m_HICfgBridgeDelay > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) + { + state->m_HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; + } + /* SCL bridge delay, same as SDA for now */ + state->m_HICfgBridgeDelay += state->m_HICfgBridgeDelay << SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; + + CHK_ERROR(InitHI(state)); + /* disable various processes */ +#if NOA1ROM + if (!(state->m_DRXK_A1_ROM_CODE) && !(state->m_DRXK_A2_ROM_CODE) ) +#endif + { + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + } + + /* disable MPEG port */ + CHK_ERROR(MPEGTSDisable(state)); + + /* Stop AUD and SCU */ + CHK_ERROR(Write16_0(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP)); + + /* enable token-ring bus through OFDM block for possible ucode upload */ + CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON)); + + /* include boot loader section */ + CHK_ERROR(Write16_0(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE)); + CHK_ERROR(BLChainCmd(state, 0, 6, 100)); + +#if 0 + if (state->m_DRXK_A3_PATCH_CODE) + CHK_ERROR(DownloadMicrocode(state, + DRXK_A3_microcode, + DRXK_A3_microcode_length)); +#else + load_microcode(state, "drxk_a3.mc"); +#endif +#if NOA1ROM + if (state->m_DRXK_A2_PATCH_CODE) + CHK_ERROR(DownloadMicrocode(state, + DRXK_A2_microcode, + DRXK_A2_microcode_length)); +#endif + /* disable token-ring bus through OFDM block for possible ucode upload */ + CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF)); + + /* Run SCU for a little while to initialize microcode version numbers */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + CHK_ERROR (DRXX_Open(state)); + // added for test + msleep(30); + + powerMode = DRXK_POWER_DOWN_OFDM; + CHK_ERROR(CtrlPowerMode(state, &powerMode)); + + /* Stamp driver version number in SCU data RAM in BCD code + Done to enable field application engineers to retreive drxdriver version + via I2C from SCU RAM. + Not using SCU command interface for SCU register access since no + microcode may be present. + */ + driverVersion = (((DRXK_VERSION_MAJOR/100) % 10) << 12) + + (((DRXK_VERSION_MAJOR/10) % 10) << 8) + + ((DRXK_VERSION_MAJOR%10) << 4) + + (DRXK_VERSION_MINOR%10); + CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion )); + driverVersion = (((DRXK_VERSION_PATCH/1000) % 10) << 12) + + (((DRXK_VERSION_PATCH/100) % 10) << 8) + + (((DRXK_VERSION_PATCH/10) % 10) << 4) + + (DRXK_VERSION_PATCH%10); + CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion )); + + printk("DRXK driver version:%d.%d.%d\n", + DRXK_VERSION_MAJOR,DRXK_VERSION_MINOR,DRXK_VERSION_PATCH); + + /* Dirty fix of default values for ROM/PATCH microcode + Dirty because this fix makes it impossible to setup suitable values + before calling DRX_Open. This solution requires changes to RF AGC speed + to be done via the CTRL function after calling DRX_Open */ + + // m_dvbtRfAgcCfg.speed=3; + + /* Reset driver debug flags to 0 */ + CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_DEBUG__A, 0)); + /* driver 0.9.0 */ + /* Setup FEC OC: + NOTE: No more full FEC resets allowed afterwards!! */ + CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP)); + // MPEGTS functions are still the same + CHK_ERROR(MPEGTSDtoInit(state)); + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(MPEGTSConfigurePolarity(state)); + CHK_ERROR(MPEGTSConfigurePins(state, state->m_enableMPEGOutput)); + // added: configure GPIO + CHK_ERROR(WriteGPIO(state)); + + state->m_DrxkState = DRXK_STOPPED; + + if (state->m_bPowerDown) { + CHK_ERROR(PowerDownDevice(state)); + state->m_DrxkState = DRXK_POWERED_DOWN; + } + else + state->m_DrxkState = DRXK_STOPPED; + } while(0); + //printk("%s=%d\n", __FUNCTION__, status); + } + else + { + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " - Init already done\n")); + } + + return 0; +} + +static void drxk_c_release(struct dvb_frontend* fe) +{ + struct drxk_state *state=fe->demodulator_priv; + printk("%s\n", __FUNCTION__); + kfree(state); +} + +static int drxk_c_init (struct dvb_frontend *fe) +{ + struct drxk_state *state=fe->demodulator_priv; + + if (mutex_trylock(&state->ctlock)==0) + return -EBUSY; + SetOperationMode(state, OM_QAM_ITU_A); + return 0; +} + +static int drxk_c_sleep(struct dvb_frontend* fe) +{ + struct drxk_state *state=fe->demodulator_priv; + + ShutDown(state); + mutex_unlock(&state->ctlock); + return 0; +} + +static int drxk_gate_ctrl(struct dvb_frontend* fe, int enable) +{ + struct drxk_state *state = fe->demodulator_priv; + + //printk("drxk_gate %d\n", enable); + return ConfigureI2CBridge(state, enable ? true : false); +} + +#ifndef USE_API3 +static int drxk_set_parameters (struct dvb_frontend *fe) +#else +static int drxk_set_parameters (struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +#endif +{ +#ifndef USE_API3 + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + u32 delsys = p->delivery_system, old_delsys; +#endif + struct drxk_state *state = fe->demodulator_priv; + u32 IF; + + //printk("%s\n", __FUNCTION__); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (fe->ops.tuner_ops.set_params) +#ifndef USE_API3 + fe->ops.tuner_ops.set_params(fe); +#else + fe->ops.tuner_ops.set_params(fe, p); +#endif + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); +#ifndef USE_API3 +#else + state->param=*p; +#endif + fe->ops.tuner_ops.get_if_frequency(fe, &IF); /* WTF is a frequency frequency? */ + Start(state, 0, IF); + + //printk("%s IF=%d done\n", __FUNCTION__, IF); + return 0; +} + +static int drxk_c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + //struct drxk_state *state = fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + return 0; +} + +static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct drxk_state *state = fe->demodulator_priv; + u32 stat; + + *status=0; + GetLockStatus(state, &stat, 0); + if (stat==MPEG_LOCK) + *status|=0x1f; + if (stat==FEC_LOCK) + *status|=0x0f; + if (stat==DEMOD_LOCK) + *status|=0x07; + return 0; +} + +static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + //struct drxk_state *state = fe->demodulator_priv; + *ber=0; + return 0; +} + +static int drxk_read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct drxk_state *state = fe->demodulator_priv; + u32 val; + + ReadIFAgc(state, &val); + *strength = val & 0xffff;; + return 0; +} + +static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct drxk_state *state = fe->demodulator_priv; + s32 snr2; + + GetSignalToNoise(state, &snr2); + *snr = snr2&0xffff; + return 0; +} + +static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct drxk_state *state = fe->demodulator_priv; + u16 err; + + DVBTQAMGetAccPktErr(state, &err); + *ucblocks = (u32) err; + return 0; +} + +static int drxk_c_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ + sets->min_delay_ms=3000; + sets->max_drift=0; + sets->step_size=0; + return 0; +} + +static void drxk_t_release(struct dvb_frontend* fe) +{ + //struct drxk_state *state=fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + //kfree(state); +} + +static int drxk_t_init (struct dvb_frontend *fe) +{ + struct drxk_state *state=fe->demodulator_priv; + if (mutex_trylock(&state->ctlock)==0) + return -EBUSY; + //printk("%s\n", __FUNCTION__); + SetOperationMode(state, OM_DVBT); + //printk("%s done\n", __FUNCTION__); + return 0; +} + +static int drxk_t_sleep(struct dvb_frontend* fe) +{ + struct drxk_state *state=fe->demodulator_priv; + mutex_unlock(&state->ctlock); + return 0; +} + +static int drxk_t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + //struct drxk_state *state = fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + return 0; +} + +static struct dvb_frontend_ops drxk_c_ops = { + .info = { + .name = "DRXK DVB-C", + .type = FE_QAM, + .frequency_stepsize = 62500, + .frequency_min = 47000000, + .frequency_max = 862000000, + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, + .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO + }, + .release = drxk_c_release, + .init = drxk_c_init, + .sleep = drxk_c_sleep, + .i2c_gate_ctrl = drxk_gate_ctrl, + + .set_frontend = drxk_set_parameters, + .get_frontend = drxk_c_get_frontend, + .get_tune_settings = drxk_c_get_tune_settings, + + .read_status = drxk_read_status, + .read_ber = drxk_read_ber, + .read_signal_strength = drxk_read_signal_strength, + .read_snr = drxk_read_snr, + .read_ucblocks = drxk_read_ucblocks, +}; + +static struct dvb_frontend_ops drxk_t_ops = { + .info = { + .name = "DRXK DVB-T", + .type = FE_OFDM, + .frequency_min = 47125000, + .frequency_max = 865000000, + .frequency_stepsize = 166667, + .frequency_tolerance = 0, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | + FE_CAN_FEC_AUTO | + FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | + FE_CAN_MUTE_TS + }, + .release = drxk_t_release, + .init = drxk_t_init, + .sleep = drxk_t_sleep, + .i2c_gate_ctrl = drxk_gate_ctrl, + + .set_frontend = drxk_set_parameters, + .get_frontend = drxk_t_get_frontend, + + .read_status = drxk_read_status, + .read_ber = drxk_read_ber, + .read_signal_strength = drxk_read_signal_strength, + .read_snr = drxk_read_snr, + .read_ucblocks = drxk_read_ucblocks, +}; + +struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, u8 adr, + struct dvb_frontend **fe_t) +{ + struct drxk_state *state = NULL; + + state=kzalloc(sizeof(struct drxk_state), GFP_KERNEL); + if (!state) + return NULL; + + state->i2c=i2c; + state->demod_address=adr; + + mutex_init(&state->mutex); + mutex_init(&state->ctlock); + + memcpy(&state->c_frontend.ops, &drxk_c_ops, sizeof(struct dvb_frontend_ops)); + memcpy(&state->t_frontend.ops, &drxk_t_ops, sizeof(struct dvb_frontend_ops)); + state->c_frontend.demodulator_priv=state; + state->t_frontend.demodulator_priv=state; + + init_state(state); + if (init_drxk(state)<0) + goto error; + *fe_t = &state->t_frontend; + return &state->c_frontend; + +error: + printk("drxk: not found\n"); + kfree(state); + return NULL; +} + +MODULE_DESCRIPTION("DRX-K driver"); +MODULE_AUTHOR("Ralph Metzler"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(drxk_attach); diff --git a/frontends/drxk_hard.h b/frontends/drxk_hard.h index 78e8e7a..1d83284 100644 --- a/frontends/drxk_hard.h +++ b/frontends/drxk_hard.h @@ -1,343 +1,343 @@ -#include "drxk_map.h" - -#define DRXK_VERSION_MAJOR 0 -#define DRXK_VERSION_MINOR 9 -#define DRXK_VERSION_PATCH 4300 - -#define HI_I2C_DELAY 42 -#define HI_I2C_BRIDGE_DELAY 350 -#define DRXK_MAX_RETRIES 100 - -#define DRIVER_4400 1 - -#define DRXX_JTAGID 0x039210D9 -#define DRXX_J_JTAGID 0x239310D9 -#define DRXX_K_JTAGID 0x039210D9 - -#define DRX_UNKNOWN 254 -#define DRX_AUTO 255 - -#define DRX_SCU_READY 0 -#define DRXK_MAX_WAITTIME (200) -#define SCU_RESULT_OK 0 -#define SCU_RESULT_UNKSTD -2 -#define SCU_RESULT_UNKCMD -1 - -#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT -#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200) -#endif - -#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/ -#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/ -#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/ -#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/ -#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/ -#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/ -#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/ -#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/ - -#define IQM_CF_OUT_ENA_OFDM__M 0x4 -#define IQM_FS_ADJ_SEL_B_QAM 0x1 -#define IQM_FS_ADJ_SEL_B_OFF 0x0 -#define IQM_FS_ADJ_SEL_B_VSB 0x2 -#define IQM_RC_ADJ_SEL_B_OFF 0x0 -#define IQM_RC_ADJ_SEL_B_QAM 0x1 -#define IQM_RC_ADJ_SEL_B_VSB 0x2 - -enum OperationMode { - OM_NONE, - OM_QAM_ITU_A, - OM_QAM_ITU_B, - OM_QAM_ITU_C, - OM_DVBT -}; - -typedef enum { - DRX_POWER_UP = 0, - DRX_POWER_MODE_1, - DRX_POWER_MODE_2, - DRX_POWER_MODE_3, - DRX_POWER_MODE_4, - DRX_POWER_MODE_5, - DRX_POWER_MODE_6, - DRX_POWER_MODE_7, - DRX_POWER_MODE_8, - - DRX_POWER_MODE_9, - DRX_POWER_MODE_10, - DRX_POWER_MODE_11, - DRX_POWER_MODE_12, - DRX_POWER_MODE_13, - DRX_POWER_MODE_14, - DRX_POWER_MODE_15, - DRX_POWER_MODE_16, - DRX_POWER_DOWN = 255 -}DRXPowerMode_t, *pDRXPowerMode_t; - - -/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ -#ifndef DRXK_POWER_DOWN_OFDM -#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 -#endif - -/** /brief Intermediate power mode for DRXK, power down core (sysclk) */ -#ifndef DRXK_POWER_DOWN_CORE -#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 -#endif - -/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ -#ifndef DRXK_POWER_DOWN_PLL -#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 -#endif - - -enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; -enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN }; -enum EDrxkCoefArrayIndex { - DRXK_COEF_IDX_MN = 0, - DRXK_COEF_IDX_FM , - DRXK_COEF_IDX_L , - DRXK_COEF_IDX_LP , - DRXK_COEF_IDX_BG , - DRXK_COEF_IDX_DK , - DRXK_COEF_IDX_I , - DRXK_COEF_IDX_MAX -}; -enum EDrxkSifAttenuation { - DRXK_SIF_ATTENUATION_0DB, - DRXK_SIF_ATTENUATION_3DB, - DRXK_SIF_ATTENUATION_6DB, - DRXK_SIF_ATTENUATION_9DB -}; -enum EDrxkConstellation { - DRX_CONSTELLATION_BPSK = 0, - DRX_CONSTELLATION_QPSK, - DRX_CONSTELLATION_PSK8, - DRX_CONSTELLATION_QAM16, - DRX_CONSTELLATION_QAM32, - DRX_CONSTELLATION_QAM64, - DRX_CONSTELLATION_QAM128, - DRX_CONSTELLATION_QAM256, - DRX_CONSTELLATION_QAM512, - DRX_CONSTELLATION_QAM1024, - DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, - DRX_CONSTELLATION_AUTO = DRX_AUTO -}; -enum EDrxkInterleaveMode { - DRXK_QAM_I12_J17 = 16, - DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN -}; -enum { - DRXK_SPIN_A1 = 0, - DRXK_SPIN_A2, - DRXK_SPIN_A3, - DRXK_SPIN_UNKNOWN -}; - -enum DRXKCfgDvbtSqiSpeed { - DRXK_DVBT_SQI_SPEED_FAST = 0, - DRXK_DVBT_SQI_SPEED_MEDIUM, - DRXK_DVBT_SQI_SPEED_SLOW, - DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN -} ; - -enum DRXFftmode_t { - DRX_FFTMODE_2K = 0, - DRX_FFTMODE_4K, - DRX_FFTMODE_8K, - DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, - DRX_FFTMODE_AUTO = DRX_AUTO -}; - -enum DRXMPEGStrWidth_t { - DRX_MPEG_STR_WIDTH_1, - DRX_MPEG_STR_WIDTH_8 -}; - -enum DRXQamLockRange_t { - DRX_QAM_LOCKRANGE_NORMAL, - DRX_QAM_LOCKRANGE_EXTENDED -}; - -struct DRXKCfgDvbtEchoThres_t { - u16 threshold; - enum DRXFftmode_t fftMode; -} ; - -struct SCfgAgc -{ - enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ - u16 outputLevel; /* range dependent on AGC */ - u16 minOutputLevel; /* range dependent on AGC */ - u16 maxOutputLevel; /* range dependent on AGC */ - u16 speed; /* range dependent on AGC */ - u16 top; /* rf-agc take over point */ - u16 cutOffCurrent; /* rf-agc is accelerated if output current - is below cut-off current */ - u16 IngainTgtMax; - u16 FastClipCtrlDelay; -}; - -struct SCfgPreSaw -{ - u16 reference; /* pre SAW reference value, range 0 .. 31 */ - bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ -}; - -struct DRXKOfdmScCmd_t -{ - u16 cmd; /**< Command number */ - u16 subcmd; /**< Sub-command parameter*/ - u16 param0; /**< General purpous param */ - u16 param1; /**< General purpous param */ - u16 param2; /**< General purpous param */ - u16 param3; /**< General purpous param */ - u16 param4; /**< General purpous param */ -}; - -struct drxk_state { - struct dvb_frontend c_frontend; - struct dvb_frontend t_frontend; -#ifndef USE_API3 - struct dtv_frontend_properties props; -#else - struct dvb_frontend_parameters param; -#endif - struct device *dev; - - struct i2c_adapter *i2c; - u8 demod_address; - void *priv; - - struct mutex mutex; - struct mutex ctlock; - - u32 m_Instance; ///< Channel 1,2,3 or 4 - - int m_ChunkSize; - u8 Chunk[256]; - - bool m_hasLNA; - bool m_hasDVBT; - bool m_hasDVBC; - bool m_hasAudio; - bool m_hasATV; - bool m_hasOOB; - bool m_hasSAWSW; /**< TRUE if mat_tx is available */ - bool m_hasGPIO1; /**< TRUE if mat_rx is available */ - bool m_hasGPIO2; /**< TRUE if GPIO is available */ - bool m_hasIRQN; /**< TRUE if IRQN is available */ - u16 m_oscClockFreq; - u16 m_HICfgTimingDiv; - u16 m_HICfgBridgeDelay; - u16 m_HICfgWakeUpKey; - u16 m_HICfgTimeout; - u16 m_HICfgCtrl; - s32 m_sysClockFreq ; ///< system clock frequency in kHz - - enum EDrxkState m_DrxkState; ///< State of Drxk (init,stopped,started) - enum OperationMode m_OperationMode; ///< digital standards - struct SCfgAgc m_vsbRfAgcCfg; ///< settings for VSB RF-AGC - struct SCfgAgc m_vsbIfAgcCfg; ///< settings for VSB IF-AGC - u16 m_vsbPgaCfg; ///< settings for VSB PGA - struct SCfgPreSaw m_vsbPreSawCfg; ///< settings for pre SAW sense - s32 m_Quality83percent; ///< MER level (*0.1 dB) for 83% quality indication - s32 m_Quality93percent; ///< MER level (*0.1 dB) for 93% quality indication - bool m_smartAntInverted; - bool m_bDebugEnableBridge; - bool m_bPDownOpenBridge; ///< only open DRXK bridge before power-down once it has been accessed - bool m_bPowerDown; ///< Power down when not used - - u32 m_IqmFsRateOfs; ///< frequency shift as written to DRXK register (28bit fixpoint) - - bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ - bool m_insertRSByte; /**< If TRUE, insert RS byte */ - bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ - bool m_invertDATA; /**< If TRUE, invert DATA signals */ - bool m_invertERR; /**< If TRUE, invert ERR signal */ - bool m_invertSTR; /**< If TRUE, invert STR signals */ - bool m_invertVAL; /**< If TRUE, invert VAL signals */ - bool m_invertCLK; /**< If TRUE, invert CLK signals */ - bool m_DVBCStaticCLK; - bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will - be used, otherwise clockrate will - adapt to the bitrate of the TS */ - u32 m_DVBTBitrate; - u32 m_DVBCBitrate; - - u8 m_TSDataStrength; - u8 m_TSClockkStrength; - - enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width**/ - u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case - static clockrate is selected */ - - //LARGE_INTEGER m_StartTime; ///< Contains the time of the last demod start - s32 m_MpegLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) - s32 m_DemodLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) - - bool m_disableTEIhandling; - - bool m_RfAgcPol; - bool m_IfAgcPol; - - struct SCfgAgc m_atvRfAgcCfg; ///< settings for ATV RF-AGC - struct SCfgAgc m_atvIfAgcCfg; ///< settings for ATV IF-AGC - struct SCfgPreSaw m_atvPreSawCfg; ///< settings for ATV pre SAW sense - bool m_phaseCorrectionBypass; - s16 m_atvTopVidPeak; - u16 m_atvTopNoiseTh; - enum EDrxkSifAttenuation m_sifAttenuation; - bool m_enableCVBSOutput; - bool m_enableSIFOutput; - bool m_bMirrorFreqSpect; - enum EDrxkConstellation m_Constellation; ///< Constellation type of the channel - u32 m_CurrSymbolRate; ///< Current QAM symbol rate - struct SCfgAgc m_qamRfAgcCfg; ///< settings for QAM RF-AGC - struct SCfgAgc m_qamIfAgcCfg; ///< settings for QAM IF-AGC - u16 m_qamPgaCfg; ///< settings for QAM PGA - struct SCfgPreSaw m_qamPreSawCfg; ///< settings for QAM pre SAW sense - enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode - u16 m_fecRsPlen; - u16 m_fecRsPrescale; - - enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; - - u16 m_GPIO; - u16 m_GPIOCfg; - - struct SCfgAgc m_dvbtRfAgcCfg; ///< settings for QAM RF-AGC - struct SCfgAgc m_dvbtIfAgcCfg; ///< settings for QAM IF-AGC - struct SCfgPreSaw m_dvbtPreSawCfg; ///< settings for QAM pre SAW sense - - u16 m_agcFastClipCtrlDelay; - bool m_adcCompPassed; - u16 m_adcCompCoef[64]; - u16 m_adcState; - - u8 *m_microcode; - int m_microcode_length; - bool m_DRXK_A1_PATCH_CODE; - bool m_DRXK_A1_ROM_CODE; - bool m_DRXK_A2_ROM_CODE; - bool m_DRXK_A3_ROM_CODE; - bool m_DRXK_A2_PATCH_CODE; - bool m_DRXK_A3_PATCH_CODE; - - bool m_rfmirror; - u8 m_deviceSpin; - u32 m_iqmRcRate; - - u16 m_AntennaDVBC; - u16 m_AntennaDVBT; - u16 m_AntennaSwitchDVBTDVBC; - - DRXPowerMode_t m_currentPowerMode; -}; - -#define NEVER_LOCK 0 -#define NOT_LOCKED 1 -#define DEMOD_LOCK 2 -#define FEC_LOCK 3 -#define MPEG_LOCK 4 - +#include "drxk_map.h" + +#define DRXK_VERSION_MAJOR 0 +#define DRXK_VERSION_MINOR 9 +#define DRXK_VERSION_PATCH 4300 + +#define HI_I2C_DELAY 42 +#define HI_I2C_BRIDGE_DELAY 350 +#define DRXK_MAX_RETRIES 100 + +#define DRIVER_4400 1 + +#define DRXX_JTAGID 0x039210D9 +#define DRXX_J_JTAGID 0x239310D9 +#define DRXX_K_JTAGID 0x039210D9 + +#define DRX_UNKNOWN 254 +#define DRX_AUTO 255 + +#define DRX_SCU_READY 0 +#define DRXK_MAX_WAITTIME (200) +#define SCU_RESULT_OK 0 +#define SCU_RESULT_UNKSTD -2 +#define SCU_RESULT_UNKCMD -1 + +#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT +#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200) +#endif + +#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/ +#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/ +#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/ +#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/ +#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/ +#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/ +#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/ +#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/ + +#define IQM_CF_OUT_ENA_OFDM__M 0x4 +#define IQM_FS_ADJ_SEL_B_QAM 0x1 +#define IQM_FS_ADJ_SEL_B_OFF 0x0 +#define IQM_FS_ADJ_SEL_B_VSB 0x2 +#define IQM_RC_ADJ_SEL_B_OFF 0x0 +#define IQM_RC_ADJ_SEL_B_QAM 0x1 +#define IQM_RC_ADJ_SEL_B_VSB 0x2 + +enum OperationMode { + OM_NONE, + OM_QAM_ITU_A, + OM_QAM_ITU_B, + OM_QAM_ITU_C, + OM_DVBT +}; + +typedef enum { + DRX_POWER_UP = 0, + DRX_POWER_MODE_1, + DRX_POWER_MODE_2, + DRX_POWER_MODE_3, + DRX_POWER_MODE_4, + DRX_POWER_MODE_5, + DRX_POWER_MODE_6, + DRX_POWER_MODE_7, + DRX_POWER_MODE_8, + + DRX_POWER_MODE_9, + DRX_POWER_MODE_10, + DRX_POWER_MODE_11, + DRX_POWER_MODE_12, + DRX_POWER_MODE_13, + DRX_POWER_MODE_14, + DRX_POWER_MODE_15, + DRX_POWER_MODE_16, + DRX_POWER_DOWN = 255 +}DRXPowerMode_t, *pDRXPowerMode_t; + + +/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ +#ifndef DRXK_POWER_DOWN_OFDM +#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 +#endif + +/** /brief Intermediate power mode for DRXK, power down core (sysclk) */ +#ifndef DRXK_POWER_DOWN_CORE +#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 +#endif + +/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ +#ifndef DRXK_POWER_DOWN_PLL +#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 +#endif + + +enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; +enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN }; +enum EDrxkCoefArrayIndex { + DRXK_COEF_IDX_MN = 0, + DRXK_COEF_IDX_FM , + DRXK_COEF_IDX_L , + DRXK_COEF_IDX_LP , + DRXK_COEF_IDX_BG , + DRXK_COEF_IDX_DK , + DRXK_COEF_IDX_I , + DRXK_COEF_IDX_MAX +}; +enum EDrxkSifAttenuation { + DRXK_SIF_ATTENUATION_0DB, + DRXK_SIF_ATTENUATION_3DB, + DRXK_SIF_ATTENUATION_6DB, + DRXK_SIF_ATTENUATION_9DB +}; +enum EDrxkConstellation { + DRX_CONSTELLATION_BPSK = 0, + DRX_CONSTELLATION_QPSK, + DRX_CONSTELLATION_PSK8, + DRX_CONSTELLATION_QAM16, + DRX_CONSTELLATION_QAM32, + DRX_CONSTELLATION_QAM64, + DRX_CONSTELLATION_QAM128, + DRX_CONSTELLATION_QAM256, + DRX_CONSTELLATION_QAM512, + DRX_CONSTELLATION_QAM1024, + DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, + DRX_CONSTELLATION_AUTO = DRX_AUTO +}; +enum EDrxkInterleaveMode { + DRXK_QAM_I12_J17 = 16, + DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN +}; +enum { + DRXK_SPIN_A1 = 0, + DRXK_SPIN_A2, + DRXK_SPIN_A3, + DRXK_SPIN_UNKNOWN +}; + +enum DRXKCfgDvbtSqiSpeed { + DRXK_DVBT_SQI_SPEED_FAST = 0, + DRXK_DVBT_SQI_SPEED_MEDIUM, + DRXK_DVBT_SQI_SPEED_SLOW, + DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN +} ; + +enum DRXFftmode_t { + DRX_FFTMODE_2K = 0, + DRX_FFTMODE_4K, + DRX_FFTMODE_8K, + DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, + DRX_FFTMODE_AUTO = DRX_AUTO +}; + +enum DRXMPEGStrWidth_t { + DRX_MPEG_STR_WIDTH_1, + DRX_MPEG_STR_WIDTH_8 +}; + +enum DRXQamLockRange_t { + DRX_QAM_LOCKRANGE_NORMAL, + DRX_QAM_LOCKRANGE_EXTENDED +}; + +struct DRXKCfgDvbtEchoThres_t { + u16 threshold; + enum DRXFftmode_t fftMode; +} ; + +struct SCfgAgc +{ + enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ + u16 outputLevel; /* range dependent on AGC */ + u16 minOutputLevel; /* range dependent on AGC */ + u16 maxOutputLevel; /* range dependent on AGC */ + u16 speed; /* range dependent on AGC */ + u16 top; /* rf-agc take over point */ + u16 cutOffCurrent; /* rf-agc is accelerated if output current + is below cut-off current */ + u16 IngainTgtMax; + u16 FastClipCtrlDelay; +}; + +struct SCfgPreSaw +{ + u16 reference; /* pre SAW reference value, range 0 .. 31 */ + bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ +}; + +struct DRXKOfdmScCmd_t +{ + u16 cmd; /**< Command number */ + u16 subcmd; /**< Sub-command parameter*/ + u16 param0; /**< General purpous param */ + u16 param1; /**< General purpous param */ + u16 param2; /**< General purpous param */ + u16 param3; /**< General purpous param */ + u16 param4; /**< General purpous param */ +}; + +struct drxk_state { + struct dvb_frontend c_frontend; + struct dvb_frontend t_frontend; +#ifndef USE_API3 + struct dtv_frontend_properties props; +#else + struct dvb_frontend_parameters param; +#endif + struct device *dev; + + struct i2c_adapter *i2c; + u8 demod_address; + void *priv; + + struct mutex mutex; + struct mutex ctlock; + + u32 m_Instance; ///< Channel 1,2,3 or 4 + + int m_ChunkSize; + u8 Chunk[256]; + + bool m_hasLNA; + bool m_hasDVBT; + bool m_hasDVBC; + bool m_hasAudio; + bool m_hasATV; + bool m_hasOOB; + bool m_hasSAWSW; /**< TRUE if mat_tx is available */ + bool m_hasGPIO1; /**< TRUE if mat_rx is available */ + bool m_hasGPIO2; /**< TRUE if GPIO is available */ + bool m_hasIRQN; /**< TRUE if IRQN is available */ + u16 m_oscClockFreq; + u16 m_HICfgTimingDiv; + u16 m_HICfgBridgeDelay; + u16 m_HICfgWakeUpKey; + u16 m_HICfgTimeout; + u16 m_HICfgCtrl; + s32 m_sysClockFreq ; ///< system clock frequency in kHz + + enum EDrxkState m_DrxkState; ///< State of Drxk (init,stopped,started) + enum OperationMode m_OperationMode; ///< digital standards + struct SCfgAgc m_vsbRfAgcCfg; ///< settings for VSB RF-AGC + struct SCfgAgc m_vsbIfAgcCfg; ///< settings for VSB IF-AGC + u16 m_vsbPgaCfg; ///< settings for VSB PGA + struct SCfgPreSaw m_vsbPreSawCfg; ///< settings for pre SAW sense + s32 m_Quality83percent; ///< MER level (*0.1 dB) for 83% quality indication + s32 m_Quality93percent; ///< MER level (*0.1 dB) for 93% quality indication + bool m_smartAntInverted; + bool m_bDebugEnableBridge; + bool m_bPDownOpenBridge; ///< only open DRXK bridge before power-down once it has been accessed + bool m_bPowerDown; ///< Power down when not used + + u32 m_IqmFsRateOfs; ///< frequency shift as written to DRXK register (28bit fixpoint) + + bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ + bool m_insertRSByte; /**< If TRUE, insert RS byte */ + bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ + bool m_invertDATA; /**< If TRUE, invert DATA signals */ + bool m_invertERR; /**< If TRUE, invert ERR signal */ + bool m_invertSTR; /**< If TRUE, invert STR signals */ + bool m_invertVAL; /**< If TRUE, invert VAL signals */ + bool m_invertCLK; /**< If TRUE, invert CLK signals */ + bool m_DVBCStaticCLK; + bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will + be used, otherwise clockrate will + adapt to the bitrate of the TS */ + u32 m_DVBTBitrate; + u32 m_DVBCBitrate; + + u8 m_TSDataStrength; + u8 m_TSClockkStrength; + + enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width**/ + u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case + static clockrate is selected */ + + //LARGE_INTEGER m_StartTime; ///< Contains the time of the last demod start + s32 m_MpegLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) + s32 m_DemodLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) + + bool m_disableTEIhandling; + + bool m_RfAgcPol; + bool m_IfAgcPol; + + struct SCfgAgc m_atvRfAgcCfg; ///< settings for ATV RF-AGC + struct SCfgAgc m_atvIfAgcCfg; ///< settings for ATV IF-AGC + struct SCfgPreSaw m_atvPreSawCfg; ///< settings for ATV pre SAW sense + bool m_phaseCorrectionBypass; + s16 m_atvTopVidPeak; + u16 m_atvTopNoiseTh; + enum EDrxkSifAttenuation m_sifAttenuation; + bool m_enableCVBSOutput; + bool m_enableSIFOutput; + bool m_bMirrorFreqSpect; + enum EDrxkConstellation m_Constellation; ///< Constellation type of the channel + u32 m_CurrSymbolRate; ///< Current QAM symbol rate + struct SCfgAgc m_qamRfAgcCfg; ///< settings for QAM RF-AGC + struct SCfgAgc m_qamIfAgcCfg; ///< settings for QAM IF-AGC + u16 m_qamPgaCfg; ///< settings for QAM PGA + struct SCfgPreSaw m_qamPreSawCfg; ///< settings for QAM pre SAW sense + enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode + u16 m_fecRsPlen; + u16 m_fecRsPrescale; + + enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; + + u16 m_GPIO; + u16 m_GPIOCfg; + + struct SCfgAgc m_dvbtRfAgcCfg; ///< settings for QAM RF-AGC + struct SCfgAgc m_dvbtIfAgcCfg; ///< settings for QAM IF-AGC + struct SCfgPreSaw m_dvbtPreSawCfg; ///< settings for QAM pre SAW sense + + u16 m_agcFastClipCtrlDelay; + bool m_adcCompPassed; + u16 m_adcCompCoef[64]; + u16 m_adcState; + + u8 *m_microcode; + int m_microcode_length; + bool m_DRXK_A1_PATCH_CODE; + bool m_DRXK_A1_ROM_CODE; + bool m_DRXK_A2_ROM_CODE; + bool m_DRXK_A3_ROM_CODE; + bool m_DRXK_A2_PATCH_CODE; + bool m_DRXK_A3_PATCH_CODE; + + bool m_rfmirror; + u8 m_deviceSpin; + u32 m_iqmRcRate; + + u16 m_AntennaDVBC; + u16 m_AntennaDVBT; + u16 m_AntennaSwitchDVBTDVBC; + + DRXPowerMode_t m_currentPowerMode; +}; + +#define NEVER_LOCK 0 +#define NOT_LOCKED 1 +#define DEMOD_LOCK 2 +#define FEC_LOCK 3 +#define MPEG_LOCK 4 + diff --git a/frontends/drxk_map.h b/frontends/drxk_map.h index 02895aa..4021508 100644 --- a/frontends/drxk_map.h +++ b/frontends/drxk_map.h @@ -1,16438 +1,16438 @@ -#ifndef __DRXK_MAP__H__ -#define __DRXK_MAP__H__ 1 - -#define AUD_COMM_EXEC__A 0x1000000 -#define AUD_COMM_EXEC__W 2 -#define AUD_COMM_EXEC__M 0x3 -#define AUD_COMM_EXEC__PRE 0x0 -#define AUD_COMM_EXEC_STOP 0x0 - -#define FEC_COMM_EXEC__A 0x1C00000 -#define FEC_COMM_EXEC__W 2 -#define FEC_COMM_EXEC__M 0x3 -#define FEC_COMM_EXEC__PRE 0x0 -#define FEC_COMM_EXEC_STOP 0x0 -#define FEC_COMM_EXEC_ACTIVE 0x1 -#define FEC_COMM_EXEC_HOLD 0x2 - -#define FEC_COMM_MB__A 0x1C00002 -#define FEC_COMM_MB__W 16 -#define FEC_COMM_MB__M 0xFFFF -#define FEC_COMM_MB__PRE 0x0 -#define FEC_COMM_INT_REQ__A 0x1C00003 -#define FEC_COMM_INT_REQ__W 16 -#define FEC_COMM_INT_REQ__M 0xFFFF -#define FEC_COMM_INT_REQ__PRE 0x0 -#define FEC_COMM_INT_REQ_OC_REQ__B 0 -#define FEC_COMM_INT_REQ_OC_REQ__W 1 -#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 -#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 -#define FEC_COMM_INT_REQ_RS_REQ__B 1 -#define FEC_COMM_INT_REQ_RS_REQ__W 1 -#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 -#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 -#define FEC_COMM_INT_REQ_DI_REQ__B 2 -#define FEC_COMM_INT_REQ_DI_REQ__W 1 -#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 -#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 - -#define FEC_COMM_INT_STA__A 0x1C00005 -#define FEC_COMM_INT_STA__W 16 -#define FEC_COMM_INT_STA__M 0xFFFF -#define FEC_COMM_INT_STA__PRE 0x0 -#define FEC_COMM_INT_MSK__A 0x1C00006 -#define FEC_COMM_INT_MSK__W 16 -#define FEC_COMM_INT_MSK__M 0xFFFF -#define FEC_COMM_INT_MSK__PRE 0x0 -#define FEC_COMM_INT_STM__A 0x1C00007 -#define FEC_COMM_INT_STM__W 16 -#define FEC_COMM_INT_STM__M 0xFFFF -#define FEC_COMM_INT_STM__PRE 0x0 - - - -#define FEC_TOP_COMM_EXEC__A 0x1C10000 -#define FEC_TOP_COMM_EXEC__W 2 -#define FEC_TOP_COMM_EXEC__M 0x3 -#define FEC_TOP_COMM_EXEC__PRE 0x0 -#define FEC_TOP_COMM_EXEC_STOP 0x0 -#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 -#define FEC_TOP_COMM_EXEC_HOLD 0x2 - -#define FEC_TOP_ANNEX__A 0x1C10010 -#define FEC_TOP_ANNEX__W 2 -#define FEC_TOP_ANNEX__M 0x3 -#define FEC_TOP_ANNEX__PRE 0x0 -#define FEC_TOP_ANNEX_A 0x0 -#define FEC_TOP_ANNEX_B 0x1 -#define FEC_TOP_ANNEX_C 0x2 -#define FEC_TOP_ANNEX_D 0x3 - - - -#define FEC_DI_COMM_EXEC__A 0x1C20000 -#define FEC_DI_COMM_EXEC__W 2 -#define FEC_DI_COMM_EXEC__M 0x3 -#define FEC_DI_COMM_EXEC__PRE 0x0 -#define FEC_DI_COMM_EXEC_STOP 0x0 -#define FEC_DI_COMM_EXEC_ACTIVE 0x1 -#define FEC_DI_COMM_EXEC_HOLD 0x2 - -#define FEC_DI_COMM_MB__A 0x1C20002 -#define FEC_DI_COMM_MB__W 2 -#define FEC_DI_COMM_MB__M 0x3 -#define FEC_DI_COMM_MB__PRE 0x0 -#define FEC_DI_COMM_MB_CTL__B 0 -#define FEC_DI_COMM_MB_CTL__W 1 -#define FEC_DI_COMM_MB_CTL__M 0x1 -#define FEC_DI_COMM_MB_CTL__PRE 0x0 -#define FEC_DI_COMM_MB_CTL_OFF 0x0 -#define FEC_DI_COMM_MB_CTL_ON 0x1 -#define FEC_DI_COMM_MB_OBS__B 1 -#define FEC_DI_COMM_MB_OBS__W 1 -#define FEC_DI_COMM_MB_OBS__M 0x2 -#define FEC_DI_COMM_MB_OBS__PRE 0x0 -#define FEC_DI_COMM_MB_OBS_OFF 0x0 -#define FEC_DI_COMM_MB_OBS_ON 0x2 - -#define FEC_DI_COMM_INT_REQ__A 0x1C20003 -#define FEC_DI_COMM_INT_REQ__W 1 -#define FEC_DI_COMM_INT_REQ__M 0x1 -#define FEC_DI_COMM_INT_REQ__PRE 0x0 -#define FEC_DI_COMM_INT_STA__A 0x1C20005 -#define FEC_DI_COMM_INT_STA__W 2 -#define FEC_DI_COMM_INT_STA__M 0x3 -#define FEC_DI_COMM_INT_STA__PRE 0x0 - -#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 -#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 -#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 -#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 - -#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 -#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 -#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 -#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 - -#define FEC_DI_COMM_INT_MSK__A 0x1C20006 -#define FEC_DI_COMM_INT_MSK__W 2 -#define FEC_DI_COMM_INT_MSK__M 0x3 -#define FEC_DI_COMM_INT_MSK__PRE 0x0 -#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 -#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 -#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 -#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 -#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 -#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 -#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 -#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 - -#define FEC_DI_COMM_INT_STM__A 0x1C20007 -#define FEC_DI_COMM_INT_STM__W 2 -#define FEC_DI_COMM_INT_STM__M 0x3 -#define FEC_DI_COMM_INT_STM__PRE 0x0 -#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 -#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 -#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 -#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 -#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 -#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 -#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 -#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 - - -#define FEC_DI_STATUS__A 0x1C20010 -#define FEC_DI_STATUS__W 1 -#define FEC_DI_STATUS__M 0x1 -#define FEC_DI_STATUS__PRE 0x0 -#define FEC_DI_MODE__A 0x1C20011 -#define FEC_DI_MODE__W 3 -#define FEC_DI_MODE__M 0x7 -#define FEC_DI_MODE__PRE 0x0 - -#define FEC_DI_MODE_NO_SYNC__B 0 -#define FEC_DI_MODE_NO_SYNC__W 1 -#define FEC_DI_MODE_NO_SYNC__M 0x1 -#define FEC_DI_MODE_NO_SYNC__PRE 0x0 - -#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 -#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 -#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 -#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 - -#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 -#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 -#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 -#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 - - -#define FEC_DI_CONTROL_WORD__A 0x1C20012 -#define FEC_DI_CONTROL_WORD__W 4 -#define FEC_DI_CONTROL_WORD__M 0xF -#define FEC_DI_CONTROL_WORD__PRE 0x0 - -#define FEC_DI_RESTART__A 0x1C20013 -#define FEC_DI_RESTART__W 1 -#define FEC_DI_RESTART__M 0x1 -#define FEC_DI_RESTART__PRE 0x0 - -#define FEC_DI_TIMEOUT_LO__A 0x1C20014 -#define FEC_DI_TIMEOUT_LO__W 16 -#define FEC_DI_TIMEOUT_LO__M 0xFFFF -#define FEC_DI_TIMEOUT_LO__PRE 0x0 - -#define FEC_DI_TIMEOUT_HI__A 0x1C20015 -#define FEC_DI_TIMEOUT_HI__W 8 -#define FEC_DI_TIMEOUT_HI__M 0xFF -#define FEC_DI_TIMEOUT_HI__PRE 0xA - -#define FEC_DI_INPUT_CTL__A 0x1C20016 -#define FEC_DI_INPUT_CTL__W 1 -#define FEC_DI_INPUT_CTL__M 0x1 -#define FEC_DI_INPUT_CTL__PRE 0x0 - - - -#define FEC_RS_COMM_EXEC__A 0x1C30000 -#define FEC_RS_COMM_EXEC__W 2 -#define FEC_RS_COMM_EXEC__M 0x3 -#define FEC_RS_COMM_EXEC__PRE 0x0 -#define FEC_RS_COMM_EXEC_STOP 0x0 -#define FEC_RS_COMM_EXEC_ACTIVE 0x1 -#define FEC_RS_COMM_EXEC_HOLD 0x2 - -#define FEC_RS_COMM_MB__A 0x1C30002 -#define FEC_RS_COMM_MB__W 2 -#define FEC_RS_COMM_MB__M 0x3 -#define FEC_RS_COMM_MB__PRE 0x0 -#define FEC_RS_COMM_MB_CTL__B 0 -#define FEC_RS_COMM_MB_CTL__W 1 -#define FEC_RS_COMM_MB_CTL__M 0x1 -#define FEC_RS_COMM_MB_CTL__PRE 0x0 -#define FEC_RS_COMM_MB_CTL_OFF 0x0 -#define FEC_RS_COMM_MB_CTL_ON 0x1 -#define FEC_RS_COMM_MB_OBS__B 1 -#define FEC_RS_COMM_MB_OBS__W 1 -#define FEC_RS_COMM_MB_OBS__M 0x2 -#define FEC_RS_COMM_MB_OBS__PRE 0x0 -#define FEC_RS_COMM_MB_OBS_OFF 0x0 -#define FEC_RS_COMM_MB_OBS_ON 0x2 - -#define FEC_RS_COMM_INT_REQ__A 0x1C30003 -#define FEC_RS_COMM_INT_REQ__W 1 -#define FEC_RS_COMM_INT_REQ__M 0x1 -#define FEC_RS_COMM_INT_REQ__PRE 0x0 -#define FEC_RS_COMM_INT_STA__A 0x1C30005 -#define FEC_RS_COMM_INT_STA__W 2 -#define FEC_RS_COMM_INT_STA__M 0x3 -#define FEC_RS_COMM_INT_STA__PRE 0x0 - -#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 -#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 -#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 -#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 - -#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 -#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 -#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 -#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 - -#define FEC_RS_COMM_INT_MSK__A 0x1C30006 -#define FEC_RS_COMM_INT_MSK__W 2 -#define FEC_RS_COMM_INT_MSK__M 0x3 -#define FEC_RS_COMM_INT_MSK__PRE 0x0 -#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 -#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 -#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 -#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 -#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 -#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 -#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 -#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 - -#define FEC_RS_COMM_INT_STM__A 0x1C30007 -#define FEC_RS_COMM_INT_STM__W 2 -#define FEC_RS_COMM_INT_STM__M 0x3 -#define FEC_RS_COMM_INT_STM__PRE 0x0 -#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 -#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 -#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 -#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 -#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 -#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 -#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 -#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 - -#define FEC_RS_STATUS__A 0x1C30010 -#define FEC_RS_STATUS__W 1 -#define FEC_RS_STATUS__M 0x1 -#define FEC_RS_STATUS__PRE 0x0 -#define FEC_RS_MODE__A 0x1C30011 -#define FEC_RS_MODE__W 1 -#define FEC_RS_MODE__M 0x1 -#define FEC_RS_MODE__PRE 0x0 - -#define FEC_RS_MODE_BYPASS__B 0 -#define FEC_RS_MODE_BYPASS__W 1 -#define FEC_RS_MODE_BYPASS__M 0x1 -#define FEC_RS_MODE_BYPASS__PRE 0x0 - -#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 -#define FEC_RS_MEASUREMENT_PERIOD__W 16 -#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF -#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x993 - -#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 -#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 -#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF -#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x993 - -#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 -#define FEC_RS_MEASUREMENT_PRESCALE__W 16 -#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF -#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 - -#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 -#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 -#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF -#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 - -#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 -#define FEC_RS_NR_BIT_ERRORS__W 16 -#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF -#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF - -#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 -#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 -#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF -#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF - -#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 -#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 -#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 -#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 - -#define FEC_RS_NR_SYMBOL_ERRORS__A 0x1C30015 -#define FEC_RS_NR_SYMBOL_ERRORS__W 16 -#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF -#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF - -#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 -#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 -#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF -#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF - -#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 -#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 -#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 -#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 - -#define FEC_RS_NR_PACKET_ERRORS__A 0x1C30016 -#define FEC_RS_NR_PACKET_ERRORS__W 16 -#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF -#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF - -#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 -#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 -#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF -#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF - -#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 -#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 -#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 -#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 - -#define FEC_RS_NR_FAILURES__A 0x1C30017 -#define FEC_RS_NR_FAILURES__W 16 -#define FEC_RS_NR_FAILURES__M 0xFFFF -#define FEC_RS_NR_FAILURES__PRE 0x0 - -#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 -#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 -#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF -#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 - -#define FEC_RS_NR_FAILURES_EXP__B 12 -#define FEC_RS_NR_FAILURES_EXP__W 4 -#define FEC_RS_NR_FAILURES_EXP__M 0xF000 -#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 - - - -#define FEC_OC_COMM_EXEC__A 0x1C40000 -#define FEC_OC_COMM_EXEC__W 2 -#define FEC_OC_COMM_EXEC__M 0x3 -#define FEC_OC_COMM_EXEC__PRE 0x0 -#define FEC_OC_COMM_EXEC_STOP 0x0 -#define FEC_OC_COMM_EXEC_ACTIVE 0x1 -#define FEC_OC_COMM_EXEC_HOLD 0x2 - -#define FEC_OC_COMM_MB__A 0x1C40002 -#define FEC_OC_COMM_MB__W 2 -#define FEC_OC_COMM_MB__M 0x3 -#define FEC_OC_COMM_MB__PRE 0x0 -#define FEC_OC_COMM_MB_CTL__B 0 -#define FEC_OC_COMM_MB_CTL__W 1 -#define FEC_OC_COMM_MB_CTL__M 0x1 -#define FEC_OC_COMM_MB_CTL__PRE 0x0 -#define FEC_OC_COMM_MB_CTL_OFF 0x0 -#define FEC_OC_COMM_MB_CTL_ON 0x1 -#define FEC_OC_COMM_MB_OBS__B 1 -#define FEC_OC_COMM_MB_OBS__W 1 -#define FEC_OC_COMM_MB_OBS__M 0x2 -#define FEC_OC_COMM_MB_OBS__PRE 0x0 -#define FEC_OC_COMM_MB_OBS_OFF 0x0 -#define FEC_OC_COMM_MB_OBS_ON 0x2 - -#define FEC_OC_COMM_INT_REQ__A 0x1C40003 -#define FEC_OC_COMM_INT_REQ__W 1 -#define FEC_OC_COMM_INT_REQ__M 0x1 -#define FEC_OC_COMM_INT_REQ__PRE 0x0 -#define FEC_OC_COMM_INT_STA__A 0x1C40005 -#define FEC_OC_COMM_INT_STA__W 8 -#define FEC_OC_COMM_INT_STA__M 0xFF -#define FEC_OC_COMM_INT_STA__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 -#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 -#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 -#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 -#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 -#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 -#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 -#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 -#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 -#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 -#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 -#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 -#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 -#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 -#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 -#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 -#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 -#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 -#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 -#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 -#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 -#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 -#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 -#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 -#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_MSK__A 0x1C40006 -#define FEC_OC_COMM_INT_MSK__W 8 -#define FEC_OC_COMM_INT_MSK__M 0xFF -#define FEC_OC_COMM_INT_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 -#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 -#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 -#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 -#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 -#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 -#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 -#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 -#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 -#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 -#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 -#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 -#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 -#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 -#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 -#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 -#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 - -#define FEC_OC_COMM_INT_STM__A 0x1C40007 -#define FEC_OC_COMM_INT_STM__W 8 -#define FEC_OC_COMM_INT_STM__M 0xFF -#define FEC_OC_COMM_INT_STM__PRE 0x0 -#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 -#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 -#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 -#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 -#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 -#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 -#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 -#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 -#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 -#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 -#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 -#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 -#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 -#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 -#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 -#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 -#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 -#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 -#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 -#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 -#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 -#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 -#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 -#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 -#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 - -#define FEC_OC_STATUS__A 0x1C40010 -#define FEC_OC_STATUS__W 5 -#define FEC_OC_STATUS__M 0x1F -#define FEC_OC_STATUS__PRE 0x0 - -#define FEC_OC_STATUS_DPR_STATUS__B 0 -#define FEC_OC_STATUS_DPR_STATUS__W 1 -#define FEC_OC_STATUS_DPR_STATUS__M 0x1 -#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 - -#define FEC_OC_STATUS_SNC_STATUS__B 1 -#define FEC_OC_STATUS_SNC_STATUS__W 2 -#define FEC_OC_STATUS_SNC_STATUS__M 0x6 -#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 -#define FEC_OC_STATUS_SNC_STATUS_HUNTING 0x0 -#define FEC_OC_STATUS_SNC_STATUS_TRACKING 0x2 -#define FEC_OC_STATUS_SNC_STATUS_LOCKED 0x4 - -#define FEC_OC_STATUS_FIFO_FULL__B 3 -#define FEC_OC_STATUS_FIFO_FULL__W 1 -#define FEC_OC_STATUS_FIFO_FULL__M 0x8 -#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 - -#define FEC_OC_STATUS_FIFO_EMPTY__B 4 -#define FEC_OC_STATUS_FIFO_EMPTY__W 1 -#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 -#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 - -#define FEC_OC_MODE__A 0x1C40011 -#define FEC_OC_MODE__W 4 -#define FEC_OC_MODE__M 0xF -#define FEC_OC_MODE__PRE 0x0 - -#define FEC_OC_MODE_PARITY__B 0 -#define FEC_OC_MODE_PARITY__W 1 -#define FEC_OC_MODE_PARITY__M 0x1 -#define FEC_OC_MODE_PARITY__PRE 0x0 - -#define FEC_OC_MODE_TRANSPARENT__B 1 -#define FEC_OC_MODE_TRANSPARENT__W 1 -#define FEC_OC_MODE_TRANSPARENT__M 0x2 -#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 - -#define FEC_OC_MODE_CLEAR__B 2 -#define FEC_OC_MODE_CLEAR__W 1 -#define FEC_OC_MODE_CLEAR__M 0x4 -#define FEC_OC_MODE_CLEAR__PRE 0x0 - -#define FEC_OC_MODE_RETAIN_FRAMING__B 3 -#define FEC_OC_MODE_RETAIN_FRAMING__W 1 -#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 -#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 - -#define FEC_OC_DPR_MODE__A 0x1C40012 -#define FEC_OC_DPR_MODE__W 2 -#define FEC_OC_DPR_MODE__M 0x3 -#define FEC_OC_DPR_MODE__PRE 0x0 - -#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 -#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 -#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 -#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 - -#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 -#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 -#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 -#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 - - -#define FEC_OC_DPR_UNLOCK__A 0x1C40013 -#define FEC_OC_DPR_UNLOCK__W 1 -#define FEC_OC_DPR_UNLOCK__M 0x1 -#define FEC_OC_DPR_UNLOCK__PRE 0x0 -#define FEC_OC_DTO_MODE__A 0x1C40014 -#define FEC_OC_DTO_MODE__W 3 -#define FEC_OC_DTO_MODE__M 0x7 -#define FEC_OC_DTO_MODE__PRE 0x0 - -#define FEC_OC_DTO_MODE_DYNAMIC__B 0 -#define FEC_OC_DTO_MODE_DYNAMIC__W 1 -#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 -#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 - -#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 -#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 -#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 -#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 - -#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 -#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 -#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 -#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 - - -#define FEC_OC_DTO_PERIOD__A 0x1C40015 -#define FEC_OC_DTO_PERIOD__W 8 -#define FEC_OC_DTO_PERIOD__M 0xFF -#define FEC_OC_DTO_PERIOD__PRE 0x0 -#define FEC_OC_DTO_RATE_LO__A 0x1C40016 -#define FEC_OC_DTO_RATE_LO__W 16 -#define FEC_OC_DTO_RATE_LO__M 0xFFFF -#define FEC_OC_DTO_RATE_LO__PRE 0x0 - -#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 -#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 -#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF -#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 - -#define FEC_OC_DTO_RATE_HI__A 0x1C40017 -#define FEC_OC_DTO_RATE_HI__W 10 -#define FEC_OC_DTO_RATE_HI__M 0x3FF -#define FEC_OC_DTO_RATE_HI__PRE 0xC0 - -#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 -#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 -#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF -#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 - -#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 -#define FEC_OC_DTO_BURST_LEN__W 8 -#define FEC_OC_DTO_BURST_LEN__M 0xFF -#define FEC_OC_DTO_BURST_LEN__PRE 0xBC - -#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 -#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 -#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF -#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC - -#define FEC_OC_FCT_MODE__A 0x1C4001A -#define FEC_OC_FCT_MODE__W 2 -#define FEC_OC_FCT_MODE__M 0x3 -#define FEC_OC_FCT_MODE__PRE 0x0 - -#define FEC_OC_FCT_MODE_RAT_ENA__B 0 -#define FEC_OC_FCT_MODE_RAT_ENA__W 1 -#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 -#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 - -#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 -#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 -#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 -#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 - -#define FEC_OC_FCT_USAGE__A 0x1C4001B -#define FEC_OC_FCT_USAGE__W 3 -#define FEC_OC_FCT_USAGE__M 0x7 -#define FEC_OC_FCT_USAGE__PRE 0x7 - -#define FEC_OC_FCT_USAGE_USAGE__B 0 -#define FEC_OC_FCT_USAGE_USAGE__W 3 -#define FEC_OC_FCT_USAGE_USAGE__M 0x7 -#define FEC_OC_FCT_USAGE_USAGE__PRE 0x7 - -#define FEC_OC_FCT_OCCUPATION__A 0x1C4001C -#define FEC_OC_FCT_OCCUPATION__W 12 -#define FEC_OC_FCT_OCCUPATION__M 0xFFF -#define FEC_OC_FCT_OCCUPATION__PRE 0x0 - -#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 -#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 -#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF -#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 - -#define FEC_OC_TMD_MODE__A 0x1C4001E -#define FEC_OC_TMD_MODE__W 3 -#define FEC_OC_TMD_MODE__M 0x7 -#define FEC_OC_TMD_MODE__PRE 0x4 - -#define FEC_OC_TMD_MODE_MODE__B 0 -#define FEC_OC_TMD_MODE_MODE__W 3 -#define FEC_OC_TMD_MODE_MODE__M 0x7 -#define FEC_OC_TMD_MODE_MODE__PRE 0x4 - -#define FEC_OC_TMD_COUNT__A 0x1C4001F -#define FEC_OC_TMD_COUNT__W 10 -#define FEC_OC_TMD_COUNT__M 0x3FF -#define FEC_OC_TMD_COUNT__PRE 0x1F4 - -#define FEC_OC_TMD_COUNT_COUNT__B 0 -#define FEC_OC_TMD_COUNT_COUNT__W 10 -#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF -#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 - -#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 -#define FEC_OC_TMD_HI_MARGIN__W 11 -#define FEC_OC_TMD_HI_MARGIN__M 0x7FF -#define FEC_OC_TMD_HI_MARGIN__PRE 0x500 - -#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 -#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 -#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF -#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x500 - -#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 -#define FEC_OC_TMD_LO_MARGIN__W 11 -#define FEC_OC_TMD_LO_MARGIN__M 0x7FF -#define FEC_OC_TMD_LO_MARGIN__PRE 0x300 - -#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 -#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 -#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF -#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x300 - -#define FEC_OC_TMD_CTL_UPD_RATE__A 0x1C40022 -#define FEC_OC_TMD_CTL_UPD_RATE__W 4 -#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF -#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 - -#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 -#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 -#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF -#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 - -#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 -#define FEC_OC_TMD_INT_UPD_RATE__W 4 -#define FEC_OC_TMD_INT_UPD_RATE__M 0xF -#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 - -#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 -#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 -#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF -#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 - -#define FEC_OC_AVR_PARM_A__A 0x1C40026 -#define FEC_OC_AVR_PARM_A__W 4 -#define FEC_OC_AVR_PARM_A__M 0xF -#define FEC_OC_AVR_PARM_A__PRE 0x6 - -#define FEC_OC_AVR_PARM_A_PARM__B 0 -#define FEC_OC_AVR_PARM_A_PARM__W 4 -#define FEC_OC_AVR_PARM_A_PARM__M 0xF -#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 - -#define FEC_OC_AVR_PARM_B__A 0x1C40027 -#define FEC_OC_AVR_PARM_B__W 4 -#define FEC_OC_AVR_PARM_B__M 0xF -#define FEC_OC_AVR_PARM_B__PRE 0x4 - -#define FEC_OC_AVR_PARM_B_PARM__B 0 -#define FEC_OC_AVR_PARM_B_PARM__W 4 -#define FEC_OC_AVR_PARM_B_PARM__M 0xF -#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 - -#define FEC_OC_AVR_AVG_LO__A 0x1C40028 -#define FEC_OC_AVR_AVG_LO__W 16 -#define FEC_OC_AVR_AVG_LO__M 0xFFFF -#define FEC_OC_AVR_AVG_LO__PRE 0x0 - -#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 -#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 -#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF -#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 - -#define FEC_OC_AVR_AVG_HI__A 0x1C40029 -#define FEC_OC_AVR_AVG_HI__W 6 -#define FEC_OC_AVR_AVG_HI__M 0x3F -#define FEC_OC_AVR_AVG_HI__PRE 0x0 - -#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 -#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 -#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F -#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 - -#define FEC_OC_RCN_MODE__A 0x1C4002C -#define FEC_OC_RCN_MODE__W 5 -#define FEC_OC_RCN_MODE__M 0x1F -#define FEC_OC_RCN_MODE__PRE 0x1F - -#define FEC_OC_RCN_MODE_MODE__B 0 -#define FEC_OC_RCN_MODE_MODE__W 5 -#define FEC_OC_RCN_MODE_MODE__M 0x1F -#define FEC_OC_RCN_MODE_MODE__PRE 0x1F - -#define FEC_OC_RCN_OCC_SETTLE__A 0x1C4002D -#define FEC_OC_RCN_OCC_SETTLE__W 11 -#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF -#define FEC_OC_RCN_OCC_SETTLE__PRE 0x400 - -#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 -#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 -#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF -#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x400 - -#define FEC_OC_RCN_GAIN__A 0x1C4002E -#define FEC_OC_RCN_GAIN__W 4 -#define FEC_OC_RCN_GAIN__M 0xF -#define FEC_OC_RCN_GAIN__PRE 0xC - -#define FEC_OC_RCN_GAIN_GAIN__B 0 -#define FEC_OC_RCN_GAIN_GAIN__W 4 -#define FEC_OC_RCN_GAIN_GAIN__M 0xF -#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC - -#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 -#define FEC_OC_RCN_CTL_RATE_LO__W 16 -#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF -#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 - -#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 -#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 -#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF -#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 - -#define FEC_OC_RCN_CTL_RATE_HI__A 0x1C40031 -#define FEC_OC_RCN_CTL_RATE_HI__W 8 -#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF -#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 - -#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 -#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 -#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF -#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 - -#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 -#define FEC_OC_RCN_CTL_STEP_LO__W 16 -#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF -#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 - -#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 -#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 -#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF -#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 - -#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 -#define FEC_OC_RCN_CTL_STEP_HI__W 8 -#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF -#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 - -#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 -#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 -#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF -#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 - -#define FEC_OC_RCN_DTO_OFS_LO__A 0x1C40034 -#define FEC_OC_RCN_DTO_OFS_LO__W 16 -#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF -#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 - -#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 -#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 -#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF -#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 - -#define FEC_OC_RCN_DTO_OFS_HI__A 0x1C40035 -#define FEC_OC_RCN_DTO_OFS_HI__W 8 -#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF -#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 - -#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 -#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 -#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF -#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 - -#define FEC_OC_RCN_DTO_RATE_LO__A 0x1C40036 -#define FEC_OC_RCN_DTO_RATE_LO__W 16 -#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF -#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 - -#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 -#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 -#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF -#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 - -#define FEC_OC_RCN_DTO_RATE_HI__A 0x1C40037 -#define FEC_OC_RCN_DTO_RATE_HI__W 8 -#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF -#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 - -#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 -#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 -#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF -#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 - -#define FEC_OC_RCN_RATE_CLIP_LO__A 0x1C40038 -#define FEC_OC_RCN_RATE_CLIP_LO__W 16 -#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF -#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 - -#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 -#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 -#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF -#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 - -#define FEC_OC_RCN_RATE_CLIP_HI__A 0x1C40039 -#define FEC_OC_RCN_RATE_CLIP_HI__W 8 -#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF -#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 - -#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 -#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 -#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF -#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 - -#define FEC_OC_RCN_DYN_RATE_LO__A 0x1C4003A -#define FEC_OC_RCN_DYN_RATE_LO__W 16 -#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF -#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 - -#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 -#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 -#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF -#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 - -#define FEC_OC_RCN_DYN_RATE_HI__A 0x1C4003B -#define FEC_OC_RCN_DYN_RATE_HI__W 8 -#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF -#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 - -#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 -#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 -#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF -#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 - -#define FEC_OC_SNC_MODE__A 0x1C40040 -#define FEC_OC_SNC_MODE__W 5 -#define FEC_OC_SNC_MODE__M 0x1F -#define FEC_OC_SNC_MODE__PRE 0x0 - -#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 -#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 -#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 -#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 - -#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 -#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 -#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 -#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 - -#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 -#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 -#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 -#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 - -#define FEC_OC_SNC_MODE_SHUTDOWN__B 4 -#define FEC_OC_SNC_MODE_SHUTDOWN__W 1 -#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 -#define FEC_OC_SNC_MODE_SHUTDOWN__PRE 0x0 - -#define FEC_OC_SNC_LWM__A 0x1C40041 -#define FEC_OC_SNC_LWM__W 4 -#define FEC_OC_SNC_LWM__M 0xF -#define FEC_OC_SNC_LWM__PRE 0x3 - -#define FEC_OC_SNC_LWM_MARK__B 0 -#define FEC_OC_SNC_LWM_MARK__W 4 -#define FEC_OC_SNC_LWM_MARK__M 0xF -#define FEC_OC_SNC_LWM_MARK__PRE 0x3 - -#define FEC_OC_SNC_HWM__A 0x1C40042 -#define FEC_OC_SNC_HWM__W 4 -#define FEC_OC_SNC_HWM__M 0xF -#define FEC_OC_SNC_HWM__PRE 0x5 - -#define FEC_OC_SNC_HWM_MARK__B 0 -#define FEC_OC_SNC_HWM_MARK__W 4 -#define FEC_OC_SNC_HWM_MARK__M 0xF -#define FEC_OC_SNC_HWM_MARK__PRE 0x5 - -#define FEC_OC_SNC_UNLOCK__A 0x1C40043 -#define FEC_OC_SNC_UNLOCK__W 1 -#define FEC_OC_SNC_UNLOCK__M 0x1 -#define FEC_OC_SNC_UNLOCK__PRE 0x0 - -#define FEC_OC_SNC_UNLOCK_RESTART__B 0 -#define FEC_OC_SNC_UNLOCK_RESTART__W 1 -#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 -#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 - -#define FEC_OC_SNC_LOCK_COUNT__A 0x1C40044 -#define FEC_OC_SNC_LOCK_COUNT__W 12 -#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF -#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 - -#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 -#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 -#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF -#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 - -#define FEC_OC_SNC_FAIL_COUNT__A 0x1C40045 -#define FEC_OC_SNC_FAIL_COUNT__W 12 -#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF -#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 - -#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 -#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 -#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF -#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 - -#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 -#define FEC_OC_SNC_FAIL_PERIOD__W 16 -#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF -#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 - -#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 -#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 -#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF -#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 - -#define FEC_OC_EMS_MODE__A 0x1C40047 -#define FEC_OC_EMS_MODE__W 2 -#define FEC_OC_EMS_MODE__M 0x3 -#define FEC_OC_EMS_MODE__PRE 0x0 - -#define FEC_OC_EMS_MODE_MODE__B 0 -#define FEC_OC_EMS_MODE_MODE__W 2 -#define FEC_OC_EMS_MODE_MODE__M 0x3 -#define FEC_OC_EMS_MODE_MODE__PRE 0x0 - -#define FEC_OC_IPR_MODE__A 0x1C40048 -#define FEC_OC_IPR_MODE__W 12 -#define FEC_OC_IPR_MODE__M 0xFFF -#define FEC_OC_IPR_MODE__PRE 0x0 - -#define FEC_OC_IPR_MODE_SERIAL__B 0 -#define FEC_OC_IPR_MODE_SERIAL__W 1 -#define FEC_OC_IPR_MODE_SERIAL__M 0x1 -#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 - -#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 -#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 -#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 -#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 - -#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 -#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 -#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 -#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 - -#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 -#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 -#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 -#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 -#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 -#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 -#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 -#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 -#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 -#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 -#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 -#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 -#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 -#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 -#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 -#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 -#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 -#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 -#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 -#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 -#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 -#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 -#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 -#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 -#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 -#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 -#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 -#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 - -#define FEC_OC_IPR_INVERT__A 0x1C40049 -#define FEC_OC_IPR_INVERT__W 12 -#define FEC_OC_IPR_INVERT__M 0xFFF -#define FEC_OC_IPR_INVERT__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD0__B 0 -#define FEC_OC_IPR_INVERT_MD0__W 1 -#define FEC_OC_IPR_INVERT_MD0__M 0x1 -#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD1__B 1 -#define FEC_OC_IPR_INVERT_MD1__W 1 -#define FEC_OC_IPR_INVERT_MD1__M 0x2 -#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD2__B 2 -#define FEC_OC_IPR_INVERT_MD2__W 1 -#define FEC_OC_IPR_INVERT_MD2__M 0x4 -#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD3__B 3 -#define FEC_OC_IPR_INVERT_MD3__W 1 -#define FEC_OC_IPR_INVERT_MD3__M 0x8 -#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD4__B 4 -#define FEC_OC_IPR_INVERT_MD4__W 1 -#define FEC_OC_IPR_INVERT_MD4__M 0x10 -#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD5__B 5 -#define FEC_OC_IPR_INVERT_MD5__W 1 -#define FEC_OC_IPR_INVERT_MD5__M 0x20 -#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD6__B 6 -#define FEC_OC_IPR_INVERT_MD6__W 1 -#define FEC_OC_IPR_INVERT_MD6__M 0x40 -#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD7__B 7 -#define FEC_OC_IPR_INVERT_MD7__W 1 -#define FEC_OC_IPR_INVERT_MD7__M 0x80 -#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MERR__B 8 -#define FEC_OC_IPR_INVERT_MERR__W 1 -#define FEC_OC_IPR_INVERT_MERR__M 0x100 -#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MSTRT__B 9 -#define FEC_OC_IPR_INVERT_MSTRT__W 1 -#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 -#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MVAL__B 10 -#define FEC_OC_IPR_INVERT_MVAL__W 1 -#define FEC_OC_IPR_INVERT_MVAL__M 0x400 -#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MCLK__B 11 -#define FEC_OC_IPR_INVERT_MCLK__W 1 -#define FEC_OC_IPR_INVERT_MCLK__M 0x800 -#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 - -#define FEC_OC_OCR_MODE__A 0x1C40050 -#define FEC_OC_OCR_MODE__W 4 -#define FEC_OC_OCR_MODE__M 0xF -#define FEC_OC_OCR_MODE__PRE 0x0 - -#define FEC_OC_OCR_MODE_MB_SELECT__B 0 -#define FEC_OC_OCR_MODE_MB_SELECT__W 1 -#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 -#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 - -#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 -#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 -#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 -#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 - -#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 -#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 -#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 -#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 - -#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 -#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 -#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 -#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 - -#define FEC_OC_OCR_RATE__A 0x1C40051 -#define FEC_OC_OCR_RATE__W 4 -#define FEC_OC_OCR_RATE__M 0xF -#define FEC_OC_OCR_RATE__PRE 0x0 - -#define FEC_OC_OCR_RATE_RATE__B 0 -#define FEC_OC_OCR_RATE_RATE__W 4 -#define FEC_OC_OCR_RATE_RATE__M 0xF -#define FEC_OC_OCR_RATE_RATE__PRE 0x0 - -#define FEC_OC_OCR_INVERT__A 0x1C40052 -#define FEC_OC_OCR_INVERT__W 12 -#define FEC_OC_OCR_INVERT__M 0xFFF -#define FEC_OC_OCR_INVERT__PRE 0x800 - -#define FEC_OC_OCR_INVERT_INVERT__B 0 -#define FEC_OC_OCR_INVERT_INVERT__W 12 -#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF -#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 - -#define FEC_OC_OCR_GRAB_COUNT__A 0x1C40053 -#define FEC_OC_OCR_GRAB_COUNT__W 16 -#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF -#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 - -#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 -#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 -#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF -#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 - -#define FEC_OC_OCR_GRAB_SYNC__A 0x1C40054 -#define FEC_OC_OCR_GRAB_SYNC__W 8 -#define FEC_OC_OCR_GRAB_SYNC__M 0xFF -#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 - -#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 -#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 -#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 -#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 - -#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 -#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 -#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 -#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 - -#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 -#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 -#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 -#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD0__A 0x1C40055 -#define FEC_OC_OCR_GRAB_RD0__W 10 -#define FEC_OC_OCR_GRAB_RD0__M 0x3FF -#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD1__A 0x1C40056 -#define FEC_OC_OCR_GRAB_RD1__W 10 -#define FEC_OC_OCR_GRAB_RD1__M 0x3FF -#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD2__A 0x1C40057 -#define FEC_OC_OCR_GRAB_RD2__W 10 -#define FEC_OC_OCR_GRAB_RD2__M 0x3FF -#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD3__A 0x1C40058 -#define FEC_OC_OCR_GRAB_RD3__W 10 -#define FEC_OC_OCR_GRAB_RD3__M 0x3FF -#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD4__A 0x1C40059 -#define FEC_OC_OCR_GRAB_RD4__W 10 -#define FEC_OC_OCR_GRAB_RD4__M 0x3FF -#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD5__A 0x1C4005A -#define FEC_OC_OCR_GRAB_RD5__W 10 -#define FEC_OC_OCR_GRAB_RD5__M 0x3FF -#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 - - - -#define FEC_DI_RAM__A 0x1C50000 - - - -#define FEC_RS_RAM__A 0x1C60000 - - - -#define FEC_OC_RAM__A 0x1C70000 - - - - - -#define IQM_COMM_EXEC__A 0x1800000 -#define IQM_COMM_EXEC__W 2 -#define IQM_COMM_EXEC__M 0x3 -#define IQM_COMM_EXEC__PRE 0x0 -#define IQM_COMM_EXEC_B__B 0 -#define IQM_COMM_EXEC_B__W 2 -#define IQM_COMM_EXEC_B__M 0x3 -#define IQM_COMM_EXEC_B__PRE 0x0 -#define IQM_COMM_EXEC_B_STOP 0x0 -#define IQM_COMM_EXEC_B_ACTIVE 0x1 -#define IQM_COMM_EXEC_B_HOLD 0x2 - -#define IQM_COMM_MB__A 0x1800002 -#define IQM_COMM_MB__W 16 -#define IQM_COMM_MB__M 0xFFFF -#define IQM_COMM_MB__PRE 0x0 -#define IQM_COMM_MB_B__B 0 -#define IQM_COMM_MB_B__W 16 -#define IQM_COMM_MB_B__M 0xFFFF -#define IQM_COMM_MB_B__PRE 0x0 - -#define IQM_COMM_INT_REQ__A 0x1800003 -#define IQM_COMM_INT_REQ__W 3 -#define IQM_COMM_INT_REQ__M 0x7 -#define IQM_COMM_INT_REQ__PRE 0x0 - -#define IQM_COMM_INT_REQ_AF_REQ__B 0 -#define IQM_COMM_INT_REQ_AF_REQ__W 1 -#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 -#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 - -#define IQM_COMM_INT_REQ_CF_REQ__B 1 -#define IQM_COMM_INT_REQ_CF_REQ__W 1 -#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 -#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 - -#define IQM_COMM_INT_REQ_CW_REQ__B 2 -#define IQM_COMM_INT_REQ_CW_REQ__W 1 -#define IQM_COMM_INT_REQ_CW_REQ__M 0x4 -#define IQM_COMM_INT_REQ_CW_REQ__PRE 0x0 - -#define IQM_COMM_INT_STA__A 0x1800005 -#define IQM_COMM_INT_STA__W 16 -#define IQM_COMM_INT_STA__M 0xFFFF -#define IQM_COMM_INT_STA__PRE 0x0 -#define IQM_COMM_INT_STA_B__B 0 -#define IQM_COMM_INT_STA_B__W 16 -#define IQM_COMM_INT_STA_B__M 0xFFFF -#define IQM_COMM_INT_STA_B__PRE 0x0 - -#define IQM_COMM_INT_MSK__A 0x1800006 -#define IQM_COMM_INT_MSK__W 16 -#define IQM_COMM_INT_MSK__M 0xFFFF -#define IQM_COMM_INT_MSK__PRE 0x0 -#define IQM_COMM_INT_MSK_B__B 0 -#define IQM_COMM_INT_MSK_B__W 16 -#define IQM_COMM_INT_MSK_B__M 0xFFFF -#define IQM_COMM_INT_MSK_B__PRE 0x0 - -#define IQM_COMM_INT_STM__A 0x1800007 -#define IQM_COMM_INT_STM__W 16 -#define IQM_COMM_INT_STM__M 0xFFFF -#define IQM_COMM_INT_STM__PRE 0x0 -#define IQM_COMM_INT_STM_B__B 0 -#define IQM_COMM_INT_STM_B__W 16 -#define IQM_COMM_INT_STM_B__M 0xFFFF -#define IQM_COMM_INT_STM_B__PRE 0x0 - - - -#define IQM_FS_COMM_EXEC__A 0x1820000 -#define IQM_FS_COMM_EXEC__W 2 -#define IQM_FS_COMM_EXEC__M 0x3 -#define IQM_FS_COMM_EXEC__PRE 0x0 -#define IQM_FS_COMM_EXEC_STOP 0x0 -#define IQM_FS_COMM_EXEC_ACTIVE 0x1 -#define IQM_FS_COMM_EXEC_HOLD 0x2 - -#define IQM_FS_COMM_MB__A 0x1820002 -#define IQM_FS_COMM_MB__W 4 -#define IQM_FS_COMM_MB__M 0xF -#define IQM_FS_COMM_MB__PRE 0x0 -#define IQM_FS_COMM_MB_CTL__B 0 -#define IQM_FS_COMM_MB_CTL__W 1 -#define IQM_FS_COMM_MB_CTL__M 0x1 -#define IQM_FS_COMM_MB_CTL__PRE 0x0 -#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_FS_COMM_MB_OBS__B 1 -#define IQM_FS_COMM_MB_OBS__W 1 -#define IQM_FS_COMM_MB_OBS__M 0x2 -#define IQM_FS_COMM_MB_OBS__PRE 0x0 -#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 -#define IQM_FS_COMM_MB_CTL_MUX__B 2 -#define IQM_FS_COMM_MB_CTL_MUX__W 1 -#define IQM_FS_COMM_MB_CTL_MUX__M 0x4 -#define IQM_FS_COMM_MB_CTL_MUX__PRE 0x0 -#define IQM_FS_COMM_MB_OBS_MUX__B 3 -#define IQM_FS_COMM_MB_OBS_MUX__W 1 -#define IQM_FS_COMM_MB_OBS_MUX__M 0x8 -#define IQM_FS_COMM_MB_OBS_MUX__PRE 0x0 - -#define IQM_FS_RATE_OFS_LO__A 0x1820010 -#define IQM_FS_RATE_OFS_LO__W 16 -#define IQM_FS_RATE_OFS_LO__M 0xFFFF -#define IQM_FS_RATE_OFS_LO__PRE 0x0 -#define IQM_FS_RATE_OFS_LO_B__B 0 -#define IQM_FS_RATE_OFS_LO_B__W 16 -#define IQM_FS_RATE_OFS_LO_B__M 0xFFFF -#define IQM_FS_RATE_OFS_LO_B__PRE 0x0 - -#define IQM_FS_RATE_OFS_HI__A 0x1820011 -#define IQM_FS_RATE_OFS_HI__W 12 -#define IQM_FS_RATE_OFS_HI__M 0xFFF -#define IQM_FS_RATE_OFS_HI__PRE 0x0 -#define IQM_FS_RATE_OFS_HI_B__B 0 -#define IQM_FS_RATE_OFS_HI_B__W 12 -#define IQM_FS_RATE_OFS_HI_B__M 0xFFF -#define IQM_FS_RATE_OFS_HI_B__PRE 0x0 - -#define IQM_FS_RATE_LO__A 0x1820012 -#define IQM_FS_RATE_LO__W 16 -#define IQM_FS_RATE_LO__M 0xFFFF -#define IQM_FS_RATE_LO__PRE 0x0 -#define IQM_FS_RATE_LO_B__B 0 -#define IQM_FS_RATE_LO_B__W 16 -#define IQM_FS_RATE_LO_B__M 0xFFFF -#define IQM_FS_RATE_LO_B__PRE 0x0 - -#define IQM_FS_RATE_HI__A 0x1820013 -#define IQM_FS_RATE_HI__W 12 -#define IQM_FS_RATE_HI__M 0xFFF -#define IQM_FS_RATE_HI__PRE 0x0 -#define IQM_FS_RATE_HI_B__B 0 -#define IQM_FS_RATE_HI_B__W 12 -#define IQM_FS_RATE_HI_B__M 0xFFF -#define IQM_FS_RATE_HI_B__PRE 0x0 - -#define IQM_FS_ADJ_SEL__A 0x1820014 -#define IQM_FS_ADJ_SEL__W 2 -#define IQM_FS_ADJ_SEL__M 0x3 -#define IQM_FS_ADJ_SEL__PRE 0x0 - -#define IQM_FS_ADJ_SEL_B__B 0 -#define IQM_FS_ADJ_SEL_B__W 2 -#define IQM_FS_ADJ_SEL_B__M 0x3 -#define IQM_FS_ADJ_SEL_B__PRE 0x0 -#define IQM_FS_ADJ_SEL_B_OFF 0x0 -#define IQM_FS_ADJ_SEL_B_QAM 0x1 -#define IQM_FS_ADJ_SEL_B_VSB 0x2 - - - -#define IQM_FD_COMM_EXEC__A 0x1830000 -#define IQM_FD_COMM_EXEC__W 2 -#define IQM_FD_COMM_EXEC__M 0x3 -#define IQM_FD_COMM_EXEC__PRE 0x0 -#define IQM_FD_COMM_EXEC_STOP 0x0 -#define IQM_FD_COMM_EXEC_ACTIVE 0x1 -#define IQM_FD_COMM_EXEC_HOLD 0x2 - -#define IQM_FD_COMM_MB__A 0x1830002 -#define IQM_FD_COMM_MB__W 2 -#define IQM_FD_COMM_MB__M 0x3 -#define IQM_FD_COMM_MB__PRE 0x0 -#define IQM_FD_COMM_MB_CTL__B 0 -#define IQM_FD_COMM_MB_CTL__W 1 -#define IQM_FD_COMM_MB_CTL__M 0x1 -#define IQM_FD_COMM_MB_CTL__PRE 0x0 -#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_FD_COMM_MB_OBS__B 1 -#define IQM_FD_COMM_MB_OBS__W 1 -#define IQM_FD_COMM_MB_OBS__M 0x2 -#define IQM_FD_COMM_MB_OBS__PRE 0x0 -#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 - -#define IQM_FD_RATESEL__A 0x1830010 -#define IQM_FD_RATESEL__W 2 -#define IQM_FD_RATESEL__M 0x3 -#define IQM_FD_RATESEL__PRE 0x0 -#define IQM_FD_RATESEL_B__B 0 -#define IQM_FD_RATESEL_B__W 2 -#define IQM_FD_RATESEL_B__M 0x3 -#define IQM_FD_RATESEL_B__PRE 0x0 -#define IQM_FD_RATESEL_B_DS0 0x0 -#define IQM_FD_RATESEL_B_DS1 0x1 -#define IQM_FD_RATESEL_B_DS2 0x2 -#define IQM_FD_RATESEL_B_DS3 0x3 - - - -#define IQM_RC_COMM_EXEC__A 0x1840000 -#define IQM_RC_COMM_EXEC__W 2 -#define IQM_RC_COMM_EXEC__M 0x3 -#define IQM_RC_COMM_EXEC__PRE 0x0 -#define IQM_RC_COMM_EXEC_STOP 0x0 -#define IQM_RC_COMM_EXEC_ACTIVE 0x1 -#define IQM_RC_COMM_EXEC_HOLD 0x2 - -#define IQM_RC_COMM_MB__A 0x1840002 -#define IQM_RC_COMM_MB__W 2 -#define IQM_RC_COMM_MB__M 0x3 -#define IQM_RC_COMM_MB__PRE 0x0 -#define IQM_RC_COMM_MB_CTL__B 0 -#define IQM_RC_COMM_MB_CTL__W 1 -#define IQM_RC_COMM_MB_CTL__M 0x1 -#define IQM_RC_COMM_MB_CTL__PRE 0x0 -#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_RC_COMM_MB_OBS__B 1 -#define IQM_RC_COMM_MB_OBS__W 1 -#define IQM_RC_COMM_MB_OBS__M 0x2 -#define IQM_RC_COMM_MB_OBS__PRE 0x0 -#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 - -#define IQM_RC_RATE_OFS_LO__A 0x1840010 -#define IQM_RC_RATE_OFS_LO__W 16 -#define IQM_RC_RATE_OFS_LO__M 0xFFFF -#define IQM_RC_RATE_OFS_LO__PRE 0x0 -#define IQM_RC_RATE_OFS_LO_B__B 0 -#define IQM_RC_RATE_OFS_LO_B__W 16 -#define IQM_RC_RATE_OFS_LO_B__M 0xFFFF -#define IQM_RC_RATE_OFS_LO_B__PRE 0x0 - -#define IQM_RC_RATE_OFS_HI__A 0x1840011 -#define IQM_RC_RATE_OFS_HI__W 8 -#define IQM_RC_RATE_OFS_HI__M 0xFF -#define IQM_RC_RATE_OFS_HI__PRE 0x0 -#define IQM_RC_RATE_OFS_HI_B__B 0 -#define IQM_RC_RATE_OFS_HI_B__W 8 -#define IQM_RC_RATE_OFS_HI_B__M 0xFF -#define IQM_RC_RATE_OFS_HI_B__PRE 0x0 - -#define IQM_RC_RATE_LO__A 0x1840012 -#define IQM_RC_RATE_LO__W 16 -#define IQM_RC_RATE_LO__M 0xFFFF -#define IQM_RC_RATE_LO__PRE 0x0 -#define IQM_RC_RATE_LO_B__B 0 -#define IQM_RC_RATE_LO_B__W 16 -#define IQM_RC_RATE_LO_B__M 0xFFFF -#define IQM_RC_RATE_LO_B__PRE 0x0 - -#define IQM_RC_RATE_HI__A 0x1840013 -#define IQM_RC_RATE_HI__W 8 -#define IQM_RC_RATE_HI__M 0xFF -#define IQM_RC_RATE_HI__PRE 0x0 -#define IQM_RC_RATE_HI_B__B 0 -#define IQM_RC_RATE_HI_B__W 8 -#define IQM_RC_RATE_HI_B__M 0xFF -#define IQM_RC_RATE_HI_B__PRE 0x0 - -#define IQM_RC_ADJ_SEL__A 0x1840014 -#define IQM_RC_ADJ_SEL__W 2 -#define IQM_RC_ADJ_SEL__M 0x3 -#define IQM_RC_ADJ_SEL__PRE 0x0 - -#define IQM_RC_ADJ_SEL_B__B 0 -#define IQM_RC_ADJ_SEL_B__W 2 -#define IQM_RC_ADJ_SEL_B__M 0x3 -#define IQM_RC_ADJ_SEL_B__PRE 0x0 -#define IQM_RC_ADJ_SEL_B_OFF 0x0 -#define IQM_RC_ADJ_SEL_B_QAM 0x1 -#define IQM_RC_ADJ_SEL_B_VSB 0x2 - -#define IQM_RC_CROUT_ENA__A 0x1840015 -#define IQM_RC_CROUT_ENA__W 1 -#define IQM_RC_CROUT_ENA__M 0x1 -#define IQM_RC_CROUT_ENA__PRE 0x0 - -#define IQM_RC_CROUT_ENA_ENA__B 0 -#define IQM_RC_CROUT_ENA_ENA__W 1 -#define IQM_RC_CROUT_ENA_ENA__M 0x1 -#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 - -#define IQM_RC_STRETCH__A 0x1840016 -#define IQM_RC_STRETCH__W 5 -#define IQM_RC_STRETCH__M 0x1F -#define IQM_RC_STRETCH__PRE 0x0 - -#define IQM_RC_STRETCH_B__B 0 -#define IQM_RC_STRETCH_B__W 5 -#define IQM_RC_STRETCH_B__M 0x1F -#define IQM_RC_STRETCH_B__PRE 0x0 - - - -#define IQM_RT_COMM_EXEC__A 0x1850000 -#define IQM_RT_COMM_EXEC__W 2 -#define IQM_RT_COMM_EXEC__M 0x3 -#define IQM_RT_COMM_EXEC__PRE 0x0 -#define IQM_RT_COMM_EXEC_STOP 0x0 -#define IQM_RT_COMM_EXEC_ACTIVE 0x1 -#define IQM_RT_COMM_EXEC_HOLD 0x2 - -#define IQM_RT_COMM_MB__A 0x1850002 -#define IQM_RT_COMM_MB__W 2 -#define IQM_RT_COMM_MB__M 0x3 -#define IQM_RT_COMM_MB__PRE 0x0 -#define IQM_RT_COMM_MB_CTL__B 0 -#define IQM_RT_COMM_MB_CTL__W 1 -#define IQM_RT_COMM_MB_CTL__M 0x1 -#define IQM_RT_COMM_MB_CTL__PRE 0x0 -#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_RT_COMM_MB_OBS__B 1 -#define IQM_RT_COMM_MB_OBS__W 1 -#define IQM_RT_COMM_MB_OBS__M 0x2 -#define IQM_RT_COMM_MB_OBS__PRE 0x0 -#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 - -#define IQM_RT_ACTIVE__A 0x1850010 -#define IQM_RT_ACTIVE__W 2 -#define IQM_RT_ACTIVE__M 0x3 -#define IQM_RT_ACTIVE__PRE 0x0 - -#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 -#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 -#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 -#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 -#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 -#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 - -#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 -#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 -#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 -#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 -#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 -#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 - - -#define IQM_RT_LO_INCR__A 0x1850011 -#define IQM_RT_LO_INCR__W 12 -#define IQM_RT_LO_INCR__M 0xFFF -#define IQM_RT_LO_INCR__PRE 0x588 -#define IQM_RT_LO_INCR_FM 0x0 -#define IQM_RT_LO_INCR_MN 0x588 - -#define IQM_RT_ROT_BP__A 0x1850012 -#define IQM_RT_ROT_BP__W 3 -#define IQM_RT_ROT_BP__M 0x7 -#define IQM_RT_ROT_BP__PRE 0x0 - -#define IQM_RT_ROT_BP_ROT_OFF__B 0 -#define IQM_RT_ROT_BP_ROT_OFF__W 1 -#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 -#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 -#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 -#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 - -#define IQM_RT_ROT_BP_ROT_BPF__B 1 -#define IQM_RT_ROT_BP_ROT_BPF__W 1 -#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 -#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 - -#define IQM_RT_ROT_BP_MIX_BP__B 2 -#define IQM_RT_ROT_BP_MIX_BP__W 1 -#define IQM_RT_ROT_BP_MIX_BP__M 0x4 -#define IQM_RT_ROT_BP_MIX_BP__PRE 0x0 - - -#define IQM_RT_LP_BP__A 0x1850013 -#define IQM_RT_LP_BP__W 1 -#define IQM_RT_LP_BP__M 0x1 -#define IQM_RT_LP_BP__PRE 0x0 - -#define IQM_RT_DELAY__A 0x1850014 -#define IQM_RT_DELAY__W 7 -#define IQM_RT_DELAY__M 0x7F -#define IQM_RT_DELAY__PRE 0x45 - - - -#define IQM_CF_COMM_EXEC__A 0x1860000 -#define IQM_CF_COMM_EXEC__W 2 -#define IQM_CF_COMM_EXEC__M 0x3 -#define IQM_CF_COMM_EXEC__PRE 0x0 -#define IQM_CF_COMM_EXEC_STOP 0x0 -#define IQM_CF_COMM_EXEC_ACTIVE 0x1 -#define IQM_CF_COMM_EXEC_HOLD 0x2 - -#define IQM_CF_COMM_MB__A 0x1860002 -#define IQM_CF_COMM_MB__W 2 -#define IQM_CF_COMM_MB__M 0x3 -#define IQM_CF_COMM_MB__PRE 0x0 -#define IQM_CF_COMM_MB_CTL__B 0 -#define IQM_CF_COMM_MB_CTL__W 1 -#define IQM_CF_COMM_MB_CTL__M 0x1 -#define IQM_CF_COMM_MB_CTL__PRE 0x0 -#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_CF_COMM_MB_OBS__B 1 -#define IQM_CF_COMM_MB_OBS__W 1 -#define IQM_CF_COMM_MB_OBS__M 0x2 -#define IQM_CF_COMM_MB_OBS__PRE 0x0 -#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 - -#define IQM_CF_COMM_INT_REQ__A 0x1860003 -#define IQM_CF_COMM_INT_REQ__W 1 -#define IQM_CF_COMM_INT_REQ__M 0x1 -#define IQM_CF_COMM_INT_REQ__PRE 0x0 -#define IQM_CF_COMM_INT_STA__A 0x1860005 -#define IQM_CF_COMM_INT_STA__W 2 -#define IQM_CF_COMM_INT_STA__M 0x3 -#define IQM_CF_COMM_INT_STA__PRE 0x0 -#define IQM_CF_COMM_INT_STA_PM__B 0 -#define IQM_CF_COMM_INT_STA_PM__W 1 -#define IQM_CF_COMM_INT_STA_PM__M 0x1 -#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 -#define IQM_CF_COMM_INT_STA_INC__B 1 -#define IQM_CF_COMM_INT_STA_INC__W 1 -#define IQM_CF_COMM_INT_STA_INC__M 0x2 -#define IQM_CF_COMM_INT_STA_INC__PRE 0x0 - -#define IQM_CF_COMM_INT_MSK__A 0x1860006 -#define IQM_CF_COMM_INT_MSK__W 2 -#define IQM_CF_COMM_INT_MSK__M 0x3 -#define IQM_CF_COMM_INT_MSK__PRE 0x0 -#define IQM_CF_COMM_INT_MSK_PM__B 0 -#define IQM_CF_COMM_INT_MSK_PM__W 1 -#define IQM_CF_COMM_INT_MSK_PM__M 0x1 -#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 -#define IQM_CF_COMM_INT_MSK_INC__B 1 -#define IQM_CF_COMM_INT_MSK_INC__W 1 -#define IQM_CF_COMM_INT_MSK_INC__M 0x2 -#define IQM_CF_COMM_INT_MSK_INC__PRE 0x0 - -#define IQM_CF_COMM_INT_STM__A 0x1860007 -#define IQM_CF_COMM_INT_STM__W 2 -#define IQM_CF_COMM_INT_STM__M 0x3 -#define IQM_CF_COMM_INT_STM__PRE 0x0 -#define IQM_CF_COMM_INT_STM_PM__B 0 -#define IQM_CF_COMM_INT_STM_PM__W 1 -#define IQM_CF_COMM_INT_STM_PM__M 0x1 -#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 -#define IQM_CF_COMM_INT_STM_INC__B 1 -#define IQM_CF_COMM_INT_STM_INC__W 1 -#define IQM_CF_COMM_INT_STM_INC__M 0x2 -#define IQM_CF_COMM_INT_STM_INC__PRE 0x0 - -#define IQM_CF_SYMMETRIC__A 0x1860010 -#define IQM_CF_SYMMETRIC__W 2 -#define IQM_CF_SYMMETRIC__M 0x3 -#define IQM_CF_SYMMETRIC__PRE 0x0 - -#define IQM_CF_SYMMETRIC_RE__B 0 -#define IQM_CF_SYMMETRIC_RE__W 1 -#define IQM_CF_SYMMETRIC_RE__M 0x1 -#define IQM_CF_SYMMETRIC_RE__PRE 0x0 - -#define IQM_CF_SYMMETRIC_IM__B 1 -#define IQM_CF_SYMMETRIC_IM__W 1 -#define IQM_CF_SYMMETRIC_IM__M 0x2 -#define IQM_CF_SYMMETRIC_IM__PRE 0x0 - -#define IQM_CF_MIDTAP__A 0x1860011 -#define IQM_CF_MIDTAP__W 3 -#define IQM_CF_MIDTAP__M 0x7 -#define IQM_CF_MIDTAP__PRE 0x3 - -#define IQM_CF_MIDTAP_RE__B 0 -#define IQM_CF_MIDTAP_RE__W 1 -#define IQM_CF_MIDTAP_RE__M 0x1 -#define IQM_CF_MIDTAP_RE__PRE 0x1 - -#define IQM_CF_MIDTAP_IM__B 1 -#define IQM_CF_MIDTAP_IM__W 1 -#define IQM_CF_MIDTAP_IM__M 0x2 -#define IQM_CF_MIDTAP_IM__PRE 0x2 - -#define IQM_CF_MIDTAP_SCALE__B 2 -#define IQM_CF_MIDTAP_SCALE__W 1 -#define IQM_CF_MIDTAP_SCALE__M 0x4 -#define IQM_CF_MIDTAP_SCALE__PRE 0x0 - -#define IQM_CF_OUT_ENA__A 0x1860012 -#define IQM_CF_OUT_ENA__W 3 -#define IQM_CF_OUT_ENA__M 0x7 -#define IQM_CF_OUT_ENA__PRE 0x0 - -#define IQM_CF_OUT_ENA_ATV__B 0 -#define IQM_CF_OUT_ENA_ATV__W 1 -#define IQM_CF_OUT_ENA_ATV__M 0x1 -#define IQM_CF_OUT_ENA_ATV__PRE 0x0 - -#define IQM_CF_OUT_ENA_QAM__B 1 -#define IQM_CF_OUT_ENA_QAM__W 1 -#define IQM_CF_OUT_ENA_QAM__M 0x2 -#define IQM_CF_OUT_ENA_QAM__PRE 0x0 - -#define IQM_CF_OUT_ENA_OFDM__B 2 -#define IQM_CF_OUT_ENA_OFDM__W 1 -#define IQM_CF_OUT_ENA_OFDM__M 0x4 -#define IQM_CF_OUT_ENA_OFDM__PRE 0x0 - -#define IQM_CF_ADJ_SEL__A 0x1860013 -#define IQM_CF_ADJ_SEL__W 2 -#define IQM_CF_ADJ_SEL__M 0x3 -#define IQM_CF_ADJ_SEL__PRE 0x0 - -#define IQM_CF_ADJ_SEL_B__B 0 -#define IQM_CF_ADJ_SEL_B__W 2 -#define IQM_CF_ADJ_SEL_B__M 0x3 -#define IQM_CF_ADJ_SEL_B__PRE 0x0 - -#define IQM_CF_SCALE__A 0x1860014 -#define IQM_CF_SCALE__W 14 -#define IQM_CF_SCALE__M 0x3FFF -#define IQM_CF_SCALE__PRE 0x400 -#define IQM_CF_SCALE_B__B 0 -#define IQM_CF_SCALE_B__W 14 -#define IQM_CF_SCALE_B__M 0x3FFF -#define IQM_CF_SCALE_B__PRE 0x400 - -#define IQM_CF_SCALE_SH__A 0x1860015 -#define IQM_CF_SCALE_SH__W 2 -#define IQM_CF_SCALE_SH__M 0x3 -#define IQM_CF_SCALE_SH__PRE 0x0 - -#define IQM_CF_SCALE_SH_B__B 0 -#define IQM_CF_SCALE_SH_B__W 2 -#define IQM_CF_SCALE_SH_B__M 0x3 -#define IQM_CF_SCALE_SH_B__PRE 0x0 - -#define IQM_CF_AMP__A 0x1860016 -#define IQM_CF_AMP__W 14 -#define IQM_CF_AMP__M 0x3FFF -#define IQM_CF_AMP__PRE 0x0 - -#define IQM_CF_AMP_B__B 0 -#define IQM_CF_AMP_B__W 14 -#define IQM_CF_AMP_B__M 0x3FFF -#define IQM_CF_AMP_B__PRE 0x0 - -#define IQM_CF_POW_MEAS_LEN__A 0x1860017 -#define IQM_CF_POW_MEAS_LEN__W 3 -#define IQM_CF_POW_MEAS_LEN__M 0x7 -#define IQM_CF_POW_MEAS_LEN__PRE 0x2 - -#define IQM_CF_POW_MEAS_LEN_B__B 0 -#define IQM_CF_POW_MEAS_LEN_B__W 3 -#define IQM_CF_POW_MEAS_LEN_B__M 0x7 -#define IQM_CF_POW_MEAS_LEN_B__PRE 0x2 - -#define IQM_CF_POW__A 0x1860018 -#define IQM_CF_POW__W 16 -#define IQM_CF_POW__M 0xFFFF -#define IQM_CF_POW__PRE 0x2 -#define IQM_CF_POW_B__B 0 -#define IQM_CF_POW_B__W 16 -#define IQM_CF_POW_B__M 0xFFFF -#define IQM_CF_POW_B__PRE 0x2 - -#define IQM_CF_DS_ENA__A 0x1860019 -#define IQM_CF_DS_ENA__W 3 -#define IQM_CF_DS_ENA__M 0x7 -#define IQM_CF_DS_ENA__PRE 0x4 - -#define IQM_CF_DS_ENA_ATV__B 0 -#define IQM_CF_DS_ENA_ATV__W 1 -#define IQM_CF_DS_ENA_ATV__M 0x1 -#define IQM_CF_DS_ENA_ATV__PRE 0x0 - -#define IQM_CF_DS_ENA_QAM__B 1 -#define IQM_CF_DS_ENA_QAM__W 1 -#define IQM_CF_DS_ENA_QAM__M 0x2 -#define IQM_CF_DS_ENA_QAM__PRE 0x0 - -#define IQM_CF_DS_ENA_VSB__B 2 -#define IQM_CF_DS_ENA_VSB__W 1 -#define IQM_CF_DS_ENA_VSB__M 0x4 -#define IQM_CF_DS_ENA_VSB__PRE 0x4 - - -#define IQM_CF_POW_UPD__A 0x186001A -#define IQM_CF_POW_UPD__W 1 -#define IQM_CF_POW_UPD__M 0x1 -#define IQM_CF_POW_UPD__PRE 0x0 -#define IQM_CF_TAP_RE0__A 0x1860020 -#define IQM_CF_TAP_RE0__W 7 -#define IQM_CF_TAP_RE0__M 0x7F -#define IQM_CF_TAP_RE0__PRE 0x2 -#define IQM_CF_TAP_RE0_B__B 0 -#define IQM_CF_TAP_RE0_B__W 7 -#define IQM_CF_TAP_RE0_B__M 0x7F -#define IQM_CF_TAP_RE0_B__PRE 0x2 - -#define IQM_CF_TAP_RE1__A 0x1860021 -#define IQM_CF_TAP_RE1__W 7 -#define IQM_CF_TAP_RE1__M 0x7F -#define IQM_CF_TAP_RE1__PRE 0x2 -#define IQM_CF_TAP_RE1_B__B 0 -#define IQM_CF_TAP_RE1_B__W 7 -#define IQM_CF_TAP_RE1_B__M 0x7F -#define IQM_CF_TAP_RE1_B__PRE 0x2 - -#define IQM_CF_TAP_RE2__A 0x1860022 -#define IQM_CF_TAP_RE2__W 7 -#define IQM_CF_TAP_RE2__M 0x7F -#define IQM_CF_TAP_RE2__PRE 0x2 -#define IQM_CF_TAP_RE2_B__B 0 -#define IQM_CF_TAP_RE2_B__W 7 -#define IQM_CF_TAP_RE2_B__M 0x7F -#define IQM_CF_TAP_RE2_B__PRE 0x2 - -#define IQM_CF_TAP_RE3__A 0x1860023 -#define IQM_CF_TAP_RE3__W 7 -#define IQM_CF_TAP_RE3__M 0x7F -#define IQM_CF_TAP_RE3__PRE 0x2 -#define IQM_CF_TAP_RE3_B__B 0 -#define IQM_CF_TAP_RE3_B__W 7 -#define IQM_CF_TAP_RE3_B__M 0x7F -#define IQM_CF_TAP_RE3_B__PRE 0x2 - -#define IQM_CF_TAP_RE4__A 0x1860024 -#define IQM_CF_TAP_RE4__W 7 -#define IQM_CF_TAP_RE4__M 0x7F -#define IQM_CF_TAP_RE4__PRE 0x2 -#define IQM_CF_TAP_RE4_B__B 0 -#define IQM_CF_TAP_RE4_B__W 7 -#define IQM_CF_TAP_RE4_B__M 0x7F -#define IQM_CF_TAP_RE4_B__PRE 0x2 - -#define IQM_CF_TAP_RE5__A 0x1860025 -#define IQM_CF_TAP_RE5__W 7 -#define IQM_CF_TAP_RE5__M 0x7F -#define IQM_CF_TAP_RE5__PRE 0x2 -#define IQM_CF_TAP_RE5_B__B 0 -#define IQM_CF_TAP_RE5_B__W 7 -#define IQM_CF_TAP_RE5_B__M 0x7F -#define IQM_CF_TAP_RE5_B__PRE 0x2 - -#define IQM_CF_TAP_RE6__A 0x1860026 -#define IQM_CF_TAP_RE6__W 7 -#define IQM_CF_TAP_RE6__M 0x7F -#define IQM_CF_TAP_RE6__PRE 0x2 -#define IQM_CF_TAP_RE6_B__B 0 -#define IQM_CF_TAP_RE6_B__W 7 -#define IQM_CF_TAP_RE6_B__M 0x7F -#define IQM_CF_TAP_RE6_B__PRE 0x2 - -#define IQM_CF_TAP_RE7__A 0x1860027 -#define IQM_CF_TAP_RE7__W 9 -#define IQM_CF_TAP_RE7__M 0x1FF -#define IQM_CF_TAP_RE7__PRE 0x2 -#define IQM_CF_TAP_RE7_B__B 0 -#define IQM_CF_TAP_RE7_B__W 9 -#define IQM_CF_TAP_RE7_B__M 0x1FF -#define IQM_CF_TAP_RE7_B__PRE 0x2 - -#define IQM_CF_TAP_RE8__A 0x1860028 -#define IQM_CF_TAP_RE8__W 9 -#define IQM_CF_TAP_RE8__M 0x1FF -#define IQM_CF_TAP_RE8__PRE 0x2 -#define IQM_CF_TAP_RE8_B__B 0 -#define IQM_CF_TAP_RE8_B__W 9 -#define IQM_CF_TAP_RE8_B__M 0x1FF -#define IQM_CF_TAP_RE8_B__PRE 0x2 - -#define IQM_CF_TAP_RE9__A 0x1860029 -#define IQM_CF_TAP_RE9__W 9 -#define IQM_CF_TAP_RE9__M 0x1FF -#define IQM_CF_TAP_RE9__PRE 0x2 -#define IQM_CF_TAP_RE9_B__B 0 -#define IQM_CF_TAP_RE9_B__W 9 -#define IQM_CF_TAP_RE9_B__M 0x1FF -#define IQM_CF_TAP_RE9_B__PRE 0x2 - -#define IQM_CF_TAP_RE10__A 0x186002A -#define IQM_CF_TAP_RE10__W 9 -#define IQM_CF_TAP_RE10__M 0x1FF -#define IQM_CF_TAP_RE10__PRE 0x2 -#define IQM_CF_TAP_RE10_B__B 0 -#define IQM_CF_TAP_RE10_B__W 9 -#define IQM_CF_TAP_RE10_B__M 0x1FF -#define IQM_CF_TAP_RE10_B__PRE 0x2 - -#define IQM_CF_TAP_RE11__A 0x186002B -#define IQM_CF_TAP_RE11__W 9 -#define IQM_CF_TAP_RE11__M 0x1FF -#define IQM_CF_TAP_RE11__PRE 0x2 -#define IQM_CF_TAP_RE11_B__B 0 -#define IQM_CF_TAP_RE11_B__W 9 -#define IQM_CF_TAP_RE11_B__M 0x1FF -#define IQM_CF_TAP_RE11_B__PRE 0x2 - -#define IQM_CF_TAP_RE12__A 0x186002C -#define IQM_CF_TAP_RE12__W 9 -#define IQM_CF_TAP_RE12__M 0x1FF -#define IQM_CF_TAP_RE12__PRE 0x2 -#define IQM_CF_TAP_RE12_B__B 0 -#define IQM_CF_TAP_RE12_B__W 9 -#define IQM_CF_TAP_RE12_B__M 0x1FF -#define IQM_CF_TAP_RE12_B__PRE 0x2 - -#define IQM_CF_TAP_RE13__A 0x186002D -#define IQM_CF_TAP_RE13__W 9 -#define IQM_CF_TAP_RE13__M 0x1FF -#define IQM_CF_TAP_RE13__PRE 0x2 -#define IQM_CF_TAP_RE13_B__B 0 -#define IQM_CF_TAP_RE13_B__W 9 -#define IQM_CF_TAP_RE13_B__M 0x1FF -#define IQM_CF_TAP_RE13_B__PRE 0x2 - -#define IQM_CF_TAP_RE14__A 0x186002E -#define IQM_CF_TAP_RE14__W 9 -#define IQM_CF_TAP_RE14__M 0x1FF -#define IQM_CF_TAP_RE14__PRE 0x2 -#define IQM_CF_TAP_RE14_B__B 0 -#define IQM_CF_TAP_RE14_B__W 9 -#define IQM_CF_TAP_RE14_B__M 0x1FF -#define IQM_CF_TAP_RE14_B__PRE 0x2 - -#define IQM_CF_TAP_RE15__A 0x186002F -#define IQM_CF_TAP_RE15__W 9 -#define IQM_CF_TAP_RE15__M 0x1FF -#define IQM_CF_TAP_RE15__PRE 0x2 -#define IQM_CF_TAP_RE15_B__B 0 -#define IQM_CF_TAP_RE15_B__W 9 -#define IQM_CF_TAP_RE15_B__M 0x1FF -#define IQM_CF_TAP_RE15_B__PRE 0x2 - -#define IQM_CF_TAP_RE16__A 0x1860030 -#define IQM_CF_TAP_RE16__W 9 -#define IQM_CF_TAP_RE16__M 0x1FF -#define IQM_CF_TAP_RE16__PRE 0x2 -#define IQM_CF_TAP_RE16_B__B 0 -#define IQM_CF_TAP_RE16_B__W 9 -#define IQM_CF_TAP_RE16_B__M 0x1FF -#define IQM_CF_TAP_RE16_B__PRE 0x2 - -#define IQM_CF_TAP_RE17__A 0x1860031 -#define IQM_CF_TAP_RE17__W 9 -#define IQM_CF_TAP_RE17__M 0x1FF -#define IQM_CF_TAP_RE17__PRE 0x2 -#define IQM_CF_TAP_RE17_B__B 0 -#define IQM_CF_TAP_RE17_B__W 9 -#define IQM_CF_TAP_RE17_B__M 0x1FF -#define IQM_CF_TAP_RE17_B__PRE 0x2 - -#define IQM_CF_TAP_RE18__A 0x1860032 -#define IQM_CF_TAP_RE18__W 9 -#define IQM_CF_TAP_RE18__M 0x1FF -#define IQM_CF_TAP_RE18__PRE 0x2 -#define IQM_CF_TAP_RE18_B__B 0 -#define IQM_CF_TAP_RE18_B__W 9 -#define IQM_CF_TAP_RE18_B__M 0x1FF -#define IQM_CF_TAP_RE18_B__PRE 0x2 - -#define IQM_CF_TAP_RE19__A 0x1860033 -#define IQM_CF_TAP_RE19__W 9 -#define IQM_CF_TAP_RE19__M 0x1FF -#define IQM_CF_TAP_RE19__PRE 0x2 -#define IQM_CF_TAP_RE19_B__B 0 -#define IQM_CF_TAP_RE19_B__W 9 -#define IQM_CF_TAP_RE19_B__M 0x1FF -#define IQM_CF_TAP_RE19_B__PRE 0x2 - -#define IQM_CF_TAP_RE20__A 0x1860034 -#define IQM_CF_TAP_RE20__W 9 -#define IQM_CF_TAP_RE20__M 0x1FF -#define IQM_CF_TAP_RE20__PRE 0x2 -#define IQM_CF_TAP_RE20_B__B 0 -#define IQM_CF_TAP_RE20_B__W 9 -#define IQM_CF_TAP_RE20_B__M 0x1FF -#define IQM_CF_TAP_RE20_B__PRE 0x2 - -#define IQM_CF_TAP_RE21__A 0x1860035 -#define IQM_CF_TAP_RE21__W 11 -#define IQM_CF_TAP_RE21__M 0x7FF -#define IQM_CF_TAP_RE21__PRE 0x2 -#define IQM_CF_TAP_RE21_B__B 0 -#define IQM_CF_TAP_RE21_B__W 11 -#define IQM_CF_TAP_RE21_B__M 0x7FF -#define IQM_CF_TAP_RE21_B__PRE 0x2 - -#define IQM_CF_TAP_RE22__A 0x1860036 -#define IQM_CF_TAP_RE22__W 11 -#define IQM_CF_TAP_RE22__M 0x7FF -#define IQM_CF_TAP_RE22__PRE 0x2 -#define IQM_CF_TAP_RE22_B__B 0 -#define IQM_CF_TAP_RE22_B__W 11 -#define IQM_CF_TAP_RE22_B__M 0x7FF -#define IQM_CF_TAP_RE22_B__PRE 0x2 - -#define IQM_CF_TAP_RE23__A 0x1860037 -#define IQM_CF_TAP_RE23__W 11 -#define IQM_CF_TAP_RE23__M 0x7FF -#define IQM_CF_TAP_RE23__PRE 0x2 -#define IQM_CF_TAP_RE23_B__B 0 -#define IQM_CF_TAP_RE23_B__W 11 -#define IQM_CF_TAP_RE23_B__M 0x7FF -#define IQM_CF_TAP_RE23_B__PRE 0x2 - -#define IQM_CF_TAP_RE24__A 0x1860038 -#define IQM_CF_TAP_RE24__W 11 -#define IQM_CF_TAP_RE24__M 0x7FF -#define IQM_CF_TAP_RE24__PRE 0x2 -#define IQM_CF_TAP_RE24_B__B 0 -#define IQM_CF_TAP_RE24_B__W 11 -#define IQM_CF_TAP_RE24_B__M 0x7FF -#define IQM_CF_TAP_RE24_B__PRE 0x2 - -#define IQM_CF_TAP_RE25__A 0x1860039 -#define IQM_CF_TAP_RE25__W 11 -#define IQM_CF_TAP_RE25__M 0x7FF -#define IQM_CF_TAP_RE25__PRE 0x2 -#define IQM_CF_TAP_RE25_B__B 0 -#define IQM_CF_TAP_RE25_B__W 11 -#define IQM_CF_TAP_RE25_B__M 0x7FF -#define IQM_CF_TAP_RE25_B__PRE 0x2 - -#define IQM_CF_TAP_RE26__A 0x186003A -#define IQM_CF_TAP_RE26__W 11 -#define IQM_CF_TAP_RE26__M 0x7FF -#define IQM_CF_TAP_RE26__PRE 0x2 -#define IQM_CF_TAP_RE26_B__B 0 -#define IQM_CF_TAP_RE26_B__W 11 -#define IQM_CF_TAP_RE26_B__M 0x7FF -#define IQM_CF_TAP_RE26_B__PRE 0x2 - -#define IQM_CF_TAP_RE27__A 0x186003B -#define IQM_CF_TAP_RE27__W 11 -#define IQM_CF_TAP_RE27__M 0x7FF -#define IQM_CF_TAP_RE27__PRE 0x2 -#define IQM_CF_TAP_RE27_B__B 0 -#define IQM_CF_TAP_RE27_B__W 11 -#define IQM_CF_TAP_RE27_B__M 0x7FF -#define IQM_CF_TAP_RE27_B__PRE 0x2 - -#define IQM_CF_TAP_IM0__A 0x1860040 -#define IQM_CF_TAP_IM0__W 7 -#define IQM_CF_TAP_IM0__M 0x7F -#define IQM_CF_TAP_IM0__PRE 0x2 -#define IQM_CF_TAP_IM0_B__B 0 -#define IQM_CF_TAP_IM0_B__W 7 -#define IQM_CF_TAP_IM0_B__M 0x7F -#define IQM_CF_TAP_IM0_B__PRE 0x2 - -#define IQM_CF_TAP_IM1__A 0x1860041 -#define IQM_CF_TAP_IM1__W 7 -#define IQM_CF_TAP_IM1__M 0x7F -#define IQM_CF_TAP_IM1__PRE 0x2 -#define IQM_CF_TAP_IM1_B__B 0 -#define IQM_CF_TAP_IM1_B__W 7 -#define IQM_CF_TAP_IM1_B__M 0x7F -#define IQM_CF_TAP_IM1_B__PRE 0x2 - -#define IQM_CF_TAP_IM2__A 0x1860042 -#define IQM_CF_TAP_IM2__W 7 -#define IQM_CF_TAP_IM2__M 0x7F -#define IQM_CF_TAP_IM2__PRE 0x2 -#define IQM_CF_TAP_IM2_B__B 0 -#define IQM_CF_TAP_IM2_B__W 7 -#define IQM_CF_TAP_IM2_B__M 0x7F -#define IQM_CF_TAP_IM2_B__PRE 0x2 - -#define IQM_CF_TAP_IM3__A 0x1860043 -#define IQM_CF_TAP_IM3__W 7 -#define IQM_CF_TAP_IM3__M 0x7F -#define IQM_CF_TAP_IM3__PRE 0x2 -#define IQM_CF_TAP_IM3_B__B 0 -#define IQM_CF_TAP_IM3_B__W 7 -#define IQM_CF_TAP_IM3_B__M 0x7F -#define IQM_CF_TAP_IM3_B__PRE 0x2 - -#define IQM_CF_TAP_IM4__A 0x1860044 -#define IQM_CF_TAP_IM4__W 7 -#define IQM_CF_TAP_IM4__M 0x7F -#define IQM_CF_TAP_IM4__PRE 0x2 -#define IQM_CF_TAP_IM4_B__B 0 -#define IQM_CF_TAP_IM4_B__W 7 -#define IQM_CF_TAP_IM4_B__M 0x7F -#define IQM_CF_TAP_IM4_B__PRE 0x2 - -#define IQM_CF_TAP_IM5__A 0x1860045 -#define IQM_CF_TAP_IM5__W 7 -#define IQM_CF_TAP_IM5__M 0x7F -#define IQM_CF_TAP_IM5__PRE 0x2 -#define IQM_CF_TAP_IM5_B__B 0 -#define IQM_CF_TAP_IM5_B__W 7 -#define IQM_CF_TAP_IM5_B__M 0x7F -#define IQM_CF_TAP_IM5_B__PRE 0x2 - -#define IQM_CF_TAP_IM6__A 0x1860046 -#define IQM_CF_TAP_IM6__W 7 -#define IQM_CF_TAP_IM6__M 0x7F -#define IQM_CF_TAP_IM6__PRE 0x2 -#define IQM_CF_TAP_IM6_B__B 0 -#define IQM_CF_TAP_IM6_B__W 7 -#define IQM_CF_TAP_IM6_B__M 0x7F -#define IQM_CF_TAP_IM6_B__PRE 0x2 - -#define IQM_CF_TAP_IM7__A 0x1860047 -#define IQM_CF_TAP_IM7__W 9 -#define IQM_CF_TAP_IM7__M 0x1FF -#define IQM_CF_TAP_IM7__PRE 0x2 -#define IQM_CF_TAP_IM7_B__B 0 -#define IQM_CF_TAP_IM7_B__W 9 -#define IQM_CF_TAP_IM7_B__M 0x1FF -#define IQM_CF_TAP_IM7_B__PRE 0x2 - -#define IQM_CF_TAP_IM8__A 0x1860048 -#define IQM_CF_TAP_IM8__W 9 -#define IQM_CF_TAP_IM8__M 0x1FF -#define IQM_CF_TAP_IM8__PRE 0x2 -#define IQM_CF_TAP_IM8_B__B 0 -#define IQM_CF_TAP_IM8_B__W 9 -#define IQM_CF_TAP_IM8_B__M 0x1FF -#define IQM_CF_TAP_IM8_B__PRE 0x2 - -#define IQM_CF_TAP_IM9__A 0x1860049 -#define IQM_CF_TAP_IM9__W 9 -#define IQM_CF_TAP_IM9__M 0x1FF -#define IQM_CF_TAP_IM9__PRE 0x2 -#define IQM_CF_TAP_IM9_B__B 0 -#define IQM_CF_TAP_IM9_B__W 9 -#define IQM_CF_TAP_IM9_B__M 0x1FF -#define IQM_CF_TAP_IM9_B__PRE 0x2 - -#define IQM_CF_TAP_IM10__A 0x186004A -#define IQM_CF_TAP_IM10__W 9 -#define IQM_CF_TAP_IM10__M 0x1FF -#define IQM_CF_TAP_IM10__PRE 0x2 -#define IQM_CF_TAP_IM10_B__B 0 -#define IQM_CF_TAP_IM10_B__W 9 -#define IQM_CF_TAP_IM10_B__M 0x1FF -#define IQM_CF_TAP_IM10_B__PRE 0x2 - -#define IQM_CF_TAP_IM11__A 0x186004B -#define IQM_CF_TAP_IM11__W 9 -#define IQM_CF_TAP_IM11__M 0x1FF -#define IQM_CF_TAP_IM11__PRE 0x2 -#define IQM_CF_TAP_IM11_B__B 0 -#define IQM_CF_TAP_IM11_B__W 9 -#define IQM_CF_TAP_IM11_B__M 0x1FF -#define IQM_CF_TAP_IM11_B__PRE 0x2 - -#define IQM_CF_TAP_IM12__A 0x186004C -#define IQM_CF_TAP_IM12__W 9 -#define IQM_CF_TAP_IM12__M 0x1FF -#define IQM_CF_TAP_IM12__PRE 0x2 -#define IQM_CF_TAP_IM12_B__B 0 -#define IQM_CF_TAP_IM12_B__W 9 -#define IQM_CF_TAP_IM12_B__M 0x1FF -#define IQM_CF_TAP_IM12_B__PRE 0x2 - -#define IQM_CF_TAP_IM13__A 0x186004D -#define IQM_CF_TAP_IM13__W 9 -#define IQM_CF_TAP_IM13__M 0x1FF -#define IQM_CF_TAP_IM13__PRE 0x2 -#define IQM_CF_TAP_IM13_B__B 0 -#define IQM_CF_TAP_IM13_B__W 9 -#define IQM_CF_TAP_IM13_B__M 0x1FF -#define IQM_CF_TAP_IM13_B__PRE 0x2 - -#define IQM_CF_TAP_IM14__A 0x186004E -#define IQM_CF_TAP_IM14__W 9 -#define IQM_CF_TAP_IM14__M 0x1FF -#define IQM_CF_TAP_IM14__PRE 0x2 -#define IQM_CF_TAP_IM14_B__B 0 -#define IQM_CF_TAP_IM14_B__W 9 -#define IQM_CF_TAP_IM14_B__M 0x1FF -#define IQM_CF_TAP_IM14_B__PRE 0x2 - -#define IQM_CF_TAP_IM15__A 0x186004F -#define IQM_CF_TAP_IM15__W 9 -#define IQM_CF_TAP_IM15__M 0x1FF -#define IQM_CF_TAP_IM15__PRE 0x2 -#define IQM_CF_TAP_IM15_B__B 0 -#define IQM_CF_TAP_IM15_B__W 9 -#define IQM_CF_TAP_IM15_B__M 0x1FF -#define IQM_CF_TAP_IM15_B__PRE 0x2 - -#define IQM_CF_TAP_IM16__A 0x1860050 -#define IQM_CF_TAP_IM16__W 9 -#define IQM_CF_TAP_IM16__M 0x1FF -#define IQM_CF_TAP_IM16__PRE 0x2 -#define IQM_CF_TAP_IM16_B__B 0 -#define IQM_CF_TAP_IM16_B__W 9 -#define IQM_CF_TAP_IM16_B__M 0x1FF -#define IQM_CF_TAP_IM16_B__PRE 0x2 - -#define IQM_CF_TAP_IM17__A 0x1860051 -#define IQM_CF_TAP_IM17__W 9 -#define IQM_CF_TAP_IM17__M 0x1FF -#define IQM_CF_TAP_IM17__PRE 0x2 -#define IQM_CF_TAP_IM17_B__B 0 -#define IQM_CF_TAP_IM17_B__W 9 -#define IQM_CF_TAP_IM17_B__M 0x1FF -#define IQM_CF_TAP_IM17_B__PRE 0x2 - -#define IQM_CF_TAP_IM18__A 0x1860052 -#define IQM_CF_TAP_IM18__W 9 -#define IQM_CF_TAP_IM18__M 0x1FF -#define IQM_CF_TAP_IM18__PRE 0x2 -#define IQM_CF_TAP_IM18_B__B 0 -#define IQM_CF_TAP_IM18_B__W 9 -#define IQM_CF_TAP_IM18_B__M 0x1FF -#define IQM_CF_TAP_IM18_B__PRE 0x2 - -#define IQM_CF_TAP_IM19__A 0x1860053 -#define IQM_CF_TAP_IM19__W 9 -#define IQM_CF_TAP_IM19__M 0x1FF -#define IQM_CF_TAP_IM19__PRE 0x2 -#define IQM_CF_TAP_IM19_B__B 0 -#define IQM_CF_TAP_IM19_B__W 9 -#define IQM_CF_TAP_IM19_B__M 0x1FF -#define IQM_CF_TAP_IM19_B__PRE 0x2 - -#define IQM_CF_TAP_IM20__A 0x1860054 -#define IQM_CF_TAP_IM20__W 9 -#define IQM_CF_TAP_IM20__M 0x1FF -#define IQM_CF_TAP_IM20__PRE 0x2 -#define IQM_CF_TAP_IM20_B__B 0 -#define IQM_CF_TAP_IM20_B__W 9 -#define IQM_CF_TAP_IM20_B__M 0x1FF -#define IQM_CF_TAP_IM20_B__PRE 0x2 - -#define IQM_CF_TAP_IM21__A 0x1860055 -#define IQM_CF_TAP_IM21__W 11 -#define IQM_CF_TAP_IM21__M 0x7FF -#define IQM_CF_TAP_IM21__PRE 0x2 -#define IQM_CF_TAP_IM21_B__B 0 -#define IQM_CF_TAP_IM21_B__W 11 -#define IQM_CF_TAP_IM21_B__M 0x7FF -#define IQM_CF_TAP_IM21_B__PRE 0x2 - -#define IQM_CF_TAP_IM22__A 0x1860056 -#define IQM_CF_TAP_IM22__W 11 -#define IQM_CF_TAP_IM22__M 0x7FF -#define IQM_CF_TAP_IM22__PRE 0x2 -#define IQM_CF_TAP_IM22_B__B 0 -#define IQM_CF_TAP_IM22_B__W 11 -#define IQM_CF_TAP_IM22_B__M 0x7FF -#define IQM_CF_TAP_IM22_B__PRE 0x2 - -#define IQM_CF_TAP_IM23__A 0x1860057 -#define IQM_CF_TAP_IM23__W 11 -#define IQM_CF_TAP_IM23__M 0x7FF -#define IQM_CF_TAP_IM23__PRE 0x2 -#define IQM_CF_TAP_IM23_B__B 0 -#define IQM_CF_TAP_IM23_B__W 11 -#define IQM_CF_TAP_IM23_B__M 0x7FF -#define IQM_CF_TAP_IM23_B__PRE 0x2 - -#define IQM_CF_TAP_IM24__A 0x1860058 -#define IQM_CF_TAP_IM24__W 11 -#define IQM_CF_TAP_IM24__M 0x7FF -#define IQM_CF_TAP_IM24__PRE 0x2 -#define IQM_CF_TAP_IM24_B__B 0 -#define IQM_CF_TAP_IM24_B__W 11 -#define IQM_CF_TAP_IM24_B__M 0x7FF -#define IQM_CF_TAP_IM24_B__PRE 0x2 - -#define IQM_CF_TAP_IM25__A 0x1860059 -#define IQM_CF_TAP_IM25__W 11 -#define IQM_CF_TAP_IM25__M 0x7FF -#define IQM_CF_TAP_IM25__PRE 0x2 -#define IQM_CF_TAP_IM25_B__B 0 -#define IQM_CF_TAP_IM25_B__W 11 -#define IQM_CF_TAP_IM25_B__M 0x7FF -#define IQM_CF_TAP_IM25_B__PRE 0x2 - -#define IQM_CF_TAP_IM26__A 0x186005A -#define IQM_CF_TAP_IM26__W 11 -#define IQM_CF_TAP_IM26__M 0x7FF -#define IQM_CF_TAP_IM26__PRE 0x2 -#define IQM_CF_TAP_IM26_B__B 0 -#define IQM_CF_TAP_IM26_B__W 11 -#define IQM_CF_TAP_IM26_B__M 0x7FF -#define IQM_CF_TAP_IM26_B__PRE 0x2 - -#define IQM_CF_TAP_IM27__A 0x186005B -#define IQM_CF_TAP_IM27__W 11 -#define IQM_CF_TAP_IM27__M 0x7FF -#define IQM_CF_TAP_IM27__PRE 0x2 -#define IQM_CF_TAP_IM27_B__B 0 -#define IQM_CF_TAP_IM27_B__W 11 -#define IQM_CF_TAP_IM27_B__M 0x7FF -#define IQM_CF_TAP_IM27_B__PRE 0x2 - - -#define IQM_CF_CLP_VAL__A 0x1860060 -#define IQM_CF_CLP_VAL__W 9 -#define IQM_CF_CLP_VAL__M 0x1FF -#define IQM_CF_CLP_VAL__PRE 0x3C - -#define IQM_CF_DATATH__A 0x1860061 -#define IQM_CF_DATATH__W 10 -#define IQM_CF_DATATH__M 0x3FF -#define IQM_CF_DATATH__PRE 0x180 - -#define IQM_CF_PKDTH__A 0x1860062 -#define IQM_CF_PKDTH__W 5 -#define IQM_CF_PKDTH__M 0x1F -#define IQM_CF_PKDTH__PRE 0x1 - -#define IQM_CF_WND_LEN__A 0x1860063 -#define IQM_CF_WND_LEN__W 4 -#define IQM_CF_WND_LEN__M 0xF -#define IQM_CF_WND_LEN__PRE 0x1 - -#define IQM_CF_DET_LCT__A 0x1860064 -#define IQM_CF_DET_LCT__W 1 -#define IQM_CF_DET_LCT__M 0x1 -#define IQM_CF_DET_LCT__PRE 0x1 - -#define IQM_CF_SNS_LEN__A 0x1860065 -#define IQM_CF_SNS_LEN__W 16 -#define IQM_CF_SNS_LEN__M 0xFFFF -#define IQM_CF_SNS_LEN__PRE 0x0 - -#define IQM_CF_SNS_SENSE__A 0x1860066 -#define IQM_CF_SNS_SENSE__W 16 -#define IQM_CF_SNS_SENSE__M 0xFFFF -#define IQM_CF_SNS_SENSE__PRE 0x0 - -#define IQM_CF_BYPASSDET__A 0x1860067 -#define IQM_CF_BYPASSDET__W 1 -#define IQM_CF_BYPASSDET__M 0x1 -#define IQM_CF_BYPASSDET__PRE 0x0 - -#define IQM_CF_UPD_ENA__A 0x1860068 -#define IQM_CF_UPD_ENA__W 1 -#define IQM_CF_UPD_ENA__M 0x1 -#define IQM_CF_UPD_ENA__PRE 0x0 -#define IQM_CF_UPD_ENA_DISABLE 0x0 -#define IQM_CF_UPD_ENA_ENABLE 0x1 - - - -#define IQM_AF_COMM_EXEC__A 0x1870000 -#define IQM_AF_COMM_EXEC__W 2 -#define IQM_AF_COMM_EXEC__M 0x3 -#define IQM_AF_COMM_EXEC__PRE 0x0 -#define IQM_AF_COMM_EXEC_STOP 0x0 -#define IQM_AF_COMM_EXEC_ACTIVE 0x1 -#define IQM_AF_COMM_EXEC_HOLD 0x2 - -#define IQM_AF_COMM_MB__A 0x1870002 -#define IQM_AF_COMM_MB__W 8 -#define IQM_AF_COMM_MB__M 0xFF -#define IQM_AF_COMM_MB__PRE 0x0 -#define IQM_AF_COMM_MB_CTL__B 0 -#define IQM_AF_COMM_MB_CTL__W 1 -#define IQM_AF_COMM_MB_CTL__M 0x1 -#define IQM_AF_COMM_MB_CTL__PRE 0x0 -#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_AF_COMM_MB_OBS__B 1 -#define IQM_AF_COMM_MB_OBS__W 1 -#define IQM_AF_COMM_MB_OBS__M 0x2 -#define IQM_AF_COMM_MB_OBS__PRE 0x0 -#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 -#define IQM_AF_COMM_MB_MUX_CTRL__B 2 -#define IQM_AF_COMM_MB_MUX_CTRL__W 3 -#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C -#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 -#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 -#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 -#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 -#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC -#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 -#define IQM_AF_COMM_MB_MUX_CTRL_CMP_ERR_DN 0x14 -#define IQM_AF_COMM_MB_MUX_OBS__B 5 -#define IQM_AF_COMM_MB_MUX_OBS__W 3 -#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 -#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 -#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 -#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 -#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 -#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 -#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 -#define IQM_AF_COMM_MB_MUX_OBS_CMP_ERR_DN 0xA0 - -#define IQM_AF_COMM_INT_REQ__A 0x1870003 -#define IQM_AF_COMM_INT_REQ__W 1 -#define IQM_AF_COMM_INT_REQ__M 0x1 -#define IQM_AF_COMM_INT_REQ__PRE 0x0 -#define IQM_AF_COMM_INT_STA__A 0x1870005 -#define IQM_AF_COMM_INT_STA__W 3 -#define IQM_AF_COMM_INT_STA__M 0x7 -#define IQM_AF_COMM_INT_STA__PRE 0x0 -#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 -#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 -#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 -#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 -#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 -#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 -#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 -#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 -#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__B 2 -#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__W 1 -#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__M 0x4 -#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__PRE 0x0 - -#define IQM_AF_COMM_INT_MSK__A 0x1870006 -#define IQM_AF_COMM_INT_MSK__W 3 -#define IQM_AF_COMM_INT_MSK__M 0x7 -#define IQM_AF_COMM_INT_MSK__PRE 0x0 -#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 -#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 -#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 -#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 -#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 -#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 -#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 -#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 -#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__B 2 -#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__W 1 -#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__M 0x4 -#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__PRE 0x0 - -#define IQM_AF_COMM_INT_STM__A 0x1870007 -#define IQM_AF_COMM_INT_STM__W 3 -#define IQM_AF_COMM_INT_STM__M 0x7 -#define IQM_AF_COMM_INT_STM__PRE 0x0 -#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 -#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 -#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 -#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 -#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 -#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 -#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 -#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 -#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__B 2 -#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__W 1 -#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__M 0x4 -#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__PRE 0x0 - - -#define IQM_AF_FDB_SEL__A 0x1870010 -#define IQM_AF_FDB_SEL__W 2 -#define IQM_AF_FDB_SEL__M 0x3 -#define IQM_AF_FDB_SEL__PRE 0x0 -#define IQM_AF_CLKNEG__A 0x1870012 -#define IQM_AF_CLKNEG__W 2 -#define IQM_AF_CLKNEG__M 0x3 -#define IQM_AF_CLKNEG__PRE 0x0 - -#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 -#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 -#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 -#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 -#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 -#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 - -#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 -#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 -#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 -#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 -#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 -#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 - - -#define IQM_AF_MON_IN_MUX__A 0x1870013 -#define IQM_AF_MON_IN_MUX__W 2 -#define IQM_AF_MON_IN_MUX__M 0x3 -#define IQM_AF_MON_IN_MUX__PRE 0x0 - -#define IQM_AF_MON_IN5__A 0x1870014 -#define IQM_AF_MON_IN5__W 10 -#define IQM_AF_MON_IN5__M 0x3FF -#define IQM_AF_MON_IN5__PRE 0x0 - -#define IQM_AF_MON_IN4__A 0x1870015 -#define IQM_AF_MON_IN4__W 10 -#define IQM_AF_MON_IN4__M 0x3FF -#define IQM_AF_MON_IN4__PRE 0x0 - -#define IQM_AF_MON_IN3__A 0x1870016 -#define IQM_AF_MON_IN3__W 10 -#define IQM_AF_MON_IN3__M 0x3FF -#define IQM_AF_MON_IN3__PRE 0x0 - -#define IQM_AF_MON_IN2__A 0x1870017 -#define IQM_AF_MON_IN2__W 10 -#define IQM_AF_MON_IN2__M 0x3FF -#define IQM_AF_MON_IN2__PRE 0x0 - -#define IQM_AF_MON_IN1__A 0x1870018 -#define IQM_AF_MON_IN1__W 10 -#define IQM_AF_MON_IN1__M 0x3FF -#define IQM_AF_MON_IN1__PRE 0x0 - -#define IQM_AF_MON_IN0__A 0x1870019 -#define IQM_AF_MON_IN0__W 10 -#define IQM_AF_MON_IN0__M 0x3FF -#define IQM_AF_MON_IN0__PRE 0x0 - -#define IQM_AF_MON_IN_VAL__A 0x187001A -#define IQM_AF_MON_IN_VAL__W 1 -#define IQM_AF_MON_IN_VAL__M 0x1 -#define IQM_AF_MON_IN_VAL__PRE 0x0 - -#define IQM_AF_START_LOCK__A 0x187001B -#define IQM_AF_START_LOCK__W 1 -#define IQM_AF_START_LOCK__M 0x1 -#define IQM_AF_START_LOCK__PRE 0x0 - -#define IQM_AF_PHASE0__A 0x187001C -#define IQM_AF_PHASE0__W 7 -#define IQM_AF_PHASE0__M 0x7F -#define IQM_AF_PHASE0__PRE 0x0 - -#define IQM_AF_PHASE1__A 0x187001D -#define IQM_AF_PHASE1__W 7 -#define IQM_AF_PHASE1__M 0x7F -#define IQM_AF_PHASE1__PRE 0x0 - -#define IQM_AF_PHASE2__A 0x187001E -#define IQM_AF_PHASE2__W 7 -#define IQM_AF_PHASE2__M 0x7F -#define IQM_AF_PHASE2__PRE 0x0 - -#define IQM_AF_SCU_PHASE__A 0x187001F -#define IQM_AF_SCU_PHASE__W 2 -#define IQM_AF_SCU_PHASE__M 0x3 -#define IQM_AF_SCU_PHASE__PRE 0x0 - -#define IQM_AF_SYNC_SEL__A 0x1870020 -#define IQM_AF_SYNC_SEL__W 2 -#define IQM_AF_SYNC_SEL__M 0x3 -#define IQM_AF_SYNC_SEL__PRE 0x0 -#define IQM_AF_ADC_CONF__A 0x1870021 -#define IQM_AF_ADC_CONF__W 4 -#define IQM_AF_ADC_CONF__M 0xF -#define IQM_AF_ADC_CONF__PRE 0x0 - -#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 -#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 -#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 -#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 -#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 -#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 - -#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 -#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 -#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 -#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 - -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 - -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 - - -#define IQM_AF_CLP_CLIP__A 0x1870022 -#define IQM_AF_CLP_CLIP__W 16 -#define IQM_AF_CLP_CLIP__M 0xFFFF -#define IQM_AF_CLP_CLIP__PRE 0x0 - -#define IQM_AF_CLP_LEN__A 0x1870023 -#define IQM_AF_CLP_LEN__W 16 -#define IQM_AF_CLP_LEN__M 0xFFFF -#define IQM_AF_CLP_LEN__PRE 0x0 - -#define IQM_AF_CLP_TH__A 0x1870024 -#define IQM_AF_CLP_TH__W 9 -#define IQM_AF_CLP_TH__M 0x1FF -#define IQM_AF_CLP_TH__PRE 0x0 - -#define IQM_AF_DCF_BYPASS__A 0x1870025 -#define IQM_AF_DCF_BYPASS__W 1 -#define IQM_AF_DCF_BYPASS__M 0x1 -#define IQM_AF_DCF_BYPASS__PRE 0x0 -#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 -#define IQM_AF_DCF_BYPASS_BYPASS 0x1 - - -#define IQM_AF_SNS_LEN__A 0x1870026 -#define IQM_AF_SNS_LEN__W 16 -#define IQM_AF_SNS_LEN__M 0xFFFF -#define IQM_AF_SNS_LEN__PRE 0x0 - -#define IQM_AF_SNS_SENSE__A 0x1870027 -#define IQM_AF_SNS_SENSE__W 16 -#define IQM_AF_SNS_SENSE__M 0xFFFF -#define IQM_AF_SNS_SENSE__PRE 0x0 - -#define IQM_AF_AGC_IF__A 0x1870028 -#define IQM_AF_AGC_IF__W 15 -#define IQM_AF_AGC_IF__M 0x7FFF -#define IQM_AF_AGC_IF__PRE 0x0 - -#define IQM_AF_AGC_RF__A 0x1870029 -#define IQM_AF_AGC_RF__W 15 -#define IQM_AF_AGC_RF__M 0x7FFF -#define IQM_AF_AGC_RF__PRE 0x0 - -#define IQM_AF_PDREF__A 0x187002B -#define IQM_AF_PDREF__W 5 -#define IQM_AF_PDREF__M 0x1F -#define IQM_AF_PDREF__PRE 0x0 -#define IQM_AF_STDBY__A 0x187002C -#define IQM_AF_STDBY__W 6 -#define IQM_AF_STDBY__M 0x3F -#define IQM_AF_STDBY__PRE 0x3E - -#define IQM_AF_STDBY_STDBY_BIAS__B 0 -#define IQM_AF_STDBY_STDBY_BIAS__W 1 -#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 -#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 -#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 - -#define IQM_AF_STDBY_STDBY_ADC__B 1 -#define IQM_AF_STDBY_STDBY_ADC__W 1 -#define IQM_AF_STDBY_STDBY_ADC__M 0x2 -#define IQM_AF_STDBY_STDBY_ADC__PRE 0x2 -#define IQM_AF_STDBY_STDBY_ADC_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 - -#define IQM_AF_STDBY_STDBY_AMP__B 2 -#define IQM_AF_STDBY_STDBY_AMP__W 1 -#define IQM_AF_STDBY_STDBY_AMP__M 0x4 -#define IQM_AF_STDBY_STDBY_AMP__PRE 0x4 -#define IQM_AF_STDBY_STDBY_AMP_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 - -#define IQM_AF_STDBY_STDBY_PD__B 3 -#define IQM_AF_STDBY_STDBY_PD__W 1 -#define IQM_AF_STDBY_STDBY_PD__M 0x8 -#define IQM_AF_STDBY_STDBY_PD__PRE 0x8 -#define IQM_AF_STDBY_STDBY_PD_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 - -#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 -#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 -#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 -#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x10 -#define IQM_AF_STDBY_STDBY_TAGC_IF_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 - -#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 -#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 -#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 -#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x20 -#define IQM_AF_STDBY_STDBY_TAGC_RF_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 - - -#define IQM_AF_AMUX__A 0x187002D -#define IQM_AF_AMUX__W 1 -#define IQM_AF_AMUX__M 0x1 -#define IQM_AF_AMUX__PRE 0x0 -#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 -#define IQM_AF_AMUX_SIGNAL2ADC 0x1 - - -#define IQM_AF_TST_AFEMAIN__A 0x187002E -#define IQM_AF_TST_AFEMAIN__W 8 -#define IQM_AF_TST_AFEMAIN__M 0xFF -#define IQM_AF_TST_AFEMAIN__PRE 0x0 - -#define IQM_AF_UPD_SEL__A 0x187002F -#define IQM_AF_UPD_SEL__W 1 -#define IQM_AF_UPD_SEL__M 0x1 -#define IQM_AF_UPD_SEL__PRE 0x0 - -#define IQM_AF_INC_DATATH__A 0x1870030 -#define IQM_AF_INC_DATATH__W 9 -#define IQM_AF_INC_DATATH__M 0x1FF -#define IQM_AF_INC_DATATH__PRE 0x180 - -#define IQM_AF_INC_PKDTH__A 0x1870031 -#define IQM_AF_INC_PKDTH__W 5 -#define IQM_AF_INC_PKDTH__M 0x1F -#define IQM_AF_INC_PKDTH__PRE 0x3 - -#define IQM_AF_INC_WND_LEN__A 0x1870032 -#define IQM_AF_INC_WND_LEN__W 4 -#define IQM_AF_INC_WND_LEN__M 0xF -#define IQM_AF_INC_WND_LEN__PRE 0xA - -#define IQM_AF_INC_DLY__A 0x1870033 -#define IQM_AF_INC_DLY__W 7 -#define IQM_AF_INC_DLY__M 0x7F -#define IQM_AF_INC_DLY__PRE 0x14 - -#define IQM_AF_INC_LCT__A 0x1870034 -#define IQM_AF_INC_LCT__W 1 -#define IQM_AF_INC_LCT__M 0x1 -#define IQM_AF_INC_LCT__PRE 0x1 - -#define IQM_AF_INC_CLP_VAL__A 0x1870035 -#define IQM_AF_INC_CLP_VAL__W 9 -#define IQM_AF_INC_CLP_VAL__M 0x1FF -#define IQM_AF_INC_CLP_VAL__PRE 0x3C - -#define IQM_AF_INC_BYPASS__A 0x1870036 -#define IQM_AF_INC_BYPASS__W 1 -#define IQM_AF_INC_BYPASS__M 0x1 -#define IQM_AF_INC_BYPASS__PRE 0x1 - -#define IQM_AF_INC_MODE_SEL__A 0x1870037 -#define IQM_AF_INC_MODE_SEL__W 2 -#define IQM_AF_INC_MODE_SEL__M 0x3 -#define IQM_AF_INC_MODE_SEL__PRE 0x1 - -#define IQM_AF_INC_A_DLY__A 0x1870038 -#define IQM_AF_INC_A_DLY__W 6 -#define IQM_AF_INC_A_DLY__M 0x3F -#define IQM_AF_INC_A_DLY__PRE 0xF - -#define IQM_AF_ISNS_LEN__A 0x1870039 -#define IQM_AF_ISNS_LEN__W 16 -#define IQM_AF_ISNS_LEN__M 0xFFFF -#define IQM_AF_ISNS_LEN__PRE 0x0 - -#define IQM_AF_ISNS_SENSE__A 0x187003A -#define IQM_AF_ISNS_SENSE__W 16 -#define IQM_AF_ISNS_SENSE__M 0xFFFF -#define IQM_AF_ISNS_SENSE__PRE 0x0 -#define IQM_AF_CMP_STATE__A 0x187003B -#define IQM_AF_CMP_STATE__W 7 -#define IQM_AF_CMP_STATE__M 0x7F -#define IQM_AF_CMP_STATE__PRE 0x0 - -#define IQM_AF_CMP_STATE_STATE__B 0 -#define IQM_AF_CMP_STATE_STATE__W 2 -#define IQM_AF_CMP_STATE_STATE__M 0x3 -#define IQM_AF_CMP_STATE_STATE__PRE 0x0 - -#define IQM_AF_CMP_STATE_ENABLE_CORING__B 2 -#define IQM_AF_CMP_STATE_ENABLE_CORING__W 1 -#define IQM_AF_CMP_STATE_ENABLE_CORING__M 0x4 -#define IQM_AF_CMP_STATE_ENABLE_CORING__PRE 0x0 - -#define IQM_AF_CMP_STATE_FILTERGAIN__B 3 -#define IQM_AF_CMP_STATE_FILTERGAIN__W 2 -#define IQM_AF_CMP_STATE_FILTERGAIN__M 0x18 -#define IQM_AF_CMP_STATE_FILTERGAIN__PRE 0x0 -#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER128 0x0 -#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER64 0x8 -#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER32 0x10 -#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER16 0x18 - -#define IQM_AF_CMP_STATE_KEEPCOEFF__B 5 -#define IQM_AF_CMP_STATE_KEEPCOEFF__W 1 -#define IQM_AF_CMP_STATE_KEEPCOEFF__M 0x20 -#define IQM_AF_CMP_STATE_KEEPCOEFF__PRE 0x0 - -#define IQM_AF_CMP_STATE_SEG64__B 6 -#define IQM_AF_CMP_STATE_SEG64__W 1 -#define IQM_AF_CMP_STATE_SEG64__M 0x40 -#define IQM_AF_CMP_STATE_SEG64__PRE 0x0 -#define IQM_AF_CMP_STATE_SEG64_SEG32 0x0 -#define IQM_AF_CMP_STATE_SEG64_SEG64 0x40 - - -#define IQM_AF_CMP_DC_OUT__A 0x187003C -#define IQM_AF_CMP_DC_OUT__W 12 -#define IQM_AF_CMP_DC_OUT__M 0xFFF -#define IQM_AF_CMP_DC_OUT__PRE 0x0 -#define IQM_AF_CMP_DC_IN__A 0x187003D -#define IQM_AF_CMP_DC_IN__W 13 -#define IQM_AF_CMP_DC_IN__M 0x1FFF -#define IQM_AF_CMP_DC_IN__PRE 0x0 - -#define IQM_AF_CMP_DC_IN_DC__B 0 -#define IQM_AF_CMP_DC_IN_DC__W 12 -#define IQM_AF_CMP_DC_IN_DC__M 0xFFF -#define IQM_AF_CMP_DC_IN_DC__PRE 0x0 -#define IQM_AF_CMP_DC_IN_DC_EN__B 12 -#define IQM_AF_CMP_DC_IN_DC_EN__W 1 -#define IQM_AF_CMP_DC_IN_DC_EN__M 0x1000 -#define IQM_AF_CMP_DC_IN_DC_EN__PRE 0x0 -#define IQM_AF_CMP_DC_IN_DC_EN_DISABLE 0x0 -#define IQM_AF_CMP_DC_IN_DC_EN_ENABLE 0x1000 - - -#define IQM_AF_CMP_AMP__A 0x187003E -#define IQM_AF_CMP_AMP__W 10 -#define IQM_AF_CMP_AMP__M 0x3FF -#define IQM_AF_CMP_AMP__PRE 0x0 -#define IQM_AF_CMP_DN_AVG__A 0x187003F -#define IQM_AF_CMP_DN_AVG__W 8 -#define IQM_AF_CMP_DN_AVG__M 0xFF -#define IQM_AF_CMP_DN_AVG__PRE 0x0 - -#define IQM_AF_CMP_DN_AVG_DN_AVG__B 0 -#define IQM_AF_CMP_DN_AVG_DN_AVG__W 8 -#define IQM_AF_CMP_DN_AVG_DN_AVG__M 0xFF -#define IQM_AF_CMP_DN_AVG_DN_AVG__PRE 0x0 - - -#define IQM_AF_CMP_ACTIVE__A 0x1870040 -#define IQM_AF_CMP_ACTIVE__W 1 -#define IQM_AF_CMP_ACTIVE__M 0x1 -#define IQM_AF_CMP_ACTIVE__PRE 0x0 -#define IQM_AF_CMP_MEM0__A 0x1870080 -#define IQM_AF_CMP_MEM0__W 13 -#define IQM_AF_CMP_MEM0__M 0x1FFF -#define IQM_AF_CMP_MEM0__PRE 0x0 - -#define IQM_AF_CMP_MEM0_COEF__B 0 -#define IQM_AF_CMP_MEM0_COEF__W 13 -#define IQM_AF_CMP_MEM0_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM0_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM1__A 0x1870081 -#define IQM_AF_CMP_MEM1__W 13 -#define IQM_AF_CMP_MEM1__M 0x1FFF -#define IQM_AF_CMP_MEM1__PRE 0x0 - -#define IQM_AF_CMP_MEM1_COEF__B 0 -#define IQM_AF_CMP_MEM1_COEF__W 13 -#define IQM_AF_CMP_MEM1_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM1_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM2__A 0x1870082 -#define IQM_AF_CMP_MEM2__W 13 -#define IQM_AF_CMP_MEM2__M 0x1FFF -#define IQM_AF_CMP_MEM2__PRE 0x0 - -#define IQM_AF_CMP_MEM2_COEF__B 0 -#define IQM_AF_CMP_MEM2_COEF__W 13 -#define IQM_AF_CMP_MEM2_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM2_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM3__A 0x1870083 -#define IQM_AF_CMP_MEM3__W 13 -#define IQM_AF_CMP_MEM3__M 0x1FFF -#define IQM_AF_CMP_MEM3__PRE 0x0 - -#define IQM_AF_CMP_MEM3_COEF__B 0 -#define IQM_AF_CMP_MEM3_COEF__W 13 -#define IQM_AF_CMP_MEM3_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM3_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM4__A 0x1870084 -#define IQM_AF_CMP_MEM4__W 13 -#define IQM_AF_CMP_MEM4__M 0x1FFF -#define IQM_AF_CMP_MEM4__PRE 0x0 - -#define IQM_AF_CMP_MEM4_COEF__B 0 -#define IQM_AF_CMP_MEM4_COEF__W 13 -#define IQM_AF_CMP_MEM4_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM4_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM5__A 0x1870085 -#define IQM_AF_CMP_MEM5__W 13 -#define IQM_AF_CMP_MEM5__M 0x1FFF -#define IQM_AF_CMP_MEM5__PRE 0x0 - -#define IQM_AF_CMP_MEM5_COEF__B 0 -#define IQM_AF_CMP_MEM5_COEF__W 13 -#define IQM_AF_CMP_MEM5_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM5_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM6__A 0x1870086 -#define IQM_AF_CMP_MEM6__W 13 -#define IQM_AF_CMP_MEM6__M 0x1FFF -#define IQM_AF_CMP_MEM6__PRE 0x0 - -#define IQM_AF_CMP_MEM6_COEF__B 0 -#define IQM_AF_CMP_MEM6_COEF__W 13 -#define IQM_AF_CMP_MEM6_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM6_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM7__A 0x1870087 -#define IQM_AF_CMP_MEM7__W 13 -#define IQM_AF_CMP_MEM7__M 0x1FFF -#define IQM_AF_CMP_MEM7__PRE 0x0 - -#define IQM_AF_CMP_MEM7_COEF__B 0 -#define IQM_AF_CMP_MEM7_COEF__W 13 -#define IQM_AF_CMP_MEM7_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM7_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM8__A 0x1870088 -#define IQM_AF_CMP_MEM8__W 13 -#define IQM_AF_CMP_MEM8__M 0x1FFF -#define IQM_AF_CMP_MEM8__PRE 0x0 - -#define IQM_AF_CMP_MEM8_COEF__B 0 -#define IQM_AF_CMP_MEM8_COEF__W 13 -#define IQM_AF_CMP_MEM8_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM8_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM9__A 0x1870089 -#define IQM_AF_CMP_MEM9__W 13 -#define IQM_AF_CMP_MEM9__M 0x1FFF -#define IQM_AF_CMP_MEM9__PRE 0x0 - -#define IQM_AF_CMP_MEM9_COEF__B 0 -#define IQM_AF_CMP_MEM9_COEF__W 13 -#define IQM_AF_CMP_MEM9_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM9_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM10__A 0x187008A -#define IQM_AF_CMP_MEM10__W 13 -#define IQM_AF_CMP_MEM10__M 0x1FFF -#define IQM_AF_CMP_MEM10__PRE 0x0 - -#define IQM_AF_CMP_MEM10_COEF__B 0 -#define IQM_AF_CMP_MEM10_COEF__W 13 -#define IQM_AF_CMP_MEM10_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM10_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM11__A 0x187008B -#define IQM_AF_CMP_MEM11__W 13 -#define IQM_AF_CMP_MEM11__M 0x1FFF -#define IQM_AF_CMP_MEM11__PRE 0x0 - -#define IQM_AF_CMP_MEM11_COEF__B 0 -#define IQM_AF_CMP_MEM11_COEF__W 13 -#define IQM_AF_CMP_MEM11_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM11_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM12__A 0x187008C -#define IQM_AF_CMP_MEM12__W 13 -#define IQM_AF_CMP_MEM12__M 0x1FFF -#define IQM_AF_CMP_MEM12__PRE 0x0 - -#define IQM_AF_CMP_MEM12_COEF__B 0 -#define IQM_AF_CMP_MEM12_COEF__W 13 -#define IQM_AF_CMP_MEM12_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM12_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM13__A 0x187008D -#define IQM_AF_CMP_MEM13__W 13 -#define IQM_AF_CMP_MEM13__M 0x1FFF -#define IQM_AF_CMP_MEM13__PRE 0x0 - -#define IQM_AF_CMP_MEM13_COEF__B 0 -#define IQM_AF_CMP_MEM13_COEF__W 13 -#define IQM_AF_CMP_MEM13_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM13_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM14__A 0x187008E -#define IQM_AF_CMP_MEM14__W 13 -#define IQM_AF_CMP_MEM14__M 0x1FFF -#define IQM_AF_CMP_MEM14__PRE 0x0 - -#define IQM_AF_CMP_MEM14_COEF__B 0 -#define IQM_AF_CMP_MEM14_COEF__W 13 -#define IQM_AF_CMP_MEM14_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM14_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM15__A 0x187008F -#define IQM_AF_CMP_MEM15__W 13 -#define IQM_AF_CMP_MEM15__M 0x1FFF -#define IQM_AF_CMP_MEM15__PRE 0x0 - -#define IQM_AF_CMP_MEM15_COEF__B 0 -#define IQM_AF_CMP_MEM15_COEF__W 13 -#define IQM_AF_CMP_MEM15_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM15_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM16__A 0x1870090 -#define IQM_AF_CMP_MEM16__W 13 -#define IQM_AF_CMP_MEM16__M 0x1FFF -#define IQM_AF_CMP_MEM16__PRE 0x0 - -#define IQM_AF_CMP_MEM16_COEF__B 0 -#define IQM_AF_CMP_MEM16_COEF__W 13 -#define IQM_AF_CMP_MEM16_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM16_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM17__A 0x1870091 -#define IQM_AF_CMP_MEM17__W 13 -#define IQM_AF_CMP_MEM17__M 0x1FFF -#define IQM_AF_CMP_MEM17__PRE 0x0 - -#define IQM_AF_CMP_MEM17_COEF__B 0 -#define IQM_AF_CMP_MEM17_COEF__W 13 -#define IQM_AF_CMP_MEM17_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM17_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM18__A 0x1870092 -#define IQM_AF_CMP_MEM18__W 13 -#define IQM_AF_CMP_MEM18__M 0x1FFF -#define IQM_AF_CMP_MEM18__PRE 0x0 - -#define IQM_AF_CMP_MEM18_COEF__B 0 -#define IQM_AF_CMP_MEM18_COEF__W 13 -#define IQM_AF_CMP_MEM18_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM18_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM19__A 0x1870093 -#define IQM_AF_CMP_MEM19__W 13 -#define IQM_AF_CMP_MEM19__M 0x1FFF -#define IQM_AF_CMP_MEM19__PRE 0x0 - -#define IQM_AF_CMP_MEM19_COEF__B 0 -#define IQM_AF_CMP_MEM19_COEF__W 13 -#define IQM_AF_CMP_MEM19_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM19_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM20__A 0x1870094 -#define IQM_AF_CMP_MEM20__W 13 -#define IQM_AF_CMP_MEM20__M 0x1FFF -#define IQM_AF_CMP_MEM20__PRE 0x0 - -#define IQM_AF_CMP_MEM20_COEF__B 0 -#define IQM_AF_CMP_MEM20_COEF__W 13 -#define IQM_AF_CMP_MEM20_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM20_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM21__A 0x1870095 -#define IQM_AF_CMP_MEM21__W 13 -#define IQM_AF_CMP_MEM21__M 0x1FFF -#define IQM_AF_CMP_MEM21__PRE 0x0 - -#define IQM_AF_CMP_MEM21_COEF__B 0 -#define IQM_AF_CMP_MEM21_COEF__W 13 -#define IQM_AF_CMP_MEM21_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM21_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM22__A 0x1870096 -#define IQM_AF_CMP_MEM22__W 13 -#define IQM_AF_CMP_MEM22__M 0x1FFF -#define IQM_AF_CMP_MEM22__PRE 0x0 - -#define IQM_AF_CMP_MEM22_COEF__B 0 -#define IQM_AF_CMP_MEM22_COEF__W 13 -#define IQM_AF_CMP_MEM22_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM22_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM23__A 0x1870097 -#define IQM_AF_CMP_MEM23__W 13 -#define IQM_AF_CMP_MEM23__M 0x1FFF -#define IQM_AF_CMP_MEM23__PRE 0x0 - -#define IQM_AF_CMP_MEM23_COEF__B 0 -#define IQM_AF_CMP_MEM23_COEF__W 13 -#define IQM_AF_CMP_MEM23_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM23_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM24__A 0x1870098 -#define IQM_AF_CMP_MEM24__W 13 -#define IQM_AF_CMP_MEM24__M 0x1FFF -#define IQM_AF_CMP_MEM24__PRE 0x0 - -#define IQM_AF_CMP_MEM24_COEF__B 0 -#define IQM_AF_CMP_MEM24_COEF__W 13 -#define IQM_AF_CMP_MEM24_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM24_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM25__A 0x1870099 -#define IQM_AF_CMP_MEM25__W 13 -#define IQM_AF_CMP_MEM25__M 0x1FFF -#define IQM_AF_CMP_MEM25__PRE 0x0 - -#define IQM_AF_CMP_MEM25_COEF__B 0 -#define IQM_AF_CMP_MEM25_COEF__W 13 -#define IQM_AF_CMP_MEM25_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM25_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM26__A 0x187009A -#define IQM_AF_CMP_MEM26__W 13 -#define IQM_AF_CMP_MEM26__M 0x1FFF -#define IQM_AF_CMP_MEM26__PRE 0x0 - -#define IQM_AF_CMP_MEM26_COEF__B 0 -#define IQM_AF_CMP_MEM26_COEF__W 13 -#define IQM_AF_CMP_MEM26_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM26_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM27__A 0x187009B -#define IQM_AF_CMP_MEM27__W 13 -#define IQM_AF_CMP_MEM27__M 0x1FFF -#define IQM_AF_CMP_MEM27__PRE 0x0 - -#define IQM_AF_CMP_MEM27_COEF__B 0 -#define IQM_AF_CMP_MEM27_COEF__W 13 -#define IQM_AF_CMP_MEM27_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM27_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM28__A 0x187009C -#define IQM_AF_CMP_MEM28__W 13 -#define IQM_AF_CMP_MEM28__M 0x1FFF -#define IQM_AF_CMP_MEM28__PRE 0x0 - -#define IQM_AF_CMP_MEM28_COEF__B 0 -#define IQM_AF_CMP_MEM28_COEF__W 13 -#define IQM_AF_CMP_MEM28_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM28_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM29__A 0x187009D -#define IQM_AF_CMP_MEM29__W 13 -#define IQM_AF_CMP_MEM29__M 0x1FFF -#define IQM_AF_CMP_MEM29__PRE 0x0 - -#define IQM_AF_CMP_MEM29_COEF__B 0 -#define IQM_AF_CMP_MEM29_COEF__W 13 -#define IQM_AF_CMP_MEM29_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM29_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM30__A 0x187009E -#define IQM_AF_CMP_MEM30__W 13 -#define IQM_AF_CMP_MEM30__M 0x1FFF -#define IQM_AF_CMP_MEM30__PRE 0x0 - -#define IQM_AF_CMP_MEM30_COEF__B 0 -#define IQM_AF_CMP_MEM30_COEF__W 13 -#define IQM_AF_CMP_MEM30_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM30_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM31__A 0x187009F -#define IQM_AF_CMP_MEM31__W 13 -#define IQM_AF_CMP_MEM31__M 0x1FFF -#define IQM_AF_CMP_MEM31__PRE 0x0 - -#define IQM_AF_CMP_MEM31_COEF__B 0 -#define IQM_AF_CMP_MEM31_COEF__W 13 -#define IQM_AF_CMP_MEM31_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM31_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM32__A 0x18700A0 -#define IQM_AF_CMP_MEM32__W 13 -#define IQM_AF_CMP_MEM32__M 0x1FFF -#define IQM_AF_CMP_MEM32__PRE 0x0 - -#define IQM_AF_CMP_MEM32_COEF__B 0 -#define IQM_AF_CMP_MEM32_COEF__W 13 -#define IQM_AF_CMP_MEM32_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM32_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM33__A 0x18700A1 -#define IQM_AF_CMP_MEM33__W 13 -#define IQM_AF_CMP_MEM33__M 0x1FFF -#define IQM_AF_CMP_MEM33__PRE 0x0 - -#define IQM_AF_CMP_MEM33_COEF__B 0 -#define IQM_AF_CMP_MEM33_COEF__W 13 -#define IQM_AF_CMP_MEM33_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM33_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM34__A 0x18700A2 -#define IQM_AF_CMP_MEM34__W 13 -#define IQM_AF_CMP_MEM34__M 0x1FFF -#define IQM_AF_CMP_MEM34__PRE 0x0 - -#define IQM_AF_CMP_MEM34_COEF__B 0 -#define IQM_AF_CMP_MEM34_COEF__W 13 -#define IQM_AF_CMP_MEM34_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM34_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM35__A 0x18700A3 -#define IQM_AF_CMP_MEM35__W 13 -#define IQM_AF_CMP_MEM35__M 0x1FFF -#define IQM_AF_CMP_MEM35__PRE 0x0 - -#define IQM_AF_CMP_MEM35_COEF__B 0 -#define IQM_AF_CMP_MEM35_COEF__W 13 -#define IQM_AF_CMP_MEM35_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM35_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM36__A 0x18700A4 -#define IQM_AF_CMP_MEM36__W 13 -#define IQM_AF_CMP_MEM36__M 0x1FFF -#define IQM_AF_CMP_MEM36__PRE 0x0 - -#define IQM_AF_CMP_MEM36_COEF__B 0 -#define IQM_AF_CMP_MEM36_COEF__W 13 -#define IQM_AF_CMP_MEM36_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM36_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM37__A 0x18700A5 -#define IQM_AF_CMP_MEM37__W 13 -#define IQM_AF_CMP_MEM37__M 0x1FFF -#define IQM_AF_CMP_MEM37__PRE 0x0 - -#define IQM_AF_CMP_MEM37_COEF__B 0 -#define IQM_AF_CMP_MEM37_COEF__W 13 -#define IQM_AF_CMP_MEM37_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM37_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM38__A 0x18700A6 -#define IQM_AF_CMP_MEM38__W 13 -#define IQM_AF_CMP_MEM38__M 0x1FFF -#define IQM_AF_CMP_MEM38__PRE 0x0 - -#define IQM_AF_CMP_MEM38_COEF__B 0 -#define IQM_AF_CMP_MEM38_COEF__W 13 -#define IQM_AF_CMP_MEM38_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM38_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM39__A 0x18700A7 -#define IQM_AF_CMP_MEM39__W 13 -#define IQM_AF_CMP_MEM39__M 0x1FFF -#define IQM_AF_CMP_MEM39__PRE 0x0 - -#define IQM_AF_CMP_MEM39_COEF__B 0 -#define IQM_AF_CMP_MEM39_COEF__W 13 -#define IQM_AF_CMP_MEM39_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM39_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM40__A 0x18700A8 -#define IQM_AF_CMP_MEM40__W 13 -#define IQM_AF_CMP_MEM40__M 0x1FFF -#define IQM_AF_CMP_MEM40__PRE 0x0 - -#define IQM_AF_CMP_MEM40_COEF__B 0 -#define IQM_AF_CMP_MEM40_COEF__W 13 -#define IQM_AF_CMP_MEM40_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM40_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM41__A 0x18700A9 -#define IQM_AF_CMP_MEM41__W 13 -#define IQM_AF_CMP_MEM41__M 0x1FFF -#define IQM_AF_CMP_MEM41__PRE 0x0 - -#define IQM_AF_CMP_MEM41_COEF__B 0 -#define IQM_AF_CMP_MEM41_COEF__W 13 -#define IQM_AF_CMP_MEM41_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM41_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM42__A 0x18700AA -#define IQM_AF_CMP_MEM42__W 13 -#define IQM_AF_CMP_MEM42__M 0x1FFF -#define IQM_AF_CMP_MEM42__PRE 0x0 - -#define IQM_AF_CMP_MEM42_COEF__B 0 -#define IQM_AF_CMP_MEM42_COEF__W 13 -#define IQM_AF_CMP_MEM42_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM42_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM43__A 0x18700AB -#define IQM_AF_CMP_MEM43__W 13 -#define IQM_AF_CMP_MEM43__M 0x1FFF -#define IQM_AF_CMP_MEM43__PRE 0x0 - -#define IQM_AF_CMP_MEM43_COEF__B 0 -#define IQM_AF_CMP_MEM43_COEF__W 13 -#define IQM_AF_CMP_MEM43_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM43_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM44__A 0x18700AC -#define IQM_AF_CMP_MEM44__W 13 -#define IQM_AF_CMP_MEM44__M 0x1FFF -#define IQM_AF_CMP_MEM44__PRE 0x0 - -#define IQM_AF_CMP_MEM44_COEF__B 0 -#define IQM_AF_CMP_MEM44_COEF__W 13 -#define IQM_AF_CMP_MEM44_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM44_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM45__A 0x18700AD -#define IQM_AF_CMP_MEM45__W 13 -#define IQM_AF_CMP_MEM45__M 0x1FFF -#define IQM_AF_CMP_MEM45__PRE 0x0 - -#define IQM_AF_CMP_MEM45_COEF__B 0 -#define IQM_AF_CMP_MEM45_COEF__W 13 -#define IQM_AF_CMP_MEM45_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM45_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM46__A 0x18700AE -#define IQM_AF_CMP_MEM46__W 13 -#define IQM_AF_CMP_MEM46__M 0x1FFF -#define IQM_AF_CMP_MEM46__PRE 0x0 - -#define IQM_AF_CMP_MEM46_COEF__B 0 -#define IQM_AF_CMP_MEM46_COEF__W 13 -#define IQM_AF_CMP_MEM46_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM46_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM47__A 0x18700AF -#define IQM_AF_CMP_MEM47__W 13 -#define IQM_AF_CMP_MEM47__M 0x1FFF -#define IQM_AF_CMP_MEM47__PRE 0x0 - -#define IQM_AF_CMP_MEM47_COEF__B 0 -#define IQM_AF_CMP_MEM47_COEF__W 13 -#define IQM_AF_CMP_MEM47_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM47_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM48__A 0x18700B0 -#define IQM_AF_CMP_MEM48__W 13 -#define IQM_AF_CMP_MEM48__M 0x1FFF -#define IQM_AF_CMP_MEM48__PRE 0x0 - -#define IQM_AF_CMP_MEM48_COEF__B 0 -#define IQM_AF_CMP_MEM48_COEF__W 13 -#define IQM_AF_CMP_MEM48_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM48_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM49__A 0x18700B1 -#define IQM_AF_CMP_MEM49__W 13 -#define IQM_AF_CMP_MEM49__M 0x1FFF -#define IQM_AF_CMP_MEM49__PRE 0x0 - -#define IQM_AF_CMP_MEM49_COEF__B 0 -#define IQM_AF_CMP_MEM49_COEF__W 13 -#define IQM_AF_CMP_MEM49_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM49_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM50__A 0x18700B2 -#define IQM_AF_CMP_MEM50__W 13 -#define IQM_AF_CMP_MEM50__M 0x1FFF -#define IQM_AF_CMP_MEM50__PRE 0x0 - -#define IQM_AF_CMP_MEM50_COEF__B 0 -#define IQM_AF_CMP_MEM50_COEF__W 13 -#define IQM_AF_CMP_MEM50_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM50_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM51__A 0x18700B3 -#define IQM_AF_CMP_MEM51__W 13 -#define IQM_AF_CMP_MEM51__M 0x1FFF -#define IQM_AF_CMP_MEM51__PRE 0x0 - -#define IQM_AF_CMP_MEM51_COEF__B 0 -#define IQM_AF_CMP_MEM51_COEF__W 13 -#define IQM_AF_CMP_MEM51_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM51_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM52__A 0x18700B4 -#define IQM_AF_CMP_MEM52__W 13 -#define IQM_AF_CMP_MEM52__M 0x1FFF -#define IQM_AF_CMP_MEM52__PRE 0x0 - -#define IQM_AF_CMP_MEM52_COEF__B 0 -#define IQM_AF_CMP_MEM52_COEF__W 13 -#define IQM_AF_CMP_MEM52_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM52_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM53__A 0x18700B5 -#define IQM_AF_CMP_MEM53__W 13 -#define IQM_AF_CMP_MEM53__M 0x1FFF -#define IQM_AF_CMP_MEM53__PRE 0x0 - -#define IQM_AF_CMP_MEM53_COEF__B 0 -#define IQM_AF_CMP_MEM53_COEF__W 13 -#define IQM_AF_CMP_MEM53_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM53_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM54__A 0x18700B6 -#define IQM_AF_CMP_MEM54__W 13 -#define IQM_AF_CMP_MEM54__M 0x1FFF -#define IQM_AF_CMP_MEM54__PRE 0x0 - -#define IQM_AF_CMP_MEM54_COEF__B 0 -#define IQM_AF_CMP_MEM54_COEF__W 13 -#define IQM_AF_CMP_MEM54_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM54_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM55__A 0x18700B7 -#define IQM_AF_CMP_MEM55__W 13 -#define IQM_AF_CMP_MEM55__M 0x1FFF -#define IQM_AF_CMP_MEM55__PRE 0x0 - -#define IQM_AF_CMP_MEM55_COEF__B 0 -#define IQM_AF_CMP_MEM55_COEF__W 13 -#define IQM_AF_CMP_MEM55_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM55_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM56__A 0x18700B8 -#define IQM_AF_CMP_MEM56__W 13 -#define IQM_AF_CMP_MEM56__M 0x1FFF -#define IQM_AF_CMP_MEM56__PRE 0x0 - -#define IQM_AF_CMP_MEM56_COEF__B 0 -#define IQM_AF_CMP_MEM56_COEF__W 13 -#define IQM_AF_CMP_MEM56_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM56_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM57__A 0x18700B9 -#define IQM_AF_CMP_MEM57__W 13 -#define IQM_AF_CMP_MEM57__M 0x1FFF -#define IQM_AF_CMP_MEM57__PRE 0x0 - -#define IQM_AF_CMP_MEM57_COEF__B 0 -#define IQM_AF_CMP_MEM57_COEF__W 13 -#define IQM_AF_CMP_MEM57_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM57_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM58__A 0x18700BA -#define IQM_AF_CMP_MEM58__W 13 -#define IQM_AF_CMP_MEM58__M 0x1FFF -#define IQM_AF_CMP_MEM58__PRE 0x0 - -#define IQM_AF_CMP_MEM58_COEF__B 0 -#define IQM_AF_CMP_MEM58_COEF__W 13 -#define IQM_AF_CMP_MEM58_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM58_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM59__A 0x18700BB -#define IQM_AF_CMP_MEM59__W 13 -#define IQM_AF_CMP_MEM59__M 0x1FFF -#define IQM_AF_CMP_MEM59__PRE 0x0 - -#define IQM_AF_CMP_MEM59_COEF__B 0 -#define IQM_AF_CMP_MEM59_COEF__W 13 -#define IQM_AF_CMP_MEM59_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM59_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM60__A 0x18700BC -#define IQM_AF_CMP_MEM60__W 13 -#define IQM_AF_CMP_MEM60__M 0x1FFF -#define IQM_AF_CMP_MEM60__PRE 0x0 - -#define IQM_AF_CMP_MEM60_COEF__B 0 -#define IQM_AF_CMP_MEM60_COEF__W 13 -#define IQM_AF_CMP_MEM60_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM60_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM61__A 0x18700BD -#define IQM_AF_CMP_MEM61__W 13 -#define IQM_AF_CMP_MEM61__M 0x1FFF -#define IQM_AF_CMP_MEM61__PRE 0x0 - -#define IQM_AF_CMP_MEM61_COEF__B 0 -#define IQM_AF_CMP_MEM61_COEF__W 13 -#define IQM_AF_CMP_MEM61_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM61_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM62__A 0x18700BE -#define IQM_AF_CMP_MEM62__W 13 -#define IQM_AF_CMP_MEM62__M 0x1FFF -#define IQM_AF_CMP_MEM62__PRE 0x0 - -#define IQM_AF_CMP_MEM62_COEF__B 0 -#define IQM_AF_CMP_MEM62_COEF__W 13 -#define IQM_AF_CMP_MEM62_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM62_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM63__A 0x18700BF -#define IQM_AF_CMP_MEM63__W 13 -#define IQM_AF_CMP_MEM63__M 0x1FFF -#define IQM_AF_CMP_MEM63__PRE 0x0 - -#define IQM_AF_CMP_MEM63_COEF__B 0 -#define IQM_AF_CMP_MEM63_COEF__W 13 -#define IQM_AF_CMP_MEM63_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM63_COEF__PRE 0x0 - - - -#define IQM_RT_RAM__A 0x1880000 - -#define IQM_RT_RAM_DLY__B 0 -#define IQM_RT_RAM_DLY__W 13 -#define IQM_RT_RAM_DLY__M 0x1FFF -#define IQM_RT_RAM_DLY__PRE 0x0 - - - - - -#define OFDM_CE_COMM_EXEC__A 0x2C00000 -#define OFDM_CE_COMM_EXEC__W 3 -#define OFDM_CE_COMM_EXEC__M 0x7 -#define OFDM_CE_COMM_EXEC__PRE 0x0 -#define OFDM_CE_COMM_EXEC_STOP 0x0 -#define OFDM_CE_COMM_EXEC_ACTIVE 0x1 -#define OFDM_CE_COMM_EXEC_HOLD 0x2 -#define OFDM_CE_COMM_EXEC_STEP 0x3 -#define OFDM_CE_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_CE_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_CE_COMM_STATE__A 0x2C00001 -#define OFDM_CE_COMM_STATE__W 16 -#define OFDM_CE_COMM_STATE__M 0xFFFF -#define OFDM_CE_COMM_STATE__PRE 0x0 -#define OFDM_CE_COMM_MB__A 0x2C00002 -#define OFDM_CE_COMM_MB__W 16 -#define OFDM_CE_COMM_MB__M 0xFFFF -#define OFDM_CE_COMM_MB__PRE 0x0 -#define OFDM_CE_COMM_INT_REQ__A 0x2C00004 -#define OFDM_CE_COMM_INT_REQ__W 16 -#define OFDM_CE_COMM_INT_REQ__M 0xFFFF -#define OFDM_CE_COMM_INT_REQ__PRE 0x0 -#define OFDM_CE_COMM_INT_REQ_TOP_REQ__B 2 -#define OFDM_CE_COMM_INT_REQ_TOP_REQ__W 1 -#define OFDM_CE_COMM_INT_REQ_TOP_REQ__M 0x4 -#define OFDM_CE_COMM_INT_REQ_TOP_REQ__PRE 0x0 - -#define OFDM_CE_COMM_INT_STA__A 0x2C00005 -#define OFDM_CE_COMM_INT_STA__W 16 -#define OFDM_CE_COMM_INT_STA__M 0xFFFF -#define OFDM_CE_COMM_INT_STA__PRE 0x0 -#define OFDM_CE_COMM_INT_MSK__A 0x2C00006 -#define OFDM_CE_COMM_INT_MSK__W 16 -#define OFDM_CE_COMM_INT_MSK__M 0xFFFF -#define OFDM_CE_COMM_INT_MSK__PRE 0x0 -#define OFDM_CE_COMM_INT_STM__A 0x2C00007 -#define OFDM_CE_COMM_INT_STM__W 16 -#define OFDM_CE_COMM_INT_STM__M 0xFFFF -#define OFDM_CE_COMM_INT_STM__PRE 0x0 -#define OFDM_CE_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_CE_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_CE_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_CE_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_CE_TOP_COMM_EXEC__A 0x2C10000 -#define OFDM_CE_TOP_COMM_EXEC__W 3 -#define OFDM_CE_TOP_COMM_EXEC__M 0x7 -#define OFDM_CE_TOP_COMM_EXEC__PRE 0x0 -#define OFDM_CE_TOP_COMM_EXEC_STOP 0x0 -#define OFDM_CE_TOP_COMM_EXEC_ACTIVE 0x1 -#define OFDM_CE_TOP_COMM_EXEC_HOLD 0x2 -#define OFDM_CE_TOP_COMM_EXEC_STEP 0x3 - -#define OFDM_CE_TOP_COMM_MB__A 0x2C10002 -#define OFDM_CE_TOP_COMM_MB__W 4 -#define OFDM_CE_TOP_COMM_MB__M 0xF -#define OFDM_CE_TOP_COMM_MB__PRE 0x0 -#define OFDM_CE_TOP_COMM_MB_CTL__B 0 -#define OFDM_CE_TOP_COMM_MB_CTL__W 1 -#define OFDM_CE_TOP_COMM_MB_CTL__M 0x1 -#define OFDM_CE_TOP_COMM_MB_CTL__PRE 0x0 -#define OFDM_CE_TOP_COMM_MB_CTL_OFF 0x0 -#define OFDM_CE_TOP_COMM_MB_CTL_ON 0x1 -#define OFDM_CE_TOP_COMM_MB_OBS__B 1 -#define OFDM_CE_TOP_COMM_MB_OBS__W 1 -#define OFDM_CE_TOP_COMM_MB_OBS__M 0x2 -#define OFDM_CE_TOP_COMM_MB_OBS__PRE 0x0 -#define OFDM_CE_TOP_COMM_MB_OBS_OFF 0x0 -#define OFDM_CE_TOP_COMM_MB_OBS_ON 0x2 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL__B 2 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL__W 2 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL__M 0xC -#define OFDM_CE_TOP_COMM_MB_OBS_SEL__PRE 0x0 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FI 0x0 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TP 0x4 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TI 0x8 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FR 0xC - -#define OFDM_CE_TOP_COMM_INT_REQ__A 0x2C10004 -#define OFDM_CE_TOP_COMM_INT_REQ__W 1 -#define OFDM_CE_TOP_COMM_INT_REQ__M 0x1 -#define OFDM_CE_TOP_COMM_INT_REQ__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STA__A 0x2C10005 -#define OFDM_CE_TOP_COMM_INT_STA__W 3 -#define OFDM_CE_TOP_COMM_INT_STA__M 0x7 -#define OFDM_CE_TOP_COMM_INT_STA__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__B 0 -#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__W 1 -#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__M 0x1 -#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__B 1 -#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__W 1 -#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__M 0x2 -#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__B 2 -#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__W 1 -#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__M 0x4 -#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__PRE 0x0 - -#define OFDM_CE_TOP_COMM_INT_MSK__A 0x2C10006 -#define OFDM_CE_TOP_COMM_INT_MSK__W 3 -#define OFDM_CE_TOP_COMM_INT_MSK__M 0x7 -#define OFDM_CE_TOP_COMM_INT_MSK__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__B 0 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__W 1 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__M 0x1 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__B 1 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__W 1 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__M 0x2 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__B 2 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__W 1 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__M 0x4 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__PRE 0x0 - -#define OFDM_CE_TOP_COMM_INT_STM__A 0x2C10007 -#define OFDM_CE_TOP_COMM_INT_STM__W 3 -#define OFDM_CE_TOP_COMM_INT_STM__M 0x7 -#define OFDM_CE_TOP_COMM_INT_STM__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__B 0 -#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__W 1 -#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__M 0x1 -#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__B 1 -#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__W 1 -#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__M 0x2 -#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__B 2 -#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__W 1 -#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__M 0x4 -#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__PRE 0x0 - - -#define OFDM_CE_TOP_MODE_2K__A 0x2C10010 -#define OFDM_CE_TOP_MODE_2K__W 1 -#define OFDM_CE_TOP_MODE_2K__M 0x1 -#define OFDM_CE_TOP_MODE_2K__PRE 0x0 - -#define OFDM_CE_TOP_TAPSET__A 0x2C10011 -#define OFDM_CE_TOP_TAPSET__W 4 -#define OFDM_CE_TOP_TAPSET__M 0xF -#define OFDM_CE_TOP_TAPSET__PRE 0x1 -#define OFDM_CE_TOP_AVG_POW__A 0x2C10012 -#define OFDM_CE_TOP_AVG_POW__W 8 -#define OFDM_CE_TOP_AVG_POW__M 0xFF -#define OFDM_CE_TOP_AVG_POW__PRE 0x65 -#define OFDM_CE_TOP_MAX_POW__A 0x2C10013 -#define OFDM_CE_TOP_MAX_POW__W 8 -#define OFDM_CE_TOP_MAX_POW__M 0xFF -#define OFDM_CE_TOP_MAX_POW__PRE 0x80 -#define OFDM_CE_TOP_ATT__A 0x2C10014 -#define OFDM_CE_TOP_ATT__W 8 -#define OFDM_CE_TOP_ATT__M 0xFF -#define OFDM_CE_TOP_ATT__PRE 0x70 -#define OFDM_CE_TOP_NRED__A 0x2C10015 -#define OFDM_CE_TOP_NRED__W 6 -#define OFDM_CE_TOP_NRED__M 0x3F -#define OFDM_CE_TOP_NRED__PRE 0x9 - -#define OFDM_CE_TOP_PU_SIGN__A 0x2C10020 -#define OFDM_CE_TOP_PU_SIGN__W 1 -#define OFDM_CE_TOP_PU_SIGN__M 0x1 -#define OFDM_CE_TOP_PU_SIGN__PRE 0x0 - -#define OFDM_CE_TOP_PU_MIX__A 0x2C10021 -#define OFDM_CE_TOP_PU_MIX__W 1 -#define OFDM_CE_TOP_PU_MIX__M 0x1 -#define OFDM_CE_TOP_PU_MIX__PRE 0x0 -#define OFDM_CE_TOP_PB_PILOT_REQ__A 0x2C10030 -#define OFDM_CE_TOP_PB_PILOT_REQ__W 15 -#define OFDM_CE_TOP_PB_PILOT_REQ__M 0x7FFF -#define OFDM_CE_TOP_PB_PILOT_REQ__PRE 0x0 -#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__B 12 -#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__W 3 -#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 -#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__PRE 0x0 -#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__B 0 -#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__W 12 -#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__M 0xFFF -#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__PRE 0x0 - - -#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__A 0x2C10031 -#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__W 1 -#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__M 0x1 -#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__PRE 0x0 - -#define OFDM_CE_TOP_PB_FREEZE__A 0x2C10032 -#define OFDM_CE_TOP_PB_FREEZE__W 1 -#define OFDM_CE_TOP_PB_FREEZE__M 0x1 -#define OFDM_CE_TOP_PB_FREEZE__PRE 0x0 - -#define OFDM_CE_TOP_PB_PILOT_EXP__A 0x2C10038 -#define OFDM_CE_TOP_PB_PILOT_EXP__W 4 -#define OFDM_CE_TOP_PB_PILOT_EXP__M 0xF -#define OFDM_CE_TOP_PB_PILOT_EXP__PRE 0x0 - -#define OFDM_CE_TOP_PB_PILOT_REAL__A 0x2C10039 -#define OFDM_CE_TOP_PB_PILOT_REAL__W 10 -#define OFDM_CE_TOP_PB_PILOT_REAL__M 0x3FF -#define OFDM_CE_TOP_PB_PILOT_REAL__PRE 0x0 - -#define OFDM_CE_TOP_PB_PILOT_IMAG__A 0x2C1003A -#define OFDM_CE_TOP_PB_PILOT_IMAG__W 10 -#define OFDM_CE_TOP_PB_PILOT_IMAG__M 0x3FF -#define OFDM_CE_TOP_PB_PILOT_IMAG__PRE 0x0 - -#define OFDM_CE_TOP_PB_SMBNR__A 0x2C1003B -#define OFDM_CE_TOP_PB_SMBNR__W 5 -#define OFDM_CE_TOP_PB_SMBNR__M 0x1F -#define OFDM_CE_TOP_PB_SMBNR__PRE 0x0 - -#define OFDM_CE_TOP_NE_PILOT_REQ__A 0x2C10040 -#define OFDM_CE_TOP_NE_PILOT_REQ__W 12 -#define OFDM_CE_TOP_NE_PILOT_REQ__M 0xFFF -#define OFDM_CE_TOP_NE_PILOT_REQ__PRE 0x0 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__A 0x2C10041 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__W 2 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__M 0x3 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__PRE 0x0 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__PRE 0x0 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__B 0 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__W 1 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__PRE 0x0 - - -#define OFDM_CE_TOP_NE_PILOT_DATA__A 0x2C10042 -#define OFDM_CE_TOP_NE_PILOT_DATA__W 10 -#define OFDM_CE_TOP_NE_PILOT_DATA__M 0x3FF -#define OFDM_CE_TOP_NE_PILOT_DATA__PRE 0x0 -#define OFDM_CE_TOP_NE_ERR_SELECT__A 0x2C10043 -#define OFDM_CE_TOP_NE_ERR_SELECT__W 5 -#define OFDM_CE_TOP_NE_ERR_SELECT__M 0x1F -#define OFDM_CE_TOP_NE_ERR_SELECT__PRE 0x7 - -#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__B 4 -#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__W 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__M 0x10 -#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__PRE 0x0 - -#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__B 3 -#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__W 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__M 0x8 -#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__PRE 0x0 - -#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__B 2 -#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__W 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__M 0x4 -#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__PRE 0x4 - -#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__B 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__W 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__M 0x2 -#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__PRE 0x2 - -#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__B 0 -#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__W 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__M 0x1 -#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__PRE 0x1 - - -#define OFDM_CE_TOP_NE_TD_CAL__A 0x2C10044 -#define OFDM_CE_TOP_NE_TD_CAL__W 9 -#define OFDM_CE_TOP_NE_TD_CAL__M 0x1FF -#define OFDM_CE_TOP_NE_TD_CAL__PRE 0x1E8 - -#define OFDM_CE_TOP_NE_FD_CAL__A 0x2C10045 -#define OFDM_CE_TOP_NE_FD_CAL__W 9 -#define OFDM_CE_TOP_NE_FD_CAL__M 0x1FF -#define OFDM_CE_TOP_NE_FD_CAL__PRE 0x1D9 - -#define OFDM_CE_TOP_NE_MIXAVG__A 0x2C10046 -#define OFDM_CE_TOP_NE_MIXAVG__W 3 -#define OFDM_CE_TOP_NE_MIXAVG__M 0x7 -#define OFDM_CE_TOP_NE_MIXAVG__PRE 0x6 - -#define OFDM_CE_TOP_NE_NUPD_OFS__A 0x2C10047 -#define OFDM_CE_TOP_NE_NUPD_OFS__W 4 -#define OFDM_CE_TOP_NE_NUPD_OFS__M 0xF -#define OFDM_CE_TOP_NE_NUPD_OFS__PRE 0x4 -#define OFDM_CE_TOP_NE_TD_POW__A 0x2C10048 -#define OFDM_CE_TOP_NE_TD_POW__W 15 -#define OFDM_CE_TOP_NE_TD_POW__M 0x7FFF -#define OFDM_CE_TOP_NE_TD_POW__PRE 0x0 - -#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__B 10 -#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__W 5 -#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__B 0 -#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__W 10 -#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__PRE 0x0 - -#define OFDM_CE_TOP_NE_FD_POW__A 0x2C10049 -#define OFDM_CE_TOP_NE_FD_POW__W 15 -#define OFDM_CE_TOP_NE_FD_POW__M 0x7FFF -#define OFDM_CE_TOP_NE_FD_POW__PRE 0x0 - -#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__B 10 -#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__W 5 -#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__B 0 -#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__W 10 -#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__PRE 0x0 - - -#define OFDM_CE_TOP_NE_NEXP_AVG__A 0x2C1004A -#define OFDM_CE_TOP_NE_NEXP_AVG__W 8 -#define OFDM_CE_TOP_NE_NEXP_AVG__M 0xFF -#define OFDM_CE_TOP_NE_NEXP_AVG__PRE 0x0 - -#define OFDM_CE_TOP_NE_OFFSET__A 0x2C1004B -#define OFDM_CE_TOP_NE_OFFSET__W 9 -#define OFDM_CE_TOP_NE_OFFSET__M 0x1FF -#define OFDM_CE_TOP_NE_OFFSET__PRE 0x0 - -#define OFDM_CE_TOP_NE_NUPD_TRH__A 0x2C1004C -#define OFDM_CE_TOP_NE_NUPD_TRH__W 5 -#define OFDM_CE_TOP_NE_NUPD_TRH__M 0x1F -#define OFDM_CE_TOP_NE_NUPD_TRH__PRE 0x14 - -#define OFDM_CE_TOP_PE_NEXP_OFFS__A 0x2C10050 -#define OFDM_CE_TOP_PE_NEXP_OFFS__W 8 -#define OFDM_CE_TOP_PE_NEXP_OFFS__M 0xFF -#define OFDM_CE_TOP_PE_NEXP_OFFS__PRE 0x0 - -#define OFDM_CE_TOP_PE_TIMESHIFT__A 0x2C10051 -#define OFDM_CE_TOP_PE_TIMESHIFT__W 14 -#define OFDM_CE_TOP_PE_TIMESHIFT__M 0x3FFF -#define OFDM_CE_TOP_PE_TIMESHIFT__PRE 0x0 - -#define OFDM_CE_TOP_PE_DIF_REAL_L__A 0x2C10052 -#define OFDM_CE_TOP_PE_DIF_REAL_L__W 16 -#define OFDM_CE_TOP_PE_DIF_REAL_L__M 0xFFFF -#define OFDM_CE_TOP_PE_DIF_REAL_L__PRE 0x0 - -#define OFDM_CE_TOP_PE_DIF_IMAG_L__A 0x2C10053 -#define OFDM_CE_TOP_PE_DIF_IMAG_L__W 16 -#define OFDM_CE_TOP_PE_DIF_IMAG_L__M 0xFFFF -#define OFDM_CE_TOP_PE_DIF_IMAG_L__PRE 0x0 - -#define OFDM_CE_TOP_PE_DIF_REAL_R__A 0x2C10054 -#define OFDM_CE_TOP_PE_DIF_REAL_R__W 16 -#define OFDM_CE_TOP_PE_DIF_REAL_R__M 0xFFFF -#define OFDM_CE_TOP_PE_DIF_REAL_R__PRE 0x0 - -#define OFDM_CE_TOP_PE_DIF_IMAG_R__A 0x2C10055 -#define OFDM_CE_TOP_PE_DIF_IMAG_R__W 16 -#define OFDM_CE_TOP_PE_DIF_IMAG_R__M 0xFFFF -#define OFDM_CE_TOP_PE_DIF_IMAG_R__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_REAL_L__A 0x2C10056 -#define OFDM_CE_TOP_PE_ABS_REAL_L__W 16 -#define OFDM_CE_TOP_PE_ABS_REAL_L__M 0xFFFF -#define OFDM_CE_TOP_PE_ABS_REAL_L__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_IMAG_L__A 0x2C10057 -#define OFDM_CE_TOP_PE_ABS_IMAG_L__W 16 -#define OFDM_CE_TOP_PE_ABS_IMAG_L__M 0xFFFF -#define OFDM_CE_TOP_PE_ABS_IMAG_L__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_REAL_R__A 0x2C10058 -#define OFDM_CE_TOP_PE_ABS_REAL_R__W 16 -#define OFDM_CE_TOP_PE_ABS_REAL_R__M 0xFFFF -#define OFDM_CE_TOP_PE_ABS_REAL_R__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_IMAG_R__A 0x2C10059 -#define OFDM_CE_TOP_PE_ABS_IMAG_R__W 16 -#define OFDM_CE_TOP_PE_ABS_IMAG_R__M 0xFFFF -#define OFDM_CE_TOP_PE_ABS_IMAG_R__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_EXP_L__A 0x2C1005A -#define OFDM_CE_TOP_PE_ABS_EXP_L__W 5 -#define OFDM_CE_TOP_PE_ABS_EXP_L__M 0x1F -#define OFDM_CE_TOP_PE_ABS_EXP_L__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_EXP_R__A 0x2C1005B -#define OFDM_CE_TOP_PE_ABS_EXP_R__W 5 -#define OFDM_CE_TOP_PE_ABS_EXP_R__M 0x1F -#define OFDM_CE_TOP_PE_ABS_EXP_R__PRE 0x0 - -#define OFDM_CE_TOP_TP_UPDATE_MODE__A 0x2C10060 -#define OFDM_CE_TOP_TP_UPDATE_MODE__W 1 -#define OFDM_CE_TOP_TP_UPDATE_MODE__M 0x1 -#define OFDM_CE_TOP_TP_UPDATE_MODE__PRE 0x0 - -#define OFDM_CE_TOP_TP_LMS_TAP_ON__A 0x2C10061 -#define OFDM_CE_TOP_TP_LMS_TAP_ON__W 1 -#define OFDM_CE_TOP_TP_LMS_TAP_ON__M 0x1 -#define OFDM_CE_TOP_TP_LMS_TAP_ON__PRE 0x0 - -#define OFDM_CE_TOP_TP_A0_TAP_NEW__A 0x2C10064 -#define OFDM_CE_TOP_TP_A0_TAP_NEW__W 10 -#define OFDM_CE_TOP_TP_A0_TAP_NEW__M 0x3FF -#define OFDM_CE_TOP_TP_A0_TAP_NEW__PRE 0x100 - -#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__A 0x2C10065 -#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__W 1 -#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__M 0x1 -#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__PRE 0x0 - -#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__A 0x2C10066 -#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__W 5 -#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__M 0x1F -#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__PRE 0xE - -#define OFDM_CE_TOP_TP_A0_TAP_CURR__A 0x2C10067 -#define OFDM_CE_TOP_TP_A0_TAP_CURR__W 10 -#define OFDM_CE_TOP_TP_A0_TAP_CURR__M 0x3FF -#define OFDM_CE_TOP_TP_A0_TAP_CURR__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_TAP_NEW__A 0x2C10068 -#define OFDM_CE_TOP_TP_A1_TAP_NEW__W 10 -#define OFDM_CE_TOP_TP_A1_TAP_NEW__M 0x3FF -#define OFDM_CE_TOP_TP_A1_TAP_NEW__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__A 0x2C10069 -#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__W 1 -#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__M 0x1 -#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__A 0x2C1006A -#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__W 5 -#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__M 0x1F -#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__PRE 0xA - -#define OFDM_CE_TOP_TP_A1_TAP_CURR__A 0x2C1006B -#define OFDM_CE_TOP_TP_A1_TAP_CURR__W 10 -#define OFDM_CE_TOP_TP_A1_TAP_CURR__M 0x3FF -#define OFDM_CE_TOP_TP_A1_TAP_CURR__PRE 0x0 -#define OFDM_CE_TOP_TP_DOPP_ENERGY__A 0x2C1006C -#define OFDM_CE_TOP_TP_DOPP_ENERGY__W 15 -#define OFDM_CE_TOP_TP_DOPP_ENERGY__M 0x7FFF -#define OFDM_CE_TOP_TP_DOPP_ENERGY__PRE 0x0 - -#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__B 10 -#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__W 5 -#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__B 0 -#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__W 10 -#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__PRE 0x0 - -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__A 0x2C1006D -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__W 15 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__M 0x7FFF -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__PRE 0x0 - -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__PRE 0x0 - -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__A 0x2C1006E -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__W 15 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__M 0x7FFF -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__PRE 0x0 - -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__B 10 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__W 5 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__B 0 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__W 10 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__A 0x2C1006F -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__W 15 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__M 0x7FFF -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__B 10 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__W 5 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__B 0 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__W 10 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__PRE 0x0 - - -#define OFDM_CE_TOP_TI_SYM_CNT__A 0x2C10072 -#define OFDM_CE_TOP_TI_SYM_CNT__W 6 -#define OFDM_CE_TOP_TI_SYM_CNT__M 0x3F -#define OFDM_CE_TOP_TI_SYM_CNT__PRE 0x20 - -#define OFDM_CE_TOP_TI_PHN_ENABLE__A 0x2C10073 -#define OFDM_CE_TOP_TI_PHN_ENABLE__W 1 -#define OFDM_CE_TOP_TI_PHN_ENABLE__M 0x1 -#define OFDM_CE_TOP_TI_PHN_ENABLE__PRE 0x1 - -#define OFDM_CE_TOP_TI_SHIFT__A 0x2C10074 -#define OFDM_CE_TOP_TI_SHIFT__W 2 -#define OFDM_CE_TOP_TI_SHIFT__M 0x3 -#define OFDM_CE_TOP_TI_SHIFT__PRE 0x0 - -#define OFDM_CE_TOP_TI_SLOW__A 0x2C10075 -#define OFDM_CE_TOP_TI_SLOW__W 1 -#define OFDM_CE_TOP_TI_SLOW__M 0x1 -#define OFDM_CE_TOP_TI_SLOW__PRE 0x1 - -#define OFDM_CE_TOP_TI_MGAIN__A 0x2C10076 -#define OFDM_CE_TOP_TI_MGAIN__W 8 -#define OFDM_CE_TOP_TI_MGAIN__M 0xFF -#define OFDM_CE_TOP_TI_MGAIN__PRE 0x0 - -#define OFDM_CE_TOP_TI_ACCU1__A 0x2C10077 -#define OFDM_CE_TOP_TI_ACCU1__W 8 -#define OFDM_CE_TOP_TI_ACCU1__M 0xFF -#define OFDM_CE_TOP_TI_ACCU1__PRE 0x0 - -#define OFDM_CE_TOP_NI_PER_LEFT__A 0x2C100B0 -#define OFDM_CE_TOP_NI_PER_LEFT__W 5 -#define OFDM_CE_TOP_NI_PER_LEFT__M 0x1F -#define OFDM_CE_TOP_NI_PER_LEFT__PRE 0xE - -#define OFDM_CE_TOP_NI_PER_RIGHT__A 0x2C100B1 -#define OFDM_CE_TOP_NI_PER_RIGHT__W 5 -#define OFDM_CE_TOP_NI_PER_RIGHT__M 0x1F -#define OFDM_CE_TOP_NI_PER_RIGHT__PRE 0x7 - -#define OFDM_CE_TOP_NI_POS_LR__A 0x2C100B2 -#define OFDM_CE_TOP_NI_POS_LR__W 9 -#define OFDM_CE_TOP_NI_POS_LR__M 0x1FF -#define OFDM_CE_TOP_NI_POS_LR__PRE 0xA0 - -#define OFDM_CE_TOP_FI_SHT_INCR__A 0x2C10090 -#define OFDM_CE_TOP_FI_SHT_INCR__W 9 -#define OFDM_CE_TOP_FI_SHT_INCR__M 0x1FF -#define OFDM_CE_TOP_FI_SHT_INCR__PRE 0x1E - -#define OFDM_CE_TOP_FI_EXP_NORM__A 0x2C10091 -#define OFDM_CE_TOP_FI_EXP_NORM__W 4 -#define OFDM_CE_TOP_FI_EXP_NORM__M 0xF -#define OFDM_CE_TOP_FI_EXP_NORM__PRE 0xC - -#define OFDM_CE_TOP_FI_SUPR_VAL__A 0x2C10092 -#define OFDM_CE_TOP_FI_SUPR_VAL__W 1 -#define OFDM_CE_TOP_FI_SUPR_VAL__M 0x1 -#define OFDM_CE_TOP_FI_SUPR_VAL__PRE 0x0 - -#define OFDM_CE_TOP_IR_INPUTSEL__A 0x2C100A0 -#define OFDM_CE_TOP_IR_INPUTSEL__W 1 -#define OFDM_CE_TOP_IR_INPUTSEL__M 0x1 -#define OFDM_CE_TOP_IR_INPUTSEL__PRE 0x0 - -#define OFDM_CE_TOP_IR_STARTPOS__A 0x2C100A1 -#define OFDM_CE_TOP_IR_STARTPOS__W 8 -#define OFDM_CE_TOP_IR_STARTPOS__M 0xFF -#define OFDM_CE_TOP_IR_STARTPOS__PRE 0x0 - -#define OFDM_CE_TOP_IR_NEXP_THRES__A 0x2C100A2 -#define OFDM_CE_TOP_IR_NEXP_THRES__W 8 -#define OFDM_CE_TOP_IR_NEXP_THRES__M 0xFF -#define OFDM_CE_TOP_IR_NEXP_THRES__PRE 0xFF - -#define OFDM_CE_TOP_IR_LENGTH__A 0x2C100A3 -#define OFDM_CE_TOP_IR_LENGTH__W 4 -#define OFDM_CE_TOP_IR_LENGTH__M 0xF -#define OFDM_CE_TOP_IR_LENGTH__PRE 0x9 - -#define OFDM_CE_TOP_IR_FREQ__A 0x2C100A4 -#define OFDM_CE_TOP_IR_FREQ__W 11 -#define OFDM_CE_TOP_IR_FREQ__M 0x7FF -#define OFDM_CE_TOP_IR_FREQ__PRE 0x0 - -#define OFDM_CE_TOP_IR_FREQINC__A 0x2C100A5 -#define OFDM_CE_TOP_IR_FREQINC__W 11 -#define OFDM_CE_TOP_IR_FREQINC__M 0x7FF -#define OFDM_CE_TOP_IR_FREQINC__PRE 0x4 - -#define OFDM_CE_TOP_IR_KAISINC__A 0x2C100A6 -#define OFDM_CE_TOP_IR_KAISINC__W 15 -#define OFDM_CE_TOP_IR_KAISINC__M 0x7FFF -#define OFDM_CE_TOP_IR_KAISINC__PRE 0x100 - -#define OFDM_CE_TOP_IR_CTL__A 0x2C100A7 -#define OFDM_CE_TOP_IR_CTL__W 3 -#define OFDM_CE_TOP_IR_CTL__M 0x7 -#define OFDM_CE_TOP_IR_CTL__PRE 0x0 - -#define OFDM_CE_TOP_IR_REAL__A 0x2C100A8 -#define OFDM_CE_TOP_IR_REAL__W 16 -#define OFDM_CE_TOP_IR_REAL__M 0xFFFF -#define OFDM_CE_TOP_IR_REAL__PRE 0x0 - -#define OFDM_CE_TOP_IR_IMAG__A 0x2C100A9 -#define OFDM_CE_TOP_IR_IMAG__W 16 -#define OFDM_CE_TOP_IR_IMAG__M 0xFFFF -#define OFDM_CE_TOP_IR_IMAG__PRE 0x0 - -#define OFDM_CE_TOP_IR_INDEX__A 0x2C100AA -#define OFDM_CE_TOP_IR_INDEX__W 12 -#define OFDM_CE_TOP_IR_INDEX__M 0xFFF -#define OFDM_CE_TOP_IR_INDEX__PRE 0x0 - - - -#define OFDM_CE_FR_COMM_EXEC__A 0x2C20000 -#define OFDM_CE_FR_COMM_EXEC__W 3 -#define OFDM_CE_FR_COMM_EXEC__M 0x7 -#define OFDM_CE_FR_COMM_EXEC__PRE 0x0 -#define OFDM_CE_FR_COMM_EXEC_STOP 0x0 -#define OFDM_CE_FR_COMM_EXEC_ACTIVE 0x1 -#define OFDM_CE_FR_COMM_EXEC_HOLD 0x2 -#define OFDM_CE_FR_COMM_EXEC_STEP 0x3 - - -#define OFDM_CE_FR_TREAL00__A 0x2C20010 -#define OFDM_CE_FR_TREAL00__W 11 -#define OFDM_CE_FR_TREAL00__M 0x7FF -#define OFDM_CE_FR_TREAL00__PRE 0x52 - -#define OFDM_CE_FR_TIMAG00__A 0x2C20011 -#define OFDM_CE_FR_TIMAG00__W 11 -#define OFDM_CE_FR_TIMAG00__M 0x7FF -#define OFDM_CE_FR_TIMAG00__PRE 0x0 - -#define OFDM_CE_FR_TREAL01__A 0x2C20012 -#define OFDM_CE_FR_TREAL01__W 11 -#define OFDM_CE_FR_TREAL01__M 0x7FF -#define OFDM_CE_FR_TREAL01__PRE 0x52 - -#define OFDM_CE_FR_TIMAG01__A 0x2C20013 -#define OFDM_CE_FR_TIMAG01__W 11 -#define OFDM_CE_FR_TIMAG01__M 0x7FF -#define OFDM_CE_FR_TIMAG01__PRE 0x0 - -#define OFDM_CE_FR_TREAL02__A 0x2C20014 -#define OFDM_CE_FR_TREAL02__W 11 -#define OFDM_CE_FR_TREAL02__M 0x7FF -#define OFDM_CE_FR_TREAL02__PRE 0x52 - -#define OFDM_CE_FR_TIMAG02__A 0x2C20015 -#define OFDM_CE_FR_TIMAG02__W 11 -#define OFDM_CE_FR_TIMAG02__M 0x7FF -#define OFDM_CE_FR_TIMAG02__PRE 0x0 - -#define OFDM_CE_FR_TREAL03__A 0x2C20016 -#define OFDM_CE_FR_TREAL03__W 11 -#define OFDM_CE_FR_TREAL03__M 0x7FF -#define OFDM_CE_FR_TREAL03__PRE 0x52 - -#define OFDM_CE_FR_TIMAG03__A 0x2C20017 -#define OFDM_CE_FR_TIMAG03__W 11 -#define OFDM_CE_FR_TIMAG03__M 0x7FF -#define OFDM_CE_FR_TIMAG03__PRE 0x0 - -#define OFDM_CE_FR_TREAL04__A 0x2C20018 -#define OFDM_CE_FR_TREAL04__W 11 -#define OFDM_CE_FR_TREAL04__M 0x7FF -#define OFDM_CE_FR_TREAL04__PRE 0x52 - -#define OFDM_CE_FR_TIMAG04__A 0x2C20019 -#define OFDM_CE_FR_TIMAG04__W 11 -#define OFDM_CE_FR_TIMAG04__M 0x7FF -#define OFDM_CE_FR_TIMAG04__PRE 0x0 - -#define OFDM_CE_FR_TREAL05__A 0x2C2001A -#define OFDM_CE_FR_TREAL05__W 11 -#define OFDM_CE_FR_TREAL05__M 0x7FF -#define OFDM_CE_FR_TREAL05__PRE 0x52 - -#define OFDM_CE_FR_TIMAG05__A 0x2C2001B -#define OFDM_CE_FR_TIMAG05__W 11 -#define OFDM_CE_FR_TIMAG05__M 0x7FF -#define OFDM_CE_FR_TIMAG05__PRE 0x0 - -#define OFDM_CE_FR_TREAL06__A 0x2C2001C -#define OFDM_CE_FR_TREAL06__W 11 -#define OFDM_CE_FR_TREAL06__M 0x7FF -#define OFDM_CE_FR_TREAL06__PRE 0x52 - -#define OFDM_CE_FR_TIMAG06__A 0x2C2001D -#define OFDM_CE_FR_TIMAG06__W 11 -#define OFDM_CE_FR_TIMAG06__M 0x7FF -#define OFDM_CE_FR_TIMAG06__PRE 0x0 - -#define OFDM_CE_FR_TREAL07__A 0x2C2001E -#define OFDM_CE_FR_TREAL07__W 11 -#define OFDM_CE_FR_TREAL07__M 0x7FF -#define OFDM_CE_FR_TREAL07__PRE 0x52 - -#define OFDM_CE_FR_TIMAG07__A 0x2C2001F -#define OFDM_CE_FR_TIMAG07__W 11 -#define OFDM_CE_FR_TIMAG07__M 0x7FF -#define OFDM_CE_FR_TIMAG07__PRE 0x0 - -#define OFDM_CE_FR_TREAL08__A 0x2C20020 -#define OFDM_CE_FR_TREAL08__W 11 -#define OFDM_CE_FR_TREAL08__M 0x7FF -#define OFDM_CE_FR_TREAL08__PRE 0x52 - -#define OFDM_CE_FR_TIMAG08__A 0x2C20021 -#define OFDM_CE_FR_TIMAG08__W 11 -#define OFDM_CE_FR_TIMAG08__M 0x7FF -#define OFDM_CE_FR_TIMAG08__PRE 0x0 - -#define OFDM_CE_FR_TREAL09__A 0x2C20022 -#define OFDM_CE_FR_TREAL09__W 11 -#define OFDM_CE_FR_TREAL09__M 0x7FF -#define OFDM_CE_FR_TREAL09__PRE 0x52 - -#define OFDM_CE_FR_TIMAG09__A 0x2C20023 -#define OFDM_CE_FR_TIMAG09__W 11 -#define OFDM_CE_FR_TIMAG09__M 0x7FF -#define OFDM_CE_FR_TIMAG09__PRE 0x0 - -#define OFDM_CE_FR_TREAL10__A 0x2C20024 -#define OFDM_CE_FR_TREAL10__W 11 -#define OFDM_CE_FR_TREAL10__M 0x7FF -#define OFDM_CE_FR_TREAL10__PRE 0x52 - -#define OFDM_CE_FR_TIMAG10__A 0x2C20025 -#define OFDM_CE_FR_TIMAG10__W 11 -#define OFDM_CE_FR_TIMAG10__M 0x7FF -#define OFDM_CE_FR_TIMAG10__PRE 0x0 - -#define OFDM_CE_FR_TREAL11__A 0x2C20026 -#define OFDM_CE_FR_TREAL11__W 11 -#define OFDM_CE_FR_TREAL11__M 0x7FF -#define OFDM_CE_FR_TREAL11__PRE 0x52 - -#define OFDM_CE_FR_TIMAG11__A 0x2C20027 -#define OFDM_CE_FR_TIMAG11__W 11 -#define OFDM_CE_FR_TIMAG11__M 0x7FF -#define OFDM_CE_FR_TIMAG11__PRE 0x0 - -#define OFDM_CE_FR_MID_TAP__A 0x2C20028 -#define OFDM_CE_FR_MID_TAP__W 11 -#define OFDM_CE_FR_MID_TAP__M 0x7FF -#define OFDM_CE_FR_MID_TAP__PRE 0x51 - -#define OFDM_CE_FR_SQS_G00__A 0x2C20029 -#define OFDM_CE_FR_SQS_G00__W 8 -#define OFDM_CE_FR_SQS_G00__M 0xFF -#define OFDM_CE_FR_SQS_G00__PRE 0xB - -#define OFDM_CE_FR_SQS_G01__A 0x2C2002A -#define OFDM_CE_FR_SQS_G01__W 8 -#define OFDM_CE_FR_SQS_G01__M 0xFF -#define OFDM_CE_FR_SQS_G01__PRE 0xB - -#define OFDM_CE_FR_SQS_G02__A 0x2C2002B -#define OFDM_CE_FR_SQS_G02__W 8 -#define OFDM_CE_FR_SQS_G02__M 0xFF -#define OFDM_CE_FR_SQS_G02__PRE 0xB - -#define OFDM_CE_FR_SQS_G03__A 0x2C2002C -#define OFDM_CE_FR_SQS_G03__W 8 -#define OFDM_CE_FR_SQS_G03__M 0xFF -#define OFDM_CE_FR_SQS_G03__PRE 0xB - -#define OFDM_CE_FR_SQS_G04__A 0x2C2002D -#define OFDM_CE_FR_SQS_G04__W 8 -#define OFDM_CE_FR_SQS_G04__M 0xFF -#define OFDM_CE_FR_SQS_G04__PRE 0xB - -#define OFDM_CE_FR_SQS_G05__A 0x2C2002E -#define OFDM_CE_FR_SQS_G05__W 8 -#define OFDM_CE_FR_SQS_G05__M 0xFF -#define OFDM_CE_FR_SQS_G05__PRE 0xB - -#define OFDM_CE_FR_SQS_G06__A 0x2C2002F -#define OFDM_CE_FR_SQS_G06__W 8 -#define OFDM_CE_FR_SQS_G06__M 0xFF -#define OFDM_CE_FR_SQS_G06__PRE 0xB - -#define OFDM_CE_FR_SQS_G07__A 0x2C20030 -#define OFDM_CE_FR_SQS_G07__W 8 -#define OFDM_CE_FR_SQS_G07__M 0xFF -#define OFDM_CE_FR_SQS_G07__PRE 0xB - -#define OFDM_CE_FR_SQS_G08__A 0x2C20031 -#define OFDM_CE_FR_SQS_G08__W 8 -#define OFDM_CE_FR_SQS_G08__M 0xFF -#define OFDM_CE_FR_SQS_G08__PRE 0xB - -#define OFDM_CE_FR_SQS_G09__A 0x2C20032 -#define OFDM_CE_FR_SQS_G09__W 8 -#define OFDM_CE_FR_SQS_G09__M 0xFF -#define OFDM_CE_FR_SQS_G09__PRE 0xB - -#define OFDM_CE_FR_SQS_G10__A 0x2C20033 -#define OFDM_CE_FR_SQS_G10__W 8 -#define OFDM_CE_FR_SQS_G10__M 0xFF -#define OFDM_CE_FR_SQS_G10__PRE 0xB - -#define OFDM_CE_FR_SQS_G11__A 0x2C20034 -#define OFDM_CE_FR_SQS_G11__W 8 -#define OFDM_CE_FR_SQS_G11__M 0xFF -#define OFDM_CE_FR_SQS_G11__PRE 0xB - -#define OFDM_CE_FR_SQS_G12__A 0x2C20035 -#define OFDM_CE_FR_SQS_G12__W 8 -#define OFDM_CE_FR_SQS_G12__M 0xFF -#define OFDM_CE_FR_SQS_G12__PRE 0x5 - -#define OFDM_CE_FR_RIO_G00__A 0x2C20036 -#define OFDM_CE_FR_RIO_G00__W 9 -#define OFDM_CE_FR_RIO_G00__M 0x1FF -#define OFDM_CE_FR_RIO_G00__PRE 0x1FF - -#define OFDM_CE_FR_RIO_G01__A 0x2C20037 -#define OFDM_CE_FR_RIO_G01__W 9 -#define OFDM_CE_FR_RIO_G01__M 0x1FF -#define OFDM_CE_FR_RIO_G01__PRE 0x190 - -#define OFDM_CE_FR_RIO_G02__A 0x2C20038 -#define OFDM_CE_FR_RIO_G02__W 9 -#define OFDM_CE_FR_RIO_G02__M 0x1FF -#define OFDM_CE_FR_RIO_G02__PRE 0x10B - -#define OFDM_CE_FR_RIO_G03__A 0x2C20039 -#define OFDM_CE_FR_RIO_G03__W 9 -#define OFDM_CE_FR_RIO_G03__M 0x1FF -#define OFDM_CE_FR_RIO_G03__PRE 0xC8 - -#define OFDM_CE_FR_RIO_G04__A 0x2C2003A -#define OFDM_CE_FR_RIO_G04__W 9 -#define OFDM_CE_FR_RIO_G04__M 0x1FF -#define OFDM_CE_FR_RIO_G04__PRE 0xA0 - -#define OFDM_CE_FR_RIO_G05__A 0x2C2003B -#define OFDM_CE_FR_RIO_G05__W 9 -#define OFDM_CE_FR_RIO_G05__M 0x1FF -#define OFDM_CE_FR_RIO_G05__PRE 0x85 - -#define OFDM_CE_FR_RIO_G06__A 0x2C2003C -#define OFDM_CE_FR_RIO_G06__W 9 -#define OFDM_CE_FR_RIO_G06__M 0x1FF -#define OFDM_CE_FR_RIO_G06__PRE 0x72 - -#define OFDM_CE_FR_RIO_G07__A 0x2C2003D -#define OFDM_CE_FR_RIO_G07__W 9 -#define OFDM_CE_FR_RIO_G07__M 0x1FF -#define OFDM_CE_FR_RIO_G07__PRE 0x64 - -#define OFDM_CE_FR_RIO_G08__A 0x2C2003E -#define OFDM_CE_FR_RIO_G08__W 9 -#define OFDM_CE_FR_RIO_G08__M 0x1FF -#define OFDM_CE_FR_RIO_G08__PRE 0x59 - -#define OFDM_CE_FR_RIO_G09__A 0x2C2003F -#define OFDM_CE_FR_RIO_G09__W 9 -#define OFDM_CE_FR_RIO_G09__M 0x1FF -#define OFDM_CE_FR_RIO_G09__PRE 0x50 - -#define OFDM_CE_FR_RIO_G10__A 0x2C20040 -#define OFDM_CE_FR_RIO_G10__W 9 -#define OFDM_CE_FR_RIO_G10__M 0x1FF -#define OFDM_CE_FR_RIO_G10__PRE 0x49 -#define OFDM_CE_FR_MODE__A 0x2C20041 -#define OFDM_CE_FR_MODE__W 9 -#define OFDM_CE_FR_MODE__M 0x1FF -#define OFDM_CE_FR_MODE__PRE 0xDE - -#define OFDM_CE_FR_MODE_UPDATE_ENABLE__B 0 -#define OFDM_CE_FR_MODE_UPDATE_ENABLE__W 1 -#define OFDM_CE_FR_MODE_UPDATE_ENABLE__M 0x1 -#define OFDM_CE_FR_MODE_UPDATE_ENABLE__PRE 0x0 - -#define OFDM_CE_FR_MODE_ERROR_SHIFT__B 1 -#define OFDM_CE_FR_MODE_ERROR_SHIFT__W 1 -#define OFDM_CE_FR_MODE_ERROR_SHIFT__M 0x2 -#define OFDM_CE_FR_MODE_ERROR_SHIFT__PRE 0x2 - -#define OFDM_CE_FR_MODE_NEXP_UPDATE__B 2 -#define OFDM_CE_FR_MODE_NEXP_UPDATE__W 1 -#define OFDM_CE_FR_MODE_NEXP_UPDATE__M 0x4 -#define OFDM_CE_FR_MODE_NEXP_UPDATE__PRE 0x4 - -#define OFDM_CE_FR_MODE_MANUAL_SHIFT__B 3 -#define OFDM_CE_FR_MODE_MANUAL_SHIFT__W 1 -#define OFDM_CE_FR_MODE_MANUAL_SHIFT__M 0x8 -#define OFDM_CE_FR_MODE_MANUAL_SHIFT__PRE 0x8 - -#define OFDM_CE_FR_MODE_SQUASH_MODE__B 4 -#define OFDM_CE_FR_MODE_SQUASH_MODE__W 1 -#define OFDM_CE_FR_MODE_SQUASH_MODE__M 0x10 -#define OFDM_CE_FR_MODE_SQUASH_MODE__PRE 0x10 - -#define OFDM_CE_FR_MODE_UPDATE_MODE__B 5 -#define OFDM_CE_FR_MODE_UPDATE_MODE__W 1 -#define OFDM_CE_FR_MODE_UPDATE_MODE__M 0x20 -#define OFDM_CE_FR_MODE_UPDATE_MODE__PRE 0x0 - -#define OFDM_CE_FR_MODE_MID_MODE__B 6 -#define OFDM_CE_FR_MODE_MID_MODE__W 1 -#define OFDM_CE_FR_MODE_MID_MODE__M 0x40 -#define OFDM_CE_FR_MODE_MID_MODE__PRE 0x40 - -#define OFDM_CE_FR_MODE_NOISE_MODE__B 7 -#define OFDM_CE_FR_MODE_NOISE_MODE__W 1 -#define OFDM_CE_FR_MODE_NOISE_MODE__M 0x80 -#define OFDM_CE_FR_MODE_NOISE_MODE__PRE 0x80 - -#define OFDM_CE_FR_MODE_NOTCH_MODE__B 8 -#define OFDM_CE_FR_MODE_NOTCH_MODE__W 1 -#define OFDM_CE_FR_MODE_NOTCH_MODE__M 0x100 -#define OFDM_CE_FR_MODE_NOTCH_MODE__PRE 0x0 - - -#define OFDM_CE_FR_SQS_TRH__A 0x2C20042 -#define OFDM_CE_FR_SQS_TRH__W 8 -#define OFDM_CE_FR_SQS_TRH__M 0xFF -#define OFDM_CE_FR_SQS_TRH__PRE 0x80 - -#define OFDM_CE_FR_RIO_GAIN__A 0x2C20043 -#define OFDM_CE_FR_RIO_GAIN__W 3 -#define OFDM_CE_FR_RIO_GAIN__M 0x7 -#define OFDM_CE_FR_RIO_GAIN__PRE 0x7 -#define OFDM_CE_FR_BYPASS__A 0x2C20044 -#define OFDM_CE_FR_BYPASS__W 10 -#define OFDM_CE_FR_BYPASS__M 0x3FF -#define OFDM_CE_FR_BYPASS__PRE 0x13B - -#define OFDM_CE_FR_BYPASS_RUN_IN__B 0 -#define OFDM_CE_FR_BYPASS_RUN_IN__W 4 -#define OFDM_CE_FR_BYPASS_RUN_IN__M 0xF -#define OFDM_CE_FR_BYPASS_RUN_IN__PRE 0xB - -#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__B 4 -#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__W 5 -#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 -#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__PRE 0x130 - -#define OFDM_CE_FR_BYPASS_TOTAL__B 9 -#define OFDM_CE_FR_BYPASS_TOTAL__W 1 -#define OFDM_CE_FR_BYPASS_TOTAL__M 0x200 -#define OFDM_CE_FR_BYPASS_TOTAL__PRE 0x0 - - -#define OFDM_CE_FR_PM_SET__A 0x2C20045 -#define OFDM_CE_FR_PM_SET__W 4 -#define OFDM_CE_FR_PM_SET__M 0xF -#define OFDM_CE_FR_PM_SET__PRE 0xD - -#define OFDM_CE_FR_ERR_SH__A 0x2C20046 -#define OFDM_CE_FR_ERR_SH__W 4 -#define OFDM_CE_FR_ERR_SH__M 0xF -#define OFDM_CE_FR_ERR_SH__PRE 0x4 - -#define OFDM_CE_FR_MAN_SH__A 0x2C20047 -#define OFDM_CE_FR_MAN_SH__W 4 -#define OFDM_CE_FR_MAN_SH__M 0xF -#define OFDM_CE_FR_MAN_SH__PRE 0x7 - -#define OFDM_CE_FR_TAP_SH__A 0x2C20048 -#define OFDM_CE_FR_TAP_SH__W 3 -#define OFDM_CE_FR_TAP_SH__M 0x7 -#define OFDM_CE_FR_TAP_SH__PRE 0x3 - -#define OFDM_CE_FR_CLIP__A 0x2C20049 -#define OFDM_CE_FR_CLIP__W 9 -#define OFDM_CE_FR_CLIP__M 0x1FF -#define OFDM_CE_FR_CLIP__PRE 0x49 - -#define OFDM_CE_FR_LEAK_UPD__A 0x2C2004A -#define OFDM_CE_FR_LEAK_UPD__W 3 -#define OFDM_CE_FR_LEAK_UPD__M 0x7 -#define OFDM_CE_FR_LEAK_UPD__PRE 0x0 - -#define OFDM_CE_FR_LEAK_SH__A 0x2C2004B -#define OFDM_CE_FR_LEAK_SH__W 3 -#define OFDM_CE_FR_LEAK_SH__M 0x7 -#define OFDM_CE_FR_LEAK_SH__PRE 0x1 - - - -#define OFDM_CE_NE_RAM__A 0x2C30000 - - - -#define OFDM_CE_PB_RAM__A 0x2C40000 - - - - - -#define OFDM_CP_COMM_EXEC__A 0x2800000 -#define OFDM_CP_COMM_EXEC__W 3 -#define OFDM_CP_COMM_EXEC__M 0x7 -#define OFDM_CP_COMM_EXEC__PRE 0x0 -#define OFDM_CP_COMM_EXEC_STOP 0x0 -#define OFDM_CP_COMM_EXEC_ACTIVE 0x1 -#define OFDM_CP_COMM_EXEC_HOLD 0x2 -#define OFDM_CP_COMM_EXEC_STEP 0x3 -#define OFDM_CP_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_CP_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_CP_COMM_STATE__A 0x2800001 -#define OFDM_CP_COMM_STATE__W 16 -#define OFDM_CP_COMM_STATE__M 0xFFFF -#define OFDM_CP_COMM_STATE__PRE 0x0 -#define OFDM_CP_COMM_MB__A 0x2800002 -#define OFDM_CP_COMM_MB__W 16 -#define OFDM_CP_COMM_MB__M 0xFFFF -#define OFDM_CP_COMM_MB__PRE 0x0 -#define OFDM_CP_COMM_INT_REQ__A 0x2800004 -#define OFDM_CP_COMM_INT_REQ__W 16 -#define OFDM_CP_COMM_INT_REQ__M 0xFFFF -#define OFDM_CP_COMM_INT_REQ__PRE 0x0 -#define OFDM_CP_COMM_INT_REQ_TOP_REQ__B 1 -#define OFDM_CP_COMM_INT_REQ_TOP_REQ__W 1 -#define OFDM_CP_COMM_INT_REQ_TOP_REQ__M 0x2 -#define OFDM_CP_COMM_INT_REQ_TOP_REQ__PRE 0x0 - -#define OFDM_CP_COMM_INT_STA__A 0x2800005 -#define OFDM_CP_COMM_INT_STA__W 16 -#define OFDM_CP_COMM_INT_STA__M 0xFFFF -#define OFDM_CP_COMM_INT_STA__PRE 0x0 -#define OFDM_CP_COMM_INT_MSK__A 0x2800006 -#define OFDM_CP_COMM_INT_MSK__W 16 -#define OFDM_CP_COMM_INT_MSK__M 0xFFFF -#define OFDM_CP_COMM_INT_MSK__PRE 0x0 -#define OFDM_CP_COMM_INT_STM__A 0x2800007 -#define OFDM_CP_COMM_INT_STM__W 16 -#define OFDM_CP_COMM_INT_STM__M 0xFFFF -#define OFDM_CP_COMM_INT_STM__PRE 0x0 -#define OFDM_CP_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_CP_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_CP_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_CP_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_CP_TOP_COMM_EXEC__A 0x2810000 -#define OFDM_CP_TOP_COMM_EXEC__W 3 -#define OFDM_CP_TOP_COMM_EXEC__M 0x7 -#define OFDM_CP_TOP_COMM_EXEC__PRE 0x0 -#define OFDM_CP_TOP_COMM_EXEC_STOP 0x0 -#define OFDM_CP_TOP_COMM_EXEC_ACTIVE 0x1 -#define OFDM_CP_TOP_COMM_EXEC_HOLD 0x2 -#define OFDM_CP_TOP_COMM_EXEC_STEP 0x3 - -#define OFDM_CP_TOP_COMM_MB__A 0x2810002 -#define OFDM_CP_TOP_COMM_MB__W 3 -#define OFDM_CP_TOP_COMM_MB__M 0x7 -#define OFDM_CP_TOP_COMM_MB__PRE 0x0 -#define OFDM_CP_TOP_COMM_MB_CTL__B 0 -#define OFDM_CP_TOP_COMM_MB_CTL__W 1 -#define OFDM_CP_TOP_COMM_MB_CTL__M 0x1 -#define OFDM_CP_TOP_COMM_MB_CTL__PRE 0x0 -#define OFDM_CP_TOP_COMM_MB_CTL_OFF 0x0 -#define OFDM_CP_TOP_COMM_MB_CTL_ON 0x1 -#define OFDM_CP_TOP_COMM_MB_OBS__B 1 -#define OFDM_CP_TOP_COMM_MB_OBS__W 1 -#define OFDM_CP_TOP_COMM_MB_OBS__M 0x2 -#define OFDM_CP_TOP_COMM_MB_OBS__PRE 0x0 -#define OFDM_CP_TOP_COMM_MB_OBS_OFF 0x0 -#define OFDM_CP_TOP_COMM_MB_OBS_ON 0x2 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX__B 2 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX__W 1 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX__M 0x4 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX__PRE 0x0 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX_CE 0x0 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX_DL 0x4 - -#define OFDM_CP_TOP_COMM_INT_REQ__A 0x2810004 -#define OFDM_CP_TOP_COMM_INT_REQ__W 1 -#define OFDM_CP_TOP_COMM_INT_REQ__M 0x1 -#define OFDM_CP_TOP_COMM_INT_REQ__PRE 0x0 -#define OFDM_CP_TOP_COMM_INT_STA__A 0x2810005 -#define OFDM_CP_TOP_COMM_INT_STA__W 1 -#define OFDM_CP_TOP_COMM_INT_STA__M 0x1 -#define OFDM_CP_TOP_COMM_INT_STA__PRE 0x0 -#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__B 0 -#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__W 1 -#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__M 0x1 -#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__PRE 0x0 - -#define OFDM_CP_TOP_COMM_INT_MSK__A 0x2810006 -#define OFDM_CP_TOP_COMM_INT_MSK__W 1 -#define OFDM_CP_TOP_COMM_INT_MSK__M 0x1 -#define OFDM_CP_TOP_COMM_INT_MSK__PRE 0x0 -#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__B 0 -#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__W 1 -#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__M 0x1 -#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__PRE 0x0 - -#define OFDM_CP_TOP_COMM_INT_STM__A 0x2810007 -#define OFDM_CP_TOP_COMM_INT_STM__W 1 -#define OFDM_CP_TOP_COMM_INT_STM__M 0x1 -#define OFDM_CP_TOP_COMM_INT_STM__PRE 0x0 -#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__B 0 -#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__W 1 -#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__M 0x1 -#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__PRE 0x0 - - -#define OFDM_CP_TOP_MODE_2K__A 0x2810010 -#define OFDM_CP_TOP_MODE_2K__W 1 -#define OFDM_CP_TOP_MODE_2K__M 0x1 -#define OFDM_CP_TOP_MODE_2K__PRE 0x0 - -#define OFDM_CP_TOP_INTERVAL__A 0x2810011 -#define OFDM_CP_TOP_INTERVAL__W 4 -#define OFDM_CP_TOP_INTERVAL__M 0xF -#define OFDM_CP_TOP_INTERVAL__PRE 0x5 -#define OFDM_CP_TOP_DETECT_ENA__A 0x2810012 -#define OFDM_CP_TOP_DETECT_ENA__W 2 -#define OFDM_CP_TOP_DETECT_ENA__M 0x3 -#define OFDM_CP_TOP_DETECT_ENA__PRE 0x0 - -#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__B 0 -#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__W 1 -#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__M 0x1 -#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__PRE 0x0 - -#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__B 1 -#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__W 1 -#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__M 0x2 -#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__PRE 0x0 - -#define OFDM_CP_TOP_FIX__A 0x2810013 -#define OFDM_CP_TOP_FIX__W 4 -#define OFDM_CP_TOP_FIX__M 0xF -#define OFDM_CP_TOP_FIX__PRE 0xF - -#define OFDM_CP_TOP_FIX_RT_SPD_MIX__B 0 -#define OFDM_CP_TOP_FIX_RT_SPD_MIX__W 1 -#define OFDM_CP_TOP_FIX_RT_SPD_MIX__M 0x1 -#define OFDM_CP_TOP_FIX_RT_SPD_MIX__PRE 0x1 -#define OFDM_CP_TOP_FIX_RT_SPD_MIX_DISABLE 0x0 -#define OFDM_CP_TOP_FIX_RT_SPD_MIX_ENABLE 0x1 - -#define OFDM_CP_TOP_FIX_RT_SPD_ADD__B 1 -#define OFDM_CP_TOP_FIX_RT_SPD_ADD__W 1 -#define OFDM_CP_TOP_FIX_RT_SPD_ADD__M 0x2 -#define OFDM_CP_TOP_FIX_RT_SPD_ADD__PRE 0x2 -#define OFDM_CP_TOP_FIX_RT_SPD_ADD_DISABLE 0x0 -#define OFDM_CP_TOP_FIX_RT_SPD_ADD_ENABLE 0x2 - -#define OFDM_CP_TOP_FIX_RT_SPD_CLP__B 2 -#define OFDM_CP_TOP_FIX_RT_SPD_CLP__W 1 -#define OFDM_CP_TOP_FIX_RT_SPD_CLP__M 0x4 -#define OFDM_CP_TOP_FIX_RT_SPD_CLP__PRE 0x4 -#define OFDM_CP_TOP_FIX_RT_SPD_CLP_DISABLE 0x0 -#define OFDM_CP_TOP_FIX_RT_SPD_CLP_ENABLE 0x4 - -#define OFDM_CP_TOP_FIX_RT_SPD_SSH__B 3 -#define OFDM_CP_TOP_FIX_RT_SPD_SSH__W 1 -#define OFDM_CP_TOP_FIX_RT_SPD_SSH__M 0x8 -#define OFDM_CP_TOP_FIX_RT_SPD_SSH__PRE 0x8 -#define OFDM_CP_TOP_FIX_RT_SPD_SSH_DISABLE 0x0 -#define OFDM_CP_TOP_FIX_RT_SPD_SSH_ENABLE 0x8 - -#define OFDM_CP_TOP_BR_SMB_NR__A 0x2810021 -#define OFDM_CP_TOP_BR_SMB_NR__W 4 -#define OFDM_CP_TOP_BR_SMB_NR__M 0xF -#define OFDM_CP_TOP_BR_SMB_NR__PRE 0x0 - -#define OFDM_CP_TOP_BR_SMB_NR_SMB__B 0 -#define OFDM_CP_TOP_BR_SMB_NR_SMB__W 2 -#define OFDM_CP_TOP_BR_SMB_NR_SMB__M 0x3 -#define OFDM_CP_TOP_BR_SMB_NR_SMB__PRE 0x0 - -#define OFDM_CP_TOP_BR_SMB_NR_VAL__B 2 -#define OFDM_CP_TOP_BR_SMB_NR_VAL__W 1 -#define OFDM_CP_TOP_BR_SMB_NR_VAL__M 0x4 -#define OFDM_CP_TOP_BR_SMB_NR_VAL__PRE 0x0 - -#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__B 3 -#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__W 1 -#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__M 0x8 -#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__PRE 0x0 - - -#define OFDM_CP_TOP_BR_CP_SMB_NR__A 0x2810022 -#define OFDM_CP_TOP_BR_CP_SMB_NR__W 2 -#define OFDM_CP_TOP_BR_CP_SMB_NR__M 0x3 -#define OFDM_CP_TOP_BR_CP_SMB_NR__PRE 0x0 - -#define OFDM_CP_TOP_BR_SPL_OFFSET__A 0x2810023 -#define OFDM_CP_TOP_BR_SPL_OFFSET__W 4 -#define OFDM_CP_TOP_BR_SPL_OFFSET__M 0xF -#define OFDM_CP_TOP_BR_SPL_OFFSET__PRE 0x8 - -#define OFDM_CP_TOP_BR_STR_DEL__A 0x2810024 -#define OFDM_CP_TOP_BR_STR_DEL__W 10 -#define OFDM_CP_TOP_BR_STR_DEL__M 0x3FF -#define OFDM_CP_TOP_BR_STR_DEL__PRE 0xA - -#define OFDM_CP_TOP_BR_EXP_ADJ__A 0x2810025 -#define OFDM_CP_TOP_BR_EXP_ADJ__W 5 -#define OFDM_CP_TOP_BR_EXP_ADJ__M 0x1F -#define OFDM_CP_TOP_BR_EXP_ADJ__PRE 0x10 - -#define OFDM_CP_TOP_RT_ANG_INC0__A 0x2810030 -#define OFDM_CP_TOP_RT_ANG_INC0__W 16 -#define OFDM_CP_TOP_RT_ANG_INC0__M 0xFFFF -#define OFDM_CP_TOP_RT_ANG_INC0__PRE 0x0 - -#define OFDM_CP_TOP_RT_ANG_INC1__A 0x2810031 -#define OFDM_CP_TOP_RT_ANG_INC1__W 8 -#define OFDM_CP_TOP_RT_ANG_INC1__M 0xFF -#define OFDM_CP_TOP_RT_ANG_INC1__PRE 0x0 - -#define OFDM_CP_TOP_RT_SPD_EXP_MARG__A 0x2810032 -#define OFDM_CP_TOP_RT_SPD_EXP_MARG__W 5 -#define OFDM_CP_TOP_RT_SPD_EXP_MARG__M 0x1F -#define OFDM_CP_TOP_RT_SPD_EXP_MARG__PRE 0x5 - -#define OFDM_CP_TOP_RT_DETECT_TRH__A 0x2810033 -#define OFDM_CP_TOP_RT_DETECT_TRH__W 2 -#define OFDM_CP_TOP_RT_DETECT_TRH__M 0x3 -#define OFDM_CP_TOP_RT_DETECT_TRH__PRE 0x3 - -#define OFDM_CP_TOP_RT_SPD_RELIABLE__A 0x2810034 -#define OFDM_CP_TOP_RT_SPD_RELIABLE__W 3 -#define OFDM_CP_TOP_RT_SPD_RELIABLE__M 0x7 -#define OFDM_CP_TOP_RT_SPD_RELIABLE__PRE 0x0 - -#define OFDM_CP_TOP_RT_SPD_DIRECTION__A 0x2810035 -#define OFDM_CP_TOP_RT_SPD_DIRECTION__W 1 -#define OFDM_CP_TOP_RT_SPD_DIRECTION__M 0x1 -#define OFDM_CP_TOP_RT_SPD_DIRECTION__PRE 0x0 - -#define OFDM_CP_TOP_RT_SPD_MOD__A 0x2810036 -#define OFDM_CP_TOP_RT_SPD_MOD__W 2 -#define OFDM_CP_TOP_RT_SPD_MOD__M 0x3 -#define OFDM_CP_TOP_RT_SPD_MOD__PRE 0x0 - -#define OFDM_CP_TOP_RT_SPD_SMB__A 0x2810037 -#define OFDM_CP_TOP_RT_SPD_SMB__W 2 -#define OFDM_CP_TOP_RT_SPD_SMB__M 0x3 -#define OFDM_CP_TOP_RT_SPD_SMB__PRE 0x0 -#define OFDM_CP_TOP_RT_CPD_MODE__A 0x2810038 -#define OFDM_CP_TOP_RT_CPD_MODE__W 3 -#define OFDM_CP_TOP_RT_CPD_MODE__M 0x7 -#define OFDM_CP_TOP_RT_CPD_MODE__PRE 0x0 - -#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__B 0 -#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__W 2 -#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__M 0x3 -#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__PRE 0x0 - -#define OFDM_CP_TOP_RT_CPD_MODE_ADD__B 2 -#define OFDM_CP_TOP_RT_CPD_MODE_ADD__W 1 -#define OFDM_CP_TOP_RT_CPD_MODE_ADD__M 0x4 -#define OFDM_CP_TOP_RT_CPD_MODE_ADD__PRE 0x0 - - -#define OFDM_CP_TOP_RT_CPD_RELIABLE__A 0x2810039 -#define OFDM_CP_TOP_RT_CPD_RELIABLE__W 3 -#define OFDM_CP_TOP_RT_CPD_RELIABLE__M 0x7 -#define OFDM_CP_TOP_RT_CPD_RELIABLE__PRE 0x0 - -#define OFDM_CP_TOP_RT_CPD_BIN__A 0x281003A -#define OFDM_CP_TOP_RT_CPD_BIN__W 5 -#define OFDM_CP_TOP_RT_CPD_BIN__M 0x1F -#define OFDM_CP_TOP_RT_CPD_BIN__PRE 0x0 - -#define OFDM_CP_TOP_RT_CPD_MAX__A 0x281003B -#define OFDM_CP_TOP_RT_CPD_MAX__W 4 -#define OFDM_CP_TOP_RT_CPD_MAX__M 0xF -#define OFDM_CP_TOP_RT_CPD_MAX__PRE 0x0 -#define OFDM_CP_TOP_RT_SUPR_VAL__A 0x281003C -#define OFDM_CP_TOP_RT_SUPR_VAL__W 2 -#define OFDM_CP_TOP_RT_SUPR_VAL__M 0x3 -#define OFDM_CP_TOP_RT_SUPR_VAL__PRE 0x0 - -#define OFDM_CP_TOP_RT_SUPR_VAL_CE__B 0 -#define OFDM_CP_TOP_RT_SUPR_VAL_CE__W 1 -#define OFDM_CP_TOP_RT_SUPR_VAL_CE__M 0x1 -#define OFDM_CP_TOP_RT_SUPR_VAL_CE__PRE 0x0 - -#define OFDM_CP_TOP_RT_SUPR_VAL_DL__B 1 -#define OFDM_CP_TOP_RT_SUPR_VAL_DL__W 1 -#define OFDM_CP_TOP_RT_SUPR_VAL_DL__M 0x2 -#define OFDM_CP_TOP_RT_SUPR_VAL_DL__PRE 0x0 - - -#define OFDM_CP_TOP_RT_EXP_AVE__A 0x281003D -#define OFDM_CP_TOP_RT_EXP_AVE__W 5 -#define OFDM_CP_TOP_RT_EXP_AVE__M 0x1F -#define OFDM_CP_TOP_RT_EXP_AVE__PRE 0x0 - -#define OFDM_CP_TOP_RT_CPD_EXP_MARG__A 0x281003E -#define OFDM_CP_TOP_RT_CPD_EXP_MARG__W 5 -#define OFDM_CP_TOP_RT_CPD_EXP_MARG__M 0x1F -#define OFDM_CP_TOP_RT_CPD_EXP_MARG__PRE 0x3 - -#define OFDM_CP_TOP_AC_NEXP_OFFS__A 0x2810040 -#define OFDM_CP_TOP_AC_NEXP_OFFS__W 8 -#define OFDM_CP_TOP_AC_NEXP_OFFS__M 0xFF -#define OFDM_CP_TOP_AC_NEXP_OFFS__PRE 0x0 - -#define OFDM_CP_TOP_AC_AVER_POW__A 0x2810041 -#define OFDM_CP_TOP_AC_AVER_POW__W 8 -#define OFDM_CP_TOP_AC_AVER_POW__M 0xFF -#define OFDM_CP_TOP_AC_AVER_POW__PRE 0x5F - -#define OFDM_CP_TOP_AC_MAX_POW__A 0x2810042 -#define OFDM_CP_TOP_AC_MAX_POW__W 8 -#define OFDM_CP_TOP_AC_MAX_POW__M 0xFF -#define OFDM_CP_TOP_AC_MAX_POW__PRE 0x7A - -#define OFDM_CP_TOP_AC_WEIGHT_MAN__A 0x2810043 -#define OFDM_CP_TOP_AC_WEIGHT_MAN__W 6 -#define OFDM_CP_TOP_AC_WEIGHT_MAN__M 0x3F -#define OFDM_CP_TOP_AC_WEIGHT_MAN__PRE 0x31 - -#define OFDM_CP_TOP_AC_WEIGHT_EXP__A 0x2810044 -#define OFDM_CP_TOP_AC_WEIGHT_EXP__W 5 -#define OFDM_CP_TOP_AC_WEIGHT_EXP__M 0x1F -#define OFDM_CP_TOP_AC_WEIGHT_EXP__PRE 0x10 - -#define OFDM_CP_TOP_AC_GAIN_MAN__A 0x2810045 -#define OFDM_CP_TOP_AC_GAIN_MAN__W 16 -#define OFDM_CP_TOP_AC_GAIN_MAN__M 0xFFFF -#define OFDM_CP_TOP_AC_GAIN_MAN__PRE 0x0 - -#define OFDM_CP_TOP_AC_GAIN_EXP__A 0x2810046 -#define OFDM_CP_TOP_AC_GAIN_EXP__W 5 -#define OFDM_CP_TOP_AC_GAIN_EXP__M 0x1F -#define OFDM_CP_TOP_AC_GAIN_EXP__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_MODE__A 0x2810047 -#define OFDM_CP_TOP_AC_AMP_MODE__W 2 -#define OFDM_CP_TOP_AC_AMP_MODE__M 0x3 -#define OFDM_CP_TOP_AC_AMP_MODE__PRE 0x2 -#define OFDM_CP_TOP_AC_AMP_MODE_NEW 0x0 -#define OFDM_CP_TOP_AC_AMP_MODE_OLD 0x1 -#define OFDM_CP_TOP_AC_AMP_MODE_FIXED 0x2 - -#define OFDM_CP_TOP_AC_AMP_FIX__A 0x2810048 -#define OFDM_CP_TOP_AC_AMP_FIX__W 14 -#define OFDM_CP_TOP_AC_AMP_FIX__M 0x3FFF -#define OFDM_CP_TOP_AC_AMP_FIX__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_FIX_MAN__B 0 -#define OFDM_CP_TOP_AC_AMP_FIX_MAN__W 10 -#define OFDM_CP_TOP_AC_AMP_FIX_MAN__M 0x3FF -#define OFDM_CP_TOP_AC_AMP_FIX_MAN__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_FIX_EXP__B 10 -#define OFDM_CP_TOP_AC_AMP_FIX_EXP__W 4 -#define OFDM_CP_TOP_AC_AMP_FIX_EXP__M 0x3C00 -#define OFDM_CP_TOP_AC_AMP_FIX_EXP__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_READ__A 0x2810049 -#define OFDM_CP_TOP_AC_AMP_READ__W 14 -#define OFDM_CP_TOP_AC_AMP_READ__M 0x3FFF -#define OFDM_CP_TOP_AC_AMP_READ__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_READ_MAN__B 0 -#define OFDM_CP_TOP_AC_AMP_READ_MAN__W 10 -#define OFDM_CP_TOP_AC_AMP_READ_MAN__M 0x3FF -#define OFDM_CP_TOP_AC_AMP_READ_MAN__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_READ_EXP__B 10 -#define OFDM_CP_TOP_AC_AMP_READ_EXP__W 4 -#define OFDM_CP_TOP_AC_AMP_READ_EXP__M 0x3C00 -#define OFDM_CP_TOP_AC_AMP_READ_EXP__PRE 0x0 - - -#define OFDM_CP_TOP_AC_ANG_MODE__A 0x281004A -#define OFDM_CP_TOP_AC_ANG_MODE__W 2 -#define OFDM_CP_TOP_AC_ANG_MODE__M 0x3 -#define OFDM_CP_TOP_AC_ANG_MODE__PRE 0x3 -#define OFDM_CP_TOP_AC_ANG_MODE_NEW 0x0 -#define OFDM_CP_TOP_AC_ANG_MODE_OLD 0x1 -#define OFDM_CP_TOP_AC_ANG_MODE_NO_INT 0x2 -#define OFDM_CP_TOP_AC_ANG_MODE_OFFSET 0x3 - - -#define OFDM_CP_TOP_AC_ANG_OFFS__A 0x281004B -#define OFDM_CP_TOP_AC_ANG_OFFS__W 16 -#define OFDM_CP_TOP_AC_ANG_OFFS__M 0xFFFF -#define OFDM_CP_TOP_AC_ANG_OFFS__PRE 0x0 - -#define OFDM_CP_TOP_AC_ANG_READ__A 0x281004C -#define OFDM_CP_TOP_AC_ANG_READ__W 16 -#define OFDM_CP_TOP_AC_ANG_READ__M 0xFFFF -#define OFDM_CP_TOP_AC_ANG_READ__PRE 0x0 - -#define OFDM_CP_TOP_AC_ACCU_REAL0__A 0x2810060 -#define OFDM_CP_TOP_AC_ACCU_REAL0__W 8 -#define OFDM_CP_TOP_AC_ACCU_REAL0__M 0xFF -#define OFDM_CP_TOP_AC_ACCU_REAL0__PRE 0x0 - -#define OFDM_CP_TOP_AC_ACCU_IMAG0__A 0x2810061 -#define OFDM_CP_TOP_AC_ACCU_IMAG0__W 8 -#define OFDM_CP_TOP_AC_ACCU_IMAG0__M 0xFF -#define OFDM_CP_TOP_AC_ACCU_IMAG0__PRE 0x0 - -#define OFDM_CP_TOP_AC_ACCU_REAL1__A 0x2810062 -#define OFDM_CP_TOP_AC_ACCU_REAL1__W 8 -#define OFDM_CP_TOP_AC_ACCU_REAL1__M 0xFF -#define OFDM_CP_TOP_AC_ACCU_REAL1__PRE 0x0 - -#define OFDM_CP_TOP_AC_ACCU_IMAG1__A 0x2810063 -#define OFDM_CP_TOP_AC_ACCU_IMAG1__W 8 -#define OFDM_CP_TOP_AC_ACCU_IMAG1__M 0xFF -#define OFDM_CP_TOP_AC_ACCU_IMAG1__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_WR_ADDR__A 0x2810050 -#define OFDM_CP_TOP_DL_MB_WR_ADDR__W 15 -#define OFDM_CP_TOP_DL_MB_WR_ADDR__M 0x7FFF -#define OFDM_CP_TOP_DL_MB_WR_ADDR__PRE 0x0 -#define OFDM_CP_TOP_DL_MB_WR_CTR__A 0x2810051 -#define OFDM_CP_TOP_DL_MB_WR_CTR__W 5 -#define OFDM_CP_TOP_DL_MB_WR_CTR__M 0x1F -#define OFDM_CP_TOP_DL_MB_WR_CTR__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__B 2 -#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__W 3 -#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__M 0x1C -#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__B 1 -#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__W 1 -#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__M 0x2 -#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__B 0 -#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__W 1 -#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__M 0x1 -#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__PRE 0x0 - - -#define OFDM_CP_TOP_DL_MB_RD_ADDR__A 0x2810052 -#define OFDM_CP_TOP_DL_MB_RD_ADDR__W 15 -#define OFDM_CP_TOP_DL_MB_RD_ADDR__M 0x7FFF -#define OFDM_CP_TOP_DL_MB_RD_ADDR__PRE 0x0 -#define OFDM_CP_TOP_DL_MB_RD_CTR__A 0x2810053 -#define OFDM_CP_TOP_DL_MB_RD_CTR__W 11 -#define OFDM_CP_TOP_DL_MB_RD_CTR__M 0x7FF -#define OFDM_CP_TOP_DL_MB_RD_CTR__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__B 10 -#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__W 1 -#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__M 0x400 -#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__B 8 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__W 2 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__M 0x300 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__B 5 -#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__W 3 -#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__M 0xE0 -#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__B 2 -#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__W 3 -#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__M 0x1C -#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__B 1 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__W 1 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__M 0x2 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__B 0 -#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__W 1 -#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__M 0x1 -#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__PRE 0x0 - - - -#define OFDM_CP_BR_BUF_CPL_RAM__A 0x2820000 - - - -#define OFDM_CP_BR_BUF_DAT_RAM__A 0x2830000 - - - -#define OFDM_CP_DL_0_RAM__A 0x2840000 - - - -#define OFDM_CP_DL_1_RAM__A 0x2850000 - - - -#define OFDM_CP_DL_2_RAM__A 0x2860000 - - - - - -#define OFDM_EC_COMM_EXEC__A 0x3400000 -#define OFDM_EC_COMM_EXEC__W 3 -#define OFDM_EC_COMM_EXEC__M 0x7 -#define OFDM_EC_COMM_EXEC__PRE 0x0 -#define OFDM_EC_COMM_EXEC_STOP 0x0 -#define OFDM_EC_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EC_COMM_EXEC_HOLD 0x2 -#define OFDM_EC_COMM_EXEC_STEP 0x3 -#define OFDM_EC_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_EC_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_EC_COMM_STATE__A 0x3400001 -#define OFDM_EC_COMM_STATE__W 16 -#define OFDM_EC_COMM_STATE__M 0xFFFF -#define OFDM_EC_COMM_STATE__PRE 0x0 -#define OFDM_EC_COMM_MB__A 0x3400002 -#define OFDM_EC_COMM_MB__W 16 -#define OFDM_EC_COMM_MB__M 0xFFFF -#define OFDM_EC_COMM_MB__PRE 0x0 -#define OFDM_EC_COMM_INT_REQ__A 0x3400004 -#define OFDM_EC_COMM_INT_REQ__W 16 -#define OFDM_EC_COMM_INT_REQ__M 0xFFFF -#define OFDM_EC_COMM_INT_REQ__PRE 0x0 -#define OFDM_EC_COMM_INT_REQ_VD_REQ__B 4 -#define OFDM_EC_COMM_INT_REQ_VD_REQ__W 1 -#define OFDM_EC_COMM_INT_REQ_VD_REQ__M 0x10 -#define OFDM_EC_COMM_INT_REQ_VD_REQ__PRE 0x0 -#define OFDM_EC_COMM_INT_REQ_SY_REQ__B 5 -#define OFDM_EC_COMM_INT_REQ_SY_REQ__W 1 -#define OFDM_EC_COMM_INT_REQ_SY_REQ__M 0x20 -#define OFDM_EC_COMM_INT_REQ_SY_REQ__PRE 0x0 - -#define OFDM_EC_COMM_INT_STA__A 0x3400005 -#define OFDM_EC_COMM_INT_STA__W 16 -#define OFDM_EC_COMM_INT_STA__M 0xFFFF -#define OFDM_EC_COMM_INT_STA__PRE 0x0 -#define OFDM_EC_COMM_INT_MSK__A 0x3400006 -#define OFDM_EC_COMM_INT_MSK__W 16 -#define OFDM_EC_COMM_INT_MSK__M 0xFFFF -#define OFDM_EC_COMM_INT_MSK__PRE 0x0 -#define OFDM_EC_COMM_INT_STM__A 0x3400007 -#define OFDM_EC_COMM_INT_STM__W 16 -#define OFDM_EC_COMM_INT_STM__M 0xFFFF -#define OFDM_EC_COMM_INT_STM__PRE 0x0 -#define OFDM_EC_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_EC_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_EC_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_EC_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_EC_SB_COMM_EXEC__A 0x3410000 -#define OFDM_EC_SB_COMM_EXEC__W 3 -#define OFDM_EC_SB_COMM_EXEC__M 0x7 -#define OFDM_EC_SB_COMM_EXEC__PRE 0x0 -#define OFDM_EC_SB_COMM_EXEC_STOP 0x0 -#define OFDM_EC_SB_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EC_SB_COMM_EXEC_HOLD 0x2 -#define OFDM_EC_SB_COMM_EXEC_STEP 0x3 - -#define OFDM_EC_SB_COMM_STATE__A 0x3410001 -#define OFDM_EC_SB_COMM_STATE__W 4 -#define OFDM_EC_SB_COMM_STATE__M 0xF -#define OFDM_EC_SB_COMM_STATE__PRE 0x0 -#define OFDM_EC_SB_COMM_MB__A 0x3410002 -#define OFDM_EC_SB_COMM_MB__W 2 -#define OFDM_EC_SB_COMM_MB__M 0x3 -#define OFDM_EC_SB_COMM_MB__PRE 0x0 -#define OFDM_EC_SB_COMM_MB_CTL__B 0 -#define OFDM_EC_SB_COMM_MB_CTL__W 1 -#define OFDM_EC_SB_COMM_MB_CTL__M 0x1 -#define OFDM_EC_SB_COMM_MB_CTL__PRE 0x0 -#define OFDM_EC_SB_COMM_MB_CTL_OFF 0x0 -#define OFDM_EC_SB_COMM_MB_CTL_ON 0x1 -#define OFDM_EC_SB_COMM_MB_OBS__B 1 -#define OFDM_EC_SB_COMM_MB_OBS__W 1 -#define OFDM_EC_SB_COMM_MB_OBS__M 0x2 -#define OFDM_EC_SB_COMM_MB_OBS__PRE 0x0 -#define OFDM_EC_SB_COMM_MB_OBS_OFF 0x0 -#define OFDM_EC_SB_COMM_MB_OBS_ON 0x2 - - -#define OFDM_EC_SB_TR_MODE__A 0x3410010 -#define OFDM_EC_SB_TR_MODE__W 1 -#define OFDM_EC_SB_TR_MODE__M 0x1 -#define OFDM_EC_SB_TR_MODE__PRE 0x0 -#define OFDM_EC_SB_TR_MODE_8K 0x0 -#define OFDM_EC_SB_TR_MODE_2K 0x1 - - -#define OFDM_EC_SB_CONST__A 0x3410011 -#define OFDM_EC_SB_CONST__W 2 -#define OFDM_EC_SB_CONST__M 0x3 -#define OFDM_EC_SB_CONST__PRE 0x2 -#define OFDM_EC_SB_CONST_QPSK 0x0 -#define OFDM_EC_SB_CONST_16QAM 0x1 -#define OFDM_EC_SB_CONST_64QAM 0x2 - - -#define OFDM_EC_SB_ALPHA__A 0x3410012 -#define OFDM_EC_SB_ALPHA__W 3 -#define OFDM_EC_SB_ALPHA__M 0x7 -#define OFDM_EC_SB_ALPHA__PRE 0x0 -#define OFDM_EC_SB_ALPHA_NH 0x0 -#define OFDM_EC_SB_ALPHA_H1 0x1 -#define OFDM_EC_SB_ALPHA_H2 0x2 -#define OFDM_EC_SB_ALPHA_H4 0x3 - - -#define OFDM_EC_SB_PRIOR__A 0x3410013 -#define OFDM_EC_SB_PRIOR__W 1 -#define OFDM_EC_SB_PRIOR__M 0x1 -#define OFDM_EC_SB_PRIOR__PRE 0x0 -#define OFDM_EC_SB_PRIOR_HI 0x0 -#define OFDM_EC_SB_PRIOR_LO 0x1 - - -#define OFDM_EC_SB_CSI_HI__A 0x3410014 -#define OFDM_EC_SB_CSI_HI__W 5 -#define OFDM_EC_SB_CSI_HI__M 0x1F -#define OFDM_EC_SB_CSI_HI__PRE 0x18 -#define OFDM_EC_SB_CSI_HI_MAX 0x1F -#define OFDM_EC_SB_CSI_HI_MIN 0x0 -#define OFDM_EC_SB_CSI_HI_TAG 0x0 - - -#define OFDM_EC_SB_CSI_LO__A 0x3410015 -#define OFDM_EC_SB_CSI_LO__W 5 -#define OFDM_EC_SB_CSI_LO__M 0x1F -#define OFDM_EC_SB_CSI_LO__PRE 0xC -#define OFDM_EC_SB_CSI_LO_MAX 0x1F -#define OFDM_EC_SB_CSI_LO_MIN 0x0 -#define OFDM_EC_SB_CSI_LO_TAG 0x0 - - -#define OFDM_EC_SB_SMB_TGL__A 0x3410016 -#define OFDM_EC_SB_SMB_TGL__W 1 -#define OFDM_EC_SB_SMB_TGL__M 0x1 -#define OFDM_EC_SB_SMB_TGL__PRE 0x1 -#define OFDM_EC_SB_SMB_TGL_OFF 0x0 -#define OFDM_EC_SB_SMB_TGL_ON 0x1 - - -#define OFDM_EC_SB_SNR_HI__A 0x3410017 -#define OFDM_EC_SB_SNR_HI__W 7 -#define OFDM_EC_SB_SNR_HI__M 0x7F -#define OFDM_EC_SB_SNR_HI__PRE 0x7F -#define OFDM_EC_SB_SNR_HI_MAX 0x7F -#define OFDM_EC_SB_SNR_HI_MIN 0x0 -#define OFDM_EC_SB_SNR_HI_TAG 0x0 - - -#define OFDM_EC_SB_SNR_MID__A 0x3410018 -#define OFDM_EC_SB_SNR_MID__W 7 -#define OFDM_EC_SB_SNR_MID__M 0x7F -#define OFDM_EC_SB_SNR_MID__PRE 0x7F -#define OFDM_EC_SB_SNR_MID_MAX 0x7F -#define OFDM_EC_SB_SNR_MID_MIN 0x0 -#define OFDM_EC_SB_SNR_MID_TAG 0x0 - - -#define OFDM_EC_SB_SNR_LO__A 0x3410019 -#define OFDM_EC_SB_SNR_LO__W 7 -#define OFDM_EC_SB_SNR_LO__M 0x7F -#define OFDM_EC_SB_SNR_LO__PRE 0x7F -#define OFDM_EC_SB_SNR_LO_MAX 0x7F -#define OFDM_EC_SB_SNR_LO_MIN 0x0 -#define OFDM_EC_SB_SNR_LO_TAG 0x0 - - -#define OFDM_EC_SB_SCALE_MSB__A 0x341001A -#define OFDM_EC_SB_SCALE_MSB__W 6 -#define OFDM_EC_SB_SCALE_MSB__M 0x3F -#define OFDM_EC_SB_SCALE_MSB__PRE 0x30 -#define OFDM_EC_SB_SCALE_MSB_MAX 0x3F - - -#define OFDM_EC_SB_SCALE_BIT2__A 0x341001B -#define OFDM_EC_SB_SCALE_BIT2__W 6 -#define OFDM_EC_SB_SCALE_BIT2__M 0x3F -#define OFDM_EC_SB_SCALE_BIT2__PRE 0xC -#define OFDM_EC_SB_SCALE_BIT2_MAX 0x3F - - -#define OFDM_EC_SB_SCALE_LSB__A 0x341001C -#define OFDM_EC_SB_SCALE_LSB__W 6 -#define OFDM_EC_SB_SCALE_LSB__M 0x3F -#define OFDM_EC_SB_SCALE_LSB__PRE 0x3 -#define OFDM_EC_SB_SCALE_LSB_MAX 0x3F - - -#define OFDM_EC_SB_CSI_OFS0__A 0x341001D -#define OFDM_EC_SB_CSI_OFS0__W 4 -#define OFDM_EC_SB_CSI_OFS0__M 0xF -#define OFDM_EC_SB_CSI_OFS0__PRE 0x1 - -#define OFDM_EC_SB_CSI_OFS1__A 0x341001E -#define OFDM_EC_SB_CSI_OFS1__W 4 -#define OFDM_EC_SB_CSI_OFS1__M 0xF -#define OFDM_EC_SB_CSI_OFS1__PRE 0x1 - -#define OFDM_EC_SB_CSI_OFS2__A 0x341001F -#define OFDM_EC_SB_CSI_OFS2__W 4 -#define OFDM_EC_SB_CSI_OFS2__M 0xF -#define OFDM_EC_SB_CSI_OFS2__PRE 0x1 - -#define OFDM_EC_SB_MAX0__A 0x3410020 -#define OFDM_EC_SB_MAX0__W 6 -#define OFDM_EC_SB_MAX0__M 0x3F -#define OFDM_EC_SB_MAX0__PRE 0x3F - -#define OFDM_EC_SB_MAX1__A 0x3410021 -#define OFDM_EC_SB_MAX1__W 6 -#define OFDM_EC_SB_MAX1__M 0x3F -#define OFDM_EC_SB_MAX1__PRE 0x3F -#define OFDM_EC_SB_MAX1_INIT 0x3F - - -#define OFDM_EC_SB_MAX2__A 0x3410022 -#define OFDM_EC_SB_MAX2__W 6 -#define OFDM_EC_SB_MAX2__M 0x3F -#define OFDM_EC_SB_MAX2__PRE 0x3F - -#define OFDM_EC_SB_CSI_DIS__A 0x3410023 -#define OFDM_EC_SB_CSI_DIS__W 1 -#define OFDM_EC_SB_CSI_DIS__M 0x1 -#define OFDM_EC_SB_CSI_DIS__PRE 0x0 - - - -#define OFDM_EC_VD_COMM_EXEC__A 0x3420000 -#define OFDM_EC_VD_COMM_EXEC__W 3 -#define OFDM_EC_VD_COMM_EXEC__M 0x7 -#define OFDM_EC_VD_COMM_EXEC__PRE 0x0 -#define OFDM_EC_VD_COMM_EXEC_STOP 0x0 -#define OFDM_EC_VD_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EC_VD_COMM_EXEC_HOLD 0x2 -#define OFDM_EC_VD_COMM_EXEC_STEP 0x3 - -#define OFDM_EC_VD_COMM_STATE__A 0x3420001 -#define OFDM_EC_VD_COMM_STATE__W 4 -#define OFDM_EC_VD_COMM_STATE__M 0xF -#define OFDM_EC_VD_COMM_STATE__PRE 0x0 -#define OFDM_EC_VD_COMM_MB__A 0x3420002 -#define OFDM_EC_VD_COMM_MB__W 2 -#define OFDM_EC_VD_COMM_MB__M 0x3 -#define OFDM_EC_VD_COMM_MB__PRE 0x0 -#define OFDM_EC_VD_COMM_MB_CTL__B 0 -#define OFDM_EC_VD_COMM_MB_CTL__W 1 -#define OFDM_EC_VD_COMM_MB_CTL__M 0x1 -#define OFDM_EC_VD_COMM_MB_CTL__PRE 0x0 -#define OFDM_EC_VD_COMM_MB_CTL_OFF 0x0 -#define OFDM_EC_VD_COMM_MB_CTL_ON 0x1 -#define OFDM_EC_VD_COMM_MB_OBS__B 1 -#define OFDM_EC_VD_COMM_MB_OBS__W 1 -#define OFDM_EC_VD_COMM_MB_OBS__M 0x2 -#define OFDM_EC_VD_COMM_MB_OBS__PRE 0x0 -#define OFDM_EC_VD_COMM_MB_OBS_OFF 0x0 -#define OFDM_EC_VD_COMM_MB_OBS_ON 0x2 - -#define OFDM_EC_VD_COMM_INT_REQ__A 0x3420003 -#define OFDM_EC_VD_COMM_INT_REQ__W 1 -#define OFDM_EC_VD_COMM_INT_REQ__M 0x1 -#define OFDM_EC_VD_COMM_INT_REQ__PRE 0x0 -#define OFDM_EC_VD_COMM_INT_STA__A 0x3420005 -#define OFDM_EC_VD_COMM_INT_STA__W 1 -#define OFDM_EC_VD_COMM_INT_STA__M 0x1 -#define OFDM_EC_VD_COMM_INT_STA__PRE 0x0 -#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__B 0 -#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__W 1 -#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__M 0x1 -#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__PRE 0x0 - -#define OFDM_EC_VD_COMM_INT_MSK__A 0x3420006 -#define OFDM_EC_VD_COMM_INT_MSK__W 1 -#define OFDM_EC_VD_COMM_INT_MSK__M 0x1 -#define OFDM_EC_VD_COMM_INT_MSK__PRE 0x0 -#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__B 0 -#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__W 1 -#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__M 0x1 -#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__PRE 0x0 - -#define OFDM_EC_VD_COMM_INT_STM__A 0x3420007 -#define OFDM_EC_VD_COMM_INT_STM__W 1 -#define OFDM_EC_VD_COMM_INT_STM__M 0x1 -#define OFDM_EC_VD_COMM_INT_STM__PRE 0x0 -#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__B 0 -#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__W 1 -#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__M 0x1 -#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__PRE 0x0 - - -#define OFDM_EC_VD_FORCE__A 0x3420010 -#define OFDM_EC_VD_FORCE__W 2 -#define OFDM_EC_VD_FORCE__M 0x3 -#define OFDM_EC_VD_FORCE__PRE 0x2 -#define OFDM_EC_VD_FORCE_FREE 0x0 -#define OFDM_EC_VD_FORCE_PROP 0x1 -#define OFDM_EC_VD_FORCE_FORCED 0x2 -#define OFDM_EC_VD_FORCE_FIXED 0x3 - - -#define OFDM_EC_VD_SET_CODERATE__A 0x3420011 -#define OFDM_EC_VD_SET_CODERATE__W 3 -#define OFDM_EC_VD_SET_CODERATE__M 0x7 -#define OFDM_EC_VD_SET_CODERATE__PRE 0x1 -#define OFDM_EC_VD_SET_CODERATE_C1_2 0x0 -#define OFDM_EC_VD_SET_CODERATE_C2_3 0x1 -#define OFDM_EC_VD_SET_CODERATE_C3_4 0x2 -#define OFDM_EC_VD_SET_CODERATE_C5_6 0x3 -#define OFDM_EC_VD_SET_CODERATE_C7_8 0x4 - - -#define OFDM_EC_VD_REQ_SMB_CNT__A 0x3420012 -#define OFDM_EC_VD_REQ_SMB_CNT__W 16 -#define OFDM_EC_VD_REQ_SMB_CNT__M 0xFFFF -#define OFDM_EC_VD_REQ_SMB_CNT__PRE 0x1 - -#define OFDM_EC_VD_REQ_BIT_CNT__A 0x3420013 -#define OFDM_EC_VD_REQ_BIT_CNT__W 16 -#define OFDM_EC_VD_REQ_BIT_CNT__M 0xFFFF -#define OFDM_EC_VD_REQ_BIT_CNT__PRE 0xFFF - -#define OFDM_EC_VD_RLK_ENA__A 0x3420014 -#define OFDM_EC_VD_RLK_ENA__W 1 -#define OFDM_EC_VD_RLK_ENA__M 0x1 -#define OFDM_EC_VD_RLK_ENA__PRE 0x1 -#define OFDM_EC_VD_RLK_ENA_OFF 0x0 -#define OFDM_EC_VD_RLK_ENA_ON 0x1 - - -#define OFDM_EC_VD_VAL__A 0x3420015 -#define OFDM_EC_VD_VAL__W 2 -#define OFDM_EC_VD_VAL__M 0x3 -#define OFDM_EC_VD_VAL__PRE 0x0 -#define OFDM_EC_VD_VAL_CODE 0x1 -#define OFDM_EC_VD_VAL_CNT 0x2 - - -#define OFDM_EC_VD_GET_CODERATE__A 0x3420016 -#define OFDM_EC_VD_GET_CODERATE__W 3 -#define OFDM_EC_VD_GET_CODERATE__M 0x7 -#define OFDM_EC_VD_GET_CODERATE__PRE 0x0 -#define OFDM_EC_VD_GET_CODERATE_C1_2 0x0 -#define OFDM_EC_VD_GET_CODERATE_C2_3 0x1 -#define OFDM_EC_VD_GET_CODERATE_C3_4 0x2 -#define OFDM_EC_VD_GET_CODERATE_C5_6 0x3 -#define OFDM_EC_VD_GET_CODERATE_C7_8 0x4 - - -#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 -#define OFDM_EC_VD_ERR_BIT_CNT__W 16 -#define OFDM_EC_VD_ERR_BIT_CNT__M 0xFFFF -#define OFDM_EC_VD_ERR_BIT_CNT__PRE 0xFFFF - -#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 -#define OFDM_EC_VD_IN_BIT_CNT__W 16 -#define OFDM_EC_VD_IN_BIT_CNT__M 0xFFFF -#define OFDM_EC_VD_IN_BIT_CNT__PRE 0x0 - -#define OFDM_EC_VD_STS__A 0x3420019 -#define OFDM_EC_VD_STS__W 1 -#define OFDM_EC_VD_STS__M 0x1 -#define OFDM_EC_VD_STS__PRE 0x0 -#define OFDM_EC_VD_STS_NO_LOCK 0x0 -#define OFDM_EC_VD_STS_IN_LOCK 0x1 - - -#define OFDM_EC_VD_RLK_CNT__A 0x342001A -#define OFDM_EC_VD_RLK_CNT__W 16 -#define OFDM_EC_VD_RLK_CNT__M 0xFFFF -#define OFDM_EC_VD_RLK_CNT__PRE 0x0 - - - -#define OFDM_EC_SY_COMM_EXEC__A 0x3430000 -#define OFDM_EC_SY_COMM_EXEC__W 2 -#define OFDM_EC_SY_COMM_EXEC__M 0x3 -#define OFDM_EC_SY_COMM_EXEC__PRE 0x0 -#define OFDM_EC_SY_COMM_EXEC_STOP 0x0 -#define OFDM_EC_SY_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EC_SY_COMM_EXEC_HOLD 0x2 -#define OFDM_EC_SY_COMM_EXEC_STEP 0x3 - -#define OFDM_EC_SY_COMM_MB__A 0x3430002 -#define OFDM_EC_SY_COMM_MB__W 2 -#define OFDM_EC_SY_COMM_MB__M 0x3 -#define OFDM_EC_SY_COMM_MB__PRE 0x0 -#define OFDM_EC_SY_COMM_MB_CTL__B 0 -#define OFDM_EC_SY_COMM_MB_CTL__W 1 -#define OFDM_EC_SY_COMM_MB_CTL__M 0x1 -#define OFDM_EC_SY_COMM_MB_CTL__PRE 0x0 -#define OFDM_EC_SY_COMM_MB_CTL_OFF 0x0 -#define OFDM_EC_SY_COMM_MB_CTL_ON 0x1 -#define OFDM_EC_SY_COMM_MB_OBS__B 1 -#define OFDM_EC_SY_COMM_MB_OBS__W 1 -#define OFDM_EC_SY_COMM_MB_OBS__M 0x2 -#define OFDM_EC_SY_COMM_MB_OBS__PRE 0x0 -#define OFDM_EC_SY_COMM_MB_OBS_OFF 0x0 -#define OFDM_EC_SY_COMM_MB_OBS_ON 0x2 - -#define OFDM_EC_SY_COMM_INT_REQ__A 0x3430003 -#define OFDM_EC_SY_COMM_INT_REQ__W 1 -#define OFDM_EC_SY_COMM_INT_REQ__M 0x1 -#define OFDM_EC_SY_COMM_INT_REQ__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_STA__A 0x3430005 -#define OFDM_EC_SY_COMM_INT_STA__W 3 -#define OFDM_EC_SY_COMM_INT_STA__M 0x7 -#define OFDM_EC_SY_COMM_INT_STA__PRE 0x0 - -#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__B 0 -#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__W 1 -#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__M 0x1 -#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 - -#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__B 1 -#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__W 1 -#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 -#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 - -#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__B 2 -#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__W 1 -#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 -#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 - -#define OFDM_EC_SY_COMM_INT_MSK__A 0x3430006 -#define OFDM_EC_SY_COMM_INT_MSK__W 3 -#define OFDM_EC_SY_COMM_INT_MSK__M 0x7 -#define OFDM_EC_SY_COMM_INT_MSK__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__B 0 -#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 -#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 -#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 -#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 -#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 -#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 - -#define OFDM_EC_SY_COMM_INT_STM__A 0x3430007 -#define OFDM_EC_SY_COMM_INT_STM__W 3 -#define OFDM_EC_SY_COMM_INT_STM__M 0x7 -#define OFDM_EC_SY_COMM_INT_STM__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__B 0 -#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__M 0x1 -#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__B 1 -#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 -#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 -#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 -#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 - -#define OFDM_EC_SY_STATUS__A 0x3430010 -#define OFDM_EC_SY_STATUS__W 2 -#define OFDM_EC_SY_STATUS__M 0x3 -#define OFDM_EC_SY_STATUS__PRE 0x0 -#define OFDM_EC_SY_STATUS_SYNC_STATE__B 0 -#define OFDM_EC_SY_STATUS_SYNC_STATE__W 2 -#define OFDM_EC_SY_STATUS_SYNC_STATE__M 0x3 -#define OFDM_EC_SY_STATUS_SYNC_STATE__PRE 0x0 -#define OFDM_EC_SY_STATUS_SYNC_STATE_HUNTING 0x0 -#define OFDM_EC_SY_STATUS_SYNC_STATE_TRYING 0x1 -#define OFDM_EC_SY_STATUS_SYNC_STATE_IN_SYNC 0x2 - - -#define OFDM_EC_SY_TIMEOUT__A 0x3430011 -#define OFDM_EC_SY_TIMEOUT__W 16 -#define OFDM_EC_SY_TIMEOUT__M 0xFFFF -#define OFDM_EC_SY_TIMEOUT__PRE 0x3A98 - -#define OFDM_EC_SY_SYNC_LWM__A 0x3430012 -#define OFDM_EC_SY_SYNC_LWM__W 4 -#define OFDM_EC_SY_SYNC_LWM__M 0xF -#define OFDM_EC_SY_SYNC_LWM__PRE 0x2 - -#define OFDM_EC_SY_SYNC_AWM__A 0x3430013 -#define OFDM_EC_SY_SYNC_AWM__W 4 -#define OFDM_EC_SY_SYNC_AWM__M 0xF -#define OFDM_EC_SY_SYNC_AWM__PRE 0x3 - -#define OFDM_EC_SY_SYNC_HWM__A 0x3430014 -#define OFDM_EC_SY_SYNC_HWM__W 4 -#define OFDM_EC_SY_SYNC_HWM__M 0xF -#define OFDM_EC_SY_SYNC_HWM__PRE 0x5 - -#define OFDM_EC_SY_UNLOCK__A 0x3430015 -#define OFDM_EC_SY_UNLOCK__W 1 -#define OFDM_EC_SY_UNLOCK__M 0x1 -#define OFDM_EC_SY_UNLOCK__PRE 0x0 - - - -#define OFDM_EC_SB_BD0_RAM__A 0x3440000 - - - -#define OFDM_EC_SB_BD1_RAM__A 0x3450000 - - - -#define OFDM_EC_SB_SD_RAM__A 0x3460000 - - - -#define OFDM_EC_VD_RE_RAM__A 0x3470000 - - - -#define OFDM_EC_VD_TB0_RAM__A 0x3480000 - - - -#define OFDM_EC_VD_TB1_RAM__A 0x3490000 - - - -#define OFDM_EC_VD_TB2_RAM__A 0x34A0000 - - - -#define OFDM_EC_VD_TB3_RAM__A 0x34B0000 - - - - - -#define OFDM_EQ_COMM_EXEC__A 0x3000000 -#define OFDM_EQ_COMM_EXEC__W 3 -#define OFDM_EQ_COMM_EXEC__M 0x7 -#define OFDM_EQ_COMM_EXEC__PRE 0x0 -#define OFDM_EQ_COMM_EXEC_STOP 0x0 -#define OFDM_EQ_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EQ_COMM_EXEC_HOLD 0x2 -#define OFDM_EQ_COMM_EXEC_STEP 0x3 -#define OFDM_EQ_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_EQ_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_EQ_COMM_STATE__A 0x3000001 -#define OFDM_EQ_COMM_STATE__W 16 -#define OFDM_EQ_COMM_STATE__M 0xFFFF -#define OFDM_EQ_COMM_STATE__PRE 0x0 -#define OFDM_EQ_COMM_MB__A 0x3000002 -#define OFDM_EQ_COMM_MB__W 16 -#define OFDM_EQ_COMM_MB__M 0xFFFF -#define OFDM_EQ_COMM_MB__PRE 0x0 -#define OFDM_EQ_COMM_INT_REQ__A 0x3000004 -#define OFDM_EQ_COMM_INT_REQ__W 16 -#define OFDM_EQ_COMM_INT_REQ__M 0xFFFF -#define OFDM_EQ_COMM_INT_REQ__PRE 0x0 -#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__B 3 -#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__W 1 -#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__M 0x8 -#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__PRE 0x0 - -#define OFDM_EQ_COMM_INT_STA__A 0x3000005 -#define OFDM_EQ_COMM_INT_STA__W 16 -#define OFDM_EQ_COMM_INT_STA__M 0xFFFF -#define OFDM_EQ_COMM_INT_STA__PRE 0x0 -#define OFDM_EQ_COMM_INT_MSK__A 0x3000006 -#define OFDM_EQ_COMM_INT_MSK__W 16 -#define OFDM_EQ_COMM_INT_MSK__M 0xFFFF -#define OFDM_EQ_COMM_INT_MSK__PRE 0x0 -#define OFDM_EQ_COMM_INT_STM__A 0x3000007 -#define OFDM_EQ_COMM_INT_STM__W 16 -#define OFDM_EQ_COMM_INT_STM__M 0xFFFF -#define OFDM_EQ_COMM_INT_STM__PRE 0x0 -#define OFDM_EQ_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_EQ_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_EQ_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_EQ_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_EQ_TOP_COMM_EXEC__A 0x3010000 -#define OFDM_EQ_TOP_COMM_EXEC__W 3 -#define OFDM_EQ_TOP_COMM_EXEC__M 0x7 -#define OFDM_EQ_TOP_COMM_EXEC__PRE 0x0 -#define OFDM_EQ_TOP_COMM_EXEC_STOP 0x0 -#define OFDM_EQ_TOP_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EQ_TOP_COMM_EXEC_HOLD 0x2 -#define OFDM_EQ_TOP_COMM_EXEC_STEP 0x3 - -#define OFDM_EQ_TOP_COMM_STATE__A 0x3010001 -#define OFDM_EQ_TOP_COMM_STATE__W 4 -#define OFDM_EQ_TOP_COMM_STATE__M 0xF -#define OFDM_EQ_TOP_COMM_STATE__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB__A 0x3010002 -#define OFDM_EQ_TOP_COMM_MB__W 6 -#define OFDM_EQ_TOP_COMM_MB__M 0x3F -#define OFDM_EQ_TOP_COMM_MB__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB_CTL__B 0 -#define OFDM_EQ_TOP_COMM_MB_CTL__W 1 -#define OFDM_EQ_TOP_COMM_MB_CTL__M 0x1 -#define OFDM_EQ_TOP_COMM_MB_CTL__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB_CTL_OFF 0x0 -#define OFDM_EQ_TOP_COMM_MB_CTL_ON 0x1 -#define OFDM_EQ_TOP_COMM_MB_OBS__B 1 -#define OFDM_EQ_TOP_COMM_MB_OBS__W 1 -#define OFDM_EQ_TOP_COMM_MB_OBS__M 0x2 -#define OFDM_EQ_TOP_COMM_MB_OBS__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB_OBS_OFF 0x0 -#define OFDM_EQ_TOP_COMM_MB_OBS_ON 0x2 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__B 2 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__W 2 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__M 0xC -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_OT 0x0 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_RC 0x4 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_IS 0x8 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__B 4 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__W 2 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__M 0x30 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_OT 0x0 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_RC 0x10 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_IS 0x20 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_SN 0x30 - -#define OFDM_EQ_TOP_COMM_INT_REQ__A 0x3010004 -#define OFDM_EQ_TOP_COMM_INT_REQ__W 1 -#define OFDM_EQ_TOP_COMM_INT_REQ__M 0x1 -#define OFDM_EQ_TOP_COMM_INT_REQ__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_STA__A 0x3010005 -#define OFDM_EQ_TOP_COMM_INT_STA__W 2 -#define OFDM_EQ_TOP_COMM_INT_STA__M 0x3 -#define OFDM_EQ_TOP_COMM_INT_STA__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__B 0 -#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__M 0x1 -#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__B 1 -#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__M 0x2 -#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__PRE 0x0 - -#define OFDM_EQ_TOP_COMM_INT_MSK__A 0x3010006 -#define OFDM_EQ_TOP_COMM_INT_MSK__W 2 -#define OFDM_EQ_TOP_COMM_INT_MSK__M 0x3 -#define OFDM_EQ_TOP_COMM_INT_MSK__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__B 0 -#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__M 0x1 -#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__B 1 -#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__M 0x2 -#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__PRE 0x0 - -#define OFDM_EQ_TOP_COMM_INT_STM__A 0x3010007 -#define OFDM_EQ_TOP_COMM_INT_STM__W 2 -#define OFDM_EQ_TOP_COMM_INT_STM__M 0x3 -#define OFDM_EQ_TOP_COMM_INT_STM__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__B 0 -#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__M 0x1 -#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__B 1 -#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__M 0x2 -#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__PRE 0x0 - -#define OFDM_EQ_TOP_IS_MODE__A 0x3010014 -#define OFDM_EQ_TOP_IS_MODE__W 4 -#define OFDM_EQ_TOP_IS_MODE__M 0xF -#define OFDM_EQ_TOP_IS_MODE__PRE 0x0 - -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__B 0 -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__W 1 -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__M 0x1 -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__PRE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_MAX 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_ZER 0x1 - -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__B 1 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__W 1 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__M 0x2 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__PRE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_ONE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_TWO 0x2 - -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__B 2 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__W 1 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__M 0x4 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__PRE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_ENABLE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_DISABLE 0x4 - -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__B 3 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__W 1 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__M 0x8 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__PRE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_ENABLE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_DISABLE 0x8 - - -#define OFDM_EQ_TOP_IS_GAIN_MAN__A 0x3010015 -#define OFDM_EQ_TOP_IS_GAIN_MAN__W 10 -#define OFDM_EQ_TOP_IS_GAIN_MAN__M 0x3FF -#define OFDM_EQ_TOP_IS_GAIN_MAN__PRE 0x114 - -#define OFDM_EQ_TOP_IS_GAIN_EXP__A 0x3010016 -#define OFDM_EQ_TOP_IS_GAIN_EXP__W 5 -#define OFDM_EQ_TOP_IS_GAIN_EXP__M 0x1F -#define OFDM_EQ_TOP_IS_GAIN_EXP__PRE 0x5 - -#define OFDM_EQ_TOP_IS_CLIP_EXP__A 0x3010017 -#define OFDM_EQ_TOP_IS_CLIP_EXP__W 5 -#define OFDM_EQ_TOP_IS_CLIP_EXP__M 0x1F -#define OFDM_EQ_TOP_IS_CLIP_EXP__PRE 0x10 -#define OFDM_EQ_TOP_DV_MODE__A 0x301001E -#define OFDM_EQ_TOP_DV_MODE__W 4 -#define OFDM_EQ_TOP_DV_MODE__M 0xF -#define OFDM_EQ_TOP_DV_MODE__PRE 0xF - -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__B 0 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__W 1 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__M 0x1 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__PRE 0x1 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_DIS 0x0 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_ENA 0x1 - -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__B 1 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__W 1 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__M 0x2 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__PRE 0x2 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_DIS 0x0 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_ENA 0x2 - -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__B 2 -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__W 1 -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__M 0x4 -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__PRE 0x4 -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_DIS 0x0 -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_ENA 0x4 - -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__B 3 -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__W 1 -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__M 0x8 -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__PRE 0x8 -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_DIS 0x0 -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_ENA 0x8 - - -#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__A 0x301001F -#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__W 16 -#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__M 0xFFFF -#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE__A 0x3010028 -#define OFDM_EQ_TOP_SN_MODE__W 8 -#define OFDM_EQ_TOP_SN_MODE__M 0xFF -#define OFDM_EQ_TOP_SN_MODE__PRE 0x18 - -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__B 0 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__M 0x1 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_ENABLE 0x1 - -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__B 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__M 0x2 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_ENABLE 0x2 - -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__B 2 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__M 0x4 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_ENABLE 0x4 - -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__B 3 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__M 0x8 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__PRE 0x8 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_ENABLE 0x8 - -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__B 4 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__M 0x10 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__PRE 0x10 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_ENABLE 0x10 - -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__B 5 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__M 0x20 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_ENABLE 0x20 - -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__B 6 -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__W 1 -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__M 0x40 -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_DYNAMIC 0x0 -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_STATIC 0x40 - -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__B 7 -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__W 1 -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__M 0x80 -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_DYNAMIC 0x0 -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_STATIC 0x80 - - -#define OFDM_EQ_TOP_SN_PFIX__A 0x3010029 -#define OFDM_EQ_TOP_SN_PFIX__W 8 -#define OFDM_EQ_TOP_SN_PFIX__M 0xFF -#define OFDM_EQ_TOP_SN_PFIX__PRE 0x0 - -#define OFDM_EQ_TOP_SN_CEGAIN__A 0x301002A -#define OFDM_EQ_TOP_SN_CEGAIN__W 8 -#define OFDM_EQ_TOP_SN_CEGAIN__M 0xFF -#define OFDM_EQ_TOP_SN_CEGAIN__PRE 0x30 - -#define OFDM_EQ_TOP_SN_OFFSET__A 0x301002B -#define OFDM_EQ_TOP_SN_OFFSET__W 6 -#define OFDM_EQ_TOP_SN_OFFSET__M 0x3F -#define OFDM_EQ_TOP_SN_OFFSET__PRE 0x39 - -#define OFDM_EQ_TOP_SN_NULLIFY__A 0x301002C -#define OFDM_EQ_TOP_SN_NULLIFY__W 6 -#define OFDM_EQ_TOP_SN_NULLIFY__M 0x3F -#define OFDM_EQ_TOP_SN_NULLIFY__PRE 0x0 -#define OFDM_EQ_TOP_SN_SQUASH__A 0x301002D -#define OFDM_EQ_TOP_SN_SQUASH__W 10 -#define OFDM_EQ_TOP_SN_SQUASH__M 0x3FF -#define OFDM_EQ_TOP_SN_SQUASH__PRE 0x7 - -#define OFDM_EQ_TOP_SN_SQUASH_MAN__B 0 -#define OFDM_EQ_TOP_SN_SQUASH_MAN__W 6 -#define OFDM_EQ_TOP_SN_SQUASH_MAN__M 0x3F -#define OFDM_EQ_TOP_SN_SQUASH_MAN__PRE 0x7 - -#define OFDM_EQ_TOP_SN_SQUASH_EXP__B 6 -#define OFDM_EQ_TOP_SN_SQUASH_EXP__W 4 -#define OFDM_EQ_TOP_SN_SQUASH_EXP__M 0x3C0 -#define OFDM_EQ_TOP_SN_SQUASH_EXP__PRE 0x0 - -#define OFDM_EQ_TOP_RC_SEL_CAR__A 0x3010032 -#define OFDM_EQ_TOP_RC_SEL_CAR__W 8 -#define OFDM_EQ_TOP_RC_SEL_CAR__M 0xFF -#define OFDM_EQ_TOP_RC_SEL_CAR__PRE 0x2 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__B 0 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__W 1 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__M 0x1 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__PRE 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_OFF 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_ON 0x1 - -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__B 1 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__W 2 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__M 0x6 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__PRE 0x2 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_A_CC 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_B_CE 0x2 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_C_DRI 0x4 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_D_CC 0x6 - -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__B 3 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__W 2 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__M 0x18 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__PRE 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_A_CC 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_B_CE 0x8 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_C_DRI 0x10 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_D_CC 0x18 - -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__B 5 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__W 2 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__M 0x60 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__PRE 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_A_CC 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_B_CE 0x20 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_C_DRI 0x40 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_D_CC 0x60 - -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__B 7 -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__W 1 -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__M 0x80 -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__PRE 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_2K 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_8K 0x80 - -#define OFDM_EQ_TOP_RC_STS__A 0x3010033 -#define OFDM_EQ_TOP_RC_STS__W 16 -#define OFDM_EQ_TOP_RC_STS__M 0xFFFF -#define OFDM_EQ_TOP_RC_STS__PRE 0x0 - -#define OFDM_EQ_TOP_RC_STS_DIFF__B 0 -#define OFDM_EQ_TOP_RC_STS_DIFF__W 11 -#define OFDM_EQ_TOP_RC_STS_DIFF__M 0x7FF -#define OFDM_EQ_TOP_RC_STS_DIFF__PRE 0x0 - -#define OFDM_EQ_TOP_RC_STS_FIRST__B 11 -#define OFDM_EQ_TOP_RC_STS_FIRST__W 1 -#define OFDM_EQ_TOP_RC_STS_FIRST__M 0x800 -#define OFDM_EQ_TOP_RC_STS_FIRST__PRE 0x0 -#define OFDM_EQ_TOP_RC_STS_FIRST_A_CE 0x0 -#define OFDM_EQ_TOP_RC_STS_FIRST_B_DRI 0x800 - -#define OFDM_EQ_TOP_RC_STS_SELEC__B 12 -#define OFDM_EQ_TOP_RC_STS_SELEC__W 1 -#define OFDM_EQ_TOP_RC_STS_SELEC__M 0x1000 -#define OFDM_EQ_TOP_RC_STS_SELEC__PRE 0x0 -#define OFDM_EQ_TOP_RC_STS_SELEC_A_CE 0x0 -#define OFDM_EQ_TOP_RC_STS_SELEC_B_DRI 0x1000 - -#define OFDM_EQ_TOP_RC_STS_OVERFLOW__B 13 -#define OFDM_EQ_TOP_RC_STS_OVERFLOW__W 1 -#define OFDM_EQ_TOP_RC_STS_OVERFLOW__M 0x2000 -#define OFDM_EQ_TOP_RC_STS_OVERFLOW__PRE 0x0 -#define OFDM_EQ_TOP_RC_STS_OVERFLOW_NO 0x0 -#define OFDM_EQ_TOP_RC_STS_OVERFLOW_YES 0x2000 - -#define OFDM_EQ_TOP_RC_STS_LOC_PRS__B 14 -#define OFDM_EQ_TOP_RC_STS_LOC_PRS__W 1 -#define OFDM_EQ_TOP_RC_STS_LOC_PRS__M 0x4000 -#define OFDM_EQ_TOP_RC_STS_LOC_PRS__PRE 0x0 -#define OFDM_EQ_TOP_RC_STS_LOC_PRS_NO 0x0 -#define OFDM_EQ_TOP_RC_STS_LOC_PRS_YES 0x4000 - -#define OFDM_EQ_TOP_RC_STS_DRI_PRS__B 15 -#define OFDM_EQ_TOP_RC_STS_DRI_PRS__W 1 -#define OFDM_EQ_TOP_RC_STS_DRI_PRS__M 0x8000 -#define OFDM_EQ_TOP_RC_STS_DRI_PRS__PRE 0x0 -#define OFDM_EQ_TOP_RC_STS_DRI_PRS_NO 0x0 -#define OFDM_EQ_TOP_RC_STS_DRI_PRS_YES 0x8000 - - -#define OFDM_EQ_TOP_OT_CONST__A 0x3010046 -#define OFDM_EQ_TOP_OT_CONST__W 2 -#define OFDM_EQ_TOP_OT_CONST__M 0x3 -#define OFDM_EQ_TOP_OT_CONST__PRE 0x2 - -#define OFDM_EQ_TOP_OT_ALPHA__A 0x3010047 -#define OFDM_EQ_TOP_OT_ALPHA__W 2 -#define OFDM_EQ_TOP_OT_ALPHA__M 0x3 -#define OFDM_EQ_TOP_OT_ALPHA__PRE 0x0 - -#define OFDM_EQ_TOP_OT_QNT_THRES0__A 0x3010048 -#define OFDM_EQ_TOP_OT_QNT_THRES0__W 5 -#define OFDM_EQ_TOP_OT_QNT_THRES0__M 0x1F -#define OFDM_EQ_TOP_OT_QNT_THRES0__PRE 0x1E - -#define OFDM_EQ_TOP_OT_QNT_THRES1__A 0x3010049 -#define OFDM_EQ_TOP_OT_QNT_THRES1__W 5 -#define OFDM_EQ_TOP_OT_QNT_THRES1__M 0x1F -#define OFDM_EQ_TOP_OT_QNT_THRES1__PRE 0x1F - -#define OFDM_EQ_TOP_OT_CSI_STEP__A 0x301004A -#define OFDM_EQ_TOP_OT_CSI_STEP__W 4 -#define OFDM_EQ_TOP_OT_CSI_STEP__M 0xF -#define OFDM_EQ_TOP_OT_CSI_STEP__PRE 0x5 - -#define OFDM_EQ_TOP_OT_CSI_OFFSET__A 0x301004B -#define OFDM_EQ_TOP_OT_CSI_OFFSET__W 8 -#define OFDM_EQ_TOP_OT_CSI_OFFSET__M 0xFF -#define OFDM_EQ_TOP_OT_CSI_OFFSET__PRE 0x5 - -#define OFDM_EQ_TOP_OT_CSI_GAIN__A 0x301004C -#define OFDM_EQ_TOP_OT_CSI_GAIN__W 8 -#define OFDM_EQ_TOP_OT_CSI_GAIN__M 0xFF -#define OFDM_EQ_TOP_OT_CSI_GAIN__PRE 0x2B - -#define OFDM_EQ_TOP_OT_CSI_MEAN__A 0x301004D -#define OFDM_EQ_TOP_OT_CSI_MEAN__W 7 -#define OFDM_EQ_TOP_OT_CSI_MEAN__M 0x7F -#define OFDM_EQ_TOP_OT_CSI_MEAN__PRE 0x0 - -#define OFDM_EQ_TOP_OT_CSI_VARIANCE__A 0x301004E -#define OFDM_EQ_TOP_OT_CSI_VARIANCE__W 7 -#define OFDM_EQ_TOP_OT_CSI_VARIANCE__M 0x7F -#define OFDM_EQ_TOP_OT_CSI_VARIANCE__PRE 0x0 - -#define OFDM_EQ_TOP_TD_TPS_INIT__A 0x3010050 -#define OFDM_EQ_TOP_TD_TPS_INIT__W 1 -#define OFDM_EQ_TOP_TD_TPS_INIT__M 0x1 -#define OFDM_EQ_TOP_TD_TPS_INIT__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_INIT_POS 0x0 -#define OFDM_EQ_TOP_TD_TPS_INIT_NEG 0x1 - - -#define OFDM_EQ_TOP_TD_TPS_SYNC__A 0x3010051 -#define OFDM_EQ_TOP_TD_TPS_SYNC__W 16 -#define OFDM_EQ_TOP_TD_TPS_SYNC__M 0xFFFF -#define OFDM_EQ_TOP_TD_TPS_SYNC__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_SYNC_ODD 0x35EE -#define OFDM_EQ_TOP_TD_TPS_SYNC_EVEN 0xCA11 - - -#define OFDM_EQ_TOP_TD_TPS_LEN__A 0x3010052 -#define OFDM_EQ_TOP_TD_TPS_LEN__W 6 -#define OFDM_EQ_TOP_TD_TPS_LEN__M 0x3F -#define OFDM_EQ_TOP_TD_TPS_LEN__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_LEN_DEF 0x17 -#define OFDM_EQ_TOP_TD_TPS_LEN_ID_SUP 0x1F - - -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__A 0x3010053 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__W 2 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_1 0x0 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_2 0x1 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_3 0x2 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_4 0x3 - - -#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 -#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 -#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 -#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 -#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 - - -#define OFDM_EQ_TOP_TD_TPS_HINFO__A 0x3010055 -#define OFDM_EQ_TOP_TD_TPS_HINFO__W 3 -#define OFDM_EQ_TOP_TD_TPS_HINFO__M 0x7 -#define OFDM_EQ_TOP_TD_TPS_HINFO__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_HINFO_NH 0x0 -#define OFDM_EQ_TOP_TD_TPS_HINFO_H1 0x1 -#define OFDM_EQ_TOP_TD_TPS_HINFO_H2 0x2 -#define OFDM_EQ_TOP_TD_TPS_HINFO_H4 0x3 - - -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__W 3 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP_1_2 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP_2_3 0x1 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP_3_4 0x2 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP_5_6 0x3 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP_7_8 0x4 - - -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 - - -#define OFDM_EQ_TOP_TD_TPS_GUARD__A 0x3010058 -#define OFDM_EQ_TOP_TD_TPS_GUARD__W 2 -#define OFDM_EQ_TOP_TD_TPS_GUARD__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_GUARD__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_GUARD_32 0x0 -#define OFDM_EQ_TOP_TD_TPS_GUARD_16 0x1 -#define OFDM_EQ_TOP_TD_TPS_GUARD_08 0x2 -#define OFDM_EQ_TOP_TD_TPS_GUARD_04 0x3 - - -#define OFDM_EQ_TOP_TD_TPS_TR_MODE__A 0x3010059 -#define OFDM_EQ_TOP_TD_TPS_TR_MODE__W 2 -#define OFDM_EQ_TOP_TD_TPS_TR_MODE__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_TR_MODE__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_TR_MODE_2K 0x0 -#define OFDM_EQ_TOP_TD_TPS_TR_MODE_8K 0x1 - - -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__A 0x301005A -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__W 8 -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__M 0xFF -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__PRE 0x0 - -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__A 0x301005B -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__W 8 -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__M 0xFF -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__PRE 0x0 - -#define OFDM_EQ_TOP_TD_TPS_RSV__A 0x301005C -#define OFDM_EQ_TOP_TD_TPS_RSV__W 6 -#define OFDM_EQ_TOP_TD_TPS_RSV__M 0x3F -#define OFDM_EQ_TOP_TD_TPS_RSV__PRE 0x0 - -#define OFDM_EQ_TOP_TD_TPS_BCH__A 0x301005D -#define OFDM_EQ_TOP_TD_TPS_BCH__W 14 -#define OFDM_EQ_TOP_TD_TPS_BCH__M 0x3FFF -#define OFDM_EQ_TOP_TD_TPS_BCH__PRE 0x0 - -#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E -#define OFDM_EQ_TOP_TD_SQR_ERR_I__W 16 -#define OFDM_EQ_TOP_TD_SQR_ERR_I__M 0xFFFF -#define OFDM_EQ_TOP_TD_SQR_ERR_I__PRE 0x0 - -#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F -#define OFDM_EQ_TOP_TD_SQR_ERR_Q__W 16 -#define OFDM_EQ_TOP_TD_SQR_ERR_Q__M 0xFFFF -#define OFDM_EQ_TOP_TD_SQR_ERR_Q__PRE 0x0 - -#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 -#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__W 4 -#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__M 0xF -#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__PRE 0x0 - -#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 -#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__W 16 -#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__M 0xFFFF -#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__PRE 0x200 - -#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 -#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__W 10 -#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__M 0x3FF -#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__PRE 0x19F - - - - - -#define OFDM_FE_COMM_EXEC__A 0x2000000 -#define OFDM_FE_COMM_EXEC__W 3 -#define OFDM_FE_COMM_EXEC__M 0x7 -#define OFDM_FE_COMM_EXEC__PRE 0x0 -#define OFDM_FE_COMM_EXEC_STOP 0x0 -#define OFDM_FE_COMM_EXEC_ACTIVE 0x1 -#define OFDM_FE_COMM_EXEC_HOLD 0x2 -#define OFDM_FE_COMM_EXEC_STEP 0x3 - -#define OFDM_FE_COMM_STATE__A 0x2000001 -#define OFDM_FE_COMM_STATE__W 16 -#define OFDM_FE_COMM_STATE__M 0xFFFF -#define OFDM_FE_COMM_STATE__PRE 0x0 -#define OFDM_FE_COMM_MB__A 0x2000002 -#define OFDM_FE_COMM_MB__W 16 -#define OFDM_FE_COMM_MB__M 0xFFFF -#define OFDM_FE_COMM_MB__PRE 0x0 -#define OFDM_FE_COMM_INT_REQ__A 0x2000004 -#define OFDM_FE_COMM_INT_REQ__W 16 -#define OFDM_FE_COMM_INT_REQ__M 0xFFFF -#define OFDM_FE_COMM_INT_REQ__PRE 0x0 -#define OFDM_FE_COMM_INT_REQ_CU_REQ__B 0 -#define OFDM_FE_COMM_INT_REQ_CU_REQ__W 1 -#define OFDM_FE_COMM_INT_REQ_CU_REQ__M 0x1 -#define OFDM_FE_COMM_INT_REQ_CU_REQ__PRE 0x0 - -#define OFDM_FE_COMM_INT_STA__A 0x2000005 -#define OFDM_FE_COMM_INT_STA__W 16 -#define OFDM_FE_COMM_INT_STA__M 0xFFFF -#define OFDM_FE_COMM_INT_STA__PRE 0x0 -#define OFDM_FE_COMM_INT_MSK__A 0x2000006 -#define OFDM_FE_COMM_INT_MSK__W 16 -#define OFDM_FE_COMM_INT_MSK__M 0xFFFF -#define OFDM_FE_COMM_INT_MSK__PRE 0x0 -#define OFDM_FE_COMM_INT_STM__A 0x2000007 -#define OFDM_FE_COMM_INT_STM__W 16 -#define OFDM_FE_COMM_INT_STM__M 0xFFFF -#define OFDM_FE_COMM_INT_STM__PRE 0x0 -#define OFDM_FE_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_FE_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_FE_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_FE_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_FE_CU_COMM_EXEC__A 0x2010000 -#define OFDM_FE_CU_COMM_EXEC__W 3 -#define OFDM_FE_CU_COMM_EXEC__M 0x7 -#define OFDM_FE_CU_COMM_EXEC__PRE 0x0 -#define OFDM_FE_CU_COMM_EXEC_STOP 0x0 -#define OFDM_FE_CU_COMM_EXEC_ACTIVE 0x1 -#define OFDM_FE_CU_COMM_EXEC_HOLD 0x2 -#define OFDM_FE_CU_COMM_EXEC_STEP 0x3 - -#define OFDM_FE_CU_COMM_STATE__A 0x2010001 -#define OFDM_FE_CU_COMM_STATE__W 4 -#define OFDM_FE_CU_COMM_STATE__M 0xF -#define OFDM_FE_CU_COMM_STATE__PRE 0x0 -#define OFDM_FE_CU_COMM_MB__A 0x2010002 -#define OFDM_FE_CU_COMM_MB__W 2 -#define OFDM_FE_CU_COMM_MB__M 0x3 -#define OFDM_FE_CU_COMM_MB__PRE 0x0 -#define OFDM_FE_CU_COMM_MB_CTL__B 0 -#define OFDM_FE_CU_COMM_MB_CTL__W 1 -#define OFDM_FE_CU_COMM_MB_CTL__M 0x1 -#define OFDM_FE_CU_COMM_MB_CTL__PRE 0x0 -#define OFDM_FE_CU_COMM_MB_CTL_OFF 0x0 -#define OFDM_FE_CU_COMM_MB_CTL_ON 0x1 -#define OFDM_FE_CU_COMM_MB_OBS__B 1 -#define OFDM_FE_CU_COMM_MB_OBS__W 1 -#define OFDM_FE_CU_COMM_MB_OBS__M 0x2 -#define OFDM_FE_CU_COMM_MB_OBS__PRE 0x0 -#define OFDM_FE_CU_COMM_MB_OBS_OFF 0x0 -#define OFDM_FE_CU_COMM_MB_OBS_ON 0x2 - -#define OFDM_FE_CU_COMM_INT_REQ__A 0x2010004 -#define OFDM_FE_CU_COMM_INT_REQ__W 1 -#define OFDM_FE_CU_COMM_INT_REQ__M 0x1 -#define OFDM_FE_CU_COMM_INT_REQ__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STA__A 0x2010005 -#define OFDM_FE_CU_COMM_INT_STA__W 4 -#define OFDM_FE_CU_COMM_INT_STA__M 0xF -#define OFDM_FE_CU_COMM_INT_STA__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STA_FE_START__B 0 -#define OFDM_FE_CU_COMM_INT_STA_FE_START__W 1 -#define OFDM_FE_CU_COMM_INT_STA_FE_START__M 0x1 -#define OFDM_FE_CU_COMM_INT_STA_FE_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STA_FT_START__B 1 -#define OFDM_FE_CU_COMM_INT_STA_FT_START__W 1 -#define OFDM_FE_CU_COMM_INT_STA_FT_START__M 0x2 -#define OFDM_FE_CU_COMM_INT_STA_FT_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STA_SB_START__B 2 -#define OFDM_FE_CU_COMM_INT_STA_SB_START__W 1 -#define OFDM_FE_CU_COMM_INT_STA_SB_START__M 0x4 -#define OFDM_FE_CU_COMM_INT_STA_SB_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STA_NF_READY__B 3 -#define OFDM_FE_CU_COMM_INT_STA_NF_READY__W 1 -#define OFDM_FE_CU_COMM_INT_STA_NF_READY__M 0x8 -#define OFDM_FE_CU_COMM_INT_STA_NF_READY__PRE 0x0 - -#define OFDM_FE_CU_COMM_INT_MSK__A 0x2010006 -#define OFDM_FE_CU_COMM_INT_MSK__W 4 -#define OFDM_FE_CU_COMM_INT_MSK__M 0xF -#define OFDM_FE_CU_COMM_INT_MSK__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_MSK_FE_START__B 0 -#define OFDM_FE_CU_COMM_INT_MSK_FE_START__W 1 -#define OFDM_FE_CU_COMM_INT_MSK_FE_START__M 0x1 -#define OFDM_FE_CU_COMM_INT_MSK_FE_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_MSK_FT_START__B 1 -#define OFDM_FE_CU_COMM_INT_MSK_FT_START__W 1 -#define OFDM_FE_CU_COMM_INT_MSK_FT_START__M 0x2 -#define OFDM_FE_CU_COMM_INT_MSK_FT_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_MSK_SB_START__B 2 -#define OFDM_FE_CU_COMM_INT_MSK_SB_START__W 1 -#define OFDM_FE_CU_COMM_INT_MSK_SB_START__M 0x4 -#define OFDM_FE_CU_COMM_INT_MSK_SB_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__B 3 -#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__W 1 -#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__M 0x8 -#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__PRE 0x0 - -#define OFDM_FE_CU_COMM_INT_STM__A 0x2010007 -#define OFDM_FE_CU_COMM_INT_STM__W 4 -#define OFDM_FE_CU_COMM_INT_STM__M 0xF -#define OFDM_FE_CU_COMM_INT_STM__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STM_FE_START__B 0 -#define OFDM_FE_CU_COMM_INT_STM_FE_START__W 1 -#define OFDM_FE_CU_COMM_INT_STM_FE_START__M 0x1 -#define OFDM_FE_CU_COMM_INT_STM_FE_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STM_FT_START__B 1 -#define OFDM_FE_CU_COMM_INT_STM_FT_START__W 1 -#define OFDM_FE_CU_COMM_INT_STM_FT_START__M 0x2 -#define OFDM_FE_CU_COMM_INT_STM_FT_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STM_SB_START__B 2 -#define OFDM_FE_CU_COMM_INT_STM_SB_START__W 1 -#define OFDM_FE_CU_COMM_INT_STM_SB_START__M 0x4 -#define OFDM_FE_CU_COMM_INT_STM_SB_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STM_NF_READY__B 3 -#define OFDM_FE_CU_COMM_INT_STM_NF_READY__W 1 -#define OFDM_FE_CU_COMM_INT_STM_NF_READY__M 0x8 -#define OFDM_FE_CU_COMM_INT_STM_NF_READY__PRE 0x0 - -#define OFDM_FE_CU_MODE__A 0x2010010 -#define OFDM_FE_CU_MODE__W 8 -#define OFDM_FE_CU_MODE__M 0xFF -#define OFDM_FE_CU_MODE__PRE 0x20 - -#define OFDM_FE_CU_MODE_FFT__B 0 -#define OFDM_FE_CU_MODE_FFT__W 1 -#define OFDM_FE_CU_MODE_FFT__M 0x1 -#define OFDM_FE_CU_MODE_FFT__PRE 0x0 -#define OFDM_FE_CU_MODE_FFT_M8K 0x0 -#define OFDM_FE_CU_MODE_FFT_M2K 0x1 - -#define OFDM_FE_CU_MODE_COR__B 1 -#define OFDM_FE_CU_MODE_COR__W 1 -#define OFDM_FE_CU_MODE_COR__M 0x2 -#define OFDM_FE_CU_MODE_COR__PRE 0x0 -#define OFDM_FE_CU_MODE_COR_OFF 0x0 -#define OFDM_FE_CU_MODE_COR_ON 0x2 - -#define OFDM_FE_CU_MODE_IFD__B 2 -#define OFDM_FE_CU_MODE_IFD__W 1 -#define OFDM_FE_CU_MODE_IFD__M 0x4 -#define OFDM_FE_CU_MODE_IFD__PRE 0x0 -#define OFDM_FE_CU_MODE_IFD_ENABLE 0x0 -#define OFDM_FE_CU_MODE_IFD_DISABLE 0x4 - -#define OFDM_FE_CU_MODE_SEL__B 3 -#define OFDM_FE_CU_MODE_SEL__W 1 -#define OFDM_FE_CU_MODE_SEL__M 0x8 -#define OFDM_FE_CU_MODE_SEL__PRE 0x0 -#define OFDM_FE_CU_MODE_SEL_COR 0x0 -#define OFDM_FE_CU_MODE_SEL_COR_NFC 0x8 - -#define OFDM_FE_CU_MODE_FES__B 4 -#define OFDM_FE_CU_MODE_FES__W 1 -#define OFDM_FE_CU_MODE_FES__M 0x10 -#define OFDM_FE_CU_MODE_FES__PRE 0x0 -#define OFDM_FE_CU_MODE_FES_SEL_RST 0x0 -#define OFDM_FE_CU_MODE_FES_SEL_UPD 0x10 -#define OFDM_FE_CU_MODE_AVG__B 5 -#define OFDM_FE_CU_MODE_AVG__W 1 -#define OFDM_FE_CU_MODE_AVG__M 0x20 -#define OFDM_FE_CU_MODE_AVG__PRE 0x20 -#define OFDM_FE_CU_MODE_AVG_OFF 0x0 -#define OFDM_FE_CU_MODE_AVG_ON 0x20 -#define OFDM_FE_CU_MODE_SHF_ENA__B 6 -#define OFDM_FE_CU_MODE_SHF_ENA__W 1 -#define OFDM_FE_CU_MODE_SHF_ENA__M 0x40 -#define OFDM_FE_CU_MODE_SHF_ENA__PRE 0x0 -#define OFDM_FE_CU_MODE_SHF_ENA_OFF 0x0 -#define OFDM_FE_CU_MODE_SHF_ENA_ON 0x40 -#define OFDM_FE_CU_MODE_SHF_DIR__B 7 -#define OFDM_FE_CU_MODE_SHF_DIR__W 1 -#define OFDM_FE_CU_MODE_SHF_DIR__M 0x80 -#define OFDM_FE_CU_MODE_SHF_DIR__PRE 0x0 -#define OFDM_FE_CU_MODE_SHF_DIR_POS 0x0 -#define OFDM_FE_CU_MODE_SHF_DIR_NEG 0x80 - - -#define OFDM_FE_CU_FRM_CNT_RST__A 0x2010011 -#define OFDM_FE_CU_FRM_CNT_RST__W 15 -#define OFDM_FE_CU_FRM_CNT_RST__M 0x7FFF -#define OFDM_FE_CU_FRM_CNT_RST__PRE 0x20FF - -#define OFDM_FE_CU_FRM_CNT_STR__A 0x2010012 -#define OFDM_FE_CU_FRM_CNT_STR__W 15 -#define OFDM_FE_CU_FRM_CNT_STR__M 0x7FFF -#define OFDM_FE_CU_FRM_CNT_STR__PRE 0x1E - -#define OFDM_FE_CU_FRM_SMP_CNT__A 0x2010013 -#define OFDM_FE_CU_FRM_SMP_CNT__W 15 -#define OFDM_FE_CU_FRM_SMP_CNT__M 0x7FFF -#define OFDM_FE_CU_FRM_SMP_CNT__PRE 0x0 - -#define OFDM_FE_CU_FRM_SMB_CNT__A 0x2010014 -#define OFDM_FE_CU_FRM_SMB_CNT__W 16 -#define OFDM_FE_CU_FRM_SMB_CNT__M 0xFFFF -#define OFDM_FE_CU_FRM_SMB_CNT__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_DAT__A 0x2010015 -#define OFDM_FE_CU_CMP_MAX_DAT__W 12 -#define OFDM_FE_CU_CMP_MAX_DAT__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_DAT__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_ADR__A 0x2010016 -#define OFDM_FE_CU_CMP_MAX_ADR__W 10 -#define OFDM_FE_CU_CMP_MAX_ADR__M 0x3FF -#define OFDM_FE_CU_CMP_MAX_ADR__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_RE__A 0x2010017 -#define OFDM_FE_CU_CMP_MAX_RE__W 12 -#define OFDM_FE_CU_CMP_MAX_RE__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_RE__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_IM__A 0x2010018 -#define OFDM_FE_CU_CMP_MAX_IM__W 12 -#define OFDM_FE_CU_CMP_MAX_IM__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_IM__PRE 0x0 - -#define OFDM_FE_CU_BUF_NFC_DEL__A 0x201001F -#define OFDM_FE_CU_BUF_NFC_DEL__W 14 -#define OFDM_FE_CU_BUF_NFC_DEL__M 0x3FFF -#define OFDM_FE_CU_BUF_NFC_DEL__PRE 0x0 - -#define OFDM_FE_CU_CTR_NFC_ICR__A 0x2010020 -#define OFDM_FE_CU_CTR_NFC_ICR__W 5 -#define OFDM_FE_CU_CTR_NFC_ICR__M 0x1F -#define OFDM_FE_CU_CTR_NFC_ICR__PRE 0x1 - -#define OFDM_FE_CU_CTR_NFC_OCR__A 0x2010021 -#define OFDM_FE_CU_CTR_NFC_OCR__W 15 -#define OFDM_FE_CU_CTR_NFC_OCR__M 0x7FFF -#define OFDM_FE_CU_CTR_NFC_OCR__PRE 0x61A8 - -#define OFDM_FE_CU_CTR_NFC_CNT__A 0x2010022 -#define OFDM_FE_CU_CTR_NFC_CNT__W 15 -#define OFDM_FE_CU_CTR_NFC_CNT__M 0x7FFF -#define OFDM_FE_CU_CTR_NFC_CNT__PRE 0x0 - -#define OFDM_FE_CU_CTR_NFC_STS__A 0x2010023 -#define OFDM_FE_CU_CTR_NFC_STS__W 3 -#define OFDM_FE_CU_CTR_NFC_STS__M 0x7 -#define OFDM_FE_CU_CTR_NFC_STS__PRE 0x0 -#define OFDM_FE_CU_CTR_NFC_STS_RUN 0x0 -#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_IMA 0x1 -#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_REA 0x2 -#define OFDM_FE_CU_CTR_NFC_STS_CNT_MAX 0x4 - - -#define OFDM_FE_CU_DIV_NFC_REA__A 0x2010024 -#define OFDM_FE_CU_DIV_NFC_REA__W 14 -#define OFDM_FE_CU_DIV_NFC_REA__M 0x3FFF -#define OFDM_FE_CU_DIV_NFC_REA__PRE 0x0 - -#define OFDM_FE_CU_DIV_NFC_IMA__A 0x2010025 -#define OFDM_FE_CU_DIV_NFC_IMA__W 14 -#define OFDM_FE_CU_DIV_NFC_IMA__M 0x3FFF -#define OFDM_FE_CU_DIV_NFC_IMA__PRE 0x0 - -#define OFDM_FE_CU_FRM_CNT_UPD__A 0x2010026 -#define OFDM_FE_CU_FRM_CNT_UPD__W 15 -#define OFDM_FE_CU_FRM_CNT_UPD__M 0x7FFF -#define OFDM_FE_CU_FRM_CNT_UPD__PRE 0x20FF - -#define OFDM_FE_CU_DIV_NFC_CLP__A 0x2010027 -#define OFDM_FE_CU_DIV_NFC_CLP__W 2 -#define OFDM_FE_CU_DIV_NFC_CLP__M 0x3 -#define OFDM_FE_CU_DIV_NFC_CLP__PRE 0x0 -#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S11 0x0 -#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S12 0x1 -#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S13 0x2 -#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S14 0x3 - - -#define OFDM_FE_CU_CMP_MAX_32__A 0x2010028 -#define OFDM_FE_CU_CMP_MAX_32__W 12 -#define OFDM_FE_CU_CMP_MAX_32__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_32__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_16__A 0x2010029 -#define OFDM_FE_CU_CMP_MAX_16__W 12 -#define OFDM_FE_CU_CMP_MAX_16__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_16__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_8__A 0x201002A -#define OFDM_FE_CU_CMP_MAX_8__W 12 -#define OFDM_FE_CU_CMP_MAX_8__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_8__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_4__A 0x201002B -#define OFDM_FE_CU_CMP_MAX_4__W 12 -#define OFDM_FE_CU_CMP_MAX_4__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_4__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_32_RE__A 0x201002C -#define OFDM_FE_CU_CMP_SUM_32_RE__W 14 -#define OFDM_FE_CU_CMP_SUM_32_RE__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_32_RE__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_32_IM__A 0x201002D -#define OFDM_FE_CU_CMP_SUM_32_IM__W 14 -#define OFDM_FE_CU_CMP_SUM_32_IM__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_32_IM__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_16_RE__A 0x201002E -#define OFDM_FE_CU_CMP_SUM_16_RE__W 14 -#define OFDM_FE_CU_CMP_SUM_16_RE__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_16_RE__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_16_IM__A 0x201002F -#define OFDM_FE_CU_CMP_SUM_16_IM__W 14 -#define OFDM_FE_CU_CMP_SUM_16_IM__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_16_IM__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_8_RE__A 0x2010030 -#define OFDM_FE_CU_CMP_SUM_8_RE__W 14 -#define OFDM_FE_CU_CMP_SUM_8_RE__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_8_RE__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_8_IM__A 0x2010031 -#define OFDM_FE_CU_CMP_SUM_8_IM__W 14 -#define OFDM_FE_CU_CMP_SUM_8_IM__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_8_IM__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_4_RE__A 0x2010032 -#define OFDM_FE_CU_CMP_SUM_4_RE__W 14 -#define OFDM_FE_CU_CMP_SUM_4_RE__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_4_RE__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_4_IM__A 0x2010033 -#define OFDM_FE_CU_CMP_SUM_4_IM__W 14 -#define OFDM_FE_CU_CMP_SUM_4_IM__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_4_IM__PRE 0x0 - - - -#define OFDM_FE_CU_BUF_RAM__A 0x2020000 - - - -#define OFDM_FE_CU_CMP_RAM__A 0x2030000 - - - - - -#define OFDM_FT_COMM_EXEC__A 0x2400000 -#define OFDM_FT_COMM_EXEC__W 3 -#define OFDM_FT_COMM_EXEC__M 0x7 -#define OFDM_FT_COMM_EXEC__PRE 0x0 -#define OFDM_FT_COMM_EXEC_STOP 0x0 -#define OFDM_FT_COMM_EXEC_ACTIVE 0x1 -#define OFDM_FT_COMM_EXEC_HOLD 0x2 -#define OFDM_FT_COMM_EXEC_STEP 0x3 -#define OFDM_FT_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_FT_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_FT_COMM_STATE__A 0x2400001 -#define OFDM_FT_COMM_STATE__W 16 -#define OFDM_FT_COMM_STATE__M 0xFFFF -#define OFDM_FT_COMM_STATE__PRE 0x0 -#define OFDM_FT_COMM_MB__A 0x2400002 -#define OFDM_FT_COMM_MB__W 16 -#define OFDM_FT_COMM_MB__M 0xFFFF -#define OFDM_FT_COMM_MB__PRE 0x0 - - - -#define OFDM_FT_TOP_COMM_EXEC__A 0x2410000 -#define OFDM_FT_TOP_COMM_EXEC__W 3 -#define OFDM_FT_TOP_COMM_EXEC__M 0x7 -#define OFDM_FT_TOP_COMM_EXEC__PRE 0x0 -#define OFDM_FT_TOP_COMM_EXEC_STOP 0x0 -#define OFDM_FT_TOP_COMM_EXEC_ACTIVE 0x1 -#define OFDM_FT_TOP_COMM_EXEC_HOLD 0x2 -#define OFDM_FT_TOP_COMM_EXEC_STEP 0x3 - -#define OFDM_FT_TOP_COMM_MB__A 0x2410002 -#define OFDM_FT_TOP_COMM_MB__W 2 -#define OFDM_FT_TOP_COMM_MB__M 0x3 -#define OFDM_FT_TOP_COMM_MB__PRE 0x0 -#define OFDM_FT_TOP_COMM_MB_CTL__B 0 -#define OFDM_FT_TOP_COMM_MB_CTL__W 1 -#define OFDM_FT_TOP_COMM_MB_CTL__M 0x1 -#define OFDM_FT_TOP_COMM_MB_CTL__PRE 0x0 -#define OFDM_FT_TOP_COMM_MB_CTL_OFF 0x0 -#define OFDM_FT_TOP_COMM_MB_CTL_ON 0x1 -#define OFDM_FT_TOP_COMM_MB_OBS__B 1 -#define OFDM_FT_TOP_COMM_MB_OBS__W 1 -#define OFDM_FT_TOP_COMM_MB_OBS__M 0x2 -#define OFDM_FT_TOP_COMM_MB_OBS__PRE 0x0 -#define OFDM_FT_TOP_COMM_MB_OBS_OFF 0x0 -#define OFDM_FT_TOP_COMM_MB_OBS_ON 0x2 - - -#define OFDM_FT_TOP_MODE_2K__A 0x2410010 -#define OFDM_FT_TOP_MODE_2K__W 1 -#define OFDM_FT_TOP_MODE_2K__M 0x1 -#define OFDM_FT_TOP_MODE_2K__PRE 0x0 -#define OFDM_FT_TOP_MODE_2K_MODE_8K 0x0 -#define OFDM_FT_TOP_MODE_2K_MODE_2K 0x1 - - -#define OFDM_FT_TOP_NORM_OFF__A 0x2410016 -#define OFDM_FT_TOP_NORM_OFF__W 4 -#define OFDM_FT_TOP_NORM_OFF__M 0xF -#define OFDM_FT_TOP_NORM_OFF__PRE 0x2 - - - -#define OFDM_FT_0TO2_0_RAM__A 0x2420000 - - - -#define OFDM_FT_0TO2_1_RAM__A 0x2430000 - - - -#define OFDM_FT_0TO2_2_RAM__A 0x2440000 - - - -#define OFDM_FT_3TO7_0_RAM__A 0x2450000 - - - -#define OFDM_FT_3TO7_1_RAM__A 0x2460000 - - - - - -#define OFDM_LC_COMM_EXEC__A 0x3800000 -#define OFDM_LC_COMM_EXEC__W 3 -#define OFDM_LC_COMM_EXEC__M 0x7 -#define OFDM_LC_COMM_EXEC__PRE 0x0 -#define OFDM_LC_COMM_EXEC_STOP 0x0 -#define OFDM_LC_COMM_EXEC_ACTIVE 0x1 -#define OFDM_LC_COMM_EXEC_HOLD 0x2 -#define OFDM_LC_COMM_EXEC_STEP 0x3 -#define OFDM_LC_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_LC_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_LC_COMM_STATE__A 0x3800001 -#define OFDM_LC_COMM_STATE__W 16 -#define OFDM_LC_COMM_STATE__M 0xFFFF -#define OFDM_LC_COMM_STATE__PRE 0x0 -#define OFDM_LC_COMM_MB__A 0x3800002 -#define OFDM_LC_COMM_MB__W 16 -#define OFDM_LC_COMM_MB__M 0xFFFF -#define OFDM_LC_COMM_MB__PRE 0x0 -#define OFDM_LC_COMM_INT_REQ__A 0x3800004 -#define OFDM_LC_COMM_INT_REQ__W 16 -#define OFDM_LC_COMM_INT_REQ__M 0xFFFF -#define OFDM_LC_COMM_INT_REQ__PRE 0x0 -#define OFDM_LC_COMM_INT_REQ_CT_REQ__B 6 -#define OFDM_LC_COMM_INT_REQ_CT_REQ__W 1 -#define OFDM_LC_COMM_INT_REQ_CT_REQ__M 0x40 -#define OFDM_LC_COMM_INT_REQ_CT_REQ__PRE 0x0 - -#define OFDM_LC_COMM_INT_STA__A 0x3800005 -#define OFDM_LC_COMM_INT_STA__W 16 -#define OFDM_LC_COMM_INT_STA__M 0xFFFF -#define OFDM_LC_COMM_INT_STA__PRE 0x0 -#define OFDM_LC_COMM_INT_MSK__A 0x3800006 -#define OFDM_LC_COMM_INT_MSK__W 16 -#define OFDM_LC_COMM_INT_MSK__M 0xFFFF -#define OFDM_LC_COMM_INT_MSK__PRE 0x0 -#define OFDM_LC_COMM_INT_STM__A 0x3800007 -#define OFDM_LC_COMM_INT_STM__W 16 -#define OFDM_LC_COMM_INT_STM__M 0xFFFF -#define OFDM_LC_COMM_INT_STM__PRE 0x0 -#define OFDM_LC_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_LC_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_LC_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_LC_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_LC_CT_COMM_EXEC__A 0x3810000 -#define OFDM_LC_CT_COMM_EXEC__W 3 -#define OFDM_LC_CT_COMM_EXEC__M 0x7 -#define OFDM_LC_CT_COMM_EXEC__PRE 0x0 -#define OFDM_LC_CT_COMM_EXEC_STOP 0x0 -#define OFDM_LC_CT_COMM_EXEC_ACTIVE 0x1 -#define OFDM_LC_CT_COMM_EXEC_HOLD 0x2 -#define OFDM_LC_CT_COMM_EXEC_STEP 0x3 - - -#define OFDM_LC_CT_COMM_STATE__A 0x3810001 -#define OFDM_LC_CT_COMM_STATE__W 10 -#define OFDM_LC_CT_COMM_STATE__M 0x3FF -#define OFDM_LC_CT_COMM_STATE__PRE 0x0 -#define OFDM_LC_CT_COMM_INT_REQ__A 0x3810004 -#define OFDM_LC_CT_COMM_INT_REQ__W 1 -#define OFDM_LC_CT_COMM_INT_REQ__M 0x1 -#define OFDM_LC_CT_COMM_INT_REQ__PRE 0x0 -#define OFDM_LC_CT_COMM_INT_STA__A 0x3810005 -#define OFDM_LC_CT_COMM_INT_STA__W 1 -#define OFDM_LC_CT_COMM_INT_STA__M 0x1 -#define OFDM_LC_CT_COMM_INT_STA__PRE 0x0 -#define OFDM_LC_CT_COMM_INT_STA_REQUEST__B 0 -#define OFDM_LC_CT_COMM_INT_STA_REQUEST__W 1 -#define OFDM_LC_CT_COMM_INT_STA_REQUEST__M 0x1 -#define OFDM_LC_CT_COMM_INT_STA_REQUEST__PRE 0x0 - -#define OFDM_LC_CT_COMM_INT_MSK__A 0x3810006 -#define OFDM_LC_CT_COMM_INT_MSK__W 1 -#define OFDM_LC_CT_COMM_INT_MSK__M 0x1 -#define OFDM_LC_CT_COMM_INT_MSK__PRE 0x0 -#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__B 0 -#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__W 1 -#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__M 0x1 -#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 - -#define OFDM_LC_CT_COMM_INT_STM__A 0x3810007 -#define OFDM_LC_CT_COMM_INT_STM__W 1 -#define OFDM_LC_CT_COMM_INT_STM__M 0x1 -#define OFDM_LC_CT_COMM_INT_STM__PRE 0x0 -#define OFDM_LC_CT_COMM_INT_STM_REQUEST__B 0 -#define OFDM_LC_CT_COMM_INT_STM_REQUEST__W 1 -#define OFDM_LC_CT_COMM_INT_STM_REQUEST__M 0x1 -#define OFDM_LC_CT_COMM_INT_STM_REQUEST__PRE 0x0 - - -#define OFDM_LC_CT_CTL_STK_0__A 0x3810010 -#define OFDM_LC_CT_CTL_STK_0__W 10 -#define OFDM_LC_CT_CTL_STK_0__M 0x3FF -#define OFDM_LC_CT_CTL_STK_0__PRE 0x0 - -#define OFDM_LC_CT_CTL_STK_1__A 0x3810011 -#define OFDM_LC_CT_CTL_STK_1__W 10 -#define OFDM_LC_CT_CTL_STK_1__M 0x3FF -#define OFDM_LC_CT_CTL_STK_1__PRE 0x0 - -#define OFDM_LC_CT_CTL_STK_2__A 0x3810012 -#define OFDM_LC_CT_CTL_STK_2__W 10 -#define OFDM_LC_CT_CTL_STK_2__M 0x3FF -#define OFDM_LC_CT_CTL_STK_2__PRE 0x0 - -#define OFDM_LC_CT_CTL_STK_3__A 0x3810013 -#define OFDM_LC_CT_CTL_STK_3__W 10 -#define OFDM_LC_CT_CTL_STK_3__M 0x3FF -#define OFDM_LC_CT_CTL_STK_3__PRE 0x0 - -#define OFDM_LC_CT_CTL_BPT_IDX__A 0x381001F -#define OFDM_LC_CT_CTL_BPT_IDX__W 1 -#define OFDM_LC_CT_CTL_BPT_IDX__M 0x1 -#define OFDM_LC_CT_CTL_BPT_IDX__PRE 0x0 - -#define OFDM_LC_CT_CTL_BPT__A 0x3810020 -#define OFDM_LC_CT_CTL_BPT__W 10 -#define OFDM_LC_CT_CTL_BPT__M 0x3FF -#define OFDM_LC_CT_CTL_BPT__PRE 0x0 - - - -#define OFDM_LC_RA_RAM__A 0x3820000 - - - - -#define OFDM_LC_IF_RAM_TRP_BPT0_0__A 0x3830000 -#define OFDM_LC_IF_RAM_TRP_BPT0_0__W 12 -#define OFDM_LC_IF_RAM_TRP_BPT0_0__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_BPT0_0__PRE 0x0 - -#define OFDM_LC_IF_RAM_TRP_BPT0_1__A 0x3830001 -#define OFDM_LC_IF_RAM_TRP_BPT0_1__W 12 -#define OFDM_LC_IF_RAM_TRP_BPT0_1__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_BPT0_1__PRE 0x0 - -#define OFDM_LC_IF_RAM_TRP_STKU_0__A 0x3830002 -#define OFDM_LC_IF_RAM_TRP_STKU_0__W 12 -#define OFDM_LC_IF_RAM_TRP_STKU_0__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_STKU_0__PRE 0x0 - -#define OFDM_LC_IF_RAM_TRP_STKU_1__A 0x3830004 -#define OFDM_LC_IF_RAM_TRP_STKU_1__W 12 -#define OFDM_LC_IF_RAM_TRP_STKU_1__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_STKU_1__PRE 0x0 - -#define OFDM_LC_IF_RAM_TRP_WARM_0__A 0x3830006 -#define OFDM_LC_IF_RAM_TRP_WARM_0__W 12 -#define OFDM_LC_IF_RAM_TRP_WARM_0__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_WARM_0__PRE 0x0 - -#define OFDM_LC_IF_RAM_TRP_WARM_1__A 0x3830007 -#define OFDM_LC_IF_RAM_TRP_WARM_1__W 12 -#define OFDM_LC_IF_RAM_TRP_WARM_1__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_WARM_1__PRE 0x0 - - - - - - - -#define OFDM_LC_RA_RAM_PROC_DELAY_IF__A 0x3820006 -#define OFDM_LC_RA_RAM_PROC_DELAY_IF__W 16 -#define OFDM_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF -#define OFDM_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 -#define OFDM_LC_RA_RAM_PROC_DELAY_FS__A 0x3820007 -#define OFDM_LC_RA_RAM_PROC_DELAY_FS__W 16 -#define OFDM_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF -#define OFDM_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 -#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__A 0x3820008 -#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__W 16 -#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 -#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__A 0x3820009 -#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__W 16 -#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 -#define OFDM_LC_RA_RAM_LOCK_COUNT__A 0x382000A -#define OFDM_LC_RA_RAM_LOCK_COUNT__W 16 -#define OFDM_LC_RA_RAM_LOCK_COUNT__M 0xFFFF -#define OFDM_LC_RA_RAM_LOCK_COUNT__PRE 0x0 -#define OFDM_LC_RA_RAM_CPRTOFS_NOM__A 0x382000B -#define OFDM_LC_RA_RAM_CPRTOFS_NOM__W 16 -#define OFDM_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF -#define OFDM_LC_RA_RAM_CPRTOFS_NOM__PRE 0x0 -#define OFDM_LC_RA_RAM_IFINCR_NOM_L__A 0x382000C -#define OFDM_LC_RA_RAM_IFINCR_NOM_L__W 16 -#define OFDM_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF -#define OFDM_LC_RA_RAM_IFINCR_NOM_L__PRE 0x0 -#define OFDM_LC_RA_RAM_IFINCR_NOM_H__A 0x382000D -#define OFDM_LC_RA_RAM_IFINCR_NOM_H__W 16 -#define OFDM_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF -#define OFDM_LC_RA_RAM_IFINCR_NOM_H__PRE 0x0 -#define OFDM_LC_RA_RAM_FSINCR_NOM_L__A 0x382000E -#define OFDM_LC_RA_RAM_FSINCR_NOM_L__W 16 -#define OFDM_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF -#define OFDM_LC_RA_RAM_FSINCR_NOM_L__PRE 0x0 -#define OFDM_LC_RA_RAM_FSINCR_NOM_H__A 0x382000F -#define OFDM_LC_RA_RAM_FSINCR_NOM_H__W 16 -#define OFDM_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF -#define OFDM_LC_RA_RAM_FSINCR_NOM_H__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_2K__A 0x3820010 -#define OFDM_LC_RA_RAM_MODE_2K__W 16 -#define OFDM_LC_RA_RAM_MODE_2K__M 0xFFFF -#define OFDM_LC_RA_RAM_MODE_2K__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_GUARD__A 0x3820011 -#define OFDM_LC_RA_RAM_MODE_GUARD__W 16 -#define OFDM_LC_RA_RAM_MODE_GUARD__M 0xFFFF -#define OFDM_LC_RA_RAM_MODE_GUARD__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_GUARD_32 0x0 -#define OFDM_LC_RA_RAM_MODE_GUARD_16 0x1 -#define OFDM_LC_RA_RAM_MODE_GUARD_8 0x2 -#define OFDM_LC_RA_RAM_MODE_GUARD_4 0x3 - -#define OFDM_LC_RA_RAM_MODE_ADJUST__A 0x3820012 -#define OFDM_LC_RA_RAM_MODE_ADJUST__W 16 -#define OFDM_LC_RA_RAM_MODE_ADJUST__M 0xFFFF -#define OFDM_LC_RA_RAM_MODE_ADJUST__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 -#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 -#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 -#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 -#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 -#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 -#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__B 12 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__M 0x1000 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__B 13 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__M 0x2000 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__PRE 0x0 - -#define OFDM_LC_RA_RAM_RC_STS__A 0x3820014 -#define OFDM_LC_RA_RAM_RC_STS__W 16 -#define OFDM_LC_RA_RAM_RC_STS__M 0xFFFF -#define OFDM_LC_RA_RAM_RC_STS__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x3820018 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x3820019 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SYM_SET__A 0x382001A -#define OFDM_LC_RA_RAM_FILTER_SYM_SET__W 16 -#define OFDM_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 -#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__A 0x382001B -#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__W 16 -#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 -#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__A 0x382001C -#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__W 16 -#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF -#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 -#define OFDM_LC_RA_RAM_MAX_ABS_EXP__A 0x382001D -#define OFDM_LC_RA_RAM_MAX_ABS_EXP__W 16 -#define OFDM_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF -#define OFDM_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 -#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x382001F -#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x3820020 -#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x3820021 -#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_PHASE__A 0x3820022 -#define OFDM_LC_RA_RAM_ACTUAL_PHASE__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_PHASE__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_DELAY__A 0x3820023 -#define OFDM_LC_RA_RAM_ACTUAL_DELAY__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_DELAY__PRE 0x0 -#define OFDM_LC_RA_RAM_ADJUST_CRMM__A 0x3820024 -#define OFDM_LC_RA_RAM_ADJUST_CRMM__W 16 -#define OFDM_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ADJUST_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ADJUST_SRMM__A 0x3820025 -#define OFDM_LC_RA_RAM_ADJUST_SRMM__W 16 -#define OFDM_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ADJUST_SRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ADJUST_PHASE__A 0x3820026 -#define OFDM_LC_RA_RAM_ADJUST_PHASE__W 16 -#define OFDM_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF -#define OFDM_LC_RA_RAM_ADJUST_PHASE__PRE 0x0 -#define OFDM_LC_RA_RAM_ADJUST_DELAY__A 0x3820027 -#define OFDM_LC_RA_RAM_ADJUST_DELAY__W 16 -#define OFDM_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF -#define OFDM_LC_RA_RAM_ADJUST_DELAY__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x3820028 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x3820029 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x382002A -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x382002B -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x382002C -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x382002D -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_BACKUP__A 0x382002E -#define OFDM_LC_RA_RAM_FILTER_BACKUP__W 16 -#define OFDM_LC_RA_RAM_FILTER_BACKUP__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_BACKUP__PRE 0x4 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x3820030 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x3820031 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x3820032 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x3820033 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x3820034 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x3820035 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x3820038 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x3820039 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x382003A -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x382003B -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x382003C -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x382003D -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_A__A 0x3820060 -#define OFDM_LC_RA_RAM_FILTER_CRMM_A__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_A__PRE 0x7 -#define OFDM_LC_RA_RAM_FILTER_CRMM_B__A 0x3820061 -#define OFDM_LC_RA_RAM_FILTER_CRMM_B__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_B__PRE 0x2 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__A 0x3820062 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__A 0x3820063 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__A 0x3820064 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__A 0x3820065 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__A 0x3820066 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__A 0x3820067 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_A__A 0x3820068 -#define OFDM_LC_RA_RAM_FILTER_SRMM_A__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 -#define OFDM_LC_RA_RAM_FILTER_SRMM_B__A 0x3820069 -#define OFDM_LC_RA_RAM_FILTER_SRMM_B__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__A 0x382006A -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__A 0x382006B -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__A 0x382006C -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__A 0x382006D -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__A 0x382006E -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__A 0x382006F -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_A__A 0x3820070 -#define OFDM_LC_RA_RAM_FILTER_PHASE_A__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 -#define OFDM_LC_RA_RAM_FILTER_PHASE_B__A 0x3820071 -#define OFDM_LC_RA_RAM_FILTER_PHASE_B__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__A 0x3820072 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__A 0x3820073 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__A 0x3820074 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__A 0x3820075 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__A 0x3820076 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__A 0x3820077 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_A__A 0x3820078 -#define OFDM_LC_RA_RAM_FILTER_DELAY_A__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 -#define OFDM_LC_RA_RAM_FILTER_DELAY_B__A 0x3820079 -#define OFDM_LC_RA_RAM_FILTER_DELAY_B__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__A 0x382007A -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__A 0x382007B -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__A 0x382007C -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__A 0x382007D -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__A 0x382007E -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__A 0x382007F -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__PRE 0x0 - - - - - -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_EXEC__W 3 -#define OFDM_SC_COMM_EXEC__M 0x7 -#define OFDM_SC_COMM_EXEC__PRE 0x0 -#define OFDM_SC_COMM_EXEC_STOP 0x0 -#define OFDM_SC_COMM_EXEC_ACTIVE 0x1 -#define OFDM_SC_COMM_EXEC_HOLD 0x2 -#define OFDM_SC_COMM_EXEC_STEP 0x3 -#define OFDM_SC_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_SC_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_SC_COMM_STATE__A 0x3C00001 -#define OFDM_SC_COMM_STATE__W 16 -#define OFDM_SC_COMM_STATE__M 0xFFFF -#define OFDM_SC_COMM_STATE__PRE 0x0 -#define OFDM_SC_COMM_MB__A 0x3C00002 -#define OFDM_SC_COMM_MB__W 16 -#define OFDM_SC_COMM_MB__M 0xFFFF -#define OFDM_SC_COMM_MB__PRE 0x0 -#define OFDM_SC_COMM_INT_REQ__A 0x3C00004 -#define OFDM_SC_COMM_INT_REQ__W 16 -#define OFDM_SC_COMM_INT_REQ__M 0xFFFF -#define OFDM_SC_COMM_INT_REQ__PRE 0x0 -#define OFDM_SC_COMM_INT_REQ_CT_REQ__B 7 -#define OFDM_SC_COMM_INT_REQ_CT_REQ__W 1 -#define OFDM_SC_COMM_INT_REQ_CT_REQ__M 0x80 -#define OFDM_SC_COMM_INT_REQ_CT_REQ__PRE 0x0 - -#define OFDM_SC_COMM_INT_STA__A 0x3C00005 -#define OFDM_SC_COMM_INT_STA__W 16 -#define OFDM_SC_COMM_INT_STA__M 0xFFFF -#define OFDM_SC_COMM_INT_STA__PRE 0x0 -#define OFDM_SC_COMM_INT_MSK__A 0x3C00006 -#define OFDM_SC_COMM_INT_MSK__W 16 -#define OFDM_SC_COMM_INT_MSK__M 0xFFFF -#define OFDM_SC_COMM_INT_MSK__PRE 0x0 -#define OFDM_SC_COMM_INT_STM__A 0x3C00007 -#define OFDM_SC_COMM_INT_STM__W 16 -#define OFDM_SC_COMM_INT_STM__M 0xFFFF -#define OFDM_SC_COMM_INT_STM__PRE 0x0 -#define OFDM_SC_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_SC_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_SC_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_SC_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_SC_CT_COMM_EXEC__A 0x3C10000 -#define OFDM_SC_CT_COMM_EXEC__W 3 -#define OFDM_SC_CT_COMM_EXEC__M 0x7 -#define OFDM_SC_CT_COMM_EXEC__PRE 0x0 -#define OFDM_SC_CT_COMM_EXEC_STOP 0x0 -#define OFDM_SC_CT_COMM_EXEC_ACTIVE 0x1 -#define OFDM_SC_CT_COMM_EXEC_HOLD 0x2 -#define OFDM_SC_CT_COMM_EXEC_STEP 0x3 - - -#define OFDM_SC_CT_COMM_STATE__A 0x3C10001 -#define OFDM_SC_CT_COMM_STATE__W 10 -#define OFDM_SC_CT_COMM_STATE__M 0x3FF -#define OFDM_SC_CT_COMM_STATE__PRE 0x0 -#define OFDM_SC_CT_COMM_INT_REQ__A 0x3C10004 -#define OFDM_SC_CT_COMM_INT_REQ__W 1 -#define OFDM_SC_CT_COMM_INT_REQ__M 0x1 -#define OFDM_SC_CT_COMM_INT_REQ__PRE 0x0 -#define OFDM_SC_CT_COMM_INT_STA__A 0x3C10005 -#define OFDM_SC_CT_COMM_INT_STA__W 1 -#define OFDM_SC_CT_COMM_INT_STA__M 0x1 -#define OFDM_SC_CT_COMM_INT_STA__PRE 0x0 -#define OFDM_SC_CT_COMM_INT_STA_REQUEST__B 0 -#define OFDM_SC_CT_COMM_INT_STA_REQUEST__W 1 -#define OFDM_SC_CT_COMM_INT_STA_REQUEST__M 0x1 -#define OFDM_SC_CT_COMM_INT_STA_REQUEST__PRE 0x0 - -#define OFDM_SC_CT_COMM_INT_MSK__A 0x3C10006 -#define OFDM_SC_CT_COMM_INT_MSK__W 1 -#define OFDM_SC_CT_COMM_INT_MSK__M 0x1 -#define OFDM_SC_CT_COMM_INT_MSK__PRE 0x0 -#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__B 0 -#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__W 1 -#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__M 0x1 -#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 - -#define OFDM_SC_CT_COMM_INT_STM__A 0x3C10007 -#define OFDM_SC_CT_COMM_INT_STM__W 1 -#define OFDM_SC_CT_COMM_INT_STM__M 0x1 -#define OFDM_SC_CT_COMM_INT_STM__PRE 0x0 -#define OFDM_SC_CT_COMM_INT_STM_REQUEST__B 0 -#define OFDM_SC_CT_COMM_INT_STM_REQUEST__W 1 -#define OFDM_SC_CT_COMM_INT_STM_REQUEST__M 0x1 -#define OFDM_SC_CT_COMM_INT_STM_REQUEST__PRE 0x0 - - -#define OFDM_SC_CT_CTL_STK_0__A 0x3C10010 -#define OFDM_SC_CT_CTL_STK_0__W 10 -#define OFDM_SC_CT_CTL_STK_0__M 0x3FF -#define OFDM_SC_CT_CTL_STK_0__PRE 0x0 - -#define OFDM_SC_CT_CTL_STK_1__A 0x3C10011 -#define OFDM_SC_CT_CTL_STK_1__W 10 -#define OFDM_SC_CT_CTL_STK_1__M 0x3FF -#define OFDM_SC_CT_CTL_STK_1__PRE 0x0 - -#define OFDM_SC_CT_CTL_STK_2__A 0x3C10012 -#define OFDM_SC_CT_CTL_STK_2__W 10 -#define OFDM_SC_CT_CTL_STK_2__M 0x3FF -#define OFDM_SC_CT_CTL_STK_2__PRE 0x0 - -#define OFDM_SC_CT_CTL_STK_3__A 0x3C10013 -#define OFDM_SC_CT_CTL_STK_3__W 10 -#define OFDM_SC_CT_CTL_STK_3__M 0x3FF -#define OFDM_SC_CT_CTL_STK_3__PRE 0x0 - -#define OFDM_SC_CT_CTL_BPT_IDX__A 0x3C1001F -#define OFDM_SC_CT_CTL_BPT_IDX__W 1 -#define OFDM_SC_CT_CTL_BPT_IDX__M 0x1 -#define OFDM_SC_CT_CTL_BPT_IDX__PRE 0x0 - -#define OFDM_SC_CT_CTL_BPT__A 0x3C10020 -#define OFDM_SC_CT_CTL_BPT__W 13 -#define OFDM_SC_CT_CTL_BPT__M 0x1FFF -#define OFDM_SC_CT_CTL_BPT__PRE 0x0 - - - -#define OFDM_SC_RA_RAM__A 0x3C20000 - - - - -#define OFDM_SC_IF_RAM_TRP_RST_0__A 0x3C30000 -#define OFDM_SC_IF_RAM_TRP_RST_0__W 12 -#define OFDM_SC_IF_RAM_TRP_RST_0__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_RST_0__PRE 0x0 - -#define OFDM_SC_IF_RAM_TRP_RST_1__A 0x3C30001 -#define OFDM_SC_IF_RAM_TRP_RST_1__W 12 -#define OFDM_SC_IF_RAM_TRP_RST_1__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_RST_1__PRE 0x0 - -#define OFDM_SC_IF_RAM_TRP_BPT0_0__A 0x3C30002 -#define OFDM_SC_IF_RAM_TRP_BPT0_0__W 12 -#define OFDM_SC_IF_RAM_TRP_BPT0_0__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_BPT0_0__PRE 0x0 - -#define OFDM_SC_IF_RAM_TRP_BPT0_1__A 0x3C30004 -#define OFDM_SC_IF_RAM_TRP_BPT0_1__W 12 -#define OFDM_SC_IF_RAM_TRP_BPT0_1__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_BPT0_1__PRE 0x0 - -#define OFDM_SC_IF_RAM_TRP_STKU_0__A 0x3C30004 -#define OFDM_SC_IF_RAM_TRP_STKU_0__W 12 -#define OFDM_SC_IF_RAM_TRP_STKU_0__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_STKU_0__PRE 0x0 - -#define OFDM_SC_IF_RAM_TRP_STKU_1__A 0x3C30005 -#define OFDM_SC_IF_RAM_TRP_STKU_1__W 12 -#define OFDM_SC_IF_RAM_TRP_STKU_1__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_STKU_1__PRE 0x0 - -#define OFDM_SC_IF_RAM_VERSION_MA_MI__A 0x3C30FFE -#define OFDM_SC_IF_RAM_VERSION_MA_MI__W 12 -#define OFDM_SC_IF_RAM_VERSION_MA_MI__M 0xFFF -#define OFDM_SC_IF_RAM_VERSION_MA_MI__PRE 0x0 - -#define OFDM_SC_IF_RAM_VERSION_PATCH__A 0x3C30FFF -#define OFDM_SC_IF_RAM_VERSION_PATCH__W 12 -#define OFDM_SC_IF_RAM_VERSION_PATCH__M 0xFFF -#define OFDM_SC_IF_RAM_VERSION_PATCH__PRE 0x0 - - - - - - - -#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 -#define OFDM_SC_RA_RAM_PARAM0__W 16 -#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 -#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 -#define OFDM_SC_RA_RAM_PARAM1__W 16 -#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 -#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 -#define OFDM_SC_RA_RAM_CMD_ADDR__W 16 -#define OFDM_SC_RA_RAM_CMD_ADDR__M 0xFFFF -#define OFDM_SC_RA_RAM_CMD_ADDR__PRE 0x0 -#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 -#define OFDM_SC_RA_RAM_CMD__W 16 -#define OFDM_SC_RA_RAM_CMD__M 0xFFFF -#define OFDM_SC_RA_RAM_CMD__PRE 0x0 -#define OFDM_SC_RA_RAM_CMD_NULL 0x0 -#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 -#define OFDM_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 -#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 -#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 -#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 -#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 -#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 -#define OFDM_SC_RA_RAM_CMD_MAX 0x9 -#define OFDM_SC_RA_RAM_CMD_LOCK__C 0x4 - -#define OFDM_SC_RA_RAM_PROC_ACTIVATE__A 0x3C20044 -#define OFDM_SC_RA_RAM_PROC_ACTIVATE__W 16 -#define OFDM_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF -#define OFDM_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF -#define OFDM_SC_RA_RAM_PROC_TERMINATED__A 0x3C20045 -#define OFDM_SC_RA_RAM_PROC_TERMINATED__W 16 -#define OFDM_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF -#define OFDM_SC_RA_RAM_PROC_TERMINATED__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT__A 0x3C20046 -#define OFDM_SC_RA_RAM_SW_EVENT__W 14 -#define OFDM_SC_RA_RAM_SW_EVENT__M 0x3FFF -#define OFDM_SC_RA_RAM_SW_EVENT__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN__B 1 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN__M 0x2 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 -#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 -#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__B 3 -#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 -#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__B 4 -#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 -#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__B 7 -#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 -#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__B 8 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__B 9 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__B 12 -#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 -#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__PRE 0x0 - -#define OFDM_SC_RA_RAM_LOCKTRACK__A 0x3C20047 -#define OFDM_SC_RA_RAM_LOCKTRACK__W 16 -#define OFDM_SC_RA_RAM_LOCKTRACK__M 0xFFFF -#define OFDM_SC_RA_RAM_LOCKTRACK__PRE 0x0 -#define OFDM_SC_RA_RAM_LOCKTRACK_NULL 0x0 -#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 -#define OFDM_SC_RA_RAM_LOCKTRACK_RESET 0x1 -#define OFDM_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 -#define OFDM_SC_RA_RAM_LOCKTRACK_SRMM_FIX 0x3 -#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT 0x4 -#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x5 -#define OFDM_SC_RA_RAM_LOCKTRACK_LC 0x6 -#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK 0x7 -#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0x8 -#define OFDM_SC_RA_RAM_LOCKTRACK_MAX 0x9 - -#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 -#define OFDM_SC_RA_RAM_OP_PARAM__W 13 -#define OFDM_SC_RA_RAM_OP_PARAM__M 0x1FFF -#define OFDM_SC_RA_RAM_OP_PARAM__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC -#define OFDM_SC_RA_RAM_OP_PARAM_CONST__B 4 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST__M 0x30 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER__B 6 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER__W 3 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__B 12 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__W 1 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 - -#define OFDM_SC_RA_RAM_OP_AUTO__A 0x3C20049 -#define OFDM_SC_RA_RAM_OP_AUTO__W 6 -#define OFDM_SC_RA_RAM_OP_AUTO__M 0x3F -#define OFDM_SC_RA_RAM_OP_AUTO__PRE 0x1F -#define OFDM_SC_RA_RAM_OP_AUTO_MODE__B 0 -#define OFDM_SC_RA_RAM_OP_AUTO_MODE__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 -#define OFDM_SC_RA_RAM_OP_AUTO_MODE__PRE 0x1 -#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__B 1 -#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 -#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__PRE 0x2 -#define OFDM_SC_RA_RAM_OP_AUTO_CONST__B 2 -#define OFDM_SC_RA_RAM_OP_AUTO_CONST__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 -#define OFDM_SC_RA_RAM_OP_AUTO_CONST__PRE 0x4 -#define OFDM_SC_RA_RAM_OP_AUTO_HIER__B 3 -#define OFDM_SC_RA_RAM_OP_AUTO_HIER__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 -#define OFDM_SC_RA_RAM_OP_AUTO_HIER__PRE 0x8 -#define OFDM_SC_RA_RAM_OP_AUTO_RATE__B 4 -#define OFDM_SC_RA_RAM_OP_AUTO_RATE__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 -#define OFDM_SC_RA_RAM_OP_AUTO_RATE__PRE 0x10 -#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__B 5 -#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 -#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__PRE 0x0 - -#define OFDM_SC_RA_RAM_PILOT_STATUS__A 0x3C2004A -#define OFDM_SC_RA_RAM_PILOT_STATUS__W 16 -#define OFDM_SC_RA_RAM_PILOT_STATUS__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_STATUS__PRE 0x0 -#define OFDM_SC_RA_RAM_PILOT_STATUS_OK 0x0 -#define OFDM_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 -#define OFDM_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 -#define OFDM_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 - -#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B -#define OFDM_SC_RA_RAM_LOCK__W 4 -#define OFDM_SC_RA_RAM_LOCK__M 0xF -#define OFDM_SC_RA_RAM_LOCK__PRE 0x0 -#define OFDM_SC_RA_RAM_LOCK_DEMOD__B 0 -#define OFDM_SC_RA_RAM_LOCK_DEMOD__W 1 -#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 -#define OFDM_SC_RA_RAM_LOCK_DEMOD__PRE 0x0 -#define OFDM_SC_RA_RAM_LOCK_FEC__B 1 -#define OFDM_SC_RA_RAM_LOCK_FEC__W 1 -#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 -#define OFDM_SC_RA_RAM_LOCK_FEC__PRE 0x0 -#define OFDM_SC_RA_RAM_LOCK_MPEG__B 2 -#define OFDM_SC_RA_RAM_LOCK_MPEG__W 1 -#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 -#define OFDM_SC_RA_RAM_LOCK_MPEG__PRE 0x0 -#define OFDM_SC_RA_RAM_LOCK_NODVBT__B 3 -#define OFDM_SC_RA_RAM_LOCK_NODVBT__W 1 -#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 -#define OFDM_SC_RA_RAM_LOCK_NODVBT__PRE 0x0 - -#define OFDM_SC_RA_RAM_BE_OPT_ENA__A 0x3C2004C -#define OFDM_SC_RA_RAM_BE_OPT_ENA__W 5 -#define OFDM_SC_RA_RAM_BE_OPT_ENA__M 0x1F -#define OFDM_SC_RA_RAM_BE_OPT_ENA__PRE 0x1C -#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__B 0 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__W 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__M 0x1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__PRE 0x0 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__B 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__W 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__M 0x2 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__PRE 0x0 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__B 2 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__W 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__M 0x4 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__PRE 0x4 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__B 3 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__W 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__M 0x8 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__PRE 0x8 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__B 4 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__W 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__M 0x10 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__PRE 0x10 - -#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D -#define OFDM_SC_RA_RAM_BE_OPT_DELAY__W 16 -#define OFDM_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF -#define OFDM_SC_RA_RAM_BE_OPT_DELAY__PRE 0x80 -#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E -#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 -#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF -#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 -#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F -#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 -#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 - -#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 -#define OFDM_SC_RA_RAM_CONFIG__W 16 -#define OFDM_SC_RA_RAM_CONFIG__M 0xFFFF -#define OFDM_SC_RA_RAM_CONFIG__PRE 0x14 -#define OFDM_SC_RA_RAM_CONFIG_ID__B 0 -#define OFDM_SC_RA_RAM_CONFIG_ID__W 1 -#define OFDM_SC_RA_RAM_CONFIG_ID__M 0x1 -#define OFDM_SC_RA_RAM_CONFIG_ID__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_ID_ID_PRO 0x0 -#define OFDM_SC_RA_RAM_CONFIG_ID_ID_CONSUMER 0x1 -#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 -#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 -#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 -#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 -#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__PRE 0x4 -#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__B 3 -#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 -#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__B 4 -#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__W 1 -#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 -#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__PRE 0x10 -#define OFDM_SC_RA_RAM_CONFIG_SLAVE__B 5 -#define OFDM_SC_RA_RAM_CONFIG_SLAVE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_SLAVE__M 0x20 -#define OFDM_SC_RA_RAM_CONFIG_SLAVE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__B 6 -#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__W 1 -#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 -#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 -#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 -#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 -#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 -#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 -#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 -#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 -#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 -#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 -#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 -#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__B 11 -#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 -#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 -#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 -#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 -#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__PRE 0x0 - -#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x3C20054 -#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 -#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF -#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 -#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__A 0x3C20055 -#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__W 16 -#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 -#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__A 0x3C20056 -#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__W 16 -#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x3C20057 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__A 0x3C20058 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__W 16 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 -#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__A 0x3C20059 -#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__W 16 -#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 -#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__A 0x3C2005A -#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__W 16 -#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x1 -#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x3C2005B -#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 -#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 -#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__A 0x3C2005C -#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__W 16 -#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x1 -#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__A 0x3C2005D -#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__W 16 -#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF -#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB -#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__A 0x3C2005E -#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__W 16 -#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 -#define OFDM_SC_RA_RAM_MOTION_OFFSET__A 0x3C2005F -#define OFDM_SC_RA_RAM_MOTION_OFFSET__W 16 -#define OFDM_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF -#define OFDM_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__A 0x3C20060 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__A 0x3C20061 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x330 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__A 0x3C20062 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x0 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__A 0x3C20063 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x4 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__A 0x3C20064 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__A 0x3C20065 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x80 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__A 0x3C20066 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__A 0x3C20067 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0xFFFE -#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__A 0x3C2006E -#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__W 16 -#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__PRE 0x1 -#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__A 0x3C2006F -#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__W 16 -#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__PRE 0x320 -#define OFDM_SC_RA_RAM_STATE_PROC_START_1__A 0x3C20070 -#define OFDM_SC_RA_RAM_STATE_PROC_START_1__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_1__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 -#define OFDM_SC_RA_RAM_STATE_PROC_START_2__A 0x3C20071 -#define OFDM_SC_RA_RAM_STATE_PROC_START_2__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_2__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 -#define OFDM_SC_RA_RAM_STATE_PROC_START_3__A 0x3C20072 -#define OFDM_SC_RA_RAM_STATE_PROC_START_3__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_3__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_3__PRE 0x40 -#define OFDM_SC_RA_RAM_STATE_PROC_START_4__A 0x3C20073 -#define OFDM_SC_RA_RAM_STATE_PROC_START_4__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_4__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 -#define OFDM_SC_RA_RAM_STATE_PROC_START_5__A 0x3C20074 -#define OFDM_SC_RA_RAM_STATE_PROC_START_5__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_5__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 -#define OFDM_SC_RA_RAM_STATE_PROC_START_6__A 0x3C20075 -#define OFDM_SC_RA_RAM_STATE_PROC_START_6__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_6__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_6__PRE 0x780 -#define OFDM_SC_RA_RAM_STATE_PROC_START_7__A 0x3C20076 -#define OFDM_SC_RA_RAM_STATE_PROC_START_7__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_7__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_7__PRE 0x230 -#define OFDM_SC_RA_RAM_STATE_PROC_START_8__A 0x3C20077 -#define OFDM_SC_RA_RAM_STATE_PROC_START_8__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_8__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 -#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C -#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 -#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 -#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D -#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 -#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C -#define OFDM_SC_RA_RAM_STATUS__A 0x3C2007E -#define OFDM_SC_RA_RAM_STATUS__W 16 -#define OFDM_SC_RA_RAM_STATUS__M 0xFFFF -#define OFDM_SC_RA_RAM_STATUS__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_BORDER_INIT__A 0x3C2007F -#define OFDM_SC_RA_RAM_NF_BORDER_INIT__W 16 -#define OFDM_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 -#define OFDM_SC_RA_RAM_TIMER__A 0x3C20080 -#define OFDM_SC_RA_RAM_TIMER__W 16 -#define OFDM_SC_RA_RAM_TIMER__M 0xFFFF -#define OFDM_SC_RA_RAM_TIMER__PRE 0x0 -#define OFDM_SC_RA_RAM_FI_OFFSET__A 0x3C20081 -#define OFDM_SC_RA_RAM_FI_OFFSET__W 16 -#define OFDM_SC_RA_RAM_FI_OFFSET__M 0xFFFF -#define OFDM_SC_RA_RAM_FI_OFFSET__PRE 0x382 -#define OFDM_SC_RA_RAM_ECHO_GUARD__A 0x3C20082 -#define OFDM_SC_RA_RAM_ECHO_GUARD__W 16 -#define OFDM_SC_RA_RAM_ECHO_GUARD__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_GUARD__PRE 0x18 -#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__A 0x3C2008D -#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__W 16 -#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__M 0xFFFF -#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__PRE 0x640 -#define OFDM_SC_RA_RAM_IF_SAVE_0__A 0x3C2008E -#define OFDM_SC_RA_RAM_IF_SAVE_0__W 16 -#define OFDM_SC_RA_RAM_IF_SAVE_0__M 0xFFFF -#define OFDM_SC_RA_RAM_IF_SAVE_0__PRE 0x0 -#define OFDM_SC_RA_RAM_IF_SAVE_1__A 0x3C2008F -#define OFDM_SC_RA_RAM_IF_SAVE_1__W 16 -#define OFDM_SC_RA_RAM_IF_SAVE_1__M 0xFFFF -#define OFDM_SC_RA_RAM_IF_SAVE_1__PRE 0x0 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x3C20098 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x3C20099 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x3C2009A -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x3C2009B -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x3C2009C -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x3C2009D -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x3C2009E -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x3C2009F -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC -#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__A 0x3C200B2 -#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__W 16 -#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__M 0xFFFF -#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__PRE 0xC8 -#define OFDM_SC_RA_RAM_MG_VALID_THRES__A 0x3C200B7 -#define OFDM_SC_RA_RAM_MG_VALID_THRES__W 16 -#define OFDM_SC_RA_RAM_MG_VALID_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_MG_VALID_THRES__PRE 0x230 -#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__A 0x3C200B8 -#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__W 16 -#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__PRE 0x320 -#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__A 0x3C200B9 -#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__W 16 -#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__PRE 0x32 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__A 0x3C200BA -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__W 16 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__PRE 0x443 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__B 0 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__W 5 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__M 0x1F -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__PRE 0x3 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__B 5 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__W 5 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__M 0x3E0 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__PRE 0x40 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__B 10 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__W 5 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__M 0x7C00 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__PRE 0x400 - -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__A 0x3C200BB -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__W 16 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__PRE 0x3 -#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__A 0x3C200BC -#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__W 16 -#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__PRE 0x6 -#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__A 0x3C200BD -#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__W 16 -#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__PRE 0x28 -#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__A 0x3C200BE -#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__W 16 -#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__PRE 0x6 -#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__A 0x3C200BF -#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__W 16 -#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__PRE 0x14 -#define OFDM_SC_RA_RAM_IR_FREQ__A 0x3C200D0 -#define OFDM_SC_RA_RAM_IR_FREQ__W 16 -#define OFDM_SC_RA_RAM_IR_FREQ__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FREQ__PRE 0x0 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x3C200D1 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x3C200D2 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x3C200D3 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x3C200D4 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x9 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x3C200D5 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x4 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x3C200D6 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x100 -#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x3C200D7 -#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 -#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x3C200D8 -#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 -#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x3C200D9 -#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 -#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x3C200DA -#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB -#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x3C200DB -#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 -#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x3C200DC -#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x3C200DD -#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 -#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__A 0x3C200DE -#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__W 16 -#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x3C200DF -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0x14C0 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__PRE 0xC0 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__PRE 0x1400 - -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 -#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__A 0x3C200E7 -#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__W 16 -#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__M 0xFFFF -#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__PRE 0x4E2 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x3C200E8 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF -#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x3C200E9 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF -#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C -#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x3C200EA -#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 -#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF -#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 -#define OFDM_SC_RA_RAM_TPS_TIMEOUT__A 0x3C200EB -#define OFDM_SC_RA_RAM_TPS_TIMEOUT__W 16 -#define OFDM_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF -#define OFDM_SC_RA_RAM_TPS_TIMEOUT__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND__A 0x3C200EC -#define OFDM_SC_RA_RAM_BAND__W 16 -#define OFDM_SC_RA_RAM_BAND__M 0xFFFF -#define OFDM_SC_RA_RAM_BAND__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL__B 0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL__W 4 -#define OFDM_SC_RA_RAM_BAND_INTERVAL__M 0xF -#define OFDM_SC_RA_RAM_BAND_INTERVAL__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__PRE 0x0 - -#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x3C200ED -#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 -#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF -#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__A 0x3C200EE -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__W 16 -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__M 0xFFFF -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__PRE 0x19 -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__A 0x3C200EF -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__W 16 -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__PRE 0x1B -#define OFDM_SC_RA_RAM_REG_0__A 0x3C200F0 -#define OFDM_SC_RA_RAM_REG_0__W 16 -#define OFDM_SC_RA_RAM_REG_0__M 0xFFFF -#define OFDM_SC_RA_RAM_REG_0__PRE 0x0 -#define OFDM_SC_RA_RAM_REG_1__A 0x3C200F1 -#define OFDM_SC_RA_RAM_REG_1__W 16 -#define OFDM_SC_RA_RAM_REG_1__M 0xFFFF -#define OFDM_SC_RA_RAM_REG_1__PRE 0x0 -#define OFDM_SC_RA_RAM_BREAK__A 0x3C200F2 -#define OFDM_SC_RA_RAM_BREAK__W 16 -#define OFDM_SC_RA_RAM_BREAK__M 0xFFFF -#define OFDM_SC_RA_RAM_BREAK__PRE 0x0 -#define OFDM_SC_RA_RAM_BOOTCOUNT__A 0x3C200F3 -#define OFDM_SC_RA_RAM_BOOTCOUNT__W 16 -#define OFDM_SC_RA_RAM_BOOTCOUNT__M 0xFFFF -#define OFDM_SC_RA_RAM_BOOTCOUNT__PRE 0x0 -#define OFDM_SC_RA_RAM_LC_ABS_2K__A 0x3C200F4 -#define OFDM_SC_RA_RAM_LC_ABS_2K__W 16 -#define OFDM_SC_RA_RAM_LC_ABS_2K__M 0xFFFF -#define OFDM_SC_RA_RAM_LC_ABS_2K__PRE 0x1F -#define OFDM_SC_RA_RAM_LC_ABS_8K__A 0x3C200F5 -#define OFDM_SC_RA_RAM_LC_ABS_8K__W 16 -#define OFDM_SC_RA_RAM_LC_ABS_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_LC_ABS_8K__PRE 0x1F -#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__A 0x3C200F6 -#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__W 16 -#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__M 0xFFFF -#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__PRE 0x1 -#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x3C200F7 -#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 -#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF -#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F - -#define OFDM_SC_RA_RAM_LC_CP__A 0x3C200F9 -#define OFDM_SC_RA_RAM_LC_CP__W 16 -#define OFDM_SC_RA_RAM_LC_CP__M 0xFFFF -#define OFDM_SC_RA_RAM_LC_CP__PRE 0x1 -#define OFDM_SC_RA_RAM_LC_DIFF__A 0x3C200FA -#define OFDM_SC_RA_RAM_LC_DIFF__W 16 -#define OFDM_SC_RA_RAM_LC_DIFF__M 0xFFFF -#define OFDM_SC_RA_RAM_LC_DIFF__PRE 0x7 -#define OFDM_SC_RA_RAM_ECHO_NF_THRES__A 0x3C200FB -#define OFDM_SC_RA_RAM_ECHO_NF_THRES__W 16 -#define OFDM_SC_RA_RAM_ECHO_NF_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_NF_THRES__PRE 0x1B58 -#define OFDM_SC_RA_RAM_ECHO_NF_FEC__A 0x3C200FC -#define OFDM_SC_RA_RAM_ECHO_NF_FEC__W 16 -#define OFDM_SC_RA_RAM_ECHO_NF_FEC__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_NF_FEC__PRE 0x0 - -#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__A 0x3C200FD -#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__W 16 -#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__PRE 0xFF38 -#define OFDM_SC_RA_RAM_RELOCK__A 0x3C200FE -#define OFDM_SC_RA_RAM_RELOCK__W 16 -#define OFDM_SC_RA_RAM_RELOCK__M 0xFFFF -#define OFDM_SC_RA_RAM_RELOCK__PRE 0x0 -#define OFDM_SC_RA_RAM_STACKUNDERFLOW__A 0x3C200FF -#define OFDM_SC_RA_RAM_STACKUNDERFLOW__W 16 -#define OFDM_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF -#define OFDM_SC_RA_RAM_STACKUNDERFLOW__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x3C20148 -#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 -#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_PREPOST__A 0x3C20149 -#define OFDM_SC_RA_RAM_NF_PREPOST__W 16 -#define OFDM_SC_RA_RAM_NF_PREPOST__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_PREPOST__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_PREBORDER__A 0x3C2014A -#define OFDM_SC_RA_RAM_NF_PREBORDER__W 16 -#define OFDM_SC_RA_RAM_NF_PREBORDER__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_PREBORDER__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_START__A 0x3C2014B -#define OFDM_SC_RA_RAM_NF_START__W 16 -#define OFDM_SC_RA_RAM_NF_START__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_START__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_MINISI_0__A 0x3C2014C -#define OFDM_SC_RA_RAM_NF_MINISI_0__W 16 -#define OFDM_SC_RA_RAM_NF_MINISI_0__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_MINISI_0__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_MINISI_1__A 0x3C2014D -#define OFDM_SC_RA_RAM_NF_MINISI_1__W 16 -#define OFDM_SC_RA_RAM_NF_MINISI_1__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_MINISI_1__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_NRECHOES__A 0x3C2014F -#define OFDM_SC_RA_RAM_NF_NRECHOES__W 16 -#define OFDM_SC_RA_RAM_NF_NRECHOES__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_NRECHOES__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__A 0x3C20150 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__A 0x3C20151 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__A 0x3C20152 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__A 0x3C20153 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__A 0x3C20154 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__A 0x3C20155 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__A 0x3C20156 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__A 0x3C20157 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__A 0x3C20158 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__A 0x3C20159 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__A 0x3C2015A -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__A 0x3C2015B -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__A 0x3C2015C -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__A 0x3C2015D -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__A 0x3C2015E -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__A 0x3C2015F -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__PRE 0x0 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x3C201A0 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x3C201A1 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x3C201A2 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x3C201A3 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x3C201A4 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x3C201A5 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x3C201A6 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x3C201A7 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x3C201A8 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x3C201A9 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x3C201AA -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x3C201AB -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x3C201AC -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x3C201AD -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x3C201AE -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x3C201AF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 -#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__A 0x3C201FE -#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__W 16 -#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__M 0xFFFF -#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__PRE 0x0 -#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__A 0x3C201FF -#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__W 16 -#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__M 0xFFFF -#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__PRE 0x0 - - - - - -#define QAM_COMM_EXEC__A 0x1400000 -#define QAM_COMM_EXEC__W 2 -#define QAM_COMM_EXEC__M 0x3 -#define QAM_COMM_EXEC__PRE 0x0 -#define QAM_COMM_EXEC_STOP 0x0 -#define QAM_COMM_EXEC_ACTIVE 0x1 -#define QAM_COMM_EXEC_HOLD 0x2 - -#define QAM_COMM_MB__A 0x1400002 -#define QAM_COMM_MB__W 16 -#define QAM_COMM_MB__M 0xFFFF -#define QAM_COMM_MB__PRE 0x0 -#define QAM_COMM_INT_REQ__A 0x1400003 -#define QAM_COMM_INT_REQ__W 16 -#define QAM_COMM_INT_REQ__M 0xFFFF -#define QAM_COMM_INT_REQ__PRE 0x0 - -#define QAM_COMM_INT_REQ_SL_REQ__B 0 -#define QAM_COMM_INT_REQ_SL_REQ__W 1 -#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 -#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 - -#define QAM_COMM_INT_REQ_LC_REQ__B 1 -#define QAM_COMM_INT_REQ_LC_REQ__W 1 -#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 -#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 - -#define QAM_COMM_INT_REQ_VD_REQ__B 2 -#define QAM_COMM_INT_REQ_VD_REQ__W 1 -#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 -#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 - -#define QAM_COMM_INT_REQ_SY_REQ__B 3 -#define QAM_COMM_INT_REQ_SY_REQ__W 1 -#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 -#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 - -#define QAM_COMM_INT_STA__A 0x1400005 -#define QAM_COMM_INT_STA__W 16 -#define QAM_COMM_INT_STA__M 0xFFFF -#define QAM_COMM_INT_STA__PRE 0x0 -#define QAM_COMM_INT_MSK__A 0x1400006 -#define QAM_COMM_INT_MSK__W 16 -#define QAM_COMM_INT_MSK__M 0xFFFF -#define QAM_COMM_INT_MSK__PRE 0x0 -#define QAM_COMM_INT_STM__A 0x1400007 -#define QAM_COMM_INT_STM__W 16 -#define QAM_COMM_INT_STM__M 0xFFFF -#define QAM_COMM_INT_STM__PRE 0x0 - - - -#define QAM_TOP_COMM_EXEC__A 0x1410000 -#define QAM_TOP_COMM_EXEC__W 2 -#define QAM_TOP_COMM_EXEC__M 0x3 -#define QAM_TOP_COMM_EXEC__PRE 0x0 -#define QAM_TOP_COMM_EXEC_STOP 0x0 -#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 -#define QAM_TOP_COMM_EXEC_HOLD 0x2 - - -#define QAM_TOP_ANNEX__A 0x1410010 -#define QAM_TOP_ANNEX__W 2 -#define QAM_TOP_ANNEX__M 0x3 -#define QAM_TOP_ANNEX__PRE 0x0 -#define QAM_TOP_ANNEX_A 0x0 -#define QAM_TOP_ANNEX_B 0x1 -#define QAM_TOP_ANNEX_C 0x2 -#define QAM_TOP_ANNEX_D 0x3 - - -#define QAM_TOP_CONSTELLATION__A 0x1410011 -#define QAM_TOP_CONSTELLATION__W 3 -#define QAM_TOP_CONSTELLATION__M 0x7 -#define QAM_TOP_CONSTELLATION__PRE 0x5 -#define QAM_TOP_CONSTELLATION_NONE 0x0 -#define QAM_TOP_CONSTELLATION_QPSK 0x1 -#define QAM_TOP_CONSTELLATION_QAM8 0x2 -#define QAM_TOP_CONSTELLATION_QAM16 0x3 -#define QAM_TOP_CONSTELLATION_QAM32 0x4 -#define QAM_TOP_CONSTELLATION_QAM64 0x5 -#define QAM_TOP_CONSTELLATION_QAM128 0x6 -#define QAM_TOP_CONSTELLATION_QAM256 0x7 - - - -#define QAM_FQ_COMM_EXEC__A 0x1420000 -#define QAM_FQ_COMM_EXEC__W 2 -#define QAM_FQ_COMM_EXEC__M 0x3 -#define QAM_FQ_COMM_EXEC__PRE 0x0 -#define QAM_FQ_COMM_EXEC_STOP 0x0 -#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 -#define QAM_FQ_COMM_EXEC_HOLD 0x2 - -#define QAM_FQ_MODE__A 0x1420010 -#define QAM_FQ_MODE__W 3 -#define QAM_FQ_MODE__M 0x7 -#define QAM_FQ_MODE__PRE 0x0 - -#define QAM_FQ_MODE_TAPRESET__B 0 -#define QAM_FQ_MODE_TAPRESET__W 1 -#define QAM_FQ_MODE_TAPRESET__M 0x1 -#define QAM_FQ_MODE_TAPRESET__PRE 0x0 -#define QAM_FQ_MODE_TAPRESET_RST 0x1 - -#define QAM_FQ_MODE_TAPLMS__B 1 -#define QAM_FQ_MODE_TAPLMS__W 1 -#define QAM_FQ_MODE_TAPLMS__M 0x2 -#define QAM_FQ_MODE_TAPLMS__PRE 0x0 -#define QAM_FQ_MODE_TAPLMS_UPD 0x2 - -#define QAM_FQ_MODE_TAPDRAIN__B 2 -#define QAM_FQ_MODE_TAPDRAIN__W 1 -#define QAM_FQ_MODE_TAPDRAIN__M 0x4 -#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 -#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 - - -#define QAM_FQ_MU_FACTOR__A 0x1420011 -#define QAM_FQ_MU_FACTOR__W 3 -#define QAM_FQ_MU_FACTOR__M 0x7 -#define QAM_FQ_MU_FACTOR__PRE 0x0 - -#define QAM_FQ_LA_FACTOR__A 0x1420012 -#define QAM_FQ_LA_FACTOR__W 4 -#define QAM_FQ_LA_FACTOR__M 0xF -#define QAM_FQ_LA_FACTOR__PRE 0xC -#define QAM_FQ_CENTTAP_IDX__A 0x1420016 -#define QAM_FQ_CENTTAP_IDX__W 5 -#define QAM_FQ_CENTTAP_IDX__M 0x1F -#define QAM_FQ_CENTTAP_IDX__PRE 0x13 - -#define QAM_FQ_CENTTAP_IDX_IDX__B 0 -#define QAM_FQ_CENTTAP_IDX_IDX__W 5 -#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F -#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 - -#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 -#define QAM_FQ_CENTTAP_VALUE__W 12 -#define QAM_FQ_CENTTAP_VALUE__M 0xFFF -#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 - -#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 -#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 -#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF -#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 - -#define QAM_FQ_TAP_RE_EL0__A 0x1420020 -#define QAM_FQ_TAP_RE_EL0__W 12 -#define QAM_FQ_TAP_RE_EL0__M 0xFFF -#define QAM_FQ_TAP_RE_EL0__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL0_TAP__B 0 -#define QAM_FQ_TAP_RE_EL0_TAP__W 12 -#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL0__A 0x1420021 -#define QAM_FQ_TAP_IM_EL0__W 12 -#define QAM_FQ_TAP_IM_EL0__M 0xFFF -#define QAM_FQ_TAP_IM_EL0__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL0_TAP__B 0 -#define QAM_FQ_TAP_IM_EL0_TAP__W 12 -#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL1__A 0x1420022 -#define QAM_FQ_TAP_RE_EL1__W 12 -#define QAM_FQ_TAP_RE_EL1__M 0xFFF -#define QAM_FQ_TAP_RE_EL1__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL1_TAP__B 0 -#define QAM_FQ_TAP_RE_EL1_TAP__W 12 -#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL1__A 0x1420023 -#define QAM_FQ_TAP_IM_EL1__W 12 -#define QAM_FQ_TAP_IM_EL1__M 0xFFF -#define QAM_FQ_TAP_IM_EL1__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL1_TAP__B 0 -#define QAM_FQ_TAP_IM_EL1_TAP__W 12 -#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL2__A 0x1420024 -#define QAM_FQ_TAP_RE_EL2__W 12 -#define QAM_FQ_TAP_RE_EL2__M 0xFFF -#define QAM_FQ_TAP_RE_EL2__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL2_TAP__B 0 -#define QAM_FQ_TAP_RE_EL2_TAP__W 12 -#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL2__A 0x1420025 -#define QAM_FQ_TAP_IM_EL2__W 12 -#define QAM_FQ_TAP_IM_EL2__M 0xFFF -#define QAM_FQ_TAP_IM_EL2__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL2_TAP__B 0 -#define QAM_FQ_TAP_IM_EL2_TAP__W 12 -#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL3__A 0x1420026 -#define QAM_FQ_TAP_RE_EL3__W 12 -#define QAM_FQ_TAP_RE_EL3__M 0xFFF -#define QAM_FQ_TAP_RE_EL3__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL3_TAP__B 0 -#define QAM_FQ_TAP_RE_EL3_TAP__W 12 -#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL3__A 0x1420027 -#define QAM_FQ_TAP_IM_EL3__W 12 -#define QAM_FQ_TAP_IM_EL3__M 0xFFF -#define QAM_FQ_TAP_IM_EL3__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL3_TAP__B 0 -#define QAM_FQ_TAP_IM_EL3_TAP__W 12 -#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL4__A 0x1420028 -#define QAM_FQ_TAP_RE_EL4__W 12 -#define QAM_FQ_TAP_RE_EL4__M 0xFFF -#define QAM_FQ_TAP_RE_EL4__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL4_TAP__B 0 -#define QAM_FQ_TAP_RE_EL4_TAP__W 12 -#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL4__A 0x1420029 -#define QAM_FQ_TAP_IM_EL4__W 12 -#define QAM_FQ_TAP_IM_EL4__M 0xFFF -#define QAM_FQ_TAP_IM_EL4__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL4_TAP__B 0 -#define QAM_FQ_TAP_IM_EL4_TAP__W 12 -#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL5__A 0x142002A -#define QAM_FQ_TAP_RE_EL5__W 12 -#define QAM_FQ_TAP_RE_EL5__M 0xFFF -#define QAM_FQ_TAP_RE_EL5__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL5_TAP__B 0 -#define QAM_FQ_TAP_RE_EL5_TAP__W 12 -#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL5__A 0x142002B -#define QAM_FQ_TAP_IM_EL5__W 12 -#define QAM_FQ_TAP_IM_EL5__M 0xFFF -#define QAM_FQ_TAP_IM_EL5__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL5_TAP__B 0 -#define QAM_FQ_TAP_IM_EL5_TAP__W 12 -#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL6__A 0x142002C -#define QAM_FQ_TAP_RE_EL6__W 12 -#define QAM_FQ_TAP_RE_EL6__M 0xFFF -#define QAM_FQ_TAP_RE_EL6__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL6_TAP__B 0 -#define QAM_FQ_TAP_RE_EL6_TAP__W 12 -#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL6__A 0x142002D -#define QAM_FQ_TAP_IM_EL6__W 12 -#define QAM_FQ_TAP_IM_EL6__M 0xFFF -#define QAM_FQ_TAP_IM_EL6__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL6_TAP__B 0 -#define QAM_FQ_TAP_IM_EL6_TAP__W 12 -#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL7__A 0x142002E -#define QAM_FQ_TAP_RE_EL7__W 12 -#define QAM_FQ_TAP_RE_EL7__M 0xFFF -#define QAM_FQ_TAP_RE_EL7__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL7_TAP__B 0 -#define QAM_FQ_TAP_RE_EL7_TAP__W 12 -#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL7__A 0x142002F -#define QAM_FQ_TAP_IM_EL7__W 12 -#define QAM_FQ_TAP_IM_EL7__M 0xFFF -#define QAM_FQ_TAP_IM_EL7__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL7_TAP__B 0 -#define QAM_FQ_TAP_IM_EL7_TAP__W 12 -#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL8__A 0x1420030 -#define QAM_FQ_TAP_RE_EL8__W 12 -#define QAM_FQ_TAP_RE_EL8__M 0xFFF -#define QAM_FQ_TAP_RE_EL8__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL8_TAP__B 0 -#define QAM_FQ_TAP_RE_EL8_TAP__W 12 -#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL8__A 0x1420031 -#define QAM_FQ_TAP_IM_EL8__W 12 -#define QAM_FQ_TAP_IM_EL8__M 0xFFF -#define QAM_FQ_TAP_IM_EL8__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL8_TAP__B 0 -#define QAM_FQ_TAP_IM_EL8_TAP__W 12 -#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL9__A 0x1420032 -#define QAM_FQ_TAP_RE_EL9__W 12 -#define QAM_FQ_TAP_RE_EL9__M 0xFFF -#define QAM_FQ_TAP_RE_EL9__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL9_TAP__B 0 -#define QAM_FQ_TAP_RE_EL9_TAP__W 12 -#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL9__A 0x1420033 -#define QAM_FQ_TAP_IM_EL9__W 12 -#define QAM_FQ_TAP_IM_EL9__M 0xFFF -#define QAM_FQ_TAP_IM_EL9__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL9_TAP__B 0 -#define QAM_FQ_TAP_IM_EL9_TAP__W 12 -#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL10__A 0x1420034 -#define QAM_FQ_TAP_RE_EL10__W 12 -#define QAM_FQ_TAP_RE_EL10__M 0xFFF -#define QAM_FQ_TAP_RE_EL10__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL10_TAP__B 0 -#define QAM_FQ_TAP_RE_EL10_TAP__W 12 -#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL10__A 0x1420035 -#define QAM_FQ_TAP_IM_EL10__W 12 -#define QAM_FQ_TAP_IM_EL10__M 0xFFF -#define QAM_FQ_TAP_IM_EL10__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL10_TAP__B 0 -#define QAM_FQ_TAP_IM_EL10_TAP__W 12 -#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL11__A 0x1420036 -#define QAM_FQ_TAP_RE_EL11__W 12 -#define QAM_FQ_TAP_RE_EL11__M 0xFFF -#define QAM_FQ_TAP_RE_EL11__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL11_TAP__B 0 -#define QAM_FQ_TAP_RE_EL11_TAP__W 12 -#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL11__A 0x1420037 -#define QAM_FQ_TAP_IM_EL11__W 12 -#define QAM_FQ_TAP_IM_EL11__M 0xFFF -#define QAM_FQ_TAP_IM_EL11__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL11_TAP__B 0 -#define QAM_FQ_TAP_IM_EL11_TAP__W 12 -#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL12__A 0x1420038 -#define QAM_FQ_TAP_RE_EL12__W 12 -#define QAM_FQ_TAP_RE_EL12__M 0xFFF -#define QAM_FQ_TAP_RE_EL12__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL12_TAP__B 0 -#define QAM_FQ_TAP_RE_EL12_TAP__W 12 -#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL12__A 0x1420039 -#define QAM_FQ_TAP_IM_EL12__W 12 -#define QAM_FQ_TAP_IM_EL12__M 0xFFF -#define QAM_FQ_TAP_IM_EL12__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL12_TAP__B 0 -#define QAM_FQ_TAP_IM_EL12_TAP__W 12 -#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL13__A 0x142003A -#define QAM_FQ_TAP_RE_EL13__W 12 -#define QAM_FQ_TAP_RE_EL13__M 0xFFF -#define QAM_FQ_TAP_RE_EL13__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL13_TAP__B 0 -#define QAM_FQ_TAP_RE_EL13_TAP__W 12 -#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL13__A 0x142003B -#define QAM_FQ_TAP_IM_EL13__W 12 -#define QAM_FQ_TAP_IM_EL13__M 0xFFF -#define QAM_FQ_TAP_IM_EL13__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL13_TAP__B 0 -#define QAM_FQ_TAP_IM_EL13_TAP__W 12 -#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL14__A 0x142003C -#define QAM_FQ_TAP_RE_EL14__W 12 -#define QAM_FQ_TAP_RE_EL14__M 0xFFF -#define QAM_FQ_TAP_RE_EL14__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL14_TAP__B 0 -#define QAM_FQ_TAP_RE_EL14_TAP__W 12 -#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL14__A 0x142003D -#define QAM_FQ_TAP_IM_EL14__W 12 -#define QAM_FQ_TAP_IM_EL14__M 0xFFF -#define QAM_FQ_TAP_IM_EL14__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL14_TAP__B 0 -#define QAM_FQ_TAP_IM_EL14_TAP__W 12 -#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL15__A 0x142003E -#define QAM_FQ_TAP_RE_EL15__W 12 -#define QAM_FQ_TAP_RE_EL15__M 0xFFF -#define QAM_FQ_TAP_RE_EL15__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL15_TAP__B 0 -#define QAM_FQ_TAP_RE_EL15_TAP__W 12 -#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL15__A 0x142003F -#define QAM_FQ_TAP_IM_EL15__W 12 -#define QAM_FQ_TAP_IM_EL15__M 0xFFF -#define QAM_FQ_TAP_IM_EL15__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL15_TAP__B 0 -#define QAM_FQ_TAP_IM_EL15_TAP__W 12 -#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL16__A 0x1420040 -#define QAM_FQ_TAP_RE_EL16__W 12 -#define QAM_FQ_TAP_RE_EL16__M 0xFFF -#define QAM_FQ_TAP_RE_EL16__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL16_TAP__B 0 -#define QAM_FQ_TAP_RE_EL16_TAP__W 12 -#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL16__A 0x1420041 -#define QAM_FQ_TAP_IM_EL16__W 12 -#define QAM_FQ_TAP_IM_EL16__M 0xFFF -#define QAM_FQ_TAP_IM_EL16__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL16_TAP__B 0 -#define QAM_FQ_TAP_IM_EL16_TAP__W 12 -#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL17__A 0x1420042 -#define QAM_FQ_TAP_RE_EL17__W 12 -#define QAM_FQ_TAP_RE_EL17__M 0xFFF -#define QAM_FQ_TAP_RE_EL17__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL17_TAP__B 0 -#define QAM_FQ_TAP_RE_EL17_TAP__W 12 -#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL17__A 0x1420043 -#define QAM_FQ_TAP_IM_EL17__W 12 -#define QAM_FQ_TAP_IM_EL17__M 0xFFF -#define QAM_FQ_TAP_IM_EL17__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL17_TAP__B 0 -#define QAM_FQ_TAP_IM_EL17_TAP__W 12 -#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL18__A 0x1420044 -#define QAM_FQ_TAP_RE_EL18__W 12 -#define QAM_FQ_TAP_RE_EL18__M 0xFFF -#define QAM_FQ_TAP_RE_EL18__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL18_TAP__B 0 -#define QAM_FQ_TAP_RE_EL18_TAP__W 12 -#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL18__A 0x1420045 -#define QAM_FQ_TAP_IM_EL18__W 12 -#define QAM_FQ_TAP_IM_EL18__M 0xFFF -#define QAM_FQ_TAP_IM_EL18__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL18_TAP__B 0 -#define QAM_FQ_TAP_IM_EL18_TAP__W 12 -#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL19__A 0x1420046 -#define QAM_FQ_TAP_RE_EL19__W 12 -#define QAM_FQ_TAP_RE_EL19__M 0xFFF -#define QAM_FQ_TAP_RE_EL19__PRE 0x600 - -#define QAM_FQ_TAP_RE_EL19_TAP__B 0 -#define QAM_FQ_TAP_RE_EL19_TAP__W 12 -#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 - -#define QAM_FQ_TAP_IM_EL19__A 0x1420047 -#define QAM_FQ_TAP_IM_EL19__W 12 -#define QAM_FQ_TAP_IM_EL19__M 0xFFF -#define QAM_FQ_TAP_IM_EL19__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL19_TAP__B 0 -#define QAM_FQ_TAP_IM_EL19_TAP__W 12 -#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL20__A 0x1420048 -#define QAM_FQ_TAP_RE_EL20__W 12 -#define QAM_FQ_TAP_RE_EL20__M 0xFFF -#define QAM_FQ_TAP_RE_EL20__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL20_TAP__B 0 -#define QAM_FQ_TAP_RE_EL20_TAP__W 12 -#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL20__A 0x1420049 -#define QAM_FQ_TAP_IM_EL20__W 12 -#define QAM_FQ_TAP_IM_EL20__M 0xFFF -#define QAM_FQ_TAP_IM_EL20__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL20_TAP__B 0 -#define QAM_FQ_TAP_IM_EL20_TAP__W 12 -#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL21__A 0x142004A -#define QAM_FQ_TAP_RE_EL21__W 12 -#define QAM_FQ_TAP_RE_EL21__M 0xFFF -#define QAM_FQ_TAP_RE_EL21__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL21_TAP__B 0 -#define QAM_FQ_TAP_RE_EL21_TAP__W 12 -#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL21__A 0x142004B -#define QAM_FQ_TAP_IM_EL21__W 12 -#define QAM_FQ_TAP_IM_EL21__M 0xFFF -#define QAM_FQ_TAP_IM_EL21__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL21_TAP__B 0 -#define QAM_FQ_TAP_IM_EL21_TAP__W 12 -#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL22__A 0x142004C -#define QAM_FQ_TAP_RE_EL22__W 12 -#define QAM_FQ_TAP_RE_EL22__M 0xFFF -#define QAM_FQ_TAP_RE_EL22__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL22_TAP__B 0 -#define QAM_FQ_TAP_RE_EL22_TAP__W 12 -#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL22__A 0x142004D -#define QAM_FQ_TAP_IM_EL22__W 12 -#define QAM_FQ_TAP_IM_EL22__M 0xFFF -#define QAM_FQ_TAP_IM_EL22__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL22_TAP__B 0 -#define QAM_FQ_TAP_IM_EL22_TAP__W 12 -#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL23__A 0x142004E -#define QAM_FQ_TAP_RE_EL23__W 12 -#define QAM_FQ_TAP_RE_EL23__M 0xFFF -#define QAM_FQ_TAP_RE_EL23__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL23_TAP__B 0 -#define QAM_FQ_TAP_RE_EL23_TAP__W 12 -#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL23__A 0x142004F -#define QAM_FQ_TAP_IM_EL23__W 12 -#define QAM_FQ_TAP_IM_EL23__M 0xFFF -#define QAM_FQ_TAP_IM_EL23__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL23_TAP__B 0 -#define QAM_FQ_TAP_IM_EL23_TAP__W 12 -#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 - - - -#define QAM_SL_COMM_EXEC__A 0x1430000 -#define QAM_SL_COMM_EXEC__W 2 -#define QAM_SL_COMM_EXEC__M 0x3 -#define QAM_SL_COMM_EXEC__PRE 0x0 -#define QAM_SL_COMM_EXEC_STOP 0x0 -#define QAM_SL_COMM_EXEC_ACTIVE 0x1 -#define QAM_SL_COMM_EXEC_HOLD 0x2 - -#define QAM_SL_COMM_MB__A 0x1430002 -#define QAM_SL_COMM_MB__W 4 -#define QAM_SL_COMM_MB__M 0xF -#define QAM_SL_COMM_MB__PRE 0x0 -#define QAM_SL_COMM_MB_CTL__B 0 -#define QAM_SL_COMM_MB_CTL__W 1 -#define QAM_SL_COMM_MB_CTL__M 0x1 -#define QAM_SL_COMM_MB_CTL__PRE 0x0 -#define QAM_SL_COMM_MB_CTL_OFF 0x0 -#define QAM_SL_COMM_MB_CTL_ON 0x1 -#define QAM_SL_COMM_MB_OBS__B 1 -#define QAM_SL_COMM_MB_OBS__W 1 -#define QAM_SL_COMM_MB_OBS__M 0x2 -#define QAM_SL_COMM_MB_OBS__PRE 0x0 -#define QAM_SL_COMM_MB_OBS_OFF 0x0 -#define QAM_SL_COMM_MB_OBS_ON 0x2 -#define QAM_SL_COMM_MB_MUX_OBS__B 2 -#define QAM_SL_COMM_MB_MUX_OBS__W 2 -#define QAM_SL_COMM_MB_MUX_OBS__M 0xC -#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 -#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 -#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 -#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 -#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC - -#define QAM_SL_COMM_INT_REQ__A 0x1430003 -#define QAM_SL_COMM_INT_REQ__W 1 -#define QAM_SL_COMM_INT_REQ__M 0x1 -#define QAM_SL_COMM_INT_REQ__PRE 0x0 -#define QAM_SL_COMM_INT_STA__A 0x1430005 -#define QAM_SL_COMM_INT_STA__W 2 -#define QAM_SL_COMM_INT_STA__M 0x3 -#define QAM_SL_COMM_INT_STA__PRE 0x0 - -#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 -#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 -#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 -#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 - -#define QAM_SL_COMM_INT_STA_MER_INT__B 1 -#define QAM_SL_COMM_INT_STA_MER_INT__W 1 -#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 -#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 - -#define QAM_SL_COMM_INT_MSK__A 0x1430006 -#define QAM_SL_COMM_INT_MSK__W 2 -#define QAM_SL_COMM_INT_MSK__M 0x3 -#define QAM_SL_COMM_INT_MSK__PRE 0x0 -#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 -#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 -#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 -#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 -#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 -#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 -#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 -#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 - -#define QAM_SL_COMM_INT_STM__A 0x1430007 -#define QAM_SL_COMM_INT_STM__W 2 -#define QAM_SL_COMM_INT_STM__M 0x3 -#define QAM_SL_COMM_INT_STM__PRE 0x0 -#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 -#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 -#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 -#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 -#define QAM_SL_COMM_INT_STM_MER_STM__B 1 -#define QAM_SL_COMM_INT_STM_MER_STM__W 1 -#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 -#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 - -#define QAM_SL_MODE__A 0x1430010 -#define QAM_SL_MODE__W 11 -#define QAM_SL_MODE__M 0x7FF -#define QAM_SL_MODE__PRE 0xA - -#define QAM_SL_MODE_SLICER4LC__B 0 -#define QAM_SL_MODE_SLICER4LC__W 2 -#define QAM_SL_MODE_SLICER4LC__M 0x3 -#define QAM_SL_MODE_SLICER4LC__PRE 0x2 -#define QAM_SL_MODE_SLICER4LC_RECT 0x0 -#define QAM_SL_MODE_SLICER4LC_ONET 0x1 -#define QAM_SL_MODE_SLICER4LC_RAD 0x2 - -#define QAM_SL_MODE_SLICER4DQ__B 2 -#define QAM_SL_MODE_SLICER4DQ__W 2 -#define QAM_SL_MODE_SLICER4DQ__M 0xC -#define QAM_SL_MODE_SLICER4DQ__PRE 0x8 -#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 -#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 -#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 - -#define QAM_SL_MODE_SLICER4VD__B 4 -#define QAM_SL_MODE_SLICER4VD__W 2 -#define QAM_SL_MODE_SLICER4VD__M 0x30 -#define QAM_SL_MODE_SLICER4VD__PRE 0x0 -#define QAM_SL_MODE_SLICER4VD_RECT 0x0 -#define QAM_SL_MODE_SLICER4VD_ONET 0x10 -#define QAM_SL_MODE_SLICER4VD_RAD 0x20 - -#define QAM_SL_MODE_ROT_DIS__B 6 -#define QAM_SL_MODE_ROT_DIS__W 1 -#define QAM_SL_MODE_ROT_DIS__M 0x40 -#define QAM_SL_MODE_ROT_DIS__PRE 0x0 -#define QAM_SL_MODE_ROT_DIS_ROTATE 0x0 -#define QAM_SL_MODE_ROT_DIS_DISABLED 0x40 - -#define QAM_SL_MODE_DQROT_DIS__B 7 -#define QAM_SL_MODE_DQROT_DIS__W 1 -#define QAM_SL_MODE_DQROT_DIS__M 0x80 -#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 -#define QAM_SL_MODE_DQROT_DIS_ROTATE 0x0 -#define QAM_SL_MODE_DQROT_DIS_DISABLED 0x80 - -#define QAM_SL_MODE_DFE_DIS__B 8 -#define QAM_SL_MODE_DFE_DIS__W 1 -#define QAM_SL_MODE_DFE_DIS__M 0x100 -#define QAM_SL_MODE_DFE_DIS__PRE 0x0 -#define QAM_SL_MODE_DFE_DIS_DQ 0x0 -#define QAM_SL_MODE_DFE_DIS_DISABLED 0x100 - -#define QAM_SL_MODE_RADIUS_MIX__B 9 -#define QAM_SL_MODE_RADIUS_MIX__W 1 -#define QAM_SL_MODE_RADIUS_MIX__M 0x200 -#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 -#define QAM_SL_MODE_RADIUS_MIX_OFF 0x0 -#define QAM_SL_MODE_RADIUS_MIX_RADMIX 0x200 - -#define QAM_SL_MODE_TILT_COMP__B 10 -#define QAM_SL_MODE_TILT_COMP__W 1 -#define QAM_SL_MODE_TILT_COMP__M 0x400 -#define QAM_SL_MODE_TILT_COMP__PRE 0x0 -#define QAM_SL_MODE_TILT_COMP_OFF 0x0 -#define QAM_SL_MODE_TILT_COMP_TILTCOMP 0x400 - - -#define QAM_SL_K_FACTOR__A 0x1430011 -#define QAM_SL_K_FACTOR__W 4 -#define QAM_SL_K_FACTOR__M 0xF -#define QAM_SL_K_FACTOR__PRE 0xC -#define QAM_SL_MEDIAN__A 0x1430012 -#define QAM_SL_MEDIAN__W 14 -#define QAM_SL_MEDIAN__M 0x3FFF -#define QAM_SL_MEDIAN__PRE 0x2C86 - -#define QAM_SL_MEDIAN_LENGTH__B 0 -#define QAM_SL_MEDIAN_LENGTH__W 2 -#define QAM_SL_MEDIAN_LENGTH__M 0x3 -#define QAM_SL_MEDIAN_LENGTH__PRE 0x2 -#define QAM_SL_MEDIAN_LENGTH_MEDL1 0x0 -#define QAM_SL_MEDIAN_LENGTH_MEDL2 0x1 -#define QAM_SL_MEDIAN_LENGTH_MEDL4 0x2 -#define QAM_SL_MEDIAN_LENGTH_MEDL8 0x3 - -#define QAM_SL_MEDIAN_CORRECT__B 2 -#define QAM_SL_MEDIAN_CORRECT__W 4 -#define QAM_SL_MEDIAN_CORRECT__M 0x3C -#define QAM_SL_MEDIAN_CORRECT__PRE 0x4 - -#define QAM_SL_MEDIAN_TOLERANCE__B 6 -#define QAM_SL_MEDIAN_TOLERANCE__W 7 -#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 -#define QAM_SL_MEDIAN_TOLERANCE__PRE 0xC80 - -#define QAM_SL_MEDIAN_FAST__B 13 -#define QAM_SL_MEDIAN_FAST__W 1 -#define QAM_SL_MEDIAN_FAST__M 0x2000 -#define QAM_SL_MEDIAN_FAST__PRE 0x2000 -#define QAM_SL_MEDIAN_FAST_AVER 0x0 -#define QAM_SL_MEDIAN_FAST_LAST 0x2000 - - -#define QAM_SL_ALPHA__A 0x1430013 -#define QAM_SL_ALPHA__W 3 -#define QAM_SL_ALPHA__M 0x7 -#define QAM_SL_ALPHA__PRE 0x0 - -#define QAM_SL_PHASELIMIT__A 0x1430014 -#define QAM_SL_PHASELIMIT__W 9 -#define QAM_SL_PHASELIMIT__M 0x1FF -#define QAM_SL_PHASELIMIT__PRE 0x0 -#define QAM_SL_MTA_LENGTH__A 0x1430015 -#define QAM_SL_MTA_LENGTH__W 2 -#define QAM_SL_MTA_LENGTH__M 0x3 -#define QAM_SL_MTA_LENGTH__PRE 0x1 - -#define QAM_SL_MTA_LENGTH_LENGTH__B 0 -#define QAM_SL_MTA_LENGTH_LENGTH__W 2 -#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 -#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 - -#define QAM_SL_MEDIAN_ERROR__A 0x1430016 -#define QAM_SL_MEDIAN_ERROR__W 10 -#define QAM_SL_MEDIAN_ERROR__M 0x3FF -#define QAM_SL_MEDIAN_ERROR__PRE 0x0 - -#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 -#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 -#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF -#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 - - -#define QAM_SL_ERR_POWER__A 0x1430017 -#define QAM_SL_ERR_POWER__W 16 -#define QAM_SL_ERR_POWER__M 0xFFFF -#define QAM_SL_ERR_POWER__PRE 0x0 -#define QAM_SL_QUAL_QAM_4_0__A 0x1430018 -#define QAM_SL_QUAL_QAM_4_0__W 3 -#define QAM_SL_QUAL_QAM_4_0__M 0x7 -#define QAM_SL_QUAL_QAM_4_0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_4_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_4_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_4_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_4_0_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_8_0__A 0x1430019 -#define QAM_SL_QUAL_QAM_8_0__W 6 -#define QAM_SL_QUAL_QAM_8_0__M 0x3F -#define QAM_SL_QUAL_QAM_8_0__PRE 0xD - -#define QAM_SL_QUAL_QAM_8_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_8_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_8_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_8_0_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_8_0_Q1__B 3 -#define QAM_SL_QUAL_QAM_8_0_Q1__W 3 -#define QAM_SL_QUAL_QAM_8_0_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_8_0_Q1__PRE 0x8 - -#define QAM_SL_QUAL_QAM_16_0__A 0x143001A -#define QAM_SL_QUAL_QAM_16_0__W 3 -#define QAM_SL_QUAL_QAM_16_0__M 0x7 -#define QAM_SL_QUAL_QAM_16_0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_16_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_16_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_16_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_16_0_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_16_1__A 0x143001B -#define QAM_SL_QUAL_QAM_16_1__W 6 -#define QAM_SL_QUAL_QAM_16_1__M 0x3F -#define QAM_SL_QUAL_QAM_16_1__PRE 0x5 - -#define QAM_SL_QUAL_QAM_16_1_Q0__B 0 -#define QAM_SL_QUAL_QAM_16_1_Q0__W 3 -#define QAM_SL_QUAL_QAM_16_1_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_16_1_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_16_1_Q1__B 3 -#define QAM_SL_QUAL_QAM_16_1_Q1__W 3 -#define QAM_SL_QUAL_QAM_16_1_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_16_1_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_32_0__A 0x143001C -#define QAM_SL_QUAL_QAM_32_0__W 3 -#define QAM_SL_QUAL_QAM_32_0__M 0x7 -#define QAM_SL_QUAL_QAM_32_0__PRE 0x4 - -#define QAM_SL_QUAL_QAM_32_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_32_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_32_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_32_0_Q0__PRE 0x4 - -#define QAM_SL_QUAL_QAM_32_1__A 0x143001D -#define QAM_SL_QUAL_QAM_32_1__W 6 -#define QAM_SL_QUAL_QAM_32_1__M 0x3F -#define QAM_SL_QUAL_QAM_32_1__PRE 0x3 - -#define QAM_SL_QUAL_QAM_32_1_Q0__B 0 -#define QAM_SL_QUAL_QAM_32_1_Q0__W 3 -#define QAM_SL_QUAL_QAM_32_1_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_32_1_Q0__PRE 0x3 - -#define QAM_SL_QUAL_QAM_32_1_Q1__B 3 -#define QAM_SL_QUAL_QAM_32_1_Q1__W 3 -#define QAM_SL_QUAL_QAM_32_1_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_32_1_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_32_2__A 0x143001E -#define QAM_SL_QUAL_QAM_32_2__W 9 -#define QAM_SL_QUAL_QAM_32_2__M 0x1FF -#define QAM_SL_QUAL_QAM_32_2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_32_2_Q0__B 0 -#define QAM_SL_QUAL_QAM_32_2_Q0__W 3 -#define QAM_SL_QUAL_QAM_32_2_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_32_2_Q0__PRE 0x0 - -#define QAM_SL_QUAL_QAM_32_2_Q1__B 3 -#define QAM_SL_QUAL_QAM_32_2_Q1__W 3 -#define QAM_SL_QUAL_QAM_32_2_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_32_2_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_32_2_Q2__B 6 -#define QAM_SL_QUAL_QAM_32_2_Q2__W 3 -#define QAM_SL_QUAL_QAM_32_2_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_32_2_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_64_0__A 0x143001F -#define QAM_SL_QUAL_QAM_64_0__W 3 -#define QAM_SL_QUAL_QAM_64_0__M 0x7 -#define QAM_SL_QUAL_QAM_64_0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_64_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_64_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_64_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_64_0_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_64_1__A 0x1430020 -#define QAM_SL_QUAL_QAM_64_1__W 6 -#define QAM_SL_QUAL_QAM_64_1__M 0x3F -#define QAM_SL_QUAL_QAM_64_1__PRE 0x2 - -#define QAM_SL_QUAL_QAM_64_1_Q0__B 0 -#define QAM_SL_QUAL_QAM_64_1_Q0__W 3 -#define QAM_SL_QUAL_QAM_64_1_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_64_1_Q0__PRE 0x2 - -#define QAM_SL_QUAL_QAM_64_1_Q1__B 3 -#define QAM_SL_QUAL_QAM_64_1_Q1__W 3 -#define QAM_SL_QUAL_QAM_64_1_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_64_1_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_64_2__A 0x1430021 -#define QAM_SL_QUAL_QAM_64_2__W 9 -#define QAM_SL_QUAL_QAM_64_2__M 0x1FF -#define QAM_SL_QUAL_QAM_64_2__PRE 0x9 - -#define QAM_SL_QUAL_QAM_64_2_Q0__B 0 -#define QAM_SL_QUAL_QAM_64_2_Q0__W 3 -#define QAM_SL_QUAL_QAM_64_2_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_64_2_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_64_2_Q1__B 3 -#define QAM_SL_QUAL_QAM_64_2_Q1__W 3 -#define QAM_SL_QUAL_QAM_64_2_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_64_2_Q1__PRE 0x8 - -#define QAM_SL_QUAL_QAM_64_2_Q2__B 6 -#define QAM_SL_QUAL_QAM_64_2_Q2__W 3 -#define QAM_SL_QUAL_QAM_64_2_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_64_2_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_64_3__A 0x1430022 -#define QAM_SL_QUAL_QAM_64_3__W 12 -#define QAM_SL_QUAL_QAM_64_3__M 0xFFF -#define QAM_SL_QUAL_QAM_64_3__PRE 0xD - -#define QAM_SL_QUAL_QAM_64_3_Q0__B 0 -#define QAM_SL_QUAL_QAM_64_3_Q0__W 3 -#define QAM_SL_QUAL_QAM_64_3_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_64_3_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_64_3_Q1__B 3 -#define QAM_SL_QUAL_QAM_64_3_Q1__W 3 -#define QAM_SL_QUAL_QAM_64_3_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_64_3_Q1__PRE 0x8 - -#define QAM_SL_QUAL_QAM_64_3_Q2__B 6 -#define QAM_SL_QUAL_QAM_64_3_Q2__W 3 -#define QAM_SL_QUAL_QAM_64_3_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_64_3_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_64_3_Q3__B 9 -#define QAM_SL_QUAL_QAM_64_3_Q3__W 3 -#define QAM_SL_QUAL_QAM_64_3_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_64_3_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_0__A 0x1430023 -#define QAM_SL_QUAL_QAM_128_0__W 3 -#define QAM_SL_QUAL_QAM_128_0__M 0x7 -#define QAM_SL_QUAL_QAM_128_0__PRE 0x4 - -#define QAM_SL_QUAL_QAM_128_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_0_Q0__PRE 0x4 - -#define QAM_SL_QUAL_QAM_128_1__A 0x1430024 -#define QAM_SL_QUAL_QAM_128_1__W 6 -#define QAM_SL_QUAL_QAM_128_1__M 0x3F -#define QAM_SL_QUAL_QAM_128_1__PRE 0x5 - -#define QAM_SL_QUAL_QAM_128_1_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_1_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_1_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_1_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_128_1_Q1__B 3 -#define QAM_SL_QUAL_QAM_128_1_Q1__W 3 -#define QAM_SL_QUAL_QAM_128_1_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_128_1_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_2__A 0x1430025 -#define QAM_SL_QUAL_QAM_128_2__W 9 -#define QAM_SL_QUAL_QAM_128_2__M 0x1FF -#define QAM_SL_QUAL_QAM_128_2__PRE 0x1 - -#define QAM_SL_QUAL_QAM_128_2_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_2_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_2_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_2_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_128_2_Q1__B 3 -#define QAM_SL_QUAL_QAM_128_2_Q1__W 3 -#define QAM_SL_QUAL_QAM_128_2_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_128_2_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_2_Q2__B 6 -#define QAM_SL_QUAL_QAM_128_2_Q2__W 3 -#define QAM_SL_QUAL_QAM_128_2_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_128_2_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_3__A 0x1430026 -#define QAM_SL_QUAL_QAM_128_3__W 12 -#define QAM_SL_QUAL_QAM_128_3__M 0xFFF -#define QAM_SL_QUAL_QAM_128_3__PRE 0x1 - -#define QAM_SL_QUAL_QAM_128_3_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_3_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_3_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_3_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_128_3_Q1__B 3 -#define QAM_SL_QUAL_QAM_128_3_Q1__W 3 -#define QAM_SL_QUAL_QAM_128_3_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_128_3_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_3_Q2__B 6 -#define QAM_SL_QUAL_QAM_128_3_Q2__W 3 -#define QAM_SL_QUAL_QAM_128_3_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_128_3_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_3_Q3__B 9 -#define QAM_SL_QUAL_QAM_128_3_Q3__W 3 -#define QAM_SL_QUAL_QAM_128_3_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_128_3_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4__A 0x1430027 -#define QAM_SL_QUAL_QAM_128_4__W 15 -#define QAM_SL_QUAL_QAM_128_4__M 0x7FFF -#define QAM_SL_QUAL_QAM_128_4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_4_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_4_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_4_Q0__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4_Q1__B 3 -#define QAM_SL_QUAL_QAM_128_4_Q1__W 3 -#define QAM_SL_QUAL_QAM_128_4_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_128_4_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4_Q2__B 6 -#define QAM_SL_QUAL_QAM_128_4_Q2__W 3 -#define QAM_SL_QUAL_QAM_128_4_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_128_4_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4_Q3__B 9 -#define QAM_SL_QUAL_QAM_128_4_Q3__W 3 -#define QAM_SL_QUAL_QAM_128_4_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_128_4_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4_Q4__B 12 -#define QAM_SL_QUAL_QAM_128_4_Q4__W 3 -#define QAM_SL_QUAL_QAM_128_4_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_128_4_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_5__A 0x1430028 -#define QAM_SL_QUAL_QAM_128_5__W 15 -#define QAM_SL_QUAL_QAM_128_5__M 0x7FFF -#define QAM_SL_QUAL_QAM_128_5__PRE 0x90 - -#define QAM_SL_QUAL_QAM_128_5_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_5_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_5_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_5_Q0__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_5_Q1__B 3 -#define QAM_SL_QUAL_QAM_128_5_Q1__W 3 -#define QAM_SL_QUAL_QAM_128_5_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_128_5_Q1__PRE 0x10 - -#define QAM_SL_QUAL_QAM_128_5_Q2__B 6 -#define QAM_SL_QUAL_QAM_128_5_Q2__W 3 -#define QAM_SL_QUAL_QAM_128_5_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_128_5_Q2__PRE 0x80 - -#define QAM_SL_QUAL_QAM_128_5_Q3__B 9 -#define QAM_SL_QUAL_QAM_128_5_Q3__W 3 -#define QAM_SL_QUAL_QAM_128_5_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_128_5_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_5_Q4__B 12 -#define QAM_SL_QUAL_QAM_128_5_Q4__W 3 -#define QAM_SL_QUAL_QAM_128_5_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_128_5_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_5H__A 0x1430029 -#define QAM_SL_QUAL_QAM_128_5H__W 3 -#define QAM_SL_QUAL_QAM_128_5H__M 0x7 -#define QAM_SL_QUAL_QAM_128_5H__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_5H_Q5__B 0 -#define QAM_SL_QUAL_QAM_128_5H_Q5__W 3 -#define QAM_SL_QUAL_QAM_128_5H_Q5__M 0x7 -#define QAM_SL_QUAL_QAM_128_5H_Q5__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_0__A 0x143002A -#define QAM_SL_QUAL_QAM_256_0__W 3 -#define QAM_SL_QUAL_QAM_256_0__M 0x7 -#define QAM_SL_QUAL_QAM_256_0__PRE 0x3 - -#define QAM_SL_QUAL_QAM_256_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_0_Q0__PRE 0x3 - -#define QAM_SL_QUAL_QAM_256_1__A 0x143002B -#define QAM_SL_QUAL_QAM_256_1__W 6 -#define QAM_SL_QUAL_QAM_256_1__M 0x3F -#define QAM_SL_QUAL_QAM_256_1__PRE 0x1 - -#define QAM_SL_QUAL_QAM_256_1_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_1_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_1_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_1_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_256_1_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_1_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_1_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_1_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_2__A 0x143002C -#define QAM_SL_QUAL_QAM_256_2__W 9 -#define QAM_SL_QUAL_QAM_256_2__M 0x1FF -#define QAM_SL_QUAL_QAM_256_2__PRE 0x9 - -#define QAM_SL_QUAL_QAM_256_2_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_2_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_2_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_2_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_256_2_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_2_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_2_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_2_Q1__PRE 0x8 - -#define QAM_SL_QUAL_QAM_256_2_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_2_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_2_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_2_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_3__A 0x143002D -#define QAM_SL_QUAL_QAM_256_3__W 12 -#define QAM_SL_QUAL_QAM_256_3__M 0xFFF -#define QAM_SL_QUAL_QAM_256_3__PRE 0x13 - -#define QAM_SL_QUAL_QAM_256_3_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_3_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_3_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_3_Q0__PRE 0x3 - -#define QAM_SL_QUAL_QAM_256_3_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_3_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_3_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_3_Q1__PRE 0x10 - -#define QAM_SL_QUAL_QAM_256_3_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_3_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_3_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_3_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_3_Q3__B 9 -#define QAM_SL_QUAL_QAM_256_3_Q3__W 3 -#define QAM_SL_QUAL_QAM_256_3_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_256_3_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_4__A 0x143002E -#define QAM_SL_QUAL_QAM_256_4__W 15 -#define QAM_SL_QUAL_QAM_256_4__M 0x7FFF -#define QAM_SL_QUAL_QAM_256_4__PRE 0x49 - -#define QAM_SL_QUAL_QAM_256_4_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_4_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_4_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_4_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_256_4_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_4_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_4_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_4_Q1__PRE 0x8 - -#define QAM_SL_QUAL_QAM_256_4_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_4_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_4_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_4_Q2__PRE 0x40 - -#define QAM_SL_QUAL_QAM_256_4_Q3__B 9 -#define QAM_SL_QUAL_QAM_256_4_Q3__W 3 -#define QAM_SL_QUAL_QAM_256_4_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_256_4_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_4_Q4__B 12 -#define QAM_SL_QUAL_QAM_256_4_Q4__W 3 -#define QAM_SL_QUAL_QAM_256_4_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_256_4_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_5__A 0x143002F -#define QAM_SL_QUAL_QAM_256_5__W 15 -#define QAM_SL_QUAL_QAM_256_5__M 0x7FFF -#define QAM_SL_QUAL_QAM_256_5__PRE 0x59 - -#define QAM_SL_QUAL_QAM_256_5_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_5_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_5_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_5_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_256_5_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_5_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_5_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_5_Q1__PRE 0x18 - -#define QAM_SL_QUAL_QAM_256_5_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_5_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_5_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_5_Q2__PRE 0x40 - -#define QAM_SL_QUAL_QAM_256_5_Q3__B 9 -#define QAM_SL_QUAL_QAM_256_5_Q3__W 3 -#define QAM_SL_QUAL_QAM_256_5_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_256_5_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_5_Q4__B 12 -#define QAM_SL_QUAL_QAM_256_5_Q4__W 3 -#define QAM_SL_QUAL_QAM_256_5_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_256_5_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_5H__A 0x1430030 -#define QAM_SL_QUAL_QAM_256_5H__W 3 -#define QAM_SL_QUAL_QAM_256_5H__M 0x7 -#define QAM_SL_QUAL_QAM_256_5H__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_5H_Q5__B 0 -#define QAM_SL_QUAL_QAM_256_5H_Q5__W 3 -#define QAM_SL_QUAL_QAM_256_5H_Q5__M 0x7 -#define QAM_SL_QUAL_QAM_256_5H_Q5__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_6__A 0x1430031 -#define QAM_SL_QUAL_QAM_256_6__W 15 -#define QAM_SL_QUAL_QAM_256_6__M 0x7FFF -#define QAM_SL_QUAL_QAM_256_6__PRE 0x21A - -#define QAM_SL_QUAL_QAM_256_6_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_6_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_6_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_6_Q0__PRE 0x2 - -#define QAM_SL_QUAL_QAM_256_6_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_6_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_6_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_6_Q1__PRE 0x18 - -#define QAM_SL_QUAL_QAM_256_6_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_6_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_6_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_6_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_6_Q3__B 9 -#define QAM_SL_QUAL_QAM_256_6_Q3__W 3 -#define QAM_SL_QUAL_QAM_256_6_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_256_6_Q3__PRE 0x200 - -#define QAM_SL_QUAL_QAM_256_6_Q4__B 12 -#define QAM_SL_QUAL_QAM_256_6_Q4__W 3 -#define QAM_SL_QUAL_QAM_256_6_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_256_6_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_6H__A 0x1430032 -#define QAM_SL_QUAL_QAM_256_6H__W 6 -#define QAM_SL_QUAL_QAM_256_6H__M 0x3F -#define QAM_SL_QUAL_QAM_256_6H__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_6H_Q5__B 0 -#define QAM_SL_QUAL_QAM_256_6H_Q5__W 3 -#define QAM_SL_QUAL_QAM_256_6H_Q5__M 0x7 -#define QAM_SL_QUAL_QAM_256_6H_Q5__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_6H_Q6__B 3 -#define QAM_SL_QUAL_QAM_256_6H_Q6__W 3 -#define QAM_SL_QUAL_QAM_256_6H_Q6__M 0x38 -#define QAM_SL_QUAL_QAM_256_6H_Q6__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_7__A 0x1430033 -#define QAM_SL_QUAL_QAM_256_7__W 15 -#define QAM_SL_QUAL_QAM_256_7__M 0x7FFF -#define QAM_SL_QUAL_QAM_256_7__PRE 0x29D - -#define QAM_SL_QUAL_QAM_256_7_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_7_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_7_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_7_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_256_7_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_7_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_7_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_7_Q1__PRE 0x18 - -#define QAM_SL_QUAL_QAM_256_7_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_7_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_7_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_7_Q2__PRE 0x80 - -#define QAM_SL_QUAL_QAM_256_7_Q3__B 9 -#define QAM_SL_QUAL_QAM_256_7_Q3__W 3 -#define QAM_SL_QUAL_QAM_256_7_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_256_7_Q3__PRE 0x200 - -#define QAM_SL_QUAL_QAM_256_7_Q4__B 12 -#define QAM_SL_QUAL_QAM_256_7_Q4__W 3 -#define QAM_SL_QUAL_QAM_256_7_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_256_7_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_7H__A 0x1430034 -#define QAM_SL_QUAL_QAM_256_7H__W 9 -#define QAM_SL_QUAL_QAM_256_7H__M 0x1FF -#define QAM_SL_QUAL_QAM_256_7H__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_7H_Q5__B 0 -#define QAM_SL_QUAL_QAM_256_7H_Q5__W 3 -#define QAM_SL_QUAL_QAM_256_7H_Q5__M 0x7 -#define QAM_SL_QUAL_QAM_256_7H_Q5__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_7H_Q6__B 3 -#define QAM_SL_QUAL_QAM_256_7H_Q6__W 3 -#define QAM_SL_QUAL_QAM_256_7H_Q6__M 0x38 -#define QAM_SL_QUAL_QAM_256_7H_Q6__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_7H_Q7__B 6 -#define QAM_SL_QUAL_QAM_256_7H_Q7__W 3 -#define QAM_SL_QUAL_QAM_256_7H_Q7__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_7H_Q7__PRE 0x0 - - - -#define QAM_DQ_COMM_EXEC__A 0x1440000 -#define QAM_DQ_COMM_EXEC__W 2 -#define QAM_DQ_COMM_EXEC__M 0x3 -#define QAM_DQ_COMM_EXEC__PRE 0x0 -#define QAM_DQ_COMM_EXEC_STOP 0x0 -#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 -#define QAM_DQ_COMM_EXEC_HOLD 0x2 - -#define QAM_DQ_MODE__A 0x1440010 -#define QAM_DQ_MODE__W 5 -#define QAM_DQ_MODE__M 0x1F -#define QAM_DQ_MODE__PRE 0x0 - -#define QAM_DQ_MODE_TAPRESET__B 0 -#define QAM_DQ_MODE_TAPRESET__W 1 -#define QAM_DQ_MODE_TAPRESET__M 0x1 -#define QAM_DQ_MODE_TAPRESET__PRE 0x0 -#define QAM_DQ_MODE_TAPRESET_RST 0x1 - -#define QAM_DQ_MODE_TAPLMS__B 1 -#define QAM_DQ_MODE_TAPLMS__W 1 -#define QAM_DQ_MODE_TAPLMS__M 0x2 -#define QAM_DQ_MODE_TAPLMS__PRE 0x0 -#define QAM_DQ_MODE_TAPLMS_UPD 0x2 - -#define QAM_DQ_MODE_TAPDRAIN__B 2 -#define QAM_DQ_MODE_TAPDRAIN__W 1 -#define QAM_DQ_MODE_TAPDRAIN__M 0x4 -#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 -#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 - -#define QAM_DQ_MODE_FB__B 3 -#define QAM_DQ_MODE_FB__W 2 -#define QAM_DQ_MODE_FB__M 0x18 -#define QAM_DQ_MODE_FB__PRE 0x0 -#define QAM_DQ_MODE_FB_CMA 0x0 -#define QAM_DQ_MODE_FB_RADIUS 0x8 -#define QAM_DQ_MODE_FB_DFB 0x10 -#define QAM_DQ_MODE_FB_TRELLIS 0x18 - - -#define QAM_DQ_MU_FACTOR__A 0x1440011 -#define QAM_DQ_MU_FACTOR__W 3 -#define QAM_DQ_MU_FACTOR__M 0x7 -#define QAM_DQ_MU_FACTOR__PRE 0x0 - -#define QAM_DQ_LA_FACTOR__A 0x1440012 -#define QAM_DQ_LA_FACTOR__W 4 -#define QAM_DQ_LA_FACTOR__M 0xF -#define QAM_DQ_LA_FACTOR__PRE 0xC - -#define QAM_DQ_CMA_RATIO__A 0x1440013 -#define QAM_DQ_CMA_RATIO__W 14 -#define QAM_DQ_CMA_RATIO__M 0x3FFF -#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 -#define QAM_DQ_CMA_RATIO_QPSK 0x2000 -#define QAM_DQ_CMA_RATIO_QAM16 0x34CD -#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 -#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D -#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 - -#define QAM_DQ_QUAL_RADSEL__A 0x1440014 -#define QAM_DQ_QUAL_RADSEL__W 3 -#define QAM_DQ_QUAL_RADSEL__M 0x7 -#define QAM_DQ_QUAL_RADSEL__PRE 0x0 - -#define QAM_DQ_QUAL_RADSEL_BIT__B 0 -#define QAM_DQ_QUAL_RADSEL_BIT__W 3 -#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 -#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 -#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 -#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 - -#define QAM_DQ_QUAL_ENA__A 0x1440015 -#define QAM_DQ_QUAL_ENA__W 1 -#define QAM_DQ_QUAL_ENA__M 0x1 -#define QAM_DQ_QUAL_ENA__PRE 0x0 - -#define QAM_DQ_QUAL_ENA_ENA__B 0 -#define QAM_DQ_QUAL_ENA_ENA__W 1 -#define QAM_DQ_QUAL_ENA_ENA__M 0x1 -#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 -#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 - -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__PRE 0x4 - -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 - -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__PRE 0x4 - -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 - -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__PRE 0x4 - -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 - -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__PRE 0x4 - -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 - -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__PRE 0x6 - -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 - -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__PRE 0x6 - -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 - -#define QAM_DQ_RAW_LIM__A 0x144001E -#define QAM_DQ_RAW_LIM__W 5 -#define QAM_DQ_RAW_LIM__M 0x1F -#define QAM_DQ_RAW_LIM__PRE 0x1F - -#define QAM_DQ_RAW_LIM_BIT__B 0 -#define QAM_DQ_RAW_LIM_BIT__W 5 -#define QAM_DQ_RAW_LIM_BIT__M 0x1F -#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F - -#define QAM_DQ_TAP_RE_EL0__A 0x1440020 -#define QAM_DQ_TAP_RE_EL0__W 12 -#define QAM_DQ_TAP_RE_EL0__M 0xFFF -#define QAM_DQ_TAP_RE_EL0__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL0_TAP__B 0 -#define QAM_DQ_TAP_RE_EL0_TAP__W 12 -#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL0__A 0x1440021 -#define QAM_DQ_TAP_IM_EL0__W 12 -#define QAM_DQ_TAP_IM_EL0__M 0xFFF -#define QAM_DQ_TAP_IM_EL0__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL0_TAP__B 0 -#define QAM_DQ_TAP_IM_EL0_TAP__W 12 -#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL1__A 0x1440022 -#define QAM_DQ_TAP_RE_EL1__W 12 -#define QAM_DQ_TAP_RE_EL1__M 0xFFF -#define QAM_DQ_TAP_RE_EL1__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL1_TAP__B 0 -#define QAM_DQ_TAP_RE_EL1_TAP__W 12 -#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL1__A 0x1440023 -#define QAM_DQ_TAP_IM_EL1__W 12 -#define QAM_DQ_TAP_IM_EL1__M 0xFFF -#define QAM_DQ_TAP_IM_EL1__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL1_TAP__B 0 -#define QAM_DQ_TAP_IM_EL1_TAP__W 12 -#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL2__A 0x1440024 -#define QAM_DQ_TAP_RE_EL2__W 12 -#define QAM_DQ_TAP_RE_EL2__M 0xFFF -#define QAM_DQ_TAP_RE_EL2__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL2_TAP__B 0 -#define QAM_DQ_TAP_RE_EL2_TAP__W 12 -#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL2__A 0x1440025 -#define QAM_DQ_TAP_IM_EL2__W 12 -#define QAM_DQ_TAP_IM_EL2__M 0xFFF -#define QAM_DQ_TAP_IM_EL2__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL2_TAP__B 0 -#define QAM_DQ_TAP_IM_EL2_TAP__W 12 -#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL3__A 0x1440026 -#define QAM_DQ_TAP_RE_EL3__W 12 -#define QAM_DQ_TAP_RE_EL3__M 0xFFF -#define QAM_DQ_TAP_RE_EL3__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL3_TAP__B 0 -#define QAM_DQ_TAP_RE_EL3_TAP__W 12 -#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL3__A 0x1440027 -#define QAM_DQ_TAP_IM_EL3__W 12 -#define QAM_DQ_TAP_IM_EL3__M 0xFFF -#define QAM_DQ_TAP_IM_EL3__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL3_TAP__B 0 -#define QAM_DQ_TAP_IM_EL3_TAP__W 12 -#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL4__A 0x1440028 -#define QAM_DQ_TAP_RE_EL4__W 12 -#define QAM_DQ_TAP_RE_EL4__M 0xFFF -#define QAM_DQ_TAP_RE_EL4__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL4_TAP__B 0 -#define QAM_DQ_TAP_RE_EL4_TAP__W 12 -#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL4__A 0x1440029 -#define QAM_DQ_TAP_IM_EL4__W 12 -#define QAM_DQ_TAP_IM_EL4__M 0xFFF -#define QAM_DQ_TAP_IM_EL4__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL4_TAP__B 0 -#define QAM_DQ_TAP_IM_EL4_TAP__W 12 -#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL5__A 0x144002A -#define QAM_DQ_TAP_RE_EL5__W 12 -#define QAM_DQ_TAP_RE_EL5__M 0xFFF -#define QAM_DQ_TAP_RE_EL5__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL5_TAP__B 0 -#define QAM_DQ_TAP_RE_EL5_TAP__W 12 -#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL5__A 0x144002B -#define QAM_DQ_TAP_IM_EL5__W 12 -#define QAM_DQ_TAP_IM_EL5__M 0xFFF -#define QAM_DQ_TAP_IM_EL5__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL5_TAP__B 0 -#define QAM_DQ_TAP_IM_EL5_TAP__W 12 -#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL6__A 0x144002C -#define QAM_DQ_TAP_RE_EL6__W 12 -#define QAM_DQ_TAP_RE_EL6__M 0xFFF -#define QAM_DQ_TAP_RE_EL6__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL6_TAP__B 0 -#define QAM_DQ_TAP_RE_EL6_TAP__W 12 -#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL6__A 0x144002D -#define QAM_DQ_TAP_IM_EL6__W 12 -#define QAM_DQ_TAP_IM_EL6__M 0xFFF -#define QAM_DQ_TAP_IM_EL6__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL6_TAP__B 0 -#define QAM_DQ_TAP_IM_EL6_TAP__W 12 -#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL7__A 0x144002E -#define QAM_DQ_TAP_RE_EL7__W 12 -#define QAM_DQ_TAP_RE_EL7__M 0xFFF -#define QAM_DQ_TAP_RE_EL7__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL7_TAP__B 0 -#define QAM_DQ_TAP_RE_EL7_TAP__W 12 -#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL7__A 0x144002F -#define QAM_DQ_TAP_IM_EL7__W 12 -#define QAM_DQ_TAP_IM_EL7__M 0xFFF -#define QAM_DQ_TAP_IM_EL7__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL7_TAP__B 0 -#define QAM_DQ_TAP_IM_EL7_TAP__W 12 -#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL8__A 0x1440030 -#define QAM_DQ_TAP_RE_EL8__W 12 -#define QAM_DQ_TAP_RE_EL8__M 0xFFF -#define QAM_DQ_TAP_RE_EL8__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL8_TAP__B 0 -#define QAM_DQ_TAP_RE_EL8_TAP__W 12 -#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL8__A 0x1440031 -#define QAM_DQ_TAP_IM_EL8__W 12 -#define QAM_DQ_TAP_IM_EL8__M 0xFFF -#define QAM_DQ_TAP_IM_EL8__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL8_TAP__B 0 -#define QAM_DQ_TAP_IM_EL8_TAP__W 12 -#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL9__A 0x1440032 -#define QAM_DQ_TAP_RE_EL9__W 12 -#define QAM_DQ_TAP_RE_EL9__M 0xFFF -#define QAM_DQ_TAP_RE_EL9__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL9_TAP__B 0 -#define QAM_DQ_TAP_RE_EL9_TAP__W 12 -#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL9__A 0x1440033 -#define QAM_DQ_TAP_IM_EL9__W 12 -#define QAM_DQ_TAP_IM_EL9__M 0xFFF -#define QAM_DQ_TAP_IM_EL9__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL9_TAP__B 0 -#define QAM_DQ_TAP_IM_EL9_TAP__W 12 -#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL10__A 0x1440034 -#define QAM_DQ_TAP_RE_EL10__W 12 -#define QAM_DQ_TAP_RE_EL10__M 0xFFF -#define QAM_DQ_TAP_RE_EL10__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL10_TAP__B 0 -#define QAM_DQ_TAP_RE_EL10_TAP__W 12 -#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL10__A 0x1440035 -#define QAM_DQ_TAP_IM_EL10__W 12 -#define QAM_DQ_TAP_IM_EL10__M 0xFFF -#define QAM_DQ_TAP_IM_EL10__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL10_TAP__B 0 -#define QAM_DQ_TAP_IM_EL10_TAP__W 12 -#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL11__A 0x1440036 -#define QAM_DQ_TAP_RE_EL11__W 12 -#define QAM_DQ_TAP_RE_EL11__M 0xFFF -#define QAM_DQ_TAP_RE_EL11__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL11_TAP__B 0 -#define QAM_DQ_TAP_RE_EL11_TAP__W 12 -#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL11__A 0x1440037 -#define QAM_DQ_TAP_IM_EL11__W 12 -#define QAM_DQ_TAP_IM_EL11__M 0xFFF -#define QAM_DQ_TAP_IM_EL11__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL11_TAP__B 0 -#define QAM_DQ_TAP_IM_EL11_TAP__W 12 -#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL12__A 0x1440038 -#define QAM_DQ_TAP_RE_EL12__W 12 -#define QAM_DQ_TAP_RE_EL12__M 0xFFF -#define QAM_DQ_TAP_RE_EL12__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL12_TAP__B 0 -#define QAM_DQ_TAP_RE_EL12_TAP__W 12 -#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL12__A 0x1440039 -#define QAM_DQ_TAP_IM_EL12__W 12 -#define QAM_DQ_TAP_IM_EL12__M 0xFFF -#define QAM_DQ_TAP_IM_EL12__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL12_TAP__B 0 -#define QAM_DQ_TAP_IM_EL12_TAP__W 12 -#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL13__A 0x144003A -#define QAM_DQ_TAP_RE_EL13__W 12 -#define QAM_DQ_TAP_RE_EL13__M 0xFFF -#define QAM_DQ_TAP_RE_EL13__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL13_TAP__B 0 -#define QAM_DQ_TAP_RE_EL13_TAP__W 12 -#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL13__A 0x144003B -#define QAM_DQ_TAP_IM_EL13__W 12 -#define QAM_DQ_TAP_IM_EL13__M 0xFFF -#define QAM_DQ_TAP_IM_EL13__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL13_TAP__B 0 -#define QAM_DQ_TAP_IM_EL13_TAP__W 12 -#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL14__A 0x144003C -#define QAM_DQ_TAP_RE_EL14__W 12 -#define QAM_DQ_TAP_RE_EL14__M 0xFFF -#define QAM_DQ_TAP_RE_EL14__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL14_TAP__B 0 -#define QAM_DQ_TAP_RE_EL14_TAP__W 12 -#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL14__A 0x144003D -#define QAM_DQ_TAP_IM_EL14__W 12 -#define QAM_DQ_TAP_IM_EL14__M 0xFFF -#define QAM_DQ_TAP_IM_EL14__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL14_TAP__B 0 -#define QAM_DQ_TAP_IM_EL14_TAP__W 12 -#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL15__A 0x144003E -#define QAM_DQ_TAP_RE_EL15__W 12 -#define QAM_DQ_TAP_RE_EL15__M 0xFFF -#define QAM_DQ_TAP_RE_EL15__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL15_TAP__B 0 -#define QAM_DQ_TAP_RE_EL15_TAP__W 12 -#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL15__A 0x144003F -#define QAM_DQ_TAP_IM_EL15__W 12 -#define QAM_DQ_TAP_IM_EL15__M 0xFFF -#define QAM_DQ_TAP_IM_EL15__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL15_TAP__B 0 -#define QAM_DQ_TAP_IM_EL15_TAP__W 12 -#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL16__A 0x1440040 -#define QAM_DQ_TAP_RE_EL16__W 12 -#define QAM_DQ_TAP_RE_EL16__M 0xFFF -#define QAM_DQ_TAP_RE_EL16__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL16_TAP__B 0 -#define QAM_DQ_TAP_RE_EL16_TAP__W 12 -#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL16__A 0x1440041 -#define QAM_DQ_TAP_IM_EL16__W 12 -#define QAM_DQ_TAP_IM_EL16__M 0xFFF -#define QAM_DQ_TAP_IM_EL16__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL16_TAP__B 0 -#define QAM_DQ_TAP_IM_EL16_TAP__W 12 -#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL17__A 0x1440042 -#define QAM_DQ_TAP_RE_EL17__W 12 -#define QAM_DQ_TAP_RE_EL17__M 0xFFF -#define QAM_DQ_TAP_RE_EL17__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL17_TAP__B 0 -#define QAM_DQ_TAP_RE_EL17_TAP__W 12 -#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL17__A 0x1440043 -#define QAM_DQ_TAP_IM_EL17__W 12 -#define QAM_DQ_TAP_IM_EL17__M 0xFFF -#define QAM_DQ_TAP_IM_EL17__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL17_TAP__B 0 -#define QAM_DQ_TAP_IM_EL17_TAP__W 12 -#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL18__A 0x1440044 -#define QAM_DQ_TAP_RE_EL18__W 12 -#define QAM_DQ_TAP_RE_EL18__M 0xFFF -#define QAM_DQ_TAP_RE_EL18__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL18_TAP__B 0 -#define QAM_DQ_TAP_RE_EL18_TAP__W 12 -#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL18__A 0x1440045 -#define QAM_DQ_TAP_IM_EL18__W 12 -#define QAM_DQ_TAP_IM_EL18__M 0xFFF -#define QAM_DQ_TAP_IM_EL18__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL18_TAP__B 0 -#define QAM_DQ_TAP_IM_EL18_TAP__W 12 -#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL19__A 0x1440046 -#define QAM_DQ_TAP_RE_EL19__W 12 -#define QAM_DQ_TAP_RE_EL19__M 0xFFF -#define QAM_DQ_TAP_RE_EL19__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL19_TAP__B 0 -#define QAM_DQ_TAP_RE_EL19_TAP__W 12 -#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL19__A 0x1440047 -#define QAM_DQ_TAP_IM_EL19__W 12 -#define QAM_DQ_TAP_IM_EL19__M 0xFFF -#define QAM_DQ_TAP_IM_EL19__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL19_TAP__B 0 -#define QAM_DQ_TAP_IM_EL19_TAP__W 12 -#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL20__A 0x1440048 -#define QAM_DQ_TAP_RE_EL20__W 12 -#define QAM_DQ_TAP_RE_EL20__M 0xFFF -#define QAM_DQ_TAP_RE_EL20__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL20_TAP__B 0 -#define QAM_DQ_TAP_RE_EL20_TAP__W 12 -#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL20__A 0x1440049 -#define QAM_DQ_TAP_IM_EL20__W 12 -#define QAM_DQ_TAP_IM_EL20__M 0xFFF -#define QAM_DQ_TAP_IM_EL20__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL20_TAP__B 0 -#define QAM_DQ_TAP_IM_EL20_TAP__W 12 -#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL21__A 0x144004A -#define QAM_DQ_TAP_RE_EL21__W 12 -#define QAM_DQ_TAP_RE_EL21__M 0xFFF -#define QAM_DQ_TAP_RE_EL21__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL21_TAP__B 0 -#define QAM_DQ_TAP_RE_EL21_TAP__W 12 -#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL21__A 0x144004B -#define QAM_DQ_TAP_IM_EL21__W 12 -#define QAM_DQ_TAP_IM_EL21__M 0xFFF -#define QAM_DQ_TAP_IM_EL21__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL21_TAP__B 0 -#define QAM_DQ_TAP_IM_EL21_TAP__W 12 -#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL22__A 0x144004C -#define QAM_DQ_TAP_RE_EL22__W 12 -#define QAM_DQ_TAP_RE_EL22__M 0xFFF -#define QAM_DQ_TAP_RE_EL22__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL22_TAP__B 0 -#define QAM_DQ_TAP_RE_EL22_TAP__W 12 -#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL22__A 0x144004D -#define QAM_DQ_TAP_IM_EL22__W 12 -#define QAM_DQ_TAP_IM_EL22__M 0xFFF -#define QAM_DQ_TAP_IM_EL22__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL22_TAP__B 0 -#define QAM_DQ_TAP_IM_EL22_TAP__W 12 -#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL23__A 0x144004E -#define QAM_DQ_TAP_RE_EL23__W 12 -#define QAM_DQ_TAP_RE_EL23__M 0xFFF -#define QAM_DQ_TAP_RE_EL23__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL23_TAP__B 0 -#define QAM_DQ_TAP_RE_EL23_TAP__W 12 -#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL23__A 0x144004F -#define QAM_DQ_TAP_IM_EL23__W 12 -#define QAM_DQ_TAP_IM_EL23__M 0xFFF -#define QAM_DQ_TAP_IM_EL23__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL23_TAP__B 0 -#define QAM_DQ_TAP_IM_EL23_TAP__W 12 -#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL24__A 0x1440050 -#define QAM_DQ_TAP_RE_EL24__W 12 -#define QAM_DQ_TAP_RE_EL24__M 0xFFF -#define QAM_DQ_TAP_RE_EL24__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL24_TAP__B 0 -#define QAM_DQ_TAP_RE_EL24_TAP__W 12 -#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL24__A 0x1440051 -#define QAM_DQ_TAP_IM_EL24__W 12 -#define QAM_DQ_TAP_IM_EL24__M 0xFFF -#define QAM_DQ_TAP_IM_EL24__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL24_TAP__B 0 -#define QAM_DQ_TAP_IM_EL24_TAP__W 12 -#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL25__A 0x1440052 -#define QAM_DQ_TAP_RE_EL25__W 12 -#define QAM_DQ_TAP_RE_EL25__M 0xFFF -#define QAM_DQ_TAP_RE_EL25__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL25_TAP__B 0 -#define QAM_DQ_TAP_RE_EL25_TAP__W 12 -#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL25__A 0x1440053 -#define QAM_DQ_TAP_IM_EL25__W 12 -#define QAM_DQ_TAP_IM_EL25__M 0xFFF -#define QAM_DQ_TAP_IM_EL25__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL25_TAP__B 0 -#define QAM_DQ_TAP_IM_EL25_TAP__W 12 -#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL26__A 0x1440054 -#define QAM_DQ_TAP_RE_EL26__W 12 -#define QAM_DQ_TAP_RE_EL26__M 0xFFF -#define QAM_DQ_TAP_RE_EL26__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL26_TAP__B 0 -#define QAM_DQ_TAP_RE_EL26_TAP__W 12 -#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL26__A 0x1440055 -#define QAM_DQ_TAP_IM_EL26__W 12 -#define QAM_DQ_TAP_IM_EL26__M 0xFFF -#define QAM_DQ_TAP_IM_EL26__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL26_TAP__B 0 -#define QAM_DQ_TAP_IM_EL26_TAP__W 12 -#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL27__A 0x1440056 -#define QAM_DQ_TAP_RE_EL27__W 12 -#define QAM_DQ_TAP_RE_EL27__M 0xFFF -#define QAM_DQ_TAP_RE_EL27__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL27_TAP__B 0 -#define QAM_DQ_TAP_RE_EL27_TAP__W 12 -#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL27__A 0x1440057 -#define QAM_DQ_TAP_IM_EL27__W 12 -#define QAM_DQ_TAP_IM_EL27__M 0xFFF -#define QAM_DQ_TAP_IM_EL27__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL27_TAP__B 0 -#define QAM_DQ_TAP_IM_EL27_TAP__W 12 -#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 - - - -#define QAM_LC_COMM_EXEC__A 0x1450000 -#define QAM_LC_COMM_EXEC__W 2 -#define QAM_LC_COMM_EXEC__M 0x3 -#define QAM_LC_COMM_EXEC__PRE 0x0 -#define QAM_LC_COMM_EXEC_STOP 0x0 -#define QAM_LC_COMM_EXEC_ACTIVE 0x1 -#define QAM_LC_COMM_EXEC_HOLD 0x2 - -#define QAM_LC_COMM_MB__A 0x1450002 -#define QAM_LC_COMM_MB__W 2 -#define QAM_LC_COMM_MB__M 0x3 -#define QAM_LC_COMM_MB__PRE 0x0 -#define QAM_LC_COMM_MB_CTL__B 0 -#define QAM_LC_COMM_MB_CTL__W 1 -#define QAM_LC_COMM_MB_CTL__M 0x1 -#define QAM_LC_COMM_MB_CTL__PRE 0x0 -#define QAM_LC_COMM_MB_CTL_OFF 0x0 -#define QAM_LC_COMM_MB_CTL_ON 0x1 -#define QAM_LC_COMM_MB_OBS__B 1 -#define QAM_LC_COMM_MB_OBS__W 1 -#define QAM_LC_COMM_MB_OBS__M 0x2 -#define QAM_LC_COMM_MB_OBS__PRE 0x0 -#define QAM_LC_COMM_MB_OBS_OFF 0x0 -#define QAM_LC_COMM_MB_OBS_ON 0x2 - -#define QAM_LC_COMM_INT_REQ__A 0x1450003 -#define QAM_LC_COMM_INT_REQ__W 1 -#define QAM_LC_COMM_INT_REQ__M 0x1 -#define QAM_LC_COMM_INT_REQ__PRE 0x0 -#define QAM_LC_COMM_INT_STA__A 0x1450005 -#define QAM_LC_COMM_INT_STA__W 3 -#define QAM_LC_COMM_INT_STA__M 0x7 -#define QAM_LC_COMM_INT_STA__PRE 0x0 - -#define QAM_LC_COMM_INT_STA_READY__B 0 -#define QAM_LC_COMM_INT_STA_READY__W 1 -#define QAM_LC_COMM_INT_STA_READY__M 0x1 -#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 - -#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 -#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 -#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 -#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 - -#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 -#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 -#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 -#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 - -#define QAM_LC_COMM_INT_MSK__A 0x1450006 -#define QAM_LC_COMM_INT_MSK__W 3 -#define QAM_LC_COMM_INT_MSK__M 0x7 -#define QAM_LC_COMM_INT_MSK__PRE 0x0 -#define QAM_LC_COMM_INT_MSK_READY__B 0 -#define QAM_LC_COMM_INT_MSK_READY__W 1 -#define QAM_LC_COMM_INT_MSK_READY__M 0x1 -#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 -#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 -#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 -#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 -#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 -#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 -#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 -#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 -#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 - -#define QAM_LC_COMM_INT_STM__A 0x1450007 -#define QAM_LC_COMM_INT_STM__W 3 -#define QAM_LC_COMM_INT_STM__M 0x7 -#define QAM_LC_COMM_INT_STM__PRE 0x0 -#define QAM_LC_COMM_INT_STM_READY__B 0 -#define QAM_LC_COMM_INT_STM_READY__W 1 -#define QAM_LC_COMM_INT_STM_READY__M 0x1 -#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 -#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 -#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 -#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 -#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 -#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 -#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 -#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 -#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 - -#define QAM_LC_MODE__A 0x1450010 -#define QAM_LC_MODE__W 4 -#define QAM_LC_MODE__M 0xF -#define QAM_LC_MODE__PRE 0xE - -#define QAM_LC_MODE_ENABLE_A__B 0 -#define QAM_LC_MODE_ENABLE_A__W 1 -#define QAM_LC_MODE_ENABLE_A__M 0x1 -#define QAM_LC_MODE_ENABLE_A__PRE 0x0 - -#define QAM_LC_MODE_ENABLE_F__B 1 -#define QAM_LC_MODE_ENABLE_F__W 1 -#define QAM_LC_MODE_ENABLE_F__M 0x2 -#define QAM_LC_MODE_ENABLE_F__PRE 0x2 - -#define QAM_LC_MODE_ENABLE_R__B 2 -#define QAM_LC_MODE_ENABLE_R__W 1 -#define QAM_LC_MODE_ENABLE_R__M 0x4 -#define QAM_LC_MODE_ENABLE_R__PRE 0x4 - -#define QAM_LC_MODE_ENABLE_PQUAL__B 3 -#define QAM_LC_MODE_ENABLE_PQUAL__W 1 -#define QAM_LC_MODE_ENABLE_PQUAL__M 0x8 -#define QAM_LC_MODE_ENABLE_PQUAL__PRE 0x8 - -#define QAM_LC_CA__A 0x1450011 -#define QAM_LC_CA__W 6 -#define QAM_LC_CA__M 0x3F -#define QAM_LC_CA__PRE 0x28 - -#define QAM_LC_CA_COEF__B 0 -#define QAM_LC_CA_COEF__W 6 -#define QAM_LC_CA_COEF__M 0x3F -#define QAM_LC_CA_COEF__PRE 0x28 - -#define QAM_LC_CF__A 0x1450012 -#define QAM_LC_CF__W 8 -#define QAM_LC_CF__M 0xFF -#define QAM_LC_CF__PRE 0x30 - -#define QAM_LC_CF_COEF__B 0 -#define QAM_LC_CF_COEF__W 8 -#define QAM_LC_CF_COEF__M 0xFF -#define QAM_LC_CF_COEF__PRE 0x30 - -#define QAM_LC_CF1__A 0x1450013 -#define QAM_LC_CF1__W 8 -#define QAM_LC_CF1__M 0xFF -#define QAM_LC_CF1__PRE 0x14 - -#define QAM_LC_CF1_COEF__B 0 -#define QAM_LC_CF1_COEF__W 8 -#define QAM_LC_CF1_COEF__M 0xFF -#define QAM_LC_CF1_COEF__PRE 0x14 - -#define QAM_LC_CP__A 0x1450014 -#define QAM_LC_CP__W 8 -#define QAM_LC_CP__M 0xFF -#define QAM_LC_CP__PRE 0x64 - -#define QAM_LC_CP_COEF__B 0 -#define QAM_LC_CP_COEF__W 8 -#define QAM_LC_CP_COEF__M 0xFF -#define QAM_LC_CP_COEF__PRE 0x64 - -#define QAM_LC_CI__A 0x1450015 -#define QAM_LC_CI__W 8 -#define QAM_LC_CI__M 0xFF -#define QAM_LC_CI__PRE 0x32 - -#define QAM_LC_CI_COEF__B 0 -#define QAM_LC_CI_COEF__W 8 -#define QAM_LC_CI_COEF__M 0xFF -#define QAM_LC_CI_COEF__PRE 0x32 - -#define QAM_LC_EP__A 0x1450016 -#define QAM_LC_EP__W 6 -#define QAM_LC_EP__M 0x3F -#define QAM_LC_EP__PRE 0x0 - -#define QAM_LC_EP_COEF__B 0 -#define QAM_LC_EP_COEF__W 6 -#define QAM_LC_EP_COEF__M 0x3F -#define QAM_LC_EP_COEF__PRE 0x0 - -#define QAM_LC_EI__A 0x1450017 -#define QAM_LC_EI__W 6 -#define QAM_LC_EI__M 0x3F -#define QAM_LC_EI__PRE 0x0 - -#define QAM_LC_EI_COEF__B 0 -#define QAM_LC_EI_COEF__W 6 -#define QAM_LC_EI_COEF__M 0x3F -#define QAM_LC_EI_COEF__PRE 0x0 - -#define QAM_LC_QUAL_TAB0__A 0x1450018 -#define QAM_LC_QUAL_TAB0__W 5 -#define QAM_LC_QUAL_TAB0__M 0x1F -#define QAM_LC_QUAL_TAB0__PRE 0x0 - -#define QAM_LC_QUAL_TAB0_VALUE__B 0 -#define QAM_LC_QUAL_TAB0_VALUE__W 5 -#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 - -#define QAM_LC_QUAL_TAB1__A 0x1450019 -#define QAM_LC_QUAL_TAB1__W 5 -#define QAM_LC_QUAL_TAB1__M 0x1F -#define QAM_LC_QUAL_TAB1__PRE 0x1 - -#define QAM_LC_QUAL_TAB1_VALUE__B 0 -#define QAM_LC_QUAL_TAB1_VALUE__W 5 -#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 - -#define QAM_LC_QUAL_TAB2__A 0x145001A -#define QAM_LC_QUAL_TAB2__W 5 -#define QAM_LC_QUAL_TAB2__M 0x1F -#define QAM_LC_QUAL_TAB2__PRE 0x2 - -#define QAM_LC_QUAL_TAB2_VALUE__B 0 -#define QAM_LC_QUAL_TAB2_VALUE__W 5 -#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 - -#define QAM_LC_QUAL_TAB3__A 0x145001B -#define QAM_LC_QUAL_TAB3__W 5 -#define QAM_LC_QUAL_TAB3__M 0x1F -#define QAM_LC_QUAL_TAB3__PRE 0x3 - -#define QAM_LC_QUAL_TAB3_VALUE__B 0 -#define QAM_LC_QUAL_TAB3_VALUE__W 5 -#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 - -#define QAM_LC_QUAL_TAB4__A 0x145001C -#define QAM_LC_QUAL_TAB4__W 5 -#define QAM_LC_QUAL_TAB4__M 0x1F -#define QAM_LC_QUAL_TAB4__PRE 0x4 - -#define QAM_LC_QUAL_TAB4_VALUE__B 0 -#define QAM_LC_QUAL_TAB4_VALUE__W 5 -#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 - -#define QAM_LC_QUAL_TAB5__A 0x145001D -#define QAM_LC_QUAL_TAB5__W 5 -#define QAM_LC_QUAL_TAB5__M 0x1F -#define QAM_LC_QUAL_TAB5__PRE 0x5 - -#define QAM_LC_QUAL_TAB5_VALUE__B 0 -#define QAM_LC_QUAL_TAB5_VALUE__W 5 -#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 - -#define QAM_LC_QUAL_TAB6__A 0x145001E -#define QAM_LC_QUAL_TAB6__W 5 -#define QAM_LC_QUAL_TAB6__M 0x1F -#define QAM_LC_QUAL_TAB6__PRE 0x6 - -#define QAM_LC_QUAL_TAB6_VALUE__B 0 -#define QAM_LC_QUAL_TAB6_VALUE__W 5 -#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 - -#define QAM_LC_QUAL_TAB8__A 0x145001F -#define QAM_LC_QUAL_TAB8__W 5 -#define QAM_LC_QUAL_TAB8__M 0x1F -#define QAM_LC_QUAL_TAB8__PRE 0x8 - -#define QAM_LC_QUAL_TAB8_VALUE__B 0 -#define QAM_LC_QUAL_TAB8_VALUE__W 5 -#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 - -#define QAM_LC_QUAL_TAB9__A 0x1450020 -#define QAM_LC_QUAL_TAB9__W 5 -#define QAM_LC_QUAL_TAB9__M 0x1F -#define QAM_LC_QUAL_TAB9__PRE 0x9 - -#define QAM_LC_QUAL_TAB9_VALUE__B 0 -#define QAM_LC_QUAL_TAB9_VALUE__W 5 -#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 - -#define QAM_LC_QUAL_TAB10__A 0x1450021 -#define QAM_LC_QUAL_TAB10__W 5 -#define QAM_LC_QUAL_TAB10__M 0x1F -#define QAM_LC_QUAL_TAB10__PRE 0xA - -#define QAM_LC_QUAL_TAB10_VALUE__B 0 -#define QAM_LC_QUAL_TAB10_VALUE__W 5 -#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA - -#define QAM_LC_QUAL_TAB12__A 0x1450022 -#define QAM_LC_QUAL_TAB12__W 5 -#define QAM_LC_QUAL_TAB12__M 0x1F -#define QAM_LC_QUAL_TAB12__PRE 0xC - -#define QAM_LC_QUAL_TAB12_VALUE__B 0 -#define QAM_LC_QUAL_TAB12_VALUE__W 5 -#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC - -#define QAM_LC_QUAL_TAB15__A 0x1450023 -#define QAM_LC_QUAL_TAB15__W 5 -#define QAM_LC_QUAL_TAB15__M 0x1F -#define QAM_LC_QUAL_TAB15__PRE 0xF - -#define QAM_LC_QUAL_TAB15_VALUE__B 0 -#define QAM_LC_QUAL_TAB15_VALUE__W 5 -#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF - -#define QAM_LC_QUAL_TAB16__A 0x1450024 -#define QAM_LC_QUAL_TAB16__W 5 -#define QAM_LC_QUAL_TAB16__M 0x1F -#define QAM_LC_QUAL_TAB16__PRE 0x10 - -#define QAM_LC_QUAL_TAB16_VALUE__B 0 -#define QAM_LC_QUAL_TAB16_VALUE__W 5 -#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 - -#define QAM_LC_QUAL_TAB20__A 0x1450025 -#define QAM_LC_QUAL_TAB20__W 5 -#define QAM_LC_QUAL_TAB20__M 0x1F -#define QAM_LC_QUAL_TAB20__PRE 0x14 - -#define QAM_LC_QUAL_TAB20_VALUE__B 0 -#define QAM_LC_QUAL_TAB20_VALUE__W 5 -#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 - -#define QAM_LC_QUAL_TAB25__A 0x1450026 -#define QAM_LC_QUAL_TAB25__W 5 -#define QAM_LC_QUAL_TAB25__M 0x1F -#define QAM_LC_QUAL_TAB25__PRE 0x19 - -#define QAM_LC_QUAL_TAB25_VALUE__B 0 -#define QAM_LC_QUAL_TAB25_VALUE__W 5 -#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 - -#define QAM_LC_EQ_TIMING__A 0x1450027 -#define QAM_LC_EQ_TIMING__W 10 -#define QAM_LC_EQ_TIMING__M 0x3FF -#define QAM_LC_EQ_TIMING__PRE 0x0 - -#define QAM_LC_EQ_TIMING_OFFS__B 0 -#define QAM_LC_EQ_TIMING_OFFS__W 10 -#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF -#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 - -#define QAM_LC_LPF_FACTORP__A 0x1450028 -#define QAM_LC_LPF_FACTORP__W 3 -#define QAM_LC_LPF_FACTORP__M 0x7 -#define QAM_LC_LPF_FACTORP__PRE 0x3 - -#define QAM_LC_LPF_FACTORP_FACTOR__B 0 -#define QAM_LC_LPF_FACTORP_FACTOR__W 3 -#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 -#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 - -#define QAM_LC_LPF_FACTORI__A 0x1450029 -#define QAM_LC_LPF_FACTORI__W 3 -#define QAM_LC_LPF_FACTORI__M 0x7 -#define QAM_LC_LPF_FACTORI__PRE 0x3 - -#define QAM_LC_LPF_FACTORI_FACTOR__B 0 -#define QAM_LC_LPF_FACTORI_FACTOR__W 3 -#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 -#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 - -#define QAM_LC_RATE_LIMIT__A 0x145002A -#define QAM_LC_RATE_LIMIT__W 2 -#define QAM_LC_RATE_LIMIT__M 0x3 -#define QAM_LC_RATE_LIMIT__PRE 0x3 - -#define QAM_LC_RATE_LIMIT_LIMIT__B 0 -#define QAM_LC_RATE_LIMIT_LIMIT__W 2 -#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 -#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 - -#define QAM_LC_SYMBOL_FREQ__A 0x145002B -#define QAM_LC_SYMBOL_FREQ__W 10 -#define QAM_LC_SYMBOL_FREQ__M 0x3FF -#define QAM_LC_SYMBOL_FREQ__PRE 0x1FF - -#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 -#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 -#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF -#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x1FF - -#define QAM_LC_MTA_LENGTH__A 0x145002C -#define QAM_LC_MTA_LENGTH__W 2 -#define QAM_LC_MTA_LENGTH__M 0x3 -#define QAM_LC_MTA_LENGTH__PRE 0x2 - -#define QAM_LC_MTA_LENGTH_LENGTH__B 0 -#define QAM_LC_MTA_LENGTH_LENGTH__W 2 -#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 -#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 - -#define QAM_LC_AMP_ACCU__A 0x145002D -#define QAM_LC_AMP_ACCU__W 14 -#define QAM_LC_AMP_ACCU__M 0x3FFF -#define QAM_LC_AMP_ACCU__PRE 0x600 - -#define QAM_LC_AMP_ACCU_ACCU__B 0 -#define QAM_LC_AMP_ACCU_ACCU__W 14 -#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF -#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 - -#define QAM_LC_FREQ_ACCU__A 0x145002E -#define QAM_LC_FREQ_ACCU__W 10 -#define QAM_LC_FREQ_ACCU__M 0x3FF -#define QAM_LC_FREQ_ACCU__PRE 0x0 - -#define QAM_LC_FREQ_ACCU_ACCU__B 0 -#define QAM_LC_FREQ_ACCU_ACCU__W 10 -#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF -#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 - -#define QAM_LC_RATE_ACCU__A 0x145002F -#define QAM_LC_RATE_ACCU__W 10 -#define QAM_LC_RATE_ACCU__M 0x3FF -#define QAM_LC_RATE_ACCU__PRE 0x0 - -#define QAM_LC_RATE_ACCU_ACCU__B 0 -#define QAM_LC_RATE_ACCU_ACCU__W 10 -#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF -#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 - -#define QAM_LC_AMPLITUDE__A 0x1450030 -#define QAM_LC_AMPLITUDE__W 10 -#define QAM_LC_AMPLITUDE__M 0x3FF -#define QAM_LC_AMPLITUDE__PRE 0x0 - -#define QAM_LC_AMPLITUDE_SIZE__B 0 -#define QAM_LC_AMPLITUDE_SIZE__W 10 -#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF -#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 - -#define QAM_LC_RAD_ERROR__A 0x1450031 -#define QAM_LC_RAD_ERROR__W 10 -#define QAM_LC_RAD_ERROR__M 0x3FF -#define QAM_LC_RAD_ERROR__PRE 0x0 - -#define QAM_LC_RAD_ERROR_SIZE__B 0 -#define QAM_LC_RAD_ERROR_SIZE__W 10 -#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF -#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 - -#define QAM_LC_FREQ_OFFS__A 0x1450032 -#define QAM_LC_FREQ_OFFS__W 10 -#define QAM_LC_FREQ_OFFS__M 0x3FF -#define QAM_LC_FREQ_OFFS__PRE 0x0 - -#define QAM_LC_FREQ_OFFS_OFFS__B 0 -#define QAM_LC_FREQ_OFFS_OFFS__W 10 -#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF -#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 - -#define QAM_LC_PHASE_ERROR__A 0x1450033 -#define QAM_LC_PHASE_ERROR__W 10 -#define QAM_LC_PHASE_ERROR__M 0x3FF -#define QAM_LC_PHASE_ERROR__PRE 0x0 - -#define QAM_LC_PHASE_ERROR_SIZE__B 0 -#define QAM_LC_PHASE_ERROR_SIZE__W 10 -#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF -#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 - - - -#define QAM_SY_COMM_EXEC__A 0x1470000 -#define QAM_SY_COMM_EXEC__W 2 -#define QAM_SY_COMM_EXEC__M 0x3 -#define QAM_SY_COMM_EXEC__PRE 0x0 -#define QAM_SY_COMM_EXEC_STOP 0x0 -#define QAM_SY_COMM_EXEC_ACTIVE 0x1 -#define QAM_SY_COMM_EXEC_HOLD 0x2 - -#define QAM_SY_COMM_MB__A 0x1470002 -#define QAM_SY_COMM_MB__W 4 -#define QAM_SY_COMM_MB__M 0xF -#define QAM_SY_COMM_MB__PRE 0x0 -#define QAM_SY_COMM_MB_CTL__B 0 -#define QAM_SY_COMM_MB_CTL__W 1 -#define QAM_SY_COMM_MB_CTL__M 0x1 -#define QAM_SY_COMM_MB_CTL__PRE 0x0 -#define QAM_SY_COMM_MB_CTL_OFF 0x0 -#define QAM_SY_COMM_MB_CTL_ON 0x1 -#define QAM_SY_COMM_MB_OBS__B 1 -#define QAM_SY_COMM_MB_OBS__W 1 -#define QAM_SY_COMM_MB_OBS__M 0x2 -#define QAM_SY_COMM_MB_OBS__PRE 0x0 -#define QAM_SY_COMM_MB_OBS_OFF 0x0 -#define QAM_SY_COMM_MB_OBS_ON 0x2 -#define QAM_SY_COMM_MB_MUX_CTL__B 2 -#define QAM_SY_COMM_MB_MUX_CTL__W 1 -#define QAM_SY_COMM_MB_MUX_CTL__M 0x4 -#define QAM_SY_COMM_MB_MUX_CTL__PRE 0x0 -#define QAM_SY_COMM_MB_MUX_CTL_MB0 0x0 -#define QAM_SY_COMM_MB_MUX_CTL_MB1 0x4 -#define QAM_SY_COMM_MB_MUX_OBS__B 3 -#define QAM_SY_COMM_MB_MUX_OBS__W 1 -#define QAM_SY_COMM_MB_MUX_OBS__M 0x8 -#define QAM_SY_COMM_MB_MUX_OBS__PRE 0x0 -#define QAM_SY_COMM_MB_MUX_OBS_MB0 0x0 -#define QAM_SY_COMM_MB_MUX_OBS_MB1 0x8 - -#define QAM_SY_COMM_INT_REQ__A 0x1470003 -#define QAM_SY_COMM_INT_REQ__W 1 -#define QAM_SY_COMM_INT_REQ__M 0x1 -#define QAM_SY_COMM_INT_REQ__PRE 0x0 -#define QAM_SY_COMM_INT_STA__A 0x1470005 -#define QAM_SY_COMM_INT_STA__W 4 -#define QAM_SY_COMM_INT_STA__M 0xF -#define QAM_SY_COMM_INT_STA__PRE 0x0 - -#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 -#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 -#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 -#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 - -#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 -#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 -#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 -#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 - -#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 -#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 -#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 -#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 - -#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 -#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 -#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 -#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 - -#define QAM_SY_COMM_INT_MSK__A 0x1470006 -#define QAM_SY_COMM_INT_MSK__W 4 -#define QAM_SY_COMM_INT_MSK__M 0xF -#define QAM_SY_COMM_INT_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 -#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 -#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 -#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 -#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 -#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 -#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 -#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 -#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 -#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 -#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 -#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 -#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 - -#define QAM_SY_COMM_INT_STM__A 0x1470007 -#define QAM_SY_COMM_INT_STM__W 4 -#define QAM_SY_COMM_INT_STM__M 0xF -#define QAM_SY_COMM_INT_STM__PRE 0x0 -#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 -#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 -#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 -#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 -#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 -#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 -#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 -#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 -#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 -#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 -#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 -#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 -#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 - -#define QAM_SY_STATUS__A 0x1470010 -#define QAM_SY_STATUS__W 2 -#define QAM_SY_STATUS__M 0x3 -#define QAM_SY_STATUS__PRE 0x0 - -#define QAM_SY_STATUS_SYNC_STATE__B 0 -#define QAM_SY_STATUS_SYNC_STATE__W 2 -#define QAM_SY_STATUS_SYNC_STATE__M 0x3 -#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 - - -#define QAM_SY_TIMEOUT__A 0x1470011 -#define QAM_SY_TIMEOUT__W 16 -#define QAM_SY_TIMEOUT__M 0xFFFF -#define QAM_SY_TIMEOUT__PRE 0x3A98 - -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_SYNC_LWM__W 4 -#define QAM_SY_SYNC_LWM__M 0xF -#define QAM_SY_SYNC_LWM__PRE 0x2 - -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_AWM__W 4 -#define QAM_SY_SYNC_AWM__M 0xF -#define QAM_SY_SYNC_AWM__PRE 0x3 - -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_HWM__W 4 -#define QAM_SY_SYNC_HWM__M 0xF -#define QAM_SY_SYNC_HWM__PRE 0x5 - -#define QAM_SY_UNLOCK__A 0x1470015 -#define QAM_SY_UNLOCK__W 1 -#define QAM_SY_UNLOCK__M 0x1 -#define QAM_SY_UNLOCK__PRE 0x0 -#define QAM_SY_CONTROL_WORD__A 0x1470016 -#define QAM_SY_CONTROL_WORD__W 4 -#define QAM_SY_CONTROL_WORD__M 0xF -#define QAM_SY_CONTROL_WORD__PRE 0x0 - -#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 -#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 -#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF -#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 - - -#define QAM_SY_SP_INV__A 0x1470017 -#define QAM_SY_SP_INV__W 1 -#define QAM_SY_SP_INV__M 0x1 -#define QAM_SY_SP_INV__PRE 0x0 -#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 -#define QAM_SY_SP_INV_SPECTRUM_INV_ENA 0x1 - - - -#define QAM_VD_ISS_RAM__A 0x1480000 - - - -#define QAM_VD_QSS_RAM__A 0x1490000 - - - -#define QAM_VD_SYM_RAM__A 0x14A0000 - - - - - -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__W 2 -#define SCU_COMM_EXEC__M 0x3 -#define SCU_COMM_EXEC__PRE 0x0 -#define SCU_COMM_EXEC_STOP 0x0 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_HOLD 0x2 - -#define SCU_COMM_STATE__A 0x800001 -#define SCU_COMM_STATE__W 16 -#define SCU_COMM_STATE__M 0xFFFF -#define SCU_COMM_STATE__PRE 0x0 - -#define SCU_COMM_STATE_COMM_STATE__B 0 -#define SCU_COMM_STATE_COMM_STATE__W 16 -#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF -#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 - - - -#define SCU_TOP_COMM_EXEC__A 0x810000 -#define SCU_TOP_COMM_EXEC__W 2 -#define SCU_TOP_COMM_EXEC__M 0x3 -#define SCU_TOP_COMM_EXEC__PRE 0x0 -#define SCU_TOP_COMM_EXEC_STOP 0x0 -#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 -#define SCU_TOP_COMM_EXEC_HOLD 0x2 - - -#define SCU_TOP_COMM_STATE__A 0x810001 -#define SCU_TOP_COMM_STATE__W 16 -#define SCU_TOP_COMM_STATE__M 0xFFFF -#define SCU_TOP_COMM_STATE__PRE 0x0 -#define SCU_TOP_MWAIT_CTR__A 0x810010 -#define SCU_TOP_MWAIT_CTR__W 2 -#define SCU_TOP_MWAIT_CTR__M 0x3 -#define SCU_TOP_MWAIT_CTR__PRE 0x0 - -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 - -#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 -#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 -#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 -#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 -#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 -#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 - - - -#define SCU_LOW_RAM__A 0x820000 - -#define SCU_LOW_RAM_LOW__B 0 -#define SCU_LOW_RAM_LOW__W 16 -#define SCU_LOW_RAM_LOW__M 0xFFFF -#define SCU_LOW_RAM_LOW__PRE 0x0 - - - -#define SCU_HIGH_RAM__A 0x830000 - -#define SCU_HIGH_RAM_HIGH__B 0 -#define SCU_HIGH_RAM_HIGH__W 16 -#define SCU_HIGH_RAM_HIGH__M 0xFFFF -#define SCU_HIGH_RAM_HIGH__PRE 0x0 - - - - - - -#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF -#define SCU_RAM_DRIVER_DEBUG__W 16 -#define SCU_RAM_DRIVER_DEBUG__M 0xFFFF -#define SCU_RAM_DRIVER_DEBUG__PRE 0x0 - -#define SCU_RAM_SP__A 0x831EC0 -#define SCU_RAM_SP__W 16 -#define SCU_RAM_SP__M 0xFFFF -#define SCU_RAM_SP__PRE 0x0 - -#define SCU_RAM_QAM_NEVERLOCK_CNT__A 0x831EC1 -#define SCU_RAM_QAM_NEVERLOCK_CNT__W 16 -#define SCU_RAM_QAM_NEVERLOCK_CNT__M 0xFFFF -#define SCU_RAM_QAM_NEVERLOCK_CNT__PRE 0x0 - -#define SCU_RAM_QAM_WRONG_RATE_CNT__A 0x831EC2 -#define SCU_RAM_QAM_WRONG_RATE_CNT__W 16 -#define SCU_RAM_QAM_WRONG_RATE_CNT__M 0xFFFF -#define SCU_RAM_QAM_WRONG_RATE_CNT__PRE 0x0 - -#define SCU_RAM_QAM_NO_ACQ_CNT__A 0x831EC3 -#define SCU_RAM_QAM_NO_ACQ_CNT__W 16 -#define SCU_RAM_QAM_NO_ACQ_CNT__M 0xFFFF -#define SCU_RAM_QAM_NO_ACQ_CNT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 -#define SCU_RAM_QAM_FSM_STEP_PERIOD__W 16 -#define SCU_RAM_QAM_FSM_STEP_PERIOD__M 0xFFFF -#define SCU_RAM_QAM_FSM_STEP_PERIOD__PRE 0x4B0 - -#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC5 -#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 -#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x8000 - -#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC6 -#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 -#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__W 2 -#define SCU_RAM_GPIO__M 0x3 -#define SCU_RAM_GPIO__PRE 0x0 - -#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 -#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 -#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 -#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 - -#define SCU_RAM_GPIO_VSYNC_IND__B 1 -#define SCU_RAM_GPIO_VSYNC_IND__W 1 -#define SCU_RAM_GPIO_VSYNC_IND__M 0x2 -#define SCU_RAM_GPIO_VSYNC_IND__PRE 0x0 -#define SCU_RAM_GPIO_VSYNC_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_VSYNC_IND_ENABLE 0x2 - -#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 -#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 -#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF -#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 - -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1 - -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 - -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 - - -#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 -#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 -#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x8000 - -#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA -#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 -#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 - -#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB -#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 -#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF -#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 - -#define SCU_RAM_INHIBIT_1__A 0x831ECC -#define SCU_RAM_INHIBIT_1__W 16 -#define SCU_RAM_INHIBIT_1__M 0xFFFF -#define SCU_RAM_INHIBIT_1__PRE 0x0 - -#define SCU_RAM_HTOL_BUF_0__A 0x831ECD -#define SCU_RAM_HTOL_BUF_0__W 16 -#define SCU_RAM_HTOL_BUF_0__M 0xFFFF -#define SCU_RAM_HTOL_BUF_0__PRE 0x0 - -#define SCU_RAM_HTOL_BUF_1__A 0x831ECE -#define SCU_RAM_HTOL_BUF_1__W 16 -#define SCU_RAM_HTOL_BUF_1__M 0xFFFF -#define SCU_RAM_HTOL_BUF_1__PRE 0x0 - -#define SCU_RAM_INHIBIT_2__A 0x831ECF -#define SCU_RAM_INHIBIT_2__W 16 -#define SCU_RAM_INHIBIT_2__M 0xFFFF -#define SCU_RAM_INHIBIT_2__PRE 0x0 - -#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 -#define SCU_RAM_TR_SHORT_BUF_0__W 16 -#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF -#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 - -#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 -#define SCU_RAM_TR_SHORT_BUF_1__W 16 -#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF -#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 -#define SCU_RAM_TR_LONG_BUF_0__W 16 -#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 -#define SCU_RAM_TR_LONG_BUF_1__W 16 -#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 -#define SCU_RAM_TR_LONG_BUF_2__W 16 -#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 -#define SCU_RAM_TR_LONG_BUF_3__W 16 -#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 -#define SCU_RAM_TR_LONG_BUF_4__W 16 -#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 -#define SCU_RAM_TR_LONG_BUF_5__W 16 -#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 -#define SCU_RAM_TR_LONG_BUF_6__W 16 -#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 -#define SCU_RAM_TR_LONG_BUF_7__W 16 -#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA -#define SCU_RAM_TR_LONG_BUF_8__W 16 -#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB -#define SCU_RAM_TR_LONG_BUF_9__W 16 -#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC -#define SCU_RAM_TR_LONG_BUF_10__W 16 -#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD -#define SCU_RAM_TR_LONG_BUF_11__W 16 -#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE -#define SCU_RAM_TR_LONG_BUF_12__W 16 -#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF -#define SCU_RAM_TR_LONG_BUF_13__W 16 -#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 -#define SCU_RAM_TR_LONG_BUF_14__W 16 -#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 -#define SCU_RAM_TR_LONG_BUF_15__W 16 -#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 -#define SCU_RAM_TR_LONG_BUF_16__W 16 -#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 -#define SCU_RAM_TR_LONG_BUF_17__W 16 -#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 -#define SCU_RAM_TR_LONG_BUF_18__W 16 -#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 -#define SCU_RAM_TR_LONG_BUF_19__W 16 -#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 -#define SCU_RAM_TR_LONG_BUF_20__W 16 -#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 -#define SCU_RAM_TR_LONG_BUF_21__W 16 -#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 -#define SCU_RAM_TR_LONG_BUF_22__W 16 -#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 -#define SCU_RAM_TR_LONG_BUF_23__W 16 -#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA -#define SCU_RAM_TR_LONG_BUF_24__W 16 -#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB -#define SCU_RAM_TR_LONG_BUF_25__W 16 -#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC -#define SCU_RAM_TR_LONG_BUF_26__W 16 -#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED -#define SCU_RAM_TR_LONG_BUF_27__W 16 -#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE -#define SCU_RAM_TR_LONG_BUF_28__W 16 -#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF -#define SCU_RAM_TR_LONG_BUF_29__W 16 -#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 -#define SCU_RAM_TR_LONG_BUF_30__W 16 -#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 -#define SCU_RAM_TR_LONG_BUF_31__W 16 -#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 -#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 -#define SCU_RAM_ATV_AMS_MAX__W 11 -#define SCU_RAM_ATV_AMS_MAX__M 0x7FF -#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 - -#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 -#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 -#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF -#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 - -#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 -#define SCU_RAM_ATV_AMS_MIN__W 11 -#define SCU_RAM_ATV_AMS_MIN__M 0x7FF -#define SCU_RAM_ATV_AMS_MIN__PRE 0x7FF - -#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 -#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 -#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF -#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x7FF - -#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 -#define SCU_RAM_ATV_FIELD_CNT__W 9 -#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF -#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 - -#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 -#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 -#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF -#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 - -#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 -#define SCU_RAM_ATV_AAGC_FAST__W 1 -#define SCU_RAM_ATV_AAGC_FAST__M 0x1 -#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 - -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 - -#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 -#define SCU_RAM_ATV_AAGC_LP2__W 16 -#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF -#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 - -#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 -#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 -#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF -#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 - -#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 -#define SCU_RAM_ATV_BP_LVL__W 11 -#define SCU_RAM_ATV_BP_LVL__M 0x7FF -#define SCU_RAM_ATV_BP_LVL__PRE 0x0 - -#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 -#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 -#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF -#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 - -#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 -#define SCU_RAM_ATV_BP_RELY__W 8 -#define SCU_RAM_ATV_BP_RELY__M 0xFF -#define SCU_RAM_ATV_BP_RELY__PRE 0x0 - -#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 -#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 -#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF -#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 - -#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 -#define SCU_RAM_ATV_BP_MTA__W 14 -#define SCU_RAM_ATV_BP_MTA__M 0x3FFF -#define SCU_RAM_ATV_BP_MTA__PRE 0x0 - -#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 -#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 -#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF -#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 - -#define SCU_RAM_ATV_BP_REF__A 0x831EFA -#define SCU_RAM_ATV_BP_REF__W 11 -#define SCU_RAM_ATV_BP_REF__M 0x7FF -#define SCU_RAM_ATV_BP_REF__PRE 0x0 - -#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 -#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 -#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF -#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 - -#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB -#define SCU_RAM_ATV_BP_REF_MIN__W 11 -#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF -#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x64 - -#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 -#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 -#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF -#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x64 - -#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC -#define SCU_RAM_ATV_BP_REF_MAX__W 11 -#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF -#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x104 - -#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 -#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 -#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF -#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x104 - -#define SCU_RAM_ATV_BP_CNT__A 0x831EFD -#define SCU_RAM_ATV_BP_CNT__W 8 -#define SCU_RAM_ATV_BP_CNT__M 0xFF -#define SCU_RAM_ATV_BP_CNT__PRE 0x0 - -#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 -#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 -#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF -#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 - -#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE -#define SCU_RAM_ATV_BP_XD_CNT__W 12 -#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF -#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 - -#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 -#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 -#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF -#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 - -#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF -#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 -#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x445 - -#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 -#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 -#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x445 - -#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 -#define SCU_RAM_ATV_BPC_KI_MIN__W 12 -#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x223 - -#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 -#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 -#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x223 - - -#define SCU_RAM_OFDM_AGC_POW_TGT__A 0x831F01 -#define SCU_RAM_OFDM_AGC_POW_TGT__W 15 -#define SCU_RAM_OFDM_AGC_POW_TGT__M 0x7FFF -#define SCU_RAM_OFDM_AGC_POW_TGT__PRE 0x5848 - -#define SCU_RAM_OFDM_RSV_01__A 0x831F02 -#define SCU_RAM_OFDM_RSV_01__W 16 -#define SCU_RAM_OFDM_RSV_01__M 0xFFFF -#define SCU_RAM_OFDM_RSV_01__PRE 0x0 - -#define SCU_RAM_OFDM_RSV_02__A 0x831F03 -#define SCU_RAM_OFDM_RSV_02__W 16 -#define SCU_RAM_OFDM_RSV_02__M 0xFFFF -#define SCU_RAM_OFDM_RSV_02__PRE 0x0 -#define SCU_RAM_FEC_PRE_RS_BER__A 0x831F04 -#define SCU_RAM_FEC_PRE_RS_BER__W 16 -#define SCU_RAM_FEC_PRE_RS_BER__M 0xFFFF -#define SCU_RAM_FEC_PRE_RS_BER__PRE 0x0 - -#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__B 0 -#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__W 16 -#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__M 0xFFFF -#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__PRE 0x0 - -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__W 16 -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__M 0xFFFF -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__PRE 0x0 - -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__B 0 -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__W 16 -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__M 0xFFFF -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__PRE 0x0 - -#define SCU_RAM_ATV_VSYNC_LINE_CNT__A 0x831F06 -#define SCU_RAM_ATV_VSYNC_LINE_CNT__W 16 -#define SCU_RAM_ATV_VSYNC_LINE_CNT__M 0xFFFF -#define SCU_RAM_ATV_VSYNC_LINE_CNT__PRE 0x0 - -#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__W 16 -#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__M 0xFFFF -#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__PRE 0x0 - -#define SCU_RAM_ATV_VSYNC_PERIOD__A 0x831F07 -#define SCU_RAM_ATV_VSYNC_PERIOD__W 16 -#define SCU_RAM_ATV_VSYNC_PERIOD__M 0xFFFF -#define SCU_RAM_ATV_VSYNC_PERIOD__PRE 0x0 - -#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__W 16 -#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__M 0xFFFF -#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__PRE 0x0 - -#define SCU_RAM_FREE_7944__A 0x831F08 -#define SCU_RAM_FREE_7944__W 16 -#define SCU_RAM_FREE_7944__M 0xFFFF -#define SCU_RAM_FREE_7944__PRE 0x0 - -#define SCU_RAM_FREE_7944_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7944_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7944_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7944_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7945__A 0x831F09 -#define SCU_RAM_FREE_7945__W 16 -#define SCU_RAM_FREE_7945__M 0xFFFF -#define SCU_RAM_FREE_7945__PRE 0x0 - -#define SCU_RAM_FREE_7945_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7945_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7945_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7945_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7946__A 0x831F0A -#define SCU_RAM_FREE_7946__W 16 -#define SCU_RAM_FREE_7946__M 0xFFFF -#define SCU_RAM_FREE_7946__PRE 0x0 - -#define SCU_RAM_FREE_7946_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7946_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7946_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7946_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7947__A 0x831F0B -#define SCU_RAM_FREE_7947__W 16 -#define SCU_RAM_FREE_7947__M 0xFFFF -#define SCU_RAM_FREE_7947__PRE 0x0 - -#define SCU_RAM_FREE_7947_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7947_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7947_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7947_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7948__A 0x831F0C -#define SCU_RAM_FREE_7948__W 16 -#define SCU_RAM_FREE_7948__M 0xFFFF -#define SCU_RAM_FREE_7948__PRE 0x0 - -#define SCU_RAM_FREE_7948_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7948_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7948_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7948_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7949__A 0x831F0D -#define SCU_RAM_FREE_7949__W 16 -#define SCU_RAM_FREE_7949__M 0xFFFF -#define SCU_RAM_FREE_7949__PRE 0x0 - -#define SCU_RAM_FREE_7949_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7949_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7949_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7949_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7950__A 0x831F0E -#define SCU_RAM_FREE_7950__W 16 -#define SCU_RAM_FREE_7950__M 0xFFFF -#define SCU_RAM_FREE_7950__PRE 0x0 - -#define SCU_RAM_FREE_7950_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7950_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7950_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7950_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7951__A 0x831F0F -#define SCU_RAM_FREE_7951__W 16 -#define SCU_RAM_FREE_7951__M 0xFFFF -#define SCU_RAM_FREE_7951__PRE 0x0 - -#define SCU_RAM_FREE_7951_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7951_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7951_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7951_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7952__A 0x831F10 -#define SCU_RAM_FREE_7952__W 16 -#define SCU_RAM_FREE_7952__M 0xFFFF -#define SCU_RAM_FREE_7952__PRE 0x0 - -#define SCU_RAM_FREE_7952_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7952_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7952_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7952_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7953__A 0x831F11 -#define SCU_RAM_FREE_7953__W 16 -#define SCU_RAM_FREE_7953__M 0xFFFF -#define SCU_RAM_FREE_7953__PRE 0x0 - -#define SCU_RAM_FREE_7953_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7953_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7953_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7953_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7954__A 0x831F12 -#define SCU_RAM_FREE_7954__W 16 -#define SCU_RAM_FREE_7954__M 0xFFFF -#define SCU_RAM_FREE_7954__PRE 0x0 - -#define SCU_RAM_FREE_7954_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7954_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7954_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7954_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7955__A 0x831F13 -#define SCU_RAM_FREE_7955__W 16 -#define SCU_RAM_FREE_7955__M 0xFFFF -#define SCU_RAM_FREE_7955__PRE 0x0 - -#define SCU_RAM_FREE_7955_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7955_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7955_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7955_SCU_RAM_FREE__PRE 0x0 - - -#define SCU_RAM_ADC_COMP_CONTROL__A 0x831F14 -#define SCU_RAM_ADC_COMP_CONTROL__W 3 -#define SCU_RAM_ADC_COMP_CONTROL__M 0x7 -#define SCU_RAM_ADC_COMP_CONTROL__PRE 0x0 -#define SCU_RAM_ADC_COMP_CONTROL_CONFIG 0x0 -#define SCU_RAM_ADC_COMP_CONTROL_DO_AGC 0x1 -#define SCU_RAM_ADC_COMP_CONTROL_SET_ADJUST 0x2 -#define SCU_RAM_ADC_COMP_CONTROL_SET_ACTIVE 0x3 - - -#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 -#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 -#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF -#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x32 - -#define SCU_RAM_AGC_KI_CYCCNT__A 0x831F16 -#define SCU_RAM_AGC_KI_CYCCNT__W 16 -#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF -#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 - -#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 -#define SCU_RAM_AGC_KI_CYCLEN__W 16 -#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF -#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x1F4 - -#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 -#define SCU_RAM_AGC_SNS_CYCLEN__W 16 -#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF -#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x1F4 - -#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 -#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 -#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF -#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x3FF - -#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A -#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 -#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF -#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0xFC01 - -#define SCU_RAM_AGC_RF_MAX__A 0x831F1B -#define SCU_RAM_AGC_RF_MAX__W 15 -#define SCU_RAM_AGC_RF_MAX__M 0x7FFF -#define SCU_RAM_AGC_RF_MAX__PRE 0x7FFF -#define SCU_RAM_FREE_7964__A 0x831F1C -#define SCU_RAM_FREE_7964__W 16 -#define SCU_RAM_FREE_7964__M 0xFFFF -#define SCU_RAM_FREE_7964__PRE 0x0 - -#define SCU_RAM_FREE_7964_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7964_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7964_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7964_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7965__A 0x831F1D -#define SCU_RAM_FREE_7965__W 16 -#define SCU_RAM_FREE_7965__M 0xFFFF -#define SCU_RAM_FREE_7965__PRE 0x0 - -#define SCU_RAM_FREE_7965_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7965_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7965_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7965_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7966__A 0x831F1E -#define SCU_RAM_FREE_7966__W 16 -#define SCU_RAM_FREE_7966__M 0xFFFF -#define SCU_RAM_FREE_7966__PRE 0x0 - -#define SCU_RAM_FREE_7966_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7966_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7966_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7966_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7967__A 0x831F1F -#define SCU_RAM_FREE_7967__W 16 -#define SCU_RAM_FREE_7967__M 0xFFFF -#define SCU_RAM_FREE_7967__PRE 0x0 - -#define SCU_RAM_FREE_7967_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7967_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7967_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7967_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_MIRRORING__A 0x831F20 -#define SCU_RAM_QAM_PARAM_MIRRORING__W 8 -#define SCU_RAM_QAM_PARAM_MIRRORING__M 0xFF -#define SCU_RAM_QAM_PARAM_MIRRORING__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_MIRRORING_SET__B 0 -#define SCU_RAM_QAM_PARAM_MIRRORING_SET__W 1 -#define SCU_RAM_QAM_PARAM_MIRRORING_SET__M 0x1 -#define SCU_RAM_QAM_PARAM_MIRRORING_SET__PRE 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_SET_NORMAL 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_SET_MIRRORED 0x1 - -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__B 1 -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__W 1 -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__M 0x2 -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__PRE 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_OFF 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_ON 0x2 - -#define SCU_RAM_QAM_PARAM_MIRRORING_DET__B 2 -#define SCU_RAM_QAM_PARAM_MIRRORING_DET__W 1 -#define SCU_RAM_QAM_PARAM_MIRRORING_DET__M 0x4 -#define SCU_RAM_QAM_PARAM_MIRRORING_DET__PRE 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_DET_NORMAL 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_DET_MIRRORED 0x4 - -#define SCU_RAM_QAM_PARAM_OPTIONS__A 0x831F21 -#define SCU_RAM_QAM_PARAM_OPTIONS__W 8 -#define SCU_RAM_QAM_PARAM_OPTIONS__M 0xFF -#define SCU_RAM_QAM_PARAM_OPTIONS__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_OPTIONS_SET__B 0 -#define SCU_RAM_QAM_PARAM_OPTIONS_SET__W 1 -#define SCU_RAM_QAM_PARAM_OPTIONS_SET__M 0x1 -#define SCU_RAM_QAM_PARAM_OPTIONS_SET__PRE 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_SET_NORMAL 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_SET_MIRRORED 0x1 - -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__B 1 -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__W 1 -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__M 0x2 -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__PRE 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_OFF 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_ON 0x2 - -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__B 4 -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__W 1 -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__M 0x10 -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__PRE 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_EXTENDED 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_NORMAL 0x10 - -#define SCU_RAM_FREE_7970__A 0x831F22 -#define SCU_RAM_FREE_7970__W 16 -#define SCU_RAM_FREE_7970__M 0xFFFF -#define SCU_RAM_FREE_7970__PRE 0x0 - -#define SCU_RAM_FREE_7970_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7970_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7970_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7970_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7971__A 0x831F23 -#define SCU_RAM_FREE_7971__W 16 -#define SCU_RAM_FREE_7971__M 0xFFFF -#define SCU_RAM_FREE_7971__PRE 0x0 - -#define SCU_RAM_FREE_7971_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7971_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7971_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7971_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG__A 0x831F24 -#define SCU_RAM_AGC_CONFIG__W 16 -#define SCU_RAM_AGC_CONFIG__M 0xFFFF -#define SCU_RAM_AGC_CONFIG__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__B 0 -#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__W 1 -#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 -#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__B 1 -#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__W 1 -#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 -#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__B 2 -#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__W 1 -#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__M 0x4 -#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG_INV_IF_POL__B 8 -#define SCU_RAM_AGC_CONFIG_INV_IF_POL__W 1 -#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 -#define SCU_RAM_AGC_CONFIG_INV_IF_POL__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG_INV_RF_POL__B 9 -#define SCU_RAM_AGC_CONFIG_INV_RF_POL__W 1 -#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 -#define SCU_RAM_AGC_CONFIG_INV_RF_POL__PRE 0x0 - -#define SCU_RAM_AGC_KI__A 0x831F25 -#define SCU_RAM_AGC_KI__W 15 -#define SCU_RAM_AGC_KI__M 0x7FFF -#define SCU_RAM_AGC_KI__PRE 0x22A - -#define SCU_RAM_AGC_KI_DGAIN__B 0 -#define SCU_RAM_AGC_KI_DGAIN__W 4 -#define SCU_RAM_AGC_KI_DGAIN__M 0xF -#define SCU_RAM_AGC_KI_DGAIN__PRE 0xA - -#define SCU_RAM_AGC_KI_RF__B 4 -#define SCU_RAM_AGC_KI_RF__W 4 -#define SCU_RAM_AGC_KI_RF__M 0xF0 -#define SCU_RAM_AGC_KI_RF__PRE 0x20 - -#define SCU_RAM_AGC_KI_IF__B 8 -#define SCU_RAM_AGC_KI_IF__W 4 -#define SCU_RAM_AGC_KI_IF__M 0xF00 -#define SCU_RAM_AGC_KI_IF__PRE 0x200 - -#define SCU_RAM_AGC_KI_RED__A 0x831F26 -#define SCU_RAM_AGC_KI_RED__W 6 -#define SCU_RAM_AGC_KI_RED__M 0x3F -#define SCU_RAM_AGC_KI_RED__PRE 0x0 - -#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 -#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 -#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 -#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 - -#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 -#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 -#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC -#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 - -#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 -#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 -#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 -#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 - - -#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 -#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 -#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF -#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 - -#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 -#define SCU_RAM_AGC_KI_MINGAIN__W 16 -#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x8000 - -#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 -#define SCU_RAM_AGC_KI_MAXGAIN__W 16 -#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 - -#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A -#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 -#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF -#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 -#define SCU_RAM_AGC_KI_MIN__A 0x831F2B -#define SCU_RAM_AGC_KI_MIN__W 12 -#define SCU_RAM_AGC_KI_MIN__M 0xFFF -#define SCU_RAM_AGC_KI_MIN__PRE 0x111 - -#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 -#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 -#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF -#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x1 - -#define SCU_RAM_AGC_KI_MIN_RF__B 4 -#define SCU_RAM_AGC_KI_MIN_RF__W 4 -#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 -#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x10 - -#define SCU_RAM_AGC_KI_MIN_IF__B 8 -#define SCU_RAM_AGC_KI_MIN_IF__W 4 -#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 -#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x100 - -#define SCU_RAM_AGC_KI_MAX__A 0x831F2C -#define SCU_RAM_AGC_KI_MAX__W 12 -#define SCU_RAM_AGC_KI_MAX__M 0xFFF -#define SCU_RAM_AGC_KI_MAX__PRE 0xFFF - -#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 -#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 -#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF -#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0xF - -#define SCU_RAM_AGC_KI_MAX_RF__B 4 -#define SCU_RAM_AGC_KI_MAX_RF__W 4 -#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 -#define SCU_RAM_AGC_KI_MAX_RF__PRE 0xF0 - -#define SCU_RAM_AGC_KI_MAX_IF__B 8 -#define SCU_RAM_AGC_KI_MAX_IF__W 4 -#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 -#define SCU_RAM_AGC_KI_MAX_IF__PRE 0xF00 - - -#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D -#define SCU_RAM_AGC_CLP_SUM__W 16 -#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF -#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 - -#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E -#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 -#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF -#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x8 - -#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F -#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 -#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF -#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x400 - -#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 -#define SCU_RAM_AGC_CLP_CYCLEN__W 16 -#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF -#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x1F4 - -#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 -#define SCU_RAM_AGC_CLP_CYCCNT__W 16 -#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF -#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 - -#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 -#define SCU_RAM_AGC_CLP_DIR_TO__W 8 -#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF -#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0xFC - -#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 -#define SCU_RAM_AGC_CLP_DIR_WD__W 8 -#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF -#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 - -#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 -#define SCU_RAM_AGC_CLP_DIR_STP__W 16 -#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF -#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x1 - -#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 -#define SCU_RAM_AGC_SNS_SUM__W 16 -#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF -#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 - -#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 -#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 -#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF -#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x8 - -#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 -#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 -#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF -#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x400 - -#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 -#define SCU_RAM_AGC_SNS_CYCCNT__W 16 -#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF -#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 - -#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 -#define SCU_RAM_AGC_SNS_DIR_TO__W 8 -#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF -#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0xFC - -#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A -#define SCU_RAM_AGC_SNS_DIR_WD__W 8 -#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF -#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 - -#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B -#define SCU_RAM_AGC_SNS_DIR_STP__W 16 -#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF -#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x1 - -#define SCU_RAM_AGC_INGAIN__A 0x831F3C -#define SCU_RAM_AGC_INGAIN__W 16 -#define SCU_RAM_AGC_INGAIN__M 0xFFFF -#define SCU_RAM_AGC_INGAIN__PRE 0x708 - -#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D -#define SCU_RAM_AGC_INGAIN_TGT__W 15 -#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF -#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x708 - -#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E -#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 -#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF -#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x708 - -#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F -#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 -#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF -#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x3FFF - -#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 -#define SCU_RAM_AGC_IF_IACCU_HI__W 16 -#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF -#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 - -#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 -#define SCU_RAM_AGC_IF_IACCU_LO__W 8 -#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF -#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 - -#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF -#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x2008 - -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 - -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x251C - -#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 -#define SCU_RAM_AGC_RF_IACCU_HI__W 16 -#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF -#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 - -#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 -#define SCU_RAM_AGC_RF_IACCU_LO__W 8 -#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF -#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 - -#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 -#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 -#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF -#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 -#define SCU_RAM_ATV_STANDARD__A 0x831F48 -#define SCU_RAM_ATV_STANDARD__W 12 -#define SCU_RAM_ATV_STANDARD__M 0xFFF -#define SCU_RAM_ATV_STANDARD__PRE 0x2 - -#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 -#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 -#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF -#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x2 -#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 -#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 -#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 -#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 -#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 -#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 -#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA -#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 - -#define SCU_RAM_ATV_DETECT__A 0x831F49 -#define SCU_RAM_ATV_DETECT__W 1 -#define SCU_RAM_ATV_DETECT__M 0x1 -#define SCU_RAM_ATV_DETECT__PRE 0x0 - -#define SCU_RAM_ATV_DETECT_DETECT__B 0 -#define SCU_RAM_ATV_DETECT_DETECT__W 1 -#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 -#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 -#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0 -#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1 - -#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A -#define SCU_RAM_ATV_DETECT_TH__W 8 -#define SCU_RAM_ATV_DETECT_TH__M 0xFF -#define SCU_RAM_ATV_DETECT_TH__PRE 0x7F - -#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 -#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 -#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF -#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x7F - -#define SCU_RAM_ATV_LOCK__A 0x831F4B -#define SCU_RAM_ATV_LOCK__W 2 -#define SCU_RAM_ATV_LOCK__M 0x3 -#define SCU_RAM_ATV_LOCK__PRE 0x0 - -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 - -#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 -#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 -#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 -#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 -#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 -#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 - -#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C -#define SCU_RAM_ATV_CR_LOCK__W 11 -#define SCU_RAM_ATV_CR_LOCK__M 0x7FF -#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 - -#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 -#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 -#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF -#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 - -#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D -#define SCU_RAM_ATV_AGC_MODE__W 8 -#define SCU_RAM_ATV_AGC_MODE__M 0xFF -#define SCU_RAM_ATV_AGC_MODE__PRE 0x50 - -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 - -#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 -#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 -#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 -#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 -#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 -#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 - -#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x10 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 - -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x40 -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 - -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 - - -#define SCU_RAM_ATV_RSV_01__A 0x831F4E -#define SCU_RAM_ATV_RSV_01__W 16 -#define SCU_RAM_ATV_RSV_01__M 0xFFFF -#define SCU_RAM_ATV_RSV_01__PRE 0x0 - -#define SCU_RAM_ATV_RSV_02__A 0x831F4F -#define SCU_RAM_ATV_RSV_02__W 16 -#define SCU_RAM_ATV_RSV_02__M 0xFFFF -#define SCU_RAM_ATV_RSV_02__PRE 0x0 - -#define SCU_RAM_ATV_RSV_03__A 0x831F50 -#define SCU_RAM_ATV_RSV_03__W 16 -#define SCU_RAM_ATV_RSV_03__M 0xFFFF -#define SCU_RAM_ATV_RSV_03__PRE 0x0 - -#define SCU_RAM_ATV_RSV_04__A 0x831F51 -#define SCU_RAM_ATV_RSV_04__W 16 -#define SCU_RAM_ATV_RSV_04__M 0xFFFF -#define SCU_RAM_ATV_RSV_04__PRE 0x0 -#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 -#define SCU_RAM_ATV_FAGC_TH_RED__W 8 -#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF -#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0xA - -#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 -#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 -#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF -#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0xA - -#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 -#define SCU_RAM_ATV_AMS_MAX_REF__W 11 -#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF -#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x2BC - -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x2BC -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A - -#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 -#define SCU_RAM_ATV_ACT_AMX__W 11 -#define SCU_RAM_ATV_ACT_AMX__M 0x7FF -#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 - -#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 -#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 -#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF -#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 - -#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 -#define SCU_RAM_ATV_ACT_AMI__W 11 -#define SCU_RAM_ATV_ACT_AMI__M 0x7FF -#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 - -#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 -#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 -#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF -#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 - -#define SCU_RAM_ATV_BPC_REF_PERIOD__A 0x831F56 -#define SCU_RAM_ATV_BPC_REF_PERIOD__W 16 -#define SCU_RAM_ATV_BPC_REF_PERIOD__M 0xFFFF -#define SCU_RAM_ATV_BPC_REF_PERIOD__PRE 0x0 - -#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__B 0 -#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__W 16 -#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__M 0xFFFF -#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__PRE 0x0 - -#define SCU_RAM_ATV_BPC_REF_CNT__A 0x831F57 -#define SCU_RAM_ATV_BPC_REF_CNT__W 16 -#define SCU_RAM_ATV_BPC_REF_CNT__M 0xFFFF -#define SCU_RAM_ATV_BPC_REF_CNT__PRE 0x0 - -#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__B 0 -#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__W 16 -#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__M 0xFFFF -#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__PRE 0x0 - - -#define SCU_RAM_ATV_RSV_07__A 0x831F58 -#define SCU_RAM_ATV_RSV_07__W 16 -#define SCU_RAM_ATV_RSV_07__M 0xFFFF -#define SCU_RAM_ATV_RSV_07__PRE 0x0 - -#define SCU_RAM_ATV_RSV_08__A 0x831F59 -#define SCU_RAM_ATV_RSV_08__W 16 -#define SCU_RAM_ATV_RSV_08__M 0xFFFF -#define SCU_RAM_ATV_RSV_08__PRE 0x0 - -#define SCU_RAM_ATV_RSV_09__A 0x831F5A -#define SCU_RAM_ATV_RSV_09__W 16 -#define SCU_RAM_ATV_RSV_09__M 0xFFFF -#define SCU_RAM_ATV_RSV_09__PRE 0x0 - -#define SCU_RAM_ATV_RSV_10__A 0x831F5B -#define SCU_RAM_ATV_RSV_10__W 16 -#define SCU_RAM_ATV_RSV_10__M 0xFFFF -#define SCU_RAM_ATV_RSV_10__PRE 0x0 - -#define SCU_RAM_ATV_RSV_11__A 0x831F5C -#define SCU_RAM_ATV_RSV_11__W 16 -#define SCU_RAM_ATV_RSV_11__M 0xFFFF -#define SCU_RAM_ATV_RSV_11__PRE 0x0 - -#define SCU_RAM_ATV_RSV_12__A 0x831F5D -#define SCU_RAM_ATV_RSV_12__W 16 -#define SCU_RAM_ATV_RSV_12__M 0xFFFF -#define SCU_RAM_ATV_RSV_12__PRE 0x0 -#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E -#define SCU_RAM_ATV_VID_GAIN_HI__W 16 -#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF -#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x1000 - -#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 -#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 -#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF -#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x1000 - -#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F -#define SCU_RAM_ATV_VID_GAIN_LO__W 8 -#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF -#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 - -#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 -#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 -#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF -#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 - - -#define SCU_RAM_ATV_RSV_13__A 0x831F60 -#define SCU_RAM_ATV_RSV_13__W 16 -#define SCU_RAM_ATV_RSV_13__M 0xFFFF -#define SCU_RAM_ATV_RSV_13__PRE 0x0 - -#define SCU_RAM_ATV_RSV_14__A 0x831F61 -#define SCU_RAM_ATV_RSV_14__W 16 -#define SCU_RAM_ATV_RSV_14__M 0xFFFF -#define SCU_RAM_ATV_RSV_14__PRE 0x0 - -#define SCU_RAM_ATV_RSV_15__A 0x831F62 -#define SCU_RAM_ATV_RSV_15__W 16 -#define SCU_RAM_ATV_RSV_15__M 0xFFFF -#define SCU_RAM_ATV_RSV_15__PRE 0x0 - -#define SCU_RAM_ATV_RSV_16__A 0x831F63 -#define SCU_RAM_ATV_RSV_16__W 16 -#define SCU_RAM_ATV_RSV_16__M 0xFFFF -#define SCU_RAM_ATV_RSV_16__PRE 0x0 -#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 -#define SCU_RAM_ATV_AAGC_CNT__W 8 -#define SCU_RAM_ATV_AAGC_CNT__M 0xFF -#define SCU_RAM_ATV_AAGC_CNT__PRE 0x7 - -#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 -#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 -#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF -#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x7 - -#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 -#define SCU_RAM_ATV_SIF_GAIN__W 11 -#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF -#define SCU_RAM_ATV_SIF_GAIN__PRE 0x80 - -#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 -#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 -#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF -#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x80 - - -#define SCU_RAM_ATV_RSV_17__A 0x831F66 -#define SCU_RAM_ATV_RSV_17__W 16 -#define SCU_RAM_ATV_RSV_17__M 0xFFFF -#define SCU_RAM_ATV_RSV_17__PRE 0x0 - -#define SCU_RAM_ATV_RSV_18__A 0x831F67 -#define SCU_RAM_ATV_RSV_18__W 16 -#define SCU_RAM_ATV_RSV_18__M 0xFFFF -#define SCU_RAM_ATV_RSV_18__PRE 0x0 - -#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 -#define SCU_RAM_ATV_RATE_OFS__W 12 -#define SCU_RAM_ATV_RATE_OFS__M 0xFFF -#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 - -#define SCU_RAM_ATV_LO_INCR__A 0x831F69 -#define SCU_RAM_ATV_LO_INCR__W 12 -#define SCU_RAM_ATV_LO_INCR__M 0xFFF -#define SCU_RAM_ATV_LO_INCR__PRE 0x0 - -#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A -#define SCU_RAM_ATV_IIR_CRIT__W 12 -#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF -#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 - -#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B -#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 -#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF -#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 - -#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C -#define SCU_RAM_ATV_DEF_LO_INCR__W 12 -#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF -#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 - -#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D -#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 -#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 -#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 -#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E -#define SCU_RAM_ATV_MOD_CONTROL__W 12 -#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF -#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 - -#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__W 12 -#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__M 0xFFF -#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__PRE 0x0 - -#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F -#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 -#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF -#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x667 - -#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__W 12 -#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF -#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__PRE 0x667 - -#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 -#define SCU_RAM_ATV_BPC_KI_MAX__W 12 -#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF -#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x337 - -#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__W 12 -#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__M 0xFFF -#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__PRE 0x337 - -#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 -#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 -#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF -#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x447 - -#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__W 12 -#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF -#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__PRE 0x447 - -#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 -#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 -#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x225 - -#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 -#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 -#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x225 - -#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 -#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 -#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF -#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x14 - -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x14 -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 - -#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 -#define SCU_RAM_QAM_PARAM_ANNEX__W 2 -#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 -#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x1 - -#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x1 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 - -#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 -#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 -#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 -#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x5 - -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x5 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 - -#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 -#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 -#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF -#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x1 - -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x1 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF - -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 - -#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 -#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 -#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF -#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x13 - -#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 -#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 -#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF -#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x13 - -#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A -#define SCU_RAM_QAM_WR_RSV_0__W 16 -#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D -#define SCU_RAM_QAM_WR_RSV_5__W 16 -#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E -#define SCU_RAM_QAM_WR_RSV_6__W 16 -#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F -#define SCU_RAM_QAM_WR_RSV_7__W 16 -#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 -#define SCU_RAM_QAM_WR_RSV_8__W 16 -#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 -#define SCU_RAM_QAM_WR_RSV_9__W 16 -#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 -#define SCU_RAM_QAM_WR_RSV_10__W 16 -#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 -#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 -#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF -#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x258 - -#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 -#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 -#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x258 -#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 - -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B -#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 -#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF -#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 - -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 - -#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D -#define SCU_RAM_QAM_FSM_ATH__W 16 -#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF -#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 - -#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 -#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 -#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_RTH__W 16 -#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_RTH__PRE 0x4B - -#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x4B -#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C -#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 -#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E -#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 -#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D - -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_FTH__W 16 -#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_FTH__PRE 0x3C - -#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x3C -#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 -#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E -#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E -#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 -#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 - -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_PTH__W 16 -#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_PTH__PRE 0x64 - -#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x64 -#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 -#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 -#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C -#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 -#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 - -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_MTH__W 16 -#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_MTH__PRE 0x6E - -#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x6E -#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A -#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 -#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 -#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C -#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 - -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_CTH__W 16 -#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_CTH__PRE 0x50 - -#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x50 -#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 -#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C -#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C -#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C -#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C - -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_QTH__W 16 -#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_QTH__PRE 0x96 - -#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x96 -#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 -#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA -#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 -#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C -#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 - -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 -#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF -#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x28 - -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x28 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 - -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 -#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF -#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0xF - -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0xF -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 - -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 -#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF -#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x4 - -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x4 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 - -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_COARSE__W 16 -#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x28 - -#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x28 - -#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 -#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x28 - -#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x28 - -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CA_FINE__W 16 -#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CA_FINE__PRE 0xF - -#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0xF - -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_COARSE__W 16 -#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x64 - -#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x64 - -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x1E - -#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x1E - -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_FINE__W 16 -#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x5 - -#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x5 - -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_COARSE__W 16 -#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x32 - -#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x32 - -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x1E - -#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x1E - -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_FINE__W 16 -#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x5 - -#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x5 - -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_COARSE__W 16 -#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x18 - -#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x18 - -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x18 - -#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x18 - -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_FINE__W 16 -#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_EP_FINE__PRE 0xC - -#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0xC - -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_COARSE__W 16 -#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x10 - -#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x10 - -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x10 - -#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x10 - -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_FINE__W 16 -#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_EI_FINE__PRE 0xC - -#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0xC - -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 - -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 - -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 - -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 - -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 - -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 - -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA - -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA - -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA - -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA - -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 - -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 - -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SCU_RAM_QAM_SL_SIG_POWER__W 16 -#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF -#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0xAA00 - -#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 -#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 -#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF -#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0xAA00 - -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 - -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE - -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A - -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 - -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 - -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF - -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 - -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 - -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 - -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D - -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 - -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 - -#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 -#define SCU_RAM_QAM_CTL_ENA__W 16 -#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF -#define SCU_RAM_QAM_CTL_ENA__PRE 0x7FF - -#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 -#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 -#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 -#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x1 - -#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 -#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 -#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 -#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x2 - -#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 -#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 -#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 -#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x4 - -#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 -#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 -#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 -#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x8 - -#define SCU_RAM_QAM_CTL_ENA_LC__B 4 -#define SCU_RAM_QAM_CTL_ENA_LC__W 1 -#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 -#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x10 - -#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 -#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 -#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 -#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x20 - -#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 -#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 -#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 -#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x40 - -#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 -#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 -#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 -#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x80 - -#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 -#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 -#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 -#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x100 - -#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 -#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 -#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 -#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x200 - -#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 -#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 -#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 -#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x400 - -#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 -#define SCU_RAM_QAM_WR_RSV_1__W 16 -#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 -#define SCU_RAM_QAM_WR_RSV_2__W 16 -#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 -#define SCU_RAM_QAM_WR_RSV_3__W 16 -#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 - -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x1 - -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x1 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE - -#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 -#define SCU_RAM_QAM_RD_RSV_4__W 16 -#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 - -#define SCU_RAM_QAM_LOCKED__A 0x831FBA -#define SCU_RAM_QAM_LOCKED__W 16 -#define SCU_RAM_QAM_LOCKED__M 0xFFFF -#define SCU_RAM_QAM_LOCKED__PRE 0x0 - -#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 -#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 -#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF -#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 - -#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 -#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 -#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 -#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 -#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 -#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 -#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 -#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 - -#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB -#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 -#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 -#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 -#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 -#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 -#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 -#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 -#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 -#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC -#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 -#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 -#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 -#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 -#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 -#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 -#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 -#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 -#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 -#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 -#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 -#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD -#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 -#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 -#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 -#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE -#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 -#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 -#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 -#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 - -#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF -#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 -#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF -#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 - -#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 -#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 -#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF -#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 - -#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 -#define SCU_RAM_QAM_TASKLETS_RUN__W 16 -#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF -#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 - -#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 -#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 -#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF -#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 -#define SCU_RAM_QAM_RD_RSV_5__W 16 -#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 -#define SCU_RAM_QAM_RD_RSV_6__W 16 -#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 -#define SCU_RAM_QAM_RD_RSV_7__W 16 -#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 -#define SCU_RAM_QAM_RD_RSV_8__W 16 -#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 -#define SCU_RAM_QAM_RD_RSV_9__W 16 -#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 -#define SCU_RAM_QAM_RD_RSV_10__W 16 -#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 - -#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 -#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 -#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF -#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 - -#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 -#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 -#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF -#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA -#define SCU_RAM_QAM_FSM_STATE__W 4 -#define SCU_RAM_QAM_FSM_STATE__M 0xF -#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 -#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 -#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF -#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 -#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 -#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 -#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 -#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 -#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 -#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 -#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 - -#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB -#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 -#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF -#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC -#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 13 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FFF -#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__B 9 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__M 0x200 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__B 10 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__M 0x400 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__B 11 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__M 0x800 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__B 12 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__M 0x1000 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__PRE 0x0 - -#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD -#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 -#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF -#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x46 - -#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 -#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 -#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x46 - -#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE -#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 -#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF -#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x1E - -#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 -#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 -#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x1E - -#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF -#define SCU_RAM_QAM_ERR_STATE__W 4 -#define SCU_RAM_QAM_ERR_STATE__M 0xF -#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 - -#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 -#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 -#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF -#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 -#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 -#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 -#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 -#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 -#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 -#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 -#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 -#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 - -#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 -#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 -#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF -#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 - -#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 -#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 -#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 -#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 - -#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 -#define SCU_RAM_QAM_EQ_LOCK__W 1 -#define SCU_RAM_QAM_EQ_LOCK__M 0x1 -#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 - -#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 -#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 -#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 -#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 - -#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 -#define SCU_RAM_QAM_EQ_STATE__W 16 -#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF -#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 - -#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 -#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 -#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF -#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 -#define SCU_RAM_QAM_RD_RSV_0__W 16 -#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 -#define SCU_RAM_QAM_RD_RSV_1__W 16 -#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 -#define SCU_RAM_QAM_RD_RSV_2__W 16 -#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 -#define SCU_RAM_QAM_RD_RSV_3__W 16 -#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 - - -#define SCU_RAM_FREE_8151__A 0x831FD7 -#define SCU_RAM_FREE_8151__W 16 -#define SCU_RAM_FREE_8151__M 0xFFFF -#define SCU_RAM_FREE_8151__PRE 0x0 - -#define SCU_RAM_FREE_8152__A 0x831FD8 -#define SCU_RAM_FREE_8152__W 16 -#define SCU_RAM_FREE_8152__M 0xFFFF -#define SCU_RAM_FREE_8152__PRE 0x0 - -#define SCU_RAM_FREE_8153__A 0x831FD9 -#define SCU_RAM_FREE_8153__W 16 -#define SCU_RAM_FREE_8153__M 0xFFFF -#define SCU_RAM_FREE_8153__PRE 0x0 - -#define SCU_RAM_FREE_8154__A 0x831FDA -#define SCU_RAM_FREE_8154__W 16 -#define SCU_RAM_FREE_8154__M 0xFFFF -#define SCU_RAM_FREE_8154__PRE 0x0 - -#define SCU_RAM_FREE_8155__A 0x831FDB -#define SCU_RAM_FREE_8155__W 16 -#define SCU_RAM_FREE_8155__M 0xFFFF -#define SCU_RAM_FREE_8155__PRE 0x0 - -#define SCU_RAM_FREE_8156__A 0x831FDC -#define SCU_RAM_FREE_8156__W 16 -#define SCU_RAM_FREE_8156__M 0xFFFF -#define SCU_RAM_FREE_8156__PRE 0x0 - -#define SCU_RAM_FREE_8157__A 0x831FDD -#define SCU_RAM_FREE_8157__W 16 -#define SCU_RAM_FREE_8157__M 0xFFFF -#define SCU_RAM_FREE_8157__PRE 0x0 - -#define SCU_RAM_FREE_8158__A 0x831FDE -#define SCU_RAM_FREE_8158__W 16 -#define SCU_RAM_FREE_8158__M 0xFFFF -#define SCU_RAM_FREE_8158__PRE 0x0 - -#define SCU_RAM_FREE_8159__A 0x831FDF -#define SCU_RAM_FREE_8159__W 16 -#define SCU_RAM_FREE_8159__M 0xFFFF -#define SCU_RAM_FREE_8159__PRE 0x0 - -#define SCU_RAM_FREE_8160__A 0x831FE0 -#define SCU_RAM_FREE_8160__W 16 -#define SCU_RAM_FREE_8160__M 0xFFFF -#define SCU_RAM_FREE_8160__PRE 0x0 - -#define SCU_RAM_FREE_8161__A 0x831FE1 -#define SCU_RAM_FREE_8161__W 16 -#define SCU_RAM_FREE_8161__M 0xFFFF -#define SCU_RAM_FREE_8161__PRE 0x0 - -#define SCU_RAM_FREE_8162__A 0x831FE2 -#define SCU_RAM_FREE_8162__W 16 -#define SCU_RAM_FREE_8162__M 0xFFFF -#define SCU_RAM_FREE_8162__PRE 0x0 - -#define SCU_RAM_FREE_8163__A 0x831FE3 -#define SCU_RAM_FREE_8163__W 16 -#define SCU_RAM_FREE_8163__M 0xFFFF -#define SCU_RAM_FREE_8163__PRE 0x0 - -#define SCU_RAM_FREE_8164__A 0x831FE4 -#define SCU_RAM_FREE_8164__W 16 -#define SCU_RAM_FREE_8164__M 0xFFFF -#define SCU_RAM_FREE_8164__PRE 0x0 - -#define SCU_RAM_FREE_8165__A 0x831FE5 -#define SCU_RAM_FREE_8165__W 16 -#define SCU_RAM_FREE_8165__M 0xFFFF -#define SCU_RAM_FREE_8165__PRE 0x0 - -#define SCU_RAM_FREE_8166__A 0x831FE6 -#define SCU_RAM_FREE_8166__W 16 -#define SCU_RAM_FREE_8166__M 0xFFFF -#define SCU_RAM_FREE_8166__PRE 0x0 - -#define SCU_RAM_FREE_8167__A 0x831FE7 -#define SCU_RAM_FREE_8167__W 16 -#define SCU_RAM_FREE_8167__M 0xFFFF -#define SCU_RAM_FREE_8167__PRE 0x0 - -#define SCU_RAM_FREE_8168__A 0x831FE8 -#define SCU_RAM_FREE_8168__W 16 -#define SCU_RAM_FREE_8168__M 0xFFFF -#define SCU_RAM_FREE_8168__PRE 0x0 - -#define SCU_RAM_FREE_8169__A 0x831FE9 -#define SCU_RAM_FREE_8169__W 16 -#define SCU_RAM_FREE_8169__M 0xFFFF -#define SCU_RAM_FREE_8169__PRE 0x0 - -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x1E - -#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB -#define SCU_RAM_DRIVER_VER_HI__W 16 -#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF -#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 - -#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC -#define SCU_RAM_DRIVER_VER_LO__W 16 -#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF -#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 - -#define SCU_RAM_PARAM_15__A 0x831FED -#define SCU_RAM_PARAM_15__W 16 -#define SCU_RAM_PARAM_15__M 0xFFFF -#define SCU_RAM_PARAM_15__PRE 0x0 - -#define SCU_RAM_PARAM_14__A 0x831FEE -#define SCU_RAM_PARAM_14__W 16 -#define SCU_RAM_PARAM_14__M 0xFFFF -#define SCU_RAM_PARAM_14__PRE 0x0 - -#define SCU_RAM_PARAM_13__A 0x831FEF -#define SCU_RAM_PARAM_13__W 16 -#define SCU_RAM_PARAM_13__M 0xFFFF -#define SCU_RAM_PARAM_13__PRE 0x0 - -#define SCU_RAM_PARAM_12__A 0x831FF0 -#define SCU_RAM_PARAM_12__W 16 -#define SCU_RAM_PARAM_12__M 0xFFFF -#define SCU_RAM_PARAM_12__PRE 0x0 - -#define SCU_RAM_PARAM_11__A 0x831FF1 -#define SCU_RAM_PARAM_11__W 16 -#define SCU_RAM_PARAM_11__M 0xFFFF -#define SCU_RAM_PARAM_11__PRE 0x0 - -#define SCU_RAM_PARAM_10__A 0x831FF2 -#define SCU_RAM_PARAM_10__W 16 -#define SCU_RAM_PARAM_10__M 0xFFFF -#define SCU_RAM_PARAM_10__PRE 0x0 - -#define SCU_RAM_PARAM_9__A 0x831FF3 -#define SCU_RAM_PARAM_9__W 16 -#define SCU_RAM_PARAM_9__M 0xFFFF -#define SCU_RAM_PARAM_9__PRE 0x0 - -#define SCU_RAM_PARAM_8__A 0x831FF4 -#define SCU_RAM_PARAM_8__W 16 -#define SCU_RAM_PARAM_8__M 0xFFFF -#define SCU_RAM_PARAM_8__PRE 0x0 - -#define SCU_RAM_PARAM_7__A 0x831FF5 -#define SCU_RAM_PARAM_7__W 16 -#define SCU_RAM_PARAM_7__M 0xFFFF -#define SCU_RAM_PARAM_7__PRE 0x0 - -#define SCU_RAM_PARAM_6__A 0x831FF6 -#define SCU_RAM_PARAM_6__W 16 -#define SCU_RAM_PARAM_6__M 0xFFFF -#define SCU_RAM_PARAM_6__PRE 0x0 - -#define SCU_RAM_PARAM_5__A 0x831FF7 -#define SCU_RAM_PARAM_5__W 16 -#define SCU_RAM_PARAM_5__M 0xFFFF -#define SCU_RAM_PARAM_5__PRE 0x0 - -#define SCU_RAM_PARAM_4__A 0x831FF8 -#define SCU_RAM_PARAM_4__W 16 -#define SCU_RAM_PARAM_4__M 0xFFFF -#define SCU_RAM_PARAM_4__PRE 0x0 - -#define SCU_RAM_PARAM_3__A 0x831FF9 -#define SCU_RAM_PARAM_3__W 16 -#define SCU_RAM_PARAM_3__M 0xFFFF -#define SCU_RAM_PARAM_3__PRE 0x0 - -#define SCU_RAM_PARAM_2__A 0x831FFA -#define SCU_RAM_PARAM_2__W 16 -#define SCU_RAM_PARAM_2__M 0xFFFF -#define SCU_RAM_PARAM_2__PRE 0x0 - -#define SCU_RAM_PARAM_1__A 0x831FFB -#define SCU_RAM_PARAM_1__W 16 -#define SCU_RAM_PARAM_1__M 0xFFFF -#define SCU_RAM_PARAM_1__PRE 0x0 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 - - -#define SCU_RAM_PARAM_0__A 0x831FFC -#define SCU_RAM_PARAM_0__W 16 -#define SCU_RAM_PARAM_0__M 0xFFFF -#define SCU_RAM_PARAM_0__PRE 0x0 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 -#define SCU_RAM_PARAM_0_RESULT_OK 0x0 -#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF -#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE -#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD -#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC - - -#define SCU_RAM_COMMAND__A 0x831FFD -#define SCU_RAM_COMMAND__W 16 -#define SCU_RAM_COMMAND__M 0xFFFF -#define SCU_RAM_COMMAND__PRE 0x0 -#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 -#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 -#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 -#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 -#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 -#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 -#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 -#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 -#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 -#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 -#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 -#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 -#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 -#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 -#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 -#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 -#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 -#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 -#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 -#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 -#define SCU_RAM_COMMAND_CMD_DEBUG_ATV_TIMINGS 0x85 -#define SCU_RAM_COMMAND_CMD_DEBUG_SET_IRQ_PRI 0x86 -#define SCU_RAM_COMMAND_CMD_DEBUG_GET_PSW 0x87 -#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF -#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE -#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD -#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 -#define SCU_RAM_COMMAND_CMD_AUX_ADC_COMP_RESTART 0xC1 - -#define SCU_RAM_COMMAND_STANDARD__B 8 -#define SCU_RAM_COMMAND_STANDARD__W 8 -#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 -#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 -#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 -#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 -#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 -#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 -#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 - -#define SCU_RAM_VERSION_HI__A 0x831FFE -#define SCU_RAM_VERSION_HI__W 16 -#define SCU_RAM_VERSION_HI__M 0xFFFF -#define SCU_RAM_VERSION_HI__PRE 0x0 - -#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 - -#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 - -#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 - -#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 -#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 -#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF -#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 - -#define SCU_RAM_VERSION_LO__A 0x831FFF -#define SCU_RAM_VERSION_LO__W 16 -#define SCU_RAM_VERSION_LO__M 0xFFFF -#define SCU_RAM_VERSION_LO__PRE 0x0 - -#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 -#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 -#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 -#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 - -#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 -#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 -#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 -#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 - -#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 -#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 -#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 -#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 - -#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 -#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 -#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF -#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 - - - - - -#define SIO_COMM_EXEC__A 0x400000 -#define SIO_COMM_EXEC__W 2 -#define SIO_COMM_EXEC__M 0x3 -#define SIO_COMM_EXEC__PRE 0x0 -#define SIO_COMM_EXEC_STOP 0x0 -#define SIO_COMM_EXEC_ACTIVE 0x1 -#define SIO_COMM_EXEC_HOLD 0x2 - -#define SIO_COMM_STATE__A 0x400001 -#define SIO_COMM_STATE__W 16 -#define SIO_COMM_STATE__M 0xFFFF -#define SIO_COMM_STATE__PRE 0x0 -#define SIO_COMM_MB__A 0x400002 -#define SIO_COMM_MB__W 16 -#define SIO_COMM_MB__M 0xFFFF -#define SIO_COMM_MB__PRE 0x0 -#define SIO_COMM_INT_REQ__A 0x400003 -#define SIO_COMM_INT_REQ__W 16 -#define SIO_COMM_INT_REQ__M 0xFFFF -#define SIO_COMM_INT_REQ__PRE 0x0 - -#define SIO_COMM_INT_REQ_HI_REQ__B 0 -#define SIO_COMM_INT_REQ_HI_REQ__W 1 -#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 -#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 - -#define SIO_COMM_INT_REQ_SA_REQ__B 1 -#define SIO_COMM_INT_REQ_SA_REQ__W 1 -#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 -#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 - -#define SIO_COMM_INT_REQ_BL_REQ__B 2 -#define SIO_COMM_INT_REQ_BL_REQ__W 1 -#define SIO_COMM_INT_REQ_BL_REQ__M 0x4 -#define SIO_COMM_INT_REQ_BL_REQ__PRE 0x0 - -#define SIO_COMM_INT_STA__A 0x400005 -#define SIO_COMM_INT_STA__W 16 -#define SIO_COMM_INT_STA__M 0xFFFF -#define SIO_COMM_INT_STA__PRE 0x0 -#define SIO_COMM_INT_MSK__A 0x400006 -#define SIO_COMM_INT_MSK__W 16 -#define SIO_COMM_INT_MSK__M 0xFFFF -#define SIO_COMM_INT_MSK__PRE 0x0 -#define SIO_COMM_INT_STM__A 0x400007 -#define SIO_COMM_INT_STM__W 16 -#define SIO_COMM_INT_STM__M 0xFFFF -#define SIO_COMM_INT_STM__PRE 0x0 - - - -#define SIO_TOP_COMM_EXEC__A 0x410000 -#define SIO_TOP_COMM_EXEC__W 2 -#define SIO_TOP_COMM_EXEC__M 0x3 -#define SIO_TOP_COMM_EXEC__PRE 0x0 -#define SIO_TOP_COMM_EXEC_STOP 0x0 -#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 -#define SIO_TOP_COMM_EXEC_HOLD 0x2 - - -#define SIO_TOP_COMM_KEY__A 0x41000F -#define SIO_TOP_COMM_KEY__W 16 -#define SIO_TOP_COMM_KEY__M 0xFFFF -#define SIO_TOP_COMM_KEY__PRE 0x0 -#define SIO_TOP_COMM_KEY_KEY 0xFABA - - -#define SIO_TOP_JTAGID_LO__A 0x410012 -#define SIO_TOP_JTAGID_LO__W 16 -#define SIO_TOP_JTAGID_LO__M 0xFFFF -#define SIO_TOP_JTAGID_LO__PRE 0x0 - -#define SIO_TOP_JTAGID_HI__A 0x410013 -#define SIO_TOP_JTAGID_HI__W 16 -#define SIO_TOP_JTAGID_HI__M 0xFFFF -#define SIO_TOP_JTAGID_HI__PRE 0x0 - - - - -#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 -#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 -#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 -#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 -#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 -#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F -#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 - -#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 -#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 -#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 -#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 -#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 -#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 -#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF -#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 -#define SIO_HI_RA_RAM_S0_STATE__W 1 -#define SIO_HI_RA_RAM_S0_STATE__M 0x1 -#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 -#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 -#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 -#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 -#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 -#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF -#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 - -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 - -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 - -#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 -#define SIO_HI_RA_RAM_S0_ADDR__W 16 -#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF -#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 -#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 -#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF -#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 - - -#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 -#define SIO_HI_RA_RAM_S0_CRC__W 16 -#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF -#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 -#define SIO_HI_RA_RAM_S0_BUFFER__W 16 -#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF -#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 -#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 -#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF -#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A -#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 -#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 -#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B -#define SIO_HI_RA_RAM_S0_TEMP0__W 16 -#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF -#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C -#define SIO_HI_RA_RAM_S0_TEMP1__W 16 -#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF -#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D -#define SIO_HI_RA_RAM_S0_OFFSET__W 16 -#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF -#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 -#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 -#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 -#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 -#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 -#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F -#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 - -#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 -#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 -#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 -#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 -#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 -#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 -#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF -#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 -#define SIO_HI_RA_RAM_S1_STATE__W 1 -#define SIO_HI_RA_RAM_S1_STATE__M 0x1 -#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 -#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 -#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 -#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 -#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 -#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF -#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 - -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 - -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 - -#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 -#define SIO_HI_RA_RAM_S1_ADDR__W 16 -#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF -#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 -#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 -#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF -#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 - - -#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 -#define SIO_HI_RA_RAM_S1_CRC__W 16 -#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF -#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 -#define SIO_HI_RA_RAM_S1_BUFFER__W 16 -#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF -#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 -#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 -#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF -#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A -#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 -#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 -#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B -#define SIO_HI_RA_RAM_S1_TEMP0__W 16 -#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF -#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C -#define SIO_HI_RA_RAM_S1_TEMP1__W 16 -#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF -#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D -#define SIO_HI_RA_RAM_S1_OFFSET__W 16 -#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF -#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 -#define SIO_HI_RA_RAM_SEMA__A 0x420030 -#define SIO_HI_RA_RAM_SEMA__W 1 -#define SIO_HI_RA_RAM_SEMA__M 0x1 -#define SIO_HI_RA_RAM_SEMA__PRE 0x0 -#define SIO_HI_RA_RAM_SEMA_FREE 0x0 -#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 - -#define SIO_HI_RA_RAM_RES__A 0x420031 -#define SIO_HI_RA_RAM_RES__W 3 -#define SIO_HI_RA_RAM_RES__M 0x7 -#define SIO_HI_RA_RAM_RES__PRE 0x0 -#define SIO_HI_RA_RAM_RES_OK 0x0 -#define SIO_HI_RA_RAM_RES_ERROR 0x1 -#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 -#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 -#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 -#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 - -#define SIO_HI_RA_RAM_CMD__A 0x420032 -#define SIO_HI_RA_RAM_CMD__W 4 -#define SIO_HI_RA_RAM_CMD__M 0xF -#define SIO_HI_RA_RAM_CMD__PRE 0x0 -#define SIO_HI_RA_RAM_CMD_NULL 0x0 -#define SIO_HI_RA_RAM_CMD_UIO 0x1 -#define SIO_HI_RA_RAM_CMD_RESET 0x2 -#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 -#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 -#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 -#define SIO_HI_RA_RAM_CMD_EXEC 0x6 -#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 -#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 - -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 - -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 - -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 - -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 - -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F - -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 - -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 - -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 - -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 - -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 - -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 - -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 - -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF - -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 - - -#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E -#define SIO_HI_RA_RAM_AB_TEMP__W 16 -#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF -#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 - -#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F -#define SIO_HI_RA_RAM_I2C_CTL__W 16 -#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF -#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 -#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 -#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 -#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 -#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 -#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 -#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 -#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 -#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 -#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 -#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A -#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B -#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C -#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D -#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E -#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F -#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 - - - -#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 -#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 -#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF -#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 -#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 -#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 -#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF -#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 -#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 -#define SIO_HI_IF_RAM_TRP_STK_0__W 12 -#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF -#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 -#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 -#define SIO_HI_IF_RAM_TRP_STK_1__W 12 -#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF -#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 -#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 -#define SIO_HI_IF_RAM_FUN_BASE__W 12 -#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF -#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 - - - -#define SIO_HI_IF_COMM_EXEC__A 0x440000 -#define SIO_HI_IF_COMM_EXEC__W 2 -#define SIO_HI_IF_COMM_EXEC__M 0x3 -#define SIO_HI_IF_COMM_EXEC__PRE 0x0 -#define SIO_HI_IF_COMM_EXEC_STOP 0x0 -#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 -#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 -#define SIO_HI_IF_COMM_EXEC_STEP 0x3 - - -#define SIO_HI_IF_COMM_STATE__A 0x440001 -#define SIO_HI_IF_COMM_STATE__W 10 -#define SIO_HI_IF_COMM_STATE__M 0x3FF -#define SIO_HI_IF_COMM_STATE__PRE 0x0 -#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 -#define SIO_HI_IF_COMM_INT_REQ__W 1 -#define SIO_HI_IF_COMM_INT_REQ__M 0x1 -#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 -#define SIO_HI_IF_COMM_INT_STA__A 0x440005 -#define SIO_HI_IF_COMM_INT_STA__W 1 -#define SIO_HI_IF_COMM_INT_STA__M 0x1 -#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 -#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 -#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 -#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 -#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 - -#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 -#define SIO_HI_IF_COMM_INT_MSK__W 1 -#define SIO_HI_IF_COMM_INT_MSK__M 0x1 -#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 -#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 -#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 -#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 -#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 - -#define SIO_HI_IF_COMM_INT_STM__A 0x440007 -#define SIO_HI_IF_COMM_INT_STM__W 1 -#define SIO_HI_IF_COMM_INT_STM__M 0x1 -#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 -#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 -#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 -#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 -#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 - -#define SIO_HI_IF_STK_0__A 0x440010 -#define SIO_HI_IF_STK_0__W 10 -#define SIO_HI_IF_STK_0__M 0x3FF -#define SIO_HI_IF_STK_0__PRE 0x2 - -#define SIO_HI_IF_STK_0_ADDR__B 0 -#define SIO_HI_IF_STK_0_ADDR__W 10 -#define SIO_HI_IF_STK_0_ADDR__M 0x3FF -#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 - -#define SIO_HI_IF_STK_1__A 0x440011 -#define SIO_HI_IF_STK_1__W 10 -#define SIO_HI_IF_STK_1__M 0x3FF -#define SIO_HI_IF_STK_1__PRE 0x2 -#define SIO_HI_IF_STK_1_ADDR__B 0 -#define SIO_HI_IF_STK_1_ADDR__W 10 -#define SIO_HI_IF_STK_1_ADDR__M 0x3FF -#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 - -#define SIO_HI_IF_STK_2__A 0x440012 -#define SIO_HI_IF_STK_2__W 10 -#define SIO_HI_IF_STK_2__M 0x3FF -#define SIO_HI_IF_STK_2__PRE 0x2 -#define SIO_HI_IF_STK_2_ADDR__B 0 -#define SIO_HI_IF_STK_2_ADDR__W 10 -#define SIO_HI_IF_STK_2_ADDR__M 0x3FF -#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 - -#define SIO_HI_IF_STK_3__A 0x440013 -#define SIO_HI_IF_STK_3__W 10 -#define SIO_HI_IF_STK_3__M 0x3FF -#define SIO_HI_IF_STK_3__PRE 0x2 - -#define SIO_HI_IF_STK_3_ADDR__B 0 -#define SIO_HI_IF_STK_3_ADDR__W 10 -#define SIO_HI_IF_STK_3_ADDR__M 0x3FF -#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 - -#define SIO_HI_IF_BPT_IDX__A 0x44001F -#define SIO_HI_IF_BPT_IDX__W 1 -#define SIO_HI_IF_BPT_IDX__M 0x1 -#define SIO_HI_IF_BPT_IDX__PRE 0x0 - -#define SIO_HI_IF_BPT_IDX_ADDR__B 0 -#define SIO_HI_IF_BPT_IDX_ADDR__W 1 -#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 -#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 - -#define SIO_HI_IF_BPT__A 0x440020 -#define SIO_HI_IF_BPT__W 10 -#define SIO_HI_IF_BPT__M 0x3FF -#define SIO_HI_IF_BPT__PRE 0x2 - -#define SIO_HI_IF_BPT_ADDR__B 0 -#define SIO_HI_IF_BPT_ADDR__W 10 -#define SIO_HI_IF_BPT_ADDR__M 0x3FF -#define SIO_HI_IF_BPT_ADDR__PRE 0x2 - - - -#define SIO_CC_COMM_EXEC__A 0x450000 -#define SIO_CC_COMM_EXEC__W 2 -#define SIO_CC_COMM_EXEC__M 0x3 -#define SIO_CC_COMM_EXEC__PRE 0x0 -#define SIO_CC_COMM_EXEC_STOP 0x0 -#define SIO_CC_COMM_EXEC_ACTIVE 0x1 -#define SIO_CC_COMM_EXEC_HOLD 0x2 - -#define SIO_CC_PLL_MODE__A 0x450010 -#define SIO_CC_PLL_MODE__W 6 -#define SIO_CC_PLL_MODE__M 0x3F -#define SIO_CC_PLL_MODE__PRE 0x0 - -#define SIO_CC_PLL_MODE_FREF_SEL__B 0 -#define SIO_CC_PLL_MODE_FREF_SEL__W 2 -#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 -#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 -#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 -#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 -#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 -#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 - -#define SIO_CC_PLL_MODE_LOCKSEL__B 2 -#define SIO_CC_PLL_MODE_LOCKSEL__W 2 -#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC -#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 - -#define SIO_CC_PLL_MODE_BYPASS__B 4 -#define SIO_CC_PLL_MODE_BYPASS__W 2 -#define SIO_CC_PLL_MODE_BYPASS__M 0x30 -#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 -#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 -#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 -#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 - - -#define SIO_CC_PLL_TEST__A 0x450011 -#define SIO_CC_PLL_TEST__W 8 -#define SIO_CC_PLL_TEST__M 0xFF -#define SIO_CC_PLL_TEST__PRE 0x0 - -#define SIO_CC_PLL_LOCK__A 0x450012 -#define SIO_CC_PLL_LOCK__W 1 -#define SIO_CC_PLL_LOCK__M 0x1 -#define SIO_CC_PLL_LOCK__PRE 0x0 -#define SIO_CC_CLK_TEST__A 0x450013 -#define SIO_CC_CLK_TEST__W 8 -#define SIO_CC_CLK_TEST__M 0xFF -#define SIO_CC_CLK_TEST__PRE 0x0 - -#define SIO_CC_CLK_TEST_SEL1__B 0 -#define SIO_CC_CLK_TEST_SEL1__W 3 -#define SIO_CC_CLK_TEST_SEL1__M 0x7 -#define SIO_CC_CLK_TEST_SEL1__PRE 0x0 - -#define SIO_CC_CLK_TEST_ENAB1__B 3 -#define SIO_CC_CLK_TEST_ENAB1__W 1 -#define SIO_CC_CLK_TEST_ENAB1__M 0x8 -#define SIO_CC_CLK_TEST_ENAB1__PRE 0x0 - -#define SIO_CC_CLK_TEST_SEL2__B 4 -#define SIO_CC_CLK_TEST_SEL2__W 3 -#define SIO_CC_CLK_TEST_SEL2__M 0x70 -#define SIO_CC_CLK_TEST_SEL2__PRE 0x0 - -#define SIO_CC_CLK_TEST_ENAB2__B 7 -#define SIO_CC_CLK_TEST_ENAB2__W 1 -#define SIO_CC_CLK_TEST_ENAB2__M 0x80 -#define SIO_CC_CLK_TEST_ENAB2__PRE 0x0 - -#define SIO_CC_CLK_MODE__A 0x450014 -#define SIO_CC_CLK_MODE__W 7 -#define SIO_CC_CLK_MODE__M 0x7F -#define SIO_CC_CLK_MODE__PRE 0x0 - -#define SIO_CC_CLK_MODE_DELAY__B 0 -#define SIO_CC_CLK_MODE_DELAY__W 4 -#define SIO_CC_CLK_MODE_DELAY__M 0xF -#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 - -#define SIO_CC_CLK_MODE_INVERT__B 4 -#define SIO_CC_CLK_MODE_INVERT__W 1 -#define SIO_CC_CLK_MODE_INVERT__M 0x10 -#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 - -#define SIO_CC_CLK_MODE_OFDM_ALIGN__B 5 -#define SIO_CC_CLK_MODE_OFDM_ALIGN__W 1 -#define SIO_CC_CLK_MODE_OFDM_ALIGN__M 0x20 -#define SIO_CC_CLK_MODE_OFDM_ALIGN__PRE 0x0 - -#define SIO_CC_CLK_MODE_OFDM_DUTYC__B 6 -#define SIO_CC_CLK_MODE_OFDM_DUTYC__W 1 -#define SIO_CC_CLK_MODE_OFDM_DUTYC__M 0x40 -#define SIO_CC_CLK_MODE_OFDM_DUTYC__PRE 0x0 - -#define SIO_CC_PWD_MODE__A 0x450015 -#define SIO_CC_PWD_MODE__W 4 -#define SIO_CC_PWD_MODE__M 0xF -#define SIO_CC_PWD_MODE__PRE 0x0 - -#define SIO_CC_PWD_MODE_LEVEL__B 0 -#define SIO_CC_PWD_MODE_LEVEL__W 3 -#define SIO_CC_PWD_MODE_LEVEL__M 0x7 -#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 -#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 -#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 -#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 -#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 -#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 - -#define SIO_CC_PWD_MODE_USE_LOCK__B 3 -#define SIO_CC_PWD_MODE_USE_LOCK__W 1 -#define SIO_CC_PWD_MODE_USE_LOCK__M 0x8 -#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 - -#define SIO_CC_SOFT_RST__A 0x450016 -#define SIO_CC_SOFT_RST__W 3 -#define SIO_CC_SOFT_RST__M 0x7 -#define SIO_CC_SOFT_RST__PRE 0x0 - -#define SIO_CC_SOFT_RST_OFDM__B 0 -#define SIO_CC_SOFT_RST_OFDM__W 1 -#define SIO_CC_SOFT_RST_OFDM__M 0x1 -#define SIO_CC_SOFT_RST_OFDM__PRE 0x0 - -#define SIO_CC_SOFT_RST_SYS__B 1 -#define SIO_CC_SOFT_RST_SYS__W 1 -#define SIO_CC_SOFT_RST_SYS__M 0x2 -#define SIO_CC_SOFT_RST_SYS__PRE 0x0 - -#define SIO_CC_SOFT_RST_OSC__B 2 -#define SIO_CC_SOFT_RST_OSC__W 1 -#define SIO_CC_SOFT_RST_OSC__M 0x4 -#define SIO_CC_SOFT_RST_OSC__PRE 0x0 - - -#define SIO_CC_UPDATE__A 0x450017 -#define SIO_CC_UPDATE__W 16 -#define SIO_CC_UPDATE__M 0xFFFF -#define SIO_CC_UPDATE__PRE 0x0 -#define SIO_CC_UPDATE_KEY 0xFABA - - - -#define SIO_SA_COMM_EXEC__A 0x460000 -#define SIO_SA_COMM_EXEC__W 2 -#define SIO_SA_COMM_EXEC__M 0x3 -#define SIO_SA_COMM_EXEC__PRE 0x0 -#define SIO_SA_COMM_EXEC_STOP 0x0 -#define SIO_SA_COMM_EXEC_ACTIVE 0x1 -#define SIO_SA_COMM_EXEC_HOLD 0x2 - -#define SIO_SA_COMM_INT_REQ__A 0x460003 -#define SIO_SA_COMM_INT_REQ__W 1 -#define SIO_SA_COMM_INT_REQ__M 0x1 -#define SIO_SA_COMM_INT_REQ__PRE 0x0 -#define SIO_SA_COMM_INT_STA__A 0x460005 -#define SIO_SA_COMM_INT_STA__W 4 -#define SIO_SA_COMM_INT_STA__M 0xF -#define SIO_SA_COMM_INT_STA__PRE 0x0 - -#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 -#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 -#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 -#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 - -#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 -#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 -#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 -#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 - -#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 -#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 -#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 -#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 - -#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 -#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 -#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 -#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 - -#define SIO_SA_COMM_INT_MSK__A 0x460006 -#define SIO_SA_COMM_INT_MSK__W 4 -#define SIO_SA_COMM_INT_MSK__M 0xF -#define SIO_SA_COMM_INT_MSK__PRE 0x0 - -#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 -#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 -#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 -#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 -#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 -#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 -#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 -#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 -#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 -#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 -#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 -#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 -#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_STM__A 0x460007 -#define SIO_SA_COMM_INT_STM__W 4 -#define SIO_SA_COMM_INT_STM__M 0xF -#define SIO_SA_COMM_INT_STM__PRE 0x0 - -#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 -#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 -#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 -#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 -#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 -#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 -#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 -#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 -#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 -#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 -#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 -#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 -#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 - -#define SIO_SA_PRESCALER__A 0x460010 -#define SIO_SA_PRESCALER__W 13 -#define SIO_SA_PRESCALER__M 0x1FFF -#define SIO_SA_PRESCALER__PRE 0x18B7 -#define SIO_SA_TX_DATA0__A 0x460011 -#define SIO_SA_TX_DATA0__W 16 -#define SIO_SA_TX_DATA0__M 0xFFFF -#define SIO_SA_TX_DATA0__PRE 0x0 -#define SIO_SA_TX_DATA1__A 0x460012 -#define SIO_SA_TX_DATA1__W 16 -#define SIO_SA_TX_DATA1__M 0xFFFF -#define SIO_SA_TX_DATA1__PRE 0x0 -#define SIO_SA_TX_DATA2__A 0x460013 -#define SIO_SA_TX_DATA2__W 16 -#define SIO_SA_TX_DATA2__M 0xFFFF -#define SIO_SA_TX_DATA2__PRE 0x0 -#define SIO_SA_TX_DATA3__A 0x460014 -#define SIO_SA_TX_DATA3__W 16 -#define SIO_SA_TX_DATA3__M 0xFFFF -#define SIO_SA_TX_DATA3__PRE 0x0 -#define SIO_SA_TX_LENGTH__A 0x460015 -#define SIO_SA_TX_LENGTH__W 6 -#define SIO_SA_TX_LENGTH__M 0x3F -#define SIO_SA_TX_LENGTH__PRE 0x0 -#define SIO_SA_TX_COMMAND__A 0x460016 -#define SIO_SA_TX_COMMAND__W 2 -#define SIO_SA_TX_COMMAND__M 0x3 -#define SIO_SA_TX_COMMAND__PRE 0x3 - -#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 -#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 -#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 -#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 - -#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 -#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 -#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 -#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 - -#define SIO_SA_TX_STATUS__A 0x460017 -#define SIO_SA_TX_STATUS__W 2 -#define SIO_SA_TX_STATUS__M 0x3 -#define SIO_SA_TX_STATUS__PRE 0x0 - -#define SIO_SA_TX_STATUS_BUSY__B 0 -#define SIO_SA_TX_STATUS_BUSY__W 1 -#define SIO_SA_TX_STATUS_BUSY__M 0x1 -#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 - -#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 -#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 -#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 -#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 - -#define SIO_SA_RX_DATA0__A 0x460018 -#define SIO_SA_RX_DATA0__W 16 -#define SIO_SA_RX_DATA0__M 0xFFFF -#define SIO_SA_RX_DATA0__PRE 0x0 -#define SIO_SA_RX_DATA1__A 0x460019 -#define SIO_SA_RX_DATA1__W 16 -#define SIO_SA_RX_DATA1__M 0xFFFF -#define SIO_SA_RX_DATA1__PRE 0x0 -#define SIO_SA_RX_LENGTH__A 0x46001A -#define SIO_SA_RX_LENGTH__W 6 -#define SIO_SA_RX_LENGTH__M 0x3F -#define SIO_SA_RX_LENGTH__PRE 0x0 -#define SIO_SA_RX_COMMAND__A 0x46001B -#define SIO_SA_RX_COMMAND__W 1 -#define SIO_SA_RX_COMMAND__M 0x1 -#define SIO_SA_RX_COMMAND__PRE 0x1 - -#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 -#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 -#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 -#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 - -#define SIO_SA_RX_STATUS__A 0x46001C -#define SIO_SA_RX_STATUS__W 2 -#define SIO_SA_RX_STATUS__M 0x3 -#define SIO_SA_RX_STATUS__PRE 0x0 - -#define SIO_SA_RX_STATUS_BUSY__B 0 -#define SIO_SA_RX_STATUS_BUSY__W 1 -#define SIO_SA_RX_STATUS_BUSY__M 0x1 -#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 - -#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 -#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 -#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 -#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 - - - -#define SIO_OFDM_SH_COMM_EXEC__A 0x470000 -#define SIO_OFDM_SH_COMM_EXEC__W 2 -#define SIO_OFDM_SH_COMM_EXEC__M 0x3 -#define SIO_OFDM_SH_COMM_EXEC__PRE 0x0 -#define SIO_OFDM_SH_COMM_EXEC_STOP 0x0 -#define SIO_OFDM_SH_COMM_EXEC_ACTIVE 0x1 -#define SIO_OFDM_SH_COMM_EXEC_HOLD 0x2 - -#define SIO_OFDM_SH_COMM_MB__A 0x470002 -#define SIO_OFDM_SH_COMM_MB__W 2 -#define SIO_OFDM_SH_COMM_MB__M 0x3 -#define SIO_OFDM_SH_COMM_MB__PRE 0x0 -#define SIO_OFDM_SH_COMM_MB_CTL__B 0 -#define SIO_OFDM_SH_COMM_MB_CTL__W 1 -#define SIO_OFDM_SH_COMM_MB_CTL__M 0x1 -#define SIO_OFDM_SH_COMM_MB_CTL__PRE 0x0 -#define SIO_OFDM_SH_COMM_MB_CTL_OFF 0x0 -#define SIO_OFDM_SH_COMM_MB_CTL_ON 0x1 -#define SIO_OFDM_SH_COMM_MB_OBS__B 1 -#define SIO_OFDM_SH_COMM_MB_OBS__W 1 -#define SIO_OFDM_SH_COMM_MB_OBS__M 0x2 -#define SIO_OFDM_SH_COMM_MB_OBS__PRE 0x0 -#define SIO_OFDM_SH_COMM_MB_OBS_OFF 0x0 -#define SIO_OFDM_SH_COMM_MB_OBS_ON 0x2 - -#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 -#define SIO_OFDM_SH_OFDM_RING_ENABLE__W 1 -#define SIO_OFDM_SH_OFDM_RING_ENABLE__M 0x1 -#define SIO_OFDM_SH_OFDM_RING_ENABLE__PRE 0x0 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 - -#define SIO_OFDM_SH_OFDM_MB_CONTROL__A 0x470011 -#define SIO_OFDM_SH_OFDM_MB_CONTROL__W 2 -#define SIO_OFDM_SH_OFDM_MB_CONTROL__M 0x3 -#define SIO_OFDM_SH_OFDM_MB_CONTROL__PRE 0x0 - -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__B 0 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__W 1 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__M 0x1 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__PRE 0x0 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OPEN 0x0 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OFDM 0x1 - -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__B 1 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__W 1 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__M 0x2 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__PRE 0x0 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_BYPASS 0x0 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_OFDM 0x2 - -#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 -#define SIO_OFDM_SH_OFDM_RING_STATUS__W 1 -#define SIO_OFDM_SH_OFDM_RING_STATUS__M 0x1 -#define SIO_OFDM_SH_OFDM_RING_STATUS__PRE 0x0 -#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 -#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 - -#define SIO_OFDM_SH_OFDM_MB_FLEN__A 0x470013 -#define SIO_OFDM_SH_OFDM_MB_FLEN__W 3 -#define SIO_OFDM_SH_OFDM_MB_FLEN__M 0x7 -#define SIO_OFDM_SH_OFDM_MB_FLEN__PRE 0x6 -#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__B 0 -#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__W 3 -#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__M 0x7 -#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__PRE 0x6 - - - -#define SIO_BL_COMM_EXEC__A 0x480000 -#define SIO_BL_COMM_EXEC__W 2 -#define SIO_BL_COMM_EXEC__M 0x3 -#define SIO_BL_COMM_EXEC__PRE 0x0 -#define SIO_BL_COMM_EXEC_STOP 0x0 -#define SIO_BL_COMM_EXEC_ACTIVE 0x1 -#define SIO_BL_COMM_EXEC_HOLD 0x2 - -#define SIO_BL_COMM_INT_REQ__A 0x480003 -#define SIO_BL_COMM_INT_REQ__W 1 -#define SIO_BL_COMM_INT_REQ__M 0x1 -#define SIO_BL_COMM_INT_REQ__PRE 0x0 -#define SIO_BL_COMM_INT_STA__A 0x480005 -#define SIO_BL_COMM_INT_STA__W 1 -#define SIO_BL_COMM_INT_STA__M 0x1 -#define SIO_BL_COMM_INT_STA__PRE 0x0 - -#define SIO_BL_COMM_INT_STA_DONE_INT_STA__B 0 -#define SIO_BL_COMM_INT_STA_DONE_INT_STA__W 1 -#define SIO_BL_COMM_INT_STA_DONE_INT_STA__M 0x1 -#define SIO_BL_COMM_INT_STA_DONE_INT_STA__PRE 0x0 - -#define SIO_BL_COMM_INT_MSK__A 0x480006 -#define SIO_BL_COMM_INT_MSK__W 1 -#define SIO_BL_COMM_INT_MSK__M 0x1 -#define SIO_BL_COMM_INT_MSK__PRE 0x0 - -#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__B 0 -#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__W 1 -#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__M 0x1 -#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__PRE 0x0 - -#define SIO_BL_COMM_INT_STM__A 0x480007 -#define SIO_BL_COMM_INT_STM__W 1 -#define SIO_BL_COMM_INT_STM__M 0x1 -#define SIO_BL_COMM_INT_STM__PRE 0x0 - -#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__B 0 -#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__W 1 -#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__M 0x1 -#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__PRE 0x0 - -#define SIO_BL_STATUS__A 0x480010 -#define SIO_BL_STATUS__W 1 -#define SIO_BL_STATUS__M 0x1 -#define SIO_BL_STATUS__PRE 0x0 -#define SIO_BL_MODE__A 0x480011 -#define SIO_BL_MODE__W 1 -#define SIO_BL_MODE__M 0x1 -#define SIO_BL_MODE__PRE 0x1 -#define SIO_BL_MODE_DIRECT 0x0 -#define SIO_BL_MODE_CHAIN 0x1 - -#define SIO_BL_ENABLE__A 0x480012 -#define SIO_BL_ENABLE__W 1 -#define SIO_BL_ENABLE__M 0x1 -#define SIO_BL_ENABLE__PRE 0x0 -#define SIO_BL_ENABLE_OFF 0x0 -#define SIO_BL_ENABLE_ON 0x1 - -#define SIO_BL_TGT_HDR__A 0x480014 -#define SIO_BL_TGT_HDR__W 12 -#define SIO_BL_TGT_HDR__M 0xFFF -#define SIO_BL_TGT_HDR__PRE 0x0 -#define SIO_BL_TGT_HDR_BANK__B 0 -#define SIO_BL_TGT_HDR_BANK__W 6 -#define SIO_BL_TGT_HDR_BANK__M 0x3F -#define SIO_BL_TGT_HDR_BANK__PRE 0x0 -#define SIO_BL_TGT_HDR_BLOCK__B 6 -#define SIO_BL_TGT_HDR_BLOCK__W 6 -#define SIO_BL_TGT_HDR_BLOCK__M 0xFC0 -#define SIO_BL_TGT_HDR_BLOCK__PRE 0x0 - -#define SIO_BL_TGT_ADDR__A 0x480015 -#define SIO_BL_TGT_ADDR__W 16 -#define SIO_BL_TGT_ADDR__M 0xFFFF -#define SIO_BL_TGT_ADDR__PRE 0x0 -#define SIO_BL_SRC_ADDR__A 0x480016 -#define SIO_BL_SRC_ADDR__W 16 -#define SIO_BL_SRC_ADDR__M 0xFFFF -#define SIO_BL_SRC_ADDR__PRE 0x0 -#define SIO_BL_SRC_LEN__A 0x480017 -#define SIO_BL_SRC_LEN__W 16 -#define SIO_BL_SRC_LEN__M 0xFFFF -#define SIO_BL_SRC_LEN__PRE 0x0 - -#define SIO_BL_CHAIN_ADDR__A 0x480018 -#define SIO_BL_CHAIN_ADDR__W 16 -#define SIO_BL_CHAIN_ADDR__M 0xFFFF -#define SIO_BL_CHAIN_ADDR__PRE 0x0 - -#define SIO_BL_CHAIN_LEN__A 0x480019 -#define SIO_BL_CHAIN_LEN__W 4 -#define SIO_BL_CHAIN_LEN__M 0xF -#define SIO_BL_CHAIN_LEN__PRE 0x2 - - - -#define SIO_OFDM_SH_TRB_R0_RAM__A 0x4C0000 - - - -#define SIO_OFDM_SH_TRB_R1_RAM__A 0x4D0000 - - - -#define SIO_BL_ROM__A 0x4E0000 - - - -#define SIO_PDR_COMM_EXEC__A 0x7F0000 -#define SIO_PDR_COMM_EXEC__W 2 -#define SIO_PDR_COMM_EXEC__M 0x3 -#define SIO_PDR_COMM_EXEC__PRE 0x0 -#define SIO_PDR_COMM_EXEC_STOP 0x0 -#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 -#define SIO_PDR_COMM_EXEC_HOLD 0x2 - -#define SIO_PDR_MON_CFG__A 0x7F0010 -#define SIO_PDR_MON_CFG__W 4 -#define SIO_PDR_MON_CFG__M 0xF -#define SIO_PDR_MON_CFG__PRE 0x0 - -#define SIO_PDR_MON_CFG_OSEL__B 0 -#define SIO_PDR_MON_CFG_OSEL__W 1 -#define SIO_PDR_MON_CFG_OSEL__M 0x1 -#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 - -#define SIO_PDR_MON_CFG_IACT__B 1 -#define SIO_PDR_MON_CFG_IACT__W 1 -#define SIO_PDR_MON_CFG_IACT__M 0x2 -#define SIO_PDR_MON_CFG_IACT__PRE 0x0 - -#define SIO_PDR_MON_CFG_ISEL__B 2 -#define SIO_PDR_MON_CFG_ISEL__W 1 -#define SIO_PDR_MON_CFG_ISEL__M 0x4 -#define SIO_PDR_MON_CFG_ISEL__PRE 0x0 - -#define SIO_PDR_MON_CFG_INV_CLK__B 3 -#define SIO_PDR_MON_CFG_INV_CLK__W 1 -#define SIO_PDR_MON_CFG_INV_CLK__M 0x8 -#define SIO_PDR_MON_CFG_INV_CLK__PRE 0x0 - -#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 -#define SIO_PDR_SMA_RX_SEL__W 4 -#define SIO_PDR_SMA_RX_SEL__M 0xF -#define SIO_PDR_SMA_RX_SEL__PRE 0x0 - -#define SIO_PDR_SMA_RX_SEL_SEL__B 0 -#define SIO_PDR_SMA_RX_SEL_SEL__W 4 -#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF -#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 - -#define SIO_PDR_SILENT__A 0x7F0013 -#define SIO_PDR_SILENT__W 13 -#define SIO_PDR_SILENT__M 0x1FFF -#define SIO_PDR_SILENT__PRE 0x0 - -#define SIO_PDR_SILENT_I2S_WS__B 0 -#define SIO_PDR_SILENT_I2S_WS__W 1 -#define SIO_PDR_SILENT_I2S_WS__M 0x1 -#define SIO_PDR_SILENT_I2S_WS__PRE 0x0 - -#define SIO_PDR_SILENT_I2S_DA__B 1 -#define SIO_PDR_SILENT_I2S_DA__W 1 -#define SIO_PDR_SILENT_I2S_DA__M 0x2 -#define SIO_PDR_SILENT_I2S_DA__PRE 0x0 - -#define SIO_PDR_SILENT_I2S_CL__B 2 -#define SIO_PDR_SILENT_I2S_CL__W 1 -#define SIO_PDR_SILENT_I2S_CL__M 0x4 -#define SIO_PDR_SILENT_I2S_CL__PRE 0x0 - -#define SIO_PDR_SILENT_I2C_SCL2__B 3 -#define SIO_PDR_SILENT_I2C_SCL2__W 1 -#define SIO_PDR_SILENT_I2C_SCL2__M 0x8 -#define SIO_PDR_SILENT_I2C_SCL2__PRE 0x0 - -#define SIO_PDR_SILENT_I2C_SDA2__B 4 -#define SIO_PDR_SILENT_I2C_SDA2__W 1 -#define SIO_PDR_SILENT_I2C_SDA2__M 0x10 -#define SIO_PDR_SILENT_I2C_SDA2__PRE 0x0 - -#define SIO_PDR_SILENT_SMA_TX__B 8 -#define SIO_PDR_SILENT_SMA_TX__W 1 -#define SIO_PDR_SILENT_SMA_TX__M 0x100 -#define SIO_PDR_SILENT_SMA_TX__PRE 0x0 - -#define SIO_PDR_SILENT_SMA_RX__B 9 -#define SIO_PDR_SILENT_SMA_RX__W 1 -#define SIO_PDR_SILENT_SMA_RX__M 0x200 -#define SIO_PDR_SILENT_SMA_RX__PRE 0x0 - -#define SIO_PDR_SILENT_GPIO__B 10 -#define SIO_PDR_SILENT_GPIO__W 1 -#define SIO_PDR_SILENT_GPIO__M 0x400 -#define SIO_PDR_SILENT_GPIO__PRE 0x0 - -#define SIO_PDR_SILENT_VSYNC__B 11 -#define SIO_PDR_SILENT_VSYNC__W 1 -#define SIO_PDR_SILENT_VSYNC__M 0x800 -#define SIO_PDR_SILENT_VSYNC__PRE 0x0 - -#define SIO_PDR_SILENT_IRQN__B 12 -#define SIO_PDR_SILENT_IRQN__W 1 -#define SIO_PDR_SILENT_IRQN__M 0x1000 -#define SIO_PDR_SILENT_IRQN__PRE 0x0 - -#define SIO_PDR_UIO_IN_LO__A 0x7F0014 -#define SIO_PDR_UIO_IN_LO__W 16 -#define SIO_PDR_UIO_IN_LO__M 0xFFFF -#define SIO_PDR_UIO_IN_LO__PRE 0x0 -#define SIO_PDR_UIO_IN_LO_DATA__B 0 -#define SIO_PDR_UIO_IN_LO_DATA__W 16 -#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF -#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 - -#define SIO_PDR_UIO_IN_HI__A 0x7F0015 -#define SIO_PDR_UIO_IN_HI__W 14 -#define SIO_PDR_UIO_IN_HI__M 0x3FFF -#define SIO_PDR_UIO_IN_HI__PRE 0x0 -#define SIO_PDR_UIO_IN_HI_DATA__B 0 -#define SIO_PDR_UIO_IN_HI_DATA__W 14 -#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF -#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 - -#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 -#define SIO_PDR_UIO_OUT_LO__W 16 -#define SIO_PDR_UIO_OUT_LO__M 0xFFFF -#define SIO_PDR_UIO_OUT_LO__PRE 0x0 -#define SIO_PDR_UIO_OUT_LO_DATA__B 0 -#define SIO_PDR_UIO_OUT_LO_DATA__W 16 -#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF -#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 - -#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 -#define SIO_PDR_UIO_OUT_HI__W 14 -#define SIO_PDR_UIO_OUT_HI__M 0x3FFF -#define SIO_PDR_UIO_OUT_HI__PRE 0x0 -#define SIO_PDR_UIO_OUT_HI_DATA__B 0 -#define SIO_PDR_UIO_OUT_HI_DATA__W 14 -#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF -#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 - -#define SIO_PDR_PWM1_MODE__A 0x7F0018 -#define SIO_PDR_PWM1_MODE__W 2 -#define SIO_PDR_PWM1_MODE__M 0x3 -#define SIO_PDR_PWM1_MODE__PRE 0x0 -#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 -#define SIO_PDR_PWM1_PRESCALE__W 6 -#define SIO_PDR_PWM1_PRESCALE__M 0x3F -#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 -#define SIO_PDR_PWM1_VALUE__A 0x7F001A -#define SIO_PDR_PWM1_VALUE__W 11 -#define SIO_PDR_PWM1_VALUE__M 0x7FF -#define SIO_PDR_PWM1_VALUE__PRE 0x0 - -#define SIO_PDR_IRQN_SEL__A 0x7F001B -#define SIO_PDR_IRQN_SEL__W 4 -#define SIO_PDR_IRQN_SEL__M 0xF -#define SIO_PDR_IRQN_SEL__PRE 0x3 -#define SIO_PDR_PWM2_MODE__A 0x7F001C -#define SIO_PDR_PWM2_MODE__W 2 -#define SIO_PDR_PWM2_MODE__M 0x3 -#define SIO_PDR_PWM2_MODE__PRE 0x0 -#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D -#define SIO_PDR_PWM2_PRESCALE__W 6 -#define SIO_PDR_PWM2_PRESCALE__M 0x3F -#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 -#define SIO_PDR_PWM2_VALUE__A 0x7F001E -#define SIO_PDR_PWM2_VALUE__W 11 -#define SIO_PDR_PWM2_VALUE__M 0x7FF -#define SIO_PDR_PWM2_VALUE__PRE 0x0 -#define SIO_PDR_OHW_CFG__A 0x7F001F -#define SIO_PDR_OHW_CFG__W 7 -#define SIO_PDR_OHW_CFG__M 0x7F -#define SIO_PDR_OHW_CFG__PRE 0x0 - -#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 -#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 -#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 -#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 - -#define SIO_PDR_OHW_CFG_BYPASS__B 2 -#define SIO_PDR_OHW_CFG_BYPASS__W 1 -#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 -#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 - -#define SIO_PDR_OHW_CFG_ASEL__B 3 -#define SIO_PDR_OHW_CFG_ASEL__W 3 -#define SIO_PDR_OHW_CFG_ASEL__M 0x38 -#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 - -#define SIO_PDR_OHW_CFG_SPEED__B 6 -#define SIO_PDR_OHW_CFG_SPEED__W 1 -#define SIO_PDR_OHW_CFG_SPEED__M 0x40 -#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 - -#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 -#define SIO_PDR_I2S_WS_CFG__W 9 -#define SIO_PDR_I2S_WS_CFG__M 0x1FF -#define SIO_PDR_I2S_WS_CFG__PRE 0x10 -#define SIO_PDR_I2S_WS_CFG_MODE__B 0 -#define SIO_PDR_I2S_WS_CFG_MODE__W 3 -#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 -#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 -#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 -#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 -#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 -#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 -#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2S_WS_CFG_UIO__B 8 -#define SIO_PDR_I2S_WS_CFG_UIO__W 1 -#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 -#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 - -#define SIO_PDR_GPIO_CFG__A 0x7F0021 -#define SIO_PDR_GPIO_CFG__W 9 -#define SIO_PDR_GPIO_CFG__M 0x1FF -#define SIO_PDR_GPIO_CFG__PRE 0x10 -#define SIO_PDR_GPIO_CFG_MODE__B 0 -#define SIO_PDR_GPIO_CFG_MODE__W 3 -#define SIO_PDR_GPIO_CFG_MODE__M 0x7 -#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 -#define SIO_PDR_GPIO_CFG_DRIVE__B 3 -#define SIO_PDR_GPIO_CFG_DRIVE__W 3 -#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 -#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_GPIO_CFG_KEEP__B 6 -#define SIO_PDR_GPIO_CFG_KEEP__W 2 -#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 -#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 -#define SIO_PDR_GPIO_CFG_UIO__B 8 -#define SIO_PDR_GPIO_CFG_UIO__W 1 -#define SIO_PDR_GPIO_CFG_UIO__M 0x100 -#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MSTRT_CFG__A 0x7F0025 -#define SIO_PDR_MSTRT_CFG__W 9 -#define SIO_PDR_MSTRT_CFG__M 0x1FF -#define SIO_PDR_MSTRT_CFG__PRE 0x50 -#define SIO_PDR_MSTRT_CFG_MODE__B 0 -#define SIO_PDR_MSTRT_CFG_MODE__W 3 -#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 -#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 -#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 -#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 -#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 -#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MSTRT_CFG_KEEP__B 6 -#define SIO_PDR_MSTRT_CFG_KEEP__W 2 -#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 -#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MSTRT_CFG_UIO__B 8 -#define SIO_PDR_MSTRT_CFG_UIO__W 1 -#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 -#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MERR_CFG__A 0x7F0026 -#define SIO_PDR_MERR_CFG__W 9 -#define SIO_PDR_MERR_CFG__M 0x1FF -#define SIO_PDR_MERR_CFG__PRE 0x50 -#define SIO_PDR_MERR_CFG_MODE__B 0 -#define SIO_PDR_MERR_CFG_MODE__W 3 -#define SIO_PDR_MERR_CFG_MODE__M 0x7 -#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 -#define SIO_PDR_MERR_CFG_DRIVE__B 3 -#define SIO_PDR_MERR_CFG_DRIVE__W 3 -#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 -#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MERR_CFG_KEEP__B 6 -#define SIO_PDR_MERR_CFG_KEEP__W 2 -#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 -#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MERR_CFG_UIO__B 8 -#define SIO_PDR_MERR_CFG_UIO__W 1 -#define SIO_PDR_MERR_CFG_UIO__M 0x100 -#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MCLK_CFG__A 0x7F0028 -#define SIO_PDR_MCLK_CFG__W 9 -#define SIO_PDR_MCLK_CFG__M 0x1FF -#define SIO_PDR_MCLK_CFG__PRE 0x50 -#define SIO_PDR_MCLK_CFG_MODE__B 0 -#define SIO_PDR_MCLK_CFG_MODE__W 3 -#define SIO_PDR_MCLK_CFG_MODE__M 0x7 -#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 -#define SIO_PDR_MCLK_CFG_DRIVE__B 3 -#define SIO_PDR_MCLK_CFG_DRIVE__W 3 -#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 -#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MCLK_CFG_KEEP__B 6 -#define SIO_PDR_MCLK_CFG_KEEP__W 2 -#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 -#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MCLK_CFG_UIO__B 8 -#define SIO_PDR_MCLK_CFG_UIO__W 1 -#define SIO_PDR_MCLK_CFG_UIO__M 0x100 -#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MVAL_CFG__A 0x7F0029 -#define SIO_PDR_MVAL_CFG__W 9 -#define SIO_PDR_MVAL_CFG__M 0x1FF -#define SIO_PDR_MVAL_CFG__PRE 0x50 -#define SIO_PDR_MVAL_CFG_MODE__B 0 -#define SIO_PDR_MVAL_CFG_MODE__W 3 -#define SIO_PDR_MVAL_CFG_MODE__M 0x7 -#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 -#define SIO_PDR_MVAL_CFG_DRIVE__B 3 -#define SIO_PDR_MVAL_CFG_DRIVE__W 3 -#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 -#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MVAL_CFG_KEEP__B 6 -#define SIO_PDR_MVAL_CFG_KEEP__W 2 -#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 -#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MVAL_CFG_UIO__B 8 -#define SIO_PDR_MVAL_CFG_UIO__W 1 -#define SIO_PDR_MVAL_CFG_UIO__M 0x100 -#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD0_CFG__A 0x7F002A -#define SIO_PDR_MD0_CFG__W 9 -#define SIO_PDR_MD0_CFG__M 0x1FF -#define SIO_PDR_MD0_CFG__PRE 0x50 -#define SIO_PDR_MD0_CFG_MODE__B 0 -#define SIO_PDR_MD0_CFG_MODE__W 3 -#define SIO_PDR_MD0_CFG_MODE__M 0x7 -#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD0_CFG_DRIVE__B 3 -#define SIO_PDR_MD0_CFG_DRIVE__W 3 -#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD0_CFG_KEEP__B 6 -#define SIO_PDR_MD0_CFG_KEEP__W 2 -#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD0_CFG_UIO__B 8 -#define SIO_PDR_MD0_CFG_UIO__W 1 -#define SIO_PDR_MD0_CFG_UIO__M 0x100 -#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD1_CFG__A 0x7F002B -#define SIO_PDR_MD1_CFG__W 9 -#define SIO_PDR_MD1_CFG__M 0x1FF -#define SIO_PDR_MD1_CFG__PRE 0x50 -#define SIO_PDR_MD1_CFG_MODE__B 0 -#define SIO_PDR_MD1_CFG_MODE__W 3 -#define SIO_PDR_MD1_CFG_MODE__M 0x7 -#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD1_CFG_DRIVE__B 3 -#define SIO_PDR_MD1_CFG_DRIVE__W 3 -#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD1_CFG_KEEP__B 6 -#define SIO_PDR_MD1_CFG_KEEP__W 2 -#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD1_CFG_UIO__B 8 -#define SIO_PDR_MD1_CFG_UIO__W 1 -#define SIO_PDR_MD1_CFG_UIO__M 0x100 -#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD2_CFG__A 0x7F002C -#define SIO_PDR_MD2_CFG__W 9 -#define SIO_PDR_MD2_CFG__M 0x1FF -#define SIO_PDR_MD2_CFG__PRE 0x50 -#define SIO_PDR_MD2_CFG_MODE__B 0 -#define SIO_PDR_MD2_CFG_MODE__W 3 -#define SIO_PDR_MD2_CFG_MODE__M 0x7 -#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD2_CFG_DRIVE__B 3 -#define SIO_PDR_MD2_CFG_DRIVE__W 3 -#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD2_CFG_KEEP__B 6 -#define SIO_PDR_MD2_CFG_KEEP__W 2 -#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD2_CFG_UIO__B 8 -#define SIO_PDR_MD2_CFG_UIO__W 1 -#define SIO_PDR_MD2_CFG_UIO__M 0x100 -#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD3_CFG__A 0x7F002D -#define SIO_PDR_MD3_CFG__W 9 -#define SIO_PDR_MD3_CFG__M 0x1FF -#define SIO_PDR_MD3_CFG__PRE 0x50 -#define SIO_PDR_MD3_CFG_MODE__B 0 -#define SIO_PDR_MD3_CFG_MODE__W 3 -#define SIO_PDR_MD3_CFG_MODE__M 0x7 -#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD3_CFG_DRIVE__B 3 -#define SIO_PDR_MD3_CFG_DRIVE__W 3 -#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD3_CFG_KEEP__B 6 -#define SIO_PDR_MD3_CFG_KEEP__W 2 -#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD3_CFG_UIO__B 8 -#define SIO_PDR_MD3_CFG_UIO__W 1 -#define SIO_PDR_MD3_CFG_UIO__M 0x100 -#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD4_CFG__A 0x7F002F -#define SIO_PDR_MD4_CFG__W 9 -#define SIO_PDR_MD4_CFG__M 0x1FF -#define SIO_PDR_MD4_CFG__PRE 0x50 -#define SIO_PDR_MD4_CFG_MODE__B 0 -#define SIO_PDR_MD4_CFG_MODE__W 3 -#define SIO_PDR_MD4_CFG_MODE__M 0x7 -#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD4_CFG_DRIVE__B 3 -#define SIO_PDR_MD4_CFG_DRIVE__W 3 -#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD4_CFG_KEEP__B 6 -#define SIO_PDR_MD4_CFG_KEEP__W 2 -#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD4_CFG_UIO__B 8 -#define SIO_PDR_MD4_CFG_UIO__W 1 -#define SIO_PDR_MD4_CFG_UIO__M 0x100 -#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD5_CFG__A 0x7F0030 -#define SIO_PDR_MD5_CFG__W 9 -#define SIO_PDR_MD5_CFG__M 0x1FF -#define SIO_PDR_MD5_CFG__PRE 0x50 -#define SIO_PDR_MD5_CFG_MODE__B 0 -#define SIO_PDR_MD5_CFG_MODE__W 3 -#define SIO_PDR_MD5_CFG_MODE__M 0x7 -#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD5_CFG_DRIVE__B 3 -#define SIO_PDR_MD5_CFG_DRIVE__W 3 -#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD5_CFG_KEEP__B 6 -#define SIO_PDR_MD5_CFG_KEEP__W 2 -#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD5_CFG_UIO__B 8 -#define SIO_PDR_MD5_CFG_UIO__W 1 -#define SIO_PDR_MD5_CFG_UIO__M 0x100 -#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD6_CFG__A 0x7F0031 -#define SIO_PDR_MD6_CFG__W 9 -#define SIO_PDR_MD6_CFG__M 0x1FF -#define SIO_PDR_MD6_CFG__PRE 0x50 -#define SIO_PDR_MD6_CFG_MODE__B 0 -#define SIO_PDR_MD6_CFG_MODE__W 3 -#define SIO_PDR_MD6_CFG_MODE__M 0x7 -#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD6_CFG_DRIVE__B 3 -#define SIO_PDR_MD6_CFG_DRIVE__W 3 -#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD6_CFG_KEEP__B 6 -#define SIO_PDR_MD6_CFG_KEEP__W 2 -#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD6_CFG_UIO__B 8 -#define SIO_PDR_MD6_CFG_UIO__W 1 -#define SIO_PDR_MD6_CFG_UIO__M 0x100 -#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD7_CFG__A 0x7F0032 -#define SIO_PDR_MD7_CFG__W 9 -#define SIO_PDR_MD7_CFG__M 0x1FF -#define SIO_PDR_MD7_CFG__PRE 0x50 -#define SIO_PDR_MD7_CFG_MODE__B 0 -#define SIO_PDR_MD7_CFG_MODE__W 3 -#define SIO_PDR_MD7_CFG_MODE__M 0x7 -#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD7_CFG_DRIVE__B 3 -#define SIO_PDR_MD7_CFG_DRIVE__W 3 -#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD7_CFG_KEEP__B 6 -#define SIO_PDR_MD7_CFG_KEEP__W 2 -#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD7_CFG_UIO__B 8 -#define SIO_PDR_MD7_CFG_UIO__W 1 -#define SIO_PDR_MD7_CFG_UIO__M 0x100 -#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 -#define SIO_PDR_I2C_SCL1_CFG__W 9 -#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF -#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 -#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 -#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 -#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 -#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 -#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 -#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 -#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 -#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 -#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 -#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 -#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 -#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 -#define SIO_PDR_I2C_SDA1_CFG__W 9 -#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF -#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 -#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 -#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 -#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 -#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 -#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 -#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 -#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 -#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 -#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 -#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 -#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 -#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 - -#define SIO_PDR_VSYNC_CFG__A 0x7F0036 -#define SIO_PDR_VSYNC_CFG__W 9 -#define SIO_PDR_VSYNC_CFG__M 0x1FF -#define SIO_PDR_VSYNC_CFG__PRE 0x10 -#define SIO_PDR_VSYNC_CFG_MODE__B 0 -#define SIO_PDR_VSYNC_CFG_MODE__W 3 -#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 -#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 -#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 -#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 -#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 -#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_VSYNC_CFG_KEEP__B 6 -#define SIO_PDR_VSYNC_CFG_KEEP__W 2 -#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 -#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 -#define SIO_PDR_VSYNC_CFG_UIO__B 8 -#define SIO_PDR_VSYNC_CFG_UIO__W 1 -#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 -#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 - -#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 -#define SIO_PDR_SMA_RX_CFG__W 9 -#define SIO_PDR_SMA_RX_CFG__M 0x1FF -#define SIO_PDR_SMA_RX_CFG__PRE 0x10 -#define SIO_PDR_SMA_RX_CFG_MODE__B 0 -#define SIO_PDR_SMA_RX_CFG_MODE__W 3 -#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 -#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 -#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 -#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 -#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 -#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 -#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 -#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 -#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 -#define SIO_PDR_SMA_RX_CFG_UIO__B 8 -#define SIO_PDR_SMA_RX_CFG_UIO__W 1 -#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 -#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 - -#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 -#define SIO_PDR_SMA_TX_CFG__W 9 -#define SIO_PDR_SMA_TX_CFG__M 0x1FF -#define SIO_PDR_SMA_TX_CFG__PRE 0x90 -#define SIO_PDR_SMA_TX_CFG_MODE__B 0 -#define SIO_PDR_SMA_TX_CFG_MODE__W 3 -#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 -#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 -#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 -#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 -#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 -#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 -#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 -#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 -#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 -#define SIO_PDR_SMA_TX_CFG_UIO__B 8 -#define SIO_PDR_SMA_TX_CFG_UIO__W 1 -#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 -#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F -#define SIO_PDR_I2C_SDA2_CFG__W 9 -#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF -#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 -#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 -#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 -#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 -#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 -#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 -#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 -#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 -#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 -#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 -#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 -#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 -#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 -#define SIO_PDR_I2C_SCL2_CFG__W 9 -#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF -#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 -#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 -#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 -#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 -#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 -#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 -#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 -#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 -#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 -#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 -#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 -#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 -#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 -#define SIO_PDR_I2S_CL_CFG__W 9 -#define SIO_PDR_I2S_CL_CFG__M 0x1FF -#define SIO_PDR_I2S_CL_CFG__PRE 0x10 -#define SIO_PDR_I2S_CL_CFG_MODE__B 0 -#define SIO_PDR_I2S_CL_CFG_MODE__W 3 -#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 -#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 -#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 -#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 -#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 -#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 -#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2S_CL_CFG_UIO__B 8 -#define SIO_PDR_I2S_CL_CFG_UIO__W 1 -#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 -#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 -#define SIO_PDR_I2S_DA_CFG__W 9 -#define SIO_PDR_I2S_DA_CFG__M 0x1FF -#define SIO_PDR_I2S_DA_CFG__PRE 0x10 -#define SIO_PDR_I2S_DA_CFG_MODE__B 0 -#define SIO_PDR_I2S_DA_CFG_MODE__W 3 -#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 -#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 -#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 -#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 -#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 -#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 -#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2S_DA_CFG_UIO__B 8 -#define SIO_PDR_I2S_DA_CFG_UIO__W 1 -#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 -#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 - -#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 -#define SIO_PDR_GPIO_GPIO_FNC__W 2 -#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 -#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 -#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 -#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 -#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 -#define SIO_PDR_MSTRT_GPIO_FNC__W 2 -#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 -#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 -#define SIO_PDR_MERR_GPIO_FNC__W 2 -#define SIO_PDR_MERR_GPIO_FNC__M 0x3 -#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 -#define SIO_PDR_MCLK_GPIO_FNC__W 2 -#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 -#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 -#define SIO_PDR_MVAL_GPIO_FNC__W 2 -#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 -#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 -#define SIO_PDR_MD0_GPIO_FNC__W 2 -#define SIO_PDR_MD0_GPIO_FNC__M 0x3 -#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 -#define SIO_PDR_MD1_GPIO_FNC__W 2 -#define SIO_PDR_MD1_GPIO_FNC__M 0x3 -#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 -#define SIO_PDR_MD2_GPIO_FNC__W 2 -#define SIO_PDR_MD2_GPIO_FNC__M 0x3 -#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 -#define SIO_PDR_MD3_GPIO_FNC__W 2 -#define SIO_PDR_MD3_GPIO_FNC__M 0x3 -#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A -#define SIO_PDR_MD4_GPIO_FNC__W 2 -#define SIO_PDR_MD4_GPIO_FNC__M 0x3 -#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B -#define SIO_PDR_MD5_GPIO_FNC__W 2 -#define SIO_PDR_MD5_GPIO_FNC__M 0x3 -#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C -#define SIO_PDR_MD6_GPIO_FNC__W 2 -#define SIO_PDR_MD6_GPIO_FNC__M 0x3 -#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D -#define SIO_PDR_MD7_GPIO_FNC__W 2 -#define SIO_PDR_MD7_GPIO_FNC__M 0x3 -#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E -#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 -#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 -#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 -#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 -#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 -#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F -#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 -#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 -#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 -#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 -#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 -#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 - -#endif - - +#ifndef __DRXK_MAP__H__ +#define __DRXK_MAP__H__ 1 + +#define AUD_COMM_EXEC__A 0x1000000 +#define AUD_COMM_EXEC__W 2 +#define AUD_COMM_EXEC__M 0x3 +#define AUD_COMM_EXEC__PRE 0x0 +#define AUD_COMM_EXEC_STOP 0x0 + +#define FEC_COMM_EXEC__A 0x1C00000 +#define FEC_COMM_EXEC__W 2 +#define FEC_COMM_EXEC__M 0x3 +#define FEC_COMM_EXEC__PRE 0x0 +#define FEC_COMM_EXEC_STOP 0x0 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_HOLD 0x2 + +#define FEC_COMM_MB__A 0x1C00002 +#define FEC_COMM_MB__W 16 +#define FEC_COMM_MB__M 0xFFFF +#define FEC_COMM_MB__PRE 0x0 +#define FEC_COMM_INT_REQ__A 0x1C00003 +#define FEC_COMM_INT_REQ__W 16 +#define FEC_COMM_INT_REQ__M 0xFFFF +#define FEC_COMM_INT_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_OC_REQ__B 0 +#define FEC_COMM_INT_REQ_OC_REQ__W 1 +#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 +#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_RS_REQ__B 1 +#define FEC_COMM_INT_REQ_RS_REQ__W 1 +#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 +#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_DI_REQ__B 2 +#define FEC_COMM_INT_REQ_DI_REQ__W 1 +#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 +#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 + +#define FEC_COMM_INT_STA__A 0x1C00005 +#define FEC_COMM_INT_STA__W 16 +#define FEC_COMM_INT_STA__M 0xFFFF +#define FEC_COMM_INT_STA__PRE 0x0 +#define FEC_COMM_INT_MSK__A 0x1C00006 +#define FEC_COMM_INT_MSK__W 16 +#define FEC_COMM_INT_MSK__M 0xFFFF +#define FEC_COMM_INT_MSK__PRE 0x0 +#define FEC_COMM_INT_STM__A 0x1C00007 +#define FEC_COMM_INT_STM__W 16 +#define FEC_COMM_INT_STM__M 0xFFFF +#define FEC_COMM_INT_STM__PRE 0x0 + + + +#define FEC_TOP_COMM_EXEC__A 0x1C10000 +#define FEC_TOP_COMM_EXEC__W 2 +#define FEC_TOP_COMM_EXEC__M 0x3 +#define FEC_TOP_COMM_EXEC__PRE 0x0 +#define FEC_TOP_COMM_EXEC_STOP 0x0 +#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 +#define FEC_TOP_COMM_EXEC_HOLD 0x2 + +#define FEC_TOP_ANNEX__A 0x1C10010 +#define FEC_TOP_ANNEX__W 2 +#define FEC_TOP_ANNEX__M 0x3 +#define FEC_TOP_ANNEX__PRE 0x0 +#define FEC_TOP_ANNEX_A 0x0 +#define FEC_TOP_ANNEX_B 0x1 +#define FEC_TOP_ANNEX_C 0x2 +#define FEC_TOP_ANNEX_D 0x3 + + + +#define FEC_DI_COMM_EXEC__A 0x1C20000 +#define FEC_DI_COMM_EXEC__W 2 +#define FEC_DI_COMM_EXEC__M 0x3 +#define FEC_DI_COMM_EXEC__PRE 0x0 +#define FEC_DI_COMM_EXEC_STOP 0x0 +#define FEC_DI_COMM_EXEC_ACTIVE 0x1 +#define FEC_DI_COMM_EXEC_HOLD 0x2 + +#define FEC_DI_COMM_MB__A 0x1C20002 +#define FEC_DI_COMM_MB__W 2 +#define FEC_DI_COMM_MB__M 0x3 +#define FEC_DI_COMM_MB__PRE 0x0 +#define FEC_DI_COMM_MB_CTL__B 0 +#define FEC_DI_COMM_MB_CTL__W 1 +#define FEC_DI_COMM_MB_CTL__M 0x1 +#define FEC_DI_COMM_MB_CTL__PRE 0x0 +#define FEC_DI_COMM_MB_CTL_OFF 0x0 +#define FEC_DI_COMM_MB_CTL_ON 0x1 +#define FEC_DI_COMM_MB_OBS__B 1 +#define FEC_DI_COMM_MB_OBS__W 1 +#define FEC_DI_COMM_MB_OBS__M 0x2 +#define FEC_DI_COMM_MB_OBS__PRE 0x0 +#define FEC_DI_COMM_MB_OBS_OFF 0x0 +#define FEC_DI_COMM_MB_OBS_ON 0x2 + +#define FEC_DI_COMM_INT_REQ__A 0x1C20003 +#define FEC_DI_COMM_INT_REQ__W 1 +#define FEC_DI_COMM_INT_REQ__M 0x1 +#define FEC_DI_COMM_INT_REQ__PRE 0x0 +#define FEC_DI_COMM_INT_STA__A 0x1C20005 +#define FEC_DI_COMM_INT_STA__W 2 +#define FEC_DI_COMM_INT_STA__M 0x3 +#define FEC_DI_COMM_INT_STA__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_MSK__A 0x1C20006 +#define FEC_DI_COMM_INT_MSK__W 2 +#define FEC_DI_COMM_INT_MSK__M 0x3 +#define FEC_DI_COMM_INT_MSK__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STM__A 0x1C20007 +#define FEC_DI_COMM_INT_STM__W 2 +#define FEC_DI_COMM_INT_STM__M 0x3 +#define FEC_DI_COMM_INT_STM__PRE 0x0 +#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 + + +#define FEC_DI_STATUS__A 0x1C20010 +#define FEC_DI_STATUS__W 1 +#define FEC_DI_STATUS__M 0x1 +#define FEC_DI_STATUS__PRE 0x0 +#define FEC_DI_MODE__A 0x1C20011 +#define FEC_DI_MODE__W 3 +#define FEC_DI_MODE__M 0x7 +#define FEC_DI_MODE__PRE 0x0 + +#define FEC_DI_MODE_NO_SYNC__B 0 +#define FEC_DI_MODE_NO_SYNC__W 1 +#define FEC_DI_MODE_NO_SYNC__M 0x1 +#define FEC_DI_MODE_NO_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 +#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 +#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 +#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 + + +#define FEC_DI_CONTROL_WORD__A 0x1C20012 +#define FEC_DI_CONTROL_WORD__W 4 +#define FEC_DI_CONTROL_WORD__M 0xF +#define FEC_DI_CONTROL_WORD__PRE 0x0 + +#define FEC_DI_RESTART__A 0x1C20013 +#define FEC_DI_RESTART__W 1 +#define FEC_DI_RESTART__M 0x1 +#define FEC_DI_RESTART__PRE 0x0 + +#define FEC_DI_TIMEOUT_LO__A 0x1C20014 +#define FEC_DI_TIMEOUT_LO__W 16 +#define FEC_DI_TIMEOUT_LO__M 0xFFFF +#define FEC_DI_TIMEOUT_LO__PRE 0x0 + +#define FEC_DI_TIMEOUT_HI__A 0x1C20015 +#define FEC_DI_TIMEOUT_HI__W 8 +#define FEC_DI_TIMEOUT_HI__M 0xFF +#define FEC_DI_TIMEOUT_HI__PRE 0xA + +#define FEC_DI_INPUT_CTL__A 0x1C20016 +#define FEC_DI_INPUT_CTL__W 1 +#define FEC_DI_INPUT_CTL__M 0x1 +#define FEC_DI_INPUT_CTL__PRE 0x0 + + + +#define FEC_RS_COMM_EXEC__A 0x1C30000 +#define FEC_RS_COMM_EXEC__W 2 +#define FEC_RS_COMM_EXEC__M 0x3 +#define FEC_RS_COMM_EXEC__PRE 0x0 +#define FEC_RS_COMM_EXEC_STOP 0x0 +#define FEC_RS_COMM_EXEC_ACTIVE 0x1 +#define FEC_RS_COMM_EXEC_HOLD 0x2 + +#define FEC_RS_COMM_MB__A 0x1C30002 +#define FEC_RS_COMM_MB__W 2 +#define FEC_RS_COMM_MB__M 0x3 +#define FEC_RS_COMM_MB__PRE 0x0 +#define FEC_RS_COMM_MB_CTL__B 0 +#define FEC_RS_COMM_MB_CTL__W 1 +#define FEC_RS_COMM_MB_CTL__M 0x1 +#define FEC_RS_COMM_MB_CTL__PRE 0x0 +#define FEC_RS_COMM_MB_CTL_OFF 0x0 +#define FEC_RS_COMM_MB_CTL_ON 0x1 +#define FEC_RS_COMM_MB_OBS__B 1 +#define FEC_RS_COMM_MB_OBS__W 1 +#define FEC_RS_COMM_MB_OBS__M 0x2 +#define FEC_RS_COMM_MB_OBS__PRE 0x0 +#define FEC_RS_COMM_MB_OBS_OFF 0x0 +#define FEC_RS_COMM_MB_OBS_ON 0x2 + +#define FEC_RS_COMM_INT_REQ__A 0x1C30003 +#define FEC_RS_COMM_INT_REQ__W 1 +#define FEC_RS_COMM_INT_REQ__M 0x1 +#define FEC_RS_COMM_INT_REQ__PRE 0x0 +#define FEC_RS_COMM_INT_STA__A 0x1C30005 +#define FEC_RS_COMM_INT_STA__W 2 +#define FEC_RS_COMM_INT_STA__M 0x3 +#define FEC_RS_COMM_INT_STA__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_MSK__A 0x1C30006 +#define FEC_RS_COMM_INT_MSK__W 2 +#define FEC_RS_COMM_INT_MSK__M 0x3 +#define FEC_RS_COMM_INT_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_COMM_INT_STM__A 0x1C30007 +#define FEC_RS_COMM_INT_STM__W 2 +#define FEC_RS_COMM_INT_STM__M 0x3 +#define FEC_RS_COMM_INT_STM__PRE 0x0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_STATUS__A 0x1C30010 +#define FEC_RS_STATUS__W 1 +#define FEC_RS_STATUS__M 0x1 +#define FEC_RS_STATUS__PRE 0x0 +#define FEC_RS_MODE__A 0x1C30011 +#define FEC_RS_MODE__W 1 +#define FEC_RS_MODE__M 0x1 +#define FEC_RS_MODE__PRE 0x0 + +#define FEC_RS_MODE_BYPASS__B 0 +#define FEC_RS_MODE_BYPASS__W 1 +#define FEC_RS_MODE_BYPASS__M 0x1 +#define FEC_RS_MODE_BYPASS__PRE 0x0 + +#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 +#define FEC_RS_MEASUREMENT_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x993 + +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x993 + +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 +#define FEC_RS_MEASUREMENT_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 + +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 + +#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 +#define FEC_RS_NR_BIT_ERRORS__W 16 +#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF +#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 +#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 +#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_SYMBOL_ERRORS__A 0x1C30015 +#define FEC_RS_NR_SYMBOL_ERRORS__W 16 +#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF +#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_PACKET_ERRORS__A 0x1C30016 +#define FEC_RS_NR_PACKET_ERRORS__W 16 +#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF +#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 +#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 +#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_FAILURES__A 0x1C30017 +#define FEC_RS_NR_FAILURES__W 16 +#define FEC_RS_NR_FAILURES__M 0xFFFF +#define FEC_RS_NR_FAILURES__PRE 0x0 + +#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 +#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 +#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 + +#define FEC_RS_NR_FAILURES_EXP__B 12 +#define FEC_RS_NR_FAILURES_EXP__W 4 +#define FEC_RS_NR_FAILURES_EXP__M 0xF000 +#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 + + + +#define FEC_OC_COMM_EXEC__A 0x1C40000 +#define FEC_OC_COMM_EXEC__W 2 +#define FEC_OC_COMM_EXEC__M 0x3 +#define FEC_OC_COMM_EXEC__PRE 0x0 +#define FEC_OC_COMM_EXEC_STOP 0x0 +#define FEC_OC_COMM_EXEC_ACTIVE 0x1 +#define FEC_OC_COMM_EXEC_HOLD 0x2 + +#define FEC_OC_COMM_MB__A 0x1C40002 +#define FEC_OC_COMM_MB__W 2 +#define FEC_OC_COMM_MB__M 0x3 +#define FEC_OC_COMM_MB__PRE 0x0 +#define FEC_OC_COMM_MB_CTL__B 0 +#define FEC_OC_COMM_MB_CTL__W 1 +#define FEC_OC_COMM_MB_CTL__M 0x1 +#define FEC_OC_COMM_MB_CTL__PRE 0x0 +#define FEC_OC_COMM_MB_CTL_OFF 0x0 +#define FEC_OC_COMM_MB_CTL_ON 0x1 +#define FEC_OC_COMM_MB_OBS__B 1 +#define FEC_OC_COMM_MB_OBS__W 1 +#define FEC_OC_COMM_MB_OBS__M 0x2 +#define FEC_OC_COMM_MB_OBS__PRE 0x0 +#define FEC_OC_COMM_MB_OBS_OFF 0x0 +#define FEC_OC_COMM_MB_OBS_ON 0x2 + +#define FEC_OC_COMM_INT_REQ__A 0x1C40003 +#define FEC_OC_COMM_INT_REQ__W 1 +#define FEC_OC_COMM_INT_REQ__M 0x1 +#define FEC_OC_COMM_INT_REQ__PRE 0x0 +#define FEC_OC_COMM_INT_STA__A 0x1C40005 +#define FEC_OC_COMM_INT_STA__W 8 +#define FEC_OC_COMM_INT_STA__M 0xFF +#define FEC_OC_COMM_INT_STA__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_MSK__A 0x1C40006 +#define FEC_OC_COMM_INT_MSK__W 8 +#define FEC_OC_COMM_INT_MSK__M 0xFF +#define FEC_OC_COMM_INT_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_COMM_INT_STM__A 0x1C40007 +#define FEC_OC_COMM_INT_STM__W 8 +#define FEC_OC_COMM_INT_STM__M 0xFF +#define FEC_OC_COMM_INT_STM__PRE 0x0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_STATUS__A 0x1C40010 +#define FEC_OC_STATUS__W 5 +#define FEC_OC_STATUS__M 0x1F +#define FEC_OC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_DPR_STATUS__B 0 +#define FEC_OC_STATUS_DPR_STATUS__W 1 +#define FEC_OC_STATUS_DPR_STATUS__M 0x1 +#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_SNC_STATUS__B 1 +#define FEC_OC_STATUS_SNC_STATUS__W 2 +#define FEC_OC_STATUS_SNC_STATUS__M 0x6 +#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 +#define FEC_OC_STATUS_SNC_STATUS_HUNTING 0x0 +#define FEC_OC_STATUS_SNC_STATUS_TRACKING 0x2 +#define FEC_OC_STATUS_SNC_STATUS_LOCKED 0x4 + +#define FEC_OC_STATUS_FIFO_FULL__B 3 +#define FEC_OC_STATUS_FIFO_FULL__W 1 +#define FEC_OC_STATUS_FIFO_FULL__M 0x8 +#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_EMPTY__B 4 +#define FEC_OC_STATUS_FIFO_EMPTY__W 1 +#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 +#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 + +#define FEC_OC_MODE__A 0x1C40011 +#define FEC_OC_MODE__W 4 +#define FEC_OC_MODE__M 0xF +#define FEC_OC_MODE__PRE 0x0 + +#define FEC_OC_MODE_PARITY__B 0 +#define FEC_OC_MODE_PARITY__W 1 +#define FEC_OC_MODE_PARITY__M 0x1 +#define FEC_OC_MODE_PARITY__PRE 0x0 + +#define FEC_OC_MODE_TRANSPARENT__B 1 +#define FEC_OC_MODE_TRANSPARENT__W 1 +#define FEC_OC_MODE_TRANSPARENT__M 0x2 +#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 + +#define FEC_OC_MODE_CLEAR__B 2 +#define FEC_OC_MODE_CLEAR__W 1 +#define FEC_OC_MODE_CLEAR__M 0x4 +#define FEC_OC_MODE_CLEAR__PRE 0x0 + +#define FEC_OC_MODE_RETAIN_FRAMING__B 3 +#define FEC_OC_MODE_RETAIN_FRAMING__W 1 +#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 +#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 + +#define FEC_OC_DPR_MODE__A 0x1C40012 +#define FEC_OC_DPR_MODE__W 2 +#define FEC_OC_DPR_MODE__M 0x3 +#define FEC_OC_DPR_MODE__PRE 0x0 + +#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 +#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 + +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 + + +#define FEC_OC_DPR_UNLOCK__A 0x1C40013 +#define FEC_OC_DPR_UNLOCK__W 1 +#define FEC_OC_DPR_UNLOCK__M 0x1 +#define FEC_OC_DPR_UNLOCK__PRE 0x0 +#define FEC_OC_DTO_MODE__A 0x1C40014 +#define FEC_OC_DTO_MODE__W 3 +#define FEC_OC_DTO_MODE__M 0x7 +#define FEC_OC_DTO_MODE__PRE 0x0 + +#define FEC_OC_DTO_MODE_DYNAMIC__B 0 +#define FEC_OC_DTO_MODE_DYNAMIC__W 1 +#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 +#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 + +#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 + +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 + + +#define FEC_OC_DTO_PERIOD__A 0x1C40015 +#define FEC_OC_DTO_PERIOD__W 8 +#define FEC_OC_DTO_PERIOD__M 0xFF +#define FEC_OC_DTO_PERIOD__PRE 0x0 +#define FEC_OC_DTO_RATE_LO__A 0x1C40016 +#define FEC_OC_DTO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 +#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_HI__A 0x1C40017 +#define FEC_OC_DTO_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 +#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 +#define FEC_OC_DTO_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN__PRE 0xBC + +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC + +#define FEC_OC_FCT_MODE__A 0x1C4001A +#define FEC_OC_FCT_MODE__W 2 +#define FEC_OC_FCT_MODE__M 0x3 +#define FEC_OC_FCT_MODE__PRE 0x0 + +#define FEC_OC_FCT_MODE_RAT_ENA__B 0 +#define FEC_OC_FCT_MODE_RAT_ENA__W 1 +#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 +#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 + +#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 +#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 + +#define FEC_OC_FCT_USAGE__A 0x1C4001B +#define FEC_OC_FCT_USAGE__W 3 +#define FEC_OC_FCT_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE__PRE 0x7 + +#define FEC_OC_FCT_USAGE_USAGE__B 0 +#define FEC_OC_FCT_USAGE_USAGE__W 3 +#define FEC_OC_FCT_USAGE_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE_USAGE__PRE 0x7 + +#define FEC_OC_FCT_OCCUPATION__A 0x1C4001C +#define FEC_OC_FCT_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION__PRE 0x0 + +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 + +#define FEC_OC_TMD_MODE__A 0x1C4001E +#define FEC_OC_TMD_MODE__W 3 +#define FEC_OC_TMD_MODE__M 0x7 +#define FEC_OC_TMD_MODE__PRE 0x4 + +#define FEC_OC_TMD_MODE_MODE__B 0 +#define FEC_OC_TMD_MODE_MODE__W 3 +#define FEC_OC_TMD_MODE_MODE__M 0x7 +#define FEC_OC_TMD_MODE_MODE__PRE 0x4 + +#define FEC_OC_TMD_COUNT__A 0x1C4001F +#define FEC_OC_TMD_COUNT__W 10 +#define FEC_OC_TMD_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_COUNT_COUNT__B 0 +#define FEC_OC_TMD_COUNT_COUNT__W 10 +#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 +#define FEC_OC_TMD_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN__PRE 0x500 + +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x500 + +#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 +#define FEC_OC_TMD_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN__PRE 0x300 + +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x300 + +#define FEC_OC_TMD_CTL_UPD_RATE__A 0x1C40022 +#define FEC_OC_TMD_CTL_UPD_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 + +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 + +#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 +#define FEC_OC_TMD_INT_UPD_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 + +#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 + +#define FEC_OC_AVR_PARM_A__A 0x1C40026 +#define FEC_OC_AVR_PARM_A__W 4 +#define FEC_OC_AVR_PARM_A__M 0xF +#define FEC_OC_AVR_PARM_A__PRE 0x6 + +#define FEC_OC_AVR_PARM_A_PARM__B 0 +#define FEC_OC_AVR_PARM_A_PARM__W 4 +#define FEC_OC_AVR_PARM_A_PARM__M 0xF +#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 + +#define FEC_OC_AVR_PARM_B__A 0x1C40027 +#define FEC_OC_AVR_PARM_B__W 4 +#define FEC_OC_AVR_PARM_B__M 0xF +#define FEC_OC_AVR_PARM_B__PRE 0x4 + +#define FEC_OC_AVR_PARM_B_PARM__B 0 +#define FEC_OC_AVR_PARM_B_PARM__W 4 +#define FEC_OC_AVR_PARM_B_PARM__M 0xF +#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 + +#define FEC_OC_AVR_AVG_LO__A 0x1C40028 +#define FEC_OC_AVR_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 +#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI__A 0x1C40029 +#define FEC_OC_AVR_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 +#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 + +#define FEC_OC_RCN_MODE__A 0x1C4002C +#define FEC_OC_RCN_MODE__W 5 +#define FEC_OC_RCN_MODE__M 0x1F +#define FEC_OC_RCN_MODE__PRE 0x1F + +#define FEC_OC_RCN_MODE_MODE__B 0 +#define FEC_OC_RCN_MODE_MODE__W 5 +#define FEC_OC_RCN_MODE_MODE__M 0x1F +#define FEC_OC_RCN_MODE_MODE__PRE 0x1F + +#define FEC_OC_RCN_OCC_SETTLE__A 0x1C4002D +#define FEC_OC_RCN_OCC_SETTLE__W 11 +#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE__PRE 0x400 + +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x400 + +#define FEC_OC_RCN_GAIN__A 0x1C4002E +#define FEC_OC_RCN_GAIN__W 4 +#define FEC_OC_RCN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN__PRE 0xC + +#define FEC_OC_RCN_GAIN_GAIN__B 0 +#define FEC_OC_RCN_GAIN_GAIN__W 4 +#define FEC_OC_RCN_GAIN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC + +#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 +#define FEC_OC_RCN_CTL_RATE_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_HI__A 0x1C40031 +#define FEC_OC_RCN_CTL_RATE_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 +#define FEC_OC_RCN_CTL_STEP_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 +#define FEC_OC_RCN_CTL_STEP_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 + +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 + +#define FEC_OC_RCN_DTO_OFS_LO__A 0x1C40034 +#define FEC_OC_RCN_DTO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI__A 0x1C40035 +#define FEC_OC_RCN_DTO_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO__A 0x1C40036 +#define FEC_OC_RCN_DTO_RATE_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI__A 0x1C40037 +#define FEC_OC_RCN_DTO_RATE_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO__A 0x1C40038 +#define FEC_OC_RCN_RATE_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_HI__A 0x1C40039 +#define FEC_OC_RCN_RATE_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_DYN_RATE_LO__A 0x1C4003A +#define FEC_OC_RCN_DYN_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI__A 0x1C4003B +#define FEC_OC_RCN_DYN_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 + +#define FEC_OC_SNC_MODE__A 0x1C40040 +#define FEC_OC_SNC_MODE__W 5 +#define FEC_OC_SNC_MODE__M 0x1F +#define FEC_OC_SNC_MODE__PRE 0x0 + +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 + +#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 +#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 +#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 +#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 + +#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 +#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 +#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 +#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 + +#define FEC_OC_SNC_MODE_SHUTDOWN__B 4 +#define FEC_OC_SNC_MODE_SHUTDOWN__W 1 +#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 +#define FEC_OC_SNC_MODE_SHUTDOWN__PRE 0x0 + +#define FEC_OC_SNC_LWM__A 0x1C40041 +#define FEC_OC_SNC_LWM__W 4 +#define FEC_OC_SNC_LWM__M 0xF +#define FEC_OC_SNC_LWM__PRE 0x3 + +#define FEC_OC_SNC_LWM_MARK__B 0 +#define FEC_OC_SNC_LWM_MARK__W 4 +#define FEC_OC_SNC_LWM_MARK__M 0xF +#define FEC_OC_SNC_LWM_MARK__PRE 0x3 + +#define FEC_OC_SNC_HWM__A 0x1C40042 +#define FEC_OC_SNC_HWM__W 4 +#define FEC_OC_SNC_HWM__M 0xF +#define FEC_OC_SNC_HWM__PRE 0x5 + +#define FEC_OC_SNC_HWM_MARK__B 0 +#define FEC_OC_SNC_HWM_MARK__W 4 +#define FEC_OC_SNC_HWM_MARK__M 0xF +#define FEC_OC_SNC_HWM_MARK__PRE 0x5 + +#define FEC_OC_SNC_UNLOCK__A 0x1C40043 +#define FEC_OC_SNC_UNLOCK__W 1 +#define FEC_OC_SNC_UNLOCK__M 0x1 +#define FEC_OC_SNC_UNLOCK__PRE 0x0 + +#define FEC_OC_SNC_UNLOCK_RESTART__B 0 +#define FEC_OC_SNC_UNLOCK_RESTART__W 1 +#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 +#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT__A 0x1C40044 +#define FEC_OC_SNC_LOCK_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT__A 0x1C40045 +#define FEC_OC_SNC_FAIL_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 +#define FEC_OC_SNC_FAIL_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 + +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_OC_EMS_MODE__A 0x1C40047 +#define FEC_OC_EMS_MODE__W 2 +#define FEC_OC_EMS_MODE__M 0x3 +#define FEC_OC_EMS_MODE__PRE 0x0 + +#define FEC_OC_EMS_MODE_MODE__B 0 +#define FEC_OC_EMS_MODE_MODE__W 2 +#define FEC_OC_EMS_MODE_MODE__M 0x3 +#define FEC_OC_EMS_MODE_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE__A 0x1C40048 +#define FEC_OC_IPR_MODE__W 12 +#define FEC_OC_IPR_MODE__M 0xFFF +#define FEC_OC_IPR_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE_SERIAL__B 0 +#define FEC_OC_IPR_MODE_SERIAL__W 1 +#define FEC_OC_IPR_MODE_SERIAL__M 0x1 +#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 + +#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT__A 0x1C40049 +#define FEC_OC_IPR_INVERT__W 12 +#define FEC_OC_IPR_INVERT__M 0xFFF +#define FEC_OC_IPR_INVERT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD0__B 0 +#define FEC_OC_IPR_INVERT_MD0__W 1 +#define FEC_OC_IPR_INVERT_MD0__M 0x1 +#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD1__B 1 +#define FEC_OC_IPR_INVERT_MD1__W 1 +#define FEC_OC_IPR_INVERT_MD1__M 0x2 +#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD2__B 2 +#define FEC_OC_IPR_INVERT_MD2__W 1 +#define FEC_OC_IPR_INVERT_MD2__M 0x4 +#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD3__B 3 +#define FEC_OC_IPR_INVERT_MD3__W 1 +#define FEC_OC_IPR_INVERT_MD3__M 0x8 +#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD4__B 4 +#define FEC_OC_IPR_INVERT_MD4__W 1 +#define FEC_OC_IPR_INVERT_MD4__M 0x10 +#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD5__B 5 +#define FEC_OC_IPR_INVERT_MD5__W 1 +#define FEC_OC_IPR_INVERT_MD5__M 0x20 +#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD6__B 6 +#define FEC_OC_IPR_INVERT_MD6__W 1 +#define FEC_OC_IPR_INVERT_MD6__M 0x40 +#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD7__B 7 +#define FEC_OC_IPR_INVERT_MD7__W 1 +#define FEC_OC_IPR_INVERT_MD7__M 0x80 +#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MERR__B 8 +#define FEC_OC_IPR_INVERT_MERR__W 1 +#define FEC_OC_IPR_INVERT_MERR__M 0x100 +#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MSTRT__B 9 +#define FEC_OC_IPR_INVERT_MSTRT__W 1 +#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 +#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MVAL__B 10 +#define FEC_OC_IPR_INVERT_MVAL__W 1 +#define FEC_OC_IPR_INVERT_MVAL__M 0x400 +#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MCLK__B 11 +#define FEC_OC_IPR_INVERT_MCLK__W 1 +#define FEC_OC_IPR_INVERT_MCLK__M 0x800 +#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 + +#define FEC_OC_OCR_MODE__A 0x1C40050 +#define FEC_OC_OCR_MODE__W 4 +#define FEC_OC_OCR_MODE__M 0xF +#define FEC_OC_OCR_MODE__PRE 0x0 + +#define FEC_OC_OCR_MODE_MB_SELECT__B 0 +#define FEC_OC_OCR_MODE_MB_SELECT__W 1 +#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 +#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 +#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 +#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 +#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 + +#define FEC_OC_OCR_RATE__A 0x1C40051 +#define FEC_OC_OCR_RATE__W 4 +#define FEC_OC_OCR_RATE__M 0xF +#define FEC_OC_OCR_RATE__PRE 0x0 + +#define FEC_OC_OCR_RATE_RATE__B 0 +#define FEC_OC_OCR_RATE_RATE__W 4 +#define FEC_OC_OCR_RATE_RATE__M 0xF +#define FEC_OC_OCR_RATE_RATE__PRE 0x0 + +#define FEC_OC_OCR_INVERT__A 0x1C40052 +#define FEC_OC_OCR_INVERT__W 12 +#define FEC_OC_OCR_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT__PRE 0x800 + +#define FEC_OC_OCR_INVERT_INVERT__B 0 +#define FEC_OC_OCR_INVERT_INVERT__W 12 +#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 + +#define FEC_OC_OCR_GRAB_COUNT__A 0x1C40053 +#define FEC_OC_OCR_GRAB_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC__A 0x1C40054 +#define FEC_OC_OCR_GRAB_SYNC__W 8 +#define FEC_OC_OCR_GRAB_SYNC__M 0xFF +#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0__A 0x1C40055 +#define FEC_OC_OCR_GRAB_RD0__W 10 +#define FEC_OC_OCR_GRAB_RD0__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1__A 0x1C40056 +#define FEC_OC_OCR_GRAB_RD1__W 10 +#define FEC_OC_OCR_GRAB_RD1__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2__A 0x1C40057 +#define FEC_OC_OCR_GRAB_RD2__W 10 +#define FEC_OC_OCR_GRAB_RD2__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3__A 0x1C40058 +#define FEC_OC_OCR_GRAB_RD3__W 10 +#define FEC_OC_OCR_GRAB_RD3__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4__A 0x1C40059 +#define FEC_OC_OCR_GRAB_RD4__W 10 +#define FEC_OC_OCR_GRAB_RD4__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5__A 0x1C4005A +#define FEC_OC_OCR_GRAB_RD5__W 10 +#define FEC_OC_OCR_GRAB_RD5__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 + + + +#define FEC_DI_RAM__A 0x1C50000 + + + +#define FEC_RS_RAM__A 0x1C60000 + + + +#define FEC_OC_RAM__A 0x1C70000 + + + + + +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__W 2 +#define IQM_COMM_EXEC__M 0x3 +#define IQM_COMM_EXEC__PRE 0x0 +#define IQM_COMM_EXEC_B__B 0 +#define IQM_COMM_EXEC_B__W 2 +#define IQM_COMM_EXEC_B__M 0x3 +#define IQM_COMM_EXEC_B__PRE 0x0 +#define IQM_COMM_EXEC_B_STOP 0x0 +#define IQM_COMM_EXEC_B_ACTIVE 0x1 +#define IQM_COMM_EXEC_B_HOLD 0x2 + +#define IQM_COMM_MB__A 0x1800002 +#define IQM_COMM_MB__W 16 +#define IQM_COMM_MB__M 0xFFFF +#define IQM_COMM_MB__PRE 0x0 +#define IQM_COMM_MB_B__B 0 +#define IQM_COMM_MB_B__W 16 +#define IQM_COMM_MB_B__M 0xFFFF +#define IQM_COMM_MB_B__PRE 0x0 + +#define IQM_COMM_INT_REQ__A 0x1800003 +#define IQM_COMM_INT_REQ__W 3 +#define IQM_COMM_INT_REQ__M 0x7 +#define IQM_COMM_INT_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_AF_REQ__B 0 +#define IQM_COMM_INT_REQ_AF_REQ__W 1 +#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 +#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_CF_REQ__B 1 +#define IQM_COMM_INT_REQ_CF_REQ__W 1 +#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 +#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_CW_REQ__B 2 +#define IQM_COMM_INT_REQ_CW_REQ__W 1 +#define IQM_COMM_INT_REQ_CW_REQ__M 0x4 +#define IQM_COMM_INT_REQ_CW_REQ__PRE 0x0 + +#define IQM_COMM_INT_STA__A 0x1800005 +#define IQM_COMM_INT_STA__W 16 +#define IQM_COMM_INT_STA__M 0xFFFF +#define IQM_COMM_INT_STA__PRE 0x0 +#define IQM_COMM_INT_STA_B__B 0 +#define IQM_COMM_INT_STA_B__W 16 +#define IQM_COMM_INT_STA_B__M 0xFFFF +#define IQM_COMM_INT_STA_B__PRE 0x0 + +#define IQM_COMM_INT_MSK__A 0x1800006 +#define IQM_COMM_INT_MSK__W 16 +#define IQM_COMM_INT_MSK__M 0xFFFF +#define IQM_COMM_INT_MSK__PRE 0x0 +#define IQM_COMM_INT_MSK_B__B 0 +#define IQM_COMM_INT_MSK_B__W 16 +#define IQM_COMM_INT_MSK_B__M 0xFFFF +#define IQM_COMM_INT_MSK_B__PRE 0x0 + +#define IQM_COMM_INT_STM__A 0x1800007 +#define IQM_COMM_INT_STM__W 16 +#define IQM_COMM_INT_STM__M 0xFFFF +#define IQM_COMM_INT_STM__PRE 0x0 +#define IQM_COMM_INT_STM_B__B 0 +#define IQM_COMM_INT_STM_B__W 16 +#define IQM_COMM_INT_STM_B__M 0xFFFF +#define IQM_COMM_INT_STM_B__PRE 0x0 + + + +#define IQM_FS_COMM_EXEC__A 0x1820000 +#define IQM_FS_COMM_EXEC__W 2 +#define IQM_FS_COMM_EXEC__M 0x3 +#define IQM_FS_COMM_EXEC__PRE 0x0 +#define IQM_FS_COMM_EXEC_STOP 0x0 +#define IQM_FS_COMM_EXEC_ACTIVE 0x1 +#define IQM_FS_COMM_EXEC_HOLD 0x2 + +#define IQM_FS_COMM_MB__A 0x1820002 +#define IQM_FS_COMM_MB__W 4 +#define IQM_FS_COMM_MB__M 0xF +#define IQM_FS_COMM_MB__PRE 0x0 +#define IQM_FS_COMM_MB_CTL__B 0 +#define IQM_FS_COMM_MB_CTL__W 1 +#define IQM_FS_COMM_MB_CTL__M 0x1 +#define IQM_FS_COMM_MB_CTL__PRE 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FS_COMM_MB_OBS__B 1 +#define IQM_FS_COMM_MB_OBS__W 1 +#define IQM_FS_COMM_MB_OBS__M 0x2 +#define IQM_FS_COMM_MB_OBS__PRE 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 +#define IQM_FS_COMM_MB_CTL_MUX__B 2 +#define IQM_FS_COMM_MB_CTL_MUX__W 1 +#define IQM_FS_COMM_MB_CTL_MUX__M 0x4 +#define IQM_FS_COMM_MB_CTL_MUX__PRE 0x0 +#define IQM_FS_COMM_MB_OBS_MUX__B 3 +#define IQM_FS_COMM_MB_OBS_MUX__W 1 +#define IQM_FS_COMM_MB_OBS_MUX__M 0x8 +#define IQM_FS_COMM_MB_OBS_MUX__PRE 0x0 + +#define IQM_FS_RATE_OFS_LO__A 0x1820010 +#define IQM_FS_RATE_OFS_LO__W 16 +#define IQM_FS_RATE_OFS_LO__M 0xFFFF +#define IQM_FS_RATE_OFS_LO__PRE 0x0 +#define IQM_FS_RATE_OFS_LO_B__B 0 +#define IQM_FS_RATE_OFS_LO_B__W 16 +#define IQM_FS_RATE_OFS_LO_B__M 0xFFFF +#define IQM_FS_RATE_OFS_LO_B__PRE 0x0 + +#define IQM_FS_RATE_OFS_HI__A 0x1820011 +#define IQM_FS_RATE_OFS_HI__W 12 +#define IQM_FS_RATE_OFS_HI__M 0xFFF +#define IQM_FS_RATE_OFS_HI__PRE 0x0 +#define IQM_FS_RATE_OFS_HI_B__B 0 +#define IQM_FS_RATE_OFS_HI_B__W 12 +#define IQM_FS_RATE_OFS_HI_B__M 0xFFF +#define IQM_FS_RATE_OFS_HI_B__PRE 0x0 + +#define IQM_FS_RATE_LO__A 0x1820012 +#define IQM_FS_RATE_LO__W 16 +#define IQM_FS_RATE_LO__M 0xFFFF +#define IQM_FS_RATE_LO__PRE 0x0 +#define IQM_FS_RATE_LO_B__B 0 +#define IQM_FS_RATE_LO_B__W 16 +#define IQM_FS_RATE_LO_B__M 0xFFFF +#define IQM_FS_RATE_LO_B__PRE 0x0 + +#define IQM_FS_RATE_HI__A 0x1820013 +#define IQM_FS_RATE_HI__W 12 +#define IQM_FS_RATE_HI__M 0xFFF +#define IQM_FS_RATE_HI__PRE 0x0 +#define IQM_FS_RATE_HI_B__B 0 +#define IQM_FS_RATE_HI_B__W 12 +#define IQM_FS_RATE_HI_B__M 0xFFF +#define IQM_FS_RATE_HI_B__PRE 0x0 + +#define IQM_FS_ADJ_SEL__A 0x1820014 +#define IQM_FS_ADJ_SEL__W 2 +#define IQM_FS_ADJ_SEL__M 0x3 +#define IQM_FS_ADJ_SEL__PRE 0x0 + +#define IQM_FS_ADJ_SEL_B__B 0 +#define IQM_FS_ADJ_SEL_B__W 2 +#define IQM_FS_ADJ_SEL_B__M 0x3 +#define IQM_FS_ADJ_SEL_B__PRE 0x0 +#define IQM_FS_ADJ_SEL_B_OFF 0x0 +#define IQM_FS_ADJ_SEL_B_QAM 0x1 +#define IQM_FS_ADJ_SEL_B_VSB 0x2 + + + +#define IQM_FD_COMM_EXEC__A 0x1830000 +#define IQM_FD_COMM_EXEC__W 2 +#define IQM_FD_COMM_EXEC__M 0x3 +#define IQM_FD_COMM_EXEC__PRE 0x0 +#define IQM_FD_COMM_EXEC_STOP 0x0 +#define IQM_FD_COMM_EXEC_ACTIVE 0x1 +#define IQM_FD_COMM_EXEC_HOLD 0x2 + +#define IQM_FD_COMM_MB__A 0x1830002 +#define IQM_FD_COMM_MB__W 2 +#define IQM_FD_COMM_MB__M 0x3 +#define IQM_FD_COMM_MB__PRE 0x0 +#define IQM_FD_COMM_MB_CTL__B 0 +#define IQM_FD_COMM_MB_CTL__W 1 +#define IQM_FD_COMM_MB_CTL__M 0x1 +#define IQM_FD_COMM_MB_CTL__PRE 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FD_COMM_MB_OBS__B 1 +#define IQM_FD_COMM_MB_OBS__W 1 +#define IQM_FD_COMM_MB_OBS__M 0x2 +#define IQM_FD_COMM_MB_OBS__PRE 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_FD_RATESEL__A 0x1830010 +#define IQM_FD_RATESEL__W 2 +#define IQM_FD_RATESEL__M 0x3 +#define IQM_FD_RATESEL__PRE 0x0 +#define IQM_FD_RATESEL_B__B 0 +#define IQM_FD_RATESEL_B__W 2 +#define IQM_FD_RATESEL_B__M 0x3 +#define IQM_FD_RATESEL_B__PRE 0x0 +#define IQM_FD_RATESEL_B_DS0 0x0 +#define IQM_FD_RATESEL_B_DS1 0x1 +#define IQM_FD_RATESEL_B_DS2 0x2 +#define IQM_FD_RATESEL_B_DS3 0x3 + + + +#define IQM_RC_COMM_EXEC__A 0x1840000 +#define IQM_RC_COMM_EXEC__W 2 +#define IQM_RC_COMM_EXEC__M 0x3 +#define IQM_RC_COMM_EXEC__PRE 0x0 +#define IQM_RC_COMM_EXEC_STOP 0x0 +#define IQM_RC_COMM_EXEC_ACTIVE 0x1 +#define IQM_RC_COMM_EXEC_HOLD 0x2 + +#define IQM_RC_COMM_MB__A 0x1840002 +#define IQM_RC_COMM_MB__W 2 +#define IQM_RC_COMM_MB__M 0x3 +#define IQM_RC_COMM_MB__PRE 0x0 +#define IQM_RC_COMM_MB_CTL__B 0 +#define IQM_RC_COMM_MB_CTL__W 1 +#define IQM_RC_COMM_MB_CTL__M 0x1 +#define IQM_RC_COMM_MB_CTL__PRE 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RC_COMM_MB_OBS__B 1 +#define IQM_RC_COMM_MB_OBS__W 1 +#define IQM_RC_COMM_MB_OBS__M 0x2 +#define IQM_RC_COMM_MB_OBS__PRE 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__W 16 +#define IQM_RC_RATE_OFS_LO__M 0xFFFF +#define IQM_RC_RATE_OFS_LO__PRE 0x0 +#define IQM_RC_RATE_OFS_LO_B__B 0 +#define IQM_RC_RATE_OFS_LO_B__W 16 +#define IQM_RC_RATE_OFS_LO_B__M 0xFFFF +#define IQM_RC_RATE_OFS_LO_B__PRE 0x0 + +#define IQM_RC_RATE_OFS_HI__A 0x1840011 +#define IQM_RC_RATE_OFS_HI__W 8 +#define IQM_RC_RATE_OFS_HI__M 0xFF +#define IQM_RC_RATE_OFS_HI__PRE 0x0 +#define IQM_RC_RATE_OFS_HI_B__B 0 +#define IQM_RC_RATE_OFS_HI_B__W 8 +#define IQM_RC_RATE_OFS_HI_B__M 0xFF +#define IQM_RC_RATE_OFS_HI_B__PRE 0x0 + +#define IQM_RC_RATE_LO__A 0x1840012 +#define IQM_RC_RATE_LO__W 16 +#define IQM_RC_RATE_LO__M 0xFFFF +#define IQM_RC_RATE_LO__PRE 0x0 +#define IQM_RC_RATE_LO_B__B 0 +#define IQM_RC_RATE_LO_B__W 16 +#define IQM_RC_RATE_LO_B__M 0xFFFF +#define IQM_RC_RATE_LO_B__PRE 0x0 + +#define IQM_RC_RATE_HI__A 0x1840013 +#define IQM_RC_RATE_HI__W 8 +#define IQM_RC_RATE_HI__M 0xFF +#define IQM_RC_RATE_HI__PRE 0x0 +#define IQM_RC_RATE_HI_B__B 0 +#define IQM_RC_RATE_HI_B__W 8 +#define IQM_RC_RATE_HI_B__M 0xFF +#define IQM_RC_RATE_HI_B__PRE 0x0 + +#define IQM_RC_ADJ_SEL__A 0x1840014 +#define IQM_RC_ADJ_SEL__W 2 +#define IQM_RC_ADJ_SEL__M 0x3 +#define IQM_RC_ADJ_SEL__PRE 0x0 + +#define IQM_RC_ADJ_SEL_B__B 0 +#define IQM_RC_ADJ_SEL_B__W 2 +#define IQM_RC_ADJ_SEL_B__M 0x3 +#define IQM_RC_ADJ_SEL_B__PRE 0x0 +#define IQM_RC_ADJ_SEL_B_OFF 0x0 +#define IQM_RC_ADJ_SEL_B_QAM 0x1 +#define IQM_RC_ADJ_SEL_B_VSB 0x2 + +#define IQM_RC_CROUT_ENA__A 0x1840015 +#define IQM_RC_CROUT_ENA__W 1 +#define IQM_RC_CROUT_ENA__M 0x1 +#define IQM_RC_CROUT_ENA__PRE 0x0 + +#define IQM_RC_CROUT_ENA_ENA__B 0 +#define IQM_RC_CROUT_ENA_ENA__W 1 +#define IQM_RC_CROUT_ENA_ENA__M 0x1 +#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 + +#define IQM_RC_STRETCH__A 0x1840016 +#define IQM_RC_STRETCH__W 5 +#define IQM_RC_STRETCH__M 0x1F +#define IQM_RC_STRETCH__PRE 0x0 + +#define IQM_RC_STRETCH_B__B 0 +#define IQM_RC_STRETCH_B__W 5 +#define IQM_RC_STRETCH_B__M 0x1F +#define IQM_RC_STRETCH_B__PRE 0x0 + + + +#define IQM_RT_COMM_EXEC__A 0x1850000 +#define IQM_RT_COMM_EXEC__W 2 +#define IQM_RT_COMM_EXEC__M 0x3 +#define IQM_RT_COMM_EXEC__PRE 0x0 +#define IQM_RT_COMM_EXEC_STOP 0x0 +#define IQM_RT_COMM_EXEC_ACTIVE 0x1 +#define IQM_RT_COMM_EXEC_HOLD 0x2 + +#define IQM_RT_COMM_MB__A 0x1850002 +#define IQM_RT_COMM_MB__W 2 +#define IQM_RT_COMM_MB__M 0x3 +#define IQM_RT_COMM_MB__PRE 0x0 +#define IQM_RT_COMM_MB_CTL__B 0 +#define IQM_RT_COMM_MB_CTL__W 1 +#define IQM_RT_COMM_MB_CTL__M 0x1 +#define IQM_RT_COMM_MB_CTL__PRE 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RT_COMM_MB_OBS__B 1 +#define IQM_RT_COMM_MB_OBS__W 1 +#define IQM_RT_COMM_MB_OBS__M 0x2 +#define IQM_RT_COMM_MB_OBS__PRE 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RT_ACTIVE__A 0x1850010 +#define IQM_RT_ACTIVE__W 2 +#define IQM_RT_ACTIVE__M 0x3 +#define IQM_RT_ACTIVE__PRE 0x0 + +#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 +#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 +#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 +#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 + +#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 +#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 + + +#define IQM_RT_LO_INCR__A 0x1850011 +#define IQM_RT_LO_INCR__W 12 +#define IQM_RT_LO_INCR__M 0xFFF +#define IQM_RT_LO_INCR__PRE 0x588 +#define IQM_RT_LO_INCR_FM 0x0 +#define IQM_RT_LO_INCR_MN 0x588 + +#define IQM_RT_ROT_BP__A 0x1850012 +#define IQM_RT_ROT_BP__W 3 +#define IQM_RT_ROT_BP__M 0x7 +#define IQM_RT_ROT_BP__PRE 0x0 + +#define IQM_RT_ROT_BP_ROT_OFF__B 0 +#define IQM_RT_ROT_BP_ROT_OFF__W 1 +#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 +#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 + +#define IQM_RT_ROT_BP_ROT_BPF__B 1 +#define IQM_RT_ROT_BP_ROT_BPF__W 1 +#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 +#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 + +#define IQM_RT_ROT_BP_MIX_BP__B 2 +#define IQM_RT_ROT_BP_MIX_BP__W 1 +#define IQM_RT_ROT_BP_MIX_BP__M 0x4 +#define IQM_RT_ROT_BP_MIX_BP__PRE 0x0 + + +#define IQM_RT_LP_BP__A 0x1850013 +#define IQM_RT_LP_BP__W 1 +#define IQM_RT_LP_BP__M 0x1 +#define IQM_RT_LP_BP__PRE 0x0 + +#define IQM_RT_DELAY__A 0x1850014 +#define IQM_RT_DELAY__W 7 +#define IQM_RT_DELAY__M 0x7F +#define IQM_RT_DELAY__PRE 0x45 + + + +#define IQM_CF_COMM_EXEC__A 0x1860000 +#define IQM_CF_COMM_EXEC__W 2 +#define IQM_CF_COMM_EXEC__M 0x3 +#define IQM_CF_COMM_EXEC__PRE 0x0 +#define IQM_CF_COMM_EXEC_STOP 0x0 +#define IQM_CF_COMM_EXEC_ACTIVE 0x1 +#define IQM_CF_COMM_EXEC_HOLD 0x2 + +#define IQM_CF_COMM_MB__A 0x1860002 +#define IQM_CF_COMM_MB__W 2 +#define IQM_CF_COMM_MB__M 0x3 +#define IQM_CF_COMM_MB__PRE 0x0 +#define IQM_CF_COMM_MB_CTL__B 0 +#define IQM_CF_COMM_MB_CTL__W 1 +#define IQM_CF_COMM_MB_CTL__M 0x1 +#define IQM_CF_COMM_MB_CTL__PRE 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_CF_COMM_MB_OBS__B 1 +#define IQM_CF_COMM_MB_OBS__W 1 +#define IQM_CF_COMM_MB_OBS__M 0x2 +#define IQM_CF_COMM_MB_OBS__PRE 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_CF_COMM_INT_REQ__A 0x1860003 +#define IQM_CF_COMM_INT_REQ__W 1 +#define IQM_CF_COMM_INT_REQ__M 0x1 +#define IQM_CF_COMM_INT_REQ__PRE 0x0 +#define IQM_CF_COMM_INT_STA__A 0x1860005 +#define IQM_CF_COMM_INT_STA__W 2 +#define IQM_CF_COMM_INT_STA__M 0x3 +#define IQM_CF_COMM_INT_STA__PRE 0x0 +#define IQM_CF_COMM_INT_STA_PM__B 0 +#define IQM_CF_COMM_INT_STA_PM__W 1 +#define IQM_CF_COMM_INT_STA_PM__M 0x1 +#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 +#define IQM_CF_COMM_INT_STA_INC__B 1 +#define IQM_CF_COMM_INT_STA_INC__W 1 +#define IQM_CF_COMM_INT_STA_INC__M 0x2 +#define IQM_CF_COMM_INT_STA_INC__PRE 0x0 + +#define IQM_CF_COMM_INT_MSK__A 0x1860006 +#define IQM_CF_COMM_INT_MSK__W 2 +#define IQM_CF_COMM_INT_MSK__M 0x3 +#define IQM_CF_COMM_INT_MSK__PRE 0x0 +#define IQM_CF_COMM_INT_MSK_PM__B 0 +#define IQM_CF_COMM_INT_MSK_PM__W 1 +#define IQM_CF_COMM_INT_MSK_PM__M 0x1 +#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 +#define IQM_CF_COMM_INT_MSK_INC__B 1 +#define IQM_CF_COMM_INT_MSK_INC__W 1 +#define IQM_CF_COMM_INT_MSK_INC__M 0x2 +#define IQM_CF_COMM_INT_MSK_INC__PRE 0x0 + +#define IQM_CF_COMM_INT_STM__A 0x1860007 +#define IQM_CF_COMM_INT_STM__W 2 +#define IQM_CF_COMM_INT_STM__M 0x3 +#define IQM_CF_COMM_INT_STM__PRE 0x0 +#define IQM_CF_COMM_INT_STM_PM__B 0 +#define IQM_CF_COMM_INT_STM_PM__W 1 +#define IQM_CF_COMM_INT_STM_PM__M 0x1 +#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 +#define IQM_CF_COMM_INT_STM_INC__B 1 +#define IQM_CF_COMM_INT_STM_INC__W 1 +#define IQM_CF_COMM_INT_STM_INC__M 0x2 +#define IQM_CF_COMM_INT_STM_INC__PRE 0x0 + +#define IQM_CF_SYMMETRIC__A 0x1860010 +#define IQM_CF_SYMMETRIC__W 2 +#define IQM_CF_SYMMETRIC__M 0x3 +#define IQM_CF_SYMMETRIC__PRE 0x0 + +#define IQM_CF_SYMMETRIC_RE__B 0 +#define IQM_CF_SYMMETRIC_RE__W 1 +#define IQM_CF_SYMMETRIC_RE__M 0x1 +#define IQM_CF_SYMMETRIC_RE__PRE 0x0 + +#define IQM_CF_SYMMETRIC_IM__B 1 +#define IQM_CF_SYMMETRIC_IM__W 1 +#define IQM_CF_SYMMETRIC_IM__M 0x2 +#define IQM_CF_SYMMETRIC_IM__PRE 0x0 + +#define IQM_CF_MIDTAP__A 0x1860011 +#define IQM_CF_MIDTAP__W 3 +#define IQM_CF_MIDTAP__M 0x7 +#define IQM_CF_MIDTAP__PRE 0x3 + +#define IQM_CF_MIDTAP_RE__B 0 +#define IQM_CF_MIDTAP_RE__W 1 +#define IQM_CF_MIDTAP_RE__M 0x1 +#define IQM_CF_MIDTAP_RE__PRE 0x1 + +#define IQM_CF_MIDTAP_IM__B 1 +#define IQM_CF_MIDTAP_IM__W 1 +#define IQM_CF_MIDTAP_IM__M 0x2 +#define IQM_CF_MIDTAP_IM__PRE 0x2 + +#define IQM_CF_MIDTAP_SCALE__B 2 +#define IQM_CF_MIDTAP_SCALE__W 1 +#define IQM_CF_MIDTAP_SCALE__M 0x4 +#define IQM_CF_MIDTAP_SCALE__PRE 0x0 + +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_OUT_ENA__W 3 +#define IQM_CF_OUT_ENA__M 0x7 +#define IQM_CF_OUT_ENA__PRE 0x0 + +#define IQM_CF_OUT_ENA_ATV__B 0 +#define IQM_CF_OUT_ENA_ATV__W 1 +#define IQM_CF_OUT_ENA_ATV__M 0x1 +#define IQM_CF_OUT_ENA_ATV__PRE 0x0 + +#define IQM_CF_OUT_ENA_QAM__B 1 +#define IQM_CF_OUT_ENA_QAM__W 1 +#define IQM_CF_OUT_ENA_QAM__M 0x2 +#define IQM_CF_OUT_ENA_QAM__PRE 0x0 + +#define IQM_CF_OUT_ENA_OFDM__B 2 +#define IQM_CF_OUT_ENA_OFDM__W 1 +#define IQM_CF_OUT_ENA_OFDM__M 0x4 +#define IQM_CF_OUT_ENA_OFDM__PRE 0x0 + +#define IQM_CF_ADJ_SEL__A 0x1860013 +#define IQM_CF_ADJ_SEL__W 2 +#define IQM_CF_ADJ_SEL__M 0x3 +#define IQM_CF_ADJ_SEL__PRE 0x0 + +#define IQM_CF_ADJ_SEL_B__B 0 +#define IQM_CF_ADJ_SEL_B__W 2 +#define IQM_CF_ADJ_SEL_B__M 0x3 +#define IQM_CF_ADJ_SEL_B__PRE 0x0 + +#define IQM_CF_SCALE__A 0x1860014 +#define IQM_CF_SCALE__W 14 +#define IQM_CF_SCALE__M 0x3FFF +#define IQM_CF_SCALE__PRE 0x400 +#define IQM_CF_SCALE_B__B 0 +#define IQM_CF_SCALE_B__W 14 +#define IQM_CF_SCALE_B__M 0x3FFF +#define IQM_CF_SCALE_B__PRE 0x400 + +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__W 2 +#define IQM_CF_SCALE_SH__M 0x3 +#define IQM_CF_SCALE_SH__PRE 0x0 + +#define IQM_CF_SCALE_SH_B__B 0 +#define IQM_CF_SCALE_SH_B__W 2 +#define IQM_CF_SCALE_SH_B__M 0x3 +#define IQM_CF_SCALE_SH_B__PRE 0x0 + +#define IQM_CF_AMP__A 0x1860016 +#define IQM_CF_AMP__W 14 +#define IQM_CF_AMP__M 0x3FFF +#define IQM_CF_AMP__PRE 0x0 + +#define IQM_CF_AMP_B__B 0 +#define IQM_CF_AMP_B__W 14 +#define IQM_CF_AMP_B__M 0x3FFF +#define IQM_CF_AMP_B__PRE 0x0 + +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_POW_MEAS_LEN__W 3 +#define IQM_CF_POW_MEAS_LEN__M 0x7 +#define IQM_CF_POW_MEAS_LEN__PRE 0x2 + +#define IQM_CF_POW_MEAS_LEN_B__B 0 +#define IQM_CF_POW_MEAS_LEN_B__W 3 +#define IQM_CF_POW_MEAS_LEN_B__M 0x7 +#define IQM_CF_POW_MEAS_LEN_B__PRE 0x2 + +#define IQM_CF_POW__A 0x1860018 +#define IQM_CF_POW__W 16 +#define IQM_CF_POW__M 0xFFFF +#define IQM_CF_POW__PRE 0x2 +#define IQM_CF_POW_B__B 0 +#define IQM_CF_POW_B__W 16 +#define IQM_CF_POW_B__M 0xFFFF +#define IQM_CF_POW_B__PRE 0x2 + +#define IQM_CF_DS_ENA__A 0x1860019 +#define IQM_CF_DS_ENA__W 3 +#define IQM_CF_DS_ENA__M 0x7 +#define IQM_CF_DS_ENA__PRE 0x4 + +#define IQM_CF_DS_ENA_ATV__B 0 +#define IQM_CF_DS_ENA_ATV__W 1 +#define IQM_CF_DS_ENA_ATV__M 0x1 +#define IQM_CF_DS_ENA_ATV__PRE 0x0 + +#define IQM_CF_DS_ENA_QAM__B 1 +#define IQM_CF_DS_ENA_QAM__W 1 +#define IQM_CF_DS_ENA_QAM__M 0x2 +#define IQM_CF_DS_ENA_QAM__PRE 0x0 + +#define IQM_CF_DS_ENA_VSB__B 2 +#define IQM_CF_DS_ENA_VSB__W 1 +#define IQM_CF_DS_ENA_VSB__M 0x4 +#define IQM_CF_DS_ENA_VSB__PRE 0x4 + + +#define IQM_CF_POW_UPD__A 0x186001A +#define IQM_CF_POW_UPD__W 1 +#define IQM_CF_POW_UPD__M 0x1 +#define IQM_CF_POW_UPD__PRE 0x0 +#define IQM_CF_TAP_RE0__A 0x1860020 +#define IQM_CF_TAP_RE0__W 7 +#define IQM_CF_TAP_RE0__M 0x7F +#define IQM_CF_TAP_RE0__PRE 0x2 +#define IQM_CF_TAP_RE0_B__B 0 +#define IQM_CF_TAP_RE0_B__W 7 +#define IQM_CF_TAP_RE0_B__M 0x7F +#define IQM_CF_TAP_RE0_B__PRE 0x2 + +#define IQM_CF_TAP_RE1__A 0x1860021 +#define IQM_CF_TAP_RE1__W 7 +#define IQM_CF_TAP_RE1__M 0x7F +#define IQM_CF_TAP_RE1__PRE 0x2 +#define IQM_CF_TAP_RE1_B__B 0 +#define IQM_CF_TAP_RE1_B__W 7 +#define IQM_CF_TAP_RE1_B__M 0x7F +#define IQM_CF_TAP_RE1_B__PRE 0x2 + +#define IQM_CF_TAP_RE2__A 0x1860022 +#define IQM_CF_TAP_RE2__W 7 +#define IQM_CF_TAP_RE2__M 0x7F +#define IQM_CF_TAP_RE2__PRE 0x2 +#define IQM_CF_TAP_RE2_B__B 0 +#define IQM_CF_TAP_RE2_B__W 7 +#define IQM_CF_TAP_RE2_B__M 0x7F +#define IQM_CF_TAP_RE2_B__PRE 0x2 + +#define IQM_CF_TAP_RE3__A 0x1860023 +#define IQM_CF_TAP_RE3__W 7 +#define IQM_CF_TAP_RE3__M 0x7F +#define IQM_CF_TAP_RE3__PRE 0x2 +#define IQM_CF_TAP_RE3_B__B 0 +#define IQM_CF_TAP_RE3_B__W 7 +#define IQM_CF_TAP_RE3_B__M 0x7F +#define IQM_CF_TAP_RE3_B__PRE 0x2 + +#define IQM_CF_TAP_RE4__A 0x1860024 +#define IQM_CF_TAP_RE4__W 7 +#define IQM_CF_TAP_RE4__M 0x7F +#define IQM_CF_TAP_RE4__PRE 0x2 +#define IQM_CF_TAP_RE4_B__B 0 +#define IQM_CF_TAP_RE4_B__W 7 +#define IQM_CF_TAP_RE4_B__M 0x7F +#define IQM_CF_TAP_RE4_B__PRE 0x2 + +#define IQM_CF_TAP_RE5__A 0x1860025 +#define IQM_CF_TAP_RE5__W 7 +#define IQM_CF_TAP_RE5__M 0x7F +#define IQM_CF_TAP_RE5__PRE 0x2 +#define IQM_CF_TAP_RE5_B__B 0 +#define IQM_CF_TAP_RE5_B__W 7 +#define IQM_CF_TAP_RE5_B__M 0x7F +#define IQM_CF_TAP_RE5_B__PRE 0x2 + +#define IQM_CF_TAP_RE6__A 0x1860026 +#define IQM_CF_TAP_RE6__W 7 +#define IQM_CF_TAP_RE6__M 0x7F +#define IQM_CF_TAP_RE6__PRE 0x2 +#define IQM_CF_TAP_RE6_B__B 0 +#define IQM_CF_TAP_RE6_B__W 7 +#define IQM_CF_TAP_RE6_B__M 0x7F +#define IQM_CF_TAP_RE6_B__PRE 0x2 + +#define IQM_CF_TAP_RE7__A 0x1860027 +#define IQM_CF_TAP_RE7__W 9 +#define IQM_CF_TAP_RE7__M 0x1FF +#define IQM_CF_TAP_RE7__PRE 0x2 +#define IQM_CF_TAP_RE7_B__B 0 +#define IQM_CF_TAP_RE7_B__W 9 +#define IQM_CF_TAP_RE7_B__M 0x1FF +#define IQM_CF_TAP_RE7_B__PRE 0x2 + +#define IQM_CF_TAP_RE8__A 0x1860028 +#define IQM_CF_TAP_RE8__W 9 +#define IQM_CF_TAP_RE8__M 0x1FF +#define IQM_CF_TAP_RE8__PRE 0x2 +#define IQM_CF_TAP_RE8_B__B 0 +#define IQM_CF_TAP_RE8_B__W 9 +#define IQM_CF_TAP_RE8_B__M 0x1FF +#define IQM_CF_TAP_RE8_B__PRE 0x2 + +#define IQM_CF_TAP_RE9__A 0x1860029 +#define IQM_CF_TAP_RE9__W 9 +#define IQM_CF_TAP_RE9__M 0x1FF +#define IQM_CF_TAP_RE9__PRE 0x2 +#define IQM_CF_TAP_RE9_B__B 0 +#define IQM_CF_TAP_RE9_B__W 9 +#define IQM_CF_TAP_RE9_B__M 0x1FF +#define IQM_CF_TAP_RE9_B__PRE 0x2 + +#define IQM_CF_TAP_RE10__A 0x186002A +#define IQM_CF_TAP_RE10__W 9 +#define IQM_CF_TAP_RE10__M 0x1FF +#define IQM_CF_TAP_RE10__PRE 0x2 +#define IQM_CF_TAP_RE10_B__B 0 +#define IQM_CF_TAP_RE10_B__W 9 +#define IQM_CF_TAP_RE10_B__M 0x1FF +#define IQM_CF_TAP_RE10_B__PRE 0x2 + +#define IQM_CF_TAP_RE11__A 0x186002B +#define IQM_CF_TAP_RE11__W 9 +#define IQM_CF_TAP_RE11__M 0x1FF +#define IQM_CF_TAP_RE11__PRE 0x2 +#define IQM_CF_TAP_RE11_B__B 0 +#define IQM_CF_TAP_RE11_B__W 9 +#define IQM_CF_TAP_RE11_B__M 0x1FF +#define IQM_CF_TAP_RE11_B__PRE 0x2 + +#define IQM_CF_TAP_RE12__A 0x186002C +#define IQM_CF_TAP_RE12__W 9 +#define IQM_CF_TAP_RE12__M 0x1FF +#define IQM_CF_TAP_RE12__PRE 0x2 +#define IQM_CF_TAP_RE12_B__B 0 +#define IQM_CF_TAP_RE12_B__W 9 +#define IQM_CF_TAP_RE12_B__M 0x1FF +#define IQM_CF_TAP_RE12_B__PRE 0x2 + +#define IQM_CF_TAP_RE13__A 0x186002D +#define IQM_CF_TAP_RE13__W 9 +#define IQM_CF_TAP_RE13__M 0x1FF +#define IQM_CF_TAP_RE13__PRE 0x2 +#define IQM_CF_TAP_RE13_B__B 0 +#define IQM_CF_TAP_RE13_B__W 9 +#define IQM_CF_TAP_RE13_B__M 0x1FF +#define IQM_CF_TAP_RE13_B__PRE 0x2 + +#define IQM_CF_TAP_RE14__A 0x186002E +#define IQM_CF_TAP_RE14__W 9 +#define IQM_CF_TAP_RE14__M 0x1FF +#define IQM_CF_TAP_RE14__PRE 0x2 +#define IQM_CF_TAP_RE14_B__B 0 +#define IQM_CF_TAP_RE14_B__W 9 +#define IQM_CF_TAP_RE14_B__M 0x1FF +#define IQM_CF_TAP_RE14_B__PRE 0x2 + +#define IQM_CF_TAP_RE15__A 0x186002F +#define IQM_CF_TAP_RE15__W 9 +#define IQM_CF_TAP_RE15__M 0x1FF +#define IQM_CF_TAP_RE15__PRE 0x2 +#define IQM_CF_TAP_RE15_B__B 0 +#define IQM_CF_TAP_RE15_B__W 9 +#define IQM_CF_TAP_RE15_B__M 0x1FF +#define IQM_CF_TAP_RE15_B__PRE 0x2 + +#define IQM_CF_TAP_RE16__A 0x1860030 +#define IQM_CF_TAP_RE16__W 9 +#define IQM_CF_TAP_RE16__M 0x1FF +#define IQM_CF_TAP_RE16__PRE 0x2 +#define IQM_CF_TAP_RE16_B__B 0 +#define IQM_CF_TAP_RE16_B__W 9 +#define IQM_CF_TAP_RE16_B__M 0x1FF +#define IQM_CF_TAP_RE16_B__PRE 0x2 + +#define IQM_CF_TAP_RE17__A 0x1860031 +#define IQM_CF_TAP_RE17__W 9 +#define IQM_CF_TAP_RE17__M 0x1FF +#define IQM_CF_TAP_RE17__PRE 0x2 +#define IQM_CF_TAP_RE17_B__B 0 +#define IQM_CF_TAP_RE17_B__W 9 +#define IQM_CF_TAP_RE17_B__M 0x1FF +#define IQM_CF_TAP_RE17_B__PRE 0x2 + +#define IQM_CF_TAP_RE18__A 0x1860032 +#define IQM_CF_TAP_RE18__W 9 +#define IQM_CF_TAP_RE18__M 0x1FF +#define IQM_CF_TAP_RE18__PRE 0x2 +#define IQM_CF_TAP_RE18_B__B 0 +#define IQM_CF_TAP_RE18_B__W 9 +#define IQM_CF_TAP_RE18_B__M 0x1FF +#define IQM_CF_TAP_RE18_B__PRE 0x2 + +#define IQM_CF_TAP_RE19__A 0x1860033 +#define IQM_CF_TAP_RE19__W 9 +#define IQM_CF_TAP_RE19__M 0x1FF +#define IQM_CF_TAP_RE19__PRE 0x2 +#define IQM_CF_TAP_RE19_B__B 0 +#define IQM_CF_TAP_RE19_B__W 9 +#define IQM_CF_TAP_RE19_B__M 0x1FF +#define IQM_CF_TAP_RE19_B__PRE 0x2 + +#define IQM_CF_TAP_RE20__A 0x1860034 +#define IQM_CF_TAP_RE20__W 9 +#define IQM_CF_TAP_RE20__M 0x1FF +#define IQM_CF_TAP_RE20__PRE 0x2 +#define IQM_CF_TAP_RE20_B__B 0 +#define IQM_CF_TAP_RE20_B__W 9 +#define IQM_CF_TAP_RE20_B__M 0x1FF +#define IQM_CF_TAP_RE20_B__PRE 0x2 + +#define IQM_CF_TAP_RE21__A 0x1860035 +#define IQM_CF_TAP_RE21__W 11 +#define IQM_CF_TAP_RE21__M 0x7FF +#define IQM_CF_TAP_RE21__PRE 0x2 +#define IQM_CF_TAP_RE21_B__B 0 +#define IQM_CF_TAP_RE21_B__W 11 +#define IQM_CF_TAP_RE21_B__M 0x7FF +#define IQM_CF_TAP_RE21_B__PRE 0x2 + +#define IQM_CF_TAP_RE22__A 0x1860036 +#define IQM_CF_TAP_RE22__W 11 +#define IQM_CF_TAP_RE22__M 0x7FF +#define IQM_CF_TAP_RE22__PRE 0x2 +#define IQM_CF_TAP_RE22_B__B 0 +#define IQM_CF_TAP_RE22_B__W 11 +#define IQM_CF_TAP_RE22_B__M 0x7FF +#define IQM_CF_TAP_RE22_B__PRE 0x2 + +#define IQM_CF_TAP_RE23__A 0x1860037 +#define IQM_CF_TAP_RE23__W 11 +#define IQM_CF_TAP_RE23__M 0x7FF +#define IQM_CF_TAP_RE23__PRE 0x2 +#define IQM_CF_TAP_RE23_B__B 0 +#define IQM_CF_TAP_RE23_B__W 11 +#define IQM_CF_TAP_RE23_B__M 0x7FF +#define IQM_CF_TAP_RE23_B__PRE 0x2 + +#define IQM_CF_TAP_RE24__A 0x1860038 +#define IQM_CF_TAP_RE24__W 11 +#define IQM_CF_TAP_RE24__M 0x7FF +#define IQM_CF_TAP_RE24__PRE 0x2 +#define IQM_CF_TAP_RE24_B__B 0 +#define IQM_CF_TAP_RE24_B__W 11 +#define IQM_CF_TAP_RE24_B__M 0x7FF +#define IQM_CF_TAP_RE24_B__PRE 0x2 + +#define IQM_CF_TAP_RE25__A 0x1860039 +#define IQM_CF_TAP_RE25__W 11 +#define IQM_CF_TAP_RE25__M 0x7FF +#define IQM_CF_TAP_RE25__PRE 0x2 +#define IQM_CF_TAP_RE25_B__B 0 +#define IQM_CF_TAP_RE25_B__W 11 +#define IQM_CF_TAP_RE25_B__M 0x7FF +#define IQM_CF_TAP_RE25_B__PRE 0x2 + +#define IQM_CF_TAP_RE26__A 0x186003A +#define IQM_CF_TAP_RE26__W 11 +#define IQM_CF_TAP_RE26__M 0x7FF +#define IQM_CF_TAP_RE26__PRE 0x2 +#define IQM_CF_TAP_RE26_B__B 0 +#define IQM_CF_TAP_RE26_B__W 11 +#define IQM_CF_TAP_RE26_B__M 0x7FF +#define IQM_CF_TAP_RE26_B__PRE 0x2 + +#define IQM_CF_TAP_RE27__A 0x186003B +#define IQM_CF_TAP_RE27__W 11 +#define IQM_CF_TAP_RE27__M 0x7FF +#define IQM_CF_TAP_RE27__PRE 0x2 +#define IQM_CF_TAP_RE27_B__B 0 +#define IQM_CF_TAP_RE27_B__W 11 +#define IQM_CF_TAP_RE27_B__M 0x7FF +#define IQM_CF_TAP_RE27_B__PRE 0x2 + +#define IQM_CF_TAP_IM0__A 0x1860040 +#define IQM_CF_TAP_IM0__W 7 +#define IQM_CF_TAP_IM0__M 0x7F +#define IQM_CF_TAP_IM0__PRE 0x2 +#define IQM_CF_TAP_IM0_B__B 0 +#define IQM_CF_TAP_IM0_B__W 7 +#define IQM_CF_TAP_IM0_B__M 0x7F +#define IQM_CF_TAP_IM0_B__PRE 0x2 + +#define IQM_CF_TAP_IM1__A 0x1860041 +#define IQM_CF_TAP_IM1__W 7 +#define IQM_CF_TAP_IM1__M 0x7F +#define IQM_CF_TAP_IM1__PRE 0x2 +#define IQM_CF_TAP_IM1_B__B 0 +#define IQM_CF_TAP_IM1_B__W 7 +#define IQM_CF_TAP_IM1_B__M 0x7F +#define IQM_CF_TAP_IM1_B__PRE 0x2 + +#define IQM_CF_TAP_IM2__A 0x1860042 +#define IQM_CF_TAP_IM2__W 7 +#define IQM_CF_TAP_IM2__M 0x7F +#define IQM_CF_TAP_IM2__PRE 0x2 +#define IQM_CF_TAP_IM2_B__B 0 +#define IQM_CF_TAP_IM2_B__W 7 +#define IQM_CF_TAP_IM2_B__M 0x7F +#define IQM_CF_TAP_IM2_B__PRE 0x2 + +#define IQM_CF_TAP_IM3__A 0x1860043 +#define IQM_CF_TAP_IM3__W 7 +#define IQM_CF_TAP_IM3__M 0x7F +#define IQM_CF_TAP_IM3__PRE 0x2 +#define IQM_CF_TAP_IM3_B__B 0 +#define IQM_CF_TAP_IM3_B__W 7 +#define IQM_CF_TAP_IM3_B__M 0x7F +#define IQM_CF_TAP_IM3_B__PRE 0x2 + +#define IQM_CF_TAP_IM4__A 0x1860044 +#define IQM_CF_TAP_IM4__W 7 +#define IQM_CF_TAP_IM4__M 0x7F +#define IQM_CF_TAP_IM4__PRE 0x2 +#define IQM_CF_TAP_IM4_B__B 0 +#define IQM_CF_TAP_IM4_B__W 7 +#define IQM_CF_TAP_IM4_B__M 0x7F +#define IQM_CF_TAP_IM4_B__PRE 0x2 + +#define IQM_CF_TAP_IM5__A 0x1860045 +#define IQM_CF_TAP_IM5__W 7 +#define IQM_CF_TAP_IM5__M 0x7F +#define IQM_CF_TAP_IM5__PRE 0x2 +#define IQM_CF_TAP_IM5_B__B 0 +#define IQM_CF_TAP_IM5_B__W 7 +#define IQM_CF_TAP_IM5_B__M 0x7F +#define IQM_CF_TAP_IM5_B__PRE 0x2 + +#define IQM_CF_TAP_IM6__A 0x1860046 +#define IQM_CF_TAP_IM6__W 7 +#define IQM_CF_TAP_IM6__M 0x7F +#define IQM_CF_TAP_IM6__PRE 0x2 +#define IQM_CF_TAP_IM6_B__B 0 +#define IQM_CF_TAP_IM6_B__W 7 +#define IQM_CF_TAP_IM6_B__M 0x7F +#define IQM_CF_TAP_IM6_B__PRE 0x2 + +#define IQM_CF_TAP_IM7__A 0x1860047 +#define IQM_CF_TAP_IM7__W 9 +#define IQM_CF_TAP_IM7__M 0x1FF +#define IQM_CF_TAP_IM7__PRE 0x2 +#define IQM_CF_TAP_IM7_B__B 0 +#define IQM_CF_TAP_IM7_B__W 9 +#define IQM_CF_TAP_IM7_B__M 0x1FF +#define IQM_CF_TAP_IM7_B__PRE 0x2 + +#define IQM_CF_TAP_IM8__A 0x1860048 +#define IQM_CF_TAP_IM8__W 9 +#define IQM_CF_TAP_IM8__M 0x1FF +#define IQM_CF_TAP_IM8__PRE 0x2 +#define IQM_CF_TAP_IM8_B__B 0 +#define IQM_CF_TAP_IM8_B__W 9 +#define IQM_CF_TAP_IM8_B__M 0x1FF +#define IQM_CF_TAP_IM8_B__PRE 0x2 + +#define IQM_CF_TAP_IM9__A 0x1860049 +#define IQM_CF_TAP_IM9__W 9 +#define IQM_CF_TAP_IM9__M 0x1FF +#define IQM_CF_TAP_IM9__PRE 0x2 +#define IQM_CF_TAP_IM9_B__B 0 +#define IQM_CF_TAP_IM9_B__W 9 +#define IQM_CF_TAP_IM9_B__M 0x1FF +#define IQM_CF_TAP_IM9_B__PRE 0x2 + +#define IQM_CF_TAP_IM10__A 0x186004A +#define IQM_CF_TAP_IM10__W 9 +#define IQM_CF_TAP_IM10__M 0x1FF +#define IQM_CF_TAP_IM10__PRE 0x2 +#define IQM_CF_TAP_IM10_B__B 0 +#define IQM_CF_TAP_IM10_B__W 9 +#define IQM_CF_TAP_IM10_B__M 0x1FF +#define IQM_CF_TAP_IM10_B__PRE 0x2 + +#define IQM_CF_TAP_IM11__A 0x186004B +#define IQM_CF_TAP_IM11__W 9 +#define IQM_CF_TAP_IM11__M 0x1FF +#define IQM_CF_TAP_IM11__PRE 0x2 +#define IQM_CF_TAP_IM11_B__B 0 +#define IQM_CF_TAP_IM11_B__W 9 +#define IQM_CF_TAP_IM11_B__M 0x1FF +#define IQM_CF_TAP_IM11_B__PRE 0x2 + +#define IQM_CF_TAP_IM12__A 0x186004C +#define IQM_CF_TAP_IM12__W 9 +#define IQM_CF_TAP_IM12__M 0x1FF +#define IQM_CF_TAP_IM12__PRE 0x2 +#define IQM_CF_TAP_IM12_B__B 0 +#define IQM_CF_TAP_IM12_B__W 9 +#define IQM_CF_TAP_IM12_B__M 0x1FF +#define IQM_CF_TAP_IM12_B__PRE 0x2 + +#define IQM_CF_TAP_IM13__A 0x186004D +#define IQM_CF_TAP_IM13__W 9 +#define IQM_CF_TAP_IM13__M 0x1FF +#define IQM_CF_TAP_IM13__PRE 0x2 +#define IQM_CF_TAP_IM13_B__B 0 +#define IQM_CF_TAP_IM13_B__W 9 +#define IQM_CF_TAP_IM13_B__M 0x1FF +#define IQM_CF_TAP_IM13_B__PRE 0x2 + +#define IQM_CF_TAP_IM14__A 0x186004E +#define IQM_CF_TAP_IM14__W 9 +#define IQM_CF_TAP_IM14__M 0x1FF +#define IQM_CF_TAP_IM14__PRE 0x2 +#define IQM_CF_TAP_IM14_B__B 0 +#define IQM_CF_TAP_IM14_B__W 9 +#define IQM_CF_TAP_IM14_B__M 0x1FF +#define IQM_CF_TAP_IM14_B__PRE 0x2 + +#define IQM_CF_TAP_IM15__A 0x186004F +#define IQM_CF_TAP_IM15__W 9 +#define IQM_CF_TAP_IM15__M 0x1FF +#define IQM_CF_TAP_IM15__PRE 0x2 +#define IQM_CF_TAP_IM15_B__B 0 +#define IQM_CF_TAP_IM15_B__W 9 +#define IQM_CF_TAP_IM15_B__M 0x1FF +#define IQM_CF_TAP_IM15_B__PRE 0x2 + +#define IQM_CF_TAP_IM16__A 0x1860050 +#define IQM_CF_TAP_IM16__W 9 +#define IQM_CF_TAP_IM16__M 0x1FF +#define IQM_CF_TAP_IM16__PRE 0x2 +#define IQM_CF_TAP_IM16_B__B 0 +#define IQM_CF_TAP_IM16_B__W 9 +#define IQM_CF_TAP_IM16_B__M 0x1FF +#define IQM_CF_TAP_IM16_B__PRE 0x2 + +#define IQM_CF_TAP_IM17__A 0x1860051 +#define IQM_CF_TAP_IM17__W 9 +#define IQM_CF_TAP_IM17__M 0x1FF +#define IQM_CF_TAP_IM17__PRE 0x2 +#define IQM_CF_TAP_IM17_B__B 0 +#define IQM_CF_TAP_IM17_B__W 9 +#define IQM_CF_TAP_IM17_B__M 0x1FF +#define IQM_CF_TAP_IM17_B__PRE 0x2 + +#define IQM_CF_TAP_IM18__A 0x1860052 +#define IQM_CF_TAP_IM18__W 9 +#define IQM_CF_TAP_IM18__M 0x1FF +#define IQM_CF_TAP_IM18__PRE 0x2 +#define IQM_CF_TAP_IM18_B__B 0 +#define IQM_CF_TAP_IM18_B__W 9 +#define IQM_CF_TAP_IM18_B__M 0x1FF +#define IQM_CF_TAP_IM18_B__PRE 0x2 + +#define IQM_CF_TAP_IM19__A 0x1860053 +#define IQM_CF_TAP_IM19__W 9 +#define IQM_CF_TAP_IM19__M 0x1FF +#define IQM_CF_TAP_IM19__PRE 0x2 +#define IQM_CF_TAP_IM19_B__B 0 +#define IQM_CF_TAP_IM19_B__W 9 +#define IQM_CF_TAP_IM19_B__M 0x1FF +#define IQM_CF_TAP_IM19_B__PRE 0x2 + +#define IQM_CF_TAP_IM20__A 0x1860054 +#define IQM_CF_TAP_IM20__W 9 +#define IQM_CF_TAP_IM20__M 0x1FF +#define IQM_CF_TAP_IM20__PRE 0x2 +#define IQM_CF_TAP_IM20_B__B 0 +#define IQM_CF_TAP_IM20_B__W 9 +#define IQM_CF_TAP_IM20_B__M 0x1FF +#define IQM_CF_TAP_IM20_B__PRE 0x2 + +#define IQM_CF_TAP_IM21__A 0x1860055 +#define IQM_CF_TAP_IM21__W 11 +#define IQM_CF_TAP_IM21__M 0x7FF +#define IQM_CF_TAP_IM21__PRE 0x2 +#define IQM_CF_TAP_IM21_B__B 0 +#define IQM_CF_TAP_IM21_B__W 11 +#define IQM_CF_TAP_IM21_B__M 0x7FF +#define IQM_CF_TAP_IM21_B__PRE 0x2 + +#define IQM_CF_TAP_IM22__A 0x1860056 +#define IQM_CF_TAP_IM22__W 11 +#define IQM_CF_TAP_IM22__M 0x7FF +#define IQM_CF_TAP_IM22__PRE 0x2 +#define IQM_CF_TAP_IM22_B__B 0 +#define IQM_CF_TAP_IM22_B__W 11 +#define IQM_CF_TAP_IM22_B__M 0x7FF +#define IQM_CF_TAP_IM22_B__PRE 0x2 + +#define IQM_CF_TAP_IM23__A 0x1860057 +#define IQM_CF_TAP_IM23__W 11 +#define IQM_CF_TAP_IM23__M 0x7FF +#define IQM_CF_TAP_IM23__PRE 0x2 +#define IQM_CF_TAP_IM23_B__B 0 +#define IQM_CF_TAP_IM23_B__W 11 +#define IQM_CF_TAP_IM23_B__M 0x7FF +#define IQM_CF_TAP_IM23_B__PRE 0x2 + +#define IQM_CF_TAP_IM24__A 0x1860058 +#define IQM_CF_TAP_IM24__W 11 +#define IQM_CF_TAP_IM24__M 0x7FF +#define IQM_CF_TAP_IM24__PRE 0x2 +#define IQM_CF_TAP_IM24_B__B 0 +#define IQM_CF_TAP_IM24_B__W 11 +#define IQM_CF_TAP_IM24_B__M 0x7FF +#define IQM_CF_TAP_IM24_B__PRE 0x2 + +#define IQM_CF_TAP_IM25__A 0x1860059 +#define IQM_CF_TAP_IM25__W 11 +#define IQM_CF_TAP_IM25__M 0x7FF +#define IQM_CF_TAP_IM25__PRE 0x2 +#define IQM_CF_TAP_IM25_B__B 0 +#define IQM_CF_TAP_IM25_B__W 11 +#define IQM_CF_TAP_IM25_B__M 0x7FF +#define IQM_CF_TAP_IM25_B__PRE 0x2 + +#define IQM_CF_TAP_IM26__A 0x186005A +#define IQM_CF_TAP_IM26__W 11 +#define IQM_CF_TAP_IM26__M 0x7FF +#define IQM_CF_TAP_IM26__PRE 0x2 +#define IQM_CF_TAP_IM26_B__B 0 +#define IQM_CF_TAP_IM26_B__W 11 +#define IQM_CF_TAP_IM26_B__M 0x7FF +#define IQM_CF_TAP_IM26_B__PRE 0x2 + +#define IQM_CF_TAP_IM27__A 0x186005B +#define IQM_CF_TAP_IM27__W 11 +#define IQM_CF_TAP_IM27__M 0x7FF +#define IQM_CF_TAP_IM27__PRE 0x2 +#define IQM_CF_TAP_IM27_B__B 0 +#define IQM_CF_TAP_IM27_B__W 11 +#define IQM_CF_TAP_IM27_B__M 0x7FF +#define IQM_CF_TAP_IM27_B__PRE 0x2 + + +#define IQM_CF_CLP_VAL__A 0x1860060 +#define IQM_CF_CLP_VAL__W 9 +#define IQM_CF_CLP_VAL__M 0x1FF +#define IQM_CF_CLP_VAL__PRE 0x3C + +#define IQM_CF_DATATH__A 0x1860061 +#define IQM_CF_DATATH__W 10 +#define IQM_CF_DATATH__M 0x3FF +#define IQM_CF_DATATH__PRE 0x180 + +#define IQM_CF_PKDTH__A 0x1860062 +#define IQM_CF_PKDTH__W 5 +#define IQM_CF_PKDTH__M 0x1F +#define IQM_CF_PKDTH__PRE 0x1 + +#define IQM_CF_WND_LEN__A 0x1860063 +#define IQM_CF_WND_LEN__W 4 +#define IQM_CF_WND_LEN__M 0xF +#define IQM_CF_WND_LEN__PRE 0x1 + +#define IQM_CF_DET_LCT__A 0x1860064 +#define IQM_CF_DET_LCT__W 1 +#define IQM_CF_DET_LCT__M 0x1 +#define IQM_CF_DET_LCT__PRE 0x1 + +#define IQM_CF_SNS_LEN__A 0x1860065 +#define IQM_CF_SNS_LEN__W 16 +#define IQM_CF_SNS_LEN__M 0xFFFF +#define IQM_CF_SNS_LEN__PRE 0x0 + +#define IQM_CF_SNS_SENSE__A 0x1860066 +#define IQM_CF_SNS_SENSE__W 16 +#define IQM_CF_SNS_SENSE__M 0xFFFF +#define IQM_CF_SNS_SENSE__PRE 0x0 + +#define IQM_CF_BYPASSDET__A 0x1860067 +#define IQM_CF_BYPASSDET__W 1 +#define IQM_CF_BYPASSDET__M 0x1 +#define IQM_CF_BYPASSDET__PRE 0x0 + +#define IQM_CF_UPD_ENA__A 0x1860068 +#define IQM_CF_UPD_ENA__W 1 +#define IQM_CF_UPD_ENA__M 0x1 +#define IQM_CF_UPD_ENA__PRE 0x0 +#define IQM_CF_UPD_ENA_DISABLE 0x0 +#define IQM_CF_UPD_ENA_ENABLE 0x1 + + + +#define IQM_AF_COMM_EXEC__A 0x1870000 +#define IQM_AF_COMM_EXEC__W 2 +#define IQM_AF_COMM_EXEC__M 0x3 +#define IQM_AF_COMM_EXEC__PRE 0x0 +#define IQM_AF_COMM_EXEC_STOP 0x0 +#define IQM_AF_COMM_EXEC_ACTIVE 0x1 +#define IQM_AF_COMM_EXEC_HOLD 0x2 + +#define IQM_AF_COMM_MB__A 0x1870002 +#define IQM_AF_COMM_MB__W 8 +#define IQM_AF_COMM_MB__M 0xFF +#define IQM_AF_COMM_MB__PRE 0x0 +#define IQM_AF_COMM_MB_CTL__B 0 +#define IQM_AF_COMM_MB_CTL__W 1 +#define IQM_AF_COMM_MB_CTL__M 0x1 +#define IQM_AF_COMM_MB_CTL__PRE 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_AF_COMM_MB_OBS__B 1 +#define IQM_AF_COMM_MB_OBS__W 1 +#define IQM_AF_COMM_MB_OBS__M 0x2 +#define IQM_AF_COMM_MB_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 +#define IQM_AF_COMM_MB_MUX_CTRL__B 2 +#define IQM_AF_COMM_MB_MUX_CTRL__W 3 +#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C +#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 +#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC +#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 +#define IQM_AF_COMM_MB_MUX_CTRL_CMP_ERR_DN 0x14 +#define IQM_AF_COMM_MB_MUX_OBS__B 5 +#define IQM_AF_COMM_MB_MUX_OBS__W 3 +#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 +#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 +#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 +#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 +#define IQM_AF_COMM_MB_MUX_OBS_CMP_ERR_DN 0xA0 + +#define IQM_AF_COMM_INT_REQ__A 0x1870003 +#define IQM_AF_COMM_INT_REQ__W 1 +#define IQM_AF_COMM_INT_REQ__M 0x1 +#define IQM_AF_COMM_INT_REQ__PRE 0x0 +#define IQM_AF_COMM_INT_STA__A 0x1870005 +#define IQM_AF_COMM_INT_STA__W 3 +#define IQM_AF_COMM_INT_STA__M 0x7 +#define IQM_AF_COMM_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__B 2 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__M 0x4 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__PRE 0x0 + +#define IQM_AF_COMM_INT_MSK__A 0x1870006 +#define IQM_AF_COMM_INT_MSK__W 3 +#define IQM_AF_COMM_INT_MSK__M 0x7 +#define IQM_AF_COMM_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__B 2 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__M 0x4 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__PRE 0x0 + +#define IQM_AF_COMM_INT_STM__A 0x1870007 +#define IQM_AF_COMM_INT_STM__W 3 +#define IQM_AF_COMM_INT_STM__M 0x7 +#define IQM_AF_COMM_INT_STM__PRE 0x0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__B 2 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__M 0x4 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__PRE 0x0 + + +#define IQM_AF_FDB_SEL__A 0x1870010 +#define IQM_AF_FDB_SEL__W 2 +#define IQM_AF_FDB_SEL__M 0x3 +#define IQM_AF_FDB_SEL__PRE 0x0 +#define IQM_AF_CLKNEG__A 0x1870012 +#define IQM_AF_CLKNEG__W 2 +#define IQM_AF_CLKNEG__M 0x3 +#define IQM_AF_CLKNEG__PRE 0x0 + +#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 +#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 + +#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 +#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 + + +#define IQM_AF_MON_IN_MUX__A 0x1870013 +#define IQM_AF_MON_IN_MUX__W 2 +#define IQM_AF_MON_IN_MUX__M 0x3 +#define IQM_AF_MON_IN_MUX__PRE 0x0 + +#define IQM_AF_MON_IN5__A 0x1870014 +#define IQM_AF_MON_IN5__W 10 +#define IQM_AF_MON_IN5__M 0x3FF +#define IQM_AF_MON_IN5__PRE 0x0 + +#define IQM_AF_MON_IN4__A 0x1870015 +#define IQM_AF_MON_IN4__W 10 +#define IQM_AF_MON_IN4__M 0x3FF +#define IQM_AF_MON_IN4__PRE 0x0 + +#define IQM_AF_MON_IN3__A 0x1870016 +#define IQM_AF_MON_IN3__W 10 +#define IQM_AF_MON_IN3__M 0x3FF +#define IQM_AF_MON_IN3__PRE 0x0 + +#define IQM_AF_MON_IN2__A 0x1870017 +#define IQM_AF_MON_IN2__W 10 +#define IQM_AF_MON_IN2__M 0x3FF +#define IQM_AF_MON_IN2__PRE 0x0 + +#define IQM_AF_MON_IN1__A 0x1870018 +#define IQM_AF_MON_IN1__W 10 +#define IQM_AF_MON_IN1__M 0x3FF +#define IQM_AF_MON_IN1__PRE 0x0 + +#define IQM_AF_MON_IN0__A 0x1870019 +#define IQM_AF_MON_IN0__W 10 +#define IQM_AF_MON_IN0__M 0x3FF +#define IQM_AF_MON_IN0__PRE 0x0 + +#define IQM_AF_MON_IN_VAL__A 0x187001A +#define IQM_AF_MON_IN_VAL__W 1 +#define IQM_AF_MON_IN_VAL__M 0x1 +#define IQM_AF_MON_IN_VAL__PRE 0x0 + +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_START_LOCK__W 1 +#define IQM_AF_START_LOCK__M 0x1 +#define IQM_AF_START_LOCK__PRE 0x0 + +#define IQM_AF_PHASE0__A 0x187001C +#define IQM_AF_PHASE0__W 7 +#define IQM_AF_PHASE0__M 0x7F +#define IQM_AF_PHASE0__PRE 0x0 + +#define IQM_AF_PHASE1__A 0x187001D +#define IQM_AF_PHASE1__W 7 +#define IQM_AF_PHASE1__M 0x7F +#define IQM_AF_PHASE1__PRE 0x0 + +#define IQM_AF_PHASE2__A 0x187001E +#define IQM_AF_PHASE2__W 7 +#define IQM_AF_PHASE2__M 0x7F +#define IQM_AF_PHASE2__PRE 0x0 + +#define IQM_AF_SCU_PHASE__A 0x187001F +#define IQM_AF_SCU_PHASE__W 2 +#define IQM_AF_SCU_PHASE__M 0x3 +#define IQM_AF_SCU_PHASE__PRE 0x0 + +#define IQM_AF_SYNC_SEL__A 0x1870020 +#define IQM_AF_SYNC_SEL__W 2 +#define IQM_AF_SYNC_SEL__M 0x3 +#define IQM_AF_SYNC_SEL__PRE 0x0 +#define IQM_AF_ADC_CONF__A 0x1870021 +#define IQM_AF_ADC_CONF__W 4 +#define IQM_AF_ADC_CONF__M 0xF +#define IQM_AF_ADC_CONF__PRE 0x0 + +#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 +#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 +#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 +#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 + +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 + + +#define IQM_AF_CLP_CLIP__A 0x1870022 +#define IQM_AF_CLP_CLIP__W 16 +#define IQM_AF_CLP_CLIP__M 0xFFFF +#define IQM_AF_CLP_CLIP__PRE 0x0 + +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_LEN__W 16 +#define IQM_AF_CLP_LEN__M 0xFFFF +#define IQM_AF_CLP_LEN__PRE 0x0 + +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_CLP_TH__W 9 +#define IQM_AF_CLP_TH__M 0x1FF +#define IQM_AF_CLP_TH__PRE 0x0 + +#define IQM_AF_DCF_BYPASS__A 0x1870025 +#define IQM_AF_DCF_BYPASS__W 1 +#define IQM_AF_DCF_BYPASS__M 0x1 +#define IQM_AF_DCF_BYPASS__PRE 0x0 +#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 +#define IQM_AF_DCF_BYPASS_BYPASS 0x1 + + +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_SNS_LEN__W 16 +#define IQM_AF_SNS_LEN__M 0xFFFF +#define IQM_AF_SNS_LEN__PRE 0x0 + +#define IQM_AF_SNS_SENSE__A 0x1870027 +#define IQM_AF_SNS_SENSE__W 16 +#define IQM_AF_SNS_SENSE__M 0xFFFF +#define IQM_AF_SNS_SENSE__PRE 0x0 + +#define IQM_AF_AGC_IF__A 0x1870028 +#define IQM_AF_AGC_IF__W 15 +#define IQM_AF_AGC_IF__M 0x7FFF +#define IQM_AF_AGC_IF__PRE 0x0 + +#define IQM_AF_AGC_RF__A 0x1870029 +#define IQM_AF_AGC_RF__W 15 +#define IQM_AF_AGC_RF__M 0x7FFF +#define IQM_AF_AGC_RF__PRE 0x0 + +#define IQM_AF_PDREF__A 0x187002B +#define IQM_AF_PDREF__W 5 +#define IQM_AF_PDREF__M 0x1F +#define IQM_AF_PDREF__PRE 0x0 +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__W 6 +#define IQM_AF_STDBY__M 0x3F +#define IQM_AF_STDBY__PRE 0x3E + +#define IQM_AF_STDBY_STDBY_BIAS__B 0 +#define IQM_AF_STDBY_STDBY_BIAS__W 1 +#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 +#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 + +#define IQM_AF_STDBY_STDBY_ADC__B 1 +#define IQM_AF_STDBY_STDBY_ADC__W 1 +#define IQM_AF_STDBY_STDBY_ADC__M 0x2 +#define IQM_AF_STDBY_STDBY_ADC__PRE 0x2 +#define IQM_AF_STDBY_STDBY_ADC_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 + +#define IQM_AF_STDBY_STDBY_AMP__B 2 +#define IQM_AF_STDBY_STDBY_AMP__W 1 +#define IQM_AF_STDBY_STDBY_AMP__M 0x4 +#define IQM_AF_STDBY_STDBY_AMP__PRE 0x4 +#define IQM_AF_STDBY_STDBY_AMP_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 + +#define IQM_AF_STDBY_STDBY_PD__B 3 +#define IQM_AF_STDBY_STDBY_PD__W 1 +#define IQM_AF_STDBY_STDBY_PD__M 0x8 +#define IQM_AF_STDBY_STDBY_PD__PRE 0x8 +#define IQM_AF_STDBY_STDBY_PD_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 + +#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 +#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 + +#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 +#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 + + +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_AMUX__W 1 +#define IQM_AF_AMUX__M 0x1 +#define IQM_AF_AMUX__PRE 0x0 +#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 +#define IQM_AF_AMUX_SIGNAL2ADC 0x1 + + +#define IQM_AF_TST_AFEMAIN__A 0x187002E +#define IQM_AF_TST_AFEMAIN__W 8 +#define IQM_AF_TST_AFEMAIN__M 0xFF +#define IQM_AF_TST_AFEMAIN__PRE 0x0 + +#define IQM_AF_UPD_SEL__A 0x187002F +#define IQM_AF_UPD_SEL__W 1 +#define IQM_AF_UPD_SEL__M 0x1 +#define IQM_AF_UPD_SEL__PRE 0x0 + +#define IQM_AF_INC_DATATH__A 0x1870030 +#define IQM_AF_INC_DATATH__W 9 +#define IQM_AF_INC_DATATH__M 0x1FF +#define IQM_AF_INC_DATATH__PRE 0x180 + +#define IQM_AF_INC_PKDTH__A 0x1870031 +#define IQM_AF_INC_PKDTH__W 5 +#define IQM_AF_INC_PKDTH__M 0x1F +#define IQM_AF_INC_PKDTH__PRE 0x3 + +#define IQM_AF_INC_WND_LEN__A 0x1870032 +#define IQM_AF_INC_WND_LEN__W 4 +#define IQM_AF_INC_WND_LEN__M 0xF +#define IQM_AF_INC_WND_LEN__PRE 0xA + +#define IQM_AF_INC_DLY__A 0x1870033 +#define IQM_AF_INC_DLY__W 7 +#define IQM_AF_INC_DLY__M 0x7F +#define IQM_AF_INC_DLY__PRE 0x14 + +#define IQM_AF_INC_LCT__A 0x1870034 +#define IQM_AF_INC_LCT__W 1 +#define IQM_AF_INC_LCT__M 0x1 +#define IQM_AF_INC_LCT__PRE 0x1 + +#define IQM_AF_INC_CLP_VAL__A 0x1870035 +#define IQM_AF_INC_CLP_VAL__W 9 +#define IQM_AF_INC_CLP_VAL__M 0x1FF +#define IQM_AF_INC_CLP_VAL__PRE 0x3C + +#define IQM_AF_INC_BYPASS__A 0x1870036 +#define IQM_AF_INC_BYPASS__W 1 +#define IQM_AF_INC_BYPASS__M 0x1 +#define IQM_AF_INC_BYPASS__PRE 0x1 + +#define IQM_AF_INC_MODE_SEL__A 0x1870037 +#define IQM_AF_INC_MODE_SEL__W 2 +#define IQM_AF_INC_MODE_SEL__M 0x3 +#define IQM_AF_INC_MODE_SEL__PRE 0x1 + +#define IQM_AF_INC_A_DLY__A 0x1870038 +#define IQM_AF_INC_A_DLY__W 6 +#define IQM_AF_INC_A_DLY__M 0x3F +#define IQM_AF_INC_A_DLY__PRE 0xF + +#define IQM_AF_ISNS_LEN__A 0x1870039 +#define IQM_AF_ISNS_LEN__W 16 +#define IQM_AF_ISNS_LEN__M 0xFFFF +#define IQM_AF_ISNS_LEN__PRE 0x0 + +#define IQM_AF_ISNS_SENSE__A 0x187003A +#define IQM_AF_ISNS_SENSE__W 16 +#define IQM_AF_ISNS_SENSE__M 0xFFFF +#define IQM_AF_ISNS_SENSE__PRE 0x0 +#define IQM_AF_CMP_STATE__A 0x187003B +#define IQM_AF_CMP_STATE__W 7 +#define IQM_AF_CMP_STATE__M 0x7F +#define IQM_AF_CMP_STATE__PRE 0x0 + +#define IQM_AF_CMP_STATE_STATE__B 0 +#define IQM_AF_CMP_STATE_STATE__W 2 +#define IQM_AF_CMP_STATE_STATE__M 0x3 +#define IQM_AF_CMP_STATE_STATE__PRE 0x0 + +#define IQM_AF_CMP_STATE_ENABLE_CORING__B 2 +#define IQM_AF_CMP_STATE_ENABLE_CORING__W 1 +#define IQM_AF_CMP_STATE_ENABLE_CORING__M 0x4 +#define IQM_AF_CMP_STATE_ENABLE_CORING__PRE 0x0 + +#define IQM_AF_CMP_STATE_FILTERGAIN__B 3 +#define IQM_AF_CMP_STATE_FILTERGAIN__W 2 +#define IQM_AF_CMP_STATE_FILTERGAIN__M 0x18 +#define IQM_AF_CMP_STATE_FILTERGAIN__PRE 0x0 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER128 0x0 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER64 0x8 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER32 0x10 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER16 0x18 + +#define IQM_AF_CMP_STATE_KEEPCOEFF__B 5 +#define IQM_AF_CMP_STATE_KEEPCOEFF__W 1 +#define IQM_AF_CMP_STATE_KEEPCOEFF__M 0x20 +#define IQM_AF_CMP_STATE_KEEPCOEFF__PRE 0x0 + +#define IQM_AF_CMP_STATE_SEG64__B 6 +#define IQM_AF_CMP_STATE_SEG64__W 1 +#define IQM_AF_CMP_STATE_SEG64__M 0x40 +#define IQM_AF_CMP_STATE_SEG64__PRE 0x0 +#define IQM_AF_CMP_STATE_SEG64_SEG32 0x0 +#define IQM_AF_CMP_STATE_SEG64_SEG64 0x40 + + +#define IQM_AF_CMP_DC_OUT__A 0x187003C +#define IQM_AF_CMP_DC_OUT__W 12 +#define IQM_AF_CMP_DC_OUT__M 0xFFF +#define IQM_AF_CMP_DC_OUT__PRE 0x0 +#define IQM_AF_CMP_DC_IN__A 0x187003D +#define IQM_AF_CMP_DC_IN__W 13 +#define IQM_AF_CMP_DC_IN__M 0x1FFF +#define IQM_AF_CMP_DC_IN__PRE 0x0 + +#define IQM_AF_CMP_DC_IN_DC__B 0 +#define IQM_AF_CMP_DC_IN_DC__W 12 +#define IQM_AF_CMP_DC_IN_DC__M 0xFFF +#define IQM_AF_CMP_DC_IN_DC__PRE 0x0 +#define IQM_AF_CMP_DC_IN_DC_EN__B 12 +#define IQM_AF_CMP_DC_IN_DC_EN__W 1 +#define IQM_AF_CMP_DC_IN_DC_EN__M 0x1000 +#define IQM_AF_CMP_DC_IN_DC_EN__PRE 0x0 +#define IQM_AF_CMP_DC_IN_DC_EN_DISABLE 0x0 +#define IQM_AF_CMP_DC_IN_DC_EN_ENABLE 0x1000 + + +#define IQM_AF_CMP_AMP__A 0x187003E +#define IQM_AF_CMP_AMP__W 10 +#define IQM_AF_CMP_AMP__M 0x3FF +#define IQM_AF_CMP_AMP__PRE 0x0 +#define IQM_AF_CMP_DN_AVG__A 0x187003F +#define IQM_AF_CMP_DN_AVG__W 8 +#define IQM_AF_CMP_DN_AVG__M 0xFF +#define IQM_AF_CMP_DN_AVG__PRE 0x0 + +#define IQM_AF_CMP_DN_AVG_DN_AVG__B 0 +#define IQM_AF_CMP_DN_AVG_DN_AVG__W 8 +#define IQM_AF_CMP_DN_AVG_DN_AVG__M 0xFF +#define IQM_AF_CMP_DN_AVG_DN_AVG__PRE 0x0 + + +#define IQM_AF_CMP_ACTIVE__A 0x1870040 +#define IQM_AF_CMP_ACTIVE__W 1 +#define IQM_AF_CMP_ACTIVE__M 0x1 +#define IQM_AF_CMP_ACTIVE__PRE 0x0 +#define IQM_AF_CMP_MEM0__A 0x1870080 +#define IQM_AF_CMP_MEM0__W 13 +#define IQM_AF_CMP_MEM0__M 0x1FFF +#define IQM_AF_CMP_MEM0__PRE 0x0 + +#define IQM_AF_CMP_MEM0_COEF__B 0 +#define IQM_AF_CMP_MEM0_COEF__W 13 +#define IQM_AF_CMP_MEM0_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM0_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM1__A 0x1870081 +#define IQM_AF_CMP_MEM1__W 13 +#define IQM_AF_CMP_MEM1__M 0x1FFF +#define IQM_AF_CMP_MEM1__PRE 0x0 + +#define IQM_AF_CMP_MEM1_COEF__B 0 +#define IQM_AF_CMP_MEM1_COEF__W 13 +#define IQM_AF_CMP_MEM1_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM1_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM2__A 0x1870082 +#define IQM_AF_CMP_MEM2__W 13 +#define IQM_AF_CMP_MEM2__M 0x1FFF +#define IQM_AF_CMP_MEM2__PRE 0x0 + +#define IQM_AF_CMP_MEM2_COEF__B 0 +#define IQM_AF_CMP_MEM2_COEF__W 13 +#define IQM_AF_CMP_MEM2_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM2_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM3__A 0x1870083 +#define IQM_AF_CMP_MEM3__W 13 +#define IQM_AF_CMP_MEM3__M 0x1FFF +#define IQM_AF_CMP_MEM3__PRE 0x0 + +#define IQM_AF_CMP_MEM3_COEF__B 0 +#define IQM_AF_CMP_MEM3_COEF__W 13 +#define IQM_AF_CMP_MEM3_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM3_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM4__A 0x1870084 +#define IQM_AF_CMP_MEM4__W 13 +#define IQM_AF_CMP_MEM4__M 0x1FFF +#define IQM_AF_CMP_MEM4__PRE 0x0 + +#define IQM_AF_CMP_MEM4_COEF__B 0 +#define IQM_AF_CMP_MEM4_COEF__W 13 +#define IQM_AF_CMP_MEM4_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM4_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM5__A 0x1870085 +#define IQM_AF_CMP_MEM5__W 13 +#define IQM_AF_CMP_MEM5__M 0x1FFF +#define IQM_AF_CMP_MEM5__PRE 0x0 + +#define IQM_AF_CMP_MEM5_COEF__B 0 +#define IQM_AF_CMP_MEM5_COEF__W 13 +#define IQM_AF_CMP_MEM5_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM5_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM6__A 0x1870086 +#define IQM_AF_CMP_MEM6__W 13 +#define IQM_AF_CMP_MEM6__M 0x1FFF +#define IQM_AF_CMP_MEM6__PRE 0x0 + +#define IQM_AF_CMP_MEM6_COEF__B 0 +#define IQM_AF_CMP_MEM6_COEF__W 13 +#define IQM_AF_CMP_MEM6_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM6_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM7__A 0x1870087 +#define IQM_AF_CMP_MEM7__W 13 +#define IQM_AF_CMP_MEM7__M 0x1FFF +#define IQM_AF_CMP_MEM7__PRE 0x0 + +#define IQM_AF_CMP_MEM7_COEF__B 0 +#define IQM_AF_CMP_MEM7_COEF__W 13 +#define IQM_AF_CMP_MEM7_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM7_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM8__A 0x1870088 +#define IQM_AF_CMP_MEM8__W 13 +#define IQM_AF_CMP_MEM8__M 0x1FFF +#define IQM_AF_CMP_MEM8__PRE 0x0 + +#define IQM_AF_CMP_MEM8_COEF__B 0 +#define IQM_AF_CMP_MEM8_COEF__W 13 +#define IQM_AF_CMP_MEM8_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM8_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM9__A 0x1870089 +#define IQM_AF_CMP_MEM9__W 13 +#define IQM_AF_CMP_MEM9__M 0x1FFF +#define IQM_AF_CMP_MEM9__PRE 0x0 + +#define IQM_AF_CMP_MEM9_COEF__B 0 +#define IQM_AF_CMP_MEM9_COEF__W 13 +#define IQM_AF_CMP_MEM9_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM9_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM10__A 0x187008A +#define IQM_AF_CMP_MEM10__W 13 +#define IQM_AF_CMP_MEM10__M 0x1FFF +#define IQM_AF_CMP_MEM10__PRE 0x0 + +#define IQM_AF_CMP_MEM10_COEF__B 0 +#define IQM_AF_CMP_MEM10_COEF__W 13 +#define IQM_AF_CMP_MEM10_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM10_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM11__A 0x187008B +#define IQM_AF_CMP_MEM11__W 13 +#define IQM_AF_CMP_MEM11__M 0x1FFF +#define IQM_AF_CMP_MEM11__PRE 0x0 + +#define IQM_AF_CMP_MEM11_COEF__B 0 +#define IQM_AF_CMP_MEM11_COEF__W 13 +#define IQM_AF_CMP_MEM11_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM11_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM12__A 0x187008C +#define IQM_AF_CMP_MEM12__W 13 +#define IQM_AF_CMP_MEM12__M 0x1FFF +#define IQM_AF_CMP_MEM12__PRE 0x0 + +#define IQM_AF_CMP_MEM12_COEF__B 0 +#define IQM_AF_CMP_MEM12_COEF__W 13 +#define IQM_AF_CMP_MEM12_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM12_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM13__A 0x187008D +#define IQM_AF_CMP_MEM13__W 13 +#define IQM_AF_CMP_MEM13__M 0x1FFF +#define IQM_AF_CMP_MEM13__PRE 0x0 + +#define IQM_AF_CMP_MEM13_COEF__B 0 +#define IQM_AF_CMP_MEM13_COEF__W 13 +#define IQM_AF_CMP_MEM13_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM13_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM14__A 0x187008E +#define IQM_AF_CMP_MEM14__W 13 +#define IQM_AF_CMP_MEM14__M 0x1FFF +#define IQM_AF_CMP_MEM14__PRE 0x0 + +#define IQM_AF_CMP_MEM14_COEF__B 0 +#define IQM_AF_CMP_MEM14_COEF__W 13 +#define IQM_AF_CMP_MEM14_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM14_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM15__A 0x187008F +#define IQM_AF_CMP_MEM15__W 13 +#define IQM_AF_CMP_MEM15__M 0x1FFF +#define IQM_AF_CMP_MEM15__PRE 0x0 + +#define IQM_AF_CMP_MEM15_COEF__B 0 +#define IQM_AF_CMP_MEM15_COEF__W 13 +#define IQM_AF_CMP_MEM15_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM15_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM16__A 0x1870090 +#define IQM_AF_CMP_MEM16__W 13 +#define IQM_AF_CMP_MEM16__M 0x1FFF +#define IQM_AF_CMP_MEM16__PRE 0x0 + +#define IQM_AF_CMP_MEM16_COEF__B 0 +#define IQM_AF_CMP_MEM16_COEF__W 13 +#define IQM_AF_CMP_MEM16_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM16_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM17__A 0x1870091 +#define IQM_AF_CMP_MEM17__W 13 +#define IQM_AF_CMP_MEM17__M 0x1FFF +#define IQM_AF_CMP_MEM17__PRE 0x0 + +#define IQM_AF_CMP_MEM17_COEF__B 0 +#define IQM_AF_CMP_MEM17_COEF__W 13 +#define IQM_AF_CMP_MEM17_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM17_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM18__A 0x1870092 +#define IQM_AF_CMP_MEM18__W 13 +#define IQM_AF_CMP_MEM18__M 0x1FFF +#define IQM_AF_CMP_MEM18__PRE 0x0 + +#define IQM_AF_CMP_MEM18_COEF__B 0 +#define IQM_AF_CMP_MEM18_COEF__W 13 +#define IQM_AF_CMP_MEM18_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM18_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM19__A 0x1870093 +#define IQM_AF_CMP_MEM19__W 13 +#define IQM_AF_CMP_MEM19__M 0x1FFF +#define IQM_AF_CMP_MEM19__PRE 0x0 + +#define IQM_AF_CMP_MEM19_COEF__B 0 +#define IQM_AF_CMP_MEM19_COEF__W 13 +#define IQM_AF_CMP_MEM19_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM19_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM20__A 0x1870094 +#define IQM_AF_CMP_MEM20__W 13 +#define IQM_AF_CMP_MEM20__M 0x1FFF +#define IQM_AF_CMP_MEM20__PRE 0x0 + +#define IQM_AF_CMP_MEM20_COEF__B 0 +#define IQM_AF_CMP_MEM20_COEF__W 13 +#define IQM_AF_CMP_MEM20_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM20_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM21__A 0x1870095 +#define IQM_AF_CMP_MEM21__W 13 +#define IQM_AF_CMP_MEM21__M 0x1FFF +#define IQM_AF_CMP_MEM21__PRE 0x0 + +#define IQM_AF_CMP_MEM21_COEF__B 0 +#define IQM_AF_CMP_MEM21_COEF__W 13 +#define IQM_AF_CMP_MEM21_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM21_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM22__A 0x1870096 +#define IQM_AF_CMP_MEM22__W 13 +#define IQM_AF_CMP_MEM22__M 0x1FFF +#define IQM_AF_CMP_MEM22__PRE 0x0 + +#define IQM_AF_CMP_MEM22_COEF__B 0 +#define IQM_AF_CMP_MEM22_COEF__W 13 +#define IQM_AF_CMP_MEM22_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM22_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM23__A 0x1870097 +#define IQM_AF_CMP_MEM23__W 13 +#define IQM_AF_CMP_MEM23__M 0x1FFF +#define IQM_AF_CMP_MEM23__PRE 0x0 + +#define IQM_AF_CMP_MEM23_COEF__B 0 +#define IQM_AF_CMP_MEM23_COEF__W 13 +#define IQM_AF_CMP_MEM23_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM23_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM24__A 0x1870098 +#define IQM_AF_CMP_MEM24__W 13 +#define IQM_AF_CMP_MEM24__M 0x1FFF +#define IQM_AF_CMP_MEM24__PRE 0x0 + +#define IQM_AF_CMP_MEM24_COEF__B 0 +#define IQM_AF_CMP_MEM24_COEF__W 13 +#define IQM_AF_CMP_MEM24_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM24_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM25__A 0x1870099 +#define IQM_AF_CMP_MEM25__W 13 +#define IQM_AF_CMP_MEM25__M 0x1FFF +#define IQM_AF_CMP_MEM25__PRE 0x0 + +#define IQM_AF_CMP_MEM25_COEF__B 0 +#define IQM_AF_CMP_MEM25_COEF__W 13 +#define IQM_AF_CMP_MEM25_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM25_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM26__A 0x187009A +#define IQM_AF_CMP_MEM26__W 13 +#define IQM_AF_CMP_MEM26__M 0x1FFF +#define IQM_AF_CMP_MEM26__PRE 0x0 + +#define IQM_AF_CMP_MEM26_COEF__B 0 +#define IQM_AF_CMP_MEM26_COEF__W 13 +#define IQM_AF_CMP_MEM26_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM26_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM27__A 0x187009B +#define IQM_AF_CMP_MEM27__W 13 +#define IQM_AF_CMP_MEM27__M 0x1FFF +#define IQM_AF_CMP_MEM27__PRE 0x0 + +#define IQM_AF_CMP_MEM27_COEF__B 0 +#define IQM_AF_CMP_MEM27_COEF__W 13 +#define IQM_AF_CMP_MEM27_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM27_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM28__A 0x187009C +#define IQM_AF_CMP_MEM28__W 13 +#define IQM_AF_CMP_MEM28__M 0x1FFF +#define IQM_AF_CMP_MEM28__PRE 0x0 + +#define IQM_AF_CMP_MEM28_COEF__B 0 +#define IQM_AF_CMP_MEM28_COEF__W 13 +#define IQM_AF_CMP_MEM28_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM28_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM29__A 0x187009D +#define IQM_AF_CMP_MEM29__W 13 +#define IQM_AF_CMP_MEM29__M 0x1FFF +#define IQM_AF_CMP_MEM29__PRE 0x0 + +#define IQM_AF_CMP_MEM29_COEF__B 0 +#define IQM_AF_CMP_MEM29_COEF__W 13 +#define IQM_AF_CMP_MEM29_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM29_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM30__A 0x187009E +#define IQM_AF_CMP_MEM30__W 13 +#define IQM_AF_CMP_MEM30__M 0x1FFF +#define IQM_AF_CMP_MEM30__PRE 0x0 + +#define IQM_AF_CMP_MEM30_COEF__B 0 +#define IQM_AF_CMP_MEM30_COEF__W 13 +#define IQM_AF_CMP_MEM30_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM30_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM31__A 0x187009F +#define IQM_AF_CMP_MEM31__W 13 +#define IQM_AF_CMP_MEM31__M 0x1FFF +#define IQM_AF_CMP_MEM31__PRE 0x0 + +#define IQM_AF_CMP_MEM31_COEF__B 0 +#define IQM_AF_CMP_MEM31_COEF__W 13 +#define IQM_AF_CMP_MEM31_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM31_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM32__A 0x18700A0 +#define IQM_AF_CMP_MEM32__W 13 +#define IQM_AF_CMP_MEM32__M 0x1FFF +#define IQM_AF_CMP_MEM32__PRE 0x0 + +#define IQM_AF_CMP_MEM32_COEF__B 0 +#define IQM_AF_CMP_MEM32_COEF__W 13 +#define IQM_AF_CMP_MEM32_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM32_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM33__A 0x18700A1 +#define IQM_AF_CMP_MEM33__W 13 +#define IQM_AF_CMP_MEM33__M 0x1FFF +#define IQM_AF_CMP_MEM33__PRE 0x0 + +#define IQM_AF_CMP_MEM33_COEF__B 0 +#define IQM_AF_CMP_MEM33_COEF__W 13 +#define IQM_AF_CMP_MEM33_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM33_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM34__A 0x18700A2 +#define IQM_AF_CMP_MEM34__W 13 +#define IQM_AF_CMP_MEM34__M 0x1FFF +#define IQM_AF_CMP_MEM34__PRE 0x0 + +#define IQM_AF_CMP_MEM34_COEF__B 0 +#define IQM_AF_CMP_MEM34_COEF__W 13 +#define IQM_AF_CMP_MEM34_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM34_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM35__A 0x18700A3 +#define IQM_AF_CMP_MEM35__W 13 +#define IQM_AF_CMP_MEM35__M 0x1FFF +#define IQM_AF_CMP_MEM35__PRE 0x0 + +#define IQM_AF_CMP_MEM35_COEF__B 0 +#define IQM_AF_CMP_MEM35_COEF__W 13 +#define IQM_AF_CMP_MEM35_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM35_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM36__A 0x18700A4 +#define IQM_AF_CMP_MEM36__W 13 +#define IQM_AF_CMP_MEM36__M 0x1FFF +#define IQM_AF_CMP_MEM36__PRE 0x0 + +#define IQM_AF_CMP_MEM36_COEF__B 0 +#define IQM_AF_CMP_MEM36_COEF__W 13 +#define IQM_AF_CMP_MEM36_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM36_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM37__A 0x18700A5 +#define IQM_AF_CMP_MEM37__W 13 +#define IQM_AF_CMP_MEM37__M 0x1FFF +#define IQM_AF_CMP_MEM37__PRE 0x0 + +#define IQM_AF_CMP_MEM37_COEF__B 0 +#define IQM_AF_CMP_MEM37_COEF__W 13 +#define IQM_AF_CMP_MEM37_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM37_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM38__A 0x18700A6 +#define IQM_AF_CMP_MEM38__W 13 +#define IQM_AF_CMP_MEM38__M 0x1FFF +#define IQM_AF_CMP_MEM38__PRE 0x0 + +#define IQM_AF_CMP_MEM38_COEF__B 0 +#define IQM_AF_CMP_MEM38_COEF__W 13 +#define IQM_AF_CMP_MEM38_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM38_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM39__A 0x18700A7 +#define IQM_AF_CMP_MEM39__W 13 +#define IQM_AF_CMP_MEM39__M 0x1FFF +#define IQM_AF_CMP_MEM39__PRE 0x0 + +#define IQM_AF_CMP_MEM39_COEF__B 0 +#define IQM_AF_CMP_MEM39_COEF__W 13 +#define IQM_AF_CMP_MEM39_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM39_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM40__A 0x18700A8 +#define IQM_AF_CMP_MEM40__W 13 +#define IQM_AF_CMP_MEM40__M 0x1FFF +#define IQM_AF_CMP_MEM40__PRE 0x0 + +#define IQM_AF_CMP_MEM40_COEF__B 0 +#define IQM_AF_CMP_MEM40_COEF__W 13 +#define IQM_AF_CMP_MEM40_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM40_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM41__A 0x18700A9 +#define IQM_AF_CMP_MEM41__W 13 +#define IQM_AF_CMP_MEM41__M 0x1FFF +#define IQM_AF_CMP_MEM41__PRE 0x0 + +#define IQM_AF_CMP_MEM41_COEF__B 0 +#define IQM_AF_CMP_MEM41_COEF__W 13 +#define IQM_AF_CMP_MEM41_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM41_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM42__A 0x18700AA +#define IQM_AF_CMP_MEM42__W 13 +#define IQM_AF_CMP_MEM42__M 0x1FFF +#define IQM_AF_CMP_MEM42__PRE 0x0 + +#define IQM_AF_CMP_MEM42_COEF__B 0 +#define IQM_AF_CMP_MEM42_COEF__W 13 +#define IQM_AF_CMP_MEM42_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM42_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM43__A 0x18700AB +#define IQM_AF_CMP_MEM43__W 13 +#define IQM_AF_CMP_MEM43__M 0x1FFF +#define IQM_AF_CMP_MEM43__PRE 0x0 + +#define IQM_AF_CMP_MEM43_COEF__B 0 +#define IQM_AF_CMP_MEM43_COEF__W 13 +#define IQM_AF_CMP_MEM43_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM43_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM44__A 0x18700AC +#define IQM_AF_CMP_MEM44__W 13 +#define IQM_AF_CMP_MEM44__M 0x1FFF +#define IQM_AF_CMP_MEM44__PRE 0x0 + +#define IQM_AF_CMP_MEM44_COEF__B 0 +#define IQM_AF_CMP_MEM44_COEF__W 13 +#define IQM_AF_CMP_MEM44_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM44_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM45__A 0x18700AD +#define IQM_AF_CMP_MEM45__W 13 +#define IQM_AF_CMP_MEM45__M 0x1FFF +#define IQM_AF_CMP_MEM45__PRE 0x0 + +#define IQM_AF_CMP_MEM45_COEF__B 0 +#define IQM_AF_CMP_MEM45_COEF__W 13 +#define IQM_AF_CMP_MEM45_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM45_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM46__A 0x18700AE +#define IQM_AF_CMP_MEM46__W 13 +#define IQM_AF_CMP_MEM46__M 0x1FFF +#define IQM_AF_CMP_MEM46__PRE 0x0 + +#define IQM_AF_CMP_MEM46_COEF__B 0 +#define IQM_AF_CMP_MEM46_COEF__W 13 +#define IQM_AF_CMP_MEM46_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM46_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM47__A 0x18700AF +#define IQM_AF_CMP_MEM47__W 13 +#define IQM_AF_CMP_MEM47__M 0x1FFF +#define IQM_AF_CMP_MEM47__PRE 0x0 + +#define IQM_AF_CMP_MEM47_COEF__B 0 +#define IQM_AF_CMP_MEM47_COEF__W 13 +#define IQM_AF_CMP_MEM47_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM47_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM48__A 0x18700B0 +#define IQM_AF_CMP_MEM48__W 13 +#define IQM_AF_CMP_MEM48__M 0x1FFF +#define IQM_AF_CMP_MEM48__PRE 0x0 + +#define IQM_AF_CMP_MEM48_COEF__B 0 +#define IQM_AF_CMP_MEM48_COEF__W 13 +#define IQM_AF_CMP_MEM48_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM48_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM49__A 0x18700B1 +#define IQM_AF_CMP_MEM49__W 13 +#define IQM_AF_CMP_MEM49__M 0x1FFF +#define IQM_AF_CMP_MEM49__PRE 0x0 + +#define IQM_AF_CMP_MEM49_COEF__B 0 +#define IQM_AF_CMP_MEM49_COEF__W 13 +#define IQM_AF_CMP_MEM49_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM49_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM50__A 0x18700B2 +#define IQM_AF_CMP_MEM50__W 13 +#define IQM_AF_CMP_MEM50__M 0x1FFF +#define IQM_AF_CMP_MEM50__PRE 0x0 + +#define IQM_AF_CMP_MEM50_COEF__B 0 +#define IQM_AF_CMP_MEM50_COEF__W 13 +#define IQM_AF_CMP_MEM50_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM50_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM51__A 0x18700B3 +#define IQM_AF_CMP_MEM51__W 13 +#define IQM_AF_CMP_MEM51__M 0x1FFF +#define IQM_AF_CMP_MEM51__PRE 0x0 + +#define IQM_AF_CMP_MEM51_COEF__B 0 +#define IQM_AF_CMP_MEM51_COEF__W 13 +#define IQM_AF_CMP_MEM51_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM51_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM52__A 0x18700B4 +#define IQM_AF_CMP_MEM52__W 13 +#define IQM_AF_CMP_MEM52__M 0x1FFF +#define IQM_AF_CMP_MEM52__PRE 0x0 + +#define IQM_AF_CMP_MEM52_COEF__B 0 +#define IQM_AF_CMP_MEM52_COEF__W 13 +#define IQM_AF_CMP_MEM52_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM52_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM53__A 0x18700B5 +#define IQM_AF_CMP_MEM53__W 13 +#define IQM_AF_CMP_MEM53__M 0x1FFF +#define IQM_AF_CMP_MEM53__PRE 0x0 + +#define IQM_AF_CMP_MEM53_COEF__B 0 +#define IQM_AF_CMP_MEM53_COEF__W 13 +#define IQM_AF_CMP_MEM53_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM53_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM54__A 0x18700B6 +#define IQM_AF_CMP_MEM54__W 13 +#define IQM_AF_CMP_MEM54__M 0x1FFF +#define IQM_AF_CMP_MEM54__PRE 0x0 + +#define IQM_AF_CMP_MEM54_COEF__B 0 +#define IQM_AF_CMP_MEM54_COEF__W 13 +#define IQM_AF_CMP_MEM54_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM54_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM55__A 0x18700B7 +#define IQM_AF_CMP_MEM55__W 13 +#define IQM_AF_CMP_MEM55__M 0x1FFF +#define IQM_AF_CMP_MEM55__PRE 0x0 + +#define IQM_AF_CMP_MEM55_COEF__B 0 +#define IQM_AF_CMP_MEM55_COEF__W 13 +#define IQM_AF_CMP_MEM55_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM55_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM56__A 0x18700B8 +#define IQM_AF_CMP_MEM56__W 13 +#define IQM_AF_CMP_MEM56__M 0x1FFF +#define IQM_AF_CMP_MEM56__PRE 0x0 + +#define IQM_AF_CMP_MEM56_COEF__B 0 +#define IQM_AF_CMP_MEM56_COEF__W 13 +#define IQM_AF_CMP_MEM56_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM56_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM57__A 0x18700B9 +#define IQM_AF_CMP_MEM57__W 13 +#define IQM_AF_CMP_MEM57__M 0x1FFF +#define IQM_AF_CMP_MEM57__PRE 0x0 + +#define IQM_AF_CMP_MEM57_COEF__B 0 +#define IQM_AF_CMP_MEM57_COEF__W 13 +#define IQM_AF_CMP_MEM57_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM57_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM58__A 0x18700BA +#define IQM_AF_CMP_MEM58__W 13 +#define IQM_AF_CMP_MEM58__M 0x1FFF +#define IQM_AF_CMP_MEM58__PRE 0x0 + +#define IQM_AF_CMP_MEM58_COEF__B 0 +#define IQM_AF_CMP_MEM58_COEF__W 13 +#define IQM_AF_CMP_MEM58_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM58_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM59__A 0x18700BB +#define IQM_AF_CMP_MEM59__W 13 +#define IQM_AF_CMP_MEM59__M 0x1FFF +#define IQM_AF_CMP_MEM59__PRE 0x0 + +#define IQM_AF_CMP_MEM59_COEF__B 0 +#define IQM_AF_CMP_MEM59_COEF__W 13 +#define IQM_AF_CMP_MEM59_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM59_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM60__A 0x18700BC +#define IQM_AF_CMP_MEM60__W 13 +#define IQM_AF_CMP_MEM60__M 0x1FFF +#define IQM_AF_CMP_MEM60__PRE 0x0 + +#define IQM_AF_CMP_MEM60_COEF__B 0 +#define IQM_AF_CMP_MEM60_COEF__W 13 +#define IQM_AF_CMP_MEM60_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM60_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM61__A 0x18700BD +#define IQM_AF_CMP_MEM61__W 13 +#define IQM_AF_CMP_MEM61__M 0x1FFF +#define IQM_AF_CMP_MEM61__PRE 0x0 + +#define IQM_AF_CMP_MEM61_COEF__B 0 +#define IQM_AF_CMP_MEM61_COEF__W 13 +#define IQM_AF_CMP_MEM61_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM61_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM62__A 0x18700BE +#define IQM_AF_CMP_MEM62__W 13 +#define IQM_AF_CMP_MEM62__M 0x1FFF +#define IQM_AF_CMP_MEM62__PRE 0x0 + +#define IQM_AF_CMP_MEM62_COEF__B 0 +#define IQM_AF_CMP_MEM62_COEF__W 13 +#define IQM_AF_CMP_MEM62_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM62_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM63__A 0x18700BF +#define IQM_AF_CMP_MEM63__W 13 +#define IQM_AF_CMP_MEM63__M 0x1FFF +#define IQM_AF_CMP_MEM63__PRE 0x0 + +#define IQM_AF_CMP_MEM63_COEF__B 0 +#define IQM_AF_CMP_MEM63_COEF__W 13 +#define IQM_AF_CMP_MEM63_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM63_COEF__PRE 0x0 + + + +#define IQM_RT_RAM__A 0x1880000 + +#define IQM_RT_RAM_DLY__B 0 +#define IQM_RT_RAM_DLY__W 13 +#define IQM_RT_RAM_DLY__M 0x1FFF +#define IQM_RT_RAM_DLY__PRE 0x0 + + + + + +#define OFDM_CE_COMM_EXEC__A 0x2C00000 +#define OFDM_CE_COMM_EXEC__W 3 +#define OFDM_CE_COMM_EXEC__M 0x7 +#define OFDM_CE_COMM_EXEC__PRE 0x0 +#define OFDM_CE_COMM_EXEC_STOP 0x0 +#define OFDM_CE_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CE_COMM_EXEC_HOLD 0x2 +#define OFDM_CE_COMM_EXEC_STEP 0x3 +#define OFDM_CE_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_CE_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_CE_COMM_STATE__A 0x2C00001 +#define OFDM_CE_COMM_STATE__W 16 +#define OFDM_CE_COMM_STATE__M 0xFFFF +#define OFDM_CE_COMM_STATE__PRE 0x0 +#define OFDM_CE_COMM_MB__A 0x2C00002 +#define OFDM_CE_COMM_MB__W 16 +#define OFDM_CE_COMM_MB__M 0xFFFF +#define OFDM_CE_COMM_MB__PRE 0x0 +#define OFDM_CE_COMM_INT_REQ__A 0x2C00004 +#define OFDM_CE_COMM_INT_REQ__W 16 +#define OFDM_CE_COMM_INT_REQ__M 0xFFFF +#define OFDM_CE_COMM_INT_REQ__PRE 0x0 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__B 2 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__W 1 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__M 0x4 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__PRE 0x0 + +#define OFDM_CE_COMM_INT_STA__A 0x2C00005 +#define OFDM_CE_COMM_INT_STA__W 16 +#define OFDM_CE_COMM_INT_STA__M 0xFFFF +#define OFDM_CE_COMM_INT_STA__PRE 0x0 +#define OFDM_CE_COMM_INT_MSK__A 0x2C00006 +#define OFDM_CE_COMM_INT_MSK__W 16 +#define OFDM_CE_COMM_INT_MSK__M 0xFFFF +#define OFDM_CE_COMM_INT_MSK__PRE 0x0 +#define OFDM_CE_COMM_INT_STM__A 0x2C00007 +#define OFDM_CE_COMM_INT_STM__W 16 +#define OFDM_CE_COMM_INT_STM__M 0xFFFF +#define OFDM_CE_COMM_INT_STM__PRE 0x0 +#define OFDM_CE_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_CE_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_CE_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_CE_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_CE_TOP_COMM_EXEC__A 0x2C10000 +#define OFDM_CE_TOP_COMM_EXEC__W 3 +#define OFDM_CE_TOP_COMM_EXEC__M 0x7 +#define OFDM_CE_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_CE_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_CE_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CE_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_CE_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_CE_TOP_COMM_MB__A 0x2C10002 +#define OFDM_CE_TOP_COMM_MB__W 4 +#define OFDM_CE_TOP_COMM_MB__M 0xF +#define OFDM_CE_TOP_COMM_MB__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_CTL__B 0 +#define OFDM_CE_TOP_COMM_MB_CTL__W 1 +#define OFDM_CE_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_CE_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_CE_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_CE_TOP_COMM_MB_OBS__B 1 +#define OFDM_CE_TOP_COMM_MB_OBS__W 1 +#define OFDM_CE_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_CE_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_ON 0x2 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__B 2 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__W 2 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__M 0xC +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FI 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TP 0x4 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TI 0x8 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FR 0xC + +#define OFDM_CE_TOP_COMM_INT_REQ__A 0x2C10004 +#define OFDM_CE_TOP_COMM_INT_REQ__W 1 +#define OFDM_CE_TOP_COMM_INT_REQ__M 0x1 +#define OFDM_CE_TOP_COMM_INT_REQ__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA__A 0x2C10005 +#define OFDM_CE_TOP_COMM_INT_STA__W 3 +#define OFDM_CE_TOP_COMM_INT_STA__M 0x7 +#define OFDM_CE_TOP_COMM_INT_STA__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__B 0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__W 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__M 0x1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__B 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__W 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__M 0x2 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__B 2 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__W 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__M 0x4 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__PRE 0x0 + +#define OFDM_CE_TOP_COMM_INT_MSK__A 0x2C10006 +#define OFDM_CE_TOP_COMM_INT_MSK__W 3 +#define OFDM_CE_TOP_COMM_INT_MSK__M 0x7 +#define OFDM_CE_TOP_COMM_INT_MSK__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__B 0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__W 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__M 0x1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__B 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__W 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__M 0x2 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__B 2 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__W 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__M 0x4 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__PRE 0x0 + +#define OFDM_CE_TOP_COMM_INT_STM__A 0x2C10007 +#define OFDM_CE_TOP_COMM_INT_STM__W 3 +#define OFDM_CE_TOP_COMM_INT_STM__M 0x7 +#define OFDM_CE_TOP_COMM_INT_STM__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__B 0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__W 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__M 0x1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__B 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__W 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__M 0x2 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__B 2 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__W 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__M 0x4 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__PRE 0x0 + + +#define OFDM_CE_TOP_MODE_2K__A 0x2C10010 +#define OFDM_CE_TOP_MODE_2K__W 1 +#define OFDM_CE_TOP_MODE_2K__M 0x1 +#define OFDM_CE_TOP_MODE_2K__PRE 0x0 + +#define OFDM_CE_TOP_TAPSET__A 0x2C10011 +#define OFDM_CE_TOP_TAPSET__W 4 +#define OFDM_CE_TOP_TAPSET__M 0xF +#define OFDM_CE_TOP_TAPSET__PRE 0x1 +#define OFDM_CE_TOP_AVG_POW__A 0x2C10012 +#define OFDM_CE_TOP_AVG_POW__W 8 +#define OFDM_CE_TOP_AVG_POW__M 0xFF +#define OFDM_CE_TOP_AVG_POW__PRE 0x65 +#define OFDM_CE_TOP_MAX_POW__A 0x2C10013 +#define OFDM_CE_TOP_MAX_POW__W 8 +#define OFDM_CE_TOP_MAX_POW__M 0xFF +#define OFDM_CE_TOP_MAX_POW__PRE 0x80 +#define OFDM_CE_TOP_ATT__A 0x2C10014 +#define OFDM_CE_TOP_ATT__W 8 +#define OFDM_CE_TOP_ATT__M 0xFF +#define OFDM_CE_TOP_ATT__PRE 0x70 +#define OFDM_CE_TOP_NRED__A 0x2C10015 +#define OFDM_CE_TOP_NRED__W 6 +#define OFDM_CE_TOP_NRED__M 0x3F +#define OFDM_CE_TOP_NRED__PRE 0x9 + +#define OFDM_CE_TOP_PU_SIGN__A 0x2C10020 +#define OFDM_CE_TOP_PU_SIGN__W 1 +#define OFDM_CE_TOP_PU_SIGN__M 0x1 +#define OFDM_CE_TOP_PU_SIGN__PRE 0x0 + +#define OFDM_CE_TOP_PU_MIX__A 0x2C10021 +#define OFDM_CE_TOP_PU_MIX__W 1 +#define OFDM_CE_TOP_PU_MIX__M 0x1 +#define OFDM_CE_TOP_PU_MIX__PRE 0x0 +#define OFDM_CE_TOP_PB_PILOT_REQ__A 0x2C10030 +#define OFDM_CE_TOP_PB_PILOT_REQ__W 15 +#define OFDM_CE_TOP_PB_PILOT_REQ__M 0x7FFF +#define OFDM_CE_TOP_PB_PILOT_REQ__PRE 0x0 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__B 12 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__W 3 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__PRE 0x0 +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__B 0 +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__W 12 +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__M 0xFFF +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__PRE 0x0 + + +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__A 0x2C10031 +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__W 1 +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__M 0x1 +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__PRE 0x0 + +#define OFDM_CE_TOP_PB_FREEZE__A 0x2C10032 +#define OFDM_CE_TOP_PB_FREEZE__W 1 +#define OFDM_CE_TOP_PB_FREEZE__M 0x1 +#define OFDM_CE_TOP_PB_FREEZE__PRE 0x0 + +#define OFDM_CE_TOP_PB_PILOT_EXP__A 0x2C10038 +#define OFDM_CE_TOP_PB_PILOT_EXP__W 4 +#define OFDM_CE_TOP_PB_PILOT_EXP__M 0xF +#define OFDM_CE_TOP_PB_PILOT_EXP__PRE 0x0 + +#define OFDM_CE_TOP_PB_PILOT_REAL__A 0x2C10039 +#define OFDM_CE_TOP_PB_PILOT_REAL__W 10 +#define OFDM_CE_TOP_PB_PILOT_REAL__M 0x3FF +#define OFDM_CE_TOP_PB_PILOT_REAL__PRE 0x0 + +#define OFDM_CE_TOP_PB_PILOT_IMAG__A 0x2C1003A +#define OFDM_CE_TOP_PB_PILOT_IMAG__W 10 +#define OFDM_CE_TOP_PB_PILOT_IMAG__M 0x3FF +#define OFDM_CE_TOP_PB_PILOT_IMAG__PRE 0x0 + +#define OFDM_CE_TOP_PB_SMBNR__A 0x2C1003B +#define OFDM_CE_TOP_PB_SMBNR__W 5 +#define OFDM_CE_TOP_PB_SMBNR__M 0x1F +#define OFDM_CE_TOP_PB_SMBNR__PRE 0x0 + +#define OFDM_CE_TOP_NE_PILOT_REQ__A 0x2C10040 +#define OFDM_CE_TOP_NE_PILOT_REQ__W 12 +#define OFDM_CE_TOP_NE_PILOT_REQ__M 0xFFF +#define OFDM_CE_TOP_NE_PILOT_REQ__PRE 0x0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__A 0x2C10041 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__W 2 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__M 0x3 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__PRE 0x0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__PRE 0x0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__B 0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__W 1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__PRE 0x0 + + +#define OFDM_CE_TOP_NE_PILOT_DATA__A 0x2C10042 +#define OFDM_CE_TOP_NE_PILOT_DATA__W 10 +#define OFDM_CE_TOP_NE_PILOT_DATA__M 0x3FF +#define OFDM_CE_TOP_NE_PILOT_DATA__PRE 0x0 +#define OFDM_CE_TOP_NE_ERR_SELECT__A 0x2C10043 +#define OFDM_CE_TOP_NE_ERR_SELECT__W 5 +#define OFDM_CE_TOP_NE_ERR_SELECT__M 0x1F +#define OFDM_CE_TOP_NE_ERR_SELECT__PRE 0x7 + +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__B 4 +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__M 0x10 +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__PRE 0x0 + +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__B 3 +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__M 0x8 +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__PRE 0x0 + +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__B 2 +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__M 0x4 +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__PRE 0x4 + +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__B 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__M 0x2 +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__PRE 0x2 + +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__B 0 +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__M 0x1 +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__PRE 0x1 + + +#define OFDM_CE_TOP_NE_TD_CAL__A 0x2C10044 +#define OFDM_CE_TOP_NE_TD_CAL__W 9 +#define OFDM_CE_TOP_NE_TD_CAL__M 0x1FF +#define OFDM_CE_TOP_NE_TD_CAL__PRE 0x1E8 + +#define OFDM_CE_TOP_NE_FD_CAL__A 0x2C10045 +#define OFDM_CE_TOP_NE_FD_CAL__W 9 +#define OFDM_CE_TOP_NE_FD_CAL__M 0x1FF +#define OFDM_CE_TOP_NE_FD_CAL__PRE 0x1D9 + +#define OFDM_CE_TOP_NE_MIXAVG__A 0x2C10046 +#define OFDM_CE_TOP_NE_MIXAVG__W 3 +#define OFDM_CE_TOP_NE_MIXAVG__M 0x7 +#define OFDM_CE_TOP_NE_MIXAVG__PRE 0x6 + +#define OFDM_CE_TOP_NE_NUPD_OFS__A 0x2C10047 +#define OFDM_CE_TOP_NE_NUPD_OFS__W 4 +#define OFDM_CE_TOP_NE_NUPD_OFS__M 0xF +#define OFDM_CE_TOP_NE_NUPD_OFS__PRE 0x4 +#define OFDM_CE_TOP_NE_TD_POW__A 0x2C10048 +#define OFDM_CE_TOP_NE_TD_POW__W 15 +#define OFDM_CE_TOP_NE_TD_POW__M 0x7FFF +#define OFDM_CE_TOP_NE_TD_POW__PRE 0x0 + +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__B 10 +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__W 5 +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__B 0 +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__W 10 +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_NE_FD_POW__A 0x2C10049 +#define OFDM_CE_TOP_NE_FD_POW__W 15 +#define OFDM_CE_TOP_NE_FD_POW__M 0x7FFF +#define OFDM_CE_TOP_NE_FD_POW__PRE 0x0 + +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__B 10 +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__W 5 +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__B 0 +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__W 10 +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__PRE 0x0 + + +#define OFDM_CE_TOP_NE_NEXP_AVG__A 0x2C1004A +#define OFDM_CE_TOP_NE_NEXP_AVG__W 8 +#define OFDM_CE_TOP_NE_NEXP_AVG__M 0xFF +#define OFDM_CE_TOP_NE_NEXP_AVG__PRE 0x0 + +#define OFDM_CE_TOP_NE_OFFSET__A 0x2C1004B +#define OFDM_CE_TOP_NE_OFFSET__W 9 +#define OFDM_CE_TOP_NE_OFFSET__M 0x1FF +#define OFDM_CE_TOP_NE_OFFSET__PRE 0x0 + +#define OFDM_CE_TOP_NE_NUPD_TRH__A 0x2C1004C +#define OFDM_CE_TOP_NE_NUPD_TRH__W 5 +#define OFDM_CE_TOP_NE_NUPD_TRH__M 0x1F +#define OFDM_CE_TOP_NE_NUPD_TRH__PRE 0x14 + +#define OFDM_CE_TOP_PE_NEXP_OFFS__A 0x2C10050 +#define OFDM_CE_TOP_PE_NEXP_OFFS__W 8 +#define OFDM_CE_TOP_PE_NEXP_OFFS__M 0xFF +#define OFDM_CE_TOP_PE_NEXP_OFFS__PRE 0x0 + +#define OFDM_CE_TOP_PE_TIMESHIFT__A 0x2C10051 +#define OFDM_CE_TOP_PE_TIMESHIFT__W 14 +#define OFDM_CE_TOP_PE_TIMESHIFT__M 0x3FFF +#define OFDM_CE_TOP_PE_TIMESHIFT__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_REAL_L__A 0x2C10052 +#define OFDM_CE_TOP_PE_DIF_REAL_L__W 16 +#define OFDM_CE_TOP_PE_DIF_REAL_L__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_REAL_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_IMAG_L__A 0x2C10053 +#define OFDM_CE_TOP_PE_DIF_IMAG_L__W 16 +#define OFDM_CE_TOP_PE_DIF_IMAG_L__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_IMAG_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_REAL_R__A 0x2C10054 +#define OFDM_CE_TOP_PE_DIF_REAL_R__W 16 +#define OFDM_CE_TOP_PE_DIF_REAL_R__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_REAL_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_IMAG_R__A 0x2C10055 +#define OFDM_CE_TOP_PE_DIF_IMAG_R__W 16 +#define OFDM_CE_TOP_PE_DIF_IMAG_R__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_IMAG_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_REAL_L__A 0x2C10056 +#define OFDM_CE_TOP_PE_ABS_REAL_L__W 16 +#define OFDM_CE_TOP_PE_ABS_REAL_L__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_REAL_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_IMAG_L__A 0x2C10057 +#define OFDM_CE_TOP_PE_ABS_IMAG_L__W 16 +#define OFDM_CE_TOP_PE_ABS_IMAG_L__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_IMAG_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_REAL_R__A 0x2C10058 +#define OFDM_CE_TOP_PE_ABS_REAL_R__W 16 +#define OFDM_CE_TOP_PE_ABS_REAL_R__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_REAL_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_IMAG_R__A 0x2C10059 +#define OFDM_CE_TOP_PE_ABS_IMAG_R__W 16 +#define OFDM_CE_TOP_PE_ABS_IMAG_R__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_IMAG_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_EXP_L__A 0x2C1005A +#define OFDM_CE_TOP_PE_ABS_EXP_L__W 5 +#define OFDM_CE_TOP_PE_ABS_EXP_L__M 0x1F +#define OFDM_CE_TOP_PE_ABS_EXP_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_EXP_R__A 0x2C1005B +#define OFDM_CE_TOP_PE_ABS_EXP_R__W 5 +#define OFDM_CE_TOP_PE_ABS_EXP_R__M 0x1F +#define OFDM_CE_TOP_PE_ABS_EXP_R__PRE 0x0 + +#define OFDM_CE_TOP_TP_UPDATE_MODE__A 0x2C10060 +#define OFDM_CE_TOP_TP_UPDATE_MODE__W 1 +#define OFDM_CE_TOP_TP_UPDATE_MODE__M 0x1 +#define OFDM_CE_TOP_TP_UPDATE_MODE__PRE 0x0 + +#define OFDM_CE_TOP_TP_LMS_TAP_ON__A 0x2C10061 +#define OFDM_CE_TOP_TP_LMS_TAP_ON__W 1 +#define OFDM_CE_TOP_TP_LMS_TAP_ON__M 0x1 +#define OFDM_CE_TOP_TP_LMS_TAP_ON__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_NEW__A 0x2C10064 +#define OFDM_CE_TOP_TP_A0_TAP_NEW__W 10 +#define OFDM_CE_TOP_TP_A0_TAP_NEW__M 0x3FF +#define OFDM_CE_TOP_TP_A0_TAP_NEW__PRE 0x100 + +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__A 0x2C10065 +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__W 1 +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__M 0x1 +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__A 0x2C10066 +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__W 5 +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__M 0x1F +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__PRE 0xE + +#define OFDM_CE_TOP_TP_A0_TAP_CURR__A 0x2C10067 +#define OFDM_CE_TOP_TP_A0_TAP_CURR__W 10 +#define OFDM_CE_TOP_TP_A0_TAP_CURR__M 0x3FF +#define OFDM_CE_TOP_TP_A0_TAP_CURR__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_NEW__A 0x2C10068 +#define OFDM_CE_TOP_TP_A1_TAP_NEW__W 10 +#define OFDM_CE_TOP_TP_A1_TAP_NEW__M 0x3FF +#define OFDM_CE_TOP_TP_A1_TAP_NEW__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__A 0x2C10069 +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__W 1 +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__M 0x1 +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__A 0x2C1006A +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__W 5 +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__M 0x1F +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__PRE 0xA + +#define OFDM_CE_TOP_TP_A1_TAP_CURR__A 0x2C1006B +#define OFDM_CE_TOP_TP_A1_TAP_CURR__W 10 +#define OFDM_CE_TOP_TP_A1_TAP_CURR__M 0x3FF +#define OFDM_CE_TOP_TP_A1_TAP_CURR__PRE 0x0 +#define OFDM_CE_TOP_TP_DOPP_ENERGY__A 0x2C1006C +#define OFDM_CE_TOP_TP_DOPP_ENERGY__W 15 +#define OFDM_CE_TOP_TP_DOPP_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_DOPP_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__A 0x2C1006D +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__W 15 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__A 0x2C1006E +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__W 15 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__A 0x2C1006F +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__W 15 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__PRE 0x0 + + +#define OFDM_CE_TOP_TI_SYM_CNT__A 0x2C10072 +#define OFDM_CE_TOP_TI_SYM_CNT__W 6 +#define OFDM_CE_TOP_TI_SYM_CNT__M 0x3F +#define OFDM_CE_TOP_TI_SYM_CNT__PRE 0x20 + +#define OFDM_CE_TOP_TI_PHN_ENABLE__A 0x2C10073 +#define OFDM_CE_TOP_TI_PHN_ENABLE__W 1 +#define OFDM_CE_TOP_TI_PHN_ENABLE__M 0x1 +#define OFDM_CE_TOP_TI_PHN_ENABLE__PRE 0x1 + +#define OFDM_CE_TOP_TI_SHIFT__A 0x2C10074 +#define OFDM_CE_TOP_TI_SHIFT__W 2 +#define OFDM_CE_TOP_TI_SHIFT__M 0x3 +#define OFDM_CE_TOP_TI_SHIFT__PRE 0x0 + +#define OFDM_CE_TOP_TI_SLOW__A 0x2C10075 +#define OFDM_CE_TOP_TI_SLOW__W 1 +#define OFDM_CE_TOP_TI_SLOW__M 0x1 +#define OFDM_CE_TOP_TI_SLOW__PRE 0x1 + +#define OFDM_CE_TOP_TI_MGAIN__A 0x2C10076 +#define OFDM_CE_TOP_TI_MGAIN__W 8 +#define OFDM_CE_TOP_TI_MGAIN__M 0xFF +#define OFDM_CE_TOP_TI_MGAIN__PRE 0x0 + +#define OFDM_CE_TOP_TI_ACCU1__A 0x2C10077 +#define OFDM_CE_TOP_TI_ACCU1__W 8 +#define OFDM_CE_TOP_TI_ACCU1__M 0xFF +#define OFDM_CE_TOP_TI_ACCU1__PRE 0x0 + +#define OFDM_CE_TOP_NI_PER_LEFT__A 0x2C100B0 +#define OFDM_CE_TOP_NI_PER_LEFT__W 5 +#define OFDM_CE_TOP_NI_PER_LEFT__M 0x1F +#define OFDM_CE_TOP_NI_PER_LEFT__PRE 0xE + +#define OFDM_CE_TOP_NI_PER_RIGHT__A 0x2C100B1 +#define OFDM_CE_TOP_NI_PER_RIGHT__W 5 +#define OFDM_CE_TOP_NI_PER_RIGHT__M 0x1F +#define OFDM_CE_TOP_NI_PER_RIGHT__PRE 0x7 + +#define OFDM_CE_TOP_NI_POS_LR__A 0x2C100B2 +#define OFDM_CE_TOP_NI_POS_LR__W 9 +#define OFDM_CE_TOP_NI_POS_LR__M 0x1FF +#define OFDM_CE_TOP_NI_POS_LR__PRE 0xA0 + +#define OFDM_CE_TOP_FI_SHT_INCR__A 0x2C10090 +#define OFDM_CE_TOP_FI_SHT_INCR__W 9 +#define OFDM_CE_TOP_FI_SHT_INCR__M 0x1FF +#define OFDM_CE_TOP_FI_SHT_INCR__PRE 0x1E + +#define OFDM_CE_TOP_FI_EXP_NORM__A 0x2C10091 +#define OFDM_CE_TOP_FI_EXP_NORM__W 4 +#define OFDM_CE_TOP_FI_EXP_NORM__M 0xF +#define OFDM_CE_TOP_FI_EXP_NORM__PRE 0xC + +#define OFDM_CE_TOP_FI_SUPR_VAL__A 0x2C10092 +#define OFDM_CE_TOP_FI_SUPR_VAL__W 1 +#define OFDM_CE_TOP_FI_SUPR_VAL__M 0x1 +#define OFDM_CE_TOP_FI_SUPR_VAL__PRE 0x0 + +#define OFDM_CE_TOP_IR_INPUTSEL__A 0x2C100A0 +#define OFDM_CE_TOP_IR_INPUTSEL__W 1 +#define OFDM_CE_TOP_IR_INPUTSEL__M 0x1 +#define OFDM_CE_TOP_IR_INPUTSEL__PRE 0x0 + +#define OFDM_CE_TOP_IR_STARTPOS__A 0x2C100A1 +#define OFDM_CE_TOP_IR_STARTPOS__W 8 +#define OFDM_CE_TOP_IR_STARTPOS__M 0xFF +#define OFDM_CE_TOP_IR_STARTPOS__PRE 0x0 + +#define OFDM_CE_TOP_IR_NEXP_THRES__A 0x2C100A2 +#define OFDM_CE_TOP_IR_NEXP_THRES__W 8 +#define OFDM_CE_TOP_IR_NEXP_THRES__M 0xFF +#define OFDM_CE_TOP_IR_NEXP_THRES__PRE 0xFF + +#define OFDM_CE_TOP_IR_LENGTH__A 0x2C100A3 +#define OFDM_CE_TOP_IR_LENGTH__W 4 +#define OFDM_CE_TOP_IR_LENGTH__M 0xF +#define OFDM_CE_TOP_IR_LENGTH__PRE 0x9 + +#define OFDM_CE_TOP_IR_FREQ__A 0x2C100A4 +#define OFDM_CE_TOP_IR_FREQ__W 11 +#define OFDM_CE_TOP_IR_FREQ__M 0x7FF +#define OFDM_CE_TOP_IR_FREQ__PRE 0x0 + +#define OFDM_CE_TOP_IR_FREQINC__A 0x2C100A5 +#define OFDM_CE_TOP_IR_FREQINC__W 11 +#define OFDM_CE_TOP_IR_FREQINC__M 0x7FF +#define OFDM_CE_TOP_IR_FREQINC__PRE 0x4 + +#define OFDM_CE_TOP_IR_KAISINC__A 0x2C100A6 +#define OFDM_CE_TOP_IR_KAISINC__W 15 +#define OFDM_CE_TOP_IR_KAISINC__M 0x7FFF +#define OFDM_CE_TOP_IR_KAISINC__PRE 0x100 + +#define OFDM_CE_TOP_IR_CTL__A 0x2C100A7 +#define OFDM_CE_TOP_IR_CTL__W 3 +#define OFDM_CE_TOP_IR_CTL__M 0x7 +#define OFDM_CE_TOP_IR_CTL__PRE 0x0 + +#define OFDM_CE_TOP_IR_REAL__A 0x2C100A8 +#define OFDM_CE_TOP_IR_REAL__W 16 +#define OFDM_CE_TOP_IR_REAL__M 0xFFFF +#define OFDM_CE_TOP_IR_REAL__PRE 0x0 + +#define OFDM_CE_TOP_IR_IMAG__A 0x2C100A9 +#define OFDM_CE_TOP_IR_IMAG__W 16 +#define OFDM_CE_TOP_IR_IMAG__M 0xFFFF +#define OFDM_CE_TOP_IR_IMAG__PRE 0x0 + +#define OFDM_CE_TOP_IR_INDEX__A 0x2C100AA +#define OFDM_CE_TOP_IR_INDEX__W 12 +#define OFDM_CE_TOP_IR_INDEX__M 0xFFF +#define OFDM_CE_TOP_IR_INDEX__PRE 0x0 + + + +#define OFDM_CE_FR_COMM_EXEC__A 0x2C20000 +#define OFDM_CE_FR_COMM_EXEC__W 3 +#define OFDM_CE_FR_COMM_EXEC__M 0x7 +#define OFDM_CE_FR_COMM_EXEC__PRE 0x0 +#define OFDM_CE_FR_COMM_EXEC_STOP 0x0 +#define OFDM_CE_FR_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CE_FR_COMM_EXEC_HOLD 0x2 +#define OFDM_CE_FR_COMM_EXEC_STEP 0x3 + + +#define OFDM_CE_FR_TREAL00__A 0x2C20010 +#define OFDM_CE_FR_TREAL00__W 11 +#define OFDM_CE_FR_TREAL00__M 0x7FF +#define OFDM_CE_FR_TREAL00__PRE 0x52 + +#define OFDM_CE_FR_TIMAG00__A 0x2C20011 +#define OFDM_CE_FR_TIMAG00__W 11 +#define OFDM_CE_FR_TIMAG00__M 0x7FF +#define OFDM_CE_FR_TIMAG00__PRE 0x0 + +#define OFDM_CE_FR_TREAL01__A 0x2C20012 +#define OFDM_CE_FR_TREAL01__W 11 +#define OFDM_CE_FR_TREAL01__M 0x7FF +#define OFDM_CE_FR_TREAL01__PRE 0x52 + +#define OFDM_CE_FR_TIMAG01__A 0x2C20013 +#define OFDM_CE_FR_TIMAG01__W 11 +#define OFDM_CE_FR_TIMAG01__M 0x7FF +#define OFDM_CE_FR_TIMAG01__PRE 0x0 + +#define OFDM_CE_FR_TREAL02__A 0x2C20014 +#define OFDM_CE_FR_TREAL02__W 11 +#define OFDM_CE_FR_TREAL02__M 0x7FF +#define OFDM_CE_FR_TREAL02__PRE 0x52 + +#define OFDM_CE_FR_TIMAG02__A 0x2C20015 +#define OFDM_CE_FR_TIMAG02__W 11 +#define OFDM_CE_FR_TIMAG02__M 0x7FF +#define OFDM_CE_FR_TIMAG02__PRE 0x0 + +#define OFDM_CE_FR_TREAL03__A 0x2C20016 +#define OFDM_CE_FR_TREAL03__W 11 +#define OFDM_CE_FR_TREAL03__M 0x7FF +#define OFDM_CE_FR_TREAL03__PRE 0x52 + +#define OFDM_CE_FR_TIMAG03__A 0x2C20017 +#define OFDM_CE_FR_TIMAG03__W 11 +#define OFDM_CE_FR_TIMAG03__M 0x7FF +#define OFDM_CE_FR_TIMAG03__PRE 0x0 + +#define OFDM_CE_FR_TREAL04__A 0x2C20018 +#define OFDM_CE_FR_TREAL04__W 11 +#define OFDM_CE_FR_TREAL04__M 0x7FF +#define OFDM_CE_FR_TREAL04__PRE 0x52 + +#define OFDM_CE_FR_TIMAG04__A 0x2C20019 +#define OFDM_CE_FR_TIMAG04__W 11 +#define OFDM_CE_FR_TIMAG04__M 0x7FF +#define OFDM_CE_FR_TIMAG04__PRE 0x0 + +#define OFDM_CE_FR_TREAL05__A 0x2C2001A +#define OFDM_CE_FR_TREAL05__W 11 +#define OFDM_CE_FR_TREAL05__M 0x7FF +#define OFDM_CE_FR_TREAL05__PRE 0x52 + +#define OFDM_CE_FR_TIMAG05__A 0x2C2001B +#define OFDM_CE_FR_TIMAG05__W 11 +#define OFDM_CE_FR_TIMAG05__M 0x7FF +#define OFDM_CE_FR_TIMAG05__PRE 0x0 + +#define OFDM_CE_FR_TREAL06__A 0x2C2001C +#define OFDM_CE_FR_TREAL06__W 11 +#define OFDM_CE_FR_TREAL06__M 0x7FF +#define OFDM_CE_FR_TREAL06__PRE 0x52 + +#define OFDM_CE_FR_TIMAG06__A 0x2C2001D +#define OFDM_CE_FR_TIMAG06__W 11 +#define OFDM_CE_FR_TIMAG06__M 0x7FF +#define OFDM_CE_FR_TIMAG06__PRE 0x0 + +#define OFDM_CE_FR_TREAL07__A 0x2C2001E +#define OFDM_CE_FR_TREAL07__W 11 +#define OFDM_CE_FR_TREAL07__M 0x7FF +#define OFDM_CE_FR_TREAL07__PRE 0x52 + +#define OFDM_CE_FR_TIMAG07__A 0x2C2001F +#define OFDM_CE_FR_TIMAG07__W 11 +#define OFDM_CE_FR_TIMAG07__M 0x7FF +#define OFDM_CE_FR_TIMAG07__PRE 0x0 + +#define OFDM_CE_FR_TREAL08__A 0x2C20020 +#define OFDM_CE_FR_TREAL08__W 11 +#define OFDM_CE_FR_TREAL08__M 0x7FF +#define OFDM_CE_FR_TREAL08__PRE 0x52 + +#define OFDM_CE_FR_TIMAG08__A 0x2C20021 +#define OFDM_CE_FR_TIMAG08__W 11 +#define OFDM_CE_FR_TIMAG08__M 0x7FF +#define OFDM_CE_FR_TIMAG08__PRE 0x0 + +#define OFDM_CE_FR_TREAL09__A 0x2C20022 +#define OFDM_CE_FR_TREAL09__W 11 +#define OFDM_CE_FR_TREAL09__M 0x7FF +#define OFDM_CE_FR_TREAL09__PRE 0x52 + +#define OFDM_CE_FR_TIMAG09__A 0x2C20023 +#define OFDM_CE_FR_TIMAG09__W 11 +#define OFDM_CE_FR_TIMAG09__M 0x7FF +#define OFDM_CE_FR_TIMAG09__PRE 0x0 + +#define OFDM_CE_FR_TREAL10__A 0x2C20024 +#define OFDM_CE_FR_TREAL10__W 11 +#define OFDM_CE_FR_TREAL10__M 0x7FF +#define OFDM_CE_FR_TREAL10__PRE 0x52 + +#define OFDM_CE_FR_TIMAG10__A 0x2C20025 +#define OFDM_CE_FR_TIMAG10__W 11 +#define OFDM_CE_FR_TIMAG10__M 0x7FF +#define OFDM_CE_FR_TIMAG10__PRE 0x0 + +#define OFDM_CE_FR_TREAL11__A 0x2C20026 +#define OFDM_CE_FR_TREAL11__W 11 +#define OFDM_CE_FR_TREAL11__M 0x7FF +#define OFDM_CE_FR_TREAL11__PRE 0x52 + +#define OFDM_CE_FR_TIMAG11__A 0x2C20027 +#define OFDM_CE_FR_TIMAG11__W 11 +#define OFDM_CE_FR_TIMAG11__M 0x7FF +#define OFDM_CE_FR_TIMAG11__PRE 0x0 + +#define OFDM_CE_FR_MID_TAP__A 0x2C20028 +#define OFDM_CE_FR_MID_TAP__W 11 +#define OFDM_CE_FR_MID_TAP__M 0x7FF +#define OFDM_CE_FR_MID_TAP__PRE 0x51 + +#define OFDM_CE_FR_SQS_G00__A 0x2C20029 +#define OFDM_CE_FR_SQS_G00__W 8 +#define OFDM_CE_FR_SQS_G00__M 0xFF +#define OFDM_CE_FR_SQS_G00__PRE 0xB + +#define OFDM_CE_FR_SQS_G01__A 0x2C2002A +#define OFDM_CE_FR_SQS_G01__W 8 +#define OFDM_CE_FR_SQS_G01__M 0xFF +#define OFDM_CE_FR_SQS_G01__PRE 0xB + +#define OFDM_CE_FR_SQS_G02__A 0x2C2002B +#define OFDM_CE_FR_SQS_G02__W 8 +#define OFDM_CE_FR_SQS_G02__M 0xFF +#define OFDM_CE_FR_SQS_G02__PRE 0xB + +#define OFDM_CE_FR_SQS_G03__A 0x2C2002C +#define OFDM_CE_FR_SQS_G03__W 8 +#define OFDM_CE_FR_SQS_G03__M 0xFF +#define OFDM_CE_FR_SQS_G03__PRE 0xB + +#define OFDM_CE_FR_SQS_G04__A 0x2C2002D +#define OFDM_CE_FR_SQS_G04__W 8 +#define OFDM_CE_FR_SQS_G04__M 0xFF +#define OFDM_CE_FR_SQS_G04__PRE 0xB + +#define OFDM_CE_FR_SQS_G05__A 0x2C2002E +#define OFDM_CE_FR_SQS_G05__W 8 +#define OFDM_CE_FR_SQS_G05__M 0xFF +#define OFDM_CE_FR_SQS_G05__PRE 0xB + +#define OFDM_CE_FR_SQS_G06__A 0x2C2002F +#define OFDM_CE_FR_SQS_G06__W 8 +#define OFDM_CE_FR_SQS_G06__M 0xFF +#define OFDM_CE_FR_SQS_G06__PRE 0xB + +#define OFDM_CE_FR_SQS_G07__A 0x2C20030 +#define OFDM_CE_FR_SQS_G07__W 8 +#define OFDM_CE_FR_SQS_G07__M 0xFF +#define OFDM_CE_FR_SQS_G07__PRE 0xB + +#define OFDM_CE_FR_SQS_G08__A 0x2C20031 +#define OFDM_CE_FR_SQS_G08__W 8 +#define OFDM_CE_FR_SQS_G08__M 0xFF +#define OFDM_CE_FR_SQS_G08__PRE 0xB + +#define OFDM_CE_FR_SQS_G09__A 0x2C20032 +#define OFDM_CE_FR_SQS_G09__W 8 +#define OFDM_CE_FR_SQS_G09__M 0xFF +#define OFDM_CE_FR_SQS_G09__PRE 0xB + +#define OFDM_CE_FR_SQS_G10__A 0x2C20033 +#define OFDM_CE_FR_SQS_G10__W 8 +#define OFDM_CE_FR_SQS_G10__M 0xFF +#define OFDM_CE_FR_SQS_G10__PRE 0xB + +#define OFDM_CE_FR_SQS_G11__A 0x2C20034 +#define OFDM_CE_FR_SQS_G11__W 8 +#define OFDM_CE_FR_SQS_G11__M 0xFF +#define OFDM_CE_FR_SQS_G11__PRE 0xB + +#define OFDM_CE_FR_SQS_G12__A 0x2C20035 +#define OFDM_CE_FR_SQS_G12__W 8 +#define OFDM_CE_FR_SQS_G12__M 0xFF +#define OFDM_CE_FR_SQS_G12__PRE 0x5 + +#define OFDM_CE_FR_RIO_G00__A 0x2C20036 +#define OFDM_CE_FR_RIO_G00__W 9 +#define OFDM_CE_FR_RIO_G00__M 0x1FF +#define OFDM_CE_FR_RIO_G00__PRE 0x1FF + +#define OFDM_CE_FR_RIO_G01__A 0x2C20037 +#define OFDM_CE_FR_RIO_G01__W 9 +#define OFDM_CE_FR_RIO_G01__M 0x1FF +#define OFDM_CE_FR_RIO_G01__PRE 0x190 + +#define OFDM_CE_FR_RIO_G02__A 0x2C20038 +#define OFDM_CE_FR_RIO_G02__W 9 +#define OFDM_CE_FR_RIO_G02__M 0x1FF +#define OFDM_CE_FR_RIO_G02__PRE 0x10B + +#define OFDM_CE_FR_RIO_G03__A 0x2C20039 +#define OFDM_CE_FR_RIO_G03__W 9 +#define OFDM_CE_FR_RIO_G03__M 0x1FF +#define OFDM_CE_FR_RIO_G03__PRE 0xC8 + +#define OFDM_CE_FR_RIO_G04__A 0x2C2003A +#define OFDM_CE_FR_RIO_G04__W 9 +#define OFDM_CE_FR_RIO_G04__M 0x1FF +#define OFDM_CE_FR_RIO_G04__PRE 0xA0 + +#define OFDM_CE_FR_RIO_G05__A 0x2C2003B +#define OFDM_CE_FR_RIO_G05__W 9 +#define OFDM_CE_FR_RIO_G05__M 0x1FF +#define OFDM_CE_FR_RIO_G05__PRE 0x85 + +#define OFDM_CE_FR_RIO_G06__A 0x2C2003C +#define OFDM_CE_FR_RIO_G06__W 9 +#define OFDM_CE_FR_RIO_G06__M 0x1FF +#define OFDM_CE_FR_RIO_G06__PRE 0x72 + +#define OFDM_CE_FR_RIO_G07__A 0x2C2003D +#define OFDM_CE_FR_RIO_G07__W 9 +#define OFDM_CE_FR_RIO_G07__M 0x1FF +#define OFDM_CE_FR_RIO_G07__PRE 0x64 + +#define OFDM_CE_FR_RIO_G08__A 0x2C2003E +#define OFDM_CE_FR_RIO_G08__W 9 +#define OFDM_CE_FR_RIO_G08__M 0x1FF +#define OFDM_CE_FR_RIO_G08__PRE 0x59 + +#define OFDM_CE_FR_RIO_G09__A 0x2C2003F +#define OFDM_CE_FR_RIO_G09__W 9 +#define OFDM_CE_FR_RIO_G09__M 0x1FF +#define OFDM_CE_FR_RIO_G09__PRE 0x50 + +#define OFDM_CE_FR_RIO_G10__A 0x2C20040 +#define OFDM_CE_FR_RIO_G10__W 9 +#define OFDM_CE_FR_RIO_G10__M 0x1FF +#define OFDM_CE_FR_RIO_G10__PRE 0x49 +#define OFDM_CE_FR_MODE__A 0x2C20041 +#define OFDM_CE_FR_MODE__W 9 +#define OFDM_CE_FR_MODE__M 0x1FF +#define OFDM_CE_FR_MODE__PRE 0xDE + +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__B 0 +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__W 1 +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__M 0x1 +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__PRE 0x0 + +#define OFDM_CE_FR_MODE_ERROR_SHIFT__B 1 +#define OFDM_CE_FR_MODE_ERROR_SHIFT__W 1 +#define OFDM_CE_FR_MODE_ERROR_SHIFT__M 0x2 +#define OFDM_CE_FR_MODE_ERROR_SHIFT__PRE 0x2 + +#define OFDM_CE_FR_MODE_NEXP_UPDATE__B 2 +#define OFDM_CE_FR_MODE_NEXP_UPDATE__W 1 +#define OFDM_CE_FR_MODE_NEXP_UPDATE__M 0x4 +#define OFDM_CE_FR_MODE_NEXP_UPDATE__PRE 0x4 + +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__B 3 +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__W 1 +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__M 0x8 +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__PRE 0x8 + +#define OFDM_CE_FR_MODE_SQUASH_MODE__B 4 +#define OFDM_CE_FR_MODE_SQUASH_MODE__W 1 +#define OFDM_CE_FR_MODE_SQUASH_MODE__M 0x10 +#define OFDM_CE_FR_MODE_SQUASH_MODE__PRE 0x10 + +#define OFDM_CE_FR_MODE_UPDATE_MODE__B 5 +#define OFDM_CE_FR_MODE_UPDATE_MODE__W 1 +#define OFDM_CE_FR_MODE_UPDATE_MODE__M 0x20 +#define OFDM_CE_FR_MODE_UPDATE_MODE__PRE 0x0 + +#define OFDM_CE_FR_MODE_MID_MODE__B 6 +#define OFDM_CE_FR_MODE_MID_MODE__W 1 +#define OFDM_CE_FR_MODE_MID_MODE__M 0x40 +#define OFDM_CE_FR_MODE_MID_MODE__PRE 0x40 + +#define OFDM_CE_FR_MODE_NOISE_MODE__B 7 +#define OFDM_CE_FR_MODE_NOISE_MODE__W 1 +#define OFDM_CE_FR_MODE_NOISE_MODE__M 0x80 +#define OFDM_CE_FR_MODE_NOISE_MODE__PRE 0x80 + +#define OFDM_CE_FR_MODE_NOTCH_MODE__B 8 +#define OFDM_CE_FR_MODE_NOTCH_MODE__W 1 +#define OFDM_CE_FR_MODE_NOTCH_MODE__M 0x100 +#define OFDM_CE_FR_MODE_NOTCH_MODE__PRE 0x0 + + +#define OFDM_CE_FR_SQS_TRH__A 0x2C20042 +#define OFDM_CE_FR_SQS_TRH__W 8 +#define OFDM_CE_FR_SQS_TRH__M 0xFF +#define OFDM_CE_FR_SQS_TRH__PRE 0x80 + +#define OFDM_CE_FR_RIO_GAIN__A 0x2C20043 +#define OFDM_CE_FR_RIO_GAIN__W 3 +#define OFDM_CE_FR_RIO_GAIN__M 0x7 +#define OFDM_CE_FR_RIO_GAIN__PRE 0x7 +#define OFDM_CE_FR_BYPASS__A 0x2C20044 +#define OFDM_CE_FR_BYPASS__W 10 +#define OFDM_CE_FR_BYPASS__M 0x3FF +#define OFDM_CE_FR_BYPASS__PRE 0x13B + +#define OFDM_CE_FR_BYPASS_RUN_IN__B 0 +#define OFDM_CE_FR_BYPASS_RUN_IN__W 4 +#define OFDM_CE_FR_BYPASS_RUN_IN__M 0xF +#define OFDM_CE_FR_BYPASS_RUN_IN__PRE 0xB + +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__B 4 +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__W 5 +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__PRE 0x130 + +#define OFDM_CE_FR_BYPASS_TOTAL__B 9 +#define OFDM_CE_FR_BYPASS_TOTAL__W 1 +#define OFDM_CE_FR_BYPASS_TOTAL__M 0x200 +#define OFDM_CE_FR_BYPASS_TOTAL__PRE 0x0 + + +#define OFDM_CE_FR_PM_SET__A 0x2C20045 +#define OFDM_CE_FR_PM_SET__W 4 +#define OFDM_CE_FR_PM_SET__M 0xF +#define OFDM_CE_FR_PM_SET__PRE 0xD + +#define OFDM_CE_FR_ERR_SH__A 0x2C20046 +#define OFDM_CE_FR_ERR_SH__W 4 +#define OFDM_CE_FR_ERR_SH__M 0xF +#define OFDM_CE_FR_ERR_SH__PRE 0x4 + +#define OFDM_CE_FR_MAN_SH__A 0x2C20047 +#define OFDM_CE_FR_MAN_SH__W 4 +#define OFDM_CE_FR_MAN_SH__M 0xF +#define OFDM_CE_FR_MAN_SH__PRE 0x7 + +#define OFDM_CE_FR_TAP_SH__A 0x2C20048 +#define OFDM_CE_FR_TAP_SH__W 3 +#define OFDM_CE_FR_TAP_SH__M 0x7 +#define OFDM_CE_FR_TAP_SH__PRE 0x3 + +#define OFDM_CE_FR_CLIP__A 0x2C20049 +#define OFDM_CE_FR_CLIP__W 9 +#define OFDM_CE_FR_CLIP__M 0x1FF +#define OFDM_CE_FR_CLIP__PRE 0x49 + +#define OFDM_CE_FR_LEAK_UPD__A 0x2C2004A +#define OFDM_CE_FR_LEAK_UPD__W 3 +#define OFDM_CE_FR_LEAK_UPD__M 0x7 +#define OFDM_CE_FR_LEAK_UPD__PRE 0x0 + +#define OFDM_CE_FR_LEAK_SH__A 0x2C2004B +#define OFDM_CE_FR_LEAK_SH__W 3 +#define OFDM_CE_FR_LEAK_SH__M 0x7 +#define OFDM_CE_FR_LEAK_SH__PRE 0x1 + + + +#define OFDM_CE_NE_RAM__A 0x2C30000 + + + +#define OFDM_CE_PB_RAM__A 0x2C40000 + + + + + +#define OFDM_CP_COMM_EXEC__A 0x2800000 +#define OFDM_CP_COMM_EXEC__W 3 +#define OFDM_CP_COMM_EXEC__M 0x7 +#define OFDM_CP_COMM_EXEC__PRE 0x0 +#define OFDM_CP_COMM_EXEC_STOP 0x0 +#define OFDM_CP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CP_COMM_EXEC_HOLD 0x2 +#define OFDM_CP_COMM_EXEC_STEP 0x3 +#define OFDM_CP_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_CP_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_CP_COMM_STATE__A 0x2800001 +#define OFDM_CP_COMM_STATE__W 16 +#define OFDM_CP_COMM_STATE__M 0xFFFF +#define OFDM_CP_COMM_STATE__PRE 0x0 +#define OFDM_CP_COMM_MB__A 0x2800002 +#define OFDM_CP_COMM_MB__W 16 +#define OFDM_CP_COMM_MB__M 0xFFFF +#define OFDM_CP_COMM_MB__PRE 0x0 +#define OFDM_CP_COMM_INT_REQ__A 0x2800004 +#define OFDM_CP_COMM_INT_REQ__W 16 +#define OFDM_CP_COMM_INT_REQ__M 0xFFFF +#define OFDM_CP_COMM_INT_REQ__PRE 0x0 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__B 1 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__W 1 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__M 0x2 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__PRE 0x0 + +#define OFDM_CP_COMM_INT_STA__A 0x2800005 +#define OFDM_CP_COMM_INT_STA__W 16 +#define OFDM_CP_COMM_INT_STA__M 0xFFFF +#define OFDM_CP_COMM_INT_STA__PRE 0x0 +#define OFDM_CP_COMM_INT_MSK__A 0x2800006 +#define OFDM_CP_COMM_INT_MSK__W 16 +#define OFDM_CP_COMM_INT_MSK__M 0xFFFF +#define OFDM_CP_COMM_INT_MSK__PRE 0x0 +#define OFDM_CP_COMM_INT_STM__A 0x2800007 +#define OFDM_CP_COMM_INT_STM__W 16 +#define OFDM_CP_COMM_INT_STM__M 0xFFFF +#define OFDM_CP_COMM_INT_STM__PRE 0x0 +#define OFDM_CP_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_CP_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_CP_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_CP_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_CP_TOP_COMM_EXEC__A 0x2810000 +#define OFDM_CP_TOP_COMM_EXEC__W 3 +#define OFDM_CP_TOP_COMM_EXEC__M 0x7 +#define OFDM_CP_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_CP_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_CP_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CP_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_CP_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_CP_TOP_COMM_MB__A 0x2810002 +#define OFDM_CP_TOP_COMM_MB__W 3 +#define OFDM_CP_TOP_COMM_MB__M 0x7 +#define OFDM_CP_TOP_COMM_MB__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_CTL__B 0 +#define OFDM_CP_TOP_COMM_MB_CTL__W 1 +#define OFDM_CP_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_CP_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_CP_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_CP_TOP_COMM_MB_OBS__B 1 +#define OFDM_CP_TOP_COMM_MB_OBS__W 1 +#define OFDM_CP_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_CP_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_ON 0x2 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__B 2 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__W 1 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__M 0x4 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX_CE 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX_DL 0x4 + +#define OFDM_CP_TOP_COMM_INT_REQ__A 0x2810004 +#define OFDM_CP_TOP_COMM_INT_REQ__W 1 +#define OFDM_CP_TOP_COMM_INT_REQ__M 0x1 +#define OFDM_CP_TOP_COMM_INT_REQ__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_STA__A 0x2810005 +#define OFDM_CP_TOP_COMM_INT_STA__W 1 +#define OFDM_CP_TOP_COMM_INT_STA__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STA__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__B 0 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__W 1 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__PRE 0x0 + +#define OFDM_CP_TOP_COMM_INT_MSK__A 0x2810006 +#define OFDM_CP_TOP_COMM_INT_MSK__W 1 +#define OFDM_CP_TOP_COMM_INT_MSK__M 0x1 +#define OFDM_CP_TOP_COMM_INT_MSK__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__B 0 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__W 1 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__M 0x1 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__PRE 0x0 + +#define OFDM_CP_TOP_COMM_INT_STM__A 0x2810007 +#define OFDM_CP_TOP_COMM_INT_STM__W 1 +#define OFDM_CP_TOP_COMM_INT_STM__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STM__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__B 0 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__W 1 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__PRE 0x0 + + +#define OFDM_CP_TOP_MODE_2K__A 0x2810010 +#define OFDM_CP_TOP_MODE_2K__W 1 +#define OFDM_CP_TOP_MODE_2K__M 0x1 +#define OFDM_CP_TOP_MODE_2K__PRE 0x0 + +#define OFDM_CP_TOP_INTERVAL__A 0x2810011 +#define OFDM_CP_TOP_INTERVAL__W 4 +#define OFDM_CP_TOP_INTERVAL__M 0xF +#define OFDM_CP_TOP_INTERVAL__PRE 0x5 +#define OFDM_CP_TOP_DETECT_ENA__A 0x2810012 +#define OFDM_CP_TOP_DETECT_ENA__W 2 +#define OFDM_CP_TOP_DETECT_ENA__M 0x3 +#define OFDM_CP_TOP_DETECT_ENA__PRE 0x0 + +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__B 0 +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__W 1 +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__M 0x1 +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__PRE 0x0 + +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__B 1 +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__W 1 +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__M 0x2 +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__PRE 0x0 + +#define OFDM_CP_TOP_FIX__A 0x2810013 +#define OFDM_CP_TOP_FIX__W 4 +#define OFDM_CP_TOP_FIX__M 0xF +#define OFDM_CP_TOP_FIX__PRE 0xF + +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__B 0 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__M 0x1 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__PRE 0x1 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX_ENABLE 0x1 + +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__B 1 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__M 0x2 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__PRE 0x2 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD_ENABLE 0x2 + +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__B 2 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__M 0x4 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__PRE 0x4 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP_ENABLE 0x4 + +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__B 3 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__M 0x8 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__PRE 0x8 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH_ENABLE 0x8 + +#define OFDM_CP_TOP_BR_SMB_NR__A 0x2810021 +#define OFDM_CP_TOP_BR_SMB_NR__W 4 +#define OFDM_CP_TOP_BR_SMB_NR__M 0xF +#define OFDM_CP_TOP_BR_SMB_NR__PRE 0x0 + +#define OFDM_CP_TOP_BR_SMB_NR_SMB__B 0 +#define OFDM_CP_TOP_BR_SMB_NR_SMB__W 2 +#define OFDM_CP_TOP_BR_SMB_NR_SMB__M 0x3 +#define OFDM_CP_TOP_BR_SMB_NR_SMB__PRE 0x0 + +#define OFDM_CP_TOP_BR_SMB_NR_VAL__B 2 +#define OFDM_CP_TOP_BR_SMB_NR_VAL__W 1 +#define OFDM_CP_TOP_BR_SMB_NR_VAL__M 0x4 +#define OFDM_CP_TOP_BR_SMB_NR_VAL__PRE 0x0 + +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__B 3 +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__W 1 +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__M 0x8 +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__PRE 0x0 + + +#define OFDM_CP_TOP_BR_CP_SMB_NR__A 0x2810022 +#define OFDM_CP_TOP_BR_CP_SMB_NR__W 2 +#define OFDM_CP_TOP_BR_CP_SMB_NR__M 0x3 +#define OFDM_CP_TOP_BR_CP_SMB_NR__PRE 0x0 + +#define OFDM_CP_TOP_BR_SPL_OFFSET__A 0x2810023 +#define OFDM_CP_TOP_BR_SPL_OFFSET__W 4 +#define OFDM_CP_TOP_BR_SPL_OFFSET__M 0xF +#define OFDM_CP_TOP_BR_SPL_OFFSET__PRE 0x8 + +#define OFDM_CP_TOP_BR_STR_DEL__A 0x2810024 +#define OFDM_CP_TOP_BR_STR_DEL__W 10 +#define OFDM_CP_TOP_BR_STR_DEL__M 0x3FF +#define OFDM_CP_TOP_BR_STR_DEL__PRE 0xA + +#define OFDM_CP_TOP_BR_EXP_ADJ__A 0x2810025 +#define OFDM_CP_TOP_BR_EXP_ADJ__W 5 +#define OFDM_CP_TOP_BR_EXP_ADJ__M 0x1F +#define OFDM_CP_TOP_BR_EXP_ADJ__PRE 0x10 + +#define OFDM_CP_TOP_RT_ANG_INC0__A 0x2810030 +#define OFDM_CP_TOP_RT_ANG_INC0__W 16 +#define OFDM_CP_TOP_RT_ANG_INC0__M 0xFFFF +#define OFDM_CP_TOP_RT_ANG_INC0__PRE 0x0 + +#define OFDM_CP_TOP_RT_ANG_INC1__A 0x2810031 +#define OFDM_CP_TOP_RT_ANG_INC1__W 8 +#define OFDM_CP_TOP_RT_ANG_INC1__M 0xFF +#define OFDM_CP_TOP_RT_ANG_INC1__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__A 0x2810032 +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__W 5 +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__M 0x1F +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__PRE 0x5 + +#define OFDM_CP_TOP_RT_DETECT_TRH__A 0x2810033 +#define OFDM_CP_TOP_RT_DETECT_TRH__W 2 +#define OFDM_CP_TOP_RT_DETECT_TRH__M 0x3 +#define OFDM_CP_TOP_RT_DETECT_TRH__PRE 0x3 + +#define OFDM_CP_TOP_RT_SPD_RELIABLE__A 0x2810034 +#define OFDM_CP_TOP_RT_SPD_RELIABLE__W 3 +#define OFDM_CP_TOP_RT_SPD_RELIABLE__M 0x7 +#define OFDM_CP_TOP_RT_SPD_RELIABLE__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_DIRECTION__A 0x2810035 +#define OFDM_CP_TOP_RT_SPD_DIRECTION__W 1 +#define OFDM_CP_TOP_RT_SPD_DIRECTION__M 0x1 +#define OFDM_CP_TOP_RT_SPD_DIRECTION__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_MOD__A 0x2810036 +#define OFDM_CP_TOP_RT_SPD_MOD__W 2 +#define OFDM_CP_TOP_RT_SPD_MOD__M 0x3 +#define OFDM_CP_TOP_RT_SPD_MOD__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_SMB__A 0x2810037 +#define OFDM_CP_TOP_RT_SPD_SMB__W 2 +#define OFDM_CP_TOP_RT_SPD_SMB__M 0x3 +#define OFDM_CP_TOP_RT_SPD_SMB__PRE 0x0 +#define OFDM_CP_TOP_RT_CPD_MODE__A 0x2810038 +#define OFDM_CP_TOP_RT_CPD_MODE__W 3 +#define OFDM_CP_TOP_RT_CPD_MODE__M 0x7 +#define OFDM_CP_TOP_RT_CPD_MODE__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__B 0 +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__W 2 +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__M 0x3 +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__B 2 +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__W 1 +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__M 0x4 +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__PRE 0x0 + + +#define OFDM_CP_TOP_RT_CPD_RELIABLE__A 0x2810039 +#define OFDM_CP_TOP_RT_CPD_RELIABLE__W 3 +#define OFDM_CP_TOP_RT_CPD_RELIABLE__M 0x7 +#define OFDM_CP_TOP_RT_CPD_RELIABLE__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_BIN__A 0x281003A +#define OFDM_CP_TOP_RT_CPD_BIN__W 5 +#define OFDM_CP_TOP_RT_CPD_BIN__M 0x1F +#define OFDM_CP_TOP_RT_CPD_BIN__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_MAX__A 0x281003B +#define OFDM_CP_TOP_RT_CPD_MAX__W 4 +#define OFDM_CP_TOP_RT_CPD_MAX__M 0xF +#define OFDM_CP_TOP_RT_CPD_MAX__PRE 0x0 +#define OFDM_CP_TOP_RT_SUPR_VAL__A 0x281003C +#define OFDM_CP_TOP_RT_SUPR_VAL__W 2 +#define OFDM_CP_TOP_RT_SUPR_VAL__M 0x3 +#define OFDM_CP_TOP_RT_SUPR_VAL__PRE 0x0 + +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__B 0 +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__W 1 +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__M 0x1 +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__PRE 0x0 + +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__B 1 +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__W 1 +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__M 0x2 +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__PRE 0x0 + + +#define OFDM_CP_TOP_RT_EXP_AVE__A 0x281003D +#define OFDM_CP_TOP_RT_EXP_AVE__W 5 +#define OFDM_CP_TOP_RT_EXP_AVE__M 0x1F +#define OFDM_CP_TOP_RT_EXP_AVE__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__A 0x281003E +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__W 5 +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__M 0x1F +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__PRE 0x3 + +#define OFDM_CP_TOP_AC_NEXP_OFFS__A 0x2810040 +#define OFDM_CP_TOP_AC_NEXP_OFFS__W 8 +#define OFDM_CP_TOP_AC_NEXP_OFFS__M 0xFF +#define OFDM_CP_TOP_AC_NEXP_OFFS__PRE 0x0 + +#define OFDM_CP_TOP_AC_AVER_POW__A 0x2810041 +#define OFDM_CP_TOP_AC_AVER_POW__W 8 +#define OFDM_CP_TOP_AC_AVER_POW__M 0xFF +#define OFDM_CP_TOP_AC_AVER_POW__PRE 0x5F + +#define OFDM_CP_TOP_AC_MAX_POW__A 0x2810042 +#define OFDM_CP_TOP_AC_MAX_POW__W 8 +#define OFDM_CP_TOP_AC_MAX_POW__M 0xFF +#define OFDM_CP_TOP_AC_MAX_POW__PRE 0x7A + +#define OFDM_CP_TOP_AC_WEIGHT_MAN__A 0x2810043 +#define OFDM_CP_TOP_AC_WEIGHT_MAN__W 6 +#define OFDM_CP_TOP_AC_WEIGHT_MAN__M 0x3F +#define OFDM_CP_TOP_AC_WEIGHT_MAN__PRE 0x31 + +#define OFDM_CP_TOP_AC_WEIGHT_EXP__A 0x2810044 +#define OFDM_CP_TOP_AC_WEIGHT_EXP__W 5 +#define OFDM_CP_TOP_AC_WEIGHT_EXP__M 0x1F +#define OFDM_CP_TOP_AC_WEIGHT_EXP__PRE 0x10 + +#define OFDM_CP_TOP_AC_GAIN_MAN__A 0x2810045 +#define OFDM_CP_TOP_AC_GAIN_MAN__W 16 +#define OFDM_CP_TOP_AC_GAIN_MAN__M 0xFFFF +#define OFDM_CP_TOP_AC_GAIN_MAN__PRE 0x0 + +#define OFDM_CP_TOP_AC_GAIN_EXP__A 0x2810046 +#define OFDM_CP_TOP_AC_GAIN_EXP__W 5 +#define OFDM_CP_TOP_AC_GAIN_EXP__M 0x1F +#define OFDM_CP_TOP_AC_GAIN_EXP__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_MODE__A 0x2810047 +#define OFDM_CP_TOP_AC_AMP_MODE__W 2 +#define OFDM_CP_TOP_AC_AMP_MODE__M 0x3 +#define OFDM_CP_TOP_AC_AMP_MODE__PRE 0x2 +#define OFDM_CP_TOP_AC_AMP_MODE_NEW 0x0 +#define OFDM_CP_TOP_AC_AMP_MODE_OLD 0x1 +#define OFDM_CP_TOP_AC_AMP_MODE_FIXED 0x2 + +#define OFDM_CP_TOP_AC_AMP_FIX__A 0x2810048 +#define OFDM_CP_TOP_AC_AMP_FIX__W 14 +#define OFDM_CP_TOP_AC_AMP_FIX__M 0x3FFF +#define OFDM_CP_TOP_AC_AMP_FIX__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__B 0 +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__W 10 +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__M 0x3FF +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__B 10 +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__W 4 +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__M 0x3C00 +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_READ__A 0x2810049 +#define OFDM_CP_TOP_AC_AMP_READ__W 14 +#define OFDM_CP_TOP_AC_AMP_READ__M 0x3FFF +#define OFDM_CP_TOP_AC_AMP_READ__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_READ_MAN__B 0 +#define OFDM_CP_TOP_AC_AMP_READ_MAN__W 10 +#define OFDM_CP_TOP_AC_AMP_READ_MAN__M 0x3FF +#define OFDM_CP_TOP_AC_AMP_READ_MAN__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_READ_EXP__B 10 +#define OFDM_CP_TOP_AC_AMP_READ_EXP__W 4 +#define OFDM_CP_TOP_AC_AMP_READ_EXP__M 0x3C00 +#define OFDM_CP_TOP_AC_AMP_READ_EXP__PRE 0x0 + + +#define OFDM_CP_TOP_AC_ANG_MODE__A 0x281004A +#define OFDM_CP_TOP_AC_ANG_MODE__W 2 +#define OFDM_CP_TOP_AC_ANG_MODE__M 0x3 +#define OFDM_CP_TOP_AC_ANG_MODE__PRE 0x3 +#define OFDM_CP_TOP_AC_ANG_MODE_NEW 0x0 +#define OFDM_CP_TOP_AC_ANG_MODE_OLD 0x1 +#define OFDM_CP_TOP_AC_ANG_MODE_NO_INT 0x2 +#define OFDM_CP_TOP_AC_ANG_MODE_OFFSET 0x3 + + +#define OFDM_CP_TOP_AC_ANG_OFFS__A 0x281004B +#define OFDM_CP_TOP_AC_ANG_OFFS__W 16 +#define OFDM_CP_TOP_AC_ANG_OFFS__M 0xFFFF +#define OFDM_CP_TOP_AC_ANG_OFFS__PRE 0x0 + +#define OFDM_CP_TOP_AC_ANG_READ__A 0x281004C +#define OFDM_CP_TOP_AC_ANG_READ__W 16 +#define OFDM_CP_TOP_AC_ANG_READ__M 0xFFFF +#define OFDM_CP_TOP_AC_ANG_READ__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_REAL0__A 0x2810060 +#define OFDM_CP_TOP_AC_ACCU_REAL0__W 8 +#define OFDM_CP_TOP_AC_ACCU_REAL0__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_REAL0__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_IMAG0__A 0x2810061 +#define OFDM_CP_TOP_AC_ACCU_IMAG0__W 8 +#define OFDM_CP_TOP_AC_ACCU_IMAG0__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_IMAG0__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_REAL1__A 0x2810062 +#define OFDM_CP_TOP_AC_ACCU_REAL1__W 8 +#define OFDM_CP_TOP_AC_ACCU_REAL1__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_REAL1__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_IMAG1__A 0x2810063 +#define OFDM_CP_TOP_AC_ACCU_IMAG1__W 8 +#define OFDM_CP_TOP_AC_ACCU_IMAG1__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_IMAG1__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_ADDR__A 0x2810050 +#define OFDM_CP_TOP_DL_MB_WR_ADDR__W 15 +#define OFDM_CP_TOP_DL_MB_WR_ADDR__M 0x7FFF +#define OFDM_CP_TOP_DL_MB_WR_ADDR__PRE 0x0 +#define OFDM_CP_TOP_DL_MB_WR_CTR__A 0x2810051 +#define OFDM_CP_TOP_DL_MB_WR_CTR__W 5 +#define OFDM_CP_TOP_DL_MB_WR_CTR__M 0x1F +#define OFDM_CP_TOP_DL_MB_WR_CTR__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__B 2 +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__W 3 +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__M 0x1C +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__B 1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__W 1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__M 0x2 +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__B 0 +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__W 1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__M 0x1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__PRE 0x0 + + +#define OFDM_CP_TOP_DL_MB_RD_ADDR__A 0x2810052 +#define OFDM_CP_TOP_DL_MB_RD_ADDR__W 15 +#define OFDM_CP_TOP_DL_MB_RD_ADDR__M 0x7FFF +#define OFDM_CP_TOP_DL_MB_RD_ADDR__PRE 0x0 +#define OFDM_CP_TOP_DL_MB_RD_CTR__A 0x2810053 +#define OFDM_CP_TOP_DL_MB_RD_CTR__W 11 +#define OFDM_CP_TOP_DL_MB_RD_CTR__M 0x7FF +#define OFDM_CP_TOP_DL_MB_RD_CTR__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__B 10 +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__W 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__M 0x400 +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__B 8 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__W 2 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__M 0x300 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__B 5 +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__W 3 +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__M 0xE0 +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__B 2 +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__W 3 +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__M 0x1C +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__B 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__W 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__M 0x2 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__B 0 +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__W 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__M 0x1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__PRE 0x0 + + + +#define OFDM_CP_BR_BUF_CPL_RAM__A 0x2820000 + + + +#define OFDM_CP_BR_BUF_DAT_RAM__A 0x2830000 + + + +#define OFDM_CP_DL_0_RAM__A 0x2840000 + + + +#define OFDM_CP_DL_1_RAM__A 0x2850000 + + + +#define OFDM_CP_DL_2_RAM__A 0x2860000 + + + + + +#define OFDM_EC_COMM_EXEC__A 0x3400000 +#define OFDM_EC_COMM_EXEC__W 3 +#define OFDM_EC_COMM_EXEC__M 0x7 +#define OFDM_EC_COMM_EXEC__PRE 0x0 +#define OFDM_EC_COMM_EXEC_STOP 0x0 +#define OFDM_EC_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_COMM_EXEC_STEP 0x3 +#define OFDM_EC_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_EC_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_EC_COMM_STATE__A 0x3400001 +#define OFDM_EC_COMM_STATE__W 16 +#define OFDM_EC_COMM_STATE__M 0xFFFF +#define OFDM_EC_COMM_STATE__PRE 0x0 +#define OFDM_EC_COMM_MB__A 0x3400002 +#define OFDM_EC_COMM_MB__W 16 +#define OFDM_EC_COMM_MB__M 0xFFFF +#define OFDM_EC_COMM_MB__PRE 0x0 +#define OFDM_EC_COMM_INT_REQ__A 0x3400004 +#define OFDM_EC_COMM_INT_REQ__W 16 +#define OFDM_EC_COMM_INT_REQ__M 0xFFFF +#define OFDM_EC_COMM_INT_REQ__PRE 0x0 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__B 4 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__W 1 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__M 0x10 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__PRE 0x0 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__B 5 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__W 1 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__M 0x20 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__PRE 0x0 + +#define OFDM_EC_COMM_INT_STA__A 0x3400005 +#define OFDM_EC_COMM_INT_STA__W 16 +#define OFDM_EC_COMM_INT_STA__M 0xFFFF +#define OFDM_EC_COMM_INT_STA__PRE 0x0 +#define OFDM_EC_COMM_INT_MSK__A 0x3400006 +#define OFDM_EC_COMM_INT_MSK__W 16 +#define OFDM_EC_COMM_INT_MSK__M 0xFFFF +#define OFDM_EC_COMM_INT_MSK__PRE 0x0 +#define OFDM_EC_COMM_INT_STM__A 0x3400007 +#define OFDM_EC_COMM_INT_STM__W 16 +#define OFDM_EC_COMM_INT_STM__M 0xFFFF +#define OFDM_EC_COMM_INT_STM__PRE 0x0 +#define OFDM_EC_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_EC_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_EC_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_EC_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_EC_SB_COMM_EXEC__A 0x3410000 +#define OFDM_EC_SB_COMM_EXEC__W 3 +#define OFDM_EC_SB_COMM_EXEC__M 0x7 +#define OFDM_EC_SB_COMM_EXEC__PRE 0x0 +#define OFDM_EC_SB_COMM_EXEC_STOP 0x0 +#define OFDM_EC_SB_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_SB_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_SB_COMM_EXEC_STEP 0x3 + +#define OFDM_EC_SB_COMM_STATE__A 0x3410001 +#define OFDM_EC_SB_COMM_STATE__W 4 +#define OFDM_EC_SB_COMM_STATE__M 0xF +#define OFDM_EC_SB_COMM_STATE__PRE 0x0 +#define OFDM_EC_SB_COMM_MB__A 0x3410002 +#define OFDM_EC_SB_COMM_MB__W 2 +#define OFDM_EC_SB_COMM_MB__M 0x3 +#define OFDM_EC_SB_COMM_MB__PRE 0x0 +#define OFDM_EC_SB_COMM_MB_CTL__B 0 +#define OFDM_EC_SB_COMM_MB_CTL__W 1 +#define OFDM_EC_SB_COMM_MB_CTL__M 0x1 +#define OFDM_EC_SB_COMM_MB_CTL__PRE 0x0 +#define OFDM_EC_SB_COMM_MB_CTL_OFF 0x0 +#define OFDM_EC_SB_COMM_MB_CTL_ON 0x1 +#define OFDM_EC_SB_COMM_MB_OBS__B 1 +#define OFDM_EC_SB_COMM_MB_OBS__W 1 +#define OFDM_EC_SB_COMM_MB_OBS__M 0x2 +#define OFDM_EC_SB_COMM_MB_OBS__PRE 0x0 +#define OFDM_EC_SB_COMM_MB_OBS_OFF 0x0 +#define OFDM_EC_SB_COMM_MB_OBS_ON 0x2 + + +#define OFDM_EC_SB_TR_MODE__A 0x3410010 +#define OFDM_EC_SB_TR_MODE__W 1 +#define OFDM_EC_SB_TR_MODE__M 0x1 +#define OFDM_EC_SB_TR_MODE__PRE 0x0 +#define OFDM_EC_SB_TR_MODE_8K 0x0 +#define OFDM_EC_SB_TR_MODE_2K 0x1 + + +#define OFDM_EC_SB_CONST__A 0x3410011 +#define OFDM_EC_SB_CONST__W 2 +#define OFDM_EC_SB_CONST__M 0x3 +#define OFDM_EC_SB_CONST__PRE 0x2 +#define OFDM_EC_SB_CONST_QPSK 0x0 +#define OFDM_EC_SB_CONST_16QAM 0x1 +#define OFDM_EC_SB_CONST_64QAM 0x2 + + +#define OFDM_EC_SB_ALPHA__A 0x3410012 +#define OFDM_EC_SB_ALPHA__W 3 +#define OFDM_EC_SB_ALPHA__M 0x7 +#define OFDM_EC_SB_ALPHA__PRE 0x0 +#define OFDM_EC_SB_ALPHA_NH 0x0 +#define OFDM_EC_SB_ALPHA_H1 0x1 +#define OFDM_EC_SB_ALPHA_H2 0x2 +#define OFDM_EC_SB_ALPHA_H4 0x3 + + +#define OFDM_EC_SB_PRIOR__A 0x3410013 +#define OFDM_EC_SB_PRIOR__W 1 +#define OFDM_EC_SB_PRIOR__M 0x1 +#define OFDM_EC_SB_PRIOR__PRE 0x0 +#define OFDM_EC_SB_PRIOR_HI 0x0 +#define OFDM_EC_SB_PRIOR_LO 0x1 + + +#define OFDM_EC_SB_CSI_HI__A 0x3410014 +#define OFDM_EC_SB_CSI_HI__W 5 +#define OFDM_EC_SB_CSI_HI__M 0x1F +#define OFDM_EC_SB_CSI_HI__PRE 0x18 +#define OFDM_EC_SB_CSI_HI_MAX 0x1F +#define OFDM_EC_SB_CSI_HI_MIN 0x0 +#define OFDM_EC_SB_CSI_HI_TAG 0x0 + + +#define OFDM_EC_SB_CSI_LO__A 0x3410015 +#define OFDM_EC_SB_CSI_LO__W 5 +#define OFDM_EC_SB_CSI_LO__M 0x1F +#define OFDM_EC_SB_CSI_LO__PRE 0xC +#define OFDM_EC_SB_CSI_LO_MAX 0x1F +#define OFDM_EC_SB_CSI_LO_MIN 0x0 +#define OFDM_EC_SB_CSI_LO_TAG 0x0 + + +#define OFDM_EC_SB_SMB_TGL__A 0x3410016 +#define OFDM_EC_SB_SMB_TGL__W 1 +#define OFDM_EC_SB_SMB_TGL__M 0x1 +#define OFDM_EC_SB_SMB_TGL__PRE 0x1 +#define OFDM_EC_SB_SMB_TGL_OFF 0x0 +#define OFDM_EC_SB_SMB_TGL_ON 0x1 + + +#define OFDM_EC_SB_SNR_HI__A 0x3410017 +#define OFDM_EC_SB_SNR_HI__W 7 +#define OFDM_EC_SB_SNR_HI__M 0x7F +#define OFDM_EC_SB_SNR_HI__PRE 0x7F +#define OFDM_EC_SB_SNR_HI_MAX 0x7F +#define OFDM_EC_SB_SNR_HI_MIN 0x0 +#define OFDM_EC_SB_SNR_HI_TAG 0x0 + + +#define OFDM_EC_SB_SNR_MID__A 0x3410018 +#define OFDM_EC_SB_SNR_MID__W 7 +#define OFDM_EC_SB_SNR_MID__M 0x7F +#define OFDM_EC_SB_SNR_MID__PRE 0x7F +#define OFDM_EC_SB_SNR_MID_MAX 0x7F +#define OFDM_EC_SB_SNR_MID_MIN 0x0 +#define OFDM_EC_SB_SNR_MID_TAG 0x0 + + +#define OFDM_EC_SB_SNR_LO__A 0x3410019 +#define OFDM_EC_SB_SNR_LO__W 7 +#define OFDM_EC_SB_SNR_LO__M 0x7F +#define OFDM_EC_SB_SNR_LO__PRE 0x7F +#define OFDM_EC_SB_SNR_LO_MAX 0x7F +#define OFDM_EC_SB_SNR_LO_MIN 0x0 +#define OFDM_EC_SB_SNR_LO_TAG 0x0 + + +#define OFDM_EC_SB_SCALE_MSB__A 0x341001A +#define OFDM_EC_SB_SCALE_MSB__W 6 +#define OFDM_EC_SB_SCALE_MSB__M 0x3F +#define OFDM_EC_SB_SCALE_MSB__PRE 0x30 +#define OFDM_EC_SB_SCALE_MSB_MAX 0x3F + + +#define OFDM_EC_SB_SCALE_BIT2__A 0x341001B +#define OFDM_EC_SB_SCALE_BIT2__W 6 +#define OFDM_EC_SB_SCALE_BIT2__M 0x3F +#define OFDM_EC_SB_SCALE_BIT2__PRE 0xC +#define OFDM_EC_SB_SCALE_BIT2_MAX 0x3F + + +#define OFDM_EC_SB_SCALE_LSB__A 0x341001C +#define OFDM_EC_SB_SCALE_LSB__W 6 +#define OFDM_EC_SB_SCALE_LSB__M 0x3F +#define OFDM_EC_SB_SCALE_LSB__PRE 0x3 +#define OFDM_EC_SB_SCALE_LSB_MAX 0x3F + + +#define OFDM_EC_SB_CSI_OFS0__A 0x341001D +#define OFDM_EC_SB_CSI_OFS0__W 4 +#define OFDM_EC_SB_CSI_OFS0__M 0xF +#define OFDM_EC_SB_CSI_OFS0__PRE 0x1 + +#define OFDM_EC_SB_CSI_OFS1__A 0x341001E +#define OFDM_EC_SB_CSI_OFS1__W 4 +#define OFDM_EC_SB_CSI_OFS1__M 0xF +#define OFDM_EC_SB_CSI_OFS1__PRE 0x1 + +#define OFDM_EC_SB_CSI_OFS2__A 0x341001F +#define OFDM_EC_SB_CSI_OFS2__W 4 +#define OFDM_EC_SB_CSI_OFS2__M 0xF +#define OFDM_EC_SB_CSI_OFS2__PRE 0x1 + +#define OFDM_EC_SB_MAX0__A 0x3410020 +#define OFDM_EC_SB_MAX0__W 6 +#define OFDM_EC_SB_MAX0__M 0x3F +#define OFDM_EC_SB_MAX0__PRE 0x3F + +#define OFDM_EC_SB_MAX1__A 0x3410021 +#define OFDM_EC_SB_MAX1__W 6 +#define OFDM_EC_SB_MAX1__M 0x3F +#define OFDM_EC_SB_MAX1__PRE 0x3F +#define OFDM_EC_SB_MAX1_INIT 0x3F + + +#define OFDM_EC_SB_MAX2__A 0x3410022 +#define OFDM_EC_SB_MAX2__W 6 +#define OFDM_EC_SB_MAX2__M 0x3F +#define OFDM_EC_SB_MAX2__PRE 0x3F + +#define OFDM_EC_SB_CSI_DIS__A 0x3410023 +#define OFDM_EC_SB_CSI_DIS__W 1 +#define OFDM_EC_SB_CSI_DIS__M 0x1 +#define OFDM_EC_SB_CSI_DIS__PRE 0x0 + + + +#define OFDM_EC_VD_COMM_EXEC__A 0x3420000 +#define OFDM_EC_VD_COMM_EXEC__W 3 +#define OFDM_EC_VD_COMM_EXEC__M 0x7 +#define OFDM_EC_VD_COMM_EXEC__PRE 0x0 +#define OFDM_EC_VD_COMM_EXEC_STOP 0x0 +#define OFDM_EC_VD_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_VD_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_VD_COMM_EXEC_STEP 0x3 + +#define OFDM_EC_VD_COMM_STATE__A 0x3420001 +#define OFDM_EC_VD_COMM_STATE__W 4 +#define OFDM_EC_VD_COMM_STATE__M 0xF +#define OFDM_EC_VD_COMM_STATE__PRE 0x0 +#define OFDM_EC_VD_COMM_MB__A 0x3420002 +#define OFDM_EC_VD_COMM_MB__W 2 +#define OFDM_EC_VD_COMM_MB__M 0x3 +#define OFDM_EC_VD_COMM_MB__PRE 0x0 +#define OFDM_EC_VD_COMM_MB_CTL__B 0 +#define OFDM_EC_VD_COMM_MB_CTL__W 1 +#define OFDM_EC_VD_COMM_MB_CTL__M 0x1 +#define OFDM_EC_VD_COMM_MB_CTL__PRE 0x0 +#define OFDM_EC_VD_COMM_MB_CTL_OFF 0x0 +#define OFDM_EC_VD_COMM_MB_CTL_ON 0x1 +#define OFDM_EC_VD_COMM_MB_OBS__B 1 +#define OFDM_EC_VD_COMM_MB_OBS__W 1 +#define OFDM_EC_VD_COMM_MB_OBS__M 0x2 +#define OFDM_EC_VD_COMM_MB_OBS__PRE 0x0 +#define OFDM_EC_VD_COMM_MB_OBS_OFF 0x0 +#define OFDM_EC_VD_COMM_MB_OBS_ON 0x2 + +#define OFDM_EC_VD_COMM_INT_REQ__A 0x3420003 +#define OFDM_EC_VD_COMM_INT_REQ__W 1 +#define OFDM_EC_VD_COMM_INT_REQ__M 0x1 +#define OFDM_EC_VD_COMM_INT_REQ__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_STA__A 0x3420005 +#define OFDM_EC_VD_COMM_INT_STA__W 1 +#define OFDM_EC_VD_COMM_INT_STA__M 0x1 +#define OFDM_EC_VD_COMM_INT_STA__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__B 0 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__W 1 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__M 0x1 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__PRE 0x0 + +#define OFDM_EC_VD_COMM_INT_MSK__A 0x3420006 +#define OFDM_EC_VD_COMM_INT_MSK__W 1 +#define OFDM_EC_VD_COMM_INT_MSK__M 0x1 +#define OFDM_EC_VD_COMM_INT_MSK__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__B 0 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__W 1 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__M 0x1 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__PRE 0x0 + +#define OFDM_EC_VD_COMM_INT_STM__A 0x3420007 +#define OFDM_EC_VD_COMM_INT_STM__W 1 +#define OFDM_EC_VD_COMM_INT_STM__M 0x1 +#define OFDM_EC_VD_COMM_INT_STM__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__B 0 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__W 1 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__M 0x1 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__PRE 0x0 + + +#define OFDM_EC_VD_FORCE__A 0x3420010 +#define OFDM_EC_VD_FORCE__W 2 +#define OFDM_EC_VD_FORCE__M 0x3 +#define OFDM_EC_VD_FORCE__PRE 0x2 +#define OFDM_EC_VD_FORCE_FREE 0x0 +#define OFDM_EC_VD_FORCE_PROP 0x1 +#define OFDM_EC_VD_FORCE_FORCED 0x2 +#define OFDM_EC_VD_FORCE_FIXED 0x3 + + +#define OFDM_EC_VD_SET_CODERATE__A 0x3420011 +#define OFDM_EC_VD_SET_CODERATE__W 3 +#define OFDM_EC_VD_SET_CODERATE__M 0x7 +#define OFDM_EC_VD_SET_CODERATE__PRE 0x1 +#define OFDM_EC_VD_SET_CODERATE_C1_2 0x0 +#define OFDM_EC_VD_SET_CODERATE_C2_3 0x1 +#define OFDM_EC_VD_SET_CODERATE_C3_4 0x2 +#define OFDM_EC_VD_SET_CODERATE_C5_6 0x3 +#define OFDM_EC_VD_SET_CODERATE_C7_8 0x4 + + +#define OFDM_EC_VD_REQ_SMB_CNT__A 0x3420012 +#define OFDM_EC_VD_REQ_SMB_CNT__W 16 +#define OFDM_EC_VD_REQ_SMB_CNT__M 0xFFFF +#define OFDM_EC_VD_REQ_SMB_CNT__PRE 0x1 + +#define OFDM_EC_VD_REQ_BIT_CNT__A 0x3420013 +#define OFDM_EC_VD_REQ_BIT_CNT__W 16 +#define OFDM_EC_VD_REQ_BIT_CNT__M 0xFFFF +#define OFDM_EC_VD_REQ_BIT_CNT__PRE 0xFFF + +#define OFDM_EC_VD_RLK_ENA__A 0x3420014 +#define OFDM_EC_VD_RLK_ENA__W 1 +#define OFDM_EC_VD_RLK_ENA__M 0x1 +#define OFDM_EC_VD_RLK_ENA__PRE 0x1 +#define OFDM_EC_VD_RLK_ENA_OFF 0x0 +#define OFDM_EC_VD_RLK_ENA_ON 0x1 + + +#define OFDM_EC_VD_VAL__A 0x3420015 +#define OFDM_EC_VD_VAL__W 2 +#define OFDM_EC_VD_VAL__M 0x3 +#define OFDM_EC_VD_VAL__PRE 0x0 +#define OFDM_EC_VD_VAL_CODE 0x1 +#define OFDM_EC_VD_VAL_CNT 0x2 + + +#define OFDM_EC_VD_GET_CODERATE__A 0x3420016 +#define OFDM_EC_VD_GET_CODERATE__W 3 +#define OFDM_EC_VD_GET_CODERATE__M 0x7 +#define OFDM_EC_VD_GET_CODERATE__PRE 0x0 +#define OFDM_EC_VD_GET_CODERATE_C1_2 0x0 +#define OFDM_EC_VD_GET_CODERATE_C2_3 0x1 +#define OFDM_EC_VD_GET_CODERATE_C3_4 0x2 +#define OFDM_EC_VD_GET_CODERATE_C5_6 0x3 +#define OFDM_EC_VD_GET_CODERATE_C7_8 0x4 + + +#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 +#define OFDM_EC_VD_ERR_BIT_CNT__W 16 +#define OFDM_EC_VD_ERR_BIT_CNT__M 0xFFFF +#define OFDM_EC_VD_ERR_BIT_CNT__PRE 0xFFFF + +#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 +#define OFDM_EC_VD_IN_BIT_CNT__W 16 +#define OFDM_EC_VD_IN_BIT_CNT__M 0xFFFF +#define OFDM_EC_VD_IN_BIT_CNT__PRE 0x0 + +#define OFDM_EC_VD_STS__A 0x3420019 +#define OFDM_EC_VD_STS__W 1 +#define OFDM_EC_VD_STS__M 0x1 +#define OFDM_EC_VD_STS__PRE 0x0 +#define OFDM_EC_VD_STS_NO_LOCK 0x0 +#define OFDM_EC_VD_STS_IN_LOCK 0x1 + + +#define OFDM_EC_VD_RLK_CNT__A 0x342001A +#define OFDM_EC_VD_RLK_CNT__W 16 +#define OFDM_EC_VD_RLK_CNT__M 0xFFFF +#define OFDM_EC_VD_RLK_CNT__PRE 0x0 + + + +#define OFDM_EC_SY_COMM_EXEC__A 0x3430000 +#define OFDM_EC_SY_COMM_EXEC__W 2 +#define OFDM_EC_SY_COMM_EXEC__M 0x3 +#define OFDM_EC_SY_COMM_EXEC__PRE 0x0 +#define OFDM_EC_SY_COMM_EXEC_STOP 0x0 +#define OFDM_EC_SY_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_SY_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_SY_COMM_EXEC_STEP 0x3 + +#define OFDM_EC_SY_COMM_MB__A 0x3430002 +#define OFDM_EC_SY_COMM_MB__W 2 +#define OFDM_EC_SY_COMM_MB__M 0x3 +#define OFDM_EC_SY_COMM_MB__PRE 0x0 +#define OFDM_EC_SY_COMM_MB_CTL__B 0 +#define OFDM_EC_SY_COMM_MB_CTL__W 1 +#define OFDM_EC_SY_COMM_MB_CTL__M 0x1 +#define OFDM_EC_SY_COMM_MB_CTL__PRE 0x0 +#define OFDM_EC_SY_COMM_MB_CTL_OFF 0x0 +#define OFDM_EC_SY_COMM_MB_CTL_ON 0x1 +#define OFDM_EC_SY_COMM_MB_OBS__B 1 +#define OFDM_EC_SY_COMM_MB_OBS__W 1 +#define OFDM_EC_SY_COMM_MB_OBS__M 0x2 +#define OFDM_EC_SY_COMM_MB_OBS__PRE 0x0 +#define OFDM_EC_SY_COMM_MB_OBS_OFF 0x0 +#define OFDM_EC_SY_COMM_MB_OBS_ON 0x2 + +#define OFDM_EC_SY_COMM_INT_REQ__A 0x3430003 +#define OFDM_EC_SY_COMM_INT_REQ__W 1 +#define OFDM_EC_SY_COMM_INT_REQ__M 0x1 +#define OFDM_EC_SY_COMM_INT_REQ__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STA__A 0x3430005 +#define OFDM_EC_SY_COMM_INT_STA__W 3 +#define OFDM_EC_SY_COMM_INT_STA__M 0x7 +#define OFDM_EC_SY_COMM_INT_STA__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__B 0 +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__W 1 +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__M 0x1 +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__B 1 +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__W 1 +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_MSK__A 0x3430006 +#define OFDM_EC_SY_COMM_INT_MSK__W 3 +#define OFDM_EC_SY_COMM_INT_MSK__M 0x7 +#define OFDM_EC_SY_COMM_INT_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__B 0 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STM__A 0x3430007 +#define OFDM_EC_SY_COMM_INT_STM__W 3 +#define OFDM_EC_SY_COMM_INT_STM__M 0x7 +#define OFDM_EC_SY_COMM_INT_STM__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__B 0 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 + +#define OFDM_EC_SY_STATUS__A 0x3430010 +#define OFDM_EC_SY_STATUS__W 2 +#define OFDM_EC_SY_STATUS__M 0x3 +#define OFDM_EC_SY_STATUS__PRE 0x0 +#define OFDM_EC_SY_STATUS_SYNC_STATE__B 0 +#define OFDM_EC_SY_STATUS_SYNC_STATE__W 2 +#define OFDM_EC_SY_STATUS_SYNC_STATE__M 0x3 +#define OFDM_EC_SY_STATUS_SYNC_STATE__PRE 0x0 +#define OFDM_EC_SY_STATUS_SYNC_STATE_HUNTING 0x0 +#define OFDM_EC_SY_STATUS_SYNC_STATE_TRYING 0x1 +#define OFDM_EC_SY_STATUS_SYNC_STATE_IN_SYNC 0x2 + + +#define OFDM_EC_SY_TIMEOUT__A 0x3430011 +#define OFDM_EC_SY_TIMEOUT__W 16 +#define OFDM_EC_SY_TIMEOUT__M 0xFFFF +#define OFDM_EC_SY_TIMEOUT__PRE 0x3A98 + +#define OFDM_EC_SY_SYNC_LWM__A 0x3430012 +#define OFDM_EC_SY_SYNC_LWM__W 4 +#define OFDM_EC_SY_SYNC_LWM__M 0xF +#define OFDM_EC_SY_SYNC_LWM__PRE 0x2 + +#define OFDM_EC_SY_SYNC_AWM__A 0x3430013 +#define OFDM_EC_SY_SYNC_AWM__W 4 +#define OFDM_EC_SY_SYNC_AWM__M 0xF +#define OFDM_EC_SY_SYNC_AWM__PRE 0x3 + +#define OFDM_EC_SY_SYNC_HWM__A 0x3430014 +#define OFDM_EC_SY_SYNC_HWM__W 4 +#define OFDM_EC_SY_SYNC_HWM__M 0xF +#define OFDM_EC_SY_SYNC_HWM__PRE 0x5 + +#define OFDM_EC_SY_UNLOCK__A 0x3430015 +#define OFDM_EC_SY_UNLOCK__W 1 +#define OFDM_EC_SY_UNLOCK__M 0x1 +#define OFDM_EC_SY_UNLOCK__PRE 0x0 + + + +#define OFDM_EC_SB_BD0_RAM__A 0x3440000 + + + +#define OFDM_EC_SB_BD1_RAM__A 0x3450000 + + + +#define OFDM_EC_SB_SD_RAM__A 0x3460000 + + + +#define OFDM_EC_VD_RE_RAM__A 0x3470000 + + + +#define OFDM_EC_VD_TB0_RAM__A 0x3480000 + + + +#define OFDM_EC_VD_TB1_RAM__A 0x3490000 + + + +#define OFDM_EC_VD_TB2_RAM__A 0x34A0000 + + + +#define OFDM_EC_VD_TB3_RAM__A 0x34B0000 + + + + + +#define OFDM_EQ_COMM_EXEC__A 0x3000000 +#define OFDM_EQ_COMM_EXEC__W 3 +#define OFDM_EQ_COMM_EXEC__M 0x7 +#define OFDM_EQ_COMM_EXEC__PRE 0x0 +#define OFDM_EQ_COMM_EXEC_STOP 0x0 +#define OFDM_EQ_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EQ_COMM_EXEC_HOLD 0x2 +#define OFDM_EQ_COMM_EXEC_STEP 0x3 +#define OFDM_EQ_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_EQ_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_EQ_COMM_STATE__A 0x3000001 +#define OFDM_EQ_COMM_STATE__W 16 +#define OFDM_EQ_COMM_STATE__M 0xFFFF +#define OFDM_EQ_COMM_STATE__PRE 0x0 +#define OFDM_EQ_COMM_MB__A 0x3000002 +#define OFDM_EQ_COMM_MB__W 16 +#define OFDM_EQ_COMM_MB__M 0xFFFF +#define OFDM_EQ_COMM_MB__PRE 0x0 +#define OFDM_EQ_COMM_INT_REQ__A 0x3000004 +#define OFDM_EQ_COMM_INT_REQ__W 16 +#define OFDM_EQ_COMM_INT_REQ__M 0xFFFF +#define OFDM_EQ_COMM_INT_REQ__PRE 0x0 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__B 3 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__W 1 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__M 0x8 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__PRE 0x0 + +#define OFDM_EQ_COMM_INT_STA__A 0x3000005 +#define OFDM_EQ_COMM_INT_STA__W 16 +#define OFDM_EQ_COMM_INT_STA__M 0xFFFF +#define OFDM_EQ_COMM_INT_STA__PRE 0x0 +#define OFDM_EQ_COMM_INT_MSK__A 0x3000006 +#define OFDM_EQ_COMM_INT_MSK__W 16 +#define OFDM_EQ_COMM_INT_MSK__M 0xFFFF +#define OFDM_EQ_COMM_INT_MSK__PRE 0x0 +#define OFDM_EQ_COMM_INT_STM__A 0x3000007 +#define OFDM_EQ_COMM_INT_STM__W 16 +#define OFDM_EQ_COMM_INT_STM__M 0xFFFF +#define OFDM_EQ_COMM_INT_STM__PRE 0x0 +#define OFDM_EQ_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_EQ_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_EQ_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_EQ_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_EQ_TOP_COMM_EXEC__A 0x3010000 +#define OFDM_EQ_TOP_COMM_EXEC__W 3 +#define OFDM_EQ_TOP_COMM_EXEC__M 0x7 +#define OFDM_EQ_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_EQ_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_EQ_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EQ_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_EQ_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_EQ_TOP_COMM_STATE__A 0x3010001 +#define OFDM_EQ_TOP_COMM_STATE__W 4 +#define OFDM_EQ_TOP_COMM_STATE__M 0xF +#define OFDM_EQ_TOP_COMM_STATE__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB__A 0x3010002 +#define OFDM_EQ_TOP_COMM_MB__W 6 +#define OFDM_EQ_TOP_COMM_MB__M 0x3F +#define OFDM_EQ_TOP_COMM_MB__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL__B 0 +#define OFDM_EQ_TOP_COMM_MB_CTL__W 1 +#define OFDM_EQ_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_EQ_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_EQ_TOP_COMM_MB_OBS__B 1 +#define OFDM_EQ_TOP_COMM_MB_OBS__W 1 +#define OFDM_EQ_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_EQ_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_ON 0x2 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__B 2 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__W 2 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__M 0xC +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_OT 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_RC 0x4 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_IS 0x8 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__B 4 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__W 2 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__M 0x30 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_OT 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_RC 0x10 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_IS 0x20 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_SN 0x30 + +#define OFDM_EQ_TOP_COMM_INT_REQ__A 0x3010004 +#define OFDM_EQ_TOP_COMM_INT_REQ__W 1 +#define OFDM_EQ_TOP_COMM_INT_REQ__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_REQ__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STA__A 0x3010005 +#define OFDM_EQ_TOP_COMM_INT_STA__W 2 +#define OFDM_EQ_TOP_COMM_INT_STA__M 0x3 +#define OFDM_EQ_TOP_COMM_INT_STA__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__B 0 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__B 1 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__M 0x2 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__PRE 0x0 + +#define OFDM_EQ_TOP_COMM_INT_MSK__A 0x3010006 +#define OFDM_EQ_TOP_COMM_INT_MSK__W 2 +#define OFDM_EQ_TOP_COMM_INT_MSK__M 0x3 +#define OFDM_EQ_TOP_COMM_INT_MSK__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__B 0 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__B 1 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__M 0x2 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__PRE 0x0 + +#define OFDM_EQ_TOP_COMM_INT_STM__A 0x3010007 +#define OFDM_EQ_TOP_COMM_INT_STM__W 2 +#define OFDM_EQ_TOP_COMM_INT_STM__M 0x3 +#define OFDM_EQ_TOP_COMM_INT_STM__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__B 0 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__B 1 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__M 0x2 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__PRE 0x0 + +#define OFDM_EQ_TOP_IS_MODE__A 0x3010014 +#define OFDM_EQ_TOP_IS_MODE__W 4 +#define OFDM_EQ_TOP_IS_MODE__M 0xF +#define OFDM_EQ_TOP_IS_MODE__PRE 0x0 + +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__B 0 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__M 0x1 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_MAX 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_ZER 0x1 + +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__B 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__M 0x2 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_ONE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_TWO 0x2 + +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__B 2 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__M 0x4 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_ENABLE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_DISABLE 0x4 + +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__B 3 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__M 0x8 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_ENABLE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_DISABLE 0x8 + + +#define OFDM_EQ_TOP_IS_GAIN_MAN__A 0x3010015 +#define OFDM_EQ_TOP_IS_GAIN_MAN__W 10 +#define OFDM_EQ_TOP_IS_GAIN_MAN__M 0x3FF +#define OFDM_EQ_TOP_IS_GAIN_MAN__PRE 0x114 + +#define OFDM_EQ_TOP_IS_GAIN_EXP__A 0x3010016 +#define OFDM_EQ_TOP_IS_GAIN_EXP__W 5 +#define OFDM_EQ_TOP_IS_GAIN_EXP__M 0x1F +#define OFDM_EQ_TOP_IS_GAIN_EXP__PRE 0x5 + +#define OFDM_EQ_TOP_IS_CLIP_EXP__A 0x3010017 +#define OFDM_EQ_TOP_IS_CLIP_EXP__W 5 +#define OFDM_EQ_TOP_IS_CLIP_EXP__M 0x1F +#define OFDM_EQ_TOP_IS_CLIP_EXP__PRE 0x10 +#define OFDM_EQ_TOP_DV_MODE__A 0x301001E +#define OFDM_EQ_TOP_DV_MODE__W 4 +#define OFDM_EQ_TOP_DV_MODE__M 0xF +#define OFDM_EQ_TOP_DV_MODE__PRE 0xF + +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__B 0 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__M 0x1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__PRE 0x1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_ENA 0x1 + +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__B 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__M 0x2 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__PRE 0x2 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_ENA 0x2 + +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__B 2 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__M 0x4 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__PRE 0x4 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_ENA 0x4 + +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__B 3 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__M 0x8 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__PRE 0x8 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_ENA 0x8 + + +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__A 0x301001F +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__W 16 +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__M 0xFFFF +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE__A 0x3010028 +#define OFDM_EQ_TOP_SN_MODE__W 8 +#define OFDM_EQ_TOP_SN_MODE__M 0xFF +#define OFDM_EQ_TOP_SN_MODE__PRE 0x18 + +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__B 0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__M 0x1 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_ENABLE 0x1 + +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__B 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__M 0x2 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_ENABLE 0x2 + +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__B 2 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__M 0x4 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_ENABLE 0x4 + +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__B 3 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__M 0x8 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__PRE 0x8 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_ENABLE 0x8 + +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__B 4 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__M 0x10 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__PRE 0x10 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_ENABLE 0x10 + +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__B 5 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__M 0x20 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_ENABLE 0x20 + +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__B 6 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__W 1 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__M 0x40 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_DYNAMIC 0x0 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_STATIC 0x40 + +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__B 7 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__W 1 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__M 0x80 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_DYNAMIC 0x0 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_STATIC 0x80 + + +#define OFDM_EQ_TOP_SN_PFIX__A 0x3010029 +#define OFDM_EQ_TOP_SN_PFIX__W 8 +#define OFDM_EQ_TOP_SN_PFIX__M 0xFF +#define OFDM_EQ_TOP_SN_PFIX__PRE 0x0 + +#define OFDM_EQ_TOP_SN_CEGAIN__A 0x301002A +#define OFDM_EQ_TOP_SN_CEGAIN__W 8 +#define OFDM_EQ_TOP_SN_CEGAIN__M 0xFF +#define OFDM_EQ_TOP_SN_CEGAIN__PRE 0x30 + +#define OFDM_EQ_TOP_SN_OFFSET__A 0x301002B +#define OFDM_EQ_TOP_SN_OFFSET__W 6 +#define OFDM_EQ_TOP_SN_OFFSET__M 0x3F +#define OFDM_EQ_TOP_SN_OFFSET__PRE 0x39 + +#define OFDM_EQ_TOP_SN_NULLIFY__A 0x301002C +#define OFDM_EQ_TOP_SN_NULLIFY__W 6 +#define OFDM_EQ_TOP_SN_NULLIFY__M 0x3F +#define OFDM_EQ_TOP_SN_NULLIFY__PRE 0x0 +#define OFDM_EQ_TOP_SN_SQUASH__A 0x301002D +#define OFDM_EQ_TOP_SN_SQUASH__W 10 +#define OFDM_EQ_TOP_SN_SQUASH__M 0x3FF +#define OFDM_EQ_TOP_SN_SQUASH__PRE 0x7 + +#define OFDM_EQ_TOP_SN_SQUASH_MAN__B 0 +#define OFDM_EQ_TOP_SN_SQUASH_MAN__W 6 +#define OFDM_EQ_TOP_SN_SQUASH_MAN__M 0x3F +#define OFDM_EQ_TOP_SN_SQUASH_MAN__PRE 0x7 + +#define OFDM_EQ_TOP_SN_SQUASH_EXP__B 6 +#define OFDM_EQ_TOP_SN_SQUASH_EXP__W 4 +#define OFDM_EQ_TOP_SN_SQUASH_EXP__M 0x3C0 +#define OFDM_EQ_TOP_SN_SQUASH_EXP__PRE 0x0 + +#define OFDM_EQ_TOP_RC_SEL_CAR__A 0x3010032 +#define OFDM_EQ_TOP_RC_SEL_CAR__W 8 +#define OFDM_EQ_TOP_RC_SEL_CAR__M 0xFF +#define OFDM_EQ_TOP_RC_SEL_CAR__PRE 0x2 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__B 0 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__W 1 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__M 0x1 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_OFF 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_ON 0x1 + +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__B 1 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__W 2 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__M 0x6 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__PRE 0x2 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_A_CC 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_B_CE 0x2 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_C_DRI 0x4 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_D_CC 0x6 + +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__B 3 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__W 2 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__M 0x18 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_A_CC 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_B_CE 0x8 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_C_DRI 0x10 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_D_CC 0x18 + +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__B 5 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__W 2 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__M 0x60 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_A_CC 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_B_CE 0x20 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_C_DRI 0x40 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_D_CC 0x60 + +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__B 7 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__W 1 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__M 0x80 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_2K 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_8K 0x80 + +#define OFDM_EQ_TOP_RC_STS__A 0x3010033 +#define OFDM_EQ_TOP_RC_STS__W 16 +#define OFDM_EQ_TOP_RC_STS__M 0xFFFF +#define OFDM_EQ_TOP_RC_STS__PRE 0x0 + +#define OFDM_EQ_TOP_RC_STS_DIFF__B 0 +#define OFDM_EQ_TOP_RC_STS_DIFF__W 11 +#define OFDM_EQ_TOP_RC_STS_DIFF__M 0x7FF +#define OFDM_EQ_TOP_RC_STS_DIFF__PRE 0x0 + +#define OFDM_EQ_TOP_RC_STS_FIRST__B 11 +#define OFDM_EQ_TOP_RC_STS_FIRST__W 1 +#define OFDM_EQ_TOP_RC_STS_FIRST__M 0x800 +#define OFDM_EQ_TOP_RC_STS_FIRST__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_FIRST_A_CE 0x0 +#define OFDM_EQ_TOP_RC_STS_FIRST_B_DRI 0x800 + +#define OFDM_EQ_TOP_RC_STS_SELEC__B 12 +#define OFDM_EQ_TOP_RC_STS_SELEC__W 1 +#define OFDM_EQ_TOP_RC_STS_SELEC__M 0x1000 +#define OFDM_EQ_TOP_RC_STS_SELEC__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_SELEC_A_CE 0x0 +#define OFDM_EQ_TOP_RC_STS_SELEC_B_DRI 0x1000 + +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__B 13 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__W 1 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__M 0x2000 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW_NO 0x0 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW_YES 0x2000 + +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__B 14 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__W 1 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__M 0x4000 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS_NO 0x0 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS_YES 0x4000 + +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__B 15 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__W 1 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__M 0x8000 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS_NO 0x0 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS_YES 0x8000 + + +#define OFDM_EQ_TOP_OT_CONST__A 0x3010046 +#define OFDM_EQ_TOP_OT_CONST__W 2 +#define OFDM_EQ_TOP_OT_CONST__M 0x3 +#define OFDM_EQ_TOP_OT_CONST__PRE 0x2 + +#define OFDM_EQ_TOP_OT_ALPHA__A 0x3010047 +#define OFDM_EQ_TOP_OT_ALPHA__W 2 +#define OFDM_EQ_TOP_OT_ALPHA__M 0x3 +#define OFDM_EQ_TOP_OT_ALPHA__PRE 0x0 + +#define OFDM_EQ_TOP_OT_QNT_THRES0__A 0x3010048 +#define OFDM_EQ_TOP_OT_QNT_THRES0__W 5 +#define OFDM_EQ_TOP_OT_QNT_THRES0__M 0x1F +#define OFDM_EQ_TOP_OT_QNT_THRES0__PRE 0x1E + +#define OFDM_EQ_TOP_OT_QNT_THRES1__A 0x3010049 +#define OFDM_EQ_TOP_OT_QNT_THRES1__W 5 +#define OFDM_EQ_TOP_OT_QNT_THRES1__M 0x1F +#define OFDM_EQ_TOP_OT_QNT_THRES1__PRE 0x1F + +#define OFDM_EQ_TOP_OT_CSI_STEP__A 0x301004A +#define OFDM_EQ_TOP_OT_CSI_STEP__W 4 +#define OFDM_EQ_TOP_OT_CSI_STEP__M 0xF +#define OFDM_EQ_TOP_OT_CSI_STEP__PRE 0x5 + +#define OFDM_EQ_TOP_OT_CSI_OFFSET__A 0x301004B +#define OFDM_EQ_TOP_OT_CSI_OFFSET__W 8 +#define OFDM_EQ_TOP_OT_CSI_OFFSET__M 0xFF +#define OFDM_EQ_TOP_OT_CSI_OFFSET__PRE 0x5 + +#define OFDM_EQ_TOP_OT_CSI_GAIN__A 0x301004C +#define OFDM_EQ_TOP_OT_CSI_GAIN__W 8 +#define OFDM_EQ_TOP_OT_CSI_GAIN__M 0xFF +#define OFDM_EQ_TOP_OT_CSI_GAIN__PRE 0x2B + +#define OFDM_EQ_TOP_OT_CSI_MEAN__A 0x301004D +#define OFDM_EQ_TOP_OT_CSI_MEAN__W 7 +#define OFDM_EQ_TOP_OT_CSI_MEAN__M 0x7F +#define OFDM_EQ_TOP_OT_CSI_MEAN__PRE 0x0 + +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__A 0x301004E +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__W 7 +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__M 0x7F +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_INIT__A 0x3010050 +#define OFDM_EQ_TOP_TD_TPS_INIT__W 1 +#define OFDM_EQ_TOP_TD_TPS_INIT__M 0x1 +#define OFDM_EQ_TOP_TD_TPS_INIT__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_INIT_POS 0x0 +#define OFDM_EQ_TOP_TD_TPS_INIT_NEG 0x1 + + +#define OFDM_EQ_TOP_TD_TPS_SYNC__A 0x3010051 +#define OFDM_EQ_TOP_TD_TPS_SYNC__W 16 +#define OFDM_EQ_TOP_TD_TPS_SYNC__M 0xFFFF +#define OFDM_EQ_TOP_TD_TPS_SYNC__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_SYNC_ODD 0x35EE +#define OFDM_EQ_TOP_TD_TPS_SYNC_EVEN 0xCA11 + + +#define OFDM_EQ_TOP_TD_TPS_LEN__A 0x3010052 +#define OFDM_EQ_TOP_TD_TPS_LEN__W 6 +#define OFDM_EQ_TOP_TD_TPS_LEN__M 0x3F +#define OFDM_EQ_TOP_TD_TPS_LEN__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_LEN_DEF 0x17 +#define OFDM_EQ_TOP_TD_TPS_LEN_ID_SUP 0x1F + + +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__A 0x3010053 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__W 2 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_1 0x0 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_2 0x1 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_3 0x2 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_4 0x3 + + +#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 +#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 +#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 +#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 +#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 + + +#define OFDM_EQ_TOP_TD_TPS_HINFO__A 0x3010055 +#define OFDM_EQ_TOP_TD_TPS_HINFO__W 3 +#define OFDM_EQ_TOP_TD_TPS_HINFO__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_HINFO__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_HINFO_NH 0x0 +#define OFDM_EQ_TOP_TD_TPS_HINFO_H1 0x1 +#define OFDM_EQ_TOP_TD_TPS_HINFO_H2 0x2 +#define OFDM_EQ_TOP_TD_TPS_HINFO_H4 0x3 + + +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__W 3 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_1_2 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_2_3 0x1 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_3_4 0x2 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_5_6 0x3 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_7_8 0x4 + + +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 + + +#define OFDM_EQ_TOP_TD_TPS_GUARD__A 0x3010058 +#define OFDM_EQ_TOP_TD_TPS_GUARD__W 2 +#define OFDM_EQ_TOP_TD_TPS_GUARD__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_GUARD__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_GUARD_32 0x0 +#define OFDM_EQ_TOP_TD_TPS_GUARD_16 0x1 +#define OFDM_EQ_TOP_TD_TPS_GUARD_08 0x2 +#define OFDM_EQ_TOP_TD_TPS_GUARD_04 0x3 + + +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__A 0x3010059 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__W 2 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE_2K 0x0 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE_8K 0x1 + + +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__A 0x301005A +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__W 8 +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__M 0xFF +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__A 0x301005B +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__W 8 +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__M 0xFF +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_RSV__A 0x301005C +#define OFDM_EQ_TOP_TD_TPS_RSV__W 6 +#define OFDM_EQ_TOP_TD_TPS_RSV__M 0x3F +#define OFDM_EQ_TOP_TD_TPS_RSV__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_BCH__A 0x301005D +#define OFDM_EQ_TOP_TD_TPS_BCH__W 14 +#define OFDM_EQ_TOP_TD_TPS_BCH__M 0x3FFF +#define OFDM_EQ_TOP_TD_TPS_BCH__PRE 0x0 + +#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E +#define OFDM_EQ_TOP_TD_SQR_ERR_I__W 16 +#define OFDM_EQ_TOP_TD_SQR_ERR_I__M 0xFFFF +#define OFDM_EQ_TOP_TD_SQR_ERR_I__PRE 0x0 + +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__W 16 +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__M 0xFFFF +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__PRE 0x0 + +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__W 4 +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__M 0xF +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__PRE 0x0 + +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__W 16 +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__M 0xFFFF +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__PRE 0x200 + +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__W 10 +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__M 0x3FF +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__PRE 0x19F + + + + + +#define OFDM_FE_COMM_EXEC__A 0x2000000 +#define OFDM_FE_COMM_EXEC__W 3 +#define OFDM_FE_COMM_EXEC__M 0x7 +#define OFDM_FE_COMM_EXEC__PRE 0x0 +#define OFDM_FE_COMM_EXEC_STOP 0x0 +#define OFDM_FE_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FE_COMM_EXEC_HOLD 0x2 +#define OFDM_FE_COMM_EXEC_STEP 0x3 + +#define OFDM_FE_COMM_STATE__A 0x2000001 +#define OFDM_FE_COMM_STATE__W 16 +#define OFDM_FE_COMM_STATE__M 0xFFFF +#define OFDM_FE_COMM_STATE__PRE 0x0 +#define OFDM_FE_COMM_MB__A 0x2000002 +#define OFDM_FE_COMM_MB__W 16 +#define OFDM_FE_COMM_MB__M 0xFFFF +#define OFDM_FE_COMM_MB__PRE 0x0 +#define OFDM_FE_COMM_INT_REQ__A 0x2000004 +#define OFDM_FE_COMM_INT_REQ__W 16 +#define OFDM_FE_COMM_INT_REQ__M 0xFFFF +#define OFDM_FE_COMM_INT_REQ__PRE 0x0 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__B 0 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__W 1 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__M 0x1 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__PRE 0x0 + +#define OFDM_FE_COMM_INT_STA__A 0x2000005 +#define OFDM_FE_COMM_INT_STA__W 16 +#define OFDM_FE_COMM_INT_STA__M 0xFFFF +#define OFDM_FE_COMM_INT_STA__PRE 0x0 +#define OFDM_FE_COMM_INT_MSK__A 0x2000006 +#define OFDM_FE_COMM_INT_MSK__W 16 +#define OFDM_FE_COMM_INT_MSK__M 0xFFFF +#define OFDM_FE_COMM_INT_MSK__PRE 0x0 +#define OFDM_FE_COMM_INT_STM__A 0x2000007 +#define OFDM_FE_COMM_INT_STM__W 16 +#define OFDM_FE_COMM_INT_STM__M 0xFFFF +#define OFDM_FE_COMM_INT_STM__PRE 0x0 +#define OFDM_FE_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_FE_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_FE_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_FE_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_FE_CU_COMM_EXEC__A 0x2010000 +#define OFDM_FE_CU_COMM_EXEC__W 3 +#define OFDM_FE_CU_COMM_EXEC__M 0x7 +#define OFDM_FE_CU_COMM_EXEC__PRE 0x0 +#define OFDM_FE_CU_COMM_EXEC_STOP 0x0 +#define OFDM_FE_CU_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FE_CU_COMM_EXEC_HOLD 0x2 +#define OFDM_FE_CU_COMM_EXEC_STEP 0x3 + +#define OFDM_FE_CU_COMM_STATE__A 0x2010001 +#define OFDM_FE_CU_COMM_STATE__W 4 +#define OFDM_FE_CU_COMM_STATE__M 0xF +#define OFDM_FE_CU_COMM_STATE__PRE 0x0 +#define OFDM_FE_CU_COMM_MB__A 0x2010002 +#define OFDM_FE_CU_COMM_MB__W 2 +#define OFDM_FE_CU_COMM_MB__M 0x3 +#define OFDM_FE_CU_COMM_MB__PRE 0x0 +#define OFDM_FE_CU_COMM_MB_CTL__B 0 +#define OFDM_FE_CU_COMM_MB_CTL__W 1 +#define OFDM_FE_CU_COMM_MB_CTL__M 0x1 +#define OFDM_FE_CU_COMM_MB_CTL__PRE 0x0 +#define OFDM_FE_CU_COMM_MB_CTL_OFF 0x0 +#define OFDM_FE_CU_COMM_MB_CTL_ON 0x1 +#define OFDM_FE_CU_COMM_MB_OBS__B 1 +#define OFDM_FE_CU_COMM_MB_OBS__W 1 +#define OFDM_FE_CU_COMM_MB_OBS__M 0x2 +#define OFDM_FE_CU_COMM_MB_OBS__PRE 0x0 +#define OFDM_FE_CU_COMM_MB_OBS_OFF 0x0 +#define OFDM_FE_CU_COMM_MB_OBS_ON 0x2 + +#define OFDM_FE_CU_COMM_INT_REQ__A 0x2010004 +#define OFDM_FE_CU_COMM_INT_REQ__W 1 +#define OFDM_FE_CU_COMM_INT_REQ__M 0x1 +#define OFDM_FE_CU_COMM_INT_REQ__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA__A 0x2010005 +#define OFDM_FE_CU_COMM_INT_STA__W 4 +#define OFDM_FE_CU_COMM_INT_STA__M 0xF +#define OFDM_FE_CU_COMM_INT_STA__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__B 0 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__W 1 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__M 0x1 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__B 1 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__W 1 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__M 0x2 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__B 2 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__W 1 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__M 0x4 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__B 3 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__W 1 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__M 0x8 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__PRE 0x0 + +#define OFDM_FE_CU_COMM_INT_MSK__A 0x2010006 +#define OFDM_FE_CU_COMM_INT_MSK__W 4 +#define OFDM_FE_CU_COMM_INT_MSK__M 0xF +#define OFDM_FE_CU_COMM_INT_MSK__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__B 0 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__M 0x1 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__B 1 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__M 0x2 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__B 2 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__M 0x4 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__B 3 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__M 0x8 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__PRE 0x0 + +#define OFDM_FE_CU_COMM_INT_STM__A 0x2010007 +#define OFDM_FE_CU_COMM_INT_STM__W 4 +#define OFDM_FE_CU_COMM_INT_STM__M 0xF +#define OFDM_FE_CU_COMM_INT_STM__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__B 0 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__W 1 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__M 0x1 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__B 1 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__W 1 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__M 0x2 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__B 2 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__W 1 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__M 0x4 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__B 3 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__W 1 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__M 0x8 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__PRE 0x0 + +#define OFDM_FE_CU_MODE__A 0x2010010 +#define OFDM_FE_CU_MODE__W 8 +#define OFDM_FE_CU_MODE__M 0xFF +#define OFDM_FE_CU_MODE__PRE 0x20 + +#define OFDM_FE_CU_MODE_FFT__B 0 +#define OFDM_FE_CU_MODE_FFT__W 1 +#define OFDM_FE_CU_MODE_FFT__M 0x1 +#define OFDM_FE_CU_MODE_FFT__PRE 0x0 +#define OFDM_FE_CU_MODE_FFT_M8K 0x0 +#define OFDM_FE_CU_MODE_FFT_M2K 0x1 + +#define OFDM_FE_CU_MODE_COR__B 1 +#define OFDM_FE_CU_MODE_COR__W 1 +#define OFDM_FE_CU_MODE_COR__M 0x2 +#define OFDM_FE_CU_MODE_COR__PRE 0x0 +#define OFDM_FE_CU_MODE_COR_OFF 0x0 +#define OFDM_FE_CU_MODE_COR_ON 0x2 + +#define OFDM_FE_CU_MODE_IFD__B 2 +#define OFDM_FE_CU_MODE_IFD__W 1 +#define OFDM_FE_CU_MODE_IFD__M 0x4 +#define OFDM_FE_CU_MODE_IFD__PRE 0x0 +#define OFDM_FE_CU_MODE_IFD_ENABLE 0x0 +#define OFDM_FE_CU_MODE_IFD_DISABLE 0x4 + +#define OFDM_FE_CU_MODE_SEL__B 3 +#define OFDM_FE_CU_MODE_SEL__W 1 +#define OFDM_FE_CU_MODE_SEL__M 0x8 +#define OFDM_FE_CU_MODE_SEL__PRE 0x0 +#define OFDM_FE_CU_MODE_SEL_COR 0x0 +#define OFDM_FE_CU_MODE_SEL_COR_NFC 0x8 + +#define OFDM_FE_CU_MODE_FES__B 4 +#define OFDM_FE_CU_MODE_FES__W 1 +#define OFDM_FE_CU_MODE_FES__M 0x10 +#define OFDM_FE_CU_MODE_FES__PRE 0x0 +#define OFDM_FE_CU_MODE_FES_SEL_RST 0x0 +#define OFDM_FE_CU_MODE_FES_SEL_UPD 0x10 +#define OFDM_FE_CU_MODE_AVG__B 5 +#define OFDM_FE_CU_MODE_AVG__W 1 +#define OFDM_FE_CU_MODE_AVG__M 0x20 +#define OFDM_FE_CU_MODE_AVG__PRE 0x20 +#define OFDM_FE_CU_MODE_AVG_OFF 0x0 +#define OFDM_FE_CU_MODE_AVG_ON 0x20 +#define OFDM_FE_CU_MODE_SHF_ENA__B 6 +#define OFDM_FE_CU_MODE_SHF_ENA__W 1 +#define OFDM_FE_CU_MODE_SHF_ENA__M 0x40 +#define OFDM_FE_CU_MODE_SHF_ENA__PRE 0x0 +#define OFDM_FE_CU_MODE_SHF_ENA_OFF 0x0 +#define OFDM_FE_CU_MODE_SHF_ENA_ON 0x40 +#define OFDM_FE_CU_MODE_SHF_DIR__B 7 +#define OFDM_FE_CU_MODE_SHF_DIR__W 1 +#define OFDM_FE_CU_MODE_SHF_DIR__M 0x80 +#define OFDM_FE_CU_MODE_SHF_DIR__PRE 0x0 +#define OFDM_FE_CU_MODE_SHF_DIR_POS 0x0 +#define OFDM_FE_CU_MODE_SHF_DIR_NEG 0x80 + + +#define OFDM_FE_CU_FRM_CNT_RST__A 0x2010011 +#define OFDM_FE_CU_FRM_CNT_RST__W 15 +#define OFDM_FE_CU_FRM_CNT_RST__M 0x7FFF +#define OFDM_FE_CU_FRM_CNT_RST__PRE 0x20FF + +#define OFDM_FE_CU_FRM_CNT_STR__A 0x2010012 +#define OFDM_FE_CU_FRM_CNT_STR__W 15 +#define OFDM_FE_CU_FRM_CNT_STR__M 0x7FFF +#define OFDM_FE_CU_FRM_CNT_STR__PRE 0x1E + +#define OFDM_FE_CU_FRM_SMP_CNT__A 0x2010013 +#define OFDM_FE_CU_FRM_SMP_CNT__W 15 +#define OFDM_FE_CU_FRM_SMP_CNT__M 0x7FFF +#define OFDM_FE_CU_FRM_SMP_CNT__PRE 0x0 + +#define OFDM_FE_CU_FRM_SMB_CNT__A 0x2010014 +#define OFDM_FE_CU_FRM_SMB_CNT__W 16 +#define OFDM_FE_CU_FRM_SMB_CNT__M 0xFFFF +#define OFDM_FE_CU_FRM_SMB_CNT__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_DAT__A 0x2010015 +#define OFDM_FE_CU_CMP_MAX_DAT__W 12 +#define OFDM_FE_CU_CMP_MAX_DAT__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_DAT__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_ADR__A 0x2010016 +#define OFDM_FE_CU_CMP_MAX_ADR__W 10 +#define OFDM_FE_CU_CMP_MAX_ADR__M 0x3FF +#define OFDM_FE_CU_CMP_MAX_ADR__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_RE__A 0x2010017 +#define OFDM_FE_CU_CMP_MAX_RE__W 12 +#define OFDM_FE_CU_CMP_MAX_RE__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_IM__A 0x2010018 +#define OFDM_FE_CU_CMP_MAX_IM__W 12 +#define OFDM_FE_CU_CMP_MAX_IM__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_IM__PRE 0x0 + +#define OFDM_FE_CU_BUF_NFC_DEL__A 0x201001F +#define OFDM_FE_CU_BUF_NFC_DEL__W 14 +#define OFDM_FE_CU_BUF_NFC_DEL__M 0x3FFF +#define OFDM_FE_CU_BUF_NFC_DEL__PRE 0x0 + +#define OFDM_FE_CU_CTR_NFC_ICR__A 0x2010020 +#define OFDM_FE_CU_CTR_NFC_ICR__W 5 +#define OFDM_FE_CU_CTR_NFC_ICR__M 0x1F +#define OFDM_FE_CU_CTR_NFC_ICR__PRE 0x1 + +#define OFDM_FE_CU_CTR_NFC_OCR__A 0x2010021 +#define OFDM_FE_CU_CTR_NFC_OCR__W 15 +#define OFDM_FE_CU_CTR_NFC_OCR__M 0x7FFF +#define OFDM_FE_CU_CTR_NFC_OCR__PRE 0x61A8 + +#define OFDM_FE_CU_CTR_NFC_CNT__A 0x2010022 +#define OFDM_FE_CU_CTR_NFC_CNT__W 15 +#define OFDM_FE_CU_CTR_NFC_CNT__M 0x7FFF +#define OFDM_FE_CU_CTR_NFC_CNT__PRE 0x0 + +#define OFDM_FE_CU_CTR_NFC_STS__A 0x2010023 +#define OFDM_FE_CU_CTR_NFC_STS__W 3 +#define OFDM_FE_CU_CTR_NFC_STS__M 0x7 +#define OFDM_FE_CU_CTR_NFC_STS__PRE 0x0 +#define OFDM_FE_CU_CTR_NFC_STS_RUN 0x0 +#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_IMA 0x1 +#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_REA 0x2 +#define OFDM_FE_CU_CTR_NFC_STS_CNT_MAX 0x4 + + +#define OFDM_FE_CU_DIV_NFC_REA__A 0x2010024 +#define OFDM_FE_CU_DIV_NFC_REA__W 14 +#define OFDM_FE_CU_DIV_NFC_REA__M 0x3FFF +#define OFDM_FE_CU_DIV_NFC_REA__PRE 0x0 + +#define OFDM_FE_CU_DIV_NFC_IMA__A 0x2010025 +#define OFDM_FE_CU_DIV_NFC_IMA__W 14 +#define OFDM_FE_CU_DIV_NFC_IMA__M 0x3FFF +#define OFDM_FE_CU_DIV_NFC_IMA__PRE 0x0 + +#define OFDM_FE_CU_FRM_CNT_UPD__A 0x2010026 +#define OFDM_FE_CU_FRM_CNT_UPD__W 15 +#define OFDM_FE_CU_FRM_CNT_UPD__M 0x7FFF +#define OFDM_FE_CU_FRM_CNT_UPD__PRE 0x20FF + +#define OFDM_FE_CU_DIV_NFC_CLP__A 0x2010027 +#define OFDM_FE_CU_DIV_NFC_CLP__W 2 +#define OFDM_FE_CU_DIV_NFC_CLP__M 0x3 +#define OFDM_FE_CU_DIV_NFC_CLP__PRE 0x0 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S11 0x0 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S12 0x1 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S13 0x2 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S14 0x3 + + +#define OFDM_FE_CU_CMP_MAX_32__A 0x2010028 +#define OFDM_FE_CU_CMP_MAX_32__W 12 +#define OFDM_FE_CU_CMP_MAX_32__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_32__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_16__A 0x2010029 +#define OFDM_FE_CU_CMP_MAX_16__W 12 +#define OFDM_FE_CU_CMP_MAX_16__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_16__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_8__A 0x201002A +#define OFDM_FE_CU_CMP_MAX_8__W 12 +#define OFDM_FE_CU_CMP_MAX_8__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_8__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_4__A 0x201002B +#define OFDM_FE_CU_CMP_MAX_4__W 12 +#define OFDM_FE_CU_CMP_MAX_4__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_4__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_32_RE__A 0x201002C +#define OFDM_FE_CU_CMP_SUM_32_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_32_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_32_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_32_IM__A 0x201002D +#define OFDM_FE_CU_CMP_SUM_32_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_32_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_32_IM__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_16_RE__A 0x201002E +#define OFDM_FE_CU_CMP_SUM_16_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_16_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_16_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_16_IM__A 0x201002F +#define OFDM_FE_CU_CMP_SUM_16_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_16_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_16_IM__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_8_RE__A 0x2010030 +#define OFDM_FE_CU_CMP_SUM_8_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_8_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_8_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_8_IM__A 0x2010031 +#define OFDM_FE_CU_CMP_SUM_8_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_8_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_8_IM__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_4_RE__A 0x2010032 +#define OFDM_FE_CU_CMP_SUM_4_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_4_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_4_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_4_IM__A 0x2010033 +#define OFDM_FE_CU_CMP_SUM_4_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_4_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_4_IM__PRE 0x0 + + + +#define OFDM_FE_CU_BUF_RAM__A 0x2020000 + + + +#define OFDM_FE_CU_CMP_RAM__A 0x2030000 + + + + + +#define OFDM_FT_COMM_EXEC__A 0x2400000 +#define OFDM_FT_COMM_EXEC__W 3 +#define OFDM_FT_COMM_EXEC__M 0x7 +#define OFDM_FT_COMM_EXEC__PRE 0x0 +#define OFDM_FT_COMM_EXEC_STOP 0x0 +#define OFDM_FT_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FT_COMM_EXEC_HOLD 0x2 +#define OFDM_FT_COMM_EXEC_STEP 0x3 +#define OFDM_FT_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_FT_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_FT_COMM_STATE__A 0x2400001 +#define OFDM_FT_COMM_STATE__W 16 +#define OFDM_FT_COMM_STATE__M 0xFFFF +#define OFDM_FT_COMM_STATE__PRE 0x0 +#define OFDM_FT_COMM_MB__A 0x2400002 +#define OFDM_FT_COMM_MB__W 16 +#define OFDM_FT_COMM_MB__M 0xFFFF +#define OFDM_FT_COMM_MB__PRE 0x0 + + + +#define OFDM_FT_TOP_COMM_EXEC__A 0x2410000 +#define OFDM_FT_TOP_COMM_EXEC__W 3 +#define OFDM_FT_TOP_COMM_EXEC__M 0x7 +#define OFDM_FT_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_FT_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_FT_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FT_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_FT_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_FT_TOP_COMM_MB__A 0x2410002 +#define OFDM_FT_TOP_COMM_MB__W 2 +#define OFDM_FT_TOP_COMM_MB__M 0x3 +#define OFDM_FT_TOP_COMM_MB__PRE 0x0 +#define OFDM_FT_TOP_COMM_MB_CTL__B 0 +#define OFDM_FT_TOP_COMM_MB_CTL__W 1 +#define OFDM_FT_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_FT_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_FT_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_FT_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_FT_TOP_COMM_MB_OBS__B 1 +#define OFDM_FT_TOP_COMM_MB_OBS__W 1 +#define OFDM_FT_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_FT_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_FT_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_FT_TOP_COMM_MB_OBS_ON 0x2 + + +#define OFDM_FT_TOP_MODE_2K__A 0x2410010 +#define OFDM_FT_TOP_MODE_2K__W 1 +#define OFDM_FT_TOP_MODE_2K__M 0x1 +#define OFDM_FT_TOP_MODE_2K__PRE 0x0 +#define OFDM_FT_TOP_MODE_2K_MODE_8K 0x0 +#define OFDM_FT_TOP_MODE_2K_MODE_2K 0x1 + + +#define OFDM_FT_TOP_NORM_OFF__A 0x2410016 +#define OFDM_FT_TOP_NORM_OFF__W 4 +#define OFDM_FT_TOP_NORM_OFF__M 0xF +#define OFDM_FT_TOP_NORM_OFF__PRE 0x2 + + + +#define OFDM_FT_0TO2_0_RAM__A 0x2420000 + + + +#define OFDM_FT_0TO2_1_RAM__A 0x2430000 + + + +#define OFDM_FT_0TO2_2_RAM__A 0x2440000 + + + +#define OFDM_FT_3TO7_0_RAM__A 0x2450000 + + + +#define OFDM_FT_3TO7_1_RAM__A 0x2460000 + + + + + +#define OFDM_LC_COMM_EXEC__A 0x3800000 +#define OFDM_LC_COMM_EXEC__W 3 +#define OFDM_LC_COMM_EXEC__M 0x7 +#define OFDM_LC_COMM_EXEC__PRE 0x0 +#define OFDM_LC_COMM_EXEC_STOP 0x0 +#define OFDM_LC_COMM_EXEC_ACTIVE 0x1 +#define OFDM_LC_COMM_EXEC_HOLD 0x2 +#define OFDM_LC_COMM_EXEC_STEP 0x3 +#define OFDM_LC_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_LC_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_LC_COMM_STATE__A 0x3800001 +#define OFDM_LC_COMM_STATE__W 16 +#define OFDM_LC_COMM_STATE__M 0xFFFF +#define OFDM_LC_COMM_STATE__PRE 0x0 +#define OFDM_LC_COMM_MB__A 0x3800002 +#define OFDM_LC_COMM_MB__W 16 +#define OFDM_LC_COMM_MB__M 0xFFFF +#define OFDM_LC_COMM_MB__PRE 0x0 +#define OFDM_LC_COMM_INT_REQ__A 0x3800004 +#define OFDM_LC_COMM_INT_REQ__W 16 +#define OFDM_LC_COMM_INT_REQ__M 0xFFFF +#define OFDM_LC_COMM_INT_REQ__PRE 0x0 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__B 6 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__W 1 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__M 0x40 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__PRE 0x0 + +#define OFDM_LC_COMM_INT_STA__A 0x3800005 +#define OFDM_LC_COMM_INT_STA__W 16 +#define OFDM_LC_COMM_INT_STA__M 0xFFFF +#define OFDM_LC_COMM_INT_STA__PRE 0x0 +#define OFDM_LC_COMM_INT_MSK__A 0x3800006 +#define OFDM_LC_COMM_INT_MSK__W 16 +#define OFDM_LC_COMM_INT_MSK__M 0xFFFF +#define OFDM_LC_COMM_INT_MSK__PRE 0x0 +#define OFDM_LC_COMM_INT_STM__A 0x3800007 +#define OFDM_LC_COMM_INT_STM__W 16 +#define OFDM_LC_COMM_INT_STM__M 0xFFFF +#define OFDM_LC_COMM_INT_STM__PRE 0x0 +#define OFDM_LC_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_LC_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_LC_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_LC_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_LC_CT_COMM_EXEC__A 0x3810000 +#define OFDM_LC_CT_COMM_EXEC__W 3 +#define OFDM_LC_CT_COMM_EXEC__M 0x7 +#define OFDM_LC_CT_COMM_EXEC__PRE 0x0 +#define OFDM_LC_CT_COMM_EXEC_STOP 0x0 +#define OFDM_LC_CT_COMM_EXEC_ACTIVE 0x1 +#define OFDM_LC_CT_COMM_EXEC_HOLD 0x2 +#define OFDM_LC_CT_COMM_EXEC_STEP 0x3 + + +#define OFDM_LC_CT_COMM_STATE__A 0x3810001 +#define OFDM_LC_CT_COMM_STATE__W 10 +#define OFDM_LC_CT_COMM_STATE__M 0x3FF +#define OFDM_LC_CT_COMM_STATE__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_REQ__A 0x3810004 +#define OFDM_LC_CT_COMM_INT_REQ__W 1 +#define OFDM_LC_CT_COMM_INT_REQ__M 0x1 +#define OFDM_LC_CT_COMM_INT_REQ__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_STA__A 0x3810005 +#define OFDM_LC_CT_COMM_INT_STA__W 1 +#define OFDM_LC_CT_COMM_INT_STA__M 0x1 +#define OFDM_LC_CT_COMM_INT_STA__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__B 0 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__W 1 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__M 0x1 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__PRE 0x0 + +#define OFDM_LC_CT_COMM_INT_MSK__A 0x3810006 +#define OFDM_LC_CT_COMM_INT_MSK__W 1 +#define OFDM_LC_CT_COMM_INT_MSK__M 0x1 +#define OFDM_LC_CT_COMM_INT_MSK__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__B 0 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__W 1 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__M 0x1 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 + +#define OFDM_LC_CT_COMM_INT_STM__A 0x3810007 +#define OFDM_LC_CT_COMM_INT_STM__W 1 +#define OFDM_LC_CT_COMM_INT_STM__M 0x1 +#define OFDM_LC_CT_COMM_INT_STM__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__B 0 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__W 1 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__M 0x1 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__PRE 0x0 + + +#define OFDM_LC_CT_CTL_STK_0__A 0x3810010 +#define OFDM_LC_CT_CTL_STK_0__W 10 +#define OFDM_LC_CT_CTL_STK_0__M 0x3FF +#define OFDM_LC_CT_CTL_STK_0__PRE 0x0 + +#define OFDM_LC_CT_CTL_STK_1__A 0x3810011 +#define OFDM_LC_CT_CTL_STK_1__W 10 +#define OFDM_LC_CT_CTL_STK_1__M 0x3FF +#define OFDM_LC_CT_CTL_STK_1__PRE 0x0 + +#define OFDM_LC_CT_CTL_STK_2__A 0x3810012 +#define OFDM_LC_CT_CTL_STK_2__W 10 +#define OFDM_LC_CT_CTL_STK_2__M 0x3FF +#define OFDM_LC_CT_CTL_STK_2__PRE 0x0 + +#define OFDM_LC_CT_CTL_STK_3__A 0x3810013 +#define OFDM_LC_CT_CTL_STK_3__W 10 +#define OFDM_LC_CT_CTL_STK_3__M 0x3FF +#define OFDM_LC_CT_CTL_STK_3__PRE 0x0 + +#define OFDM_LC_CT_CTL_BPT_IDX__A 0x381001F +#define OFDM_LC_CT_CTL_BPT_IDX__W 1 +#define OFDM_LC_CT_CTL_BPT_IDX__M 0x1 +#define OFDM_LC_CT_CTL_BPT_IDX__PRE 0x0 + +#define OFDM_LC_CT_CTL_BPT__A 0x3810020 +#define OFDM_LC_CT_CTL_BPT__W 10 +#define OFDM_LC_CT_CTL_BPT__M 0x3FF +#define OFDM_LC_CT_CTL_BPT__PRE 0x0 + + + +#define OFDM_LC_RA_RAM__A 0x3820000 + + + + +#define OFDM_LC_IF_RAM_TRP_BPT0_0__A 0x3830000 +#define OFDM_LC_IF_RAM_TRP_BPT0_0__W 12 +#define OFDM_LC_IF_RAM_TRP_BPT0_0__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_BPT0_0__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_BPT0_1__A 0x3830001 +#define OFDM_LC_IF_RAM_TRP_BPT0_1__W 12 +#define OFDM_LC_IF_RAM_TRP_BPT0_1__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_BPT0_1__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_STKU_0__A 0x3830002 +#define OFDM_LC_IF_RAM_TRP_STKU_0__W 12 +#define OFDM_LC_IF_RAM_TRP_STKU_0__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_STKU_0__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_STKU_1__A 0x3830004 +#define OFDM_LC_IF_RAM_TRP_STKU_1__W 12 +#define OFDM_LC_IF_RAM_TRP_STKU_1__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_STKU_1__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_WARM_0__A 0x3830006 +#define OFDM_LC_IF_RAM_TRP_WARM_0__W 12 +#define OFDM_LC_IF_RAM_TRP_WARM_0__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_WARM_0__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_WARM_1__A 0x3830007 +#define OFDM_LC_IF_RAM_TRP_WARM_1__W 12 +#define OFDM_LC_IF_RAM_TRP_WARM_1__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_WARM_1__PRE 0x0 + + + + + + + +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__A 0x3820006 +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__W 16 +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__A 0x3820007 +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__W 16 +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__A 0x3820008 +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__W 16 +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__A 0x3820009 +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__W 16 +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 +#define OFDM_LC_RA_RAM_LOCK_COUNT__A 0x382000A +#define OFDM_LC_RA_RAM_LOCK_COUNT__W 16 +#define OFDM_LC_RA_RAM_LOCK_COUNT__M 0xFFFF +#define OFDM_LC_RA_RAM_LOCK_COUNT__PRE 0x0 +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__A 0x382000B +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__W 16 +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__PRE 0x0 +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__A 0x382000C +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__W 16 +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__PRE 0x0 +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__A 0x382000D +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__W 16 +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__PRE 0x0 +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__A 0x382000E +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__W 16 +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__PRE 0x0 +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__A 0x382000F +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__W 16 +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_2K__A 0x3820010 +#define OFDM_LC_RA_RAM_MODE_2K__W 16 +#define OFDM_LC_RA_RAM_MODE_2K__M 0xFFFF +#define OFDM_LC_RA_RAM_MODE_2K__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_GUARD__A 0x3820011 +#define OFDM_LC_RA_RAM_MODE_GUARD__W 16 +#define OFDM_LC_RA_RAM_MODE_GUARD__M 0xFFFF +#define OFDM_LC_RA_RAM_MODE_GUARD__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_GUARD_32 0x0 +#define OFDM_LC_RA_RAM_MODE_GUARD_16 0x1 +#define OFDM_LC_RA_RAM_MODE_GUARD_8 0x2 +#define OFDM_LC_RA_RAM_MODE_GUARD_4 0x3 + +#define OFDM_LC_RA_RAM_MODE_ADJUST__A 0x3820012 +#define OFDM_LC_RA_RAM_MODE_ADJUST__W 16 +#define OFDM_LC_RA_RAM_MODE_ADJUST__M 0xFFFF +#define OFDM_LC_RA_RAM_MODE_ADJUST__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__B 12 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__M 0x1000 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__B 13 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__M 0x2000 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__PRE 0x0 + +#define OFDM_LC_RA_RAM_RC_STS__A 0x3820014 +#define OFDM_LC_RA_RAM_RC_STS__W 16 +#define OFDM_LC_RA_RAM_RC_STS__M 0xFFFF +#define OFDM_LC_RA_RAM_RC_STS__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x3820018 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x3820019 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__A 0x382001A +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__W 16 +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__A 0x382001B +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__W 16 +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__A 0x382001C +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__W 16 +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__A 0x382001D +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__W 16 +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x382001F +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x3820020 +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x3820021 +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__A 0x3820022 +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__A 0x3820023 +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_CRMM__A 0x3820024 +#define OFDM_LC_RA_RAM_ADJUST_CRMM__W 16 +#define OFDM_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_SRMM__A 0x3820025 +#define OFDM_LC_RA_RAM_ADJUST_SRMM__W 16 +#define OFDM_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_PHASE__A 0x3820026 +#define OFDM_LC_RA_RAM_ADJUST_PHASE__W 16 +#define OFDM_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_PHASE__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_DELAY__A 0x3820027 +#define OFDM_LC_RA_RAM_ADJUST_DELAY__W 16 +#define OFDM_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_DELAY__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x3820028 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x3820029 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x382002A +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x382002B +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x382002C +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x382002D +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_BACKUP__A 0x382002E +#define OFDM_LC_RA_RAM_FILTER_BACKUP__W 16 +#define OFDM_LC_RA_RAM_FILTER_BACKUP__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_BACKUP__PRE 0x4 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x3820030 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x3820031 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x3820032 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x3820033 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x3820034 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x3820035 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x3820038 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x3820039 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x382003A +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x382003B +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x382003C +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x382003D +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__A 0x3820060 +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__PRE 0x7 +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__A 0x3820061 +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__PRE 0x2 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__A 0x3820062 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__A 0x3820063 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__A 0x3820064 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__A 0x3820065 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__A 0x3820066 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__A 0x3820067 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__A 0x3820068 +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__A 0x3820069 +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__A 0x382006A +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__A 0x382006B +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__A 0x382006C +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__A 0x382006D +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__A 0x382006E +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__A 0x382006F +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__A 0x3820070 +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__A 0x3820071 +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__A 0x3820072 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__A 0x3820073 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__A 0x3820074 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__A 0x3820075 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__A 0x3820076 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__A 0x3820077 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__A 0x3820078 +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__A 0x3820079 +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__A 0x382007A +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__A 0x382007B +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__A 0x382007C +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__A 0x382007D +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__A 0x382007E +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__A 0x382007F +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__PRE 0x0 + + + + + +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__W 3 +#define OFDM_SC_COMM_EXEC__M 0x7 +#define OFDM_SC_COMM_EXEC__PRE 0x0 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC_ACTIVE 0x1 +#define OFDM_SC_COMM_EXEC_HOLD 0x2 +#define OFDM_SC_COMM_EXEC_STEP 0x3 +#define OFDM_SC_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_SC_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_SC_COMM_STATE__A 0x3C00001 +#define OFDM_SC_COMM_STATE__W 16 +#define OFDM_SC_COMM_STATE__M 0xFFFF +#define OFDM_SC_COMM_STATE__PRE 0x0 +#define OFDM_SC_COMM_MB__A 0x3C00002 +#define OFDM_SC_COMM_MB__W 16 +#define OFDM_SC_COMM_MB__M 0xFFFF +#define OFDM_SC_COMM_MB__PRE 0x0 +#define OFDM_SC_COMM_INT_REQ__A 0x3C00004 +#define OFDM_SC_COMM_INT_REQ__W 16 +#define OFDM_SC_COMM_INT_REQ__M 0xFFFF +#define OFDM_SC_COMM_INT_REQ__PRE 0x0 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__B 7 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__W 1 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__M 0x80 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__PRE 0x0 + +#define OFDM_SC_COMM_INT_STA__A 0x3C00005 +#define OFDM_SC_COMM_INT_STA__W 16 +#define OFDM_SC_COMM_INT_STA__M 0xFFFF +#define OFDM_SC_COMM_INT_STA__PRE 0x0 +#define OFDM_SC_COMM_INT_MSK__A 0x3C00006 +#define OFDM_SC_COMM_INT_MSK__W 16 +#define OFDM_SC_COMM_INT_MSK__M 0xFFFF +#define OFDM_SC_COMM_INT_MSK__PRE 0x0 +#define OFDM_SC_COMM_INT_STM__A 0x3C00007 +#define OFDM_SC_COMM_INT_STM__W 16 +#define OFDM_SC_COMM_INT_STM__M 0xFFFF +#define OFDM_SC_COMM_INT_STM__PRE 0x0 +#define OFDM_SC_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_SC_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_SC_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_SC_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_SC_CT_COMM_EXEC__A 0x3C10000 +#define OFDM_SC_CT_COMM_EXEC__W 3 +#define OFDM_SC_CT_COMM_EXEC__M 0x7 +#define OFDM_SC_CT_COMM_EXEC__PRE 0x0 +#define OFDM_SC_CT_COMM_EXEC_STOP 0x0 +#define OFDM_SC_CT_COMM_EXEC_ACTIVE 0x1 +#define OFDM_SC_CT_COMM_EXEC_HOLD 0x2 +#define OFDM_SC_CT_COMM_EXEC_STEP 0x3 + + +#define OFDM_SC_CT_COMM_STATE__A 0x3C10001 +#define OFDM_SC_CT_COMM_STATE__W 10 +#define OFDM_SC_CT_COMM_STATE__M 0x3FF +#define OFDM_SC_CT_COMM_STATE__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_REQ__A 0x3C10004 +#define OFDM_SC_CT_COMM_INT_REQ__W 1 +#define OFDM_SC_CT_COMM_INT_REQ__M 0x1 +#define OFDM_SC_CT_COMM_INT_REQ__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_STA__A 0x3C10005 +#define OFDM_SC_CT_COMM_INT_STA__W 1 +#define OFDM_SC_CT_COMM_INT_STA__M 0x1 +#define OFDM_SC_CT_COMM_INT_STA__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__B 0 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__W 1 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__M 0x1 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__PRE 0x0 + +#define OFDM_SC_CT_COMM_INT_MSK__A 0x3C10006 +#define OFDM_SC_CT_COMM_INT_MSK__W 1 +#define OFDM_SC_CT_COMM_INT_MSK__M 0x1 +#define OFDM_SC_CT_COMM_INT_MSK__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__B 0 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__W 1 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__M 0x1 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 + +#define OFDM_SC_CT_COMM_INT_STM__A 0x3C10007 +#define OFDM_SC_CT_COMM_INT_STM__W 1 +#define OFDM_SC_CT_COMM_INT_STM__M 0x1 +#define OFDM_SC_CT_COMM_INT_STM__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__B 0 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__W 1 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__M 0x1 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__PRE 0x0 + + +#define OFDM_SC_CT_CTL_STK_0__A 0x3C10010 +#define OFDM_SC_CT_CTL_STK_0__W 10 +#define OFDM_SC_CT_CTL_STK_0__M 0x3FF +#define OFDM_SC_CT_CTL_STK_0__PRE 0x0 + +#define OFDM_SC_CT_CTL_STK_1__A 0x3C10011 +#define OFDM_SC_CT_CTL_STK_1__W 10 +#define OFDM_SC_CT_CTL_STK_1__M 0x3FF +#define OFDM_SC_CT_CTL_STK_1__PRE 0x0 + +#define OFDM_SC_CT_CTL_STK_2__A 0x3C10012 +#define OFDM_SC_CT_CTL_STK_2__W 10 +#define OFDM_SC_CT_CTL_STK_2__M 0x3FF +#define OFDM_SC_CT_CTL_STK_2__PRE 0x0 + +#define OFDM_SC_CT_CTL_STK_3__A 0x3C10013 +#define OFDM_SC_CT_CTL_STK_3__W 10 +#define OFDM_SC_CT_CTL_STK_3__M 0x3FF +#define OFDM_SC_CT_CTL_STK_3__PRE 0x0 + +#define OFDM_SC_CT_CTL_BPT_IDX__A 0x3C1001F +#define OFDM_SC_CT_CTL_BPT_IDX__W 1 +#define OFDM_SC_CT_CTL_BPT_IDX__M 0x1 +#define OFDM_SC_CT_CTL_BPT_IDX__PRE 0x0 + +#define OFDM_SC_CT_CTL_BPT__A 0x3C10020 +#define OFDM_SC_CT_CTL_BPT__W 13 +#define OFDM_SC_CT_CTL_BPT__M 0x1FFF +#define OFDM_SC_CT_CTL_BPT__PRE 0x0 + + + +#define OFDM_SC_RA_RAM__A 0x3C20000 + + + + +#define OFDM_SC_IF_RAM_TRP_RST_0__A 0x3C30000 +#define OFDM_SC_IF_RAM_TRP_RST_0__W 12 +#define OFDM_SC_IF_RAM_TRP_RST_0__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_RST_0__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_RST_1__A 0x3C30001 +#define OFDM_SC_IF_RAM_TRP_RST_1__W 12 +#define OFDM_SC_IF_RAM_TRP_RST_1__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_RST_1__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_BPT0_0__A 0x3C30002 +#define OFDM_SC_IF_RAM_TRP_BPT0_0__W 12 +#define OFDM_SC_IF_RAM_TRP_BPT0_0__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_BPT0_0__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_BPT0_1__A 0x3C30004 +#define OFDM_SC_IF_RAM_TRP_BPT0_1__W 12 +#define OFDM_SC_IF_RAM_TRP_BPT0_1__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_BPT0_1__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_STKU_0__A 0x3C30004 +#define OFDM_SC_IF_RAM_TRP_STKU_0__W 12 +#define OFDM_SC_IF_RAM_TRP_STKU_0__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_STKU_0__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_STKU_1__A 0x3C30005 +#define OFDM_SC_IF_RAM_TRP_STKU_1__W 12 +#define OFDM_SC_IF_RAM_TRP_STKU_1__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_STKU_1__PRE 0x0 + +#define OFDM_SC_IF_RAM_VERSION_MA_MI__A 0x3C30FFE +#define OFDM_SC_IF_RAM_VERSION_MA_MI__W 12 +#define OFDM_SC_IF_RAM_VERSION_MA_MI__M 0xFFF +#define OFDM_SC_IF_RAM_VERSION_MA_MI__PRE 0x0 + +#define OFDM_SC_IF_RAM_VERSION_PATCH__A 0x3C30FFF +#define OFDM_SC_IF_RAM_VERSION_PATCH__W 12 +#define OFDM_SC_IF_RAM_VERSION_PATCH__M 0xFFF +#define OFDM_SC_IF_RAM_VERSION_PATCH__PRE 0x0 + + + + + + + +#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 +#define OFDM_SC_RA_RAM_PARAM0__W 16 +#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 +#define OFDM_SC_RA_RAM_PARAM1__W 16 +#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 +#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 +#define OFDM_SC_RA_RAM_CMD_ADDR__W 16 +#define OFDM_SC_RA_RAM_CMD_ADDR__M 0xFFFF +#define OFDM_SC_RA_RAM_CMD_ADDR__PRE 0x0 +#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 +#define OFDM_SC_RA_RAM_CMD__W 16 +#define OFDM_SC_RA_RAM_CMD__M 0xFFFF +#define OFDM_SC_RA_RAM_CMD__PRE 0x0 +#define OFDM_SC_RA_RAM_CMD_NULL 0x0 +#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 +#define OFDM_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 +#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 +#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 +#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 +#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 +#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 +#define OFDM_SC_RA_RAM_CMD_MAX 0x9 +#define OFDM_SC_RA_RAM_CMD_LOCK__C 0x4 + +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__A 0x3C20044 +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__W 16 +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF +#define OFDM_SC_RA_RAM_PROC_TERMINATED__A 0x3C20045 +#define OFDM_SC_RA_RAM_PROC_TERMINATED__W 16 +#define OFDM_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF +#define OFDM_SC_RA_RAM_PROC_TERMINATED__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT__A 0x3C20046 +#define OFDM_SC_RA_RAM_SW_EVENT__W 14 +#define OFDM_SC_RA_RAM_SW_EVENT__M 0x3FFF +#define OFDM_SC_RA_RAM_SW_EVENT__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__B 1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__M 0x2 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__B 3 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__B 4 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__B 7 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__B 8 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__B 9 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__B 12 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__PRE 0x0 + +#define OFDM_SC_RA_RAM_LOCKTRACK__A 0x3C20047 +#define OFDM_SC_RA_RAM_LOCKTRACK__W 16 +#define OFDM_SC_RA_RAM_LOCKTRACK__M 0xFFFF +#define OFDM_SC_RA_RAM_LOCKTRACK__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCKTRACK_NULL 0x0 +#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 +#define OFDM_SC_RA_RAM_LOCKTRACK_RESET 0x1 +#define OFDM_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 +#define OFDM_SC_RA_RAM_LOCKTRACK_SRMM_FIX 0x3 +#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT 0x4 +#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x5 +#define OFDM_SC_RA_RAM_LOCKTRACK_LC 0x6 +#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK 0x7 +#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0x8 +#define OFDM_SC_RA_RAM_LOCKTRACK_MAX 0x9 + +#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 +#define OFDM_SC_RA_RAM_OP_PARAM__W 13 +#define OFDM_SC_RA_RAM_OP_PARAM__M 0x1FFF +#define OFDM_SC_RA_RAM_OP_PARAM__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__B 4 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__M 0x30 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__B 6 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__W 3 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__B 12 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__W 1 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 + +#define OFDM_SC_RA_RAM_OP_AUTO__A 0x3C20049 +#define OFDM_SC_RA_RAM_OP_AUTO__W 6 +#define OFDM_SC_RA_RAM_OP_AUTO__M 0x3F +#define OFDM_SC_RA_RAM_OP_AUTO__PRE 0x1F +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__B 0 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__PRE 0x1 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__B 1 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__PRE 0x2 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__B 2 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__PRE 0x4 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__B 3 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__PRE 0x8 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__B 4 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__PRE 0x10 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__B 5 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__PRE 0x0 + +#define OFDM_SC_RA_RAM_PILOT_STATUS__A 0x3C2004A +#define OFDM_SC_RA_RAM_PILOT_STATUS__W 16 +#define OFDM_SC_RA_RAM_PILOT_STATUS__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_STATUS__PRE 0x0 +#define OFDM_SC_RA_RAM_PILOT_STATUS_OK 0x0 +#define OFDM_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 +#define OFDM_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 +#define OFDM_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 + +#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B +#define OFDM_SC_RA_RAM_LOCK__W 4 +#define OFDM_SC_RA_RAM_LOCK__M 0xF +#define OFDM_SC_RA_RAM_LOCK__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__B 0 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__W 1 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_FEC__B 1 +#define OFDM_SC_RA_RAM_LOCK_FEC__W 1 +#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 +#define OFDM_SC_RA_RAM_LOCK_FEC__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_MPEG__B 2 +#define OFDM_SC_RA_RAM_LOCK_MPEG__W 1 +#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 +#define OFDM_SC_RA_RAM_LOCK_MPEG__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__B 3 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__W 1 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__PRE 0x0 + +#define OFDM_SC_RA_RAM_BE_OPT_ENA__A 0x3C2004C +#define OFDM_SC_RA_RAM_BE_OPT_ENA__W 5 +#define OFDM_SC_RA_RAM_BE_OPT_ENA__M 0x1F +#define OFDM_SC_RA_RAM_BE_OPT_ENA__PRE 0x1C +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__B 0 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__M 0x1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__PRE 0x0 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__B 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__M 0x2 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__PRE 0x0 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__B 2 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__M 0x4 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__PRE 0x4 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__B 3 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__M 0x8 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__PRE 0x8 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__B 4 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__M 0x10 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__PRE 0x10 + +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__W 16 +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__PRE 0x80 +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 +#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F +#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 +#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 + +#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 +#define OFDM_SC_RA_RAM_CONFIG__W 16 +#define OFDM_SC_RA_RAM_CONFIG__M 0xFFFF +#define OFDM_SC_RA_RAM_CONFIG__PRE 0x14 +#define OFDM_SC_RA_RAM_CONFIG_ID__B 0 +#define OFDM_SC_RA_RAM_CONFIG_ID__W 1 +#define OFDM_SC_RA_RAM_CONFIG_ID__M 0x1 +#define OFDM_SC_RA_RAM_CONFIG_ID__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ID_ID_PRO 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ID_ID_CONSUMER 0x1 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__PRE 0x4 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__B 3 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__B 4 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__PRE 0x10 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__B 5 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__M 0x20 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__B 6 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__B 11 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__PRE 0x0 + +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x3C20054 +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__A 0x3C20055 +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__W 16 +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__A 0x3C20056 +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__W 16 +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x3C20057 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__A 0x3C20058 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__W 16 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__A 0x3C20059 +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__W 16 +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__A 0x3C2005A +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__W 16 +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x1 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x3C2005B +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__A 0x3C2005C +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__W 16 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x1 +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__A 0x3C2005D +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__W 16 +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__A 0x3C2005E +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__W 16 +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 +#define OFDM_SC_RA_RAM_MOTION_OFFSET__A 0x3C2005F +#define OFDM_SC_RA_RAM_MOTION_OFFSET__W 16 +#define OFDM_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF +#define OFDM_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__A 0x3C20060 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__A 0x3C20061 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x330 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__A 0x3C20062 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x0 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__A 0x3C20063 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x4 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__A 0x3C20064 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__A 0x3C20065 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x80 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__A 0x3C20066 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__A 0x3C20067 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0xFFFE +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__A 0x3C2006E +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__W 16 +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__PRE 0x1 +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__A 0x3C2006F +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__W 16 +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__PRE 0x320 +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__A 0x3C20070 +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__A 0x3C20071 +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__A 0x3C20072 +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__PRE 0x40 +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__A 0x3C20073 +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__A 0x3C20074 +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__A 0x3C20075 +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__PRE 0x780 +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__A 0x3C20076 +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__PRE 0x230 +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__A 0x3C20077 +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 +#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C +#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 +#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 +#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D +#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 +#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C +#define OFDM_SC_RA_RAM_STATUS__A 0x3C2007E +#define OFDM_SC_RA_RAM_STATUS__W 16 +#define OFDM_SC_RA_RAM_STATUS__M 0xFFFF +#define OFDM_SC_RA_RAM_STATUS__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__A 0x3C2007F +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__W 16 +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 +#define OFDM_SC_RA_RAM_TIMER__A 0x3C20080 +#define OFDM_SC_RA_RAM_TIMER__W 16 +#define OFDM_SC_RA_RAM_TIMER__M 0xFFFF +#define OFDM_SC_RA_RAM_TIMER__PRE 0x0 +#define OFDM_SC_RA_RAM_FI_OFFSET__A 0x3C20081 +#define OFDM_SC_RA_RAM_FI_OFFSET__W 16 +#define OFDM_SC_RA_RAM_FI_OFFSET__M 0xFFFF +#define OFDM_SC_RA_RAM_FI_OFFSET__PRE 0x382 +#define OFDM_SC_RA_RAM_ECHO_GUARD__A 0x3C20082 +#define OFDM_SC_RA_RAM_ECHO_GUARD__W 16 +#define OFDM_SC_RA_RAM_ECHO_GUARD__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_GUARD__PRE 0x18 +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__A 0x3C2008D +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__W 16 +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__M 0xFFFF +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__PRE 0x640 +#define OFDM_SC_RA_RAM_IF_SAVE_0__A 0x3C2008E +#define OFDM_SC_RA_RAM_IF_SAVE_0__W 16 +#define OFDM_SC_RA_RAM_IF_SAVE_0__M 0xFFFF +#define OFDM_SC_RA_RAM_IF_SAVE_0__PRE 0x0 +#define OFDM_SC_RA_RAM_IF_SAVE_1__A 0x3C2008F +#define OFDM_SC_RA_RAM_IF_SAVE_1__W 16 +#define OFDM_SC_RA_RAM_IF_SAVE_1__M 0xFFFF +#define OFDM_SC_RA_RAM_IF_SAVE_1__PRE 0x0 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x3C20098 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x3C20099 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x3C2009A +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x3C2009B +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x3C2009C +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x3C2009D +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x3C2009E +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x3C2009F +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__A 0x3C200B2 +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__W 16 +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__M 0xFFFF +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__PRE 0xC8 +#define OFDM_SC_RA_RAM_MG_VALID_THRES__A 0x3C200B7 +#define OFDM_SC_RA_RAM_MG_VALID_THRES__W 16 +#define OFDM_SC_RA_RAM_MG_VALID_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_MG_VALID_THRES__PRE 0x230 +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__A 0x3C200B8 +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__W 16 +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__PRE 0x320 +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__A 0x3C200B9 +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__W 16 +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__PRE 0x32 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__A 0x3C200BA +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__PRE 0x443 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__B 0 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__W 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__M 0x1F +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__PRE 0x3 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__B 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__W 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__M 0x3E0 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__PRE 0x40 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__B 10 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__W 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__M 0x7C00 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__PRE 0x400 + +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__A 0x3C200BB +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__PRE 0x3 +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__A 0x3C200BC +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__W 16 +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__PRE 0x6 +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__A 0x3C200BD +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__W 16 +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__PRE 0x28 +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__A 0x3C200BE +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__PRE 0x6 +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__A 0x3C200BF +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__PRE 0x14 +#define OFDM_SC_RA_RAM_IR_FREQ__A 0x3C200D0 +#define OFDM_SC_RA_RAM_IR_FREQ__W 16 +#define OFDM_SC_RA_RAM_IR_FREQ__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FREQ__PRE 0x0 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x3C200D1 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x3C200D2 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x3C200D3 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x3C200D4 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x9 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x3C200D5 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x4 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x3C200D6 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x100 +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x3C200D7 +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x3C200D8 +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x3C200D9 +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x3C200DA +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x3C200DB +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x3C200DC +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x3C200DD +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__A 0x3C200DE +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__W 16 +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x3C200DF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0x14C0 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__PRE 0xC0 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__PRE 0x1400 + +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__A 0x3C200E7 +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__W 16 +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__PRE 0x4E2 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x3C200E8 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x3C200E9 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x3C200EA +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__A 0x3C200EB +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__W 16 +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND__A 0x3C200EC +#define OFDM_SC_RA_RAM_BAND__W 16 +#define OFDM_SC_RA_RAM_BAND__M 0xFFFF +#define OFDM_SC_RA_RAM_BAND__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL__B 0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL__W 4 +#define OFDM_SC_RA_RAM_BAND_INTERVAL__M 0xF +#define OFDM_SC_RA_RAM_BAND_INTERVAL__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__PRE 0x0 + +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x3C200ED +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__A 0x3C200EE +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__W 16 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__PRE 0x19 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__A 0x3C200EF +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__W 16 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__PRE 0x1B +#define OFDM_SC_RA_RAM_REG_0__A 0x3C200F0 +#define OFDM_SC_RA_RAM_REG_0__W 16 +#define OFDM_SC_RA_RAM_REG_0__M 0xFFFF +#define OFDM_SC_RA_RAM_REG_0__PRE 0x0 +#define OFDM_SC_RA_RAM_REG_1__A 0x3C200F1 +#define OFDM_SC_RA_RAM_REG_1__W 16 +#define OFDM_SC_RA_RAM_REG_1__M 0xFFFF +#define OFDM_SC_RA_RAM_REG_1__PRE 0x0 +#define OFDM_SC_RA_RAM_BREAK__A 0x3C200F2 +#define OFDM_SC_RA_RAM_BREAK__W 16 +#define OFDM_SC_RA_RAM_BREAK__M 0xFFFF +#define OFDM_SC_RA_RAM_BREAK__PRE 0x0 +#define OFDM_SC_RA_RAM_BOOTCOUNT__A 0x3C200F3 +#define OFDM_SC_RA_RAM_BOOTCOUNT__W 16 +#define OFDM_SC_RA_RAM_BOOTCOUNT__M 0xFFFF +#define OFDM_SC_RA_RAM_BOOTCOUNT__PRE 0x0 +#define OFDM_SC_RA_RAM_LC_ABS_2K__A 0x3C200F4 +#define OFDM_SC_RA_RAM_LC_ABS_2K__W 16 +#define OFDM_SC_RA_RAM_LC_ABS_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_ABS_2K__PRE 0x1F +#define OFDM_SC_RA_RAM_LC_ABS_8K__A 0x3C200F5 +#define OFDM_SC_RA_RAM_LC_ABS_8K__W 16 +#define OFDM_SC_RA_RAM_LC_ABS_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_ABS_8K__PRE 0x1F +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__A 0x3C200F6 +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__W 16 +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__M 0xFFFF +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__PRE 0x1 +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x3C200F7 +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F + +#define OFDM_SC_RA_RAM_LC_CP__A 0x3C200F9 +#define OFDM_SC_RA_RAM_LC_CP__W 16 +#define OFDM_SC_RA_RAM_LC_CP__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_CP__PRE 0x1 +#define OFDM_SC_RA_RAM_LC_DIFF__A 0x3C200FA +#define OFDM_SC_RA_RAM_LC_DIFF__W 16 +#define OFDM_SC_RA_RAM_LC_DIFF__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_DIFF__PRE 0x7 +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__A 0x3C200FB +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__W 16 +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__PRE 0x1B58 +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__A 0x3C200FC +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__W 16 +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__PRE 0x0 + +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__A 0x3C200FD +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__W 16 +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__PRE 0xFF38 +#define OFDM_SC_RA_RAM_RELOCK__A 0x3C200FE +#define OFDM_SC_RA_RAM_RELOCK__W 16 +#define OFDM_SC_RA_RAM_RELOCK__M 0xFFFF +#define OFDM_SC_RA_RAM_RELOCK__PRE 0x0 +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__A 0x3C200FF +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__W 16 +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x3C20148 +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_PREPOST__A 0x3C20149 +#define OFDM_SC_RA_RAM_NF_PREPOST__W 16 +#define OFDM_SC_RA_RAM_NF_PREPOST__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_PREPOST__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_PREBORDER__A 0x3C2014A +#define OFDM_SC_RA_RAM_NF_PREBORDER__W 16 +#define OFDM_SC_RA_RAM_NF_PREBORDER__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_PREBORDER__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_START__A 0x3C2014B +#define OFDM_SC_RA_RAM_NF_START__W 16 +#define OFDM_SC_RA_RAM_NF_START__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_START__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_MINISI_0__A 0x3C2014C +#define OFDM_SC_RA_RAM_NF_MINISI_0__W 16 +#define OFDM_SC_RA_RAM_NF_MINISI_0__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_MINISI_0__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_MINISI_1__A 0x3C2014D +#define OFDM_SC_RA_RAM_NF_MINISI_1__W 16 +#define OFDM_SC_RA_RAM_NF_MINISI_1__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_MINISI_1__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_NRECHOES__A 0x3C2014F +#define OFDM_SC_RA_RAM_NF_NRECHOES__W 16 +#define OFDM_SC_RA_RAM_NF_NRECHOES__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_NRECHOES__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__A 0x3C20150 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__A 0x3C20151 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__A 0x3C20152 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__A 0x3C20153 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__A 0x3C20154 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__A 0x3C20155 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__A 0x3C20156 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__A 0x3C20157 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__A 0x3C20158 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__A 0x3C20159 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__A 0x3C2015A +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__A 0x3C2015B +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__A 0x3C2015C +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__A 0x3C2015D +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__A 0x3C2015E +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__A 0x3C2015F +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__PRE 0x0 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x3C201A0 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x3C201A1 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x3C201A2 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x3C201A3 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x3C201A4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x3C201A5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x3C201A6 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x3C201A7 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x3C201A8 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x3C201A9 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x3C201AA +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x3C201AB +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x3C201AC +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x3C201AD +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x3C201AE +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x3C201AF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__A 0x3C201FE +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__W 16 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__M 0xFFFF +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__PRE 0x0 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__A 0x3C201FF +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__W 16 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__M 0xFFFF +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__PRE 0x0 + + + + + +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__W 2 +#define QAM_COMM_EXEC__M 0x3 +#define QAM_COMM_EXEC__PRE 0x0 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC_ACTIVE 0x1 +#define QAM_COMM_EXEC_HOLD 0x2 + +#define QAM_COMM_MB__A 0x1400002 +#define QAM_COMM_MB__W 16 +#define QAM_COMM_MB__M 0xFFFF +#define QAM_COMM_MB__PRE 0x0 +#define QAM_COMM_INT_REQ__A 0x1400003 +#define QAM_COMM_INT_REQ__W 16 +#define QAM_COMM_INT_REQ__M 0xFFFF +#define QAM_COMM_INT_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SL_REQ__B 0 +#define QAM_COMM_INT_REQ_SL_REQ__W 1 +#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 +#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_LC_REQ__B 1 +#define QAM_COMM_INT_REQ_LC_REQ__W 1 +#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 +#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_VD_REQ__B 2 +#define QAM_COMM_INT_REQ_VD_REQ__W 1 +#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 +#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SY_REQ__B 3 +#define QAM_COMM_INT_REQ_SY_REQ__W 1 +#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 +#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 + +#define QAM_COMM_INT_STA__A 0x1400005 +#define QAM_COMM_INT_STA__W 16 +#define QAM_COMM_INT_STA__M 0xFFFF +#define QAM_COMM_INT_STA__PRE 0x0 +#define QAM_COMM_INT_MSK__A 0x1400006 +#define QAM_COMM_INT_MSK__W 16 +#define QAM_COMM_INT_MSK__M 0xFFFF +#define QAM_COMM_INT_MSK__PRE 0x0 +#define QAM_COMM_INT_STM__A 0x1400007 +#define QAM_COMM_INT_STM__W 16 +#define QAM_COMM_INT_STM__M 0xFFFF +#define QAM_COMM_INT_STM__PRE 0x0 + + + +#define QAM_TOP_COMM_EXEC__A 0x1410000 +#define QAM_TOP_COMM_EXEC__W 2 +#define QAM_TOP_COMM_EXEC__M 0x3 +#define QAM_TOP_COMM_EXEC__PRE 0x0 +#define QAM_TOP_COMM_EXEC_STOP 0x0 +#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 +#define QAM_TOP_COMM_EXEC_HOLD 0x2 + + +#define QAM_TOP_ANNEX__A 0x1410010 +#define QAM_TOP_ANNEX__W 2 +#define QAM_TOP_ANNEX__M 0x3 +#define QAM_TOP_ANNEX__PRE 0x0 +#define QAM_TOP_ANNEX_A 0x0 +#define QAM_TOP_ANNEX_B 0x1 +#define QAM_TOP_ANNEX_C 0x2 +#define QAM_TOP_ANNEX_D 0x3 + + +#define QAM_TOP_CONSTELLATION__A 0x1410011 +#define QAM_TOP_CONSTELLATION__W 3 +#define QAM_TOP_CONSTELLATION__M 0x7 +#define QAM_TOP_CONSTELLATION__PRE 0x5 +#define QAM_TOP_CONSTELLATION_NONE 0x0 +#define QAM_TOP_CONSTELLATION_QPSK 0x1 +#define QAM_TOP_CONSTELLATION_QAM8 0x2 +#define QAM_TOP_CONSTELLATION_QAM16 0x3 +#define QAM_TOP_CONSTELLATION_QAM32 0x4 +#define QAM_TOP_CONSTELLATION_QAM64 0x5 +#define QAM_TOP_CONSTELLATION_QAM128 0x6 +#define QAM_TOP_CONSTELLATION_QAM256 0x7 + + + +#define QAM_FQ_COMM_EXEC__A 0x1420000 +#define QAM_FQ_COMM_EXEC__W 2 +#define QAM_FQ_COMM_EXEC__M 0x3 +#define QAM_FQ_COMM_EXEC__PRE 0x0 +#define QAM_FQ_COMM_EXEC_STOP 0x0 +#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_FQ_COMM_EXEC_HOLD 0x2 + +#define QAM_FQ_MODE__A 0x1420010 +#define QAM_FQ_MODE__W 3 +#define QAM_FQ_MODE__M 0x7 +#define QAM_FQ_MODE__PRE 0x0 + +#define QAM_FQ_MODE_TAPRESET__B 0 +#define QAM_FQ_MODE_TAPRESET__W 1 +#define QAM_FQ_MODE_TAPRESET__M 0x1 +#define QAM_FQ_MODE_TAPRESET__PRE 0x0 +#define QAM_FQ_MODE_TAPRESET_RST 0x1 + +#define QAM_FQ_MODE_TAPLMS__B 1 +#define QAM_FQ_MODE_TAPLMS__W 1 +#define QAM_FQ_MODE_TAPLMS__M 0x2 +#define QAM_FQ_MODE_TAPLMS__PRE 0x0 +#define QAM_FQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_FQ_MODE_TAPDRAIN__B 2 +#define QAM_FQ_MODE_TAPDRAIN__W 1 +#define QAM_FQ_MODE_TAPDRAIN__M 0x4 +#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 + + +#define QAM_FQ_MU_FACTOR__A 0x1420011 +#define QAM_FQ_MU_FACTOR__W 3 +#define QAM_FQ_MU_FACTOR__M 0x7 +#define QAM_FQ_MU_FACTOR__PRE 0x0 + +#define QAM_FQ_LA_FACTOR__A 0x1420012 +#define QAM_FQ_LA_FACTOR__W 4 +#define QAM_FQ_LA_FACTOR__M 0xF +#define QAM_FQ_LA_FACTOR__PRE 0xC +#define QAM_FQ_CENTTAP_IDX__A 0x1420016 +#define QAM_FQ_CENTTAP_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_IDX_IDX__B 0 +#define QAM_FQ_CENTTAP_IDX_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 +#define QAM_FQ_CENTTAP_VALUE__W 12 +#define QAM_FQ_CENTTAP_VALUE__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 + +#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 +#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 +#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL0__A 0x1420020 +#define QAM_FQ_TAP_RE_EL0__W 12 +#define QAM_FQ_TAP_RE_EL0__M 0xFFF +#define QAM_FQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL0_TAP__B 0 +#define QAM_FQ_TAP_RE_EL0_TAP__W 12 +#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0__A 0x1420021 +#define QAM_FQ_TAP_IM_EL0__W 12 +#define QAM_FQ_TAP_IM_EL0__M 0xFFF +#define QAM_FQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0_TAP__B 0 +#define QAM_FQ_TAP_IM_EL0_TAP__W 12 +#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1__A 0x1420022 +#define QAM_FQ_TAP_RE_EL1__W 12 +#define QAM_FQ_TAP_RE_EL1__M 0xFFF +#define QAM_FQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1_TAP__B 0 +#define QAM_FQ_TAP_RE_EL1_TAP__W 12 +#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1__A 0x1420023 +#define QAM_FQ_TAP_IM_EL1__W 12 +#define QAM_FQ_TAP_IM_EL1__M 0xFFF +#define QAM_FQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1_TAP__B 0 +#define QAM_FQ_TAP_IM_EL1_TAP__W 12 +#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2__A 0x1420024 +#define QAM_FQ_TAP_RE_EL2__W 12 +#define QAM_FQ_TAP_RE_EL2__M 0xFFF +#define QAM_FQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2_TAP__B 0 +#define QAM_FQ_TAP_RE_EL2_TAP__W 12 +#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2__A 0x1420025 +#define QAM_FQ_TAP_IM_EL2__W 12 +#define QAM_FQ_TAP_IM_EL2__M 0xFFF +#define QAM_FQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2_TAP__B 0 +#define QAM_FQ_TAP_IM_EL2_TAP__W 12 +#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3__A 0x1420026 +#define QAM_FQ_TAP_RE_EL3__W 12 +#define QAM_FQ_TAP_RE_EL3__M 0xFFF +#define QAM_FQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3_TAP__B 0 +#define QAM_FQ_TAP_RE_EL3_TAP__W 12 +#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3__A 0x1420027 +#define QAM_FQ_TAP_IM_EL3__W 12 +#define QAM_FQ_TAP_IM_EL3__M 0xFFF +#define QAM_FQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3_TAP__B 0 +#define QAM_FQ_TAP_IM_EL3_TAP__W 12 +#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4__A 0x1420028 +#define QAM_FQ_TAP_RE_EL4__W 12 +#define QAM_FQ_TAP_RE_EL4__M 0xFFF +#define QAM_FQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4_TAP__B 0 +#define QAM_FQ_TAP_RE_EL4_TAP__W 12 +#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4__A 0x1420029 +#define QAM_FQ_TAP_IM_EL4__W 12 +#define QAM_FQ_TAP_IM_EL4__M 0xFFF +#define QAM_FQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4_TAP__B 0 +#define QAM_FQ_TAP_IM_EL4_TAP__W 12 +#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5__A 0x142002A +#define QAM_FQ_TAP_RE_EL5__W 12 +#define QAM_FQ_TAP_RE_EL5__M 0xFFF +#define QAM_FQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5_TAP__B 0 +#define QAM_FQ_TAP_RE_EL5_TAP__W 12 +#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5__A 0x142002B +#define QAM_FQ_TAP_IM_EL5__W 12 +#define QAM_FQ_TAP_IM_EL5__M 0xFFF +#define QAM_FQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5_TAP__B 0 +#define QAM_FQ_TAP_IM_EL5_TAP__W 12 +#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6__A 0x142002C +#define QAM_FQ_TAP_RE_EL6__W 12 +#define QAM_FQ_TAP_RE_EL6__M 0xFFF +#define QAM_FQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6_TAP__B 0 +#define QAM_FQ_TAP_RE_EL6_TAP__W 12 +#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6__A 0x142002D +#define QAM_FQ_TAP_IM_EL6__W 12 +#define QAM_FQ_TAP_IM_EL6__M 0xFFF +#define QAM_FQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6_TAP__B 0 +#define QAM_FQ_TAP_IM_EL6_TAP__W 12 +#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7__A 0x142002E +#define QAM_FQ_TAP_RE_EL7__W 12 +#define QAM_FQ_TAP_RE_EL7__M 0xFFF +#define QAM_FQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7_TAP__B 0 +#define QAM_FQ_TAP_RE_EL7_TAP__W 12 +#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7__A 0x142002F +#define QAM_FQ_TAP_IM_EL7__W 12 +#define QAM_FQ_TAP_IM_EL7__M 0xFFF +#define QAM_FQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7_TAP__B 0 +#define QAM_FQ_TAP_IM_EL7_TAP__W 12 +#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8__A 0x1420030 +#define QAM_FQ_TAP_RE_EL8__W 12 +#define QAM_FQ_TAP_RE_EL8__M 0xFFF +#define QAM_FQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8_TAP__B 0 +#define QAM_FQ_TAP_RE_EL8_TAP__W 12 +#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8__A 0x1420031 +#define QAM_FQ_TAP_IM_EL8__W 12 +#define QAM_FQ_TAP_IM_EL8__M 0xFFF +#define QAM_FQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8_TAP__B 0 +#define QAM_FQ_TAP_IM_EL8_TAP__W 12 +#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9__A 0x1420032 +#define QAM_FQ_TAP_RE_EL9__W 12 +#define QAM_FQ_TAP_RE_EL9__M 0xFFF +#define QAM_FQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9_TAP__B 0 +#define QAM_FQ_TAP_RE_EL9_TAP__W 12 +#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9__A 0x1420033 +#define QAM_FQ_TAP_IM_EL9__W 12 +#define QAM_FQ_TAP_IM_EL9__M 0xFFF +#define QAM_FQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9_TAP__B 0 +#define QAM_FQ_TAP_IM_EL9_TAP__W 12 +#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10__A 0x1420034 +#define QAM_FQ_TAP_RE_EL10__W 12 +#define QAM_FQ_TAP_RE_EL10__M 0xFFF +#define QAM_FQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10_TAP__B 0 +#define QAM_FQ_TAP_RE_EL10_TAP__W 12 +#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10__A 0x1420035 +#define QAM_FQ_TAP_IM_EL10__W 12 +#define QAM_FQ_TAP_IM_EL10__M 0xFFF +#define QAM_FQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10_TAP__B 0 +#define QAM_FQ_TAP_IM_EL10_TAP__W 12 +#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11__A 0x1420036 +#define QAM_FQ_TAP_RE_EL11__W 12 +#define QAM_FQ_TAP_RE_EL11__M 0xFFF +#define QAM_FQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11_TAP__B 0 +#define QAM_FQ_TAP_RE_EL11_TAP__W 12 +#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11__A 0x1420037 +#define QAM_FQ_TAP_IM_EL11__W 12 +#define QAM_FQ_TAP_IM_EL11__M 0xFFF +#define QAM_FQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11_TAP__B 0 +#define QAM_FQ_TAP_IM_EL11_TAP__W 12 +#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12__A 0x1420038 +#define QAM_FQ_TAP_RE_EL12__W 12 +#define QAM_FQ_TAP_RE_EL12__M 0xFFF +#define QAM_FQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12_TAP__B 0 +#define QAM_FQ_TAP_RE_EL12_TAP__W 12 +#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12__A 0x1420039 +#define QAM_FQ_TAP_IM_EL12__W 12 +#define QAM_FQ_TAP_IM_EL12__M 0xFFF +#define QAM_FQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12_TAP__B 0 +#define QAM_FQ_TAP_IM_EL12_TAP__W 12 +#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13__A 0x142003A +#define QAM_FQ_TAP_RE_EL13__W 12 +#define QAM_FQ_TAP_RE_EL13__M 0xFFF +#define QAM_FQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13_TAP__B 0 +#define QAM_FQ_TAP_RE_EL13_TAP__W 12 +#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13__A 0x142003B +#define QAM_FQ_TAP_IM_EL13__W 12 +#define QAM_FQ_TAP_IM_EL13__M 0xFFF +#define QAM_FQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13_TAP__B 0 +#define QAM_FQ_TAP_IM_EL13_TAP__W 12 +#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14__A 0x142003C +#define QAM_FQ_TAP_RE_EL14__W 12 +#define QAM_FQ_TAP_RE_EL14__M 0xFFF +#define QAM_FQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14_TAP__B 0 +#define QAM_FQ_TAP_RE_EL14_TAP__W 12 +#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14__A 0x142003D +#define QAM_FQ_TAP_IM_EL14__W 12 +#define QAM_FQ_TAP_IM_EL14__M 0xFFF +#define QAM_FQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14_TAP__B 0 +#define QAM_FQ_TAP_IM_EL14_TAP__W 12 +#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15__A 0x142003E +#define QAM_FQ_TAP_RE_EL15__W 12 +#define QAM_FQ_TAP_RE_EL15__M 0xFFF +#define QAM_FQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15_TAP__B 0 +#define QAM_FQ_TAP_RE_EL15_TAP__W 12 +#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15__A 0x142003F +#define QAM_FQ_TAP_IM_EL15__W 12 +#define QAM_FQ_TAP_IM_EL15__M 0xFFF +#define QAM_FQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15_TAP__B 0 +#define QAM_FQ_TAP_IM_EL15_TAP__W 12 +#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16__A 0x1420040 +#define QAM_FQ_TAP_RE_EL16__W 12 +#define QAM_FQ_TAP_RE_EL16__M 0xFFF +#define QAM_FQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16_TAP__B 0 +#define QAM_FQ_TAP_RE_EL16_TAP__W 12 +#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16__A 0x1420041 +#define QAM_FQ_TAP_IM_EL16__W 12 +#define QAM_FQ_TAP_IM_EL16__M 0xFFF +#define QAM_FQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16_TAP__B 0 +#define QAM_FQ_TAP_IM_EL16_TAP__W 12 +#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17__A 0x1420042 +#define QAM_FQ_TAP_RE_EL17__W 12 +#define QAM_FQ_TAP_RE_EL17__M 0xFFF +#define QAM_FQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17_TAP__B 0 +#define QAM_FQ_TAP_RE_EL17_TAP__W 12 +#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17__A 0x1420043 +#define QAM_FQ_TAP_IM_EL17__W 12 +#define QAM_FQ_TAP_IM_EL17__M 0xFFF +#define QAM_FQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17_TAP__B 0 +#define QAM_FQ_TAP_IM_EL17_TAP__W 12 +#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18__A 0x1420044 +#define QAM_FQ_TAP_RE_EL18__W 12 +#define QAM_FQ_TAP_RE_EL18__M 0xFFF +#define QAM_FQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18_TAP__B 0 +#define QAM_FQ_TAP_RE_EL18_TAP__W 12 +#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18__A 0x1420045 +#define QAM_FQ_TAP_IM_EL18__W 12 +#define QAM_FQ_TAP_IM_EL18__M 0xFFF +#define QAM_FQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18_TAP__B 0 +#define QAM_FQ_TAP_IM_EL18_TAP__W 12 +#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL19__A 0x1420046 +#define QAM_FQ_TAP_RE_EL19__W 12 +#define QAM_FQ_TAP_RE_EL19__M 0xFFF +#define QAM_FQ_TAP_RE_EL19__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL19_TAP__B 0 +#define QAM_FQ_TAP_RE_EL19_TAP__W 12 +#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 + +#define QAM_FQ_TAP_IM_EL19__A 0x1420047 +#define QAM_FQ_TAP_IM_EL19__W 12 +#define QAM_FQ_TAP_IM_EL19__M 0xFFF +#define QAM_FQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL19_TAP__B 0 +#define QAM_FQ_TAP_IM_EL19_TAP__W 12 +#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20__A 0x1420048 +#define QAM_FQ_TAP_RE_EL20__W 12 +#define QAM_FQ_TAP_RE_EL20__M 0xFFF +#define QAM_FQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20_TAP__B 0 +#define QAM_FQ_TAP_RE_EL20_TAP__W 12 +#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20__A 0x1420049 +#define QAM_FQ_TAP_IM_EL20__W 12 +#define QAM_FQ_TAP_IM_EL20__M 0xFFF +#define QAM_FQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20_TAP__B 0 +#define QAM_FQ_TAP_IM_EL20_TAP__W 12 +#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21__A 0x142004A +#define QAM_FQ_TAP_RE_EL21__W 12 +#define QAM_FQ_TAP_RE_EL21__M 0xFFF +#define QAM_FQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21_TAP__B 0 +#define QAM_FQ_TAP_RE_EL21_TAP__W 12 +#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21__A 0x142004B +#define QAM_FQ_TAP_IM_EL21__W 12 +#define QAM_FQ_TAP_IM_EL21__M 0xFFF +#define QAM_FQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21_TAP__B 0 +#define QAM_FQ_TAP_IM_EL21_TAP__W 12 +#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22__A 0x142004C +#define QAM_FQ_TAP_RE_EL22__W 12 +#define QAM_FQ_TAP_RE_EL22__M 0xFFF +#define QAM_FQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22_TAP__B 0 +#define QAM_FQ_TAP_RE_EL22_TAP__W 12 +#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22__A 0x142004D +#define QAM_FQ_TAP_IM_EL22__W 12 +#define QAM_FQ_TAP_IM_EL22__M 0xFFF +#define QAM_FQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22_TAP__B 0 +#define QAM_FQ_TAP_IM_EL22_TAP__W 12 +#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23__A 0x142004E +#define QAM_FQ_TAP_RE_EL23__W 12 +#define QAM_FQ_TAP_RE_EL23__M 0xFFF +#define QAM_FQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23_TAP__B 0 +#define QAM_FQ_TAP_RE_EL23_TAP__W 12 +#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23__A 0x142004F +#define QAM_FQ_TAP_IM_EL23__W 12 +#define QAM_FQ_TAP_IM_EL23__M 0xFFF +#define QAM_FQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23_TAP__B 0 +#define QAM_FQ_TAP_IM_EL23_TAP__W 12 +#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 + + + +#define QAM_SL_COMM_EXEC__A 0x1430000 +#define QAM_SL_COMM_EXEC__W 2 +#define QAM_SL_COMM_EXEC__M 0x3 +#define QAM_SL_COMM_EXEC__PRE 0x0 +#define QAM_SL_COMM_EXEC_STOP 0x0 +#define QAM_SL_COMM_EXEC_ACTIVE 0x1 +#define QAM_SL_COMM_EXEC_HOLD 0x2 + +#define QAM_SL_COMM_MB__A 0x1430002 +#define QAM_SL_COMM_MB__W 4 +#define QAM_SL_COMM_MB__M 0xF +#define QAM_SL_COMM_MB__PRE 0x0 +#define QAM_SL_COMM_MB_CTL__B 0 +#define QAM_SL_COMM_MB_CTL__W 1 +#define QAM_SL_COMM_MB_CTL__M 0x1 +#define QAM_SL_COMM_MB_CTL__PRE 0x0 +#define QAM_SL_COMM_MB_CTL_OFF 0x0 +#define QAM_SL_COMM_MB_CTL_ON 0x1 +#define QAM_SL_COMM_MB_OBS__B 1 +#define QAM_SL_COMM_MB_OBS__W 1 +#define QAM_SL_COMM_MB_OBS__M 0x2 +#define QAM_SL_COMM_MB_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_OBS_OFF 0x0 +#define QAM_SL_COMM_MB_OBS_ON 0x2 +#define QAM_SL_COMM_MB_MUX_OBS__B 2 +#define QAM_SL_COMM_MB_MUX_OBS__W 2 +#define QAM_SL_COMM_MB_MUX_OBS__M 0xC +#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 +#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC + +#define QAM_SL_COMM_INT_REQ__A 0x1430003 +#define QAM_SL_COMM_INT_REQ__W 1 +#define QAM_SL_COMM_INT_REQ__M 0x1 +#define QAM_SL_COMM_INT_REQ__PRE 0x0 +#define QAM_SL_COMM_INT_STA__A 0x1430005 +#define QAM_SL_COMM_INT_STA__W 2 +#define QAM_SL_COMM_INT_STA__M 0x3 +#define QAM_SL_COMM_INT_STA__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MER_INT__B 1 +#define QAM_SL_COMM_INT_STA_MER_INT__W 1 +#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 +#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_MSK__A 0x1430006 +#define QAM_SL_COMM_INT_MSK__W 2 +#define QAM_SL_COMM_INT_MSK__M 0x3 +#define QAM_SL_COMM_INT_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 +#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 + +#define QAM_SL_COMM_INT_STM__A 0x1430007 +#define QAM_SL_COMM_INT_STM__W 2 +#define QAM_SL_COMM_INT_STM__M 0x3 +#define QAM_SL_COMM_INT_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MER_STM__B 1 +#define QAM_SL_COMM_INT_STM_MER_STM__W 1 +#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 +#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 + +#define QAM_SL_MODE__A 0x1430010 +#define QAM_SL_MODE__W 11 +#define QAM_SL_MODE__M 0x7FF +#define QAM_SL_MODE__PRE 0xA + +#define QAM_SL_MODE_SLICER4LC__B 0 +#define QAM_SL_MODE_SLICER4LC__W 2 +#define QAM_SL_MODE_SLICER4LC__M 0x3 +#define QAM_SL_MODE_SLICER4LC__PRE 0x2 +#define QAM_SL_MODE_SLICER4LC_RECT 0x0 +#define QAM_SL_MODE_SLICER4LC_ONET 0x1 +#define QAM_SL_MODE_SLICER4LC_RAD 0x2 + +#define QAM_SL_MODE_SLICER4DQ__B 2 +#define QAM_SL_MODE_SLICER4DQ__W 2 +#define QAM_SL_MODE_SLICER4DQ__M 0xC +#define QAM_SL_MODE_SLICER4DQ__PRE 0x8 +#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 +#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 +#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 + +#define QAM_SL_MODE_SLICER4VD__B 4 +#define QAM_SL_MODE_SLICER4VD__W 2 +#define QAM_SL_MODE_SLICER4VD__M 0x30 +#define QAM_SL_MODE_SLICER4VD__PRE 0x0 +#define QAM_SL_MODE_SLICER4VD_RECT 0x0 +#define QAM_SL_MODE_SLICER4VD_ONET 0x10 +#define QAM_SL_MODE_SLICER4VD_RAD 0x20 + +#define QAM_SL_MODE_ROT_DIS__B 6 +#define QAM_SL_MODE_ROT_DIS__W 1 +#define QAM_SL_MODE_ROT_DIS__M 0x40 +#define QAM_SL_MODE_ROT_DIS__PRE 0x0 +#define QAM_SL_MODE_ROT_DIS_ROTATE 0x0 +#define QAM_SL_MODE_ROT_DIS_DISABLED 0x40 + +#define QAM_SL_MODE_DQROT_DIS__B 7 +#define QAM_SL_MODE_DQROT_DIS__W 1 +#define QAM_SL_MODE_DQROT_DIS__M 0x80 +#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 +#define QAM_SL_MODE_DQROT_DIS_ROTATE 0x0 +#define QAM_SL_MODE_DQROT_DIS_DISABLED 0x80 + +#define QAM_SL_MODE_DFE_DIS__B 8 +#define QAM_SL_MODE_DFE_DIS__W 1 +#define QAM_SL_MODE_DFE_DIS__M 0x100 +#define QAM_SL_MODE_DFE_DIS__PRE 0x0 +#define QAM_SL_MODE_DFE_DIS_DQ 0x0 +#define QAM_SL_MODE_DFE_DIS_DISABLED 0x100 + +#define QAM_SL_MODE_RADIUS_MIX__B 9 +#define QAM_SL_MODE_RADIUS_MIX__W 1 +#define QAM_SL_MODE_RADIUS_MIX__M 0x200 +#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 +#define QAM_SL_MODE_RADIUS_MIX_OFF 0x0 +#define QAM_SL_MODE_RADIUS_MIX_RADMIX 0x200 + +#define QAM_SL_MODE_TILT_COMP__B 10 +#define QAM_SL_MODE_TILT_COMP__W 1 +#define QAM_SL_MODE_TILT_COMP__M 0x400 +#define QAM_SL_MODE_TILT_COMP__PRE 0x0 +#define QAM_SL_MODE_TILT_COMP_OFF 0x0 +#define QAM_SL_MODE_TILT_COMP_TILTCOMP 0x400 + + +#define QAM_SL_K_FACTOR__A 0x1430011 +#define QAM_SL_K_FACTOR__W 4 +#define QAM_SL_K_FACTOR__M 0xF +#define QAM_SL_K_FACTOR__PRE 0xC +#define QAM_SL_MEDIAN__A 0x1430012 +#define QAM_SL_MEDIAN__W 14 +#define QAM_SL_MEDIAN__M 0x3FFF +#define QAM_SL_MEDIAN__PRE 0x2C86 + +#define QAM_SL_MEDIAN_LENGTH__B 0 +#define QAM_SL_MEDIAN_LENGTH__W 2 +#define QAM_SL_MEDIAN_LENGTH__M 0x3 +#define QAM_SL_MEDIAN_LENGTH__PRE 0x2 +#define QAM_SL_MEDIAN_LENGTH_MEDL1 0x0 +#define QAM_SL_MEDIAN_LENGTH_MEDL2 0x1 +#define QAM_SL_MEDIAN_LENGTH_MEDL4 0x2 +#define QAM_SL_MEDIAN_LENGTH_MEDL8 0x3 + +#define QAM_SL_MEDIAN_CORRECT__B 2 +#define QAM_SL_MEDIAN_CORRECT__W 4 +#define QAM_SL_MEDIAN_CORRECT__M 0x3C +#define QAM_SL_MEDIAN_CORRECT__PRE 0x4 + +#define QAM_SL_MEDIAN_TOLERANCE__B 6 +#define QAM_SL_MEDIAN_TOLERANCE__W 7 +#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 +#define QAM_SL_MEDIAN_TOLERANCE__PRE 0xC80 + +#define QAM_SL_MEDIAN_FAST__B 13 +#define QAM_SL_MEDIAN_FAST__W 1 +#define QAM_SL_MEDIAN_FAST__M 0x2000 +#define QAM_SL_MEDIAN_FAST__PRE 0x2000 +#define QAM_SL_MEDIAN_FAST_AVER 0x0 +#define QAM_SL_MEDIAN_FAST_LAST 0x2000 + + +#define QAM_SL_ALPHA__A 0x1430013 +#define QAM_SL_ALPHA__W 3 +#define QAM_SL_ALPHA__M 0x7 +#define QAM_SL_ALPHA__PRE 0x0 + +#define QAM_SL_PHASELIMIT__A 0x1430014 +#define QAM_SL_PHASELIMIT__W 9 +#define QAM_SL_PHASELIMIT__M 0x1FF +#define QAM_SL_PHASELIMIT__PRE 0x0 +#define QAM_SL_MTA_LENGTH__A 0x1430015 +#define QAM_SL_MTA_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH__PRE 0x1 + +#define QAM_SL_MTA_LENGTH_LENGTH__B 0 +#define QAM_SL_MTA_LENGTH_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 + +#define QAM_SL_MEDIAN_ERROR__A 0x1430016 +#define QAM_SL_MEDIAN_ERROR__W 10 +#define QAM_SL_MEDIAN_ERROR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR__PRE 0x0 + +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 + + +#define QAM_SL_ERR_POWER__A 0x1430017 +#define QAM_SL_ERR_POWER__W 16 +#define QAM_SL_ERR_POWER__M 0xFFFF +#define QAM_SL_ERR_POWER__PRE 0x0 +#define QAM_SL_QUAL_QAM_4_0__A 0x1430018 +#define QAM_SL_QUAL_QAM_4_0__W 3 +#define QAM_SL_QUAL_QAM_4_0__M 0x7 +#define QAM_SL_QUAL_QAM_4_0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_4_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_4_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_4_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_4_0_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_8_0__A 0x1430019 +#define QAM_SL_QUAL_QAM_8_0__W 6 +#define QAM_SL_QUAL_QAM_8_0__M 0x3F +#define QAM_SL_QUAL_QAM_8_0__PRE 0xD + +#define QAM_SL_QUAL_QAM_8_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_8_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_8_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_8_0_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_8_0_Q1__B 3 +#define QAM_SL_QUAL_QAM_8_0_Q1__W 3 +#define QAM_SL_QUAL_QAM_8_0_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_8_0_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_16_0__A 0x143001A +#define QAM_SL_QUAL_QAM_16_0__W 3 +#define QAM_SL_QUAL_QAM_16_0__M 0x7 +#define QAM_SL_QUAL_QAM_16_0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_16_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_16_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_16_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_16_0_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_16_1__A 0x143001B +#define QAM_SL_QUAL_QAM_16_1__W 6 +#define QAM_SL_QUAL_QAM_16_1__M 0x3F +#define QAM_SL_QUAL_QAM_16_1__PRE 0x5 + +#define QAM_SL_QUAL_QAM_16_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_16_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_16_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_16_1_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_16_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_16_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_16_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_16_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_0__A 0x143001C +#define QAM_SL_QUAL_QAM_32_0__W 3 +#define QAM_SL_QUAL_QAM_32_0__M 0x7 +#define QAM_SL_QUAL_QAM_32_0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_32_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_32_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_32_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_32_0_Q0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_32_1__A 0x143001D +#define QAM_SL_QUAL_QAM_32_1__W 6 +#define QAM_SL_QUAL_QAM_32_1__M 0x3F +#define QAM_SL_QUAL_QAM_32_1__PRE 0x3 + +#define QAM_SL_QUAL_QAM_32_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_32_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_32_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_32_1_Q0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_32_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_32_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_32_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_32_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2__A 0x143001E +#define QAM_SL_QUAL_QAM_32_2__W 9 +#define QAM_SL_QUAL_QAM_32_2__M 0x1FF +#define QAM_SL_QUAL_QAM_32_2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_32_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_32_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_32_2_Q0__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_32_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_32_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_32_2_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_32_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_32_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_32_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_0__A 0x143001F +#define QAM_SL_QUAL_QAM_64_0__W 3 +#define QAM_SL_QUAL_QAM_64_0__M 0x7 +#define QAM_SL_QUAL_QAM_64_0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_64_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_0_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_64_1__A 0x1430020 +#define QAM_SL_QUAL_QAM_64_1__W 6 +#define QAM_SL_QUAL_QAM_64_1__M 0x3F +#define QAM_SL_QUAL_QAM_64_1__PRE 0x2 + +#define QAM_SL_QUAL_QAM_64_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_1_Q0__PRE 0x2 + +#define QAM_SL_QUAL_QAM_64_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_64_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_64_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_64_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_2__A 0x1430021 +#define QAM_SL_QUAL_QAM_64_2__W 9 +#define QAM_SL_QUAL_QAM_64_2__M 0x1FF +#define QAM_SL_QUAL_QAM_64_2__PRE 0x9 + +#define QAM_SL_QUAL_QAM_64_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_2_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_64_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_64_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_64_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_64_2_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_64_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_64_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_64_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_64_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_3__A 0x1430022 +#define QAM_SL_QUAL_QAM_64_3__W 12 +#define QAM_SL_QUAL_QAM_64_3__M 0xFFF +#define QAM_SL_QUAL_QAM_64_3__PRE 0xD + +#define QAM_SL_QUAL_QAM_64_3_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_3_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_3_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_64_3_Q1__B 3 +#define QAM_SL_QUAL_QAM_64_3_Q1__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_64_3_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_64_3_Q2__B 6 +#define QAM_SL_QUAL_QAM_64_3_Q2__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_64_3_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_3_Q3__B 9 +#define QAM_SL_QUAL_QAM_64_3_Q3__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_64_3_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_0__A 0x1430023 +#define QAM_SL_QUAL_QAM_128_0__W 3 +#define QAM_SL_QUAL_QAM_128_0__M 0x7 +#define QAM_SL_QUAL_QAM_128_0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_128_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_0_Q0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_128_1__A 0x1430024 +#define QAM_SL_QUAL_QAM_128_1__W 6 +#define QAM_SL_QUAL_QAM_128_1__M 0x3F +#define QAM_SL_QUAL_QAM_128_1__PRE 0x5 + +#define QAM_SL_QUAL_QAM_128_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_1_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_128_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_2__A 0x1430025 +#define QAM_SL_QUAL_QAM_128_2__W 9 +#define QAM_SL_QUAL_QAM_128_2__M 0x1FF +#define QAM_SL_QUAL_QAM_128_2__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_2_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_2_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_3__A 0x1430026 +#define QAM_SL_QUAL_QAM_128_3__W 12 +#define QAM_SL_QUAL_QAM_128_3__M 0xFFF +#define QAM_SL_QUAL_QAM_128_3__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_3_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_3_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_3_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_3_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_3_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_3_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_3_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_3_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_3_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_3_Q3__B 9 +#define QAM_SL_QUAL_QAM_128_3_Q3__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_128_3_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4__A 0x1430027 +#define QAM_SL_QUAL_QAM_128_4__W 15 +#define QAM_SL_QUAL_QAM_128_4__M 0x7FFF +#define QAM_SL_QUAL_QAM_128_4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_4_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_4_Q0__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_4_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_4_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_4_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_4_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q3__B 9 +#define QAM_SL_QUAL_QAM_128_4_Q3__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_128_4_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q4__B 12 +#define QAM_SL_QUAL_QAM_128_4_Q4__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_128_4_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5__A 0x1430028 +#define QAM_SL_QUAL_QAM_128_5__W 15 +#define QAM_SL_QUAL_QAM_128_5__M 0x7FFF +#define QAM_SL_QUAL_QAM_128_5__PRE 0x90 + +#define QAM_SL_QUAL_QAM_128_5_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_5_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_5_Q0__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_5_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_5_Q1__PRE 0x10 + +#define QAM_SL_QUAL_QAM_128_5_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_5_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_5_Q2__PRE 0x80 + +#define QAM_SL_QUAL_QAM_128_5_Q3__B 9 +#define QAM_SL_QUAL_QAM_128_5_Q3__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_128_5_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5_Q4__B 12 +#define QAM_SL_QUAL_QAM_128_5_Q4__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_128_5_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5H__A 0x1430029 +#define QAM_SL_QUAL_QAM_128_5H__W 3 +#define QAM_SL_QUAL_QAM_128_5H__M 0x7 +#define QAM_SL_QUAL_QAM_128_5H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5H_Q5__B 0 +#define QAM_SL_QUAL_QAM_128_5H_Q5__W 3 +#define QAM_SL_QUAL_QAM_128_5H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_128_5H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_0__A 0x143002A +#define QAM_SL_QUAL_QAM_256_0__W 3 +#define QAM_SL_QUAL_QAM_256_0__M 0x7 +#define QAM_SL_QUAL_QAM_256_0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_256_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_0_Q0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_256_1__A 0x143002B +#define QAM_SL_QUAL_QAM_256_1__W 6 +#define QAM_SL_QUAL_QAM_256_1__M 0x3F +#define QAM_SL_QUAL_QAM_256_1__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_1_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_2__A 0x143002C +#define QAM_SL_QUAL_QAM_256_2__W 9 +#define QAM_SL_QUAL_QAM_256_2__M 0x1FF +#define QAM_SL_QUAL_QAM_256_2__PRE 0x9 + +#define QAM_SL_QUAL_QAM_256_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_2_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_2_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_256_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_3__A 0x143002D +#define QAM_SL_QUAL_QAM_256_3__W 12 +#define QAM_SL_QUAL_QAM_256_3__M 0xFFF +#define QAM_SL_QUAL_QAM_256_3__PRE 0x13 + +#define QAM_SL_QUAL_QAM_256_3_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_3_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_3_Q0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_256_3_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_3_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_3_Q1__PRE 0x10 + +#define QAM_SL_QUAL_QAM_256_3_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_3_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_3_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_3_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_3_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_3_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_4__A 0x143002E +#define QAM_SL_QUAL_QAM_256_4__W 15 +#define QAM_SL_QUAL_QAM_256_4__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_4__PRE 0x49 + +#define QAM_SL_QUAL_QAM_256_4_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_4_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_4_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_4_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_4_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_4_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_256_4_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_4_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_4_Q2__PRE 0x40 + +#define QAM_SL_QUAL_QAM_256_4_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_4_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_4_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_4_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_4_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_4_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5__A 0x143002F +#define QAM_SL_QUAL_QAM_256_5__W 15 +#define QAM_SL_QUAL_QAM_256_5__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_5__PRE 0x59 + +#define QAM_SL_QUAL_QAM_256_5_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_5_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_5_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_5_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_5_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_5_Q1__PRE 0x18 + +#define QAM_SL_QUAL_QAM_256_5_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_5_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_5_Q2__PRE 0x40 + +#define QAM_SL_QUAL_QAM_256_5_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_5_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_5_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_5_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_5_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5H__A 0x1430030 +#define QAM_SL_QUAL_QAM_256_5H__W 3 +#define QAM_SL_QUAL_QAM_256_5H__M 0x7 +#define QAM_SL_QUAL_QAM_256_5H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5H_Q5__B 0 +#define QAM_SL_QUAL_QAM_256_5H_Q5__W 3 +#define QAM_SL_QUAL_QAM_256_5H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_256_5H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6__A 0x1430031 +#define QAM_SL_QUAL_QAM_256_6__W 15 +#define QAM_SL_QUAL_QAM_256_6__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_6__PRE 0x21A + +#define QAM_SL_QUAL_QAM_256_6_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_6_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_6_Q0__PRE 0x2 + +#define QAM_SL_QUAL_QAM_256_6_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_6_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_6_Q1__PRE 0x18 + +#define QAM_SL_QUAL_QAM_256_6_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_6_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_6_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_6_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_6_Q3__PRE 0x200 + +#define QAM_SL_QUAL_QAM_256_6_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_6_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_6_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6H__A 0x1430032 +#define QAM_SL_QUAL_QAM_256_6H__W 6 +#define QAM_SL_QUAL_QAM_256_6H__M 0x3F +#define QAM_SL_QUAL_QAM_256_6H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6H_Q5__B 0 +#define QAM_SL_QUAL_QAM_256_6H_Q5__W 3 +#define QAM_SL_QUAL_QAM_256_6H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_256_6H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6H_Q6__B 3 +#define QAM_SL_QUAL_QAM_256_6H_Q6__W 3 +#define QAM_SL_QUAL_QAM_256_6H_Q6__M 0x38 +#define QAM_SL_QUAL_QAM_256_6H_Q6__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7__A 0x1430033 +#define QAM_SL_QUAL_QAM_256_7__W 15 +#define QAM_SL_QUAL_QAM_256_7__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_7__PRE 0x29D + +#define QAM_SL_QUAL_QAM_256_7_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_7_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_7_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_256_7_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_7_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_7_Q1__PRE 0x18 + +#define QAM_SL_QUAL_QAM_256_7_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_7_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_7_Q2__PRE 0x80 + +#define QAM_SL_QUAL_QAM_256_7_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_7_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_7_Q3__PRE 0x200 + +#define QAM_SL_QUAL_QAM_256_7_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_7_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_7_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H__A 0x1430034 +#define QAM_SL_QUAL_QAM_256_7H__W 9 +#define QAM_SL_QUAL_QAM_256_7H__M 0x1FF +#define QAM_SL_QUAL_QAM_256_7H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H_Q5__B 0 +#define QAM_SL_QUAL_QAM_256_7H_Q5__W 3 +#define QAM_SL_QUAL_QAM_256_7H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_256_7H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H_Q6__B 3 +#define QAM_SL_QUAL_QAM_256_7H_Q6__W 3 +#define QAM_SL_QUAL_QAM_256_7H_Q6__M 0x38 +#define QAM_SL_QUAL_QAM_256_7H_Q6__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H_Q7__B 6 +#define QAM_SL_QUAL_QAM_256_7H_Q7__W 3 +#define QAM_SL_QUAL_QAM_256_7H_Q7__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_7H_Q7__PRE 0x0 + + + +#define QAM_DQ_COMM_EXEC__A 0x1440000 +#define QAM_DQ_COMM_EXEC__W 2 +#define QAM_DQ_COMM_EXEC__M 0x3 +#define QAM_DQ_COMM_EXEC__PRE 0x0 +#define QAM_DQ_COMM_EXEC_STOP 0x0 +#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_DQ_COMM_EXEC_HOLD 0x2 + +#define QAM_DQ_MODE__A 0x1440010 +#define QAM_DQ_MODE__W 5 +#define QAM_DQ_MODE__M 0x1F +#define QAM_DQ_MODE__PRE 0x0 + +#define QAM_DQ_MODE_TAPRESET__B 0 +#define QAM_DQ_MODE_TAPRESET__W 1 +#define QAM_DQ_MODE_TAPRESET__M 0x1 +#define QAM_DQ_MODE_TAPRESET__PRE 0x0 +#define QAM_DQ_MODE_TAPRESET_RST 0x1 + +#define QAM_DQ_MODE_TAPLMS__B 1 +#define QAM_DQ_MODE_TAPLMS__W 1 +#define QAM_DQ_MODE_TAPLMS__M 0x2 +#define QAM_DQ_MODE_TAPLMS__PRE 0x0 +#define QAM_DQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_DQ_MODE_TAPDRAIN__B 2 +#define QAM_DQ_MODE_TAPDRAIN__W 1 +#define QAM_DQ_MODE_TAPDRAIN__M 0x4 +#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 + +#define QAM_DQ_MODE_FB__B 3 +#define QAM_DQ_MODE_FB__W 2 +#define QAM_DQ_MODE_FB__M 0x18 +#define QAM_DQ_MODE_FB__PRE 0x0 +#define QAM_DQ_MODE_FB_CMA 0x0 +#define QAM_DQ_MODE_FB_RADIUS 0x8 +#define QAM_DQ_MODE_FB_DFB 0x10 +#define QAM_DQ_MODE_FB_TRELLIS 0x18 + + +#define QAM_DQ_MU_FACTOR__A 0x1440011 +#define QAM_DQ_MU_FACTOR__W 3 +#define QAM_DQ_MU_FACTOR__M 0x7 +#define QAM_DQ_MU_FACTOR__PRE 0x0 + +#define QAM_DQ_LA_FACTOR__A 0x1440012 +#define QAM_DQ_LA_FACTOR__W 4 +#define QAM_DQ_LA_FACTOR__M 0xF +#define QAM_DQ_LA_FACTOR__PRE 0xC + +#define QAM_DQ_CMA_RATIO__A 0x1440013 +#define QAM_DQ_CMA_RATIO__W 14 +#define QAM_DQ_CMA_RATIO__M 0x3FFF +#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 +#define QAM_DQ_CMA_RATIO_QPSK 0x2000 +#define QAM_DQ_CMA_RATIO_QAM16 0x34CD +#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 +#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D +#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 + +#define QAM_DQ_QUAL_RADSEL__A 0x1440014 +#define QAM_DQ_QUAL_RADSEL__W 3 +#define QAM_DQ_QUAL_RADSEL__M 0x7 +#define QAM_DQ_QUAL_RADSEL__PRE 0x0 + +#define QAM_DQ_QUAL_RADSEL_BIT__B 0 +#define QAM_DQ_QUAL_RADSEL_BIT__W 3 +#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 +#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 + +#define QAM_DQ_QUAL_ENA__A 0x1440015 +#define QAM_DQ_QUAL_ENA__W 1 +#define QAM_DQ_QUAL_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA__PRE 0x0 + +#define QAM_DQ_QUAL_ENA_ENA__B 0 +#define QAM_DQ_QUAL_ENA_ENA__W 1 +#define QAM_DQ_QUAL_ENA_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 +#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 + +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__PRE 0x4 + +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__PRE 0x6 + +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 + +#define QAM_DQ_RAW_LIM__A 0x144001E +#define QAM_DQ_RAW_LIM__W 5 +#define QAM_DQ_RAW_LIM__M 0x1F +#define QAM_DQ_RAW_LIM__PRE 0x1F + +#define QAM_DQ_RAW_LIM_BIT__B 0 +#define QAM_DQ_RAW_LIM_BIT__W 5 +#define QAM_DQ_RAW_LIM_BIT__M 0x1F +#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F + +#define QAM_DQ_TAP_RE_EL0__A 0x1440020 +#define QAM_DQ_TAP_RE_EL0__W 12 +#define QAM_DQ_TAP_RE_EL0__M 0xFFF +#define QAM_DQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL0_TAP__B 0 +#define QAM_DQ_TAP_RE_EL0_TAP__W 12 +#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0__A 0x1440021 +#define QAM_DQ_TAP_IM_EL0__W 12 +#define QAM_DQ_TAP_IM_EL0__M 0xFFF +#define QAM_DQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0_TAP__B 0 +#define QAM_DQ_TAP_IM_EL0_TAP__W 12 +#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1__A 0x1440022 +#define QAM_DQ_TAP_RE_EL1__W 12 +#define QAM_DQ_TAP_RE_EL1__M 0xFFF +#define QAM_DQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1_TAP__B 0 +#define QAM_DQ_TAP_RE_EL1_TAP__W 12 +#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1__A 0x1440023 +#define QAM_DQ_TAP_IM_EL1__W 12 +#define QAM_DQ_TAP_IM_EL1__M 0xFFF +#define QAM_DQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1_TAP__B 0 +#define QAM_DQ_TAP_IM_EL1_TAP__W 12 +#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2__A 0x1440024 +#define QAM_DQ_TAP_RE_EL2__W 12 +#define QAM_DQ_TAP_RE_EL2__M 0xFFF +#define QAM_DQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2_TAP__B 0 +#define QAM_DQ_TAP_RE_EL2_TAP__W 12 +#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2__A 0x1440025 +#define QAM_DQ_TAP_IM_EL2__W 12 +#define QAM_DQ_TAP_IM_EL2__M 0xFFF +#define QAM_DQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2_TAP__B 0 +#define QAM_DQ_TAP_IM_EL2_TAP__W 12 +#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3__A 0x1440026 +#define QAM_DQ_TAP_RE_EL3__W 12 +#define QAM_DQ_TAP_RE_EL3__M 0xFFF +#define QAM_DQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3_TAP__B 0 +#define QAM_DQ_TAP_RE_EL3_TAP__W 12 +#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3__A 0x1440027 +#define QAM_DQ_TAP_IM_EL3__W 12 +#define QAM_DQ_TAP_IM_EL3__M 0xFFF +#define QAM_DQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3_TAP__B 0 +#define QAM_DQ_TAP_IM_EL3_TAP__W 12 +#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4__A 0x1440028 +#define QAM_DQ_TAP_RE_EL4__W 12 +#define QAM_DQ_TAP_RE_EL4__M 0xFFF +#define QAM_DQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4_TAP__B 0 +#define QAM_DQ_TAP_RE_EL4_TAP__W 12 +#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4__A 0x1440029 +#define QAM_DQ_TAP_IM_EL4__W 12 +#define QAM_DQ_TAP_IM_EL4__M 0xFFF +#define QAM_DQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4_TAP__B 0 +#define QAM_DQ_TAP_IM_EL4_TAP__W 12 +#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5__A 0x144002A +#define QAM_DQ_TAP_RE_EL5__W 12 +#define QAM_DQ_TAP_RE_EL5__M 0xFFF +#define QAM_DQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5_TAP__B 0 +#define QAM_DQ_TAP_RE_EL5_TAP__W 12 +#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5__A 0x144002B +#define QAM_DQ_TAP_IM_EL5__W 12 +#define QAM_DQ_TAP_IM_EL5__M 0xFFF +#define QAM_DQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5_TAP__B 0 +#define QAM_DQ_TAP_IM_EL5_TAP__W 12 +#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6__A 0x144002C +#define QAM_DQ_TAP_RE_EL6__W 12 +#define QAM_DQ_TAP_RE_EL6__M 0xFFF +#define QAM_DQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6_TAP__B 0 +#define QAM_DQ_TAP_RE_EL6_TAP__W 12 +#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6__A 0x144002D +#define QAM_DQ_TAP_IM_EL6__W 12 +#define QAM_DQ_TAP_IM_EL6__M 0xFFF +#define QAM_DQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6_TAP__B 0 +#define QAM_DQ_TAP_IM_EL6_TAP__W 12 +#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7__A 0x144002E +#define QAM_DQ_TAP_RE_EL7__W 12 +#define QAM_DQ_TAP_RE_EL7__M 0xFFF +#define QAM_DQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7_TAP__B 0 +#define QAM_DQ_TAP_RE_EL7_TAP__W 12 +#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7__A 0x144002F +#define QAM_DQ_TAP_IM_EL7__W 12 +#define QAM_DQ_TAP_IM_EL7__M 0xFFF +#define QAM_DQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7_TAP__B 0 +#define QAM_DQ_TAP_IM_EL7_TAP__W 12 +#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8__A 0x1440030 +#define QAM_DQ_TAP_RE_EL8__W 12 +#define QAM_DQ_TAP_RE_EL8__M 0xFFF +#define QAM_DQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8_TAP__B 0 +#define QAM_DQ_TAP_RE_EL8_TAP__W 12 +#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8__A 0x1440031 +#define QAM_DQ_TAP_IM_EL8__W 12 +#define QAM_DQ_TAP_IM_EL8__M 0xFFF +#define QAM_DQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8_TAP__B 0 +#define QAM_DQ_TAP_IM_EL8_TAP__W 12 +#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9__A 0x1440032 +#define QAM_DQ_TAP_RE_EL9__W 12 +#define QAM_DQ_TAP_RE_EL9__M 0xFFF +#define QAM_DQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9_TAP__B 0 +#define QAM_DQ_TAP_RE_EL9_TAP__W 12 +#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9__A 0x1440033 +#define QAM_DQ_TAP_IM_EL9__W 12 +#define QAM_DQ_TAP_IM_EL9__M 0xFFF +#define QAM_DQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9_TAP__B 0 +#define QAM_DQ_TAP_IM_EL9_TAP__W 12 +#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10__A 0x1440034 +#define QAM_DQ_TAP_RE_EL10__W 12 +#define QAM_DQ_TAP_RE_EL10__M 0xFFF +#define QAM_DQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10_TAP__B 0 +#define QAM_DQ_TAP_RE_EL10_TAP__W 12 +#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10__A 0x1440035 +#define QAM_DQ_TAP_IM_EL10__W 12 +#define QAM_DQ_TAP_IM_EL10__M 0xFFF +#define QAM_DQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10_TAP__B 0 +#define QAM_DQ_TAP_IM_EL10_TAP__W 12 +#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11__A 0x1440036 +#define QAM_DQ_TAP_RE_EL11__W 12 +#define QAM_DQ_TAP_RE_EL11__M 0xFFF +#define QAM_DQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11_TAP__B 0 +#define QAM_DQ_TAP_RE_EL11_TAP__W 12 +#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11__A 0x1440037 +#define QAM_DQ_TAP_IM_EL11__W 12 +#define QAM_DQ_TAP_IM_EL11__M 0xFFF +#define QAM_DQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11_TAP__B 0 +#define QAM_DQ_TAP_IM_EL11_TAP__W 12 +#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12__A 0x1440038 +#define QAM_DQ_TAP_RE_EL12__W 12 +#define QAM_DQ_TAP_RE_EL12__M 0xFFF +#define QAM_DQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12_TAP__B 0 +#define QAM_DQ_TAP_RE_EL12_TAP__W 12 +#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12__A 0x1440039 +#define QAM_DQ_TAP_IM_EL12__W 12 +#define QAM_DQ_TAP_IM_EL12__M 0xFFF +#define QAM_DQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12_TAP__B 0 +#define QAM_DQ_TAP_IM_EL12_TAP__W 12 +#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13__A 0x144003A +#define QAM_DQ_TAP_RE_EL13__W 12 +#define QAM_DQ_TAP_RE_EL13__M 0xFFF +#define QAM_DQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13_TAP__B 0 +#define QAM_DQ_TAP_RE_EL13_TAP__W 12 +#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13__A 0x144003B +#define QAM_DQ_TAP_IM_EL13__W 12 +#define QAM_DQ_TAP_IM_EL13__M 0xFFF +#define QAM_DQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13_TAP__B 0 +#define QAM_DQ_TAP_IM_EL13_TAP__W 12 +#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14__A 0x144003C +#define QAM_DQ_TAP_RE_EL14__W 12 +#define QAM_DQ_TAP_RE_EL14__M 0xFFF +#define QAM_DQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14_TAP__B 0 +#define QAM_DQ_TAP_RE_EL14_TAP__W 12 +#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14__A 0x144003D +#define QAM_DQ_TAP_IM_EL14__W 12 +#define QAM_DQ_TAP_IM_EL14__M 0xFFF +#define QAM_DQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14_TAP__B 0 +#define QAM_DQ_TAP_IM_EL14_TAP__W 12 +#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15__A 0x144003E +#define QAM_DQ_TAP_RE_EL15__W 12 +#define QAM_DQ_TAP_RE_EL15__M 0xFFF +#define QAM_DQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15_TAP__B 0 +#define QAM_DQ_TAP_RE_EL15_TAP__W 12 +#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15__A 0x144003F +#define QAM_DQ_TAP_IM_EL15__W 12 +#define QAM_DQ_TAP_IM_EL15__M 0xFFF +#define QAM_DQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15_TAP__B 0 +#define QAM_DQ_TAP_IM_EL15_TAP__W 12 +#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16__A 0x1440040 +#define QAM_DQ_TAP_RE_EL16__W 12 +#define QAM_DQ_TAP_RE_EL16__M 0xFFF +#define QAM_DQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16_TAP__B 0 +#define QAM_DQ_TAP_RE_EL16_TAP__W 12 +#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16__A 0x1440041 +#define QAM_DQ_TAP_IM_EL16__W 12 +#define QAM_DQ_TAP_IM_EL16__M 0xFFF +#define QAM_DQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16_TAP__B 0 +#define QAM_DQ_TAP_IM_EL16_TAP__W 12 +#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17__A 0x1440042 +#define QAM_DQ_TAP_RE_EL17__W 12 +#define QAM_DQ_TAP_RE_EL17__M 0xFFF +#define QAM_DQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17_TAP__B 0 +#define QAM_DQ_TAP_RE_EL17_TAP__W 12 +#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17__A 0x1440043 +#define QAM_DQ_TAP_IM_EL17__W 12 +#define QAM_DQ_TAP_IM_EL17__M 0xFFF +#define QAM_DQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17_TAP__B 0 +#define QAM_DQ_TAP_IM_EL17_TAP__W 12 +#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18__A 0x1440044 +#define QAM_DQ_TAP_RE_EL18__W 12 +#define QAM_DQ_TAP_RE_EL18__M 0xFFF +#define QAM_DQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18_TAP__B 0 +#define QAM_DQ_TAP_RE_EL18_TAP__W 12 +#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18__A 0x1440045 +#define QAM_DQ_TAP_IM_EL18__W 12 +#define QAM_DQ_TAP_IM_EL18__M 0xFFF +#define QAM_DQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18_TAP__B 0 +#define QAM_DQ_TAP_IM_EL18_TAP__W 12 +#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19__A 0x1440046 +#define QAM_DQ_TAP_RE_EL19__W 12 +#define QAM_DQ_TAP_RE_EL19__M 0xFFF +#define QAM_DQ_TAP_RE_EL19__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19_TAP__B 0 +#define QAM_DQ_TAP_RE_EL19_TAP__W 12 +#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19__A 0x1440047 +#define QAM_DQ_TAP_IM_EL19__W 12 +#define QAM_DQ_TAP_IM_EL19__M 0xFFF +#define QAM_DQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19_TAP__B 0 +#define QAM_DQ_TAP_IM_EL19_TAP__W 12 +#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20__A 0x1440048 +#define QAM_DQ_TAP_RE_EL20__W 12 +#define QAM_DQ_TAP_RE_EL20__M 0xFFF +#define QAM_DQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20_TAP__B 0 +#define QAM_DQ_TAP_RE_EL20_TAP__W 12 +#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20__A 0x1440049 +#define QAM_DQ_TAP_IM_EL20__W 12 +#define QAM_DQ_TAP_IM_EL20__M 0xFFF +#define QAM_DQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20_TAP__B 0 +#define QAM_DQ_TAP_IM_EL20_TAP__W 12 +#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21__A 0x144004A +#define QAM_DQ_TAP_RE_EL21__W 12 +#define QAM_DQ_TAP_RE_EL21__M 0xFFF +#define QAM_DQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21_TAP__B 0 +#define QAM_DQ_TAP_RE_EL21_TAP__W 12 +#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21__A 0x144004B +#define QAM_DQ_TAP_IM_EL21__W 12 +#define QAM_DQ_TAP_IM_EL21__M 0xFFF +#define QAM_DQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21_TAP__B 0 +#define QAM_DQ_TAP_IM_EL21_TAP__W 12 +#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22__A 0x144004C +#define QAM_DQ_TAP_RE_EL22__W 12 +#define QAM_DQ_TAP_RE_EL22__M 0xFFF +#define QAM_DQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22_TAP__B 0 +#define QAM_DQ_TAP_RE_EL22_TAP__W 12 +#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22__A 0x144004D +#define QAM_DQ_TAP_IM_EL22__W 12 +#define QAM_DQ_TAP_IM_EL22__M 0xFFF +#define QAM_DQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22_TAP__B 0 +#define QAM_DQ_TAP_IM_EL22_TAP__W 12 +#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23__A 0x144004E +#define QAM_DQ_TAP_RE_EL23__W 12 +#define QAM_DQ_TAP_RE_EL23__M 0xFFF +#define QAM_DQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23_TAP__B 0 +#define QAM_DQ_TAP_RE_EL23_TAP__W 12 +#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23__A 0x144004F +#define QAM_DQ_TAP_IM_EL23__W 12 +#define QAM_DQ_TAP_IM_EL23__M 0xFFF +#define QAM_DQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23_TAP__B 0 +#define QAM_DQ_TAP_IM_EL23_TAP__W 12 +#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24__A 0x1440050 +#define QAM_DQ_TAP_RE_EL24__W 12 +#define QAM_DQ_TAP_RE_EL24__M 0xFFF +#define QAM_DQ_TAP_RE_EL24__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24_TAP__B 0 +#define QAM_DQ_TAP_RE_EL24_TAP__W 12 +#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24__A 0x1440051 +#define QAM_DQ_TAP_IM_EL24__W 12 +#define QAM_DQ_TAP_IM_EL24__M 0xFFF +#define QAM_DQ_TAP_IM_EL24__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24_TAP__B 0 +#define QAM_DQ_TAP_IM_EL24_TAP__W 12 +#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25__A 0x1440052 +#define QAM_DQ_TAP_RE_EL25__W 12 +#define QAM_DQ_TAP_RE_EL25__M 0xFFF +#define QAM_DQ_TAP_RE_EL25__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25_TAP__B 0 +#define QAM_DQ_TAP_RE_EL25_TAP__W 12 +#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25__A 0x1440053 +#define QAM_DQ_TAP_IM_EL25__W 12 +#define QAM_DQ_TAP_IM_EL25__M 0xFFF +#define QAM_DQ_TAP_IM_EL25__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25_TAP__B 0 +#define QAM_DQ_TAP_IM_EL25_TAP__W 12 +#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26__A 0x1440054 +#define QAM_DQ_TAP_RE_EL26__W 12 +#define QAM_DQ_TAP_RE_EL26__M 0xFFF +#define QAM_DQ_TAP_RE_EL26__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26_TAP__B 0 +#define QAM_DQ_TAP_RE_EL26_TAP__W 12 +#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26__A 0x1440055 +#define QAM_DQ_TAP_IM_EL26__W 12 +#define QAM_DQ_TAP_IM_EL26__M 0xFFF +#define QAM_DQ_TAP_IM_EL26__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26_TAP__B 0 +#define QAM_DQ_TAP_IM_EL26_TAP__W 12 +#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27__A 0x1440056 +#define QAM_DQ_TAP_RE_EL27__W 12 +#define QAM_DQ_TAP_RE_EL27__M 0xFFF +#define QAM_DQ_TAP_RE_EL27__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27_TAP__B 0 +#define QAM_DQ_TAP_RE_EL27_TAP__W 12 +#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27__A 0x1440057 +#define QAM_DQ_TAP_IM_EL27__W 12 +#define QAM_DQ_TAP_IM_EL27__M 0xFFF +#define QAM_DQ_TAP_IM_EL27__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27_TAP__B 0 +#define QAM_DQ_TAP_IM_EL27_TAP__W 12 +#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 + + + +#define QAM_LC_COMM_EXEC__A 0x1450000 +#define QAM_LC_COMM_EXEC__W 2 +#define QAM_LC_COMM_EXEC__M 0x3 +#define QAM_LC_COMM_EXEC__PRE 0x0 +#define QAM_LC_COMM_EXEC_STOP 0x0 +#define QAM_LC_COMM_EXEC_ACTIVE 0x1 +#define QAM_LC_COMM_EXEC_HOLD 0x2 + +#define QAM_LC_COMM_MB__A 0x1450002 +#define QAM_LC_COMM_MB__W 2 +#define QAM_LC_COMM_MB__M 0x3 +#define QAM_LC_COMM_MB__PRE 0x0 +#define QAM_LC_COMM_MB_CTL__B 0 +#define QAM_LC_COMM_MB_CTL__W 1 +#define QAM_LC_COMM_MB_CTL__M 0x1 +#define QAM_LC_COMM_MB_CTL__PRE 0x0 +#define QAM_LC_COMM_MB_CTL_OFF 0x0 +#define QAM_LC_COMM_MB_CTL_ON 0x1 +#define QAM_LC_COMM_MB_OBS__B 1 +#define QAM_LC_COMM_MB_OBS__W 1 +#define QAM_LC_COMM_MB_OBS__M 0x2 +#define QAM_LC_COMM_MB_OBS__PRE 0x0 +#define QAM_LC_COMM_MB_OBS_OFF 0x0 +#define QAM_LC_COMM_MB_OBS_ON 0x2 + +#define QAM_LC_COMM_INT_REQ__A 0x1450003 +#define QAM_LC_COMM_INT_REQ__W 1 +#define QAM_LC_COMM_INT_REQ__M 0x1 +#define QAM_LC_COMM_INT_REQ__PRE 0x0 +#define QAM_LC_COMM_INT_STA__A 0x1450005 +#define QAM_LC_COMM_INT_STA__W 3 +#define QAM_LC_COMM_INT_STA__M 0x7 +#define QAM_LC_COMM_INT_STA__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_READY__B 0 +#define QAM_LC_COMM_INT_STA_READY__W 1 +#define QAM_LC_COMM_INT_STA_READY__M 0x1 +#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_MSK__A 0x1450006 +#define QAM_LC_COMM_INT_MSK__W 3 +#define QAM_LC_COMM_INT_MSK__M 0x7 +#define QAM_LC_COMM_INT_MSK__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_READY__B 0 +#define QAM_LC_COMM_INT_MSK_READY__W 1 +#define QAM_LC_COMM_INT_MSK_READY__M 0x1 +#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_STM__A 0x1450007 +#define QAM_LC_COMM_INT_STM__W 3 +#define QAM_LC_COMM_INT_STM__M 0x7 +#define QAM_LC_COMM_INT_STM__PRE 0x0 +#define QAM_LC_COMM_INT_STM_READY__B 0 +#define QAM_LC_COMM_INT_STM_READY__W 1 +#define QAM_LC_COMM_INT_STM_READY__M 0x1 +#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 +#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_MODE__A 0x1450010 +#define QAM_LC_MODE__W 4 +#define QAM_LC_MODE__M 0xF +#define QAM_LC_MODE__PRE 0xE + +#define QAM_LC_MODE_ENABLE_A__B 0 +#define QAM_LC_MODE_ENABLE_A__W 1 +#define QAM_LC_MODE_ENABLE_A__M 0x1 +#define QAM_LC_MODE_ENABLE_A__PRE 0x0 + +#define QAM_LC_MODE_ENABLE_F__B 1 +#define QAM_LC_MODE_ENABLE_F__W 1 +#define QAM_LC_MODE_ENABLE_F__M 0x2 +#define QAM_LC_MODE_ENABLE_F__PRE 0x2 + +#define QAM_LC_MODE_ENABLE_R__B 2 +#define QAM_LC_MODE_ENABLE_R__W 1 +#define QAM_LC_MODE_ENABLE_R__M 0x4 +#define QAM_LC_MODE_ENABLE_R__PRE 0x4 + +#define QAM_LC_MODE_ENABLE_PQUAL__B 3 +#define QAM_LC_MODE_ENABLE_PQUAL__W 1 +#define QAM_LC_MODE_ENABLE_PQUAL__M 0x8 +#define QAM_LC_MODE_ENABLE_PQUAL__PRE 0x8 + +#define QAM_LC_CA__A 0x1450011 +#define QAM_LC_CA__W 6 +#define QAM_LC_CA__M 0x3F +#define QAM_LC_CA__PRE 0x28 + +#define QAM_LC_CA_COEF__B 0 +#define QAM_LC_CA_COEF__W 6 +#define QAM_LC_CA_COEF__M 0x3F +#define QAM_LC_CA_COEF__PRE 0x28 + +#define QAM_LC_CF__A 0x1450012 +#define QAM_LC_CF__W 8 +#define QAM_LC_CF__M 0xFF +#define QAM_LC_CF__PRE 0x30 + +#define QAM_LC_CF_COEF__B 0 +#define QAM_LC_CF_COEF__W 8 +#define QAM_LC_CF_COEF__M 0xFF +#define QAM_LC_CF_COEF__PRE 0x30 + +#define QAM_LC_CF1__A 0x1450013 +#define QAM_LC_CF1__W 8 +#define QAM_LC_CF1__M 0xFF +#define QAM_LC_CF1__PRE 0x14 + +#define QAM_LC_CF1_COEF__B 0 +#define QAM_LC_CF1_COEF__W 8 +#define QAM_LC_CF1_COEF__M 0xFF +#define QAM_LC_CF1_COEF__PRE 0x14 + +#define QAM_LC_CP__A 0x1450014 +#define QAM_LC_CP__W 8 +#define QAM_LC_CP__M 0xFF +#define QAM_LC_CP__PRE 0x64 + +#define QAM_LC_CP_COEF__B 0 +#define QAM_LC_CP_COEF__W 8 +#define QAM_LC_CP_COEF__M 0xFF +#define QAM_LC_CP_COEF__PRE 0x64 + +#define QAM_LC_CI__A 0x1450015 +#define QAM_LC_CI__W 8 +#define QAM_LC_CI__M 0xFF +#define QAM_LC_CI__PRE 0x32 + +#define QAM_LC_CI_COEF__B 0 +#define QAM_LC_CI_COEF__W 8 +#define QAM_LC_CI_COEF__M 0xFF +#define QAM_LC_CI_COEF__PRE 0x32 + +#define QAM_LC_EP__A 0x1450016 +#define QAM_LC_EP__W 6 +#define QAM_LC_EP__M 0x3F +#define QAM_LC_EP__PRE 0x0 + +#define QAM_LC_EP_COEF__B 0 +#define QAM_LC_EP_COEF__W 6 +#define QAM_LC_EP_COEF__M 0x3F +#define QAM_LC_EP_COEF__PRE 0x0 + +#define QAM_LC_EI__A 0x1450017 +#define QAM_LC_EI__W 6 +#define QAM_LC_EI__M 0x3F +#define QAM_LC_EI__PRE 0x0 + +#define QAM_LC_EI_COEF__B 0 +#define QAM_LC_EI_COEF__W 6 +#define QAM_LC_EI_COEF__M 0x3F +#define QAM_LC_EI_COEF__PRE 0x0 + +#define QAM_LC_QUAL_TAB0__A 0x1450018 +#define QAM_LC_QUAL_TAB0__W 5 +#define QAM_LC_QUAL_TAB0__M 0x1F +#define QAM_LC_QUAL_TAB0__PRE 0x0 + +#define QAM_LC_QUAL_TAB0_VALUE__B 0 +#define QAM_LC_QUAL_TAB0_VALUE__W 5 +#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 + +#define QAM_LC_QUAL_TAB1__A 0x1450019 +#define QAM_LC_QUAL_TAB1__W 5 +#define QAM_LC_QUAL_TAB1__M 0x1F +#define QAM_LC_QUAL_TAB1__PRE 0x1 + +#define QAM_LC_QUAL_TAB1_VALUE__B 0 +#define QAM_LC_QUAL_TAB1_VALUE__W 5 +#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB2__A 0x145001A +#define QAM_LC_QUAL_TAB2__W 5 +#define QAM_LC_QUAL_TAB2__M 0x1F +#define QAM_LC_QUAL_TAB2__PRE 0x2 + +#define QAM_LC_QUAL_TAB2_VALUE__B 0 +#define QAM_LC_QUAL_TAB2_VALUE__W 5 +#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 + +#define QAM_LC_QUAL_TAB3__A 0x145001B +#define QAM_LC_QUAL_TAB3__W 5 +#define QAM_LC_QUAL_TAB3__M 0x1F +#define QAM_LC_QUAL_TAB3__PRE 0x3 + +#define QAM_LC_QUAL_TAB3_VALUE__B 0 +#define QAM_LC_QUAL_TAB3_VALUE__W 5 +#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 + +#define QAM_LC_QUAL_TAB4__A 0x145001C +#define QAM_LC_QUAL_TAB4__W 5 +#define QAM_LC_QUAL_TAB4__M 0x1F +#define QAM_LC_QUAL_TAB4__PRE 0x4 + +#define QAM_LC_QUAL_TAB4_VALUE__B 0 +#define QAM_LC_QUAL_TAB4_VALUE__W 5 +#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 + +#define QAM_LC_QUAL_TAB5__A 0x145001D +#define QAM_LC_QUAL_TAB5__W 5 +#define QAM_LC_QUAL_TAB5__M 0x1F +#define QAM_LC_QUAL_TAB5__PRE 0x5 + +#define QAM_LC_QUAL_TAB5_VALUE__B 0 +#define QAM_LC_QUAL_TAB5_VALUE__W 5 +#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 + +#define QAM_LC_QUAL_TAB6__A 0x145001E +#define QAM_LC_QUAL_TAB6__W 5 +#define QAM_LC_QUAL_TAB6__M 0x1F +#define QAM_LC_QUAL_TAB6__PRE 0x6 + +#define QAM_LC_QUAL_TAB6_VALUE__B 0 +#define QAM_LC_QUAL_TAB6_VALUE__W 5 +#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 + +#define QAM_LC_QUAL_TAB8__A 0x145001F +#define QAM_LC_QUAL_TAB8__W 5 +#define QAM_LC_QUAL_TAB8__M 0x1F +#define QAM_LC_QUAL_TAB8__PRE 0x8 + +#define QAM_LC_QUAL_TAB8_VALUE__B 0 +#define QAM_LC_QUAL_TAB8_VALUE__W 5 +#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 + +#define QAM_LC_QUAL_TAB9__A 0x1450020 +#define QAM_LC_QUAL_TAB9__W 5 +#define QAM_LC_QUAL_TAB9__M 0x1F +#define QAM_LC_QUAL_TAB9__PRE 0x9 + +#define QAM_LC_QUAL_TAB9_VALUE__B 0 +#define QAM_LC_QUAL_TAB9_VALUE__W 5 +#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 + +#define QAM_LC_QUAL_TAB10__A 0x1450021 +#define QAM_LC_QUAL_TAB10__W 5 +#define QAM_LC_QUAL_TAB10__M 0x1F +#define QAM_LC_QUAL_TAB10__PRE 0xA + +#define QAM_LC_QUAL_TAB10_VALUE__B 0 +#define QAM_LC_QUAL_TAB10_VALUE__W 5 +#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA + +#define QAM_LC_QUAL_TAB12__A 0x1450022 +#define QAM_LC_QUAL_TAB12__W 5 +#define QAM_LC_QUAL_TAB12__M 0x1F +#define QAM_LC_QUAL_TAB12__PRE 0xC + +#define QAM_LC_QUAL_TAB12_VALUE__B 0 +#define QAM_LC_QUAL_TAB12_VALUE__W 5 +#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC + +#define QAM_LC_QUAL_TAB15__A 0x1450023 +#define QAM_LC_QUAL_TAB15__W 5 +#define QAM_LC_QUAL_TAB15__M 0x1F +#define QAM_LC_QUAL_TAB15__PRE 0xF + +#define QAM_LC_QUAL_TAB15_VALUE__B 0 +#define QAM_LC_QUAL_TAB15_VALUE__W 5 +#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF + +#define QAM_LC_QUAL_TAB16__A 0x1450024 +#define QAM_LC_QUAL_TAB16__W 5 +#define QAM_LC_QUAL_TAB16__M 0x1F +#define QAM_LC_QUAL_TAB16__PRE 0x10 + +#define QAM_LC_QUAL_TAB16_VALUE__B 0 +#define QAM_LC_QUAL_TAB16_VALUE__W 5 +#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 + +#define QAM_LC_QUAL_TAB20__A 0x1450025 +#define QAM_LC_QUAL_TAB20__W 5 +#define QAM_LC_QUAL_TAB20__M 0x1F +#define QAM_LC_QUAL_TAB20__PRE 0x14 + +#define QAM_LC_QUAL_TAB20_VALUE__B 0 +#define QAM_LC_QUAL_TAB20_VALUE__W 5 +#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 + +#define QAM_LC_QUAL_TAB25__A 0x1450026 +#define QAM_LC_QUAL_TAB25__W 5 +#define QAM_LC_QUAL_TAB25__M 0x1F +#define QAM_LC_QUAL_TAB25__PRE 0x19 + +#define QAM_LC_QUAL_TAB25_VALUE__B 0 +#define QAM_LC_QUAL_TAB25_VALUE__W 5 +#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 + +#define QAM_LC_EQ_TIMING__A 0x1450027 +#define QAM_LC_EQ_TIMING__W 10 +#define QAM_LC_EQ_TIMING__M 0x3FF +#define QAM_LC_EQ_TIMING__PRE 0x0 + +#define QAM_LC_EQ_TIMING_OFFS__B 0 +#define QAM_LC_EQ_TIMING_OFFS__W 10 +#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF +#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 + +#define QAM_LC_LPF_FACTORP__A 0x1450028 +#define QAM_LC_LPF_FACTORP__W 3 +#define QAM_LC_LPF_FACTORP__M 0x7 +#define QAM_LC_LPF_FACTORP__PRE 0x3 + +#define QAM_LC_LPF_FACTORP_FACTOR__B 0 +#define QAM_LC_LPF_FACTORP_FACTOR__W 3 +#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 + +#define QAM_LC_LPF_FACTORI__A 0x1450029 +#define QAM_LC_LPF_FACTORI__W 3 +#define QAM_LC_LPF_FACTORI__M 0x7 +#define QAM_LC_LPF_FACTORI__PRE 0x3 + +#define QAM_LC_LPF_FACTORI_FACTOR__B 0 +#define QAM_LC_LPF_FACTORI_FACTOR__W 3 +#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 + +#define QAM_LC_RATE_LIMIT__A 0x145002A +#define QAM_LC_RATE_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT__PRE 0x3 + +#define QAM_LC_RATE_LIMIT_LIMIT__B 0 +#define QAM_LC_RATE_LIMIT_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 + +#define QAM_LC_SYMBOL_FREQ__A 0x145002B +#define QAM_LC_SYMBOL_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ__PRE 0x1FF + +#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 +#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x1FF + +#define QAM_LC_MTA_LENGTH__A 0x145002C +#define QAM_LC_MTA_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH__PRE 0x2 + +#define QAM_LC_MTA_LENGTH_LENGTH__B 0 +#define QAM_LC_MTA_LENGTH_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 + +#define QAM_LC_AMP_ACCU__A 0x145002D +#define QAM_LC_AMP_ACCU__W 14 +#define QAM_LC_AMP_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU__PRE 0x600 + +#define QAM_LC_AMP_ACCU_ACCU__B 0 +#define QAM_LC_AMP_ACCU_ACCU__W 14 +#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 + +#define QAM_LC_FREQ_ACCU__A 0x145002E +#define QAM_LC_FREQ_ACCU__W 10 +#define QAM_LC_FREQ_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU__PRE 0x0 + +#define QAM_LC_FREQ_ACCU_ACCU__B 0 +#define QAM_LC_FREQ_ACCU_ACCU__W 10 +#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU__A 0x145002F +#define QAM_LC_RATE_ACCU__W 10 +#define QAM_LC_RATE_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU_ACCU__B 0 +#define QAM_LC_RATE_ACCU_ACCU__W 10 +#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_AMPLITUDE__A 0x1450030 +#define QAM_LC_AMPLITUDE__W 10 +#define QAM_LC_AMPLITUDE__M 0x3FF +#define QAM_LC_AMPLITUDE__PRE 0x0 + +#define QAM_LC_AMPLITUDE_SIZE__B 0 +#define QAM_LC_AMPLITUDE_SIZE__W 10 +#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF +#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 + +#define QAM_LC_RAD_ERROR__A 0x1450031 +#define QAM_LC_RAD_ERROR__W 10 +#define QAM_LC_RAD_ERROR__M 0x3FF +#define QAM_LC_RAD_ERROR__PRE 0x0 + +#define QAM_LC_RAD_ERROR_SIZE__B 0 +#define QAM_LC_RAD_ERROR_SIZE__W 10 +#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF +#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 + +#define QAM_LC_FREQ_OFFS__A 0x1450032 +#define QAM_LC_FREQ_OFFS__W 10 +#define QAM_LC_FREQ_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS__PRE 0x0 + +#define QAM_LC_FREQ_OFFS_OFFS__B 0 +#define QAM_LC_FREQ_OFFS_OFFS__W 10 +#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 + +#define QAM_LC_PHASE_ERROR__A 0x1450033 +#define QAM_LC_PHASE_ERROR__W 10 +#define QAM_LC_PHASE_ERROR__M 0x3FF +#define QAM_LC_PHASE_ERROR__PRE 0x0 + +#define QAM_LC_PHASE_ERROR_SIZE__B 0 +#define QAM_LC_PHASE_ERROR_SIZE__W 10 +#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF +#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 + + + +#define QAM_SY_COMM_EXEC__A 0x1470000 +#define QAM_SY_COMM_EXEC__W 2 +#define QAM_SY_COMM_EXEC__M 0x3 +#define QAM_SY_COMM_EXEC__PRE 0x0 +#define QAM_SY_COMM_EXEC_STOP 0x0 +#define QAM_SY_COMM_EXEC_ACTIVE 0x1 +#define QAM_SY_COMM_EXEC_HOLD 0x2 + +#define QAM_SY_COMM_MB__A 0x1470002 +#define QAM_SY_COMM_MB__W 4 +#define QAM_SY_COMM_MB__M 0xF +#define QAM_SY_COMM_MB__PRE 0x0 +#define QAM_SY_COMM_MB_CTL__B 0 +#define QAM_SY_COMM_MB_CTL__W 1 +#define QAM_SY_COMM_MB_CTL__M 0x1 +#define QAM_SY_COMM_MB_CTL__PRE 0x0 +#define QAM_SY_COMM_MB_CTL_OFF 0x0 +#define QAM_SY_COMM_MB_CTL_ON 0x1 +#define QAM_SY_COMM_MB_OBS__B 1 +#define QAM_SY_COMM_MB_OBS__W 1 +#define QAM_SY_COMM_MB_OBS__M 0x2 +#define QAM_SY_COMM_MB_OBS__PRE 0x0 +#define QAM_SY_COMM_MB_OBS_OFF 0x0 +#define QAM_SY_COMM_MB_OBS_ON 0x2 +#define QAM_SY_COMM_MB_MUX_CTL__B 2 +#define QAM_SY_COMM_MB_MUX_CTL__W 1 +#define QAM_SY_COMM_MB_MUX_CTL__M 0x4 +#define QAM_SY_COMM_MB_MUX_CTL__PRE 0x0 +#define QAM_SY_COMM_MB_MUX_CTL_MB0 0x0 +#define QAM_SY_COMM_MB_MUX_CTL_MB1 0x4 +#define QAM_SY_COMM_MB_MUX_OBS__B 3 +#define QAM_SY_COMM_MB_MUX_OBS__W 1 +#define QAM_SY_COMM_MB_MUX_OBS__M 0x8 +#define QAM_SY_COMM_MB_MUX_OBS__PRE 0x0 +#define QAM_SY_COMM_MB_MUX_OBS_MB0 0x0 +#define QAM_SY_COMM_MB_MUX_OBS_MB1 0x8 + +#define QAM_SY_COMM_INT_REQ__A 0x1470003 +#define QAM_SY_COMM_INT_REQ__W 1 +#define QAM_SY_COMM_INT_REQ__M 0x1 +#define QAM_SY_COMM_INT_REQ__PRE 0x0 +#define QAM_SY_COMM_INT_STA__A 0x1470005 +#define QAM_SY_COMM_INT_STA__W 4 +#define QAM_SY_COMM_INT_STA__M 0xF +#define QAM_SY_COMM_INT_STA__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_MSK__A 0x1470006 +#define QAM_SY_COMM_INT_MSK__W 4 +#define QAM_SY_COMM_INT_MSK__M 0xF +#define QAM_SY_COMM_INT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_COMM_INT_STM__A 0x1470007 +#define QAM_SY_COMM_INT_STM__W 4 +#define QAM_SY_COMM_INT_STM__M 0xF +#define QAM_SY_COMM_INT_STM__PRE 0x0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_STATUS__A 0x1470010 +#define QAM_SY_STATUS__W 2 +#define QAM_SY_STATUS__M 0x3 +#define QAM_SY_STATUS__PRE 0x0 + +#define QAM_SY_STATUS_SYNC_STATE__B 0 +#define QAM_SY_STATUS_SYNC_STATE__W 2 +#define QAM_SY_STATUS_SYNC_STATE__M 0x3 +#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 + + +#define QAM_SY_TIMEOUT__A 0x1470011 +#define QAM_SY_TIMEOUT__W 16 +#define QAM_SY_TIMEOUT__M 0xFFFF +#define QAM_SY_TIMEOUT__PRE 0x3A98 + +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__W 4 +#define QAM_SY_SYNC_LWM__M 0xF +#define QAM_SY_SYNC_LWM__PRE 0x2 + +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__W 4 +#define QAM_SY_SYNC_AWM__M 0xF +#define QAM_SY_SYNC_AWM__PRE 0x3 + +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__W 4 +#define QAM_SY_SYNC_HWM__M 0xF +#define QAM_SY_SYNC_HWM__PRE 0x5 + +#define QAM_SY_UNLOCK__A 0x1470015 +#define QAM_SY_UNLOCK__W 1 +#define QAM_SY_UNLOCK__M 0x1 +#define QAM_SY_UNLOCK__PRE 0x0 +#define QAM_SY_CONTROL_WORD__A 0x1470016 +#define QAM_SY_CONTROL_WORD__W 4 +#define QAM_SY_CONTROL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD__PRE 0x0 + +#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 + + +#define QAM_SY_SP_INV__A 0x1470017 +#define QAM_SY_SP_INV__W 1 +#define QAM_SY_SP_INV__M 0x1 +#define QAM_SY_SP_INV__PRE 0x0 +#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 +#define QAM_SY_SP_INV_SPECTRUM_INV_ENA 0x1 + + + +#define QAM_VD_ISS_RAM__A 0x1480000 + + + +#define QAM_VD_QSS_RAM__A 0x1490000 + + + +#define QAM_VD_SYM_RAM__A 0x14A0000 + + + + + +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__W 2 +#define SCU_COMM_EXEC__M 0x3 +#define SCU_COMM_EXEC__PRE 0x0 +#define SCU_COMM_EXEC_STOP 0x0 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_HOLD 0x2 + +#define SCU_COMM_STATE__A 0x800001 +#define SCU_COMM_STATE__W 16 +#define SCU_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE__PRE 0x0 + +#define SCU_COMM_STATE_COMM_STATE__B 0 +#define SCU_COMM_STATE_COMM_STATE__W 16 +#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 + + + +#define SCU_TOP_COMM_EXEC__A 0x810000 +#define SCU_TOP_COMM_EXEC__W 2 +#define SCU_TOP_COMM_EXEC__M 0x3 +#define SCU_TOP_COMM_EXEC__PRE 0x0 +#define SCU_TOP_COMM_EXEC_STOP 0x0 +#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 +#define SCU_TOP_COMM_EXEC_HOLD 0x2 + + +#define SCU_TOP_COMM_STATE__A 0x810001 +#define SCU_TOP_COMM_STATE__W 16 +#define SCU_TOP_COMM_STATE__M 0xFFFF +#define SCU_TOP_COMM_STATE__PRE 0x0 +#define SCU_TOP_MWAIT_CTR__A 0x810010 +#define SCU_TOP_MWAIT_CTR__W 2 +#define SCU_TOP_MWAIT_CTR__M 0x3 +#define SCU_TOP_MWAIT_CTR__PRE 0x0 + +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 + +#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 +#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 + + + +#define SCU_LOW_RAM__A 0x820000 + +#define SCU_LOW_RAM_LOW__B 0 +#define SCU_LOW_RAM_LOW__W 16 +#define SCU_LOW_RAM_LOW__M 0xFFFF +#define SCU_LOW_RAM_LOW__PRE 0x0 + + + +#define SCU_HIGH_RAM__A 0x830000 + +#define SCU_HIGH_RAM_HIGH__B 0 +#define SCU_HIGH_RAM_HIGH__W 16 +#define SCU_HIGH_RAM_HIGH__M 0xFFFF +#define SCU_HIGH_RAM_HIGH__PRE 0x0 + + + + + + +#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF +#define SCU_RAM_DRIVER_DEBUG__W 16 +#define SCU_RAM_DRIVER_DEBUG__M 0xFFFF +#define SCU_RAM_DRIVER_DEBUG__PRE 0x0 + +#define SCU_RAM_SP__A 0x831EC0 +#define SCU_RAM_SP__W 16 +#define SCU_RAM_SP__M 0xFFFF +#define SCU_RAM_SP__PRE 0x0 + +#define SCU_RAM_QAM_NEVERLOCK_CNT__A 0x831EC1 +#define SCU_RAM_QAM_NEVERLOCK_CNT__W 16 +#define SCU_RAM_QAM_NEVERLOCK_CNT__M 0xFFFF +#define SCU_RAM_QAM_NEVERLOCK_CNT__PRE 0x0 + +#define SCU_RAM_QAM_WRONG_RATE_CNT__A 0x831EC2 +#define SCU_RAM_QAM_WRONG_RATE_CNT__W 16 +#define SCU_RAM_QAM_WRONG_RATE_CNT__M 0xFFFF +#define SCU_RAM_QAM_WRONG_RATE_CNT__PRE 0x0 + +#define SCU_RAM_QAM_NO_ACQ_CNT__A 0x831EC3 +#define SCU_RAM_QAM_NO_ACQ_CNT__W 16 +#define SCU_RAM_QAM_NO_ACQ_CNT__M 0xFFFF +#define SCU_RAM_QAM_NO_ACQ_CNT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 +#define SCU_RAM_QAM_FSM_STEP_PERIOD__W 16 +#define SCU_RAM_QAM_FSM_STEP_PERIOD__M 0xFFFF +#define SCU_RAM_QAM_FSM_STEP_PERIOD__PRE 0x4B0 + +#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC5 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x8000 + +#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC6 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__W 2 +#define SCU_RAM_GPIO__M 0x3 +#define SCU_RAM_GPIO__PRE 0x0 + +#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 +#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 +#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 +#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 + +#define SCU_RAM_GPIO_VSYNC_IND__B 1 +#define SCU_RAM_GPIO_VSYNC_IND__W 1 +#define SCU_RAM_GPIO_VSYNC_IND__M 0x2 +#define SCU_RAM_GPIO_VSYNC_IND__PRE 0x0 +#define SCU_RAM_GPIO_VSYNC_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_VSYNC_IND_ENABLE 0x2 + +#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF +#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 + + +#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x8000 + +#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA +#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 + +#define SCU_RAM_INHIBIT_1__A 0x831ECC +#define SCU_RAM_INHIBIT_1__W 16 +#define SCU_RAM_INHIBIT_1__M 0xFFFF +#define SCU_RAM_INHIBIT_1__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_0__A 0x831ECD +#define SCU_RAM_HTOL_BUF_0__W 16 +#define SCU_RAM_HTOL_BUF_0__M 0xFFFF +#define SCU_RAM_HTOL_BUF_0__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_1__A 0x831ECE +#define SCU_RAM_HTOL_BUF_1__W 16 +#define SCU_RAM_HTOL_BUF_1__M 0xFFFF +#define SCU_RAM_HTOL_BUF_1__PRE 0x0 + +#define SCU_RAM_INHIBIT_2__A 0x831ECF +#define SCU_RAM_INHIBIT_2__W 16 +#define SCU_RAM_INHIBIT_2__M 0xFFFF +#define SCU_RAM_INHIBIT_2__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 +#define SCU_RAM_TR_SHORT_BUF_0__W 16 +#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 +#define SCU_RAM_TR_SHORT_BUF_1__W 16 +#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 +#define SCU_RAM_TR_LONG_BUF_0__W 16 +#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 +#define SCU_RAM_TR_LONG_BUF_1__W 16 +#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 +#define SCU_RAM_TR_LONG_BUF_2__W 16 +#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 +#define SCU_RAM_TR_LONG_BUF_3__W 16 +#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 +#define SCU_RAM_TR_LONG_BUF_4__W 16 +#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 +#define SCU_RAM_TR_LONG_BUF_5__W 16 +#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 +#define SCU_RAM_TR_LONG_BUF_6__W 16 +#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 +#define SCU_RAM_TR_LONG_BUF_7__W 16 +#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA +#define SCU_RAM_TR_LONG_BUF_8__W 16 +#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB +#define SCU_RAM_TR_LONG_BUF_9__W 16 +#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC +#define SCU_RAM_TR_LONG_BUF_10__W 16 +#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD +#define SCU_RAM_TR_LONG_BUF_11__W 16 +#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE +#define SCU_RAM_TR_LONG_BUF_12__W 16 +#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF +#define SCU_RAM_TR_LONG_BUF_13__W 16 +#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 +#define SCU_RAM_TR_LONG_BUF_14__W 16 +#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 +#define SCU_RAM_TR_LONG_BUF_15__W 16 +#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 +#define SCU_RAM_TR_LONG_BUF_16__W 16 +#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 +#define SCU_RAM_TR_LONG_BUF_17__W 16 +#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 +#define SCU_RAM_TR_LONG_BUF_18__W 16 +#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 +#define SCU_RAM_TR_LONG_BUF_19__W 16 +#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 +#define SCU_RAM_TR_LONG_BUF_20__W 16 +#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 +#define SCU_RAM_TR_LONG_BUF_21__W 16 +#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 +#define SCU_RAM_TR_LONG_BUF_22__W 16 +#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 +#define SCU_RAM_TR_LONG_BUF_23__W 16 +#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA +#define SCU_RAM_TR_LONG_BUF_24__W 16 +#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB +#define SCU_RAM_TR_LONG_BUF_25__W 16 +#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC +#define SCU_RAM_TR_LONG_BUF_26__W 16 +#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED +#define SCU_RAM_TR_LONG_BUF_27__W 16 +#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE +#define SCU_RAM_TR_LONG_BUF_28__W 16 +#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF +#define SCU_RAM_TR_LONG_BUF_29__W 16 +#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 +#define SCU_RAM_TR_LONG_BUF_30__W 16 +#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 +#define SCU_RAM_TR_LONG_BUF_31__W 16 +#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 +#define SCU_RAM_ATV_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 +#define SCU_RAM_ATV_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN__PRE 0x7FF + +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x7FF + +#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 +#define SCU_RAM_ATV_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 +#define SCU_RAM_ATV_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 + +#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 +#define SCU_RAM_ATV_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 +#define SCU_RAM_ATV_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 +#define SCU_RAM_ATV_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 +#define SCU_RAM_ATV_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF__A 0x831EFA +#define SCU_RAM_ATV_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 +#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB +#define SCU_RAM_ATV_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x64 + +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x64 + +#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC +#define SCU_RAM_ATV_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x104 + +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x104 + +#define SCU_RAM_ATV_BP_CNT__A 0x831EFD +#define SCU_RAM_ATV_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE +#define SCU_RAM_ATV_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF +#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x445 + +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x445 + +#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 +#define SCU_RAM_ATV_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x223 + +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x223 + + +#define SCU_RAM_OFDM_AGC_POW_TGT__A 0x831F01 +#define SCU_RAM_OFDM_AGC_POW_TGT__W 15 +#define SCU_RAM_OFDM_AGC_POW_TGT__M 0x7FFF +#define SCU_RAM_OFDM_AGC_POW_TGT__PRE 0x5848 + +#define SCU_RAM_OFDM_RSV_01__A 0x831F02 +#define SCU_RAM_OFDM_RSV_01__W 16 +#define SCU_RAM_OFDM_RSV_01__M 0xFFFF +#define SCU_RAM_OFDM_RSV_01__PRE 0x0 + +#define SCU_RAM_OFDM_RSV_02__A 0x831F03 +#define SCU_RAM_OFDM_RSV_02__W 16 +#define SCU_RAM_OFDM_RSV_02__M 0xFFFF +#define SCU_RAM_OFDM_RSV_02__PRE 0x0 +#define SCU_RAM_FEC_PRE_RS_BER__A 0x831F04 +#define SCU_RAM_FEC_PRE_RS_BER__W 16 +#define SCU_RAM_FEC_PRE_RS_BER__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER__PRE 0x0 + +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__B 0 +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__W 16 +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__PRE 0x0 + +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__W 16 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__PRE 0x0 + +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__B 0 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__W 16 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_LINE_CNT__A 0x831F06 +#define SCU_RAM_ATV_VSYNC_LINE_CNT__W 16 +#define SCU_RAM_ATV_VSYNC_LINE_CNT__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_LINE_CNT__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__W 16 +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_PERIOD__A 0x831F07 +#define SCU_RAM_ATV_VSYNC_PERIOD__W 16 +#define SCU_RAM_ATV_VSYNC_PERIOD__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_PERIOD__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__W 16 +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__PRE 0x0 + +#define SCU_RAM_FREE_7944__A 0x831F08 +#define SCU_RAM_FREE_7944__W 16 +#define SCU_RAM_FREE_7944__M 0xFFFF +#define SCU_RAM_FREE_7944__PRE 0x0 + +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7945__A 0x831F09 +#define SCU_RAM_FREE_7945__W 16 +#define SCU_RAM_FREE_7945__M 0xFFFF +#define SCU_RAM_FREE_7945__PRE 0x0 + +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7946__A 0x831F0A +#define SCU_RAM_FREE_7946__W 16 +#define SCU_RAM_FREE_7946__M 0xFFFF +#define SCU_RAM_FREE_7946__PRE 0x0 + +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7947__A 0x831F0B +#define SCU_RAM_FREE_7947__W 16 +#define SCU_RAM_FREE_7947__M 0xFFFF +#define SCU_RAM_FREE_7947__PRE 0x0 + +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7948__A 0x831F0C +#define SCU_RAM_FREE_7948__W 16 +#define SCU_RAM_FREE_7948__M 0xFFFF +#define SCU_RAM_FREE_7948__PRE 0x0 + +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7949__A 0x831F0D +#define SCU_RAM_FREE_7949__W 16 +#define SCU_RAM_FREE_7949__M 0xFFFF +#define SCU_RAM_FREE_7949__PRE 0x0 + +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7950__A 0x831F0E +#define SCU_RAM_FREE_7950__W 16 +#define SCU_RAM_FREE_7950__M 0xFFFF +#define SCU_RAM_FREE_7950__PRE 0x0 + +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7951__A 0x831F0F +#define SCU_RAM_FREE_7951__W 16 +#define SCU_RAM_FREE_7951__M 0xFFFF +#define SCU_RAM_FREE_7951__PRE 0x0 + +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7952__A 0x831F10 +#define SCU_RAM_FREE_7952__W 16 +#define SCU_RAM_FREE_7952__M 0xFFFF +#define SCU_RAM_FREE_7952__PRE 0x0 + +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7953__A 0x831F11 +#define SCU_RAM_FREE_7953__W 16 +#define SCU_RAM_FREE_7953__M 0xFFFF +#define SCU_RAM_FREE_7953__PRE 0x0 + +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7954__A 0x831F12 +#define SCU_RAM_FREE_7954__W 16 +#define SCU_RAM_FREE_7954__M 0xFFFF +#define SCU_RAM_FREE_7954__PRE 0x0 + +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7955__A 0x831F13 +#define SCU_RAM_FREE_7955__W 16 +#define SCU_RAM_FREE_7955__M 0xFFFF +#define SCU_RAM_FREE_7955__PRE 0x0 + +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__PRE 0x0 + + +#define SCU_RAM_ADC_COMP_CONTROL__A 0x831F14 +#define SCU_RAM_ADC_COMP_CONTROL__W 3 +#define SCU_RAM_ADC_COMP_CONTROL__M 0x7 +#define SCU_RAM_ADC_COMP_CONTROL__PRE 0x0 +#define SCU_RAM_ADC_COMP_CONTROL_CONFIG 0x0 +#define SCU_RAM_ADC_COMP_CONTROL_DO_AGC 0x1 +#define SCU_RAM_ADC_COMP_CONTROL_SET_ADJUST 0x2 +#define SCU_RAM_ADC_COMP_CONTROL_SET_ACTIVE 0x3 + + +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x32 + +#define SCU_RAM_AGC_KI_CYCCNT__A 0x831F16 +#define SCU_RAM_AGC_KI_CYCCNT__W 16 +#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 +#define SCU_RAM_AGC_KI_CYCLEN__W 16 +#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x1F4 + +#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 +#define SCU_RAM_AGC_SNS_CYCLEN__W 16 +#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x1F4 + +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x3FF + +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0xFC01 + +#define SCU_RAM_AGC_RF_MAX__A 0x831F1B +#define SCU_RAM_AGC_RF_MAX__W 15 +#define SCU_RAM_AGC_RF_MAX__M 0x7FFF +#define SCU_RAM_AGC_RF_MAX__PRE 0x7FFF +#define SCU_RAM_FREE_7964__A 0x831F1C +#define SCU_RAM_FREE_7964__W 16 +#define SCU_RAM_FREE_7964__M 0xFFFF +#define SCU_RAM_FREE_7964__PRE 0x0 + +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7965__A 0x831F1D +#define SCU_RAM_FREE_7965__W 16 +#define SCU_RAM_FREE_7965__M 0xFFFF +#define SCU_RAM_FREE_7965__PRE 0x0 + +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7966__A 0x831F1E +#define SCU_RAM_FREE_7966__W 16 +#define SCU_RAM_FREE_7966__M 0xFFFF +#define SCU_RAM_FREE_7966__PRE 0x0 + +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7967__A 0x831F1F +#define SCU_RAM_FREE_7967__W 16 +#define SCU_RAM_FREE_7967__M 0xFFFF +#define SCU_RAM_FREE_7967__PRE 0x0 + +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_MIRRORING__A 0x831F20 +#define SCU_RAM_QAM_PARAM_MIRRORING__W 8 +#define SCU_RAM_QAM_PARAM_MIRRORING__M 0xFF +#define SCU_RAM_QAM_PARAM_MIRRORING__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__B 0 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__W 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__M 0x1 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__PRE 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET_NORMAL 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET_MIRRORED 0x1 + +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__B 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__W 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__M 0x2 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__PRE 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_OFF 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_ON 0x2 + +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__B 2 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__W 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__M 0x4 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__PRE 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET_NORMAL 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET_MIRRORED 0x4 + +#define SCU_RAM_QAM_PARAM_OPTIONS__A 0x831F21 +#define SCU_RAM_QAM_PARAM_OPTIONS__W 8 +#define SCU_RAM_QAM_PARAM_OPTIONS__M 0xFF +#define SCU_RAM_QAM_PARAM_OPTIONS__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__B 0 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__W 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__M 0x1 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__PRE 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET_NORMAL 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET_MIRRORED 0x1 + +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__B 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__W 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__M 0x2 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__PRE 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_OFF 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_ON 0x2 + +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__B 4 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__W 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__M 0x10 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__PRE 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_EXTENDED 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_NORMAL 0x10 + +#define SCU_RAM_FREE_7970__A 0x831F22 +#define SCU_RAM_FREE_7970__W 16 +#define SCU_RAM_FREE_7970__M 0xFFFF +#define SCU_RAM_FREE_7970__PRE 0x0 + +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7971__A 0x831F23 +#define SCU_RAM_FREE_7971__W 16 +#define SCU_RAM_FREE_7971__M 0xFFFF +#define SCU_RAM_FREE_7971__PRE 0x0 + +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG__A 0x831F24 +#define SCU_RAM_AGC_CONFIG__W 16 +#define SCU_RAM_AGC_CONFIG__M 0xFFFF +#define SCU_RAM_AGC_CONFIG__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__B 0 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__W 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__B 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__W 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__B 2 +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__W 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__M 0x4 +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__B 8 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__W 1 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__B 9 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__W 1 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI__A 0x831F25 +#define SCU_RAM_AGC_KI__W 15 +#define SCU_RAM_AGC_KI__M 0x7FFF +#define SCU_RAM_AGC_KI__PRE 0x22A + +#define SCU_RAM_AGC_KI_DGAIN__B 0 +#define SCU_RAM_AGC_KI_DGAIN__W 4 +#define SCU_RAM_AGC_KI_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_DGAIN__PRE 0xA + +#define SCU_RAM_AGC_KI_RF__B 4 +#define SCU_RAM_AGC_KI_RF__W 4 +#define SCU_RAM_AGC_KI_RF__M 0xF0 +#define SCU_RAM_AGC_KI_RF__PRE 0x20 + +#define SCU_RAM_AGC_KI_IF__B 8 +#define SCU_RAM_AGC_KI_IF__W 4 +#define SCU_RAM_AGC_KI_IF__M 0xF00 +#define SCU_RAM_AGC_KI_IF__PRE 0x200 + +#define SCU_RAM_AGC_KI_RED__A 0x831F26 +#define SCU_RAM_AGC_KI_RED__W 6 +#define SCU_RAM_AGC_KI_RED__M 0x3F +#define SCU_RAM_AGC_KI_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 +#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 +#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 +#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC +#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 + + +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 +#define SCU_RAM_AGC_KI_MINGAIN__W 16 +#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x8000 + +#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 +#define SCU_RAM_AGC_KI_MAXGAIN__W 16 +#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 +#define SCU_RAM_AGC_KI_MIN__A 0x831F2B +#define SCU_RAM_AGC_KI_MIN__W 12 +#define SCU_RAM_AGC_KI_MIN__M 0xFFF +#define SCU_RAM_AGC_KI_MIN__PRE 0x111 + +#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x1 + +#define SCU_RAM_AGC_KI_MIN_RF__B 4 +#define SCU_RAM_AGC_KI_MIN_RF__W 4 +#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x10 + +#define SCU_RAM_AGC_KI_MIN_IF__B 8 +#define SCU_RAM_AGC_KI_MIN_IF__W 4 +#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x100 + +#define SCU_RAM_AGC_KI_MAX__A 0x831F2C +#define SCU_RAM_AGC_KI_MAX__W 12 +#define SCU_RAM_AGC_KI_MAX__M 0xFFF +#define SCU_RAM_AGC_KI_MAX__PRE 0xFFF + +#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0xF + +#define SCU_RAM_AGC_KI_MAX_RF__B 4 +#define SCU_RAM_AGC_KI_MAX_RF__W 4 +#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MAX_RF__PRE 0xF0 + +#define SCU_RAM_AGC_KI_MAX_IF__B 8 +#define SCU_RAM_AGC_KI_MAX_IF__W 4 +#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MAX_IF__PRE 0xF00 + + +#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D +#define SCU_RAM_AGC_CLP_SUM__W 16 +#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E +#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 +#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x8 + +#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F +#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 +#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x400 + +#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 +#define SCU_RAM_AGC_CLP_CYCLEN__W 16 +#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x1F4 + +#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 +#define SCU_RAM_AGC_CLP_CYCCNT__W 16 +#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 +#define SCU_RAM_AGC_CLP_DIR_TO__W 8 +#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0xFC + +#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 +#define SCU_RAM_AGC_CLP_DIR_WD__W 8 +#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 +#define SCU_RAM_AGC_CLP_DIR_STP__W 16 +#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x1 + +#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 +#define SCU_RAM_AGC_SNS_SUM__W 16 +#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 +#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 +#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x8 + +#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 +#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 +#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x400 + +#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 +#define SCU_RAM_AGC_SNS_CYCCNT__W 16 +#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 +#define SCU_RAM_AGC_SNS_DIR_TO__W 8 +#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0xFC + +#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A +#define SCU_RAM_AGC_SNS_DIR_WD__W 8 +#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B +#define SCU_RAM_AGC_SNS_DIR_STP__W 16 +#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x1 + +#define SCU_RAM_AGC_INGAIN__A 0x831F3C +#define SCU_RAM_AGC_INGAIN__W 16 +#define SCU_RAM_AGC_INGAIN__M 0xFFFF +#define SCU_RAM_AGC_INGAIN__PRE 0x708 + +#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D +#define SCU_RAM_AGC_INGAIN_TGT__W 15 +#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x708 + +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E +#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x708 + +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F +#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x3FFF + +#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 +#define SCU_RAM_AGC_IF_IACCU_HI__W 16 +#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 +#define SCU_RAM_AGC_IF_IACCU_LO__W 8 +#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x2008 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x251C + +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 +#define SCU_RAM_AGC_RF_IACCU_HI__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 +#define SCU_RAM_AGC_RF_IACCU_LO__W 8 +#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 +#define SCU_RAM_ATV_STANDARD__A 0x831F48 +#define SCU_RAM_ATV_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD__PRE 0x2 + +#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 +#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x2 +#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 +#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 +#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 +#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 +#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 +#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 +#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA +#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 + +#define SCU_RAM_ATV_DETECT__A 0x831F49 +#define SCU_RAM_ATV_DETECT__W 1 +#define SCU_RAM_ATV_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_DETECT__B 0 +#define SCU_RAM_ATV_DETECT_DETECT__W 1 +#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1 + +#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A +#define SCU_RAM_ATV_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH__PRE 0x7F + +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x7F + +#define SCU_RAM_ATV_LOCK__A 0x831F4B +#define SCU_RAM_ATV_LOCK__W 2 +#define SCU_RAM_ATV_LOCK__M 0x3 +#define SCU_RAM_ATV_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 + +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 + +#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C +#define SCU_RAM_ATV_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D +#define SCU_RAM_ATV_AGC_MODE__W 8 +#define SCU_RAM_ATV_AGC_MODE__M 0xFF +#define SCU_RAM_ATV_AGC_MODE__PRE 0x50 + +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 + +#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 + +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x10 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 + +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x40 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 + +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 + + +#define SCU_RAM_ATV_RSV_01__A 0x831F4E +#define SCU_RAM_ATV_RSV_01__W 16 +#define SCU_RAM_ATV_RSV_01__M 0xFFFF +#define SCU_RAM_ATV_RSV_01__PRE 0x0 + +#define SCU_RAM_ATV_RSV_02__A 0x831F4F +#define SCU_RAM_ATV_RSV_02__W 16 +#define SCU_RAM_ATV_RSV_02__M 0xFFFF +#define SCU_RAM_ATV_RSV_02__PRE 0x0 + +#define SCU_RAM_ATV_RSV_03__A 0x831F50 +#define SCU_RAM_ATV_RSV_03__W 16 +#define SCU_RAM_ATV_RSV_03__M 0xFFFF +#define SCU_RAM_ATV_RSV_03__PRE 0x0 + +#define SCU_RAM_ATV_RSV_04__A 0x831F51 +#define SCU_RAM_ATV_RSV_04__W 16 +#define SCU_RAM_ATV_RSV_04__M 0xFFFF +#define SCU_RAM_ATV_RSV_04__PRE 0x0 +#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 +#define SCU_RAM_ATV_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0xA + +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0xA + +#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 +#define SCU_RAM_ATV_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x2BC + +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x2BC +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A + +#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 +#define SCU_RAM_ATV_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 +#define SCU_RAM_ATV_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_PERIOD__A 0x831F56 +#define SCU_RAM_ATV_BPC_REF_PERIOD__W 16 +#define SCU_RAM_ATV_BPC_REF_PERIOD__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_PERIOD__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__B 0 +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__W 16 +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_CNT__A 0x831F57 +#define SCU_RAM_ATV_BPC_REF_CNT__W 16 +#define SCU_RAM_ATV_BPC_REF_CNT__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__B 0 +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__W 16 +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_07__A 0x831F58 +#define SCU_RAM_ATV_RSV_07__W 16 +#define SCU_RAM_ATV_RSV_07__M 0xFFFF +#define SCU_RAM_ATV_RSV_07__PRE 0x0 + +#define SCU_RAM_ATV_RSV_08__A 0x831F59 +#define SCU_RAM_ATV_RSV_08__W 16 +#define SCU_RAM_ATV_RSV_08__M 0xFFFF +#define SCU_RAM_ATV_RSV_08__PRE 0x0 + +#define SCU_RAM_ATV_RSV_09__A 0x831F5A +#define SCU_RAM_ATV_RSV_09__W 16 +#define SCU_RAM_ATV_RSV_09__M 0xFFFF +#define SCU_RAM_ATV_RSV_09__PRE 0x0 + +#define SCU_RAM_ATV_RSV_10__A 0x831F5B +#define SCU_RAM_ATV_RSV_10__W 16 +#define SCU_RAM_ATV_RSV_10__M 0xFFFF +#define SCU_RAM_ATV_RSV_10__PRE 0x0 + +#define SCU_RAM_ATV_RSV_11__A 0x831F5C +#define SCU_RAM_ATV_RSV_11__W 16 +#define SCU_RAM_ATV_RSV_11__M 0xFFFF +#define SCU_RAM_ATV_RSV_11__PRE 0x0 + +#define SCU_RAM_ATV_RSV_12__A 0x831F5D +#define SCU_RAM_ATV_RSV_12__W 16 +#define SCU_RAM_ATV_RSV_12__M 0xFFFF +#define SCU_RAM_ATV_RSV_12__PRE 0x0 +#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E +#define SCU_RAM_ATV_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x1000 + +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x1000 + +#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F +#define SCU_RAM_ATV_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_13__A 0x831F60 +#define SCU_RAM_ATV_RSV_13__W 16 +#define SCU_RAM_ATV_RSV_13__M 0xFFFF +#define SCU_RAM_ATV_RSV_13__PRE 0x0 + +#define SCU_RAM_ATV_RSV_14__A 0x831F61 +#define SCU_RAM_ATV_RSV_14__W 16 +#define SCU_RAM_ATV_RSV_14__M 0xFFFF +#define SCU_RAM_ATV_RSV_14__PRE 0x0 + +#define SCU_RAM_ATV_RSV_15__A 0x831F62 +#define SCU_RAM_ATV_RSV_15__W 16 +#define SCU_RAM_ATV_RSV_15__M 0xFFFF +#define SCU_RAM_ATV_RSV_15__PRE 0x0 + +#define SCU_RAM_ATV_RSV_16__A 0x831F63 +#define SCU_RAM_ATV_RSV_16__W 16 +#define SCU_RAM_ATV_RSV_16__M 0xFFFF +#define SCU_RAM_ATV_RSV_16__PRE 0x0 +#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 +#define SCU_RAM_ATV_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT__PRE 0x7 + +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x7 + +#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 +#define SCU_RAM_ATV_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN__PRE 0x80 + +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x80 + + +#define SCU_RAM_ATV_RSV_17__A 0x831F66 +#define SCU_RAM_ATV_RSV_17__W 16 +#define SCU_RAM_ATV_RSV_17__M 0xFFFF +#define SCU_RAM_ATV_RSV_17__PRE 0x0 + +#define SCU_RAM_ATV_RSV_18__A 0x831F67 +#define SCU_RAM_ATV_RSV_18__W 16 +#define SCU_RAM_ATV_RSV_18__M 0xFFFF +#define SCU_RAM_ATV_RSV_18__PRE 0x0 + +#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 +#define SCU_RAM_ATV_RATE_OFS__W 12 +#define SCU_RAM_ATV_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_LO_INCR__A 0x831F69 +#define SCU_RAM_ATV_LO_INCR__W 12 +#define SCU_RAM_ATV_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A +#define SCU_RAM_ATV_IIR_CRIT__W 12 +#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF +#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 + +#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B +#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 +#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C +#define SCU_RAM_ATV_DEF_LO_INCR__W 12 +#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D +#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 +#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E +#define SCU_RAM_ATV_MOD_CONTROL__W 12 +#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF +#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 + +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F +#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x667 + +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__PRE 0x667 + +#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 +#define SCU_RAM_ATV_BPC_KI_MAX__W 12 +#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x337 + +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__PRE 0x337 + +#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 +#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x447 + +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__PRE 0x447 + +#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 +#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x225 + +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x225 + +#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 +#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x14 + +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x14 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 + +#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 +#define SCU_RAM_QAM_PARAM_ANNEX__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x1 + +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x1 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x5 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x5 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x1 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x1 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 +#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 +#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF +#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x13 + +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x13 + +#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A +#define SCU_RAM_QAM_WR_RSV_0__W 16 +#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D +#define SCU_RAM_QAM_WR_RSV_5__W 16 +#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E +#define SCU_RAM_QAM_WR_RSV_6__W 16 +#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F +#define SCU_RAM_QAM_WR_RSV_7__W 16 +#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 +#define SCU_RAM_QAM_WR_RSV_8__W 16 +#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 +#define SCU_RAM_QAM_WR_RSV_9__W 16 +#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 +#define SCU_RAM_QAM_WR_RSV_10__W 16 +#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 +#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x258 + +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x258 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B +#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D +#define SCU_RAM_QAM_FSM_ATH__W 16 +#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 +#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 +#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__W 16 +#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH__PRE 0x4B + +#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x4B +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D + +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__W 16 +#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH__PRE 0x3C + +#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x3C +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 + +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__W 16 +#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH__PRE 0x64 + +#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x64 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 + +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__W 16 +#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH__PRE 0x6E + +#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x6E +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 + +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__W 16 +#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH__PRE 0x50 + +#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x50 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C + +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__W 16 +#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH__PRE 0x96 + +#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x96 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 + +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x28 + +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x28 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 + +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0xF + +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0xF +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 + +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x4 + +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x4 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 + +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__W 16 +#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 +#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__W 16 +#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_FINE__PRE 0xF + +#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0xF + +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__W 16 +#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x64 + +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x64 + +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x1E + +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x1E + +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__W 16 +#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x5 + +#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x5 + +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__W 16 +#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x32 + +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x32 + +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x1E + +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x1E + +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__W 16 +#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x5 + +#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x5 + +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__W 16 +#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__W 16 +#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_FINE__PRE 0xC + +#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0xC + +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__W 16 +#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__W 16 +#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_FINE__PRE 0xC + +#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0xC + +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 + +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 + +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 + +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 + +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 + +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 + +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 + +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 + +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0xAA00 + +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0xAA00 + +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 + +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE + +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A + +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 + +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 + +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF + +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 + +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 + +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 + +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D + +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 + +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 + +#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 +#define SCU_RAM_QAM_CTL_ENA__W 16 +#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF +#define SCU_RAM_QAM_CTL_ENA__PRE 0x7FF + +#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 +#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 +#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 +#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x1 + +#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 +#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x2 + +#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 +#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 +#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x4 + +#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 +#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 +#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 +#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x8 + +#define SCU_RAM_QAM_CTL_ENA_LC__B 4 +#define SCU_RAM_QAM_CTL_ENA_LC__W 1 +#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 +#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x10 + +#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 +#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 +#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 +#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x20 + +#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 +#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 +#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 +#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x40 + +#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 +#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 +#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 +#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x80 + +#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x100 + +#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x200 + +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x400 + +#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 +#define SCU_RAM_QAM_WR_RSV_1__W 16 +#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 +#define SCU_RAM_QAM_WR_RSV_2__W 16 +#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 +#define SCU_RAM_QAM_WR_RSV_3__W 16 +#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x1 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x1 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE + +#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 +#define SCU_RAM_QAM_RD_RSV_4__W 16 +#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED__A 0x831FBA +#define SCU_RAM_QAM_LOCKED__W 16 +#define SCU_RAM_QAM_LOCKED__M 0xFFFF +#define SCU_RAM_QAM_LOCKED__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF +#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 + +#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 +#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 +#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 +#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 + +#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB +#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC +#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD +#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE +#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF +#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 +#define SCU_RAM_QAM_TASKLETS_RUN__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 +#define SCU_RAM_QAM_RD_RSV_5__W 16 +#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 +#define SCU_RAM_QAM_RD_RSV_6__W 16 +#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 +#define SCU_RAM_QAM_RD_RSV_7__W 16 +#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 +#define SCU_RAM_QAM_RD_RSV_8__W 16 +#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 +#define SCU_RAM_QAM_RD_RSV_9__W 16 +#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 +#define SCU_RAM_QAM_RD_RSV_10__W 16 +#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA +#define SCU_RAM_QAM_FSM_STATE__W 4 +#define SCU_RAM_QAM_FSM_STATE__M 0xF +#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB +#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 13 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FFF +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__B 9 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__M 0x200 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__B 10 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__M 0x400 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__B 11 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__M 0x800 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__B 12 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__M 0x1000 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD +#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x46 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x46 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x1E + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x1E + +#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF +#define SCU_RAM_QAM_ERR_STATE__W 4 +#define SCU_RAM_QAM_ERR_STATE__M 0xF +#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 +#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 +#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF +#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 +#define SCU_RAM_QAM_EQ_LOCK__W 1 +#define SCU_RAM_QAM_EQ_LOCK__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 +#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 +#define SCU_RAM_QAM_EQ_STATE__W 16 +#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 +#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 +#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 +#define SCU_RAM_QAM_RD_RSV_0__W 16 +#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 +#define SCU_RAM_QAM_RD_RSV_1__W 16 +#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 +#define SCU_RAM_QAM_RD_RSV_2__W 16 +#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 +#define SCU_RAM_QAM_RD_RSV_3__W 16 +#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 + + +#define SCU_RAM_FREE_8151__A 0x831FD7 +#define SCU_RAM_FREE_8151__W 16 +#define SCU_RAM_FREE_8151__M 0xFFFF +#define SCU_RAM_FREE_8151__PRE 0x0 + +#define SCU_RAM_FREE_8152__A 0x831FD8 +#define SCU_RAM_FREE_8152__W 16 +#define SCU_RAM_FREE_8152__M 0xFFFF +#define SCU_RAM_FREE_8152__PRE 0x0 + +#define SCU_RAM_FREE_8153__A 0x831FD9 +#define SCU_RAM_FREE_8153__W 16 +#define SCU_RAM_FREE_8153__M 0xFFFF +#define SCU_RAM_FREE_8153__PRE 0x0 + +#define SCU_RAM_FREE_8154__A 0x831FDA +#define SCU_RAM_FREE_8154__W 16 +#define SCU_RAM_FREE_8154__M 0xFFFF +#define SCU_RAM_FREE_8154__PRE 0x0 + +#define SCU_RAM_FREE_8155__A 0x831FDB +#define SCU_RAM_FREE_8155__W 16 +#define SCU_RAM_FREE_8155__M 0xFFFF +#define SCU_RAM_FREE_8155__PRE 0x0 + +#define SCU_RAM_FREE_8156__A 0x831FDC +#define SCU_RAM_FREE_8156__W 16 +#define SCU_RAM_FREE_8156__M 0xFFFF +#define SCU_RAM_FREE_8156__PRE 0x0 + +#define SCU_RAM_FREE_8157__A 0x831FDD +#define SCU_RAM_FREE_8157__W 16 +#define SCU_RAM_FREE_8157__M 0xFFFF +#define SCU_RAM_FREE_8157__PRE 0x0 + +#define SCU_RAM_FREE_8158__A 0x831FDE +#define SCU_RAM_FREE_8158__W 16 +#define SCU_RAM_FREE_8158__M 0xFFFF +#define SCU_RAM_FREE_8158__PRE 0x0 + +#define SCU_RAM_FREE_8159__A 0x831FDF +#define SCU_RAM_FREE_8159__W 16 +#define SCU_RAM_FREE_8159__M 0xFFFF +#define SCU_RAM_FREE_8159__PRE 0x0 + +#define SCU_RAM_FREE_8160__A 0x831FE0 +#define SCU_RAM_FREE_8160__W 16 +#define SCU_RAM_FREE_8160__M 0xFFFF +#define SCU_RAM_FREE_8160__PRE 0x0 + +#define SCU_RAM_FREE_8161__A 0x831FE1 +#define SCU_RAM_FREE_8161__W 16 +#define SCU_RAM_FREE_8161__M 0xFFFF +#define SCU_RAM_FREE_8161__PRE 0x0 + +#define SCU_RAM_FREE_8162__A 0x831FE2 +#define SCU_RAM_FREE_8162__W 16 +#define SCU_RAM_FREE_8162__M 0xFFFF +#define SCU_RAM_FREE_8162__PRE 0x0 + +#define SCU_RAM_FREE_8163__A 0x831FE3 +#define SCU_RAM_FREE_8163__W 16 +#define SCU_RAM_FREE_8163__M 0xFFFF +#define SCU_RAM_FREE_8163__PRE 0x0 + +#define SCU_RAM_FREE_8164__A 0x831FE4 +#define SCU_RAM_FREE_8164__W 16 +#define SCU_RAM_FREE_8164__M 0xFFFF +#define SCU_RAM_FREE_8164__PRE 0x0 + +#define SCU_RAM_FREE_8165__A 0x831FE5 +#define SCU_RAM_FREE_8165__W 16 +#define SCU_RAM_FREE_8165__M 0xFFFF +#define SCU_RAM_FREE_8165__PRE 0x0 + +#define SCU_RAM_FREE_8166__A 0x831FE6 +#define SCU_RAM_FREE_8166__W 16 +#define SCU_RAM_FREE_8166__M 0xFFFF +#define SCU_RAM_FREE_8166__PRE 0x0 + +#define SCU_RAM_FREE_8167__A 0x831FE7 +#define SCU_RAM_FREE_8167__W 16 +#define SCU_RAM_FREE_8167__M 0xFFFF +#define SCU_RAM_FREE_8167__PRE 0x0 + +#define SCU_RAM_FREE_8168__A 0x831FE8 +#define SCU_RAM_FREE_8168__W 16 +#define SCU_RAM_FREE_8168__M 0xFFFF +#define SCU_RAM_FREE_8168__PRE 0x0 + +#define SCU_RAM_FREE_8169__A 0x831FE9 +#define SCU_RAM_FREE_8169__W 16 +#define SCU_RAM_FREE_8169__M 0xFFFF +#define SCU_RAM_FREE_8169__PRE 0x0 + +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x1E + +#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB +#define SCU_RAM_DRIVER_VER_HI__W 16 +#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF +#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC +#define SCU_RAM_DRIVER_VER_LO__W 16 +#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF +#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 + +#define SCU_RAM_PARAM_15__A 0x831FED +#define SCU_RAM_PARAM_15__W 16 +#define SCU_RAM_PARAM_15__M 0xFFFF +#define SCU_RAM_PARAM_15__PRE 0x0 + +#define SCU_RAM_PARAM_14__A 0x831FEE +#define SCU_RAM_PARAM_14__W 16 +#define SCU_RAM_PARAM_14__M 0xFFFF +#define SCU_RAM_PARAM_14__PRE 0x0 + +#define SCU_RAM_PARAM_13__A 0x831FEF +#define SCU_RAM_PARAM_13__W 16 +#define SCU_RAM_PARAM_13__M 0xFFFF +#define SCU_RAM_PARAM_13__PRE 0x0 + +#define SCU_RAM_PARAM_12__A 0x831FF0 +#define SCU_RAM_PARAM_12__W 16 +#define SCU_RAM_PARAM_12__M 0xFFFF +#define SCU_RAM_PARAM_12__PRE 0x0 + +#define SCU_RAM_PARAM_11__A 0x831FF1 +#define SCU_RAM_PARAM_11__W 16 +#define SCU_RAM_PARAM_11__M 0xFFFF +#define SCU_RAM_PARAM_11__PRE 0x0 + +#define SCU_RAM_PARAM_10__A 0x831FF2 +#define SCU_RAM_PARAM_10__W 16 +#define SCU_RAM_PARAM_10__M 0xFFFF +#define SCU_RAM_PARAM_10__PRE 0x0 + +#define SCU_RAM_PARAM_9__A 0x831FF3 +#define SCU_RAM_PARAM_9__W 16 +#define SCU_RAM_PARAM_9__M 0xFFFF +#define SCU_RAM_PARAM_9__PRE 0x0 + +#define SCU_RAM_PARAM_8__A 0x831FF4 +#define SCU_RAM_PARAM_8__W 16 +#define SCU_RAM_PARAM_8__M 0xFFFF +#define SCU_RAM_PARAM_8__PRE 0x0 + +#define SCU_RAM_PARAM_7__A 0x831FF5 +#define SCU_RAM_PARAM_7__W 16 +#define SCU_RAM_PARAM_7__M 0xFFFF +#define SCU_RAM_PARAM_7__PRE 0x0 + +#define SCU_RAM_PARAM_6__A 0x831FF6 +#define SCU_RAM_PARAM_6__W 16 +#define SCU_RAM_PARAM_6__M 0xFFFF +#define SCU_RAM_PARAM_6__PRE 0x0 + +#define SCU_RAM_PARAM_5__A 0x831FF7 +#define SCU_RAM_PARAM_5__W 16 +#define SCU_RAM_PARAM_5__M 0xFFFF +#define SCU_RAM_PARAM_5__PRE 0x0 + +#define SCU_RAM_PARAM_4__A 0x831FF8 +#define SCU_RAM_PARAM_4__W 16 +#define SCU_RAM_PARAM_4__M 0xFFFF +#define SCU_RAM_PARAM_4__PRE 0x0 + +#define SCU_RAM_PARAM_3__A 0x831FF9 +#define SCU_RAM_PARAM_3__W 16 +#define SCU_RAM_PARAM_3__M 0xFFFF +#define SCU_RAM_PARAM_3__PRE 0x0 + +#define SCU_RAM_PARAM_2__A 0x831FFA +#define SCU_RAM_PARAM_2__W 16 +#define SCU_RAM_PARAM_2__M 0xFFFF +#define SCU_RAM_PARAM_2__PRE 0x0 + +#define SCU_RAM_PARAM_1__A 0x831FFB +#define SCU_RAM_PARAM_1__W 16 +#define SCU_RAM_PARAM_1__M 0xFFFF +#define SCU_RAM_PARAM_1__PRE 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 + + +#define SCU_RAM_PARAM_0__A 0x831FFC +#define SCU_RAM_PARAM_0__W 16 +#define SCU_RAM_PARAM_0__M 0xFFFF +#define SCU_RAM_PARAM_0__PRE 0x0 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 +#define SCU_RAM_PARAM_0_RESULT_OK 0x0 +#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF +#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE +#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD +#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC + + +#define SCU_RAM_COMMAND__A 0x831FFD +#define SCU_RAM_COMMAND__W 16 +#define SCU_RAM_COMMAND__M 0xFFFF +#define SCU_RAM_COMMAND__PRE 0x0 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 +#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 +#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 +#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 +#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 +#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 +#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 +#define SCU_RAM_COMMAND_CMD_DEBUG_ATV_TIMINGS 0x85 +#define SCU_RAM_COMMAND_CMD_DEBUG_SET_IRQ_PRI 0x86 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_PSW 0x87 +#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD +#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 +#define SCU_RAM_COMMAND_CMD_AUX_ADC_COMP_RESTART 0xC1 + +#define SCU_RAM_COMMAND_STANDARD__B 8 +#define SCU_RAM_COMMAND_STANDARD__W 8 +#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 +#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 +#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 +#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 + +#define SCU_RAM_VERSION_HI__A 0x831FFE +#define SCU_RAM_VERSION_HI__W 16 +#define SCU_RAM_VERSION_HI__M 0xFFFF +#define SCU_RAM_VERSION_HI__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_LO__A 0x831FFF +#define SCU_RAM_VERSION_LO__W 16 +#define SCU_RAM_VERSION_LO__M 0xFFFF +#define SCU_RAM_VERSION_LO__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 + + + + + +#define SIO_COMM_EXEC__A 0x400000 +#define SIO_COMM_EXEC__W 2 +#define SIO_COMM_EXEC__M 0x3 +#define SIO_COMM_EXEC__PRE 0x0 +#define SIO_COMM_EXEC_STOP 0x0 +#define SIO_COMM_EXEC_ACTIVE 0x1 +#define SIO_COMM_EXEC_HOLD 0x2 + +#define SIO_COMM_STATE__A 0x400001 +#define SIO_COMM_STATE__W 16 +#define SIO_COMM_STATE__M 0xFFFF +#define SIO_COMM_STATE__PRE 0x0 +#define SIO_COMM_MB__A 0x400002 +#define SIO_COMM_MB__W 16 +#define SIO_COMM_MB__M 0xFFFF +#define SIO_COMM_MB__PRE 0x0 +#define SIO_COMM_INT_REQ__A 0x400003 +#define SIO_COMM_INT_REQ__W 16 +#define SIO_COMM_INT_REQ__M 0xFFFF +#define SIO_COMM_INT_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_HI_REQ__B 0 +#define SIO_COMM_INT_REQ_HI_REQ__W 1 +#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 +#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_SA_REQ__B 1 +#define SIO_COMM_INT_REQ_SA_REQ__W 1 +#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 +#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_BL_REQ__B 2 +#define SIO_COMM_INT_REQ_BL_REQ__W 1 +#define SIO_COMM_INT_REQ_BL_REQ__M 0x4 +#define SIO_COMM_INT_REQ_BL_REQ__PRE 0x0 + +#define SIO_COMM_INT_STA__A 0x400005 +#define SIO_COMM_INT_STA__W 16 +#define SIO_COMM_INT_STA__M 0xFFFF +#define SIO_COMM_INT_STA__PRE 0x0 +#define SIO_COMM_INT_MSK__A 0x400006 +#define SIO_COMM_INT_MSK__W 16 +#define SIO_COMM_INT_MSK__M 0xFFFF +#define SIO_COMM_INT_MSK__PRE 0x0 +#define SIO_COMM_INT_STM__A 0x400007 +#define SIO_COMM_INT_STM__W 16 +#define SIO_COMM_INT_STM__M 0xFFFF +#define SIO_COMM_INT_STM__PRE 0x0 + + + +#define SIO_TOP_COMM_EXEC__A 0x410000 +#define SIO_TOP_COMM_EXEC__W 2 +#define SIO_TOP_COMM_EXEC__M 0x3 +#define SIO_TOP_COMM_EXEC__PRE 0x0 +#define SIO_TOP_COMM_EXEC_STOP 0x0 +#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 +#define SIO_TOP_COMM_EXEC_HOLD 0x2 + + +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__W 16 +#define SIO_TOP_COMM_KEY__M 0xFFFF +#define SIO_TOP_COMM_KEY__PRE 0x0 +#define SIO_TOP_COMM_KEY_KEY 0xFABA + + +#define SIO_TOP_JTAGID_LO__A 0x410012 +#define SIO_TOP_JTAGID_LO__W 16 +#define SIO_TOP_JTAGID_LO__M 0xFFFF +#define SIO_TOP_JTAGID_LO__PRE 0x0 + +#define SIO_TOP_JTAGID_HI__A 0x410013 +#define SIO_TOP_JTAGID_HI__W 16 +#define SIO_TOP_JTAGID_HI__M 0xFFFF +#define SIO_TOP_JTAGID_HI__PRE 0x0 + + + + +#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 +#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 +#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 +#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 +#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 +#define SIO_HI_RA_RAM_S0_STATE__W 1 +#define SIO_HI_RA_RAM_S0_STATE__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 +#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 +#define SIO_HI_RA_RAM_S0_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 + + +#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 +#define SIO_HI_RA_RAM_S0_CRC__W 16 +#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 +#define SIO_HI_RA_RAM_S0_BUFFER__W 16 +#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 +#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A +#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B +#define SIO_HI_RA_RAM_S0_TEMP0__W 16 +#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C +#define SIO_HI_RA_RAM_S0_TEMP1__W 16 +#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D +#define SIO_HI_RA_RAM_S0_OFFSET__W 16 +#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 +#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 +#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 +#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 +#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 +#define SIO_HI_RA_RAM_S1_STATE__W 1 +#define SIO_HI_RA_RAM_S1_STATE__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 +#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 +#define SIO_HI_RA_RAM_S1_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 + + +#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 +#define SIO_HI_RA_RAM_S1_CRC__W 16 +#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 +#define SIO_HI_RA_RAM_S1_BUFFER__W 16 +#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 +#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A +#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B +#define SIO_HI_RA_RAM_S1_TEMP0__W 16 +#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C +#define SIO_HI_RA_RAM_S1_TEMP1__W 16 +#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D +#define SIO_HI_RA_RAM_S1_OFFSET__W 16 +#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA__A 0x420030 +#define SIO_HI_RA_RAM_SEMA__W 1 +#define SIO_HI_RA_RAM_SEMA__M 0x1 +#define SIO_HI_RA_RAM_SEMA__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA_FREE 0x0 +#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 + +#define SIO_HI_RA_RAM_RES__A 0x420031 +#define SIO_HI_RA_RAM_RES__W 3 +#define SIO_HI_RA_RAM_RES__M 0x7 +#define SIO_HI_RA_RAM_RES__PRE 0x0 +#define SIO_HI_RA_RAM_RES_OK 0x0 +#define SIO_HI_RA_RAM_RES_ERROR 0x1 +#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 +#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 +#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 +#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 + +#define SIO_HI_RA_RAM_CMD__A 0x420032 +#define SIO_HI_RA_RAM_CMD__W 4 +#define SIO_HI_RA_RAM_CMD__M 0xF +#define SIO_HI_RA_RAM_CMD__PRE 0x0 +#define SIO_HI_RA_RAM_CMD_NULL 0x0 +#define SIO_HI_RA_RAM_CMD_UIO 0x1 +#define SIO_HI_RA_RAM_CMD_RESET 0x2 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 +#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 +#define SIO_HI_RA_RAM_CMD_EXEC 0x6 +#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 +#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 + +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 + +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 + +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 + +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 + +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 + +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 + +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 + +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF + +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 + + +#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E +#define SIO_HI_RA_RAM_AB_TEMP__W 16 +#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF +#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 + +#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F +#define SIO_HI_RA_RAM_I2C_CTL__W 16 +#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF +#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 +#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 +#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 +#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 +#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 +#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 +#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 +#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 +#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 +#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 +#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A +#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B +#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C +#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D +#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E +#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F +#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 + + + +#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 +#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 +#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 +#define SIO_HI_IF_RAM_TRP_STK_0__W 12 +#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 +#define SIO_HI_IF_RAM_TRP_STK_1__W 12 +#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 +#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 +#define SIO_HI_IF_RAM_FUN_BASE__W 12 +#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF +#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 + + + +#define SIO_HI_IF_COMM_EXEC__A 0x440000 +#define SIO_HI_IF_COMM_EXEC__W 2 +#define SIO_HI_IF_COMM_EXEC__M 0x3 +#define SIO_HI_IF_COMM_EXEC__PRE 0x0 +#define SIO_HI_IF_COMM_EXEC_STOP 0x0 +#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 +#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 +#define SIO_HI_IF_COMM_EXEC_STEP 0x3 + + +#define SIO_HI_IF_COMM_STATE__A 0x440001 +#define SIO_HI_IF_COMM_STATE__W 10 +#define SIO_HI_IF_COMM_STATE__M 0x3FF +#define SIO_HI_IF_COMM_STATE__PRE 0x0 +#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 +#define SIO_HI_IF_COMM_INT_REQ__W 1 +#define SIO_HI_IF_COMM_INT_REQ__M 0x1 +#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA__A 0x440005 +#define SIO_HI_IF_COMM_INT_STA__W 1 +#define SIO_HI_IF_COMM_INT_STA__M 0x1 +#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 +#define SIO_HI_IF_COMM_INT_MSK__W 1 +#define SIO_HI_IF_COMM_INT_MSK__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_STM__A 0x440007 +#define SIO_HI_IF_COMM_INT_STM__W 1 +#define SIO_HI_IF_COMM_INT_STM__M 0x1 +#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 + +#define SIO_HI_IF_STK_0__A 0x440010 +#define SIO_HI_IF_STK_0__W 10 +#define SIO_HI_IF_STK_0__M 0x3FF +#define SIO_HI_IF_STK_0__PRE 0x2 + +#define SIO_HI_IF_STK_0_ADDR__B 0 +#define SIO_HI_IF_STK_0_ADDR__W 10 +#define SIO_HI_IF_STK_0_ADDR__M 0x3FF +#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_1__A 0x440011 +#define SIO_HI_IF_STK_1__W 10 +#define SIO_HI_IF_STK_1__M 0x3FF +#define SIO_HI_IF_STK_1__PRE 0x2 +#define SIO_HI_IF_STK_1_ADDR__B 0 +#define SIO_HI_IF_STK_1_ADDR__W 10 +#define SIO_HI_IF_STK_1_ADDR__M 0x3FF +#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_2__A 0x440012 +#define SIO_HI_IF_STK_2__W 10 +#define SIO_HI_IF_STK_2__M 0x3FF +#define SIO_HI_IF_STK_2__PRE 0x2 +#define SIO_HI_IF_STK_2_ADDR__B 0 +#define SIO_HI_IF_STK_2_ADDR__W 10 +#define SIO_HI_IF_STK_2_ADDR__M 0x3FF +#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_3__A 0x440013 +#define SIO_HI_IF_STK_3__W 10 +#define SIO_HI_IF_STK_3__M 0x3FF +#define SIO_HI_IF_STK_3__PRE 0x2 + +#define SIO_HI_IF_STK_3_ADDR__B 0 +#define SIO_HI_IF_STK_3_ADDR__W 10 +#define SIO_HI_IF_STK_3_ADDR__M 0x3FF +#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 + +#define SIO_HI_IF_BPT_IDX__A 0x44001F +#define SIO_HI_IF_BPT_IDX__W 1 +#define SIO_HI_IF_BPT_IDX__M 0x1 +#define SIO_HI_IF_BPT_IDX__PRE 0x0 + +#define SIO_HI_IF_BPT_IDX_ADDR__B 0 +#define SIO_HI_IF_BPT_IDX_ADDR__W 1 +#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 +#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 + +#define SIO_HI_IF_BPT__A 0x440020 +#define SIO_HI_IF_BPT__W 10 +#define SIO_HI_IF_BPT__M 0x3FF +#define SIO_HI_IF_BPT__PRE 0x2 + +#define SIO_HI_IF_BPT_ADDR__B 0 +#define SIO_HI_IF_BPT_ADDR__W 10 +#define SIO_HI_IF_BPT_ADDR__M 0x3FF +#define SIO_HI_IF_BPT_ADDR__PRE 0x2 + + + +#define SIO_CC_COMM_EXEC__A 0x450000 +#define SIO_CC_COMM_EXEC__W 2 +#define SIO_CC_COMM_EXEC__M 0x3 +#define SIO_CC_COMM_EXEC__PRE 0x0 +#define SIO_CC_COMM_EXEC_STOP 0x0 +#define SIO_CC_COMM_EXEC_ACTIVE 0x1 +#define SIO_CC_COMM_EXEC_HOLD 0x2 + +#define SIO_CC_PLL_MODE__A 0x450010 +#define SIO_CC_PLL_MODE__W 6 +#define SIO_CC_PLL_MODE__M 0x3F +#define SIO_CC_PLL_MODE__PRE 0x0 + +#define SIO_CC_PLL_MODE_FREF_SEL__B 0 +#define SIO_CC_PLL_MODE_FREF_SEL__W 2 +#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 +#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 +#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 +#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 + +#define SIO_CC_PLL_MODE_LOCKSEL__B 2 +#define SIO_CC_PLL_MODE_LOCKSEL__W 2 +#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC +#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 + +#define SIO_CC_PLL_MODE_BYPASS__B 4 +#define SIO_CC_PLL_MODE_BYPASS__W 2 +#define SIO_CC_PLL_MODE_BYPASS__M 0x30 +#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 +#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 + + +#define SIO_CC_PLL_TEST__A 0x450011 +#define SIO_CC_PLL_TEST__W 8 +#define SIO_CC_PLL_TEST__M 0xFF +#define SIO_CC_PLL_TEST__PRE 0x0 + +#define SIO_CC_PLL_LOCK__A 0x450012 +#define SIO_CC_PLL_LOCK__W 1 +#define SIO_CC_PLL_LOCK__M 0x1 +#define SIO_CC_PLL_LOCK__PRE 0x0 +#define SIO_CC_CLK_TEST__A 0x450013 +#define SIO_CC_CLK_TEST__W 8 +#define SIO_CC_CLK_TEST__M 0xFF +#define SIO_CC_CLK_TEST__PRE 0x0 + +#define SIO_CC_CLK_TEST_SEL1__B 0 +#define SIO_CC_CLK_TEST_SEL1__W 3 +#define SIO_CC_CLK_TEST_SEL1__M 0x7 +#define SIO_CC_CLK_TEST_SEL1__PRE 0x0 + +#define SIO_CC_CLK_TEST_ENAB1__B 3 +#define SIO_CC_CLK_TEST_ENAB1__W 1 +#define SIO_CC_CLK_TEST_ENAB1__M 0x8 +#define SIO_CC_CLK_TEST_ENAB1__PRE 0x0 + +#define SIO_CC_CLK_TEST_SEL2__B 4 +#define SIO_CC_CLK_TEST_SEL2__W 3 +#define SIO_CC_CLK_TEST_SEL2__M 0x70 +#define SIO_CC_CLK_TEST_SEL2__PRE 0x0 + +#define SIO_CC_CLK_TEST_ENAB2__B 7 +#define SIO_CC_CLK_TEST_ENAB2__W 1 +#define SIO_CC_CLK_TEST_ENAB2__M 0x80 +#define SIO_CC_CLK_TEST_ENAB2__PRE 0x0 + +#define SIO_CC_CLK_MODE__A 0x450014 +#define SIO_CC_CLK_MODE__W 7 +#define SIO_CC_CLK_MODE__M 0x7F +#define SIO_CC_CLK_MODE__PRE 0x0 + +#define SIO_CC_CLK_MODE_DELAY__B 0 +#define SIO_CC_CLK_MODE_DELAY__W 4 +#define SIO_CC_CLK_MODE_DELAY__M 0xF +#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 + +#define SIO_CC_CLK_MODE_INVERT__B 4 +#define SIO_CC_CLK_MODE_INVERT__W 1 +#define SIO_CC_CLK_MODE_INVERT__M 0x10 +#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 + +#define SIO_CC_CLK_MODE_OFDM_ALIGN__B 5 +#define SIO_CC_CLK_MODE_OFDM_ALIGN__W 1 +#define SIO_CC_CLK_MODE_OFDM_ALIGN__M 0x20 +#define SIO_CC_CLK_MODE_OFDM_ALIGN__PRE 0x0 + +#define SIO_CC_CLK_MODE_OFDM_DUTYC__B 6 +#define SIO_CC_CLK_MODE_OFDM_DUTYC__W 1 +#define SIO_CC_CLK_MODE_OFDM_DUTYC__M 0x40 +#define SIO_CC_CLK_MODE_OFDM_DUTYC__PRE 0x0 + +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__W 4 +#define SIO_CC_PWD_MODE__M 0xF +#define SIO_CC_PWD_MODE__PRE 0x0 + +#define SIO_CC_PWD_MODE_LEVEL__B 0 +#define SIO_CC_PWD_MODE_LEVEL__W 3 +#define SIO_CC_PWD_MODE_LEVEL__M 0x7 +#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 +#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 +#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 + +#define SIO_CC_PWD_MODE_USE_LOCK__B 3 +#define SIO_CC_PWD_MODE_USE_LOCK__W 1 +#define SIO_CC_PWD_MODE_USE_LOCK__M 0x8 +#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 + +#define SIO_CC_SOFT_RST__A 0x450016 +#define SIO_CC_SOFT_RST__W 3 +#define SIO_CC_SOFT_RST__M 0x7 +#define SIO_CC_SOFT_RST__PRE 0x0 + +#define SIO_CC_SOFT_RST_OFDM__B 0 +#define SIO_CC_SOFT_RST_OFDM__W 1 +#define SIO_CC_SOFT_RST_OFDM__M 0x1 +#define SIO_CC_SOFT_RST_OFDM__PRE 0x0 + +#define SIO_CC_SOFT_RST_SYS__B 1 +#define SIO_CC_SOFT_RST_SYS__W 1 +#define SIO_CC_SOFT_RST_SYS__M 0x2 +#define SIO_CC_SOFT_RST_SYS__PRE 0x0 + +#define SIO_CC_SOFT_RST_OSC__B 2 +#define SIO_CC_SOFT_RST_OSC__W 1 +#define SIO_CC_SOFT_RST_OSC__M 0x4 +#define SIO_CC_SOFT_RST_OSC__PRE 0x0 + + +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__W 16 +#define SIO_CC_UPDATE__M 0xFFFF +#define SIO_CC_UPDATE__PRE 0x0 +#define SIO_CC_UPDATE_KEY 0xFABA + + + +#define SIO_SA_COMM_EXEC__A 0x460000 +#define SIO_SA_COMM_EXEC__W 2 +#define SIO_SA_COMM_EXEC__M 0x3 +#define SIO_SA_COMM_EXEC__PRE 0x0 +#define SIO_SA_COMM_EXEC_STOP 0x0 +#define SIO_SA_COMM_EXEC_ACTIVE 0x1 +#define SIO_SA_COMM_EXEC_HOLD 0x2 + +#define SIO_SA_COMM_INT_REQ__A 0x460003 +#define SIO_SA_COMM_INT_REQ__W 1 +#define SIO_SA_COMM_INT_REQ__M 0x1 +#define SIO_SA_COMM_INT_REQ__PRE 0x0 +#define SIO_SA_COMM_INT_STA__A 0x460005 +#define SIO_SA_COMM_INT_STA__W 4 +#define SIO_SA_COMM_INT_STA__M 0xF +#define SIO_SA_COMM_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK__A 0x460006 +#define SIO_SA_COMM_INT_MSK__W 4 +#define SIO_SA_COMM_INT_MSK__M 0xF +#define SIO_SA_COMM_INT_MSK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM__A 0x460007 +#define SIO_SA_COMM_INT_STM__W 4 +#define SIO_SA_COMM_INT_STM__M 0xF +#define SIO_SA_COMM_INT_STM__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_PRESCALER__A 0x460010 +#define SIO_SA_PRESCALER__W 13 +#define SIO_SA_PRESCALER__M 0x1FFF +#define SIO_SA_PRESCALER__PRE 0x18B7 +#define SIO_SA_TX_DATA0__A 0x460011 +#define SIO_SA_TX_DATA0__W 16 +#define SIO_SA_TX_DATA0__M 0xFFFF +#define SIO_SA_TX_DATA0__PRE 0x0 +#define SIO_SA_TX_DATA1__A 0x460012 +#define SIO_SA_TX_DATA1__W 16 +#define SIO_SA_TX_DATA1__M 0xFFFF +#define SIO_SA_TX_DATA1__PRE 0x0 +#define SIO_SA_TX_DATA2__A 0x460013 +#define SIO_SA_TX_DATA2__W 16 +#define SIO_SA_TX_DATA2__M 0xFFFF +#define SIO_SA_TX_DATA2__PRE 0x0 +#define SIO_SA_TX_DATA3__A 0x460014 +#define SIO_SA_TX_DATA3__W 16 +#define SIO_SA_TX_DATA3__M 0xFFFF +#define SIO_SA_TX_DATA3__PRE 0x0 +#define SIO_SA_TX_LENGTH__A 0x460015 +#define SIO_SA_TX_LENGTH__W 6 +#define SIO_SA_TX_LENGTH__M 0x3F +#define SIO_SA_TX_LENGTH__PRE 0x0 +#define SIO_SA_TX_COMMAND__A 0x460016 +#define SIO_SA_TX_COMMAND__W 2 +#define SIO_SA_TX_COMMAND__M 0x3 +#define SIO_SA_TX_COMMAND__PRE 0x3 + +#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 +#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 +#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 +#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 + +#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 +#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 + +#define SIO_SA_TX_STATUS__A 0x460017 +#define SIO_SA_TX_STATUS__W 2 +#define SIO_SA_TX_STATUS__M 0x3 +#define SIO_SA_TX_STATUS__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUSY__B 0 +#define SIO_SA_TX_STATUS_BUSY__W 1 +#define SIO_SA_TX_STATUS_BUSY__M 0x1 +#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 + +#define SIO_SA_RX_DATA0__A 0x460018 +#define SIO_SA_RX_DATA0__W 16 +#define SIO_SA_RX_DATA0__M 0xFFFF +#define SIO_SA_RX_DATA0__PRE 0x0 +#define SIO_SA_RX_DATA1__A 0x460019 +#define SIO_SA_RX_DATA1__W 16 +#define SIO_SA_RX_DATA1__M 0xFFFF +#define SIO_SA_RX_DATA1__PRE 0x0 +#define SIO_SA_RX_LENGTH__A 0x46001A +#define SIO_SA_RX_LENGTH__W 6 +#define SIO_SA_RX_LENGTH__M 0x3F +#define SIO_SA_RX_LENGTH__PRE 0x0 +#define SIO_SA_RX_COMMAND__A 0x46001B +#define SIO_SA_RX_COMMAND__W 1 +#define SIO_SA_RX_COMMAND__M 0x1 +#define SIO_SA_RX_COMMAND__PRE 0x1 + +#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 +#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 +#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 +#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 + +#define SIO_SA_RX_STATUS__A 0x46001C +#define SIO_SA_RX_STATUS__W 2 +#define SIO_SA_RX_STATUS__M 0x3 +#define SIO_SA_RX_STATUS__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUSY__B 0 +#define SIO_SA_RX_STATUS_BUSY__W 1 +#define SIO_SA_RX_STATUS_BUSY__M 0x1 +#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 + + + +#define SIO_OFDM_SH_COMM_EXEC__A 0x470000 +#define SIO_OFDM_SH_COMM_EXEC__W 2 +#define SIO_OFDM_SH_COMM_EXEC__M 0x3 +#define SIO_OFDM_SH_COMM_EXEC__PRE 0x0 +#define SIO_OFDM_SH_COMM_EXEC_STOP 0x0 +#define SIO_OFDM_SH_COMM_EXEC_ACTIVE 0x1 +#define SIO_OFDM_SH_COMM_EXEC_HOLD 0x2 + +#define SIO_OFDM_SH_COMM_MB__A 0x470002 +#define SIO_OFDM_SH_COMM_MB__W 2 +#define SIO_OFDM_SH_COMM_MB__M 0x3 +#define SIO_OFDM_SH_COMM_MB__PRE 0x0 +#define SIO_OFDM_SH_COMM_MB_CTL__B 0 +#define SIO_OFDM_SH_COMM_MB_CTL__W 1 +#define SIO_OFDM_SH_COMM_MB_CTL__M 0x1 +#define SIO_OFDM_SH_COMM_MB_CTL__PRE 0x0 +#define SIO_OFDM_SH_COMM_MB_CTL_OFF 0x0 +#define SIO_OFDM_SH_COMM_MB_CTL_ON 0x1 +#define SIO_OFDM_SH_COMM_MB_OBS__B 1 +#define SIO_OFDM_SH_COMM_MB_OBS__W 1 +#define SIO_OFDM_SH_COMM_MB_OBS__M 0x2 +#define SIO_OFDM_SH_COMM_MB_OBS__PRE 0x0 +#define SIO_OFDM_SH_COMM_MB_OBS_OFF 0x0 +#define SIO_OFDM_SH_COMM_MB_OBS_ON 0x2 + +#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__W 1 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__M 0x1 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__PRE 0x0 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 + +#define SIO_OFDM_SH_OFDM_MB_CONTROL__A 0x470011 +#define SIO_OFDM_SH_OFDM_MB_CONTROL__W 2 +#define SIO_OFDM_SH_OFDM_MB_CONTROL__M 0x3 +#define SIO_OFDM_SH_OFDM_MB_CONTROL__PRE 0x0 + +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__B 0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__W 1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__M 0x1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__PRE 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OPEN 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OFDM 0x1 + +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__B 1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__W 1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__M 0x2 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__PRE 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_BYPASS 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_OFDM 0x2 + +#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 +#define SIO_OFDM_SH_OFDM_RING_STATUS__W 1 +#define SIO_OFDM_SH_OFDM_RING_STATUS__M 0x1 +#define SIO_OFDM_SH_OFDM_RING_STATUS__PRE 0x0 +#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 +#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 + +#define SIO_OFDM_SH_OFDM_MB_FLEN__A 0x470013 +#define SIO_OFDM_SH_OFDM_MB_FLEN__W 3 +#define SIO_OFDM_SH_OFDM_MB_FLEN__M 0x7 +#define SIO_OFDM_SH_OFDM_MB_FLEN__PRE 0x6 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__B 0 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__W 3 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__M 0x7 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__PRE 0x6 + + + +#define SIO_BL_COMM_EXEC__A 0x480000 +#define SIO_BL_COMM_EXEC__W 2 +#define SIO_BL_COMM_EXEC__M 0x3 +#define SIO_BL_COMM_EXEC__PRE 0x0 +#define SIO_BL_COMM_EXEC_STOP 0x0 +#define SIO_BL_COMM_EXEC_ACTIVE 0x1 +#define SIO_BL_COMM_EXEC_HOLD 0x2 + +#define SIO_BL_COMM_INT_REQ__A 0x480003 +#define SIO_BL_COMM_INT_REQ__W 1 +#define SIO_BL_COMM_INT_REQ__M 0x1 +#define SIO_BL_COMM_INT_REQ__PRE 0x0 +#define SIO_BL_COMM_INT_STA__A 0x480005 +#define SIO_BL_COMM_INT_STA__W 1 +#define SIO_BL_COMM_INT_STA__M 0x1 +#define SIO_BL_COMM_INT_STA__PRE 0x0 + +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__B 0 +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__W 1 +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__M 0x1 +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__PRE 0x0 + +#define SIO_BL_COMM_INT_MSK__A 0x480006 +#define SIO_BL_COMM_INT_MSK__W 1 +#define SIO_BL_COMM_INT_MSK__M 0x1 +#define SIO_BL_COMM_INT_MSK__PRE 0x0 + +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__B 0 +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__W 1 +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__M 0x1 +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__PRE 0x0 + +#define SIO_BL_COMM_INT_STM__A 0x480007 +#define SIO_BL_COMM_INT_STM__W 1 +#define SIO_BL_COMM_INT_STM__M 0x1 +#define SIO_BL_COMM_INT_STM__PRE 0x0 + +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__B 0 +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__W 1 +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__M 0x1 +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__PRE 0x0 + +#define SIO_BL_STATUS__A 0x480010 +#define SIO_BL_STATUS__W 1 +#define SIO_BL_STATUS__M 0x1 +#define SIO_BL_STATUS__PRE 0x0 +#define SIO_BL_MODE__A 0x480011 +#define SIO_BL_MODE__W 1 +#define SIO_BL_MODE__M 0x1 +#define SIO_BL_MODE__PRE 0x1 +#define SIO_BL_MODE_DIRECT 0x0 +#define SIO_BL_MODE_CHAIN 0x1 + +#define SIO_BL_ENABLE__A 0x480012 +#define SIO_BL_ENABLE__W 1 +#define SIO_BL_ENABLE__M 0x1 +#define SIO_BL_ENABLE__PRE 0x0 +#define SIO_BL_ENABLE_OFF 0x0 +#define SIO_BL_ENABLE_ON 0x1 + +#define SIO_BL_TGT_HDR__A 0x480014 +#define SIO_BL_TGT_HDR__W 12 +#define SIO_BL_TGT_HDR__M 0xFFF +#define SIO_BL_TGT_HDR__PRE 0x0 +#define SIO_BL_TGT_HDR_BANK__B 0 +#define SIO_BL_TGT_HDR_BANK__W 6 +#define SIO_BL_TGT_HDR_BANK__M 0x3F +#define SIO_BL_TGT_HDR_BANK__PRE 0x0 +#define SIO_BL_TGT_HDR_BLOCK__B 6 +#define SIO_BL_TGT_HDR_BLOCK__W 6 +#define SIO_BL_TGT_HDR_BLOCK__M 0xFC0 +#define SIO_BL_TGT_HDR_BLOCK__PRE 0x0 + +#define SIO_BL_TGT_ADDR__A 0x480015 +#define SIO_BL_TGT_ADDR__W 16 +#define SIO_BL_TGT_ADDR__M 0xFFFF +#define SIO_BL_TGT_ADDR__PRE 0x0 +#define SIO_BL_SRC_ADDR__A 0x480016 +#define SIO_BL_SRC_ADDR__W 16 +#define SIO_BL_SRC_ADDR__M 0xFFFF +#define SIO_BL_SRC_ADDR__PRE 0x0 +#define SIO_BL_SRC_LEN__A 0x480017 +#define SIO_BL_SRC_LEN__W 16 +#define SIO_BL_SRC_LEN__M 0xFFFF +#define SIO_BL_SRC_LEN__PRE 0x0 + +#define SIO_BL_CHAIN_ADDR__A 0x480018 +#define SIO_BL_CHAIN_ADDR__W 16 +#define SIO_BL_CHAIN_ADDR__M 0xFFFF +#define SIO_BL_CHAIN_ADDR__PRE 0x0 + +#define SIO_BL_CHAIN_LEN__A 0x480019 +#define SIO_BL_CHAIN_LEN__W 4 +#define SIO_BL_CHAIN_LEN__M 0xF +#define SIO_BL_CHAIN_LEN__PRE 0x2 + + + +#define SIO_OFDM_SH_TRB_R0_RAM__A 0x4C0000 + + + +#define SIO_OFDM_SH_TRB_R1_RAM__A 0x4D0000 + + + +#define SIO_BL_ROM__A 0x4E0000 + + + +#define SIO_PDR_COMM_EXEC__A 0x7F0000 +#define SIO_PDR_COMM_EXEC__W 2 +#define SIO_PDR_COMM_EXEC__M 0x3 +#define SIO_PDR_COMM_EXEC__PRE 0x0 +#define SIO_PDR_COMM_EXEC_STOP 0x0 +#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 +#define SIO_PDR_COMM_EXEC_HOLD 0x2 + +#define SIO_PDR_MON_CFG__A 0x7F0010 +#define SIO_PDR_MON_CFG__W 4 +#define SIO_PDR_MON_CFG__M 0xF +#define SIO_PDR_MON_CFG__PRE 0x0 + +#define SIO_PDR_MON_CFG_OSEL__B 0 +#define SIO_PDR_MON_CFG_OSEL__W 1 +#define SIO_PDR_MON_CFG_OSEL__M 0x1 +#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 + +#define SIO_PDR_MON_CFG_IACT__B 1 +#define SIO_PDR_MON_CFG_IACT__W 1 +#define SIO_PDR_MON_CFG_IACT__M 0x2 +#define SIO_PDR_MON_CFG_IACT__PRE 0x0 + +#define SIO_PDR_MON_CFG_ISEL__B 2 +#define SIO_PDR_MON_CFG_ISEL__W 1 +#define SIO_PDR_MON_CFG_ISEL__M 0x4 +#define SIO_PDR_MON_CFG_ISEL__PRE 0x0 + +#define SIO_PDR_MON_CFG_INV_CLK__B 3 +#define SIO_PDR_MON_CFG_INV_CLK__W 1 +#define SIO_PDR_MON_CFG_INV_CLK__M 0x8 +#define SIO_PDR_MON_CFG_INV_CLK__PRE 0x0 + +#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 +#define SIO_PDR_SMA_RX_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_SEL_SEL__B 0 +#define SIO_PDR_SMA_RX_SEL_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 + +#define SIO_PDR_SILENT__A 0x7F0013 +#define SIO_PDR_SILENT__W 13 +#define SIO_PDR_SILENT__M 0x1FFF +#define SIO_PDR_SILENT__PRE 0x0 + +#define SIO_PDR_SILENT_I2S_WS__B 0 +#define SIO_PDR_SILENT_I2S_WS__W 1 +#define SIO_PDR_SILENT_I2S_WS__M 0x1 +#define SIO_PDR_SILENT_I2S_WS__PRE 0x0 + +#define SIO_PDR_SILENT_I2S_DA__B 1 +#define SIO_PDR_SILENT_I2S_DA__W 1 +#define SIO_PDR_SILENT_I2S_DA__M 0x2 +#define SIO_PDR_SILENT_I2S_DA__PRE 0x0 + +#define SIO_PDR_SILENT_I2S_CL__B 2 +#define SIO_PDR_SILENT_I2S_CL__W 1 +#define SIO_PDR_SILENT_I2S_CL__M 0x4 +#define SIO_PDR_SILENT_I2S_CL__PRE 0x0 + +#define SIO_PDR_SILENT_I2C_SCL2__B 3 +#define SIO_PDR_SILENT_I2C_SCL2__W 1 +#define SIO_PDR_SILENT_I2C_SCL2__M 0x8 +#define SIO_PDR_SILENT_I2C_SCL2__PRE 0x0 + +#define SIO_PDR_SILENT_I2C_SDA2__B 4 +#define SIO_PDR_SILENT_I2C_SDA2__W 1 +#define SIO_PDR_SILENT_I2C_SDA2__M 0x10 +#define SIO_PDR_SILENT_I2C_SDA2__PRE 0x0 + +#define SIO_PDR_SILENT_SMA_TX__B 8 +#define SIO_PDR_SILENT_SMA_TX__W 1 +#define SIO_PDR_SILENT_SMA_TX__M 0x100 +#define SIO_PDR_SILENT_SMA_TX__PRE 0x0 + +#define SIO_PDR_SILENT_SMA_RX__B 9 +#define SIO_PDR_SILENT_SMA_RX__W 1 +#define SIO_PDR_SILENT_SMA_RX__M 0x200 +#define SIO_PDR_SILENT_SMA_RX__PRE 0x0 + +#define SIO_PDR_SILENT_GPIO__B 10 +#define SIO_PDR_SILENT_GPIO__W 1 +#define SIO_PDR_SILENT_GPIO__M 0x400 +#define SIO_PDR_SILENT_GPIO__PRE 0x0 + +#define SIO_PDR_SILENT_VSYNC__B 11 +#define SIO_PDR_SILENT_VSYNC__W 1 +#define SIO_PDR_SILENT_VSYNC__M 0x800 +#define SIO_PDR_SILENT_VSYNC__PRE 0x0 + +#define SIO_PDR_SILENT_IRQN__B 12 +#define SIO_PDR_SILENT_IRQN__W 1 +#define SIO_PDR_SILENT_IRQN__M 0x1000 +#define SIO_PDR_SILENT_IRQN__PRE 0x0 + +#define SIO_PDR_UIO_IN_LO__A 0x7F0014 +#define SIO_PDR_UIO_IN_LO__W 16 +#define SIO_PDR_UIO_IN_LO__M 0xFFFF +#define SIO_PDR_UIO_IN_LO__PRE 0x0 +#define SIO_PDR_UIO_IN_LO_DATA__B 0 +#define SIO_PDR_UIO_IN_LO_DATA__W 16 +#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_IN_HI__A 0x7F0015 +#define SIO_PDR_UIO_IN_HI__W 14 +#define SIO_PDR_UIO_IN_HI__M 0x3FFF +#define SIO_PDR_UIO_IN_HI__PRE 0x0 +#define SIO_PDR_UIO_IN_HI_DATA__B 0 +#define SIO_PDR_UIO_IN_HI_DATA__W 14 +#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 +#define SIO_PDR_UIO_OUT_LO__W 16 +#define SIO_PDR_UIO_OUT_LO__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO__PRE 0x0 +#define SIO_PDR_UIO_OUT_LO_DATA__B 0 +#define SIO_PDR_UIO_OUT_LO_DATA__W 16 +#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 +#define SIO_PDR_UIO_OUT_HI__W 14 +#define SIO_PDR_UIO_OUT_HI__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI__PRE 0x0 +#define SIO_PDR_UIO_OUT_HI_DATA__B 0 +#define SIO_PDR_UIO_OUT_HI_DATA__W 14 +#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 + +#define SIO_PDR_PWM1_MODE__A 0x7F0018 +#define SIO_PDR_PWM1_MODE__W 2 +#define SIO_PDR_PWM1_MODE__M 0x3 +#define SIO_PDR_PWM1_MODE__PRE 0x0 +#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 +#define SIO_PDR_PWM1_PRESCALE__W 6 +#define SIO_PDR_PWM1_PRESCALE__M 0x3F +#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM1_VALUE__A 0x7F001A +#define SIO_PDR_PWM1_VALUE__W 11 +#define SIO_PDR_PWM1_VALUE__M 0x7FF +#define SIO_PDR_PWM1_VALUE__PRE 0x0 + +#define SIO_PDR_IRQN_SEL__A 0x7F001B +#define SIO_PDR_IRQN_SEL__W 4 +#define SIO_PDR_IRQN_SEL__M 0xF +#define SIO_PDR_IRQN_SEL__PRE 0x3 +#define SIO_PDR_PWM2_MODE__A 0x7F001C +#define SIO_PDR_PWM2_MODE__W 2 +#define SIO_PDR_PWM2_MODE__M 0x3 +#define SIO_PDR_PWM2_MODE__PRE 0x0 +#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D +#define SIO_PDR_PWM2_PRESCALE__W 6 +#define SIO_PDR_PWM2_PRESCALE__M 0x3F +#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM2_VALUE__A 0x7F001E +#define SIO_PDR_PWM2_VALUE__W 11 +#define SIO_PDR_PWM2_VALUE__M 0x7FF +#define SIO_PDR_PWM2_VALUE__PRE 0x0 +#define SIO_PDR_OHW_CFG__A 0x7F001F +#define SIO_PDR_OHW_CFG__W 7 +#define SIO_PDR_OHW_CFG__M 0x7F +#define SIO_PDR_OHW_CFG__PRE 0x0 + +#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 +#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 +#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 +#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_BYPASS__B 2 +#define SIO_PDR_OHW_CFG_BYPASS__W 1 +#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 +#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 + +#define SIO_PDR_OHW_CFG_ASEL__B 3 +#define SIO_PDR_OHW_CFG_ASEL__W 3 +#define SIO_PDR_OHW_CFG_ASEL__M 0x38 +#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_SPEED__B 6 +#define SIO_PDR_OHW_CFG_SPEED__W 1 +#define SIO_PDR_OHW_CFG_SPEED__M 0x40 +#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 + +#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 +#define SIO_PDR_I2S_WS_CFG__W 9 +#define SIO_PDR_I2S_WS_CFG__M 0x1FF +#define SIO_PDR_I2S_WS_CFG__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_MODE__B 0 +#define SIO_PDR_I2S_WS_CFG_MODE__W 3 +#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 +#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 +#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_UIO__B 8 +#define SIO_PDR_I2S_WS_CFG_UIO__W 1 +#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_CFG__A 0x7F0021 +#define SIO_PDR_GPIO_CFG__W 9 +#define SIO_PDR_GPIO_CFG__M 0x1FF +#define SIO_PDR_GPIO_CFG__PRE 0x10 +#define SIO_PDR_GPIO_CFG_MODE__B 0 +#define SIO_PDR_GPIO_CFG_MODE__W 3 +#define SIO_PDR_GPIO_CFG_MODE__M 0x7 +#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 +#define SIO_PDR_GPIO_CFG_DRIVE__B 3 +#define SIO_PDR_GPIO_CFG_DRIVE__W 3 +#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 +#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_GPIO_CFG_KEEP__B 6 +#define SIO_PDR_GPIO_CFG_KEEP__W 2 +#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 +#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 +#define SIO_PDR_GPIO_CFG_UIO__B 8 +#define SIO_PDR_GPIO_CFG_UIO__W 1 +#define SIO_PDR_GPIO_CFG_UIO__M 0x100 +#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MSTRT_CFG__A 0x7F0025 +#define SIO_PDR_MSTRT_CFG__W 9 +#define SIO_PDR_MSTRT_CFG__M 0x1FF +#define SIO_PDR_MSTRT_CFG__PRE 0x50 +#define SIO_PDR_MSTRT_CFG_MODE__B 0 +#define SIO_PDR_MSTRT_CFG_MODE__W 3 +#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 +#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 +#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 +#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MSTRT_CFG_KEEP__B 6 +#define SIO_PDR_MSTRT_CFG_KEEP__W 2 +#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 +#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MSTRT_CFG_UIO__B 8 +#define SIO_PDR_MSTRT_CFG_UIO__W 1 +#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 +#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MERR_CFG__A 0x7F0026 +#define SIO_PDR_MERR_CFG__W 9 +#define SIO_PDR_MERR_CFG__M 0x1FF +#define SIO_PDR_MERR_CFG__PRE 0x50 +#define SIO_PDR_MERR_CFG_MODE__B 0 +#define SIO_PDR_MERR_CFG_MODE__W 3 +#define SIO_PDR_MERR_CFG_MODE__M 0x7 +#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 +#define SIO_PDR_MERR_CFG_DRIVE__B 3 +#define SIO_PDR_MERR_CFG_DRIVE__W 3 +#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 +#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MERR_CFG_KEEP__B 6 +#define SIO_PDR_MERR_CFG_KEEP__W 2 +#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 +#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MERR_CFG_UIO__B 8 +#define SIO_PDR_MERR_CFG_UIO__W 1 +#define SIO_PDR_MERR_CFG_UIO__M 0x100 +#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MCLK_CFG__A 0x7F0028 +#define SIO_PDR_MCLK_CFG__W 9 +#define SIO_PDR_MCLK_CFG__M 0x1FF +#define SIO_PDR_MCLK_CFG__PRE 0x50 +#define SIO_PDR_MCLK_CFG_MODE__B 0 +#define SIO_PDR_MCLK_CFG_MODE__W 3 +#define SIO_PDR_MCLK_CFG_MODE__M 0x7 +#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 +#define SIO_PDR_MCLK_CFG_DRIVE__B 3 +#define SIO_PDR_MCLK_CFG_DRIVE__W 3 +#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 +#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MCLK_CFG_KEEP__B 6 +#define SIO_PDR_MCLK_CFG_KEEP__W 2 +#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 +#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MCLK_CFG_UIO__B 8 +#define SIO_PDR_MCLK_CFG_UIO__W 1 +#define SIO_PDR_MCLK_CFG_UIO__M 0x100 +#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MVAL_CFG__A 0x7F0029 +#define SIO_PDR_MVAL_CFG__W 9 +#define SIO_PDR_MVAL_CFG__M 0x1FF +#define SIO_PDR_MVAL_CFG__PRE 0x50 +#define SIO_PDR_MVAL_CFG_MODE__B 0 +#define SIO_PDR_MVAL_CFG_MODE__W 3 +#define SIO_PDR_MVAL_CFG_MODE__M 0x7 +#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 +#define SIO_PDR_MVAL_CFG_DRIVE__B 3 +#define SIO_PDR_MVAL_CFG_DRIVE__W 3 +#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 +#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MVAL_CFG_KEEP__B 6 +#define SIO_PDR_MVAL_CFG_KEEP__W 2 +#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 +#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MVAL_CFG_UIO__B 8 +#define SIO_PDR_MVAL_CFG_UIO__W 1 +#define SIO_PDR_MVAL_CFG_UIO__M 0x100 +#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD0_CFG__A 0x7F002A +#define SIO_PDR_MD0_CFG__W 9 +#define SIO_PDR_MD0_CFG__M 0x1FF +#define SIO_PDR_MD0_CFG__PRE 0x50 +#define SIO_PDR_MD0_CFG_MODE__B 0 +#define SIO_PDR_MD0_CFG_MODE__W 3 +#define SIO_PDR_MD0_CFG_MODE__M 0x7 +#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD0_CFG_DRIVE__B 3 +#define SIO_PDR_MD0_CFG_DRIVE__W 3 +#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD0_CFG_KEEP__B 6 +#define SIO_PDR_MD0_CFG_KEEP__W 2 +#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD0_CFG_UIO__B 8 +#define SIO_PDR_MD0_CFG_UIO__W 1 +#define SIO_PDR_MD0_CFG_UIO__M 0x100 +#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD1_CFG__A 0x7F002B +#define SIO_PDR_MD1_CFG__W 9 +#define SIO_PDR_MD1_CFG__M 0x1FF +#define SIO_PDR_MD1_CFG__PRE 0x50 +#define SIO_PDR_MD1_CFG_MODE__B 0 +#define SIO_PDR_MD1_CFG_MODE__W 3 +#define SIO_PDR_MD1_CFG_MODE__M 0x7 +#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD1_CFG_DRIVE__B 3 +#define SIO_PDR_MD1_CFG_DRIVE__W 3 +#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD1_CFG_KEEP__B 6 +#define SIO_PDR_MD1_CFG_KEEP__W 2 +#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD1_CFG_UIO__B 8 +#define SIO_PDR_MD1_CFG_UIO__W 1 +#define SIO_PDR_MD1_CFG_UIO__M 0x100 +#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD2_CFG__A 0x7F002C +#define SIO_PDR_MD2_CFG__W 9 +#define SIO_PDR_MD2_CFG__M 0x1FF +#define SIO_PDR_MD2_CFG__PRE 0x50 +#define SIO_PDR_MD2_CFG_MODE__B 0 +#define SIO_PDR_MD2_CFG_MODE__W 3 +#define SIO_PDR_MD2_CFG_MODE__M 0x7 +#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD2_CFG_DRIVE__B 3 +#define SIO_PDR_MD2_CFG_DRIVE__W 3 +#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD2_CFG_KEEP__B 6 +#define SIO_PDR_MD2_CFG_KEEP__W 2 +#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD2_CFG_UIO__B 8 +#define SIO_PDR_MD2_CFG_UIO__W 1 +#define SIO_PDR_MD2_CFG_UIO__M 0x100 +#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD3_CFG__A 0x7F002D +#define SIO_PDR_MD3_CFG__W 9 +#define SIO_PDR_MD3_CFG__M 0x1FF +#define SIO_PDR_MD3_CFG__PRE 0x50 +#define SIO_PDR_MD3_CFG_MODE__B 0 +#define SIO_PDR_MD3_CFG_MODE__W 3 +#define SIO_PDR_MD3_CFG_MODE__M 0x7 +#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD3_CFG_DRIVE__B 3 +#define SIO_PDR_MD3_CFG_DRIVE__W 3 +#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD3_CFG_KEEP__B 6 +#define SIO_PDR_MD3_CFG_KEEP__W 2 +#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD3_CFG_UIO__B 8 +#define SIO_PDR_MD3_CFG_UIO__W 1 +#define SIO_PDR_MD3_CFG_UIO__M 0x100 +#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD4_CFG__A 0x7F002F +#define SIO_PDR_MD4_CFG__W 9 +#define SIO_PDR_MD4_CFG__M 0x1FF +#define SIO_PDR_MD4_CFG__PRE 0x50 +#define SIO_PDR_MD4_CFG_MODE__B 0 +#define SIO_PDR_MD4_CFG_MODE__W 3 +#define SIO_PDR_MD4_CFG_MODE__M 0x7 +#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD4_CFG_DRIVE__B 3 +#define SIO_PDR_MD4_CFG_DRIVE__W 3 +#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD4_CFG_KEEP__B 6 +#define SIO_PDR_MD4_CFG_KEEP__W 2 +#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD4_CFG_UIO__B 8 +#define SIO_PDR_MD4_CFG_UIO__W 1 +#define SIO_PDR_MD4_CFG_UIO__M 0x100 +#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD5_CFG__A 0x7F0030 +#define SIO_PDR_MD5_CFG__W 9 +#define SIO_PDR_MD5_CFG__M 0x1FF +#define SIO_PDR_MD5_CFG__PRE 0x50 +#define SIO_PDR_MD5_CFG_MODE__B 0 +#define SIO_PDR_MD5_CFG_MODE__W 3 +#define SIO_PDR_MD5_CFG_MODE__M 0x7 +#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD5_CFG_DRIVE__B 3 +#define SIO_PDR_MD5_CFG_DRIVE__W 3 +#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD5_CFG_KEEP__B 6 +#define SIO_PDR_MD5_CFG_KEEP__W 2 +#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD5_CFG_UIO__B 8 +#define SIO_PDR_MD5_CFG_UIO__W 1 +#define SIO_PDR_MD5_CFG_UIO__M 0x100 +#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD6_CFG__A 0x7F0031 +#define SIO_PDR_MD6_CFG__W 9 +#define SIO_PDR_MD6_CFG__M 0x1FF +#define SIO_PDR_MD6_CFG__PRE 0x50 +#define SIO_PDR_MD6_CFG_MODE__B 0 +#define SIO_PDR_MD6_CFG_MODE__W 3 +#define SIO_PDR_MD6_CFG_MODE__M 0x7 +#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD6_CFG_DRIVE__B 3 +#define SIO_PDR_MD6_CFG_DRIVE__W 3 +#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD6_CFG_KEEP__B 6 +#define SIO_PDR_MD6_CFG_KEEP__W 2 +#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD6_CFG_UIO__B 8 +#define SIO_PDR_MD6_CFG_UIO__W 1 +#define SIO_PDR_MD6_CFG_UIO__M 0x100 +#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD7_CFG__A 0x7F0032 +#define SIO_PDR_MD7_CFG__W 9 +#define SIO_PDR_MD7_CFG__M 0x1FF +#define SIO_PDR_MD7_CFG__PRE 0x50 +#define SIO_PDR_MD7_CFG_MODE__B 0 +#define SIO_PDR_MD7_CFG_MODE__W 3 +#define SIO_PDR_MD7_CFG_MODE__M 0x7 +#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD7_CFG_DRIVE__B 3 +#define SIO_PDR_MD7_CFG_DRIVE__W 3 +#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD7_CFG_KEEP__B 6 +#define SIO_PDR_MD7_CFG_KEEP__W 2 +#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD7_CFG_UIO__B 8 +#define SIO_PDR_MD7_CFG_UIO__W 1 +#define SIO_PDR_MD7_CFG_UIO__M 0x100 +#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 +#define SIO_PDR_I2C_SCL1_CFG__W 9 +#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 +#define SIO_PDR_I2C_SDA1_CFG__W 9 +#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_VSYNC_CFG__A 0x7F0036 +#define SIO_PDR_VSYNC_CFG__W 9 +#define SIO_PDR_VSYNC_CFG__M 0x1FF +#define SIO_PDR_VSYNC_CFG__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_MODE__B 0 +#define SIO_PDR_VSYNC_CFG_MODE__W 3 +#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 +#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 +#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_KEEP__B 6 +#define SIO_PDR_VSYNC_CFG_KEEP__W 2 +#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 +#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_UIO__B 8 +#define SIO_PDR_VSYNC_CFG_UIO__W 1 +#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 +#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 +#define SIO_PDR_SMA_RX_CFG__W 9 +#define SIO_PDR_SMA_RX_CFG__M 0x1FF +#define SIO_PDR_SMA_RX_CFG__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_MODE__B 0 +#define SIO_PDR_SMA_RX_CFG_MODE__W 3 +#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_UIO__B 8 +#define SIO_PDR_SMA_RX_CFG_UIO__W 1 +#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +#define SIO_PDR_SMA_TX_CFG__W 9 +#define SIO_PDR_SMA_TX_CFG__M 0x1FF +#define SIO_PDR_SMA_TX_CFG__PRE 0x90 +#define SIO_PDR_SMA_TX_CFG_MODE__B 0 +#define SIO_PDR_SMA_TX_CFG_MODE__W 3 +#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 +#define SIO_PDR_SMA_TX_CFG_UIO__B 8 +#define SIO_PDR_SMA_TX_CFG_UIO__W 1 +#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F +#define SIO_PDR_I2C_SDA2_CFG__W 9 +#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 +#define SIO_PDR_I2C_SCL2_CFG__W 9 +#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 +#define SIO_PDR_I2S_CL_CFG__W 9 +#define SIO_PDR_I2S_CL_CFG__M 0x1FF +#define SIO_PDR_I2S_CL_CFG__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_MODE__B 0 +#define SIO_PDR_I2S_CL_CFG_MODE__W 3 +#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 +#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 +#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_UIO__B 8 +#define SIO_PDR_I2S_CL_CFG_UIO__W 1 +#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 +#define SIO_PDR_I2S_DA_CFG__W 9 +#define SIO_PDR_I2S_DA_CFG__M 0x1FF +#define SIO_PDR_I2S_DA_CFG__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_MODE__B 0 +#define SIO_PDR_I2S_DA_CFG_MODE__W 3 +#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 +#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 +#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_UIO__B 8 +#define SIO_PDR_I2S_DA_CFG_UIO__W 1 +#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 +#define SIO_PDR_GPIO_GPIO_FNC__W 2 +#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 +#define SIO_PDR_MSTRT_GPIO_FNC__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 +#define SIO_PDR_MERR_GPIO_FNC__W 2 +#define SIO_PDR_MERR_GPIO_FNC__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 +#define SIO_PDR_MCLK_GPIO_FNC__W 2 +#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 +#define SIO_PDR_MVAL_GPIO_FNC__W 2 +#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 +#define SIO_PDR_MD0_GPIO_FNC__W 2 +#define SIO_PDR_MD0_GPIO_FNC__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 +#define SIO_PDR_MD1_GPIO_FNC__W 2 +#define SIO_PDR_MD1_GPIO_FNC__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 +#define SIO_PDR_MD2_GPIO_FNC__W 2 +#define SIO_PDR_MD2_GPIO_FNC__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 +#define SIO_PDR_MD3_GPIO_FNC__W 2 +#define SIO_PDR_MD3_GPIO_FNC__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A +#define SIO_PDR_MD4_GPIO_FNC__W 2 +#define SIO_PDR_MD4_GPIO_FNC__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B +#define SIO_PDR_MD5_GPIO_FNC__W 2 +#define SIO_PDR_MD5_GPIO_FNC__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C +#define SIO_PDR_MD6_GPIO_FNC__W 2 +#define SIO_PDR_MD6_GPIO_FNC__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D +#define SIO_PDR_MD7_GPIO_FNC__W 2 +#define SIO_PDR_MD7_GPIO_FNC__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E +#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F +#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 + +#endif + + diff --git a/frontends/drxk_map_b.h b/frontends/drxk_map_b.h index 8a50a52..9d7055a 100644 --- a/frontends/drxk_map_b.h +++ b/frontends/drxk_map_b.h @@ -1,4340 +1,4340 @@ -#define AUD_COMM_EXEC_STOP 0x0 -#define AUD_COMM_EXEC__A 0x1000000 -#define FEC_COMM_EXEC_ACTIVE 0x1 -#define FEC_COMM_EXEC_ACTIVE 0x1 -#define FEC_COMM_EXEC_STOP 0x0 -#define FEC_COMM_EXEC__A 0x1C00000 -#define FEC_COMM_EXEC__A 0x1C00000 -#define FEC_COMM_EXEC__A 0x1C00000 -#define FEC_DI_COMM_EXEC_STOP 0x0 -#define FEC_DI_COMM_EXEC__A 0x1C20000 -#define FEC_DI_INPUT_CTL__A 0x1C20016 -#define FEC_OC_AVR_PARM_A__A 0x1C40026 -#define FEC_OC_AVR_PARM_B__A 0x1C40027 -#define FEC_OC_COMM_MB_CTL_ON 0x1 -#define FEC_OC_COMM_MB__A 0x1C40002 -#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 -#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 -#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 -#define FEC_OC_DTO_MODE__A 0x1C40014 -#define FEC_OC_DTO_PERIOD__A 0x1C40015 -#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 -#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 -#define FEC_OC_FCT_MODE__A 0x1C4001A -#define FEC_OC_FCT_MODE__PRE 0x0 -#define FEC_OC_IPR_INVERT_MCLK__M 0x800 -#define FEC_OC_IPR_INVERT_MD0__B 0 -#define FEC_OC_IPR_INVERT_MD0__M 0x1 -#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD0__W 1 -#define FEC_OC_IPR_INVERT_MD1__B 1 -#define FEC_OC_IPR_INVERT_MD1__M 0x2 -#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD1__W 1 -#define FEC_OC_IPR_INVERT_MD2__B 2 -#define FEC_OC_IPR_INVERT_MD2__M 0x4 -#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD2__W 1 -#define FEC_OC_IPR_INVERT_MD3__B 3 -#define FEC_OC_IPR_INVERT_MD3__M 0x8 -#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD3__W 1 -#define FEC_OC_IPR_INVERT_MD4__B 4 -#define FEC_OC_IPR_INVERT_MD4__M 0x10 -#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD4__W 1 -#define FEC_OC_IPR_INVERT_MD5__B 5 -#define FEC_OC_IPR_INVERT_MD5__M 0x20 -#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD5__W 1 -#define FEC_OC_IPR_INVERT_MD6__B 6 -#define FEC_OC_IPR_INVERT_MD6__M 0x40 -#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD6__W 1 -#define FEC_OC_IPR_INVERT_MD7__B 7 -#define FEC_OC_IPR_INVERT_MD7__M 0x80 -#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD7__W 1 -#define FEC_OC_IPR_INVERT_MERR__M 0x100 -#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 -#define FEC_OC_IPR_INVERT_MVAL__M 0x400 -#define FEC_OC_IPR_INVERT__A 0x1C40049 -#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 -#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 -#define FEC_OC_IPR_MODE_SERIAL__M 0x1 -#define FEC_OC_IPR_MODE__A 0x1C40048 -#define FEC_OC_IPR_MODE__A 0x1C40048 -#define FEC_OC_MODE_PARITY__M 0x1 -#define FEC_OC_MODE__A 0x1C40011 -#define FEC_OC_OCR_INVERT__A 0x1C40052 -#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 -#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 -#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 -#define FEC_OC_RCN_GAIN__A 0x1C4002E -#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 -#define FEC_OC_SNC_HWM__A 0x1C40042 -#define FEC_OC_SNC_LWM__A 0x1C40041 -#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 -#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 -#define FEC_OC_SNC_MODE__A 0x1C40040 -#define FEC_OC_SNC_MODE__A 0x1C40040 -#define FEC_OC_SNC_UNLOCK__A 0x1C40043 -#define FEC_OC_TMD_COUNT__A 0x1C4001F -#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 -#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 -#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 -#define FEC_OC_TMD_MODE__A 0x1C4001E -#define FEC_RS_COMM_EXEC_STOP 0x0 -#define FEC_RS_COMM_EXEC__A 0x1C30000 -#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 -#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 -#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 -#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 -#define IQM_AF_AGC_IF__A 0x1870028 -#define IQM_AF_AGC_RF__A 0x1870029 -#define IQM_AF_AMUX_SIGNAL2ADC 0x1 -#define IQM_AF_AMUX_SIGNAL2ADC 0x1 -#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 -#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 -#define IQM_AF_AMUX__A 0x187002D -#define IQM_AF_AMUX__A 0x187002D -#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 -#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 -#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 -#define IQM_AF_CLKNEG__A 0x1870012 -#define IQM_AF_CLP_LEN__A 0x1870023 -#define IQM_AF_CLP_LEN__A 0x1870023 -#define IQM_AF_CLP_TH__A 0x1870024 -#define IQM_AF_CLP_TH__A 0x1870024 -#define IQM_AF_COMM_EXEC_ACTIVE 0x1 -#define IQM_AF_COMM_EXEC__A 0x1870000 -#define IQM_AF_INC_BYPASS__A 0x1870036 -#define IQM_AF_INC_LCT__A 0x1870034 -#define IQM_AF_PDREF__A 0x187002B -#define IQM_AF_PDREF__M 0x1F -#define IQM_AF_PHASE0__A 0x187001C -#define IQM_AF_PHASE0__M 0x7F -#define IQM_AF_PHASE0__PRE 0x0 -#define IQM_AF_PHASE0__W 7 -#define IQM_AF_PHASE1__A 0x187001D -#define IQM_AF_PHASE1__M 0x7F -#define IQM_AF_PHASE1__PRE 0x0 -#define IQM_AF_PHASE1__W 7 -#define IQM_AF_PHASE2__A 0x187001E -#define IQM_AF_PHASE2__M 0x7F -#define IQM_AF_PHASE2__PRE 0x0 -#define IQM_AF_PHASE2__W 7 -#define IQM_AF_SNS_LEN__A 0x1870026 -#define IQM_AF_SNS_LEN__A 0x1870026 -#define IQM_AF_START_LOCK__A 0x187001B -#define IQM_AF_START_LOCK__A 0x187001B -#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 -#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 -#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 -#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 -#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 -#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 -#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 -#define IQM_AF_STDBY__A 0x187002C -#define IQM_AF_STDBY__A 0x187002C -#define IQM_AF_STDBY__A 0x187002C -#define IQM_AF_UPD_SEL__A 0x187002F -#define IQM_AF_UPD_SEL__A 0x187002F -#define IQM_CF_ADJ_SEL__A 0x1860013 -#define IQM_CF_BYPASSDET__A 0x1860067 -#define IQM_CF_BYPASSDET__A 0x1860067 -#define IQM_CF_CLP_VAL__A 0x1860060 -#define IQM_CF_COMM_INT_MSK__A 0x1860006 -#define IQM_CF_DATATH__A 0x1860061 -#define IQM_CF_DATATH__A 0x1860061 -#define IQM_CF_DET_LCT__A 0x1860064 -#define IQM_CF_DET_LCT__A 0x1860064 -#define IQM_CF_DS_ENA__A 0x1860019 -#define IQM_CF_MIDTAP_IM__B 1 -#define IQM_CF_MIDTAP_RE__B 0 -#define IQM_CF_MIDTAP__A 0x1860011 -#define IQM_CF_OUT_ENA_QAM__B 1 -#define IQM_CF_OUT_ENA__A 0x1860012 -#define IQM_CF_OUT_ENA__A 0x1860012 -#define IQM_CF_PKDTH__A 0x1860062 -#define IQM_CF_PKDTH__A 0x1860062 -#define IQM_CF_POW_MEAS_LEN__A 0x1860017 -#define IQM_CF_POW_MEAS_LEN__A 0x1860017 -#define IQM_CF_SCALE_SH__A 0x1860015 -#define IQM_CF_SCALE_SH__A 0x1860015 -#define IQM_CF_SCALE_SH__PRE 0x0 -#define IQM_CF_SCALE__A 0x1860014 -#define IQM_CF_SYMMETRIC__A 0x1860010 -#define IQM_CF_TAP_IM0_B__B 0 -#define IQM_CF_TAP_IM0_B__M 0x7F -#define IQM_CF_TAP_IM0_B__PRE 0x2 -#define IQM_CF_TAP_IM0_B__W 7 -#define IQM_CF_TAP_IM0__A 0x1860040 -#define IQM_CF_TAP_IM0__M 0x7F -#define IQM_CF_TAP_IM0__PRE 0x2 -#define IQM_CF_TAP_IM0__W 7 -#define IQM_CF_TAP_IM10_B__B 0 -#define IQM_CF_TAP_IM10_B__M 0x1FF -#define IQM_CF_TAP_IM10_B__PRE 0x2 -#define IQM_CF_TAP_IM10_B__W 9 -#define IQM_CF_TAP_IM10__A 0x186004A -#define IQM_CF_TAP_IM10__M 0x1FF -#define IQM_CF_TAP_IM10__PRE 0x2 -#define IQM_CF_TAP_IM10__W 9 -#define IQM_CF_TAP_IM11_B__B 0 -#define IQM_CF_TAP_IM11_B__M 0x1FF -#define IQM_CF_TAP_IM11_B__PRE 0x2 -#define IQM_CF_TAP_IM11_B__W 9 -#define IQM_CF_TAP_IM11__A 0x186004B -#define IQM_CF_TAP_IM11__M 0x1FF -#define IQM_CF_TAP_IM11__PRE 0x2 -#define IQM_CF_TAP_IM11__W 9 -#define IQM_CF_TAP_IM12_B__B 0 -#define IQM_CF_TAP_IM12_B__M 0x1FF -#define IQM_CF_TAP_IM12_B__PRE 0x2 -#define IQM_CF_TAP_IM12_B__W 9 -#define IQM_CF_TAP_IM12__A 0x186004C -#define IQM_CF_TAP_IM12__M 0x1FF -#define IQM_CF_TAP_IM12__PRE 0x2 -#define IQM_CF_TAP_IM12__W 9 -#define IQM_CF_TAP_IM13_B__B 0 -#define IQM_CF_TAP_IM13_B__M 0x1FF -#define IQM_CF_TAP_IM13_B__PRE 0x2 -#define IQM_CF_TAP_IM13_B__W 9 -#define IQM_CF_TAP_IM13__A 0x186004D -#define IQM_CF_TAP_IM13__M 0x1FF -#define IQM_CF_TAP_IM13__PRE 0x2 -#define IQM_CF_TAP_IM13__W 9 -#define IQM_CF_TAP_IM14_B__B 0 -#define IQM_CF_TAP_IM14_B__M 0x1FF -#define IQM_CF_TAP_IM14_B__PRE 0x2 -#define IQM_CF_TAP_IM14_B__W 9 -#define IQM_CF_TAP_IM14__A 0x186004E -#define IQM_CF_TAP_IM14__M 0x1FF -#define IQM_CF_TAP_IM14__PRE 0x2 -#define IQM_CF_TAP_IM14__W 9 -#define IQM_CF_TAP_IM15_B__B 0 -#define IQM_CF_TAP_IM15_B__M 0x1FF -#define IQM_CF_TAP_IM15_B__PRE 0x2 -#define IQM_CF_TAP_IM15_B__W 9 -#define IQM_CF_TAP_IM15__A 0x186004F -#define IQM_CF_TAP_IM15__M 0x1FF -#define IQM_CF_TAP_IM15__PRE 0x2 -#define IQM_CF_TAP_IM15__W 9 -#define IQM_CF_TAP_IM16_B__B 0 -#define IQM_CF_TAP_IM16_B__M 0x1FF -#define IQM_CF_TAP_IM16_B__PRE 0x2 -#define IQM_CF_TAP_IM16_B__W 9 -#define IQM_CF_TAP_IM16__A 0x1860050 -#define IQM_CF_TAP_IM16__M 0x1FF -#define IQM_CF_TAP_IM16__PRE 0x2 -#define IQM_CF_TAP_IM16__W 9 -#define IQM_CF_TAP_IM17_B__B 0 -#define IQM_CF_TAP_IM17_B__M 0x1FF -#define IQM_CF_TAP_IM17_B__PRE 0x2 -#define IQM_CF_TAP_IM17_B__W 9 -#define IQM_CF_TAP_IM17__A 0x1860051 -#define IQM_CF_TAP_IM17__M 0x1FF -#define IQM_CF_TAP_IM17__PRE 0x2 -#define IQM_CF_TAP_IM17__W 9 -#define IQM_CF_TAP_IM18_B__B 0 -#define IQM_CF_TAP_IM18_B__M 0x1FF -#define IQM_CF_TAP_IM18_B__PRE 0x2 -#define IQM_CF_TAP_IM18_B__W 9 -#define IQM_CF_TAP_IM18__A 0x1860052 -#define IQM_CF_TAP_IM18__M 0x1FF -#define IQM_CF_TAP_IM18__PRE 0x2 -#define IQM_CF_TAP_IM18__W 9 -#define IQM_CF_TAP_IM19_B__B 0 -#define IQM_CF_TAP_IM19_B__M 0x1FF -#define IQM_CF_TAP_IM19_B__PRE 0x2 -#define IQM_CF_TAP_IM19_B__W 9 -#define IQM_CF_TAP_IM19__A 0x1860053 -#define IQM_CF_TAP_IM19__M 0x1FF -#define IQM_CF_TAP_IM19__PRE 0x2 -#define IQM_CF_TAP_IM19__W 9 -#define IQM_CF_TAP_IM1_B__B 0 -#define IQM_CF_TAP_IM1_B__M 0x7F -#define IQM_CF_TAP_IM1_B__PRE 0x2 -#define IQM_CF_TAP_IM1_B__W 7 -#define IQM_CF_TAP_IM1__A 0x1860041 -#define IQM_CF_TAP_IM1__M 0x7F -#define IQM_CF_TAP_IM1__PRE 0x2 -#define IQM_CF_TAP_IM1__W 7 -#define IQM_CF_TAP_IM20_B__B 0 -#define IQM_CF_TAP_IM20_B__M 0x1FF -#define IQM_CF_TAP_IM20_B__PRE 0x2 -#define IQM_CF_TAP_IM20_B__W 9 -#define IQM_CF_TAP_IM20__A 0x1860054 -#define IQM_CF_TAP_IM20__M 0x1FF -#define IQM_CF_TAP_IM20__PRE 0x2 -#define IQM_CF_TAP_IM20__W 9 -#define IQM_CF_TAP_IM21_B__B 0 -#define IQM_CF_TAP_IM21_B__M 0x7FF -#define IQM_CF_TAP_IM21_B__PRE 0x2 -#define IQM_CF_TAP_IM21_B__W 11 -#define IQM_CF_TAP_IM21__A 0x1860055 -#define IQM_CF_TAP_IM21__M 0x7FF -#define IQM_CF_TAP_IM21__PRE 0x2 -#define IQM_CF_TAP_IM21__W 11 -#define IQM_CF_TAP_IM22_B__B 0 -#define IQM_CF_TAP_IM22_B__M 0x7FF -#define IQM_CF_TAP_IM22_B__PRE 0x2 -#define IQM_CF_TAP_IM22_B__W 11 -#define IQM_CF_TAP_IM22__A 0x1860056 -#define IQM_CF_TAP_IM22__M 0x7FF -#define IQM_CF_TAP_IM22__PRE 0x2 -#define IQM_CF_TAP_IM22__W 11 -#define IQM_CF_TAP_IM23_B__B 0 -#define IQM_CF_TAP_IM23_B__M 0x7FF -#define IQM_CF_TAP_IM23_B__PRE 0x2 -#define IQM_CF_TAP_IM23_B__W 11 -#define IQM_CF_TAP_IM23__A 0x1860057 -#define IQM_CF_TAP_IM23__M 0x7FF -#define IQM_CF_TAP_IM23__PRE 0x2 -#define IQM_CF_TAP_IM23__W 11 -#define IQM_CF_TAP_IM24_B__B 0 -#define IQM_CF_TAP_IM24_B__M 0x7FF -#define IQM_CF_TAP_IM24_B__PRE 0x2 -#define IQM_CF_TAP_IM24_B__W 11 -#define IQM_CF_TAP_IM24__A 0x1860058 -#define IQM_CF_TAP_IM24__M 0x7FF -#define IQM_CF_TAP_IM24__PRE 0x2 -#define IQM_CF_TAP_IM24__W 11 -#define IQM_CF_TAP_IM25_B__B 0 -#define IQM_CF_TAP_IM25_B__M 0x7FF -#define IQM_CF_TAP_IM25_B__PRE 0x2 -#define IQM_CF_TAP_IM25_B__W 11 -#define IQM_CF_TAP_IM25__A 0x1860059 -#define IQM_CF_TAP_IM25__M 0x7FF -#define IQM_CF_TAP_IM25__PRE 0x2 -#define IQM_CF_TAP_IM25__W 11 -#define IQM_CF_TAP_IM26_B__B 0 -#define IQM_CF_TAP_IM26_B__M 0x7FF -#define IQM_CF_TAP_IM26_B__PRE 0x2 -#define IQM_CF_TAP_IM26_B__W 11 -#define IQM_CF_TAP_IM26__A 0x186005A -#define IQM_CF_TAP_IM26__M 0x7FF -#define IQM_CF_TAP_IM26__PRE 0x2 -#define IQM_CF_TAP_IM26__W 11 -#define IQM_CF_TAP_IM27_B__B 0 -#define IQM_CF_TAP_IM27_B__M 0x7FF -#define IQM_CF_TAP_IM27_B__PRE 0x2 -#define IQM_CF_TAP_IM27_B__W 11 -#define IQM_CF_TAP_IM27__A 0x186005B -#define IQM_CF_TAP_IM27__M 0x7FF -#define IQM_CF_TAP_IM27__PRE 0x2 -#define IQM_CF_TAP_IM27__W 11 -#define IQM_CF_TAP_IM2_B__B 0 -#define IQM_CF_TAP_IM2_B__M 0x7F -#define IQM_CF_TAP_IM2_B__PRE 0x2 -#define IQM_CF_TAP_IM2_B__W 7 -#define IQM_CF_TAP_IM2__A 0x1860042 -#define IQM_CF_TAP_IM2__M 0x7F -#define IQM_CF_TAP_IM2__PRE 0x2 -#define IQM_CF_TAP_IM2__W 7 -#define IQM_CF_TAP_IM3_B__B 0 -#define IQM_CF_TAP_IM3_B__M 0x7F -#define IQM_CF_TAP_IM3_B__PRE 0x2 -#define IQM_CF_TAP_IM3_B__W 7 -#define IQM_CF_TAP_IM3__A 0x1860043 -#define IQM_CF_TAP_IM3__M 0x7F -#define IQM_CF_TAP_IM3__PRE 0x2 -#define IQM_CF_TAP_IM3__W 7 -#define IQM_CF_TAP_IM4_B__B 0 -#define IQM_CF_TAP_IM4_B__M 0x7F -#define IQM_CF_TAP_IM4_B__PRE 0x2 -#define IQM_CF_TAP_IM4_B__W 7 -#define IQM_CF_TAP_IM4__A 0x1860044 -#define IQM_CF_TAP_IM4__M 0x7F -#define IQM_CF_TAP_IM4__PRE 0x2 -#define IQM_CF_TAP_IM4__W 7 -#define IQM_CF_TAP_IM5_B__B 0 -#define IQM_CF_TAP_IM5_B__M 0x7F -#define IQM_CF_TAP_IM5_B__PRE 0x2 -#define IQM_CF_TAP_IM5_B__W 7 -#define IQM_CF_TAP_IM5__A 0x1860045 -#define IQM_CF_TAP_IM5__M 0x7F -#define IQM_CF_TAP_IM5__PRE 0x2 -#define IQM_CF_TAP_IM5__W 7 -#define IQM_CF_TAP_IM6_B__B 0 -#define IQM_CF_TAP_IM6_B__M 0x7F -#define IQM_CF_TAP_IM6_B__PRE 0x2 -#define IQM_CF_TAP_IM6_B__W 7 -#define IQM_CF_TAP_IM6__A 0x1860046 -#define IQM_CF_TAP_IM6__M 0x7F -#define IQM_CF_TAP_IM6__PRE 0x2 -#define IQM_CF_TAP_IM6__W 7 -#define IQM_CF_TAP_IM7_B__B 0 -#define IQM_CF_TAP_IM7_B__M 0x1FF -#define IQM_CF_TAP_IM7_B__PRE 0x2 -#define IQM_CF_TAP_IM7_B__W 9 -#define IQM_CF_TAP_IM7__A 0x1860047 -#define IQM_CF_TAP_IM7__M 0x1FF -#define IQM_CF_TAP_IM7__PRE 0x2 -#define IQM_CF_TAP_IM7__W 9 -#define IQM_CF_TAP_IM8_B__B 0 -#define IQM_CF_TAP_IM8_B__M 0x1FF -#define IQM_CF_TAP_IM8_B__PRE 0x2 -#define IQM_CF_TAP_IM8_B__W 9 -#define IQM_CF_TAP_IM8__A 0x1860048 -#define IQM_CF_TAP_IM8__M 0x1FF -#define IQM_CF_TAP_IM8__PRE 0x2 -#define IQM_CF_TAP_IM8__W 9 -#define IQM_CF_TAP_IM9_B__B 0 -#define IQM_CF_TAP_IM9_B__M 0x1FF -#define IQM_CF_TAP_IM9_B__PRE 0x2 -#define IQM_CF_TAP_IM9_B__W 9 -#define IQM_CF_TAP_IM9__A 0x1860049 -#define IQM_CF_TAP_IM9__M 0x1FF -#define IQM_CF_TAP_IM9__PRE 0x2 -#define IQM_CF_TAP_IM9__W 9 -#define IQM_CF_TAP_RE0_B__B 0 -#define IQM_CF_TAP_RE0_B__M 0x7F -#define IQM_CF_TAP_RE0_B__PRE 0x2 -#define IQM_CF_TAP_RE0_B__W 7 -#define IQM_CF_TAP_RE0__A 0x1860020 -#define IQM_CF_TAP_RE0__M 0x7F -#define IQM_CF_TAP_RE0__PRE 0x2 -#define IQM_CF_TAP_RE0__W 7 -#define IQM_CF_TAP_RE10_B__B 0 -#define IQM_CF_TAP_RE10_B__M 0x1FF -#define IQM_CF_TAP_RE10_B__PRE 0x2 -#define IQM_CF_TAP_RE10_B__W 9 -#define IQM_CF_TAP_RE10__A 0x186002A -#define IQM_CF_TAP_RE10__M 0x1FF -#define IQM_CF_TAP_RE10__PRE 0x2 -#define IQM_CF_TAP_RE10__W 9 -#define IQM_CF_TAP_RE11_B__B 0 -#define IQM_CF_TAP_RE11_B__M 0x1FF -#define IQM_CF_TAP_RE11_B__PRE 0x2 -#define IQM_CF_TAP_RE11_B__W 9 -#define IQM_CF_TAP_RE11__A 0x186002B -#define IQM_CF_TAP_RE11__M 0x1FF -#define IQM_CF_TAP_RE11__PRE 0x2 -#define IQM_CF_TAP_RE11__W 9 -#define IQM_CF_TAP_RE12_B__B 0 -#define IQM_CF_TAP_RE12_B__M 0x1FF -#define IQM_CF_TAP_RE12_B__PRE 0x2 -#define IQM_CF_TAP_RE12_B__W 9 -#define IQM_CF_TAP_RE12__A 0x186002C -#define IQM_CF_TAP_RE12__M 0x1FF -#define IQM_CF_TAP_RE12__PRE 0x2 -#define IQM_CF_TAP_RE12__W 9 -#define IQM_CF_TAP_RE13_B__B 0 -#define IQM_CF_TAP_RE13_B__M 0x1FF -#define IQM_CF_TAP_RE13_B__PRE 0x2 -#define IQM_CF_TAP_RE13_B__W 9 -#define IQM_CF_TAP_RE13__A 0x186002D -#define IQM_CF_TAP_RE13__M 0x1FF -#define IQM_CF_TAP_RE13__PRE 0x2 -#define IQM_CF_TAP_RE13__W 9 -#define IQM_CF_TAP_RE14_B__B 0 -#define IQM_CF_TAP_RE14_B__M 0x1FF -#define IQM_CF_TAP_RE14_B__PRE 0x2 -#define IQM_CF_TAP_RE14_B__W 9 -#define IQM_CF_TAP_RE14__A 0x186002E -#define IQM_CF_TAP_RE14__M 0x1FF -#define IQM_CF_TAP_RE14__PRE 0x2 -#define IQM_CF_TAP_RE14__W 9 -#define IQM_CF_TAP_RE15_B__B 0 -#define IQM_CF_TAP_RE15_B__M 0x1FF -#define IQM_CF_TAP_RE15_B__PRE 0x2 -#define IQM_CF_TAP_RE15_B__W 9 -#define IQM_CF_TAP_RE15__A 0x186002F -#define IQM_CF_TAP_RE15__M 0x1FF -#define IQM_CF_TAP_RE15__PRE 0x2 -#define IQM_CF_TAP_RE15__W 9 -#define IQM_CF_TAP_RE16_B__B 0 -#define IQM_CF_TAP_RE16_B__M 0x1FF -#define IQM_CF_TAP_RE16_B__PRE 0x2 -#define IQM_CF_TAP_RE16_B__W 9 -#define IQM_CF_TAP_RE16__A 0x1860030 -#define IQM_CF_TAP_RE16__M 0x1FF -#define IQM_CF_TAP_RE16__PRE 0x2 -#define IQM_CF_TAP_RE16__W 9 -#define IQM_CF_TAP_RE17_B__B 0 -#define IQM_CF_TAP_RE17_B__M 0x1FF -#define IQM_CF_TAP_RE17_B__PRE 0x2 -#define IQM_CF_TAP_RE17_B__W 9 -#define IQM_CF_TAP_RE17__A 0x1860031 -#define IQM_CF_TAP_RE17__M 0x1FF -#define IQM_CF_TAP_RE17__PRE 0x2 -#define IQM_CF_TAP_RE17__W 9 -#define IQM_CF_TAP_RE18_B__B 0 -#define IQM_CF_TAP_RE18_B__M 0x1FF -#define IQM_CF_TAP_RE18_B__PRE 0x2 -#define IQM_CF_TAP_RE18_B__W 9 -#define IQM_CF_TAP_RE18__A 0x1860032 -#define IQM_CF_TAP_RE18__M 0x1FF -#define IQM_CF_TAP_RE18__PRE 0x2 -#define IQM_CF_TAP_RE18__W 9 -#define IQM_CF_TAP_RE19_B__B 0 -#define IQM_CF_TAP_RE19_B__M 0x1FF -#define IQM_CF_TAP_RE19_B__PRE 0x2 -#define IQM_CF_TAP_RE19_B__W 9 -#define IQM_CF_TAP_RE19__A 0x1860033 -#define IQM_CF_TAP_RE19__M 0x1FF -#define IQM_CF_TAP_RE19__PRE 0x2 -#define IQM_CF_TAP_RE19__W 9 -#define IQM_CF_TAP_RE1_B__B 0 -#define IQM_CF_TAP_RE1_B__M 0x7F -#define IQM_CF_TAP_RE1_B__PRE 0x2 -#define IQM_CF_TAP_RE1_B__W 7 -#define IQM_CF_TAP_RE1__A 0x1860021 -#define IQM_CF_TAP_RE1__M 0x7F -#define IQM_CF_TAP_RE1__PRE 0x2 -#define IQM_CF_TAP_RE1__W 7 -#define IQM_CF_TAP_RE20_B__B 0 -#define IQM_CF_TAP_RE20_B__M 0x1FF -#define IQM_CF_TAP_RE20_B__PRE 0x2 -#define IQM_CF_TAP_RE20_B__W 9 -#define IQM_CF_TAP_RE20__A 0x1860034 -#define IQM_CF_TAP_RE20__M 0x1FF -#define IQM_CF_TAP_RE20__PRE 0x2 -#define IQM_CF_TAP_RE20__W 9 -#define IQM_CF_TAP_RE21_B__B 0 -#define IQM_CF_TAP_RE21_B__M 0x7FF -#define IQM_CF_TAP_RE21_B__PRE 0x2 -#define IQM_CF_TAP_RE21_B__W 11 -#define IQM_CF_TAP_RE21__A 0x1860035 -#define IQM_CF_TAP_RE21__M 0x7FF -#define IQM_CF_TAP_RE21__PRE 0x2 -#define IQM_CF_TAP_RE21__W 11 -#define IQM_CF_TAP_RE22_B__B 0 -#define IQM_CF_TAP_RE22_B__M 0x7FF -#define IQM_CF_TAP_RE22_B__PRE 0x2 -#define IQM_CF_TAP_RE22_B__W 11 -#define IQM_CF_TAP_RE22__A 0x1860036 -#define IQM_CF_TAP_RE22__M 0x7FF -#define IQM_CF_TAP_RE22__PRE 0x2 -#define IQM_CF_TAP_RE22__W 11 -#define IQM_CF_TAP_RE23_B__B 0 -#define IQM_CF_TAP_RE23_B__M 0x7FF -#define IQM_CF_TAP_RE23_B__PRE 0x2 -#define IQM_CF_TAP_RE23_B__W 11 -#define IQM_CF_TAP_RE23__A 0x1860037 -#define IQM_CF_TAP_RE23__M 0x7FF -#define IQM_CF_TAP_RE23__PRE 0x2 -#define IQM_CF_TAP_RE23__W 11 -#define IQM_CF_TAP_RE24_B__B 0 -#define IQM_CF_TAP_RE24_B__M 0x7FF -#define IQM_CF_TAP_RE24_B__PRE 0x2 -#define IQM_CF_TAP_RE24_B__W 11 -#define IQM_CF_TAP_RE24__A 0x1860038 -#define IQM_CF_TAP_RE24__M 0x7FF -#define IQM_CF_TAP_RE24__PRE 0x2 -#define IQM_CF_TAP_RE24__W 11 -#define IQM_CF_TAP_RE25_B__B 0 -#define IQM_CF_TAP_RE25_B__M 0x7FF -#define IQM_CF_TAP_RE25_B__PRE 0x2 -#define IQM_CF_TAP_RE25_B__W 11 -#define IQM_CF_TAP_RE25__A 0x1860039 -#define IQM_CF_TAP_RE25__M 0x7FF -#define IQM_CF_TAP_RE25__PRE 0x2 -#define IQM_CF_TAP_RE25__W 11 -#define IQM_CF_TAP_RE26_B__B 0 -#define IQM_CF_TAP_RE26_B__M 0x7FF -#define IQM_CF_TAP_RE26_B__PRE 0x2 -#define IQM_CF_TAP_RE26_B__W 11 -#define IQM_CF_TAP_RE26__A 0x186003A -#define IQM_CF_TAP_RE26__M 0x7FF -#define IQM_CF_TAP_RE26__PRE 0x2 -#define IQM_CF_TAP_RE26__W 11 -#define IQM_CF_TAP_RE27_B__B 0 -#define IQM_CF_TAP_RE27_B__M 0x7FF -#define IQM_CF_TAP_RE27_B__PRE 0x2 -#define IQM_CF_TAP_RE27_B__W 11 -#define IQM_CF_TAP_RE27__A 0x186003B -#define IQM_CF_TAP_RE27__M 0x7FF -#define IQM_CF_TAP_RE27__PRE 0x2 -#define IQM_CF_TAP_RE27__W 11 -#define IQM_CF_TAP_RE2_B__B 0 -#define IQM_CF_TAP_RE2_B__M 0x7F -#define IQM_CF_TAP_RE2_B__PRE 0x2 -#define IQM_CF_TAP_RE2_B__W 7 -#define IQM_CF_TAP_RE2__A 0x1860022 -#define IQM_CF_TAP_RE2__M 0x7F -#define IQM_CF_TAP_RE2__PRE 0x2 -#define IQM_CF_TAP_RE2__W 7 -#define IQM_CF_TAP_RE3_B__B 0 -#define IQM_CF_TAP_RE3_B__M 0x7F -#define IQM_CF_TAP_RE3_B__PRE 0x2 -#define IQM_CF_TAP_RE3_B__W 7 -#define IQM_CF_TAP_RE3__A 0x1860023 -#define IQM_CF_TAP_RE3__M 0x7F -#define IQM_CF_TAP_RE3__PRE 0x2 -#define IQM_CF_TAP_RE3__W 7 -#define IQM_CF_TAP_RE4_B__B 0 -#define IQM_CF_TAP_RE4_B__M 0x7F -#define IQM_CF_TAP_RE4_B__PRE 0x2 -#define IQM_CF_TAP_RE4_B__W 7 -#define IQM_CF_TAP_RE4__A 0x1860024 -#define IQM_CF_TAP_RE4__M 0x7F -#define IQM_CF_TAP_RE4__PRE 0x2 -#define IQM_CF_TAP_RE4__W 7 -#define IQM_CF_TAP_RE5_B__B 0 -#define IQM_CF_TAP_RE5_B__M 0x7F -#define IQM_CF_TAP_RE5_B__PRE 0x2 -#define IQM_CF_TAP_RE5_B__W 7 -#define IQM_CF_TAP_RE5__A 0x1860025 -#define IQM_CF_TAP_RE5__M 0x7F -#define IQM_CF_TAP_RE5__PRE 0x2 -#define IQM_CF_TAP_RE5__W 7 -#define IQM_CF_TAP_RE6_B__B 0 -#define IQM_CF_TAP_RE6_B__M 0x7F -#define IQM_CF_TAP_RE6_B__PRE 0x2 -#define IQM_CF_TAP_RE6_B__W 7 -#define IQM_CF_TAP_RE6__A 0x1860026 -#define IQM_CF_TAP_RE6__M 0x7F -#define IQM_CF_TAP_RE6__PRE 0x2 -#define IQM_CF_TAP_RE6__W 7 -#define IQM_CF_TAP_RE7_B__B 0 -#define IQM_CF_TAP_RE7_B__M 0x1FF -#define IQM_CF_TAP_RE7_B__PRE 0x2 -#define IQM_CF_TAP_RE7_B__W 9 -#define IQM_CF_TAP_RE7__A 0x1860027 -#define IQM_CF_TAP_RE7__M 0x1FF -#define IQM_CF_TAP_RE7__PRE 0x2 -#define IQM_CF_TAP_RE7__W 9 -#define IQM_CF_TAP_RE8_B__B 0 -#define IQM_CF_TAP_RE8_B__M 0x1FF -#define IQM_CF_TAP_RE8_B__PRE 0x2 -#define IQM_CF_TAP_RE8_B__W 9 -#define IQM_CF_TAP_RE8__A 0x1860028 -#define IQM_CF_TAP_RE8__M 0x1FF -#define IQM_CF_TAP_RE8__PRE 0x2 -#define IQM_CF_TAP_RE8__W 9 -#define IQM_CF_TAP_RE9_B__B 0 -#define IQM_CF_TAP_RE9_B__M 0x1FF -#define IQM_CF_TAP_RE9_B__PRE 0x2 -#define IQM_CF_TAP_RE9_B__W 9 -#define IQM_CF_TAP_RE9__A 0x1860029 -#define IQM_CF_TAP_RE9__M 0x1FF -#define IQM_CF_TAP_RE9__PRE 0x2 -#define IQM_CF_TAP_RE9__W 9 -#define IQM_CF_WND_LEN__A 0x1860063 -#define IQM_CF_WND_LEN__A 0x1860063 -#define IQM_COMM_EXEC_B_ACTIVE 0x1 -#define IQM_COMM_EXEC_B_ACTIVE 0x1 -#define IQM_COMM_EXEC_B_STOP 0x0 -#define IQM_COMM_EXEC_B_STOP 0x0 -#define IQM_COMM_EXEC_B_STOP 0x0 -#define IQM_COMM_EXEC__A 0x1800000 -#define IQM_COMM_EXEC__A 0x1800000 -#define IQM_COMM_EXEC__A 0x1800000 -#define IQM_COMM_EXEC__A 0x1800000 -#define IQM_FD_RATESEL__A 0x1830010 -#define IQM_FS_ADJ_SEL__A 0x1820014 -#define IQM_FS_RATE_LO__A 0x1820012 -#define IQM_FS_RATE_OFS_LO__A 0x1820010 -#define IQM_RC_ADJ_SEL__A 0x1840014 -#define IQM_RC_RATE_OFS_HI__M 0xFF -#define IQM_RC_RATE_OFS_LO__A 0x1840010 -#define IQM_RC_RATE_OFS_LO__A 0x1840010 -#define IQM_RC_RATE_OFS_LO__M 0xFFFF -#define IQM_RC_RATE_OFS_LO__W 16 -#define IQM_RC_STRETCH__A 0x1840016 -#define IQM_RC_STRETCH__A 0x1840016 -#define OFDM_CP_COMM_EXEC_STOP 0x0 -#define OFDM_CP_COMM_EXEC__A 0x2800000 -#define OFDM_EC_SB_PRIOR_HI 0x0 -#define OFDM_EC_SB_PRIOR__A 0x3410013 -#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 -#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 -#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E -#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 -#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 -#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 -#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 -#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 -#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 -#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 -#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 -#define OFDM_LC_COMM_EXEC_STOP 0x0 -#define OFDM_LC_COMM_EXEC_STOP 0x0 -#define OFDM_LC_COMM_EXEC_STOP 0x0 -#define OFDM_LC_COMM_EXEC__A 0x3800000 -#define OFDM_LC_COMM_EXEC__A 0x3800000 -#define OFDM_LC_COMM_EXEC__A 0x3800000 -#define OFDM_SC_COMM_EXEC_STOP 0x0 -#define OFDM_SC_COMM_EXEC_STOP 0x0 -#define OFDM_SC_COMM_EXEC_STOP 0x0 -#define OFDM_SC_COMM_EXEC_STOP 0x0 -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_STATE__A 0x3C00001 -#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 -#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 -#define OFDM_SC_RA_RAM_CMD_NULL 0x0 -#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 -#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 -#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 -#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 -#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 -#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 -#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 -#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 -#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 -#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F -#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F -#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 -#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 -#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C -#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 -#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 -#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D -#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C -#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 -#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 -#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 -#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 -#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 -#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 -#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 -#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 -#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 -#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 -#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 -#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 -#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 -#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 -#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 -#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 -#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 -#define OFDM_SC_RA_RAM_PARAM0__W 16 -#define OFDM_SC_RA_RAM_PARAM0__W 16 -#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 -#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 -#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 -#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 -#define OFDM_SC_RA_RAM_PARAM1__W 16 -#define OFDM_SC_RA_RAM_PARAM1__W 16 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 -#define QAM_COMM_EXEC_ACTIVE 0x1 -#define QAM_COMM_EXEC_STOP 0x0 -#define QAM_COMM_EXEC_STOP 0x0 -#define QAM_COMM_EXEC__A 0x1400000 -#define QAM_COMM_EXEC__A 0x1400000 -#define QAM_COMM_EXEC__A 0x1400000 -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__PRE 0x4 -#define QAM_DQ_QUAL_FUN0__PRE 0x4 -#define QAM_DQ_QUAL_FUN0__PRE 0x4 -#define QAM_DQ_QUAL_FUN0__PRE 0x4 -#define QAM_DQ_QUAL_FUN0__PRE 0x4 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__PRE 0x4 -#define QAM_DQ_QUAL_FUN1__PRE 0x4 -#define QAM_DQ_QUAL_FUN1__PRE 0x4 -#define QAM_DQ_QUAL_FUN1__PRE 0x4 -#define QAM_DQ_QUAL_FUN1__PRE 0x4 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__PRE 0x4 -#define QAM_DQ_QUAL_FUN2__PRE 0x4 -#define QAM_DQ_QUAL_FUN2__PRE 0x4 -#define QAM_DQ_QUAL_FUN2__PRE 0x4 -#define QAM_DQ_QUAL_FUN2__PRE 0x4 -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__PRE 0x4 -#define QAM_DQ_QUAL_FUN3__PRE 0x4 -#define QAM_DQ_QUAL_FUN3__PRE 0x4 -#define QAM_DQ_QUAL_FUN3__PRE 0x4 -#define QAM_DQ_QUAL_FUN3__PRE 0x4 -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__PRE 0x6 -#define QAM_DQ_QUAL_FUN4__PRE 0x6 -#define QAM_DQ_QUAL_FUN4__PRE 0x6 -#define QAM_DQ_QUAL_FUN4__PRE 0x6 -#define QAM_DQ_QUAL_FUN4__PRE 0x6 -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__PRE 0x6 -#define QAM_DQ_QUAL_FUN5__PRE 0x6 -#define QAM_DQ_QUAL_FUN5__PRE 0x6 -#define QAM_DQ_QUAL_FUN5__PRE 0x6 -#define QAM_DQ_QUAL_FUN5__PRE 0x6 -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_LC_LPF_FACTORI__A 0x1450029 -#define QAM_LC_LPF_FACTORP__A 0x1450028 -#define QAM_LC_MODE__A 0x1450010 -#define QAM_LC_QUAL_TAB0_VALUE__B 0 -#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 -#define QAM_LC_QUAL_TAB0_VALUE__W 5 -#define QAM_LC_QUAL_TAB0__A 0x1450018 -#define QAM_LC_QUAL_TAB0__M 0x1F -#define QAM_LC_QUAL_TAB0__PRE 0x0 -#define QAM_LC_QUAL_TAB0__W 5 -#define QAM_LC_QUAL_TAB10_VALUE__B 0 -#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA -#define QAM_LC_QUAL_TAB10_VALUE__W 5 -#define QAM_LC_QUAL_TAB10__A 0x1450021 -#define QAM_LC_QUAL_TAB10__M 0x1F -#define QAM_LC_QUAL_TAB10__PRE 0xA -#define QAM_LC_QUAL_TAB10__W 5 -#define QAM_LC_QUAL_TAB12_VALUE__B 0 -#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC -#define QAM_LC_QUAL_TAB12_VALUE__W 5 -#define QAM_LC_QUAL_TAB12__A 0x1450022 -#define QAM_LC_QUAL_TAB12__M 0x1F -#define QAM_LC_QUAL_TAB12__PRE 0xC -#define QAM_LC_QUAL_TAB12__W 5 -#define QAM_LC_QUAL_TAB15_VALUE__B 0 -#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF -#define QAM_LC_QUAL_TAB15_VALUE__W 5 -#define QAM_LC_QUAL_TAB15__A 0x1450023 -#define QAM_LC_QUAL_TAB15__M 0x1F -#define QAM_LC_QUAL_TAB15__PRE 0xF -#define QAM_LC_QUAL_TAB15__W 5 -#define QAM_LC_QUAL_TAB16_VALUE__B 0 -#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 -#define QAM_LC_QUAL_TAB16_VALUE__W 5 -#define QAM_LC_QUAL_TAB16__A 0x1450024 -#define QAM_LC_QUAL_TAB16__M 0x1F -#define QAM_LC_QUAL_TAB16__PRE 0x10 -#define QAM_LC_QUAL_TAB16__W 5 -#define QAM_LC_QUAL_TAB1_VALUE__B 0 -#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 -#define QAM_LC_QUAL_TAB1_VALUE__W 5 -#define QAM_LC_QUAL_TAB1__A 0x1450019 -#define QAM_LC_QUAL_TAB1__M 0x1F -#define QAM_LC_QUAL_TAB1__PRE 0x1 -#define QAM_LC_QUAL_TAB1__W 5 -#define QAM_LC_QUAL_TAB20_VALUE__B 0 -#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 -#define QAM_LC_QUAL_TAB20_VALUE__W 5 -#define QAM_LC_QUAL_TAB20__A 0x1450025 -#define QAM_LC_QUAL_TAB20__M 0x1F -#define QAM_LC_QUAL_TAB20__PRE 0x14 -#define QAM_LC_QUAL_TAB20__W 5 -#define QAM_LC_QUAL_TAB25_VALUE__B 0 -#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 -#define QAM_LC_QUAL_TAB25_VALUE__W 5 -#define QAM_LC_QUAL_TAB25__A 0x1450026 -#define QAM_LC_QUAL_TAB25__M 0x1F -#define QAM_LC_QUAL_TAB25__PRE 0x19 -#define QAM_LC_QUAL_TAB25__W 5 -#define QAM_LC_QUAL_TAB2_VALUE__B 0 -#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 -#define QAM_LC_QUAL_TAB2_VALUE__W 5 -#define QAM_LC_QUAL_TAB2__A 0x145001A -#define QAM_LC_QUAL_TAB2__M 0x1F -#define QAM_LC_QUAL_TAB2__PRE 0x2 -#define QAM_LC_QUAL_TAB2__W 5 -#define QAM_LC_QUAL_TAB3_VALUE__B 0 -#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 -#define QAM_LC_QUAL_TAB3_VALUE__W 5 -#define QAM_LC_QUAL_TAB3__A 0x145001B -#define QAM_LC_QUAL_TAB3__M 0x1F -#define QAM_LC_QUAL_TAB3__PRE 0x3 -#define QAM_LC_QUAL_TAB3__W 5 -#define QAM_LC_QUAL_TAB4_VALUE__B 0 -#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 -#define QAM_LC_QUAL_TAB4_VALUE__W 5 -#define QAM_LC_QUAL_TAB4__A 0x145001C -#define QAM_LC_QUAL_TAB4__M 0x1F -#define QAM_LC_QUAL_TAB4__PRE 0x4 -#define QAM_LC_QUAL_TAB4__W 5 -#define QAM_LC_QUAL_TAB5_VALUE__B 0 -#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 -#define QAM_LC_QUAL_TAB5_VALUE__W 5 -#define QAM_LC_QUAL_TAB5__A 0x145001D -#define QAM_LC_QUAL_TAB5__M 0x1F -#define QAM_LC_QUAL_TAB5__PRE 0x5 -#define QAM_LC_QUAL_TAB5__W 5 -#define QAM_LC_QUAL_TAB6_VALUE__B 0 -#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 -#define QAM_LC_QUAL_TAB6_VALUE__W 5 -#define QAM_LC_QUAL_TAB6__A 0x145001E -#define QAM_LC_QUAL_TAB6__M 0x1F -#define QAM_LC_QUAL_TAB6__PRE 0x6 -#define QAM_LC_QUAL_TAB6__W 5 -#define QAM_LC_QUAL_TAB8_VALUE__B 0 -#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 -#define QAM_LC_QUAL_TAB8_VALUE__W 5 -#define QAM_LC_QUAL_TAB8__A 0x145001F -#define QAM_LC_QUAL_TAB8__M 0x1F -#define QAM_LC_QUAL_TAB8__PRE 0x8 -#define QAM_LC_QUAL_TAB8__W 5 -#define QAM_LC_QUAL_TAB9_VALUE__B 0 -#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 -#define QAM_LC_QUAL_TAB9_VALUE__W 5 -#define QAM_LC_QUAL_TAB9__A 0x1450020 -#define QAM_LC_QUAL_TAB9__M 0x1F -#define QAM_LC_QUAL_TAB9__PRE 0x9 -#define QAM_LC_QUAL_TAB9__W 5 -#define QAM_LC_RATE_LIMIT__A 0x145002A -#define QAM_LC_SYMBOL_FREQ__A 0x145002B -#define QAM_SL_ERR_POWER__A 0x1430017 -#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 -#define QAM_SY_SP_INV__A 0x1470017 -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_TIMEOUT__A 0x1470011 -#define QAM_SY_TIMEOUT__PRE 0x3A98 -#define QAM_TOP_ANNEX_A 0x0 -#define QAM_TOP_ANNEX_C 0x2 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_HOLD 0x2 -#define SCU_COMM_EXEC_HOLD 0x2 -#define SCU_COMM_EXEC_HOLD 0x2 -#define SCU_COMM_EXEC_HOLD 0x2 -#define SCU_COMM_EXEC_STOP 0x0 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 -#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 -#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 -#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 -#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 -#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 -#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F -#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E -#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D -#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 -#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 -#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 -#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 -#define SCU_RAM_AGC_CONFIG__A 0x831F24 -#define SCU_RAM_AGC_CONFIG__A 0x831F24 -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA -#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 -#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 -#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 -#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F -#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F -#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E -#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E -#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D -#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 -#define SCU_RAM_AGC_KI_IF__B 8 -#define SCU_RAM_AGC_KI_IF__M 0xF00 -#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 -#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 -#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A -#define SCU_RAM_AGC_KI_MAX__A 0x831F2C -#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 -#define SCU_RAM_AGC_KI_MIN__A 0x831F2B -#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 -#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 -#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 -#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC -#define SCU_RAM_AGC_KI_RED__A 0x831F26 -#define SCU_RAM_AGC_KI_RED__A 0x831F26 -#define SCU_RAM_AGC_KI_RF__B 4 -#define SCU_RAM_AGC_KI_RF__M 0xF0 -#define SCU_RAM_AGC_KI__A 0x831F25 -#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 -#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 -#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 -#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 -#define SCU_RAM_AGC_RF_MAX__A 0x831F1B -#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 -#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A -#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 -#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 -#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B -#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 -#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A -#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 -#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 -#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 -#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 -#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 -#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 -#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 -#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 -#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 -#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 -#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 -#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 -#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 -#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 -#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 -#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 -#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 -#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -#define SCU_RAM_COMMAND__A 0x831FFD -#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF -#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB -#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC -#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 -#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD -#define SCU_RAM_PARAM_0_RESULT_OK 0x0 -#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC -#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF -#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE -#define SCU_RAM_PARAM_0__A 0x831FFC -#define SCU_RAM_PARAM_0__M 0xFFFF -#define SCU_RAM_PARAM_0__PRE 0x0 -#define SCU_RAM_PARAM_0__W 16 -#define SCU_RAM_PARAM_10__A 0x831FF2 -#define SCU_RAM_PARAM_10__M 0xFFFF -#define SCU_RAM_PARAM_10__PRE 0x0 -#define SCU_RAM_PARAM_10__W 16 -#define SCU_RAM_PARAM_11__A 0x831FF1 -#define SCU_RAM_PARAM_11__M 0xFFFF -#define SCU_RAM_PARAM_11__PRE 0x0 -#define SCU_RAM_PARAM_11__W 16 -#define SCU_RAM_PARAM_12__A 0x831FF0 -#define SCU_RAM_PARAM_12__M 0xFFFF -#define SCU_RAM_PARAM_12__PRE 0x0 -#define SCU_RAM_PARAM_12__W 16 -#define SCU_RAM_PARAM_13__A 0x831FEF -#define SCU_RAM_PARAM_13__M 0xFFFF -#define SCU_RAM_PARAM_13__PRE 0x0 -#define SCU_RAM_PARAM_13__W 16 -#define SCU_RAM_PARAM_14__A 0x831FEE -#define SCU_RAM_PARAM_14__M 0xFFFF -#define SCU_RAM_PARAM_14__PRE 0x0 -#define SCU_RAM_PARAM_14__W 16 -#define SCU_RAM_PARAM_15__A 0x831FED -#define SCU_RAM_PARAM_15__M 0xFFFF -#define SCU_RAM_PARAM_15__PRE 0x0 -#define SCU_RAM_PARAM_15__W 16 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 -#define SCU_RAM_PARAM_1__A 0x831FFB -#define SCU_RAM_PARAM_1__M 0xFFFF -#define SCU_RAM_PARAM_1__PRE 0x0 -#define SCU_RAM_PARAM_1__W 16 -#define SCU_RAM_PARAM_2__A 0x831FFA -#define SCU_RAM_PARAM_2__M 0xFFFF -#define SCU_RAM_PARAM_2__PRE 0x0 -#define SCU_RAM_PARAM_2__W 16 -#define SCU_RAM_PARAM_3__A 0x831FF9 -#define SCU_RAM_PARAM_3__M 0xFFFF -#define SCU_RAM_PARAM_3__PRE 0x0 -#define SCU_RAM_PARAM_3__W 16 -#define SCU_RAM_PARAM_4__A 0x831FF8 -#define SCU_RAM_PARAM_4__M 0xFFFF -#define SCU_RAM_PARAM_4__PRE 0x0 -#define SCU_RAM_PARAM_4__W 16 -#define SCU_RAM_PARAM_5__A 0x831FF7 -#define SCU_RAM_PARAM_5__M 0xFFFF -#define SCU_RAM_PARAM_5__PRE 0x0 -#define SCU_RAM_PARAM_5__W 16 -#define SCU_RAM_PARAM_6__A 0x831FF6 -#define SCU_RAM_PARAM_6__M 0xFFFF -#define SCU_RAM_PARAM_6__PRE 0x0 -#define SCU_RAM_PARAM_6__W 16 -#define SCU_RAM_PARAM_7__A 0x831FF5 -#define SCU_RAM_PARAM_7__M 0xFFFF -#define SCU_RAM_PARAM_7__PRE 0x0 -#define SCU_RAM_PARAM_7__W 16 -#define SCU_RAM_PARAM_8__A 0x831FF4 -#define SCU_RAM_PARAM_8__M 0xFFFF -#define SCU_RAM_PARAM_8__PRE 0x0 -#define SCU_RAM_PARAM_8__W 16 -#define SCU_RAM_PARAM_9__A 0x831FF3 -#define SCU_RAM_PARAM_9__M 0xFFFF -#define SCU_RAM_PARAM_9__PRE 0x0 -#define SCU_RAM_PARAM_9__W 16 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 -#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 -#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SIO_BL_CHAIN_ADDR__A 0x480018 -#define SIO_BL_CHAIN_LEN__A 0x480019 -#define SIO_BL_COMM_EXEC_ACTIVE 0x1 -#define SIO_BL_COMM_EXEC__A 0x480000 -#define SIO_BL_ENABLE_ON 0x1 -#define SIO_BL_ENABLE_ON 0x1 -#define SIO_BL_ENABLE__A 0x480012 -#define SIO_BL_ENABLE__A 0x480012 -#define SIO_BL_MODE_CHAIN 0x1 -#define SIO_BL_MODE_DIRECT 0x0 -#define SIO_BL_MODE__A 0x480011 -#define SIO_BL_MODE__A 0x480011 -#define SIO_BL_SRC_ADDR__A 0x480016 -#define SIO_BL_SRC_LEN__A 0x480017 -#define SIO_BL_STATUS__A 0x480010 -#define SIO_BL_STATUS__A 0x480010 -#define SIO_BL_TGT_ADDR__A 0x480015 -#define SIO_BL_TGT_HDR__A 0x480014 -#define SIO_CC_PLL_LOCK__A 0x450012 -#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 -#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 -#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 -#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 -#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 -#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 -#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 -#define SIO_CC_PWD_MODE__A 0x450015 -#define SIO_CC_PWD_MODE__A 0x450015 -#define SIO_CC_PWD_MODE__A 0x450015 -#define SIO_CC_SOFT_RST_OFDM__M 0x1 -#define SIO_CC_SOFT_RST_OSC__M 0x4 -#define SIO_CC_SOFT_RST_SYS__M 0x2 -#define SIO_CC_SOFT_RST__A 0x450016 -#define SIO_CC_UPDATE_KEY 0xFABA -#define SIO_CC_UPDATE_KEY 0xFABA -#define SIO_CC_UPDATE_KEY 0xFABA -#define SIO_CC_UPDATE_KEY 0xFABA -#define SIO_CC_UPDATE__A 0x450017 -#define SIO_CC_UPDATE__A 0x450017 -#define SIO_CC_UPDATE__A 0x450017 -#define SIO_CC_UPDATE__A 0x450017 -#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 -#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 -#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 -#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 -#define SIO_HI_RA_RAM_CMD_RESET 0x2 -#define SIO_HI_RA_RAM_CMD__A 0x420032 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_RES__A 0x420031 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 -#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 -#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 -#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 -#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 -#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 -#define SIO_PDR_MCLK_CFG_DRIVE__B 3 -#define SIO_PDR_MCLK_CFG__A 0x7F0028 -#define SIO_PDR_MD0_CFG_DRIVE__B 3 -#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD0_CFG_DRIVE__W 3 -#define SIO_PDR_MD0_CFG_KEEP__B 6 -#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD0_CFG_KEEP__W 2 -#define SIO_PDR_MD0_CFG_MODE__B 0 -#define SIO_PDR_MD0_CFG_MODE__M 0x7 -#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD0_CFG_MODE__W 3 -#define SIO_PDR_MD0_CFG_UIO__B 8 -#define SIO_PDR_MD0_CFG_UIO__M 0x100 -#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD0_CFG_UIO__W 1 -#define SIO_PDR_MD0_CFG__A 0x7F002A -#define SIO_PDR_MD0_CFG__M 0x1FF -#define SIO_PDR_MD0_CFG__PRE 0x50 -#define SIO_PDR_MD0_CFG__W 9 -#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 -#define SIO_PDR_MD0_GPIO_FNC__M 0x3 -#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD0_GPIO_FNC__W 2 -#define SIO_PDR_MD1_CFG_DRIVE__B 3 -#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD1_CFG_DRIVE__W 3 -#define SIO_PDR_MD1_CFG_KEEP__B 6 -#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD1_CFG_KEEP__W 2 -#define SIO_PDR_MD1_CFG_MODE__B 0 -#define SIO_PDR_MD1_CFG_MODE__M 0x7 -#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD1_CFG_MODE__W 3 -#define SIO_PDR_MD1_CFG_UIO__B 8 -#define SIO_PDR_MD1_CFG_UIO__M 0x100 -#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD1_CFG_UIO__W 1 -#define SIO_PDR_MD1_CFG__A 0x7F002B -#define SIO_PDR_MD1_CFG__M 0x1FF -#define SIO_PDR_MD1_CFG__PRE 0x50 -#define SIO_PDR_MD1_CFG__W 9 -#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 -#define SIO_PDR_MD1_GPIO_FNC__M 0x3 -#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD1_GPIO_FNC__W 2 -#define SIO_PDR_MD2_CFG_DRIVE__B 3 -#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD2_CFG_DRIVE__W 3 -#define SIO_PDR_MD2_CFG_KEEP__B 6 -#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD2_CFG_KEEP__W 2 -#define SIO_PDR_MD2_CFG_MODE__B 0 -#define SIO_PDR_MD2_CFG_MODE__M 0x7 -#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD2_CFG_MODE__W 3 -#define SIO_PDR_MD2_CFG_UIO__B 8 -#define SIO_PDR_MD2_CFG_UIO__M 0x100 -#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD2_CFG_UIO__W 1 -#define SIO_PDR_MD2_CFG__A 0x7F002C -#define SIO_PDR_MD2_CFG__M 0x1FF -#define SIO_PDR_MD2_CFG__PRE 0x50 -#define SIO_PDR_MD2_CFG__W 9 -#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 -#define SIO_PDR_MD2_GPIO_FNC__M 0x3 -#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD2_GPIO_FNC__W 2 -#define SIO_PDR_MD3_CFG_DRIVE__B 3 -#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD3_CFG_DRIVE__W 3 -#define SIO_PDR_MD3_CFG_KEEP__B 6 -#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD3_CFG_KEEP__W 2 -#define SIO_PDR_MD3_CFG_MODE__B 0 -#define SIO_PDR_MD3_CFG_MODE__M 0x7 -#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD3_CFG_MODE__W 3 -#define SIO_PDR_MD3_CFG_UIO__B 8 -#define SIO_PDR_MD3_CFG_UIO__M 0x100 -#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD3_CFG_UIO__W 1 -#define SIO_PDR_MD3_CFG__A 0x7F002D -#define SIO_PDR_MD3_CFG__M 0x1FF -#define SIO_PDR_MD3_CFG__PRE 0x50 -#define SIO_PDR_MD3_CFG__W 9 -#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 -#define SIO_PDR_MD3_GPIO_FNC__M 0x3 -#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD3_GPIO_FNC__W 2 -#define SIO_PDR_MD4_CFG_DRIVE__B 3 -#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD4_CFG_DRIVE__W 3 -#define SIO_PDR_MD4_CFG_KEEP__B 6 -#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD4_CFG_KEEP__W 2 -#define SIO_PDR_MD4_CFG_MODE__B 0 -#define SIO_PDR_MD4_CFG_MODE__M 0x7 -#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD4_CFG_MODE__W 3 -#define SIO_PDR_MD4_CFG_UIO__B 8 -#define SIO_PDR_MD4_CFG_UIO__M 0x100 -#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD4_CFG_UIO__W 1 -#define SIO_PDR_MD4_CFG__A 0x7F002F -#define SIO_PDR_MD4_CFG__M 0x1FF -#define SIO_PDR_MD4_CFG__PRE 0x50 -#define SIO_PDR_MD4_CFG__W 9 -#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A -#define SIO_PDR_MD4_GPIO_FNC__M 0x3 -#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD4_GPIO_FNC__W 2 -#define SIO_PDR_MD5_CFG_DRIVE__B 3 -#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD5_CFG_DRIVE__W 3 -#define SIO_PDR_MD5_CFG_KEEP__B 6 -#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD5_CFG_KEEP__W 2 -#define SIO_PDR_MD5_CFG_MODE__B 0 -#define SIO_PDR_MD5_CFG_MODE__M 0x7 -#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD5_CFG_MODE__W 3 -#define SIO_PDR_MD5_CFG_UIO__B 8 -#define SIO_PDR_MD5_CFG_UIO__M 0x100 -#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD5_CFG_UIO__W 1 -#define SIO_PDR_MD5_CFG__A 0x7F0030 -#define SIO_PDR_MD5_CFG__M 0x1FF -#define SIO_PDR_MD5_CFG__PRE 0x50 -#define SIO_PDR_MD5_CFG__W 9 -#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B -#define SIO_PDR_MD5_GPIO_FNC__M 0x3 -#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD5_GPIO_FNC__W 2 -#define SIO_PDR_MD6_CFG_DRIVE__B 3 -#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD6_CFG_DRIVE__W 3 -#define SIO_PDR_MD6_CFG_KEEP__B 6 -#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD6_CFG_KEEP__W 2 -#define SIO_PDR_MD6_CFG_MODE__B 0 -#define SIO_PDR_MD6_CFG_MODE__M 0x7 -#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD6_CFG_MODE__W 3 -#define SIO_PDR_MD6_CFG_UIO__B 8 -#define SIO_PDR_MD6_CFG_UIO__M 0x100 -#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD6_CFG_UIO__W 1 -#define SIO_PDR_MD6_CFG__A 0x7F0031 -#define SIO_PDR_MD6_CFG__M 0x1FF -#define SIO_PDR_MD6_CFG__PRE 0x50 -#define SIO_PDR_MD6_CFG__W 9 -#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C -#define SIO_PDR_MD6_GPIO_FNC__M 0x3 -#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD6_GPIO_FNC__W 2 -#define SIO_PDR_MD7_CFG_DRIVE__B 3 -#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD7_CFG_DRIVE__W 3 -#define SIO_PDR_MD7_CFG_KEEP__B 6 -#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD7_CFG_KEEP__W 2 -#define SIO_PDR_MD7_CFG_MODE__B 0 -#define SIO_PDR_MD7_CFG_MODE__M 0x7 -#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD7_CFG_MODE__W 3 -#define SIO_PDR_MD7_CFG_UIO__B 8 -#define SIO_PDR_MD7_CFG_UIO__M 0x100 -#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD7_CFG_UIO__W 1 -#define SIO_PDR_MD7_CFG__A 0x7F0032 -#define SIO_PDR_MD7_CFG__M 0x1FF -#define SIO_PDR_MD7_CFG__PRE 0x50 -#define SIO_PDR_MD7_CFG__W 9 -#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D -#define SIO_PDR_MD7_GPIO_FNC__M 0x3 -#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD7_GPIO_FNC__W 2 -#define SIO_PDR_MERR_CFG__A 0x7F0026 -#define SIO_PDR_MON_CFG__A 0x7F0010 -#define SIO_PDR_MSTRT_CFG__A 0x7F0025 -#define SIO_PDR_MVAL_CFG__A 0x7F0029 -#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 -#define SIO_PDR_OHW_CFG__A 0x7F001F -#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 -#define SIO_PDR_UIO_IN_HI__A 0x7F0015 -#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 -#define SIO_TOP_COMM_KEY_KEY 0xFABA -#define SIO_TOP_COMM_KEY_KEY 0xFABA -#define SIO_TOP_COMM_KEY__A 0x41000F -#define SIO_TOP_COMM_KEY__A 0x41000F -#define SIO_TOP_COMM_KEY__A 0x41000F -#define SIO_TOP_COMM_KEY__A 0x41000F -#define SIO_TOP_JTAGID_LO__A 0x410012 -#define SIO_TOP_JTAGID_LO__A 0x410012 +#define AUD_COMM_EXEC_STOP 0x0 +#define AUD_COMM_EXEC__A 0x1000000 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_STOP 0x0 +#define FEC_COMM_EXEC__A 0x1C00000 +#define FEC_COMM_EXEC__A 0x1C00000 +#define FEC_COMM_EXEC__A 0x1C00000 +#define FEC_DI_COMM_EXEC_STOP 0x0 +#define FEC_DI_COMM_EXEC__A 0x1C20000 +#define FEC_DI_INPUT_CTL__A 0x1C20016 +#define FEC_OC_AVR_PARM_A__A 0x1C40026 +#define FEC_OC_AVR_PARM_B__A 0x1C40027 +#define FEC_OC_COMM_MB_CTL_ON 0x1 +#define FEC_OC_COMM_MB__A 0x1C40002 +#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 +#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 +#define FEC_OC_DTO_MODE__A 0x1C40014 +#define FEC_OC_DTO_PERIOD__A 0x1C40015 +#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 +#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 +#define FEC_OC_FCT_MODE__A 0x1C4001A +#define FEC_OC_FCT_MODE__PRE 0x0 +#define FEC_OC_IPR_INVERT_MCLK__M 0x800 +#define FEC_OC_IPR_INVERT_MD0__B 0 +#define FEC_OC_IPR_INVERT_MD0__M 0x1 +#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD0__W 1 +#define FEC_OC_IPR_INVERT_MD1__B 1 +#define FEC_OC_IPR_INVERT_MD1__M 0x2 +#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD1__W 1 +#define FEC_OC_IPR_INVERT_MD2__B 2 +#define FEC_OC_IPR_INVERT_MD2__M 0x4 +#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD2__W 1 +#define FEC_OC_IPR_INVERT_MD3__B 3 +#define FEC_OC_IPR_INVERT_MD3__M 0x8 +#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD3__W 1 +#define FEC_OC_IPR_INVERT_MD4__B 4 +#define FEC_OC_IPR_INVERT_MD4__M 0x10 +#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD4__W 1 +#define FEC_OC_IPR_INVERT_MD5__B 5 +#define FEC_OC_IPR_INVERT_MD5__M 0x20 +#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD5__W 1 +#define FEC_OC_IPR_INVERT_MD6__B 6 +#define FEC_OC_IPR_INVERT_MD6__M 0x40 +#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD6__W 1 +#define FEC_OC_IPR_INVERT_MD7__B 7 +#define FEC_OC_IPR_INVERT_MD7__M 0x80 +#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD7__W 1 +#define FEC_OC_IPR_INVERT_MERR__M 0x100 +#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 +#define FEC_OC_IPR_INVERT_MVAL__M 0x400 +#define FEC_OC_IPR_INVERT__A 0x1C40049 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 +#define FEC_OC_IPR_MODE_SERIAL__M 0x1 +#define FEC_OC_IPR_MODE__A 0x1C40048 +#define FEC_OC_IPR_MODE__A 0x1C40048 +#define FEC_OC_MODE_PARITY__M 0x1 +#define FEC_OC_MODE__A 0x1C40011 +#define FEC_OC_OCR_INVERT__A 0x1C40052 +#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 +#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 +#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 +#define FEC_OC_RCN_GAIN__A 0x1C4002E +#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 +#define FEC_OC_SNC_HWM__A 0x1C40042 +#define FEC_OC_SNC_LWM__A 0x1C40041 +#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 +#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 +#define FEC_OC_SNC_MODE__A 0x1C40040 +#define FEC_OC_SNC_MODE__A 0x1C40040 +#define FEC_OC_SNC_UNLOCK__A 0x1C40043 +#define FEC_OC_TMD_COUNT__A 0x1C4001F +#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 +#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 +#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 +#define FEC_OC_TMD_MODE__A 0x1C4001E +#define FEC_RS_COMM_EXEC_STOP 0x0 +#define FEC_RS_COMM_EXEC__A 0x1C30000 +#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 +#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 +#define IQM_AF_AGC_IF__A 0x1870028 +#define IQM_AF_AGC_RF__A 0x1870029 +#define IQM_AF_AMUX_SIGNAL2ADC 0x1 +#define IQM_AF_AMUX_SIGNAL2ADC 0x1 +#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 +#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 +#define IQM_AF_CLKNEG__A 0x1870012 +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_COMM_EXEC_ACTIVE 0x1 +#define IQM_AF_COMM_EXEC__A 0x1870000 +#define IQM_AF_INC_BYPASS__A 0x1870036 +#define IQM_AF_INC_LCT__A 0x1870034 +#define IQM_AF_PDREF__A 0x187002B +#define IQM_AF_PDREF__M 0x1F +#define IQM_AF_PHASE0__A 0x187001C +#define IQM_AF_PHASE0__M 0x7F +#define IQM_AF_PHASE0__PRE 0x0 +#define IQM_AF_PHASE0__W 7 +#define IQM_AF_PHASE1__A 0x187001D +#define IQM_AF_PHASE1__M 0x7F +#define IQM_AF_PHASE1__PRE 0x0 +#define IQM_AF_PHASE1__W 7 +#define IQM_AF_PHASE2__A 0x187001E +#define IQM_AF_PHASE2__M 0x7F +#define IQM_AF_PHASE2__PRE 0x0 +#define IQM_AF_PHASE2__W 7 +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 +#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 +#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 +#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_UPD_SEL__A 0x187002F +#define IQM_AF_UPD_SEL__A 0x187002F +#define IQM_CF_ADJ_SEL__A 0x1860013 +#define IQM_CF_BYPASSDET__A 0x1860067 +#define IQM_CF_BYPASSDET__A 0x1860067 +#define IQM_CF_CLP_VAL__A 0x1860060 +#define IQM_CF_COMM_INT_MSK__A 0x1860006 +#define IQM_CF_DATATH__A 0x1860061 +#define IQM_CF_DATATH__A 0x1860061 +#define IQM_CF_DET_LCT__A 0x1860064 +#define IQM_CF_DET_LCT__A 0x1860064 +#define IQM_CF_DS_ENA__A 0x1860019 +#define IQM_CF_MIDTAP_IM__B 1 +#define IQM_CF_MIDTAP_RE__B 0 +#define IQM_CF_MIDTAP__A 0x1860011 +#define IQM_CF_OUT_ENA_QAM__B 1 +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_PKDTH__A 0x1860062 +#define IQM_CF_PKDTH__A 0x1860062 +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__PRE 0x0 +#define IQM_CF_SCALE__A 0x1860014 +#define IQM_CF_SYMMETRIC__A 0x1860010 +#define IQM_CF_TAP_IM0_B__B 0 +#define IQM_CF_TAP_IM0_B__M 0x7F +#define IQM_CF_TAP_IM0_B__PRE 0x2 +#define IQM_CF_TAP_IM0_B__W 7 +#define IQM_CF_TAP_IM0__A 0x1860040 +#define IQM_CF_TAP_IM0__M 0x7F +#define IQM_CF_TAP_IM0__PRE 0x2 +#define IQM_CF_TAP_IM0__W 7 +#define IQM_CF_TAP_IM10_B__B 0 +#define IQM_CF_TAP_IM10_B__M 0x1FF +#define IQM_CF_TAP_IM10_B__PRE 0x2 +#define IQM_CF_TAP_IM10_B__W 9 +#define IQM_CF_TAP_IM10__A 0x186004A +#define IQM_CF_TAP_IM10__M 0x1FF +#define IQM_CF_TAP_IM10__PRE 0x2 +#define IQM_CF_TAP_IM10__W 9 +#define IQM_CF_TAP_IM11_B__B 0 +#define IQM_CF_TAP_IM11_B__M 0x1FF +#define IQM_CF_TAP_IM11_B__PRE 0x2 +#define IQM_CF_TAP_IM11_B__W 9 +#define IQM_CF_TAP_IM11__A 0x186004B +#define IQM_CF_TAP_IM11__M 0x1FF +#define IQM_CF_TAP_IM11__PRE 0x2 +#define IQM_CF_TAP_IM11__W 9 +#define IQM_CF_TAP_IM12_B__B 0 +#define IQM_CF_TAP_IM12_B__M 0x1FF +#define IQM_CF_TAP_IM12_B__PRE 0x2 +#define IQM_CF_TAP_IM12_B__W 9 +#define IQM_CF_TAP_IM12__A 0x186004C +#define IQM_CF_TAP_IM12__M 0x1FF +#define IQM_CF_TAP_IM12__PRE 0x2 +#define IQM_CF_TAP_IM12__W 9 +#define IQM_CF_TAP_IM13_B__B 0 +#define IQM_CF_TAP_IM13_B__M 0x1FF +#define IQM_CF_TAP_IM13_B__PRE 0x2 +#define IQM_CF_TAP_IM13_B__W 9 +#define IQM_CF_TAP_IM13__A 0x186004D +#define IQM_CF_TAP_IM13__M 0x1FF +#define IQM_CF_TAP_IM13__PRE 0x2 +#define IQM_CF_TAP_IM13__W 9 +#define IQM_CF_TAP_IM14_B__B 0 +#define IQM_CF_TAP_IM14_B__M 0x1FF +#define IQM_CF_TAP_IM14_B__PRE 0x2 +#define IQM_CF_TAP_IM14_B__W 9 +#define IQM_CF_TAP_IM14__A 0x186004E +#define IQM_CF_TAP_IM14__M 0x1FF +#define IQM_CF_TAP_IM14__PRE 0x2 +#define IQM_CF_TAP_IM14__W 9 +#define IQM_CF_TAP_IM15_B__B 0 +#define IQM_CF_TAP_IM15_B__M 0x1FF +#define IQM_CF_TAP_IM15_B__PRE 0x2 +#define IQM_CF_TAP_IM15_B__W 9 +#define IQM_CF_TAP_IM15__A 0x186004F +#define IQM_CF_TAP_IM15__M 0x1FF +#define IQM_CF_TAP_IM15__PRE 0x2 +#define IQM_CF_TAP_IM15__W 9 +#define IQM_CF_TAP_IM16_B__B 0 +#define IQM_CF_TAP_IM16_B__M 0x1FF +#define IQM_CF_TAP_IM16_B__PRE 0x2 +#define IQM_CF_TAP_IM16_B__W 9 +#define IQM_CF_TAP_IM16__A 0x1860050 +#define IQM_CF_TAP_IM16__M 0x1FF +#define IQM_CF_TAP_IM16__PRE 0x2 +#define IQM_CF_TAP_IM16__W 9 +#define IQM_CF_TAP_IM17_B__B 0 +#define IQM_CF_TAP_IM17_B__M 0x1FF +#define IQM_CF_TAP_IM17_B__PRE 0x2 +#define IQM_CF_TAP_IM17_B__W 9 +#define IQM_CF_TAP_IM17__A 0x1860051 +#define IQM_CF_TAP_IM17__M 0x1FF +#define IQM_CF_TAP_IM17__PRE 0x2 +#define IQM_CF_TAP_IM17__W 9 +#define IQM_CF_TAP_IM18_B__B 0 +#define IQM_CF_TAP_IM18_B__M 0x1FF +#define IQM_CF_TAP_IM18_B__PRE 0x2 +#define IQM_CF_TAP_IM18_B__W 9 +#define IQM_CF_TAP_IM18__A 0x1860052 +#define IQM_CF_TAP_IM18__M 0x1FF +#define IQM_CF_TAP_IM18__PRE 0x2 +#define IQM_CF_TAP_IM18__W 9 +#define IQM_CF_TAP_IM19_B__B 0 +#define IQM_CF_TAP_IM19_B__M 0x1FF +#define IQM_CF_TAP_IM19_B__PRE 0x2 +#define IQM_CF_TAP_IM19_B__W 9 +#define IQM_CF_TAP_IM19__A 0x1860053 +#define IQM_CF_TAP_IM19__M 0x1FF +#define IQM_CF_TAP_IM19__PRE 0x2 +#define IQM_CF_TAP_IM19__W 9 +#define IQM_CF_TAP_IM1_B__B 0 +#define IQM_CF_TAP_IM1_B__M 0x7F +#define IQM_CF_TAP_IM1_B__PRE 0x2 +#define IQM_CF_TAP_IM1_B__W 7 +#define IQM_CF_TAP_IM1__A 0x1860041 +#define IQM_CF_TAP_IM1__M 0x7F +#define IQM_CF_TAP_IM1__PRE 0x2 +#define IQM_CF_TAP_IM1__W 7 +#define IQM_CF_TAP_IM20_B__B 0 +#define IQM_CF_TAP_IM20_B__M 0x1FF +#define IQM_CF_TAP_IM20_B__PRE 0x2 +#define IQM_CF_TAP_IM20_B__W 9 +#define IQM_CF_TAP_IM20__A 0x1860054 +#define IQM_CF_TAP_IM20__M 0x1FF +#define IQM_CF_TAP_IM20__PRE 0x2 +#define IQM_CF_TAP_IM20__W 9 +#define IQM_CF_TAP_IM21_B__B 0 +#define IQM_CF_TAP_IM21_B__M 0x7FF +#define IQM_CF_TAP_IM21_B__PRE 0x2 +#define IQM_CF_TAP_IM21_B__W 11 +#define IQM_CF_TAP_IM21__A 0x1860055 +#define IQM_CF_TAP_IM21__M 0x7FF +#define IQM_CF_TAP_IM21__PRE 0x2 +#define IQM_CF_TAP_IM21__W 11 +#define IQM_CF_TAP_IM22_B__B 0 +#define IQM_CF_TAP_IM22_B__M 0x7FF +#define IQM_CF_TAP_IM22_B__PRE 0x2 +#define IQM_CF_TAP_IM22_B__W 11 +#define IQM_CF_TAP_IM22__A 0x1860056 +#define IQM_CF_TAP_IM22__M 0x7FF +#define IQM_CF_TAP_IM22__PRE 0x2 +#define IQM_CF_TAP_IM22__W 11 +#define IQM_CF_TAP_IM23_B__B 0 +#define IQM_CF_TAP_IM23_B__M 0x7FF +#define IQM_CF_TAP_IM23_B__PRE 0x2 +#define IQM_CF_TAP_IM23_B__W 11 +#define IQM_CF_TAP_IM23__A 0x1860057 +#define IQM_CF_TAP_IM23__M 0x7FF +#define IQM_CF_TAP_IM23__PRE 0x2 +#define IQM_CF_TAP_IM23__W 11 +#define IQM_CF_TAP_IM24_B__B 0 +#define IQM_CF_TAP_IM24_B__M 0x7FF +#define IQM_CF_TAP_IM24_B__PRE 0x2 +#define IQM_CF_TAP_IM24_B__W 11 +#define IQM_CF_TAP_IM24__A 0x1860058 +#define IQM_CF_TAP_IM24__M 0x7FF +#define IQM_CF_TAP_IM24__PRE 0x2 +#define IQM_CF_TAP_IM24__W 11 +#define IQM_CF_TAP_IM25_B__B 0 +#define IQM_CF_TAP_IM25_B__M 0x7FF +#define IQM_CF_TAP_IM25_B__PRE 0x2 +#define IQM_CF_TAP_IM25_B__W 11 +#define IQM_CF_TAP_IM25__A 0x1860059 +#define IQM_CF_TAP_IM25__M 0x7FF +#define IQM_CF_TAP_IM25__PRE 0x2 +#define IQM_CF_TAP_IM25__W 11 +#define IQM_CF_TAP_IM26_B__B 0 +#define IQM_CF_TAP_IM26_B__M 0x7FF +#define IQM_CF_TAP_IM26_B__PRE 0x2 +#define IQM_CF_TAP_IM26_B__W 11 +#define IQM_CF_TAP_IM26__A 0x186005A +#define IQM_CF_TAP_IM26__M 0x7FF +#define IQM_CF_TAP_IM26__PRE 0x2 +#define IQM_CF_TAP_IM26__W 11 +#define IQM_CF_TAP_IM27_B__B 0 +#define IQM_CF_TAP_IM27_B__M 0x7FF +#define IQM_CF_TAP_IM27_B__PRE 0x2 +#define IQM_CF_TAP_IM27_B__W 11 +#define IQM_CF_TAP_IM27__A 0x186005B +#define IQM_CF_TAP_IM27__M 0x7FF +#define IQM_CF_TAP_IM27__PRE 0x2 +#define IQM_CF_TAP_IM27__W 11 +#define IQM_CF_TAP_IM2_B__B 0 +#define IQM_CF_TAP_IM2_B__M 0x7F +#define IQM_CF_TAP_IM2_B__PRE 0x2 +#define IQM_CF_TAP_IM2_B__W 7 +#define IQM_CF_TAP_IM2__A 0x1860042 +#define IQM_CF_TAP_IM2__M 0x7F +#define IQM_CF_TAP_IM2__PRE 0x2 +#define IQM_CF_TAP_IM2__W 7 +#define IQM_CF_TAP_IM3_B__B 0 +#define IQM_CF_TAP_IM3_B__M 0x7F +#define IQM_CF_TAP_IM3_B__PRE 0x2 +#define IQM_CF_TAP_IM3_B__W 7 +#define IQM_CF_TAP_IM3__A 0x1860043 +#define IQM_CF_TAP_IM3__M 0x7F +#define IQM_CF_TAP_IM3__PRE 0x2 +#define IQM_CF_TAP_IM3__W 7 +#define IQM_CF_TAP_IM4_B__B 0 +#define IQM_CF_TAP_IM4_B__M 0x7F +#define IQM_CF_TAP_IM4_B__PRE 0x2 +#define IQM_CF_TAP_IM4_B__W 7 +#define IQM_CF_TAP_IM4__A 0x1860044 +#define IQM_CF_TAP_IM4__M 0x7F +#define IQM_CF_TAP_IM4__PRE 0x2 +#define IQM_CF_TAP_IM4__W 7 +#define IQM_CF_TAP_IM5_B__B 0 +#define IQM_CF_TAP_IM5_B__M 0x7F +#define IQM_CF_TAP_IM5_B__PRE 0x2 +#define IQM_CF_TAP_IM5_B__W 7 +#define IQM_CF_TAP_IM5__A 0x1860045 +#define IQM_CF_TAP_IM5__M 0x7F +#define IQM_CF_TAP_IM5__PRE 0x2 +#define IQM_CF_TAP_IM5__W 7 +#define IQM_CF_TAP_IM6_B__B 0 +#define IQM_CF_TAP_IM6_B__M 0x7F +#define IQM_CF_TAP_IM6_B__PRE 0x2 +#define IQM_CF_TAP_IM6_B__W 7 +#define IQM_CF_TAP_IM6__A 0x1860046 +#define IQM_CF_TAP_IM6__M 0x7F +#define IQM_CF_TAP_IM6__PRE 0x2 +#define IQM_CF_TAP_IM6__W 7 +#define IQM_CF_TAP_IM7_B__B 0 +#define IQM_CF_TAP_IM7_B__M 0x1FF +#define IQM_CF_TAP_IM7_B__PRE 0x2 +#define IQM_CF_TAP_IM7_B__W 9 +#define IQM_CF_TAP_IM7__A 0x1860047 +#define IQM_CF_TAP_IM7__M 0x1FF +#define IQM_CF_TAP_IM7__PRE 0x2 +#define IQM_CF_TAP_IM7__W 9 +#define IQM_CF_TAP_IM8_B__B 0 +#define IQM_CF_TAP_IM8_B__M 0x1FF +#define IQM_CF_TAP_IM8_B__PRE 0x2 +#define IQM_CF_TAP_IM8_B__W 9 +#define IQM_CF_TAP_IM8__A 0x1860048 +#define IQM_CF_TAP_IM8__M 0x1FF +#define IQM_CF_TAP_IM8__PRE 0x2 +#define IQM_CF_TAP_IM8__W 9 +#define IQM_CF_TAP_IM9_B__B 0 +#define IQM_CF_TAP_IM9_B__M 0x1FF +#define IQM_CF_TAP_IM9_B__PRE 0x2 +#define IQM_CF_TAP_IM9_B__W 9 +#define IQM_CF_TAP_IM9__A 0x1860049 +#define IQM_CF_TAP_IM9__M 0x1FF +#define IQM_CF_TAP_IM9__PRE 0x2 +#define IQM_CF_TAP_IM9__W 9 +#define IQM_CF_TAP_RE0_B__B 0 +#define IQM_CF_TAP_RE0_B__M 0x7F +#define IQM_CF_TAP_RE0_B__PRE 0x2 +#define IQM_CF_TAP_RE0_B__W 7 +#define IQM_CF_TAP_RE0__A 0x1860020 +#define IQM_CF_TAP_RE0__M 0x7F +#define IQM_CF_TAP_RE0__PRE 0x2 +#define IQM_CF_TAP_RE0__W 7 +#define IQM_CF_TAP_RE10_B__B 0 +#define IQM_CF_TAP_RE10_B__M 0x1FF +#define IQM_CF_TAP_RE10_B__PRE 0x2 +#define IQM_CF_TAP_RE10_B__W 9 +#define IQM_CF_TAP_RE10__A 0x186002A +#define IQM_CF_TAP_RE10__M 0x1FF +#define IQM_CF_TAP_RE10__PRE 0x2 +#define IQM_CF_TAP_RE10__W 9 +#define IQM_CF_TAP_RE11_B__B 0 +#define IQM_CF_TAP_RE11_B__M 0x1FF +#define IQM_CF_TAP_RE11_B__PRE 0x2 +#define IQM_CF_TAP_RE11_B__W 9 +#define IQM_CF_TAP_RE11__A 0x186002B +#define IQM_CF_TAP_RE11__M 0x1FF +#define IQM_CF_TAP_RE11__PRE 0x2 +#define IQM_CF_TAP_RE11__W 9 +#define IQM_CF_TAP_RE12_B__B 0 +#define IQM_CF_TAP_RE12_B__M 0x1FF +#define IQM_CF_TAP_RE12_B__PRE 0x2 +#define IQM_CF_TAP_RE12_B__W 9 +#define IQM_CF_TAP_RE12__A 0x186002C +#define IQM_CF_TAP_RE12__M 0x1FF +#define IQM_CF_TAP_RE12__PRE 0x2 +#define IQM_CF_TAP_RE12__W 9 +#define IQM_CF_TAP_RE13_B__B 0 +#define IQM_CF_TAP_RE13_B__M 0x1FF +#define IQM_CF_TAP_RE13_B__PRE 0x2 +#define IQM_CF_TAP_RE13_B__W 9 +#define IQM_CF_TAP_RE13__A 0x186002D +#define IQM_CF_TAP_RE13__M 0x1FF +#define IQM_CF_TAP_RE13__PRE 0x2 +#define IQM_CF_TAP_RE13__W 9 +#define IQM_CF_TAP_RE14_B__B 0 +#define IQM_CF_TAP_RE14_B__M 0x1FF +#define IQM_CF_TAP_RE14_B__PRE 0x2 +#define IQM_CF_TAP_RE14_B__W 9 +#define IQM_CF_TAP_RE14__A 0x186002E +#define IQM_CF_TAP_RE14__M 0x1FF +#define IQM_CF_TAP_RE14__PRE 0x2 +#define IQM_CF_TAP_RE14__W 9 +#define IQM_CF_TAP_RE15_B__B 0 +#define IQM_CF_TAP_RE15_B__M 0x1FF +#define IQM_CF_TAP_RE15_B__PRE 0x2 +#define IQM_CF_TAP_RE15_B__W 9 +#define IQM_CF_TAP_RE15__A 0x186002F +#define IQM_CF_TAP_RE15__M 0x1FF +#define IQM_CF_TAP_RE15__PRE 0x2 +#define IQM_CF_TAP_RE15__W 9 +#define IQM_CF_TAP_RE16_B__B 0 +#define IQM_CF_TAP_RE16_B__M 0x1FF +#define IQM_CF_TAP_RE16_B__PRE 0x2 +#define IQM_CF_TAP_RE16_B__W 9 +#define IQM_CF_TAP_RE16__A 0x1860030 +#define IQM_CF_TAP_RE16__M 0x1FF +#define IQM_CF_TAP_RE16__PRE 0x2 +#define IQM_CF_TAP_RE16__W 9 +#define IQM_CF_TAP_RE17_B__B 0 +#define IQM_CF_TAP_RE17_B__M 0x1FF +#define IQM_CF_TAP_RE17_B__PRE 0x2 +#define IQM_CF_TAP_RE17_B__W 9 +#define IQM_CF_TAP_RE17__A 0x1860031 +#define IQM_CF_TAP_RE17__M 0x1FF +#define IQM_CF_TAP_RE17__PRE 0x2 +#define IQM_CF_TAP_RE17__W 9 +#define IQM_CF_TAP_RE18_B__B 0 +#define IQM_CF_TAP_RE18_B__M 0x1FF +#define IQM_CF_TAP_RE18_B__PRE 0x2 +#define IQM_CF_TAP_RE18_B__W 9 +#define IQM_CF_TAP_RE18__A 0x1860032 +#define IQM_CF_TAP_RE18__M 0x1FF +#define IQM_CF_TAP_RE18__PRE 0x2 +#define IQM_CF_TAP_RE18__W 9 +#define IQM_CF_TAP_RE19_B__B 0 +#define IQM_CF_TAP_RE19_B__M 0x1FF +#define IQM_CF_TAP_RE19_B__PRE 0x2 +#define IQM_CF_TAP_RE19_B__W 9 +#define IQM_CF_TAP_RE19__A 0x1860033 +#define IQM_CF_TAP_RE19__M 0x1FF +#define IQM_CF_TAP_RE19__PRE 0x2 +#define IQM_CF_TAP_RE19__W 9 +#define IQM_CF_TAP_RE1_B__B 0 +#define IQM_CF_TAP_RE1_B__M 0x7F +#define IQM_CF_TAP_RE1_B__PRE 0x2 +#define IQM_CF_TAP_RE1_B__W 7 +#define IQM_CF_TAP_RE1__A 0x1860021 +#define IQM_CF_TAP_RE1__M 0x7F +#define IQM_CF_TAP_RE1__PRE 0x2 +#define IQM_CF_TAP_RE1__W 7 +#define IQM_CF_TAP_RE20_B__B 0 +#define IQM_CF_TAP_RE20_B__M 0x1FF +#define IQM_CF_TAP_RE20_B__PRE 0x2 +#define IQM_CF_TAP_RE20_B__W 9 +#define IQM_CF_TAP_RE20__A 0x1860034 +#define IQM_CF_TAP_RE20__M 0x1FF +#define IQM_CF_TAP_RE20__PRE 0x2 +#define IQM_CF_TAP_RE20__W 9 +#define IQM_CF_TAP_RE21_B__B 0 +#define IQM_CF_TAP_RE21_B__M 0x7FF +#define IQM_CF_TAP_RE21_B__PRE 0x2 +#define IQM_CF_TAP_RE21_B__W 11 +#define IQM_CF_TAP_RE21__A 0x1860035 +#define IQM_CF_TAP_RE21__M 0x7FF +#define IQM_CF_TAP_RE21__PRE 0x2 +#define IQM_CF_TAP_RE21__W 11 +#define IQM_CF_TAP_RE22_B__B 0 +#define IQM_CF_TAP_RE22_B__M 0x7FF +#define IQM_CF_TAP_RE22_B__PRE 0x2 +#define IQM_CF_TAP_RE22_B__W 11 +#define IQM_CF_TAP_RE22__A 0x1860036 +#define IQM_CF_TAP_RE22__M 0x7FF +#define IQM_CF_TAP_RE22__PRE 0x2 +#define IQM_CF_TAP_RE22__W 11 +#define IQM_CF_TAP_RE23_B__B 0 +#define IQM_CF_TAP_RE23_B__M 0x7FF +#define IQM_CF_TAP_RE23_B__PRE 0x2 +#define IQM_CF_TAP_RE23_B__W 11 +#define IQM_CF_TAP_RE23__A 0x1860037 +#define IQM_CF_TAP_RE23__M 0x7FF +#define IQM_CF_TAP_RE23__PRE 0x2 +#define IQM_CF_TAP_RE23__W 11 +#define IQM_CF_TAP_RE24_B__B 0 +#define IQM_CF_TAP_RE24_B__M 0x7FF +#define IQM_CF_TAP_RE24_B__PRE 0x2 +#define IQM_CF_TAP_RE24_B__W 11 +#define IQM_CF_TAP_RE24__A 0x1860038 +#define IQM_CF_TAP_RE24__M 0x7FF +#define IQM_CF_TAP_RE24__PRE 0x2 +#define IQM_CF_TAP_RE24__W 11 +#define IQM_CF_TAP_RE25_B__B 0 +#define IQM_CF_TAP_RE25_B__M 0x7FF +#define IQM_CF_TAP_RE25_B__PRE 0x2 +#define IQM_CF_TAP_RE25_B__W 11 +#define IQM_CF_TAP_RE25__A 0x1860039 +#define IQM_CF_TAP_RE25__M 0x7FF +#define IQM_CF_TAP_RE25__PRE 0x2 +#define IQM_CF_TAP_RE25__W 11 +#define IQM_CF_TAP_RE26_B__B 0 +#define IQM_CF_TAP_RE26_B__M 0x7FF +#define IQM_CF_TAP_RE26_B__PRE 0x2 +#define IQM_CF_TAP_RE26_B__W 11 +#define IQM_CF_TAP_RE26__A 0x186003A +#define IQM_CF_TAP_RE26__M 0x7FF +#define IQM_CF_TAP_RE26__PRE 0x2 +#define IQM_CF_TAP_RE26__W 11 +#define IQM_CF_TAP_RE27_B__B 0 +#define IQM_CF_TAP_RE27_B__M 0x7FF +#define IQM_CF_TAP_RE27_B__PRE 0x2 +#define IQM_CF_TAP_RE27_B__W 11 +#define IQM_CF_TAP_RE27__A 0x186003B +#define IQM_CF_TAP_RE27__M 0x7FF +#define IQM_CF_TAP_RE27__PRE 0x2 +#define IQM_CF_TAP_RE27__W 11 +#define IQM_CF_TAP_RE2_B__B 0 +#define IQM_CF_TAP_RE2_B__M 0x7F +#define IQM_CF_TAP_RE2_B__PRE 0x2 +#define IQM_CF_TAP_RE2_B__W 7 +#define IQM_CF_TAP_RE2__A 0x1860022 +#define IQM_CF_TAP_RE2__M 0x7F +#define IQM_CF_TAP_RE2__PRE 0x2 +#define IQM_CF_TAP_RE2__W 7 +#define IQM_CF_TAP_RE3_B__B 0 +#define IQM_CF_TAP_RE3_B__M 0x7F +#define IQM_CF_TAP_RE3_B__PRE 0x2 +#define IQM_CF_TAP_RE3_B__W 7 +#define IQM_CF_TAP_RE3__A 0x1860023 +#define IQM_CF_TAP_RE3__M 0x7F +#define IQM_CF_TAP_RE3__PRE 0x2 +#define IQM_CF_TAP_RE3__W 7 +#define IQM_CF_TAP_RE4_B__B 0 +#define IQM_CF_TAP_RE4_B__M 0x7F +#define IQM_CF_TAP_RE4_B__PRE 0x2 +#define IQM_CF_TAP_RE4_B__W 7 +#define IQM_CF_TAP_RE4__A 0x1860024 +#define IQM_CF_TAP_RE4__M 0x7F +#define IQM_CF_TAP_RE4__PRE 0x2 +#define IQM_CF_TAP_RE4__W 7 +#define IQM_CF_TAP_RE5_B__B 0 +#define IQM_CF_TAP_RE5_B__M 0x7F +#define IQM_CF_TAP_RE5_B__PRE 0x2 +#define IQM_CF_TAP_RE5_B__W 7 +#define IQM_CF_TAP_RE5__A 0x1860025 +#define IQM_CF_TAP_RE5__M 0x7F +#define IQM_CF_TAP_RE5__PRE 0x2 +#define IQM_CF_TAP_RE5__W 7 +#define IQM_CF_TAP_RE6_B__B 0 +#define IQM_CF_TAP_RE6_B__M 0x7F +#define IQM_CF_TAP_RE6_B__PRE 0x2 +#define IQM_CF_TAP_RE6_B__W 7 +#define IQM_CF_TAP_RE6__A 0x1860026 +#define IQM_CF_TAP_RE6__M 0x7F +#define IQM_CF_TAP_RE6__PRE 0x2 +#define IQM_CF_TAP_RE6__W 7 +#define IQM_CF_TAP_RE7_B__B 0 +#define IQM_CF_TAP_RE7_B__M 0x1FF +#define IQM_CF_TAP_RE7_B__PRE 0x2 +#define IQM_CF_TAP_RE7_B__W 9 +#define IQM_CF_TAP_RE7__A 0x1860027 +#define IQM_CF_TAP_RE7__M 0x1FF +#define IQM_CF_TAP_RE7__PRE 0x2 +#define IQM_CF_TAP_RE7__W 9 +#define IQM_CF_TAP_RE8_B__B 0 +#define IQM_CF_TAP_RE8_B__M 0x1FF +#define IQM_CF_TAP_RE8_B__PRE 0x2 +#define IQM_CF_TAP_RE8_B__W 9 +#define IQM_CF_TAP_RE8__A 0x1860028 +#define IQM_CF_TAP_RE8__M 0x1FF +#define IQM_CF_TAP_RE8__PRE 0x2 +#define IQM_CF_TAP_RE8__W 9 +#define IQM_CF_TAP_RE9_B__B 0 +#define IQM_CF_TAP_RE9_B__M 0x1FF +#define IQM_CF_TAP_RE9_B__PRE 0x2 +#define IQM_CF_TAP_RE9_B__W 9 +#define IQM_CF_TAP_RE9__A 0x1860029 +#define IQM_CF_TAP_RE9__M 0x1FF +#define IQM_CF_TAP_RE9__PRE 0x2 +#define IQM_CF_TAP_RE9__W 9 +#define IQM_CF_WND_LEN__A 0x1860063 +#define IQM_CF_WND_LEN__A 0x1860063 +#define IQM_COMM_EXEC_B_ACTIVE 0x1 +#define IQM_COMM_EXEC_B_ACTIVE 0x1 +#define IQM_COMM_EXEC_B_STOP 0x0 +#define IQM_COMM_EXEC_B_STOP 0x0 +#define IQM_COMM_EXEC_B_STOP 0x0 +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_FD_RATESEL__A 0x1830010 +#define IQM_FS_ADJ_SEL__A 0x1820014 +#define IQM_FS_RATE_LO__A 0x1820012 +#define IQM_FS_RATE_OFS_LO__A 0x1820010 +#define IQM_RC_ADJ_SEL__A 0x1840014 +#define IQM_RC_RATE_OFS_HI__M 0xFF +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__M 0xFFFF +#define IQM_RC_RATE_OFS_LO__W 16 +#define IQM_RC_STRETCH__A 0x1840016 +#define IQM_RC_STRETCH__A 0x1840016 +#define OFDM_CP_COMM_EXEC_STOP 0x0 +#define OFDM_CP_COMM_EXEC__A 0x2800000 +#define OFDM_EC_SB_PRIOR_HI 0x0 +#define OFDM_EC_SB_PRIOR__A 0x3410013 +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 +#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 +#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 +#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 +#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 +#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 +#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 +#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 +#define OFDM_LC_COMM_EXEC_STOP 0x0 +#define OFDM_LC_COMM_EXEC_STOP 0x0 +#define OFDM_LC_COMM_EXEC_STOP 0x0 +#define OFDM_LC_COMM_EXEC__A 0x3800000 +#define OFDM_LC_COMM_EXEC__A 0x3800000 +#define OFDM_LC_COMM_EXEC__A 0x3800000 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_STATE__A 0x3C00001 +#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 +#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 +#define OFDM_SC_RA_RAM_CMD_NULL 0x0 +#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 +#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 +#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 +#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 +#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 +#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 +#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 +#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 +#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F +#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F +#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 +#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 +#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C +#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 +#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 +#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D +#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C +#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 +#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 +#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 +#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 +#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 +#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 +#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 +#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 +#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM0__W 16 +#define OFDM_SC_RA_RAM_PARAM0__W 16 +#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 +#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 +#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM1__W 16 +#define OFDM_SC_RA_RAM_PARAM1__W 16 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 +#define QAM_COMM_EXEC_ACTIVE 0x1 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__PRE 0x4 +#define QAM_DQ_QUAL_FUN0__PRE 0x4 +#define QAM_DQ_QUAL_FUN0__PRE 0x4 +#define QAM_DQ_QUAL_FUN0__PRE 0x4 +#define QAM_DQ_QUAL_FUN0__PRE 0x4 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__PRE 0x4 +#define QAM_DQ_QUAL_FUN1__PRE 0x4 +#define QAM_DQ_QUAL_FUN1__PRE 0x4 +#define QAM_DQ_QUAL_FUN1__PRE 0x4 +#define QAM_DQ_QUAL_FUN1__PRE 0x4 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__PRE 0x4 +#define QAM_DQ_QUAL_FUN2__PRE 0x4 +#define QAM_DQ_QUAL_FUN2__PRE 0x4 +#define QAM_DQ_QUAL_FUN2__PRE 0x4 +#define QAM_DQ_QUAL_FUN2__PRE 0x4 +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__PRE 0x4 +#define QAM_DQ_QUAL_FUN3__PRE 0x4 +#define QAM_DQ_QUAL_FUN3__PRE 0x4 +#define QAM_DQ_QUAL_FUN3__PRE 0x4 +#define QAM_DQ_QUAL_FUN3__PRE 0x4 +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__PRE 0x6 +#define QAM_DQ_QUAL_FUN4__PRE 0x6 +#define QAM_DQ_QUAL_FUN4__PRE 0x6 +#define QAM_DQ_QUAL_FUN4__PRE 0x6 +#define QAM_DQ_QUAL_FUN4__PRE 0x6 +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__PRE 0x6 +#define QAM_DQ_QUAL_FUN5__PRE 0x6 +#define QAM_DQ_QUAL_FUN5__PRE 0x6 +#define QAM_DQ_QUAL_FUN5__PRE 0x6 +#define QAM_DQ_QUAL_FUN5__PRE 0x6 +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_LC_LPF_FACTORI__A 0x1450029 +#define QAM_LC_LPF_FACTORP__A 0x1450028 +#define QAM_LC_MODE__A 0x1450010 +#define QAM_LC_QUAL_TAB0_VALUE__B 0 +#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 +#define QAM_LC_QUAL_TAB0_VALUE__W 5 +#define QAM_LC_QUAL_TAB0__A 0x1450018 +#define QAM_LC_QUAL_TAB0__M 0x1F +#define QAM_LC_QUAL_TAB0__PRE 0x0 +#define QAM_LC_QUAL_TAB0__W 5 +#define QAM_LC_QUAL_TAB10_VALUE__B 0 +#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA +#define QAM_LC_QUAL_TAB10_VALUE__W 5 +#define QAM_LC_QUAL_TAB10__A 0x1450021 +#define QAM_LC_QUAL_TAB10__M 0x1F +#define QAM_LC_QUAL_TAB10__PRE 0xA +#define QAM_LC_QUAL_TAB10__W 5 +#define QAM_LC_QUAL_TAB12_VALUE__B 0 +#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC +#define QAM_LC_QUAL_TAB12_VALUE__W 5 +#define QAM_LC_QUAL_TAB12__A 0x1450022 +#define QAM_LC_QUAL_TAB12__M 0x1F +#define QAM_LC_QUAL_TAB12__PRE 0xC +#define QAM_LC_QUAL_TAB12__W 5 +#define QAM_LC_QUAL_TAB15_VALUE__B 0 +#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF +#define QAM_LC_QUAL_TAB15_VALUE__W 5 +#define QAM_LC_QUAL_TAB15__A 0x1450023 +#define QAM_LC_QUAL_TAB15__M 0x1F +#define QAM_LC_QUAL_TAB15__PRE 0xF +#define QAM_LC_QUAL_TAB15__W 5 +#define QAM_LC_QUAL_TAB16_VALUE__B 0 +#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 +#define QAM_LC_QUAL_TAB16_VALUE__W 5 +#define QAM_LC_QUAL_TAB16__A 0x1450024 +#define QAM_LC_QUAL_TAB16__M 0x1F +#define QAM_LC_QUAL_TAB16__PRE 0x10 +#define QAM_LC_QUAL_TAB16__W 5 +#define QAM_LC_QUAL_TAB1_VALUE__B 0 +#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 +#define QAM_LC_QUAL_TAB1_VALUE__W 5 +#define QAM_LC_QUAL_TAB1__A 0x1450019 +#define QAM_LC_QUAL_TAB1__M 0x1F +#define QAM_LC_QUAL_TAB1__PRE 0x1 +#define QAM_LC_QUAL_TAB1__W 5 +#define QAM_LC_QUAL_TAB20_VALUE__B 0 +#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 +#define QAM_LC_QUAL_TAB20_VALUE__W 5 +#define QAM_LC_QUAL_TAB20__A 0x1450025 +#define QAM_LC_QUAL_TAB20__M 0x1F +#define QAM_LC_QUAL_TAB20__PRE 0x14 +#define QAM_LC_QUAL_TAB20__W 5 +#define QAM_LC_QUAL_TAB25_VALUE__B 0 +#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 +#define QAM_LC_QUAL_TAB25_VALUE__W 5 +#define QAM_LC_QUAL_TAB25__A 0x1450026 +#define QAM_LC_QUAL_TAB25__M 0x1F +#define QAM_LC_QUAL_TAB25__PRE 0x19 +#define QAM_LC_QUAL_TAB25__W 5 +#define QAM_LC_QUAL_TAB2_VALUE__B 0 +#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 +#define QAM_LC_QUAL_TAB2_VALUE__W 5 +#define QAM_LC_QUAL_TAB2__A 0x145001A +#define QAM_LC_QUAL_TAB2__M 0x1F +#define QAM_LC_QUAL_TAB2__PRE 0x2 +#define QAM_LC_QUAL_TAB2__W 5 +#define QAM_LC_QUAL_TAB3_VALUE__B 0 +#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 +#define QAM_LC_QUAL_TAB3_VALUE__W 5 +#define QAM_LC_QUAL_TAB3__A 0x145001B +#define QAM_LC_QUAL_TAB3__M 0x1F +#define QAM_LC_QUAL_TAB3__PRE 0x3 +#define QAM_LC_QUAL_TAB3__W 5 +#define QAM_LC_QUAL_TAB4_VALUE__B 0 +#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 +#define QAM_LC_QUAL_TAB4_VALUE__W 5 +#define QAM_LC_QUAL_TAB4__A 0x145001C +#define QAM_LC_QUAL_TAB4__M 0x1F +#define QAM_LC_QUAL_TAB4__PRE 0x4 +#define QAM_LC_QUAL_TAB4__W 5 +#define QAM_LC_QUAL_TAB5_VALUE__B 0 +#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 +#define QAM_LC_QUAL_TAB5_VALUE__W 5 +#define QAM_LC_QUAL_TAB5__A 0x145001D +#define QAM_LC_QUAL_TAB5__M 0x1F +#define QAM_LC_QUAL_TAB5__PRE 0x5 +#define QAM_LC_QUAL_TAB5__W 5 +#define QAM_LC_QUAL_TAB6_VALUE__B 0 +#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 +#define QAM_LC_QUAL_TAB6_VALUE__W 5 +#define QAM_LC_QUAL_TAB6__A 0x145001E +#define QAM_LC_QUAL_TAB6__M 0x1F +#define QAM_LC_QUAL_TAB6__PRE 0x6 +#define QAM_LC_QUAL_TAB6__W 5 +#define QAM_LC_QUAL_TAB8_VALUE__B 0 +#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 +#define QAM_LC_QUAL_TAB8_VALUE__W 5 +#define QAM_LC_QUAL_TAB8__A 0x145001F +#define QAM_LC_QUAL_TAB8__M 0x1F +#define QAM_LC_QUAL_TAB8__PRE 0x8 +#define QAM_LC_QUAL_TAB8__W 5 +#define QAM_LC_QUAL_TAB9_VALUE__B 0 +#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 +#define QAM_LC_QUAL_TAB9_VALUE__W 5 +#define QAM_LC_QUAL_TAB9__A 0x1450020 +#define QAM_LC_QUAL_TAB9__M 0x1F +#define QAM_LC_QUAL_TAB9__PRE 0x9 +#define QAM_LC_QUAL_TAB9__W 5 +#define QAM_LC_RATE_LIMIT__A 0x145002A +#define QAM_LC_SYMBOL_FREQ__A 0x145002B +#define QAM_SL_ERR_POWER__A 0x1430017 +#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 +#define QAM_SY_SP_INV__A 0x1470017 +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_TIMEOUT__A 0x1470011 +#define QAM_SY_TIMEOUT__PRE 0x3A98 +#define QAM_TOP_ANNEX_A 0x0 +#define QAM_TOP_ANNEX_C 0x2 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_HOLD 0x2 +#define SCU_COMM_EXEC_HOLD 0x2 +#define SCU_COMM_EXEC_HOLD 0x2 +#define SCU_COMM_EXEC_HOLD 0x2 +#define SCU_COMM_EXEC_STOP 0x0 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 +#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 +#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 +#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 +#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 +#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 +#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F +#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E +#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 +#define SCU_RAM_AGC_CONFIG__A 0x831F24 +#define SCU_RAM_AGC_CONFIG__A 0x831F24 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 +#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 +#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E +#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D +#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 +#define SCU_RAM_AGC_KI_IF__B 8 +#define SCU_RAM_AGC_KI_IF__M 0xF00 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 +#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A +#define SCU_RAM_AGC_KI_MAX__A 0x831F2C +#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 +#define SCU_RAM_AGC_KI_MIN__A 0x831F2B +#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC +#define SCU_RAM_AGC_KI_RED__A 0x831F26 +#define SCU_RAM_AGC_KI_RED__A 0x831F26 +#define SCU_RAM_AGC_KI_RF__B 4 +#define SCU_RAM_AGC_KI_RF__M 0xF0 +#define SCU_RAM_AGC_KI__A 0x831F25 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 +#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 +#define SCU_RAM_AGC_RF_MAX__A 0x831F1B +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A +#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 +#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 +#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B +#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 +#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A +#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 +#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 +#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND__A 0x831FFD +#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF +#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB +#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 +#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD +#define SCU_RAM_PARAM_0_RESULT_OK 0x0 +#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC +#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF +#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE +#define SCU_RAM_PARAM_0__A 0x831FFC +#define SCU_RAM_PARAM_0__M 0xFFFF +#define SCU_RAM_PARAM_0__PRE 0x0 +#define SCU_RAM_PARAM_0__W 16 +#define SCU_RAM_PARAM_10__A 0x831FF2 +#define SCU_RAM_PARAM_10__M 0xFFFF +#define SCU_RAM_PARAM_10__PRE 0x0 +#define SCU_RAM_PARAM_10__W 16 +#define SCU_RAM_PARAM_11__A 0x831FF1 +#define SCU_RAM_PARAM_11__M 0xFFFF +#define SCU_RAM_PARAM_11__PRE 0x0 +#define SCU_RAM_PARAM_11__W 16 +#define SCU_RAM_PARAM_12__A 0x831FF0 +#define SCU_RAM_PARAM_12__M 0xFFFF +#define SCU_RAM_PARAM_12__PRE 0x0 +#define SCU_RAM_PARAM_12__W 16 +#define SCU_RAM_PARAM_13__A 0x831FEF +#define SCU_RAM_PARAM_13__M 0xFFFF +#define SCU_RAM_PARAM_13__PRE 0x0 +#define SCU_RAM_PARAM_13__W 16 +#define SCU_RAM_PARAM_14__A 0x831FEE +#define SCU_RAM_PARAM_14__M 0xFFFF +#define SCU_RAM_PARAM_14__PRE 0x0 +#define SCU_RAM_PARAM_14__W 16 +#define SCU_RAM_PARAM_15__A 0x831FED +#define SCU_RAM_PARAM_15__M 0xFFFF +#define SCU_RAM_PARAM_15__PRE 0x0 +#define SCU_RAM_PARAM_15__W 16 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 +#define SCU_RAM_PARAM_1__A 0x831FFB +#define SCU_RAM_PARAM_1__M 0xFFFF +#define SCU_RAM_PARAM_1__PRE 0x0 +#define SCU_RAM_PARAM_1__W 16 +#define SCU_RAM_PARAM_2__A 0x831FFA +#define SCU_RAM_PARAM_2__M 0xFFFF +#define SCU_RAM_PARAM_2__PRE 0x0 +#define SCU_RAM_PARAM_2__W 16 +#define SCU_RAM_PARAM_3__A 0x831FF9 +#define SCU_RAM_PARAM_3__M 0xFFFF +#define SCU_RAM_PARAM_3__PRE 0x0 +#define SCU_RAM_PARAM_3__W 16 +#define SCU_RAM_PARAM_4__A 0x831FF8 +#define SCU_RAM_PARAM_4__M 0xFFFF +#define SCU_RAM_PARAM_4__PRE 0x0 +#define SCU_RAM_PARAM_4__W 16 +#define SCU_RAM_PARAM_5__A 0x831FF7 +#define SCU_RAM_PARAM_5__M 0xFFFF +#define SCU_RAM_PARAM_5__PRE 0x0 +#define SCU_RAM_PARAM_5__W 16 +#define SCU_RAM_PARAM_6__A 0x831FF6 +#define SCU_RAM_PARAM_6__M 0xFFFF +#define SCU_RAM_PARAM_6__PRE 0x0 +#define SCU_RAM_PARAM_6__W 16 +#define SCU_RAM_PARAM_7__A 0x831FF5 +#define SCU_RAM_PARAM_7__M 0xFFFF +#define SCU_RAM_PARAM_7__PRE 0x0 +#define SCU_RAM_PARAM_7__W 16 +#define SCU_RAM_PARAM_8__A 0x831FF4 +#define SCU_RAM_PARAM_8__M 0xFFFF +#define SCU_RAM_PARAM_8__PRE 0x0 +#define SCU_RAM_PARAM_8__W 16 +#define SCU_RAM_PARAM_9__A 0x831FF3 +#define SCU_RAM_PARAM_9__M 0xFFFF +#define SCU_RAM_PARAM_9__PRE 0x0 +#define SCU_RAM_PARAM_9__W 16 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 +#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 +#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SIO_BL_CHAIN_ADDR__A 0x480018 +#define SIO_BL_CHAIN_LEN__A 0x480019 +#define SIO_BL_COMM_EXEC_ACTIVE 0x1 +#define SIO_BL_COMM_EXEC__A 0x480000 +#define SIO_BL_ENABLE_ON 0x1 +#define SIO_BL_ENABLE_ON 0x1 +#define SIO_BL_ENABLE__A 0x480012 +#define SIO_BL_ENABLE__A 0x480012 +#define SIO_BL_MODE_CHAIN 0x1 +#define SIO_BL_MODE_DIRECT 0x0 +#define SIO_BL_MODE__A 0x480011 +#define SIO_BL_MODE__A 0x480011 +#define SIO_BL_SRC_ADDR__A 0x480016 +#define SIO_BL_SRC_LEN__A 0x480017 +#define SIO_BL_STATUS__A 0x480010 +#define SIO_BL_STATUS__A 0x480010 +#define SIO_BL_TGT_ADDR__A 0x480015 +#define SIO_BL_TGT_HDR__A 0x480014 +#define SIO_CC_PLL_LOCK__A 0x450012 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 +#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 +#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_SOFT_RST_OFDM__M 0x1 +#define SIO_CC_SOFT_RST_OSC__M 0x4 +#define SIO_CC_SOFT_RST_SYS__M 0x2 +#define SIO_CC_SOFT_RST__A 0x450016 +#define SIO_CC_UPDATE_KEY 0xFABA +#define SIO_CC_UPDATE_KEY 0xFABA +#define SIO_CC_UPDATE_KEY 0xFABA +#define SIO_CC_UPDATE_KEY 0xFABA +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 +#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_RESET 0x2 +#define SIO_HI_RA_RAM_CMD__A 0x420032 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_RES__A 0x420031 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 +#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 +#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 +#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 +#define SIO_PDR_MCLK_CFG_DRIVE__B 3 +#define SIO_PDR_MCLK_CFG__A 0x7F0028 +#define SIO_PDR_MD0_CFG_DRIVE__B 3 +#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD0_CFG_DRIVE__W 3 +#define SIO_PDR_MD0_CFG_KEEP__B 6 +#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD0_CFG_KEEP__W 2 +#define SIO_PDR_MD0_CFG_MODE__B 0 +#define SIO_PDR_MD0_CFG_MODE__M 0x7 +#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD0_CFG_MODE__W 3 +#define SIO_PDR_MD0_CFG_UIO__B 8 +#define SIO_PDR_MD0_CFG_UIO__M 0x100 +#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD0_CFG_UIO__W 1 +#define SIO_PDR_MD0_CFG__A 0x7F002A +#define SIO_PDR_MD0_CFG__M 0x1FF +#define SIO_PDR_MD0_CFG__PRE 0x50 +#define SIO_PDR_MD0_CFG__W 9 +#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 +#define SIO_PDR_MD0_GPIO_FNC__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC__W 2 +#define SIO_PDR_MD1_CFG_DRIVE__B 3 +#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD1_CFG_DRIVE__W 3 +#define SIO_PDR_MD1_CFG_KEEP__B 6 +#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD1_CFG_KEEP__W 2 +#define SIO_PDR_MD1_CFG_MODE__B 0 +#define SIO_PDR_MD1_CFG_MODE__M 0x7 +#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD1_CFG_MODE__W 3 +#define SIO_PDR_MD1_CFG_UIO__B 8 +#define SIO_PDR_MD1_CFG_UIO__M 0x100 +#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD1_CFG_UIO__W 1 +#define SIO_PDR_MD1_CFG__A 0x7F002B +#define SIO_PDR_MD1_CFG__M 0x1FF +#define SIO_PDR_MD1_CFG__PRE 0x50 +#define SIO_PDR_MD1_CFG__W 9 +#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 +#define SIO_PDR_MD1_GPIO_FNC__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC__W 2 +#define SIO_PDR_MD2_CFG_DRIVE__B 3 +#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD2_CFG_DRIVE__W 3 +#define SIO_PDR_MD2_CFG_KEEP__B 6 +#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD2_CFG_KEEP__W 2 +#define SIO_PDR_MD2_CFG_MODE__B 0 +#define SIO_PDR_MD2_CFG_MODE__M 0x7 +#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD2_CFG_MODE__W 3 +#define SIO_PDR_MD2_CFG_UIO__B 8 +#define SIO_PDR_MD2_CFG_UIO__M 0x100 +#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD2_CFG_UIO__W 1 +#define SIO_PDR_MD2_CFG__A 0x7F002C +#define SIO_PDR_MD2_CFG__M 0x1FF +#define SIO_PDR_MD2_CFG__PRE 0x50 +#define SIO_PDR_MD2_CFG__W 9 +#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 +#define SIO_PDR_MD2_GPIO_FNC__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC__W 2 +#define SIO_PDR_MD3_CFG_DRIVE__B 3 +#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD3_CFG_DRIVE__W 3 +#define SIO_PDR_MD3_CFG_KEEP__B 6 +#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD3_CFG_KEEP__W 2 +#define SIO_PDR_MD3_CFG_MODE__B 0 +#define SIO_PDR_MD3_CFG_MODE__M 0x7 +#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD3_CFG_MODE__W 3 +#define SIO_PDR_MD3_CFG_UIO__B 8 +#define SIO_PDR_MD3_CFG_UIO__M 0x100 +#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD3_CFG_UIO__W 1 +#define SIO_PDR_MD3_CFG__A 0x7F002D +#define SIO_PDR_MD3_CFG__M 0x1FF +#define SIO_PDR_MD3_CFG__PRE 0x50 +#define SIO_PDR_MD3_CFG__W 9 +#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 +#define SIO_PDR_MD3_GPIO_FNC__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC__W 2 +#define SIO_PDR_MD4_CFG_DRIVE__B 3 +#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD4_CFG_DRIVE__W 3 +#define SIO_PDR_MD4_CFG_KEEP__B 6 +#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD4_CFG_KEEP__W 2 +#define SIO_PDR_MD4_CFG_MODE__B 0 +#define SIO_PDR_MD4_CFG_MODE__M 0x7 +#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD4_CFG_MODE__W 3 +#define SIO_PDR_MD4_CFG_UIO__B 8 +#define SIO_PDR_MD4_CFG_UIO__M 0x100 +#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD4_CFG_UIO__W 1 +#define SIO_PDR_MD4_CFG__A 0x7F002F +#define SIO_PDR_MD4_CFG__M 0x1FF +#define SIO_PDR_MD4_CFG__PRE 0x50 +#define SIO_PDR_MD4_CFG__W 9 +#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A +#define SIO_PDR_MD4_GPIO_FNC__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC__W 2 +#define SIO_PDR_MD5_CFG_DRIVE__B 3 +#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD5_CFG_DRIVE__W 3 +#define SIO_PDR_MD5_CFG_KEEP__B 6 +#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD5_CFG_KEEP__W 2 +#define SIO_PDR_MD5_CFG_MODE__B 0 +#define SIO_PDR_MD5_CFG_MODE__M 0x7 +#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD5_CFG_MODE__W 3 +#define SIO_PDR_MD5_CFG_UIO__B 8 +#define SIO_PDR_MD5_CFG_UIO__M 0x100 +#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD5_CFG_UIO__W 1 +#define SIO_PDR_MD5_CFG__A 0x7F0030 +#define SIO_PDR_MD5_CFG__M 0x1FF +#define SIO_PDR_MD5_CFG__PRE 0x50 +#define SIO_PDR_MD5_CFG__W 9 +#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B +#define SIO_PDR_MD5_GPIO_FNC__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC__W 2 +#define SIO_PDR_MD6_CFG_DRIVE__B 3 +#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD6_CFG_DRIVE__W 3 +#define SIO_PDR_MD6_CFG_KEEP__B 6 +#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD6_CFG_KEEP__W 2 +#define SIO_PDR_MD6_CFG_MODE__B 0 +#define SIO_PDR_MD6_CFG_MODE__M 0x7 +#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD6_CFG_MODE__W 3 +#define SIO_PDR_MD6_CFG_UIO__B 8 +#define SIO_PDR_MD6_CFG_UIO__M 0x100 +#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD6_CFG_UIO__W 1 +#define SIO_PDR_MD6_CFG__A 0x7F0031 +#define SIO_PDR_MD6_CFG__M 0x1FF +#define SIO_PDR_MD6_CFG__PRE 0x50 +#define SIO_PDR_MD6_CFG__W 9 +#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C +#define SIO_PDR_MD6_GPIO_FNC__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC__W 2 +#define SIO_PDR_MD7_CFG_DRIVE__B 3 +#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD7_CFG_DRIVE__W 3 +#define SIO_PDR_MD7_CFG_KEEP__B 6 +#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD7_CFG_KEEP__W 2 +#define SIO_PDR_MD7_CFG_MODE__B 0 +#define SIO_PDR_MD7_CFG_MODE__M 0x7 +#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD7_CFG_MODE__W 3 +#define SIO_PDR_MD7_CFG_UIO__B 8 +#define SIO_PDR_MD7_CFG_UIO__M 0x100 +#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD7_CFG_UIO__W 1 +#define SIO_PDR_MD7_CFG__A 0x7F0032 +#define SIO_PDR_MD7_CFG__M 0x1FF +#define SIO_PDR_MD7_CFG__PRE 0x50 +#define SIO_PDR_MD7_CFG__W 9 +#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D +#define SIO_PDR_MD7_GPIO_FNC__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC__W 2 +#define SIO_PDR_MERR_CFG__A 0x7F0026 +#define SIO_PDR_MON_CFG__A 0x7F0010 +#define SIO_PDR_MSTRT_CFG__A 0x7F0025 +#define SIO_PDR_MVAL_CFG__A 0x7F0029 +#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 +#define SIO_PDR_OHW_CFG__A 0x7F001F +#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +#define SIO_PDR_UIO_IN_HI__A 0x7F0015 +#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 +#define SIO_TOP_COMM_KEY_KEY 0xFABA +#define SIO_TOP_COMM_KEY_KEY 0xFABA +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_JTAGID_LO__A 0x410012 +#define SIO_TOP_JTAGID_LO__A 0x410012 diff --git a/frontends/mxl5xx_regs.h b/frontends/mxl5xx_regs.h index c8feba9..e983d0b 100644 --- a/frontends/mxl5xx_regs.h +++ b/frontends/mxl5xx_regs.h @@ -1,941 +1,941 @@ -/* -* Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved -* -* License type: GPLv2 -* -* This program is free software; you can redistribute it and/or modify it under -* the terms of the GNU General Public License as published by the Free Software -* Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS -* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA -* -* This program may alternatively be licensed under a proprietary license from -* MaxLinear, Inc. -* -* See terms and conditions defined in file 'LICENSE.txt', which is part of this -* source code package. -*/ - -#ifndef __MXL58X_REGISTERS_H__ -#define __MXL58X_REGISTERS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#define HYDRA_INTR_STATUS_REG 0x80030008 -#define HYDRA_INTR_MASK_REG 0x8003000C - -#define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 // 0 - 24 MHz & 1 - 27 MHz -#define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 // 0 - 24 MHz & 1 - 27 MHz - -#define HYDRA_CPU_RESET_REG 0x8003003C -#define HYDRA_CPU_RESET_DATA 0x00000400 - -#define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028 -#define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000 - -#define HYDRA_RESET_BBAND_REG 0x80030024 -#define HYDRA_RESET_BBAND_DATA 0x00000000 - -#define HYDRA_RESET_XBAR_REG 0x80030020 -#define HYDRA_RESET_XBAR_DATA 0x00000000 - -#define HYDRA_MODULES_CLK_1_REG 0x80030014 -#define HYDRA_DISABLE_CLK_1 0x00000000 - -#define HYDRA_MODULES_CLK_2_REG 0x8003001C -#define HYDRA_DISABLE_CLK_2 0x0000000B - -#define HYDRA_PRCM_ROOT_CLK_REG 0x80030018 -#define HYDRA_PRCM_ROOT_CLK_DISABLE 0x00000000 - -#define HYDRA_CPU_RESET_CHECK_REG 0x80030008 -#define HYDRA_CPU_RESET_CHECK_OFFSET 0x40000000 // - -#define HYDRA_SKU_ID_REG 0x90000190 - -#define FW_DL_SIGN_ADDR 0x3FFFEAE0 - -// Register to check if FW is running or not -#define HYDRA_HEAR_BEAT 0x3FFFEDDC - -// Firmware version -#define HYDRA_FIRMWARE_VERSION 0x3FFFEDB8 -#define HYDRA_FW_RC_VERSION 0x3FFFCFAC - -// Firmware patch version -#define HYDRA_FIRMWARE_PATCH_VERSION 0x3FFFEDC2 - -// SOC operating temperature in C -#define HYDRA_TEMPARATURE 0x3FFFEDB4 - -// Demod & Tuner status registers -// Demod 0 status base address -#define HYDRA_DEMOD_0_BASE_ADDR 0x3FFFC64C - -// Tuner 0 status base address -#define HYDRA_TUNER_0_BASE_ADDR 0x3FFFCE4C - -#define POWER_FROM_ADCRSSI_READBACK 0x3FFFEB6C - -// Macros to determine base address of respective demod or tuner -#define HYDRA_DMD_STATUS_OFFSET(demodID) ((demodID) * 0x100) -#define HYDRA_TUNER_STATUS_OFFSET(tunerID) ((tunerID) * 0x40) - -// Demod status address offset from respective demod's base address -#define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET 0x3FFFC64C -#define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET 0x3FFFC650 -#define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET 0x3FFFC654 - -#define HYDRA_DMD_STANDARD_ADDR_OFFSET 0x3FFFC658 -#define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET 0x3FFFC65C -#define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET 0x3FFFC660 -#define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET 0x3FFFC664 -#define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET 0x3FFFC668 -#define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET 0x3FFFC66C - -#define HYDRA_DMD_SNR_ADDR_OFFSET 0x3FFFC670 -#define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC674 -#define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC678 -#define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67C -#define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC680 -#define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET 0x3FFFC684 -#define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET 0x3FFFC688 - -#define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET 0x3FFFC68C -#define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET 0x3FFFC68E - -#define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET 0x3FFFC690 -#define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET 0x3FFFC694 -#define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET 0x3FFFC698 - -#define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC69C -#define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6A0 -#define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET 0x3FFFC6A4 -#define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET 0x3FFFC6A8 - -// Debug-purpose DVB-S DMD 0 -#define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6C8 // corrected RS Errors: 1st iteration -#define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6CC // uncorrected RS Errors: 1st iteration -#define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET 0x3FFFC6D0 -#define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET 0x3FFFC6D4 - -#define HYDRA_DMD_TUNER_ID_ADDR_OFFSET 0x3FFFC6AC -#define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET 0x3FFFC6B0 -#define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET 0x3FFFC6B4 -#define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET 0x3FFFC6B8 -#define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR 0x3FFFC704 -#define HYDRA_DMD_STATUS_INPUT_POWER_ADDR 0x3FFFC708 - -// DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information" -#define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR 0x3FFFC710 // DMD 0: 1st iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR -#define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR 0x3FFFC714 // DMD 0: 2nd iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR - -#define DMD0_SPECTRUM_MIN_GAIN_STATUS 0x3FFFC73C -#define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE 0x3FFFC740 -#define DMD0_SPECTRUM_ MIN_GAIN_NB_SAGC_VALUE 0x3FFFC744 - -#define HYDRA_DMD_STATUS_END_ADDR_OFFSET 0x3FFFC748 - -// Tuner status address offset from respective tuners's base address -#define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET 0x3FFFCE4C -#define HYDRA_TUNER_AGC_LOCK_OFFSET 0x3FFFCE50 -#define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET 0x3FFFCE54 -#define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET 0x3FFFCE58 -#define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET 0x3FFFCE5C -#define HYDRA_TUNER_ENABLE_COMPLETE 0x3FFFEB78 - -#define HYDRA_DEMOD_STATUS_LOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES) -#define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO) - -#define HYDRA_TUNER_STATUS_LOCK(devId,tunerId) MxLWare_HYDRA_WriteRegister(devId,(HYDRA_TUNER_STATUS_LOCK_ADDR_OFFSET + HYDRA_TUNER_STATUS_OFFSET(tunerId)), MXL_YES) -#define HYDRA_TUNER_STATUS_UNLOCK(devId,tunerId) MxLWare_HYDRA_WriteRegister(devId,(HYDRA_TUNER_STATUS_LOCK_ADDR_OFFSET + HYDRA_TUNER_STATUS_OFFSET(tunerId)), MXL_NO) - -#define HYDRA_VERSION 0x3FFFEDB8 -#define HYDRA_DEMOD0_VERSION 0x3FFFEDBC -#define HYDRA_DEMOD1_VERSION 0x3FFFEDC0 -#define HYDRA_DEMOD2_VERSION 0x3FFFEDC4 -#define HYDRA_DEMOD3_VERSION 0x3FFFEDC8 -#define HYDRA_DEMOD4_VERSION 0x3FFFEDCC -#define HYDRA_DEMOD5_VERSION 0x3FFFEDD0 -#define HYDRA_DEMOD6_VERSION 0x3FFFEDD4 -#define HYDRA_DEMOD7_VERSION 0x3FFFEDD8 -#define HYDRA_HEAR_BEAT 0x3FFFEDDC -#define HYDRA_SKU_MGMT 0x3FFFEBC0 - -#define MXL_HYDRA_FPGA_A_ADDRESS 0x91C00000 -#define MXL_HYDRA_FPGA_B_ADDRESS 0x91D00000 - -// TS control base address -#define HYDRA_TS_CTRL_BASE_ADDR 0x90700000 - -#define MPEG_MUX_MODE_SLICE0_REG HYDRA_TS_CTRL_BASE_ADDR + 0x08 -#define MPEG_MUX_MODE_SLICE0_OFFSET (0),(2) - -#define MPEG_MUX_MODE_SLICE1_REG HYDRA_TS_CTRL_BASE_ADDR + 0x08 -#define MPEG_MUX_MODE_SLICE1_OFFSET (2),(2) - -#define PID_BANK_SEL_SLICE0_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190 -#define PID_BANK_SEL_SLICE1_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0 - -#define SW_REGULAR_PID_SW_BANK_OFFSET 0,1 -#define SW_FIXED_PID_SW_BANK_OFFSET 1,1 - -#define HW_REGULAR_PID_BANK_OFFSET 8,4 -#define HW_FIXED_PID_BANK_OFFSET 4,4 - -#define MPEG_CLK_GATED_REG HYDRA_TS_CTRL_BASE_ADDR + 0x20 -#define MPEG_CLK_GATED_OFFSET 0,1 - -#define MPEG_CLK_ALWAYS_ON_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1D4 -#define MPEG_CLK_ALWAYS_ON_OFFSET 0,1 - -#define HYDRA_REGULAR_PID_BANK_A_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190 -#define HYDRA_REGULAR_PID_BAN K_A_OFFSET 0,1 - -#define HYDRA_FIXED_PID_BANK_A_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190 -#define HYDRA_FIXED_PID_BANK_A_OFFSET 1,1 - -#define HYDRA_REGULAR_PID_BANK_B_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0 -#define HYDRA_REGULAR_PID_BANK_B_OFFSET 0,1 - -#define HYDRA_FIXED_PID_BANK_B_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0 -#define HYDRA_FIXED_PID_BANK_B_OFFSET 1,1 - -#define FIXED_PID_TBL_REG_ADDRESS_0 HYDRA_TS_CTRL_BASE_ADDR + 0x9000 -#define FIXED_PID_TBL_REG_ADDRESS_1 HYDRA_TS_CTRL_BASE_ADDR + 0x9100 -#define FIXED_PID_TBL_REG_ADDRESS_2 HYDRA_TS_CTRL_BASE_ADDR + 0x9200 -#define FIXED_PID_TBL_REG_ADDRESS_3 HYDRA_TS_CTRL_BASE_ADDR + 0x9300 - -#define FIXED_PID_TBL_REG_ADDRESS_4 HYDRA_TS_CTRL_BASE_ADDR + 0xB000 -#define FIXED_PID_TBL_REG_ADDRESS_5 HYDRA_TS_CTRL_BASE_ADDR + 0xB100 -#define FIXED_PID_TBL_REG_ADDRESS_6 HYDRA_TS_CTRL_BASE_ADDR + 0xB200 -#define FIXED_PID_TBL_REG_ADDRESS_7 HYDRA_TS_CTRL_BASE_ADDR + 0xB300 - -#define REGULAR_PID_TBL_REG_ADDRESS_0 HYDRA_TS_CTRL_BASE_ADDR + 0x8000 -#define REGULAR_PID_TBL_REG_ADDRESS_1 HYDRA_TS_CTRL_BASE_ADDR + 0x8200 -#define REGULAR_PID_TBL_REG_ADDRESS_2 HYDRA_TS_CTRL_BASE_ADDR + 0x8400 -#define REGULAR_PID_TBL_REG_ADDRESS_3 HYDRA_TS_CTRL_BASE_ADDR + 0x8600 - -#define REGULAR_PID_TBL_REG_ADDRESS_4 HYDRA_TS_CTRL_BASE_ADDR + 0xA000 -#define REGULAR_PID_TBL_REG_ADDRESS_5 HYDRA_TS_CTRL_BASE_ADDR + 0xA200 -#define REGULAR_PID_TBL_REG_ADDRESS_6 HYDRA_TS_CTRL_BASE_ADDR + 0xA400 -#define REGULAR_PID_TBL_REG_ADDRESS_7 HYDRA_TS_CTRL_BASE_ADDR + 0xA600 - -#define PID_VALID_OFFSET 0,1 -#define PID_DROP_OFFSET 1,1 -#define PID_REMAP_ENABLE_OFFSET 2,1 -#define PID_VALUE_OFFSET 4,13 -#define PID_MASK_OFFSET 19,13 - -#define REGULAR_PID_REMAP_VALUE_OFFSET 0,13 -#define FIXED_PID_REMAP_VALUE_OFFSET 0,16 -#define PID_DEMODID_OFFSET 16,3 - - -/////////////////////////////////////////////// - -#if 0 -#define AFE_REG_D2A_TA_ADC_CLK_OUT_FLIP 0x90200004,12,1 -#define AFE_REG_D2A_TA_RFFE_LNACAPLOAD_1P8 0x90200028,24,4 -#define AFE_REG_D2A_TA_RFFE_RF1_EN_1P8 0x90200028,5,1 -#define AFE_REG_D2A_TA_RFFE_SPARE_1P8 0x90200028,8,8 -#define AFE_REG_D2A_TB_ADC_CLK_OUT_FLIP 0x9020000C,23,1 -#define AFE_REG_D2A_TB_RFFE_LNACAPLOAD_1P8 0x90200030,16,4 -#define AFE_REG_D2A_TB_RFFE_RF1_EN_1P8 0x9020002C,21,1 -#define AFE_REG_D2A_TB_RFFE_SPARE_1P8 0x90200030,0,8 -#define AFE_REG_D2A_TC_ADC_CLK_OUT_FLIP 0x90200018,7,1 -#define AFE_REG_D2A_TC_RFFE_LNACAPLOAD_1P8 0x90200038,2,4 -#define AFE_REG_D2A_TC_RFFE_RF1_EN_1P8 0x90200034,14,1 -#define AFE_REG_D2A_TC_RFFE_SPARE_1P8 0x90200034,17,8 -#define AFE_REG_D2A_TD_ADC_CLK_OUT_FLIP 0x90200020,18,1 -#define AFE_REG_D2A_TD_RFFE_LNACAPLOAD_1P8 0x9020003C,17,4 -#define AFE_REG_D2A_TD_RFFE_RF1_EN_1P8 0x90200038,29,1 -#define AFE_REG_D2A_TD_RFFE_SPARE_1P8 0x9020003C,1,8 -#endif -#define AFE_REG_D2A_XTAL_EN_CLKOUT_1P8 0x90200054,23,1 - -#define PAD_MUX_TS0_IN_CLK_PINMUX_SEL 0x90000018,0,3 -#define PAD_MUX_TS0_IN_DATA_PINMUX_SEL 0x90000018,4,3 -#define PAD_MUX_TS1_IN_CLK_PINMUX_SEL 0x90000018,8,3 -#define PAD_MUX_TS1_IN_DATA_PINMUX_SEL 0x90000018,12,3 -#define PAD_MUX_TS2_IN_CLK_PINMUX_SEL 0x90000018,16,3 -#define PAD_MUX_TS2_IN_DATA_PINMUX_SEL 0x90000018,20,3 -#define PAD_MUX_TS3_IN_CLK_PINMUX_SEL 0x90000018,24,3 -#define PAD_MUX_TS3_IN_DATA_PINMUX_SEL 0x90000018,28,3 - -#define PAD_MUX_GPIO_00_SYNC_BASEADDR 0x90000188 -#define PAD_MUX_GPIO_01_SYNC_IN PAD_MUX_GPIO_00_SYNC_BASEADDR,1,1 - -#define PRCM_AFE_SOC_ID 0x80030004,24,8 - -#define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C -#define PAD_MUX_UART_RX_C_PINMUX_SEL PAD_MUX_UART_RX_C_PINMUX_BASEADDR,0,3 -#define PAD_MUX_UART_RX_D_PINMUX_SEL PAD_MUX_UART_RX_C_PINMUX_BASEADDR,4,3 -#define PAD_MUX_BOND_OPTION 0x90000190,0,3 -#define PAD_MUX_DIGIO_01_PINMUX_SEL 0x9000016C,4,3 -#define PAD_MUX_DIGIO_02_PINMUX_SEL 0x9000016C,8,3 -#define PAD_MUX_DIGIO_03_PINMUX_SEL 0x9000016C,12,3 -#define PAD_MUX_DIGIO_04_PINMUX_SEL 0x9000016C,16,3 -#define PAD_MUX_DIGIO_05_PINMUX_SEL 0x9000016C,20,3 -#define PAD_MUX_DIGIO_06_PINMUX_SEL 0x9000016C,24,3 -#define PAD_MUX_DIGIO_07_PINMUX_SEL 0x9000016C,28,3 -#define PAD_MUX_DIGIO_08_PINMUX_SEL 0x90000170,0,3 -#define PAD_MUX_DIGIO_09_PINMUX_SEL 0x90000170,4,3 -#define PAD_MUX_DIGIO_10_PINMUX_SEL 0x90000170,8,3 -#define PAD_MUX_DIGIO_11_PINMUX_SEL 0x90000170,12,3 -#define PAD_MUX_DIGIO_12_PINMUX_SEL 0x90000170,16,3 -#define PAD_MUX_DIGIO_13_PINMUX_SEL 0x90000170,20,3 -#define PAD_MUX_DIGIO_14_PINMUX_SEL 0x90000170,24,3 -#define PAD_MUX_DIGIO_15_PINMUX_SEL 0x90000170,28,3 -#define PAD_MUX_DIGIO_16_PINMUX_SEL 0x90000174,0,3 -#define PAD_MUX_DIGIO_17_PINMUX_SEL 0x90000174,4,3 -#define PAD_MUX_DIGIO_18_PINMUX_SEL 0x90000174,8,3 -#define PAD_MUX_DIGIO_19_PINMUX_SEL 0x90000174,12,3 -#define PAD_MUX_DIGIO_20_PINMUX_SEL 0x90000174,16,3 -#define PAD_MUX_DIGIO_21_PINMUX_SEL 0x90000174,20,3 -#define PAD_MUX_DIGIO_22_PINMUX_SEL 0x90000174,24,3 -#define PAD_MUX_DIGIO_23_PINMUX_SEL 0x90000174,28,3 -#define PAD_MUX_DIGIO_24_PINMUX_SEL 0x90000178,0,3 -#define PAD_MUX_DIGIO_25_PINMUX_SEL 0x90000178,4,3 -#define PAD_MUX_DIGIO_26_PINMUX_SEL 0x90000178,8,3 -#define PAD_MUX_DIGIO_27_PINMUX_SEL 0x90000178,12,3 -#define PAD_MUX_DIGIO_28_PINMUX_SEL 0x90000178,16,3 -#define PAD_MUX_DIGIO_29_PINMUX_SEL 0x90000178,20,3 -#define PAD_MUX_DIGIO_30_PINMUX_SEL 0x90000178,24,3 -#define PAD_MUX_DIGIO_31_PINMUX_SEL 0x90000178,28,3 -#define PAD_MUX_DIGIO_32_PINMUX_SEL 0x9000017C,0,3 -#define PAD_MUX_DIGIO_33_PINMUX_SEL 0x9000017C,4,3 -#define PAD_MUX_DIGIO_34_PINMUX_SEL 0x9000017C,8,3 -#define PAD_MUX_EJTAG_TCK_PINMUX_SEL 0x90000020,0,3 -#define PAD_MUX_EJTAG_TDI_PINMUX_SEL 0x90000020,8,3 -#define PAD_MUX_EJTAG_TMS_PINMUX_SEL 0x90000020,4,3 -#define PAD_MUX_EJTAG_TRSTN_PINMUX_SEL 0x90000020,12,3 -#define PAD_MUX_PAD_DRV_DIGIO_00 0x90000194,0,3 -#define PAD_MUX_PAD_DRV_DIGIO_05 0x90000194,20,3 -#define PAD_MUX_PAD_DRV_DIGIO_06 0x90000194,24,3 -#define PAD_MUX_PAD_DRV_DIGIO_11 0x90000198,12,3 -#define PAD_MUX_PAD_DRV_DIGIO_12 0x90000198,16,3 -#define PAD_MUX_PAD_DRV_DIGIO_13 0x90000198,20,3 -#define PAD_MUX_PAD_DRV_DIGIO_14 0x90000198,24,3 -#define PAD_MUX_PAD_DRV_DIGIO_16 0x9000019C,0,3 -#define PAD_MUX_PAD_DRV_DIGIO_17 0x9000019C,4,3 -#define PAD_MUX_PAD_DRV_DIGIO_18 0x9000019C,8,3 -#define PAD_MUX_PAD_DRV_DIGIO_22 0x9000019C,24,3 -#define PAD_MUX_PAD_DRV_DIGIO_23 0x9000019C,28,3 -#define PAD_MUX_PAD_DRV_DIGIO_24 0x900001A0,0,3 -#define PAD_MUX_PAD_DRV_DIGIO_25 0x900001A0,4,3 -#define PAD_MUX_PAD_DRV_DIGIO_29 0x900001A0,20,3 -#define PAD_MUX_PAD_DRV_DIGIO_30 0x900001A0,24,3 -#define PAD_MUX_PAD_DRV_DIGIO_31 0x900001A0,28,3 -#define PRCM_AFE_REG_CLOCK_ENABLE 0x80030014,9,1 -#define PRCM_CHIP_VERSION 0x80030000,12,4 -#define PRCM_AFE_CHIP_MMSK_VER 0x80030004,8,8 -#define PRCM_PRCM_AFE_REG_SOFT_RST_N 0x8003003C,12,1 -#define PRCM_PRCM_CPU_SOFT_RST_N 0x8003003C,0,1 -#define PRCM_PRCM_DIGRF_APB_DATA_BB0 0x80030074,0,20 -#define PRCM_PRCM_DIGRF_APB_DATA_BB1 0x80030078,0,20 -#define PRCM_PRCM_DIGRF_APB_DATA_BB2 0x8003007C,0,20 -#define PRCM_PRCM_DIGRF_APB_DATA_BB3 0x80030080,0,20 -#define PRCM_PRCM_DIGRF_APB_DATA_BB4 0x80030084,0,20 -#define PRCM_PRCM_DIGRF_APB_DATA_BB5 0x80030088,0,20 -#define PRCM_PRCM_DIGRF_APB_DATA_BB6 0x8003008C,0,20 -#define PRCM_PRCM_DIGRF_APB_DATA_BB7 0x80030090,0,20 -#define PRCM_PRCM_DIGRF_CAPT_DONE 0x80030070,24,8 -#define PRCM_PRCM_DIGRF_START_CAPT 0x80030064,2,1 -#define PRCM_PRCM_PAD_MUX_SOFT_RST_N 0x8003003C,11,1 -#define PRCM_PRCM_XPT_PARALLEL_FIFO_RST_N 0x80030028,20,1 -#define XPT_APPEND_BYTES0 0x90700008,4,2 -#define XPT_APPEND_BYTES1 0x90700008,6,2 -#define XPT_CLOCK_POLARITY0 0x90700010,16,1 -#define XPT_CLOCK_POLARITY1 0x90700010,17,1 -#define XPT_CLOCK_POLARITY2 0x90700010,18,1 -#define XPT_CLOCK_POLARITY3 0x90700010,19,1 -#define XPT_CLOCK_POLARITY4 0x90700010,20,1 -#define XPT_CLOCK_POLARITY5 0x90700010,21,1 -#define XPT_CLOCK_POLARITY6 0x90700010,22,1 -#define XPT_CLOCK_POLARITY7 0x90700010,23,1 -#define XPT_DSS_DVB_ENCAP_EN0 0x90700000,16,1 -#define XPT_DSS_DVB_ENCAP_EN1 0x90700000,17,1 -#define XPT_DSS_DVB_ENCAP_EN2 0x90700000,18,1 -#define XPT_DSS_DVB_ENCAP_EN3 0x90700000,19,1 -#define XPT_DSS_DVB_ENCAP_EN4 0x90700000,20,1 -#define XPT_DSS_DVB_ENCAP_EN5 0x90700000,21,1 -#define XPT_DSS_DVB_ENCAP_EN6 0x90700000,22,1 -#define XPT_DSS_DVB_ENCAP_EN7 0x90700000,23,1 -#define XPT_DVB_MATCH_BYTE 0x9070017C,16,8 -#define XPT_DVB_PACKET_SIZE0 0x90700180,0,8 -#define XPT_DVB_PACKET_SIZE1 0x90700180,8,8 -#define XPT_DVB_PACKET_SIZE2 0x90700180,16,8 -#define XPT_DVB_PACKET_SIZE3 0x90700180,24,8 -#define XPT_ENABLE_DVB_INPUT0 0x90700178,0,1 -#define XPT_ENABLE_DVB_INPUT1 0x90700178,1,1 -#define XPT_ENABLE_DVB_INPUT2 0x90700178,2,1 -#define XPT_ENABLE_DVB_INPUT3 0x90700178,3,1 -#define XPT_ENABLE_INPUT0 0x90700000,0,1 -#define XPT_ENABLE_INPUT1 0x90700000,1,1 -#define XPT_ENABLE_INPUT2 0x90700000,2,1 -#define XPT_ENABLE_INPUT3 0x90700000,3,1 -#define XPT_ENABLE_INPUT4 0x90700000,4,1 -#define XPT_ENABLE_INPUT5 0x90700000,5,1 -#define XPT_ENABLE_INPUT6 0x90700000,6,1 -#define XPT_ENABLE_INPUT7 0x90700000,7,1 -#define XPT_ENABLE_OUTPUT0 0x9070000C,0,1 -#define XPT_ENABLE_OUTPUT1 0x9070000C,1,1 -#define XPT_ENABLE_OUTPUT2 0x9070000C,2,1 -#define XPT_ENABLE_OUTPUT3 0x9070000C,3,1 -#define XPT_ENABLE_OUTPUT4 0x9070000C,4,1 -#define XPT_ENABLE_OUTPUT5 0x9070000C,5,1 -#define XPT_ENABLE_OUTPUT6 0x9070000C,6,1 -#define XPT_ENABLE_OUTPUT7 0x9070000C,7,1 -#define XPT_ENABLE_PARALLEL_OUTPUT 0x90700010,27,1 -#define XPT_ENABLE_PCR_COUNT 0x90700184,1,1 -#define XPT_ERROR_REPLACE_SYNC0 0x9070000C,24,1 -#define XPT_ERROR_REPLACE_SYNC1 0x9070000C,25,1 -#define XPT_ERROR_REPLACE_SYNC2 0x9070000C,26,1 -#define XPT_ERROR_REPLACE_SYNC3 0x9070000C,27,1 -#define XPT_ERROR_REPLACE_SYNC4 0x9070000C,28,1 -#define XPT_ERROR_REPLACE_SYNC5 0x9070000C,29,1 -#define XPT_ERROR_REPLACE_SYNC6 0x9070000C,30,1 -#define XPT_ERROR_REPLACE_SYNC7 0x9070000C,31,1 -#define XPT_ERROR_REPLACE_VALID0 0x90700014,8,1 -#define XPT_ERROR_REPLACE_VALID1 0x90700014,9,1 -#define XPT_ERROR_REPLACE_VALID2 0x90700014,10,1 -#define XPT_ERROR_REPLACE_VALID3 0x90700014,11,1 -#define XPT_ERROR_REPLACE_VALID4 0x90700014,12,1 -#define XPT_ERROR_REPLACE_VALID5 0x90700014,13,1 -#define XPT_ERROR_REPLACE_VALID6 0x90700014,14,1 -#define XPT_ERROR_REPLACE_VALID7 0x90700014,15,1 -#define XPT_INP0_MERGE_HDR0 0x90700058,0,32 -#define XPT_INP0_MERGE_HDR1 0x9070005C,0,32 -#define XPT_INP0_MERGE_HDR2 0x90700060,0,32 -#define XPT_INP1_MERGE_HDR0 0x90700064,0,32 -#define XPT_INP1_MERGE_HDR1 0x90700068,0,32 -#define XPT_INP1_MERGE_HDR2 0x9070006C,0,32 -#define XPT_INP2_MERGE_HDR0 0x90700070,0,32 -#define XPT_INP2_MERGE_HDR1 0x90700074,0,32 -#define XPT_INP2_MERGE_HDR2 0x90700078,0,32 -#define XPT_INP3_MERGE_HDR0 0x9070007C,0,32 -#define XPT_INP3_MERGE_HDR1 0x90700080,0,32 -#define XPT_INP3_MERGE_HDR2 0x90700084,0,32 -#define XPT_INP4_MERGE_HDR0 0x90700088,0,32 -#define XPT_INP4_MERGE_HDR1 0x9070008C,0,32 -#define XPT_INP4_MERGE_HDR2 0x90700090,0,32 -#define XPT_INP5_MERGE_HDR0 0x90700094,0,32 -#define XPT_INP5_MERGE_HDR1 0x90700098,0,32 -#define XPT_INP5_MERGE_HDR2 0x9070009C,0,32 -#define XPT_INP6_MERGE_HDR0 0x907000A0,0,32 -#define XPT_INP6_MERGE_HDR1 0x907000A4,0,32 -#define XPT_INP6_MERGE_HDR2 0x907000A8,0,32 -#define XPT_INP7_MERGE_HDR0 0x907000AC,0,32 -#define XPT_INP7_MERGE_HDR1 0x907000B0,0,32 -#define XPT_INP7_MERGE_HDR2 0x907000B4,0,32 -#define XPT_INP_MODE_DSS0 0x90700000,8,1 -#define XPT_INP_MODE_DSS1 0x90700000,9,1 -#define XPT_INP_MODE_DSS2 0x90700000,10,1 -#define XPT_INP_MODE_DSS3 0x90700000,11,1 -#define XPT_INP_MODE_DSS4 0x90700000,12,1 -#define XPT_INP_MODE_DSS5 0x90700000,13,1 -#define XPT_INP_MODE_DSS6 0x90700000,14,1 -#define XPT_INP_MODE_DSS7 0x90700000,15,1 -#define XPT_KNOWN_PID_MUX_SELECT0 0x90700190,8,4 -#define XPT_KNOWN_PID_MUX_SELECT1 0x907001B0,8,4 -#define XPT_LSB_FIRST0 0x9070000C,16,1 -#define XPT_LSB_FIRST1 0x9070000C,17,1 -#define XPT_LSB_FIRST2 0x9070000C,18,1 -#define XPT_LSB_FIRST3 0x9070000C,19,1 -#define XPT_LSB_FIRST4 0x9070000C,20,1 -#define XPT_LSB_FIRST5 0x9070000C,21,1 -#define XPT_LSB_FIRST6 0x9070000C,22,1 -#define XPT_LSB_FIRST7 0x9070000C,23,1 -#define XPT_MODE_27MHZ 0x90700184,0,1 -#define XPT_NCO_COUNT_MIN 0x90700044,16,8 -#define XPT_OUTPUT_MODE_DSS0 0x9070000C,8,1 -#define XPT_OUTPUT_MODE_DSS1 0x9070000C,9,1 -#define XPT_OUTPUT_MODE_DSS2 0x9070000C,10,1 -#define XPT_OUTPUT_MODE_DSS3 0x9070000C,11,1 -#define XPT_OUTPUT_MODE_DSS4 0x9070000C,12,1 -#define XPT_OUTPUT_MODE_DSS5 0x9070000C,13,1 -#define XPT_OUTPUT_MODE_DSS6 0x9070000C,14,1 -#define XPT_OUTPUT_MODE_DSS7 0x9070000C,15,1 -#define XPT_OUTPUT_MODE_MUXGATING0 0x90700020,0,1 -#define XPT_OUTPUT_MODE_MUXGATING1 0x90700020,1,1 -#define XPT_OUTPUT_MODE_MUXGATING2 0x90700020,2,1 -#define XPT_OUTPUT_MODE_MUXGATING3 0x90700020,3,1 -#define XPT_OUTPUT_MODE_MUXGATING4 0x90700020,4,1 -#define XPT_OUTPUT_MODE_MUXGATING5 0x90700020,5,1 -#define XPT_OUTPUT_MODE_MUXGATING6 0x90700020,6,1 -#define XPT_OUTPUT_MODE_MUXGATING7 0x90700020,7,1 -#define XPT_OUTPUT_MUXSELECT0 0x9070001C,0,3 -#define XPT_OUTPUT_MUXSELECT1 0x9070001C,4,3 -#define XPT_OUTPUT_MUXSELECT2 0x9070001C,8,3 -#define XPT_OUTPUT_MUXSELECT3 0x9070001C,12,3 -#define XPT_OUTPUT_MUXSELECT4 0x9070001C,16,3 -#define XPT_OUTPUT_MUXSELECT5 0x9070001C,20,3 -#define XPT_PCR_RTS_CORRECTION_ENABLE 0x90700008,14,1 -#define XPT_PID_DEFAULT_DROP0 0x90700190,12,1 -#define XPT_PID_DEFAULT_DROP1 0x90700190,13,1 -#define XPT_PID_DEFAULT_DROP2 0x90700190,14,1 -#define XPT_PID_DEFAULT_DROP3 0x90700190,15,1 -#define XPT_PID_DEFAULT_DROP4 0x907001B0,12,1 -#define XPT_PID_DEFAULT_DROP5 0x907001B0,13,1 -#define XPT_PID_DEFAULT_DROP6 0x907001B0,14,1 -#define XPT_PID_DEFAULT_DROP7 0x907001B0,15,1 -#define XPT_PID_MUX_SELECT0 0x90700190,4,4 -#define XPT_PID_MUX_SELECT1 0x907001B0,4,4 -#define XPT_STREAM_MUXMODE0 0x90700008,0,2 -#define XPT_STREAM_MUXMODE1 0x90700008,2,2 -#define XPT_SYNC_FULL_BYTE0 0x90700010,0,1 -#define XPT_SYNC_FULL_BYTE1 0x90700010,1,1 -#define XPT_SYNC_FULL_BYTE2 0x90700010,2,1 -#define XPT_SYNC_FULL_BYTE3 0x90700010,3,1 -#define XPT_SYNC_FULL_BYTE4 0x90700010,4,1 -#define XPT_SYNC_FULL_BYTE5 0x90700010,5,1 -#define XPT_SYNC_FULL_BYTE6 0x90700010,6,1 -#define XPT_SYNC_FULL_BYTE7 0x90700010,7,1 -#define XPT_SYNC_LOCK_THRESHOLD 0x9070017C,0,8 -#define XPT_SYNC_MISS_THRESHOLD 0x9070017C,8,8 -#define XPT_SYNC_POLARITY0 0x90700010,8,1 -#define XPT_SYNC_POLARITY1 0x90700010,9,1 -#define XPT_SYNC_POLARITY2 0x90700010,10,1 -#define XPT_SYNC_POLARITY3 0x90700010,11,1 -#define XPT_SYNC_POLARITY4 0x90700010,12,1 -#define XPT_SYNC_POLARITY5 0x90700010,13,1 -#define XPT_SYNC_POLARITY6 0x90700010,14,1 -#define XPT_SYNC_POLARITY7 0x90700010,15,1 -#define XPT_TS_CLK_OUT_EN0 0x907001D4,0,1 -#define XPT_TS_CLK_OUT_EN1 0x907001D4,1,1 -#define XPT_TS_CLK_OUT_EN2 0x907001D4,2,1 -#define XPT_TS_CLK_OUT_EN3 0x907001D4,3,1 -#define XPT_TS_CLK_OUT_EN4 0x907001D4,4,1 -#define XPT_TS_CLK_OUT_EN5 0x907001D4,5,1 -#define XPT_TS_CLK_OUT_EN6 0x907001D4,6,1 -#define XPT_TS_CLK_OUT_EN7 0x907001D4,7,1 -#define XPT_TS_CLK_OUT_EN_PARALLEL 0x907001D4,8,1 -#define XPT_TS_CLK_PHASE0 0x90700018,0,3 -#define XPT_TS_CLK_PHASE1 0x90700018,4,3 -#define XPT_TS_CLK_PHASE2 0x90700018,8,3 -#define XPT_TS_CLK_PHASE3 0x90700018,12,3 -#define XPT_TS_CLK_PHASE4 0x90700018,16,3 -#define XPT_TS_CLK_PHASE5 0x90700018,20,3 -#define XPT_TS_CLK_PHASE6 0x90700018,24,3 -#define XPT_TS_CLK_PHASE7 0x90700018,28,3 -#define XPT_VALID_POLARITY0 0x90700014,0,1 -#define XPT_VALID_POLARITY1 0x90700014,1,1 -#define XPT_VALID_POLARITY2 0x90700014,2,1 -#define XPT_VALID_POLARITY3 0x90700014,3,1 -#define XPT_VALID_POLARITY4 0x90700014,4,1 -#define XPT_VALID_POLARITY5 0x90700014,5,1 -#define XPT_VALID_POLARITY6 0x90700014,6,1 -#define XPT_VALID_POLARITY7 0x90700014,7,1 -#define XPT_ZERO_FILL_COUNT 0x90700008,8,6 - -#define XPT_PACKET_GAP_MIN_BASEADDR 0x90700044 -#define XPT_PACKET_GAP_MIN_TIMER XPT_PACKET_GAP_MIN_BASEADDR,0,16 -#define XPT_NCO_COUNT_MIN0 XPT_PACKET_GAP_MIN_BASEADDR,16,8 -#define XPT_NCO_COUNT_BASEADDR 0x90700238 -#define XPT_NCO_COUNT_MIN1 XPT_NCO_COUNT_BASEADDR,0,8 -#define XPT_NCO_COUNT_MIN2 XPT_NCO_COUNT_BASEADDR,8,8 -#define XPT_NCO_COUNT_MIN3 XPT_NCO_COUNT_BASEADDR,16,8 -#define XPT_NCO_COUNT_MIN4 XPT_NCO_COUNT_BASEADDR,24,8 - -#define XPT_NCO_COUNT_BASEADDR1 0x9070023C -#define XPT_NCO_COUNT_MIN5 XPT_NCO_COUNT_BASEADDR1,0,8 -#define XPT_NCO_COUNT_MIN6 XPT_NCO_COUNT_BASEADDR1,8,8 -#define XPT_NCO_COUNT_MIN7 XPT_NCO_COUNT_BASEADDR1,16,8 - -// V2 DigRF status register -#define BB0_DIGRF_CAPT_DONE 0x908000CC,0,1 -#define PRCM_PRCM_CHIP_ID 0x80030000,0,12 - -#define XPT_PID_BASEADDR 0x90708000 -#define XPT_PID_VALID0 XPT_PID_BASEADDR,0,1 -#define XPT_PID_DROP0 XPT_PID_BASEADDR,1,1 -#define XPT_PID_REMAP0 XPT_PID_BASEADDR,2,1 -#define XPT_PID_VALUE0 XPT_PID_BASEADDR,4,13 -#define XPT_PID_MASK0 XPT_PID_BASEADDR,19,13 - -#define XPT_PID_REMAP_BASEADDR 0x90708004 -#define XPT_PID_REMAP_VALUE0 XPT_PID_REMAP_BASEADDR,0,13 -#define XPT_PID_PORT_ID0 XPT_PID_REMAP_BASEADDR,16,3 - -#define XPT_KNOWN_PID_BASEADDR 0x90709000 -#define XPT_KNOWN_PID_VALID0 XPT_KNOWN_PID_BASEADDR,0,1 -#define XPT_KNOWN_PID_DROP0 XPT_KNOWN_PID_BASEADDR,1,1 -#define XPT_KNOWN_PID_REMAP0 XPT_KNOWN_PID_BASEADDR,2,1 -#define XPT_KNOWN_PID_REMAP_VALUE0 XPT_KNOWN_PID_BASEADDR,16,13 - -#define XPT_PID_BASEADDR1 0x9070A000 -#define XPT_PID_VALID1 XPT_PID_BASEADDR1,0,1 -#define XPT_PID_DROP1 XPT_PID_BASEADDR1,1,1 -#define XPT_PID_REMAP1 XPT_PID_BASEADDR1,2,1 -#define XPT_PID_VALUE1 XPT_PID_BASEADDR1,4,13 -#define XPT_PID_MASK1 XPT_PID_BASEADDR1,19,13 - -#define XPT_PID_REMAP_BASEADDR1 0x9070A004 -#define XPT_PID_REMAP_VALUE1 XPT_PID_REMAP_BASEADDR1,0,13 - -#define XPT_KNOWN_PID_BASEADDR1 0x9070B000 -#define XPT_KNOWN_PID_VALID1 XPT_KNOWN_PID_BASEADDR1,0,1 -#define XPT_KNOWN_PID_DROP1 XPT_KNOWN_PID_BASEADDR1,1,1 -#define XPT_KNOWN_PID_REMAP1 XPT_KNOWN_PID_BASEADDR1,2,1 -#define XPT_KNOWN_PID_REMAP_VALUE1 XPT_KNOWN_PID_BASEADDR1,16,13 - -#define XPT_BERT_LOCK_BASEADDR 0x907000B8 -#define XPT_BERT_LOCK_THRESHOLD XPT_BERT_LOCK_BASEADDR,0,8 -#define XPT_BERT_LOCK_WINDOW XPT_BERT_LOCK_BASEADDR,8,8 - -#define XPT_BERT_BASEADDR 0x907000BC -#define XPT_BERT_ENABLE0 XPT_BERT_BASEADDR,0,1 -#define XPT_BERT_ENABLE1 XPT_BERT_BASEADDR,1,1 -#define XPT_BERT_ENABLE2 XPT_BERT_BASEADDR,2,1 -#define XPT_BERT_ENABLE3 XPT_BERT_BASEADDR,3,1 -#define XPT_BERT_ENABLE4 XPT_BERT_BASEADDR,4,1 -#define XPT_BERT_ENABLE5 XPT_BERT_BASEADDR,5,1 -#define XPT_BERT_ENABLE6 XPT_BERT_BASEADDR,6,1 -#define XPT_BERT_ENABLE7 XPT_BERT_BASEADDR,7,1 -#define XPT_BERT_SEQUENCE_PN23_0 XPT_BERT_BASEADDR,8,1 -#define XPT_BERT_SEQUENCE_PN23_1 XPT_BERT_BASEADDR,9,1 -#define XPT_BERT_SEQUENCE_PN23_2 XPT_BERT_BASEADDR,10,1 -#define XPT_BERT_SEQUENCE_PN23_3 XPT_BERT_BASEADDR,11,1 -#define XPT_BERT_SEQUENCE_PN23_4 XPT_BERT_BASEADDR,12,1 -#define XPT_BERT_SEQUENCE_PN23_5 XPT_BERT_BASEADDR,13,1 -#define XPT_BERT_SEQUENCE_PN23_6 XPT_BERT_BASEADDR,14,1 -#define XPT_BERT_SEQUENCE_PN23_7 XPT_BERT_BASEADDR,15,1 -#define XPT_LOCK_RESYNC0 XPT_BERT_BASEADDR,16,1 -#define XPT_LOCK_RESYNC1 XPT_BERT_BASEADDR,17,1 -#define XPT_LOCK_RESYNC2 XPT_BERT_BASEADDR,18,1 -#define XPT_LOCK_RESYNC3 XPT_BERT_BASEADDR,19,1 -#define XPT_LOCK_RESYNC4 XPT_BERT_BASEADDR,20,1 -#define XPT_LOCK_RESYNC5 XPT_BERT_BASEADDR,21,1 -#define XPT_LOCK_RESYNC6 XPT_BERT_BASEADDR,22,1 -#define XPT_LOCK_RESYNC7 XPT_BERT_BASEADDR,23,1 -#define XPT_BERT_DATA_POLARITY0 XPT_BERT_BASEADDR,24,1 -#define XPT_BERT_DATA_POLARITY1 XPT_BERT_BASEADDR,25,1 -#define XPT_BERT_DATA_POLARITY2 XPT_BERT_BASEADDR,26,1 -#define XPT_BERT_DATA_POLARITY3 XPT_BERT_BASEADDR,27,1 -#define XPT_BERT_DATA_POLARITY4 XPT_BERT_BASEADDR,28,1 -#define XPT_BERT_DATA_POLARITY5 XPT_BERT_BASEADDR,29,1 -#define XPT_BERT_DATA_POLARITY6 XPT_BERT_BASEADDR,30,1 -#define XPT_BERT_DATA_POLARITY7 XPT_BERT_BASEADDR,31,1 - -#define XPT_BERT_INVERT_BASEADDR 0x907000C0 -#define XPT_BERT_INVERT_DATA0 XPT_BERT_INVERT_BASEADDR,0,1 -#define XPT_BERT_INVERT_DATA1 XPT_BERT_INVERT_BASEADDR,1,1 -#define XPT_BERT_INVERT_DATA2 XPT_BERT_INVERT_BASEADDR,2,1 -#define XPT_BERT_INVERT_DATA3 XPT_BERT_INVERT_BASEADDR,3,1 -#define XPT_BERT_INVERT_DATA4 XPT_BERT_INVERT_BASEADDR,4,1 -#define XPT_BERT_INVERT_DATA5 XPT_BERT_INVERT_BASEADDR,5,1 -#define XPT_BERT_INVERT_DATA6 XPT_BERT_INVERT_BASEADDR,6,1 -#define XPT_BERT_INVERT_DATA7 XPT_BERT_INVERT_BASEADDR,7,1 -#define XPT_BERT_INVERT_SEQUENCE0 XPT_BERT_INVERT_BASEADDR,8,1 -#define XPT_BERT_INVERT_SEQUENCE1 XPT_BERT_INVERT_BASEADDR,9,1 -#define XPT_BERT_INVERT_SEQUENCE2 XPT_BERT_INVERT_BASEADDR,10,1 -#define XPT_BERT_INVERT_SEQUENCE3 XPT_BERT_INVERT_BASEADDR,11,1 -#define XPT_BERT_INVERT_SEQUENCE4 XPT_BERT_INVERT_BASEADDR,12,1 -#define XPT_BERT_INVERT_SEQUENCE5 XPT_BERT_INVERT_BASEADDR,13,1 -#define XPT_BERT_INVERT_SEQUENCE6 XPT_BERT_INVERT_BASEADDR,14,1 -#define XPT_BERT_INVERT_SEQUENCE7 XPT_BERT_INVERT_BASEADDR,15,1 -#define XPT_BERT_OUTPUT_POLARITY0 XPT_BERT_INVERT_BASEADDR,16,1 -#define XPT_BERT_OUTPUT_POLARITY1 XPT_BERT_INVERT_BASEADDR,17,1 -#define XPT_BERT_OUTPUT_POLARITY2 XPT_BERT_INVERT_BASEADDR,18,1 -#define XPT_BERT_OUTPUT_POLARITY3 XPT_BERT_INVERT_BASEADDR,19,1 -#define XPT_BERT_OUTPUT_POLARITY4 XPT_BERT_INVERT_BASEADDR,20,1 -#define XPT_BERT_OUTPUT_POLARITY5 XPT_BERT_INVERT_BASEADDR,21,1 -#define XPT_BERT_OUTPUT_POLARITY6 XPT_BERT_INVERT_BASEADDR,22,1 -#define XPT_BERT_OUTPUT_POLARITY7 XPT_BERT_INVERT_BASEADDR,23,1 - -#define XPT_BERT_HEADER_BASEADDR 0x907000C4 -#define XPT_BERT_HEADER_MODE0 XPT_BERT_HEADER_BASEADDR,0,2 -#define XPT_BERT_HEADER_MODE1 XPT_BERT_HEADER_BASEADDR,2,2 -#define XPT_BERT_HEADER_MODE2 XPT_BERT_HEADER_BASEADDR,4,2 -#define XPT_BERT_HEADER_MODE3 XPT_BERT_HEADER_BASEADDR,6,2 -#define XPT_BERT_HEADER_MODE4 XPT_BERT_HEADER_BASEADDR,8,2 -#define XPT_BERT_HEADER_MODE5 XPT_BERT_HEADER_BASEADDR,10,2 -#define XPT_BERT_HEADER_MODE6 XPT_BERT_HEADER_BASEADDR,12,2 -#define XPT_BERT_HEADER_MODE7 XPT_BERT_HEADER_BASEADDR,14,2 - -#define XPT_BERT_BASEADDR1 0x907000C8 -#define XPT_BERT_LOCKED0 XPT_BERT_BASEADDR1,0,1 -#define XPT_BERT_LOCKED1 XPT_BERT_BASEADDR1,1,1 -#define XPT_BERT_LOCKED2 XPT_BERT_BASEADDR1,2,1 -#define XPT_BERT_LOCKED3 XPT_BERT_BASEADDR1,3,1 -#define XPT_BERT_LOCKED4 XPT_BERT_BASEADDR1,4,1 -#define XPT_BERT_LOCKED5 XPT_BERT_BASEADDR1,5,1 -#define XPT_BERT_LOCKED6 XPT_BERT_BASEADDR1,6,1 -#define XPT_BERT_LOCKED7 XPT_BERT_BASEADDR1,7,1 -#define XPT_BERT_BIT_COUNT_SAT0 XPT_BERT_BASEADDR1,8,1 -#define XPT_BERT_BIT_COUNT_SAT1 XPT_BERT_BASEADDR1,9,1 -#define XPT_BERT_BIT_COUNT_SAT2 XPT_BERT_BASEADDR1,10,1 -#define XPT_BERT_BIT_COUNT_SAT3 XPT_BERT_BASEADDR1,11,1 -#define XPT_BERT_BIT_COUNT_SAT4 XPT_BERT_BASEADDR1,12,1 -#define XPT_BERT_BIT_COUNT_SAT5 XPT_BERT_BASEADDR1,13,1 -#define XPT_BERT_BIT_COUNT_SAT6 XPT_BERT_BASEADDR1,14,1 -#define XPT_BERT_BIT_COUNT_SAT7 XPT_BERT_BASEADDR1,15,1 - -#define XPT_BERT_BIT_COUNT0_BASEADDR 0x907000CC -#define XPT_BERT_BIT_COUNT0_LO XPT_BERT_BIT_COUNT0_BASEADDR,0,32 - -#define XPT_BERT_BIT_COUNT0_BASEADDR1 0x907000D0 -#define XPT_BERT_BIT_COUNT0_HI XPT_BERT_BIT_COUNT0_BASEADDR1,0,18 - -#define XPT_BERT_BIT_COUNT1_BASEADDR 0x907000D4 -#define XPT_BERT_BIT_COUNT1_LO XPT_BERT_BIT_COUNT1_BASEADDR,0,32 - -#define XPT_BERT_BIT_COUNT1_BASEADDR1 0x907000D8 -#define XPT_BERT_BIT_COUNT1_HI XPT_BERT_BIT_COUNT1_BASEADDR1,0,18 - -#define XPT_BERT_BIT_COUNT2_BASEADDR 0x907000DC -#define XPT_BERT_BIT_COUNT2_LO XPT_BERT_BIT_COUNT2_BASEADDR,0,32 - -#define XPT_BERT_BIT_COUNT2_BASEADDR1 0x907000E0 -#define XPT_BERT_BIT_COUNT2_HI XPT_BERT_BIT_COUNT2_BASEADDR1,0,18 - -#define XPT_BERT_BIT_COUNT3_BASEADDR 0x907000E4 -#define XPT_BERT_BIT_COUNT3_LO XPT_BERT_BIT_COUNT3_BASEADDR,0,32 - -#define XPT_BERT_BIT_COUNT3_BASEADDR1 0x907000E8 -#define XPT_BERT_BIT_COUNT3_HI XPT_BERT_BIT_COUNT3_BASEADDR1,0,18 - -#define XPT_BERT_BIT_COUNT4_BASEADDR 0x907000EC -#define XPT_BERT_BIT_COUNT4_LO XPT_BERT_BIT_COUNT4_BASEADDR,0,32 - -#define XPT_BERT_BIT_COUNT4_BASEADDR1 0x907000F0 -#define XPT_BERT_BIT_COUNT4_HI XPT_BERT_BIT_COUNT4_BASEADDR1,0,18 - -#define XPT_BERT_BIT_COUNT5_BASEADDR 0x907000F4 -#define XPT_BERT_BIT_COUNT5_LO XPT_BERT_BIT_COUNT5_BASEADDR,0,32 - -#define XPT_BERT_BIT_COUNT5_BASEADDR1 0x907000F8 -#define XPT_BERT_BIT_COUNT5_HI XPT_BERT_BIT_COUNT5_BASEADDR1,0,18 - -#define XPT_BERT_BIT_COUNT6_BASEADDR 0x907000FC -#define XPT_BERT_BIT_COUNT6_LO XPT_BERT_BIT_COUNT6_BASEADDR,0,32 - -#define XPT_BERT_BIT_COUNT6_BASEADDR1 0x90700100 -#define XPT_BERT_BIT_COUNT6_HI XPT_BERT_BIT_COUNT6_BASEADDR1,0,18 - -#define XPT_BERT_BIT_COUNT7_BASEADDR 0x90700104 -#define XPT_BERT_BIT_COUNT7_LO XPT_BERT_BIT_COUNT7_BASEADDR,0,32 - -#define XPT_BERT_BIT_COUNT7_BASEADDR1 0x90700108 -#define XPT_BERT_BIT_COUNT7_HI XPT_BERT_BIT_COUNT7_BASEADDR1,0,18 - -#define XPT_BERT_ERR_COUNT0_BASEADDR 0x9070010C -#define XPT_BERT_ERR_COUNT0_LO XPT_BERT_ERR_COUNT0_BASEADDR,0,32 - -#define XPT_BERT_ERR_COUNT0_BASEADDR1 0x90700110 -#define XPT_BERT_ERR_COUNT0_HI XPT_BERT_ERR_COUNT0_BASEADDR1,0,8 - -#define XPT_BERT_ERR_COUNT1_BASEADDR 0x90700114 -#define XPT_BERT_ERR_COUNT1_LO XPT_BERT_ERR_COUNT1_BASEADDR,0,32 - -#define XPT_BERT_ERR_COUNT1_BASEADDR1 0x90700118 -#define XPT_BERT_ERR_COUNT1_HI XPT_BERT_ERR_COUNT1_BASEADDR1,0,8 - -#define XPT_BERT_ERR_COUNT2_BASEADDR 0x9070011C -#define XPT_BERT_ERR_COUNT2_LO XPT_BERT_ERR_COUNT2_BASEADDR,0,32 - -#define XPT_BERT_ERR_COUNT2_BASEADDR1 0x90700120 -#define XPT_BERT_ERR_COUNT2_HI XPT_BERT_ERR_COUNT2_BASEADDR1,0,8 - -#define XPT_BERT_ERR_COUNT3_BASEADDR 0x90700124 -#define XPT_BERT_ERR_COUNT3_LO XPT_BERT_ERR_COUNT3_BASEADDR,0,32 - -#define XPT_BERT_ERR_COUNT3_BASEADDR1 0x90700128 -#define XPT_BERT_ERR_COUNT3_HI XPT_BERT_ERR_COUNT3_BASEADDR1,0,8 - -#define XPT_BERT_ERR_COUNT4_BASEADDR 0x9070012C -#define XPT_BERT_ERR_COUNT4_LO XPT_BERT_ERR_COUNT4_BASEADDR,0,32 - -#define XPT_BERT_ERR_COUNT4_BASEADDR1 0x90700130 -#define XPT_BERT_ERR_COUNT4_HI XPT_BERT_ERR_COUNT4_BASEADDR1,0,8 - -#define XPT_BERT_ERR_COUNT5_BASEADDR 0x90700134 -#define XPT_BERT_ERR_COUNT5_LO XPT_BERT_ERR_COUNT5_BASEADDR,0,32 - -#define XPT_BERT_ERR_COUNT5_BASEADDR1 0x90700138 -#define XPT_BERT_ERR_COUNT5_HI XPT_BERT_ERR_COUNT5_BASEADDR1,0,8 - -#define XPT_BERT_ERR_COUNT6_BASEADDR 0x9070013C -#define XPT_BERT_ERR_COUNT6_LO XPT_BERT_ERR_COUNT6_BASEADDR,0,32 - -#define XPT_BERT_ERR_COUNT6_BASEADDR1 0x90700140 -#define XPT_BERT_ERR_COUNT6_HI XPT_BERT_ERR_COUNT6_BASEADDR1,0,8 - -#define XPT_BERT_ERR_COUNT7_BASEADDR 0x90700144 -#define XPT_BERT_ERR_COUNT7_LO XPT_BERT_ERR_COUNT7_BASEADDR,0,32 - -#define XPT_BERT_ERR_COUNT7_BASEADDR1 0x90700148 -#define XPT_BERT_ERR_COUNT7_HI XPT_BERT_ERR_COUNT7_BASEADDR1,0,8 - -#define XPT_BERT_ERROR_BASEADDR 0x9070014C -#define XPT_BERT_ERROR_INSERT XPT_BERT_ERROR_BASEADDR,0,24 - -#define XPT_BERT_ANALYZER_BASEADDR 0x90700150 -#define XPT_BERT_ANALYZER_ENABLE XPT_BERT_ANALYZER_BASEADDR,0,1 -#define XPT_BERT_ANALYZER_PORT XPT_BERT_ANALYZER_BASEADDR,4,3 -#define XPT_BERT_ANALYZER_ERR_THRES XPT_BERT_ANALYZER_BASEADDR,15,17 - -#define XPT_BERT_ANALYZER_BASEADDR1 0x90700154 -#define XPT_BERT_ANALYZER_START XPT_BERT_ANALYZER_BASEADDR1,0,32 - -#define XPT_BERT_ANALYZER_BASEADDR2 0x90700158 -#define XPT_BERT_ANALYZER_TSTAMP0 XPT_BERT_ANALYZER_BASEADDR2,0,32 - -#define XPT_BERT_ANALYZER_BASEADDR3 0x9070015C -#define XPT_BERT_ANALYZER_TSTAMP1 XPT_BERT_ANALYZER_BASEADDR3,0,32 - -#define XPT_BERT_ANALYZER_BASEADDR4 0x90700160 -#define XPT_BERT_ANALYZER_TSTAMP2 XPT_BERT_ANALYZER_BASEADDR4,0,32 - -#define XPT_BERT_ANALYZER_BASEADDR5 0x90700164 -#define XPT_BERT_ANALYZER_TSTAMP3 XPT_BERT_ANALYZER_BASEADDR5,0,32 - -#define XPT_BERT_ANALYZER_BASEADDR6 0x90700168 -#define XPT_BERT_ANALYZER_TSTAMP4 XPT_BERT_ANALYZER_BASEADDR6,0,32 - -#define XPT_BERT_ANALYZER_BASEADDR7 0x9070016C -#define XPT_BERT_ANALYZER_TSTAMP5 XPT_BERT_ANALYZER_BASEADDR7,0,32 - -#define XPT_BERT_ANALYZER_BASEADDR8 0x90700170 -#define XPT_BERT_ANALYZER_TSTAMP6 XPT_BERT_ANALYZER_BASEADDR8,0,32 - -#define XPT_BERT_ANALYZER_BASEADDR9 0x90700174 -#define XPT_BERT_ANALYZER_TSTAMP7 XPT_BERT_ANALYZER_BASEADDR9,0,32 - -#define XPT_DMD0_BASEADDR 0x9070024C -#define XPT_DMD0_SEL XPT_DMD0_BASEADDR,0,3 -#define XPT_DMD1_SEL XPT_DMD0_BASEADDR,4,3 -#define XPT_DMD2_SEL XPT_DMD0_BASEADDR,8,3 -#define XPT_DMD3_SEL XPT_DMD0_BASEADDR,12,3 -#define XPT_DMD4_SEL XPT_DMD0_BASEADDR,16,3 -#define XPT_DMD5_SEL XPT_DMD0_BASEADDR,20,3 -#define XPT_DMD6_SEL XPT_DMD0_BASEADDR,24,3 -#define XPT_DMD7_SEL XPT_DMD0_BASEADDR,28,3 - -// V2 AGC Gain Freeze & step -#define DBG_ENABLE_DISABLE_AGC (0x3FFFCF60) // 1: DISABLE, 0:ENABLE -#define WB_DFE0_DFE_FB_RF1_BASEADDR 0x903004A4 -#define WB_DFE0_DFE_FB_RF1_BO WB_DFE0_DFE_FB_RF1_BASEADDR,0,3 -#define WB_DFE0_DFE_FB_RF2_BO WB_DFE0_DFE_FB_RF1_BASEADDR,4,4 -#define WB_DFE0_DFE_FB_LNA_BO WB_DFE0_DFE_FB_RF1_BASEADDR,8,2 - -#define WB_DFE1_DFE_FB_RF1_BASEADDR 0x904004A4 -#define WB_DFE1_DFE_FB_RF1_BO WB_DFE1_DFE_FB_RF1_BASEADDR,0,3 -#define WB_DFE1_DFE_FB_RF2_BO WB_DFE1_DFE_FB_RF1_BASEADDR,4,4 -#define WB_DFE1_DFE_FB_LNA_BO WB_DFE1_DFE_FB_RF1_BASEADDR,8,2 - -#define WB_DFE2_DFE_FB_RF1_BASEADDR 0x905004A4 -#define WB_DFE2_DFE_FB_RF1_BO WB_DFE2_DFE_FB_RF1_BASEADDR,0,3 -#define WB_DFE2_DFE_FB_RF2_BO WB_DFE2_DFE_FB_RF1_BASEADDR,4,4 -#define WB_DFE2_DFE_FB_LNA_BO WB_DFE2_DFE_FB_RF1_BASEADDR,8,2 - -#define WB_DFE3_DFE_FB_RF1_BASEADDR 0x906004A4 -#define WB_DFE3_DFE_FB_RF1_BO WB_DFE3_DFE_FB_RF1_BASEADDR,0,3 -#define WB_DFE3_DFE_FB_RF2_BO WB_DFE3_DFE_FB_RF1_BASEADDR,4,4 -#define WB_DFE3_DFE_FB_LNA_BO WB_DFE3_DFE_FB_RF1_BASEADDR,8,2 - -#define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR 0x90200104 -#define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,0,1 -#define AFE_REG_D2A_TA_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,1,1 -#define AFE_REG_D2A_TB_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,2,1 -#define AFE_REG_D2A_TB_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,3,1 -#define AFE_REG_D2A_TC_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,4,1 -#define AFE_REG_D2A_TC_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,5,1 -#define AFE_REG_D2A_TD_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,6,1 -#define AFE_REG_D2A_TD_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,7,1 - -#define AFE_REG_AFE_REG_SPARE_BASEADDR 0x902000A0 -#define AFE_REG_D2A_TA_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR,13,5 - -#define AFE_REG_AFE_REG_SPARE_BASEADDR1 0x902000B4 -#define AFE_REG_D2A_TB_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR1,13,5 - -#define AFE_REG_AFE_REG_SPARE_BASEADDR2 0x902000C4 -#define AFE_REG_D2A_TC_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR2,13,5 - -#define AFE_REG_AFE_REG_SPARE_BASEADDR3 0x902000D4 -#define AFE_REG_D2A_TD_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR3,13,5 - -#define WB_DFE0_DFE_FB_AGC_BASEADDR 0x90300498 -#define WB_DFE0_DFE_FB_AGC_APPLY WB_DFE0_DFE_FB_AGC_BASEADDR,0,1 - -#define WB_DFE1_DFE_FB_AGC_BASEADDR 0x90400498 -#define WB_DFE1_DFE_FB_AGC_APPLY WB_DFE1_DFE_FB_AGC_BASEADDR,0,1 - -#define WB_DFE2_DFE_FB_AGC_BASEADDR 0x90500498 -#define WB_DFE2_DFE_FB_AGC_APPLY WB_DFE2_DFE_FB_AGC_BASEADDR,0,1 - -#define WB_DFE3_DFE_FB_AGC_BASEADDR 0x90600498 -#define WB_DFE3_DFE_FB_AGC_APPLY WB_DFE3_DFE_FB_AGC_BASEADDR,0,1 - -#define WDT_WD_INT_BASEADDR 0x8002000C -#define WDT_WD_INT_STATUS WDT_WD_INT_BASEADDR,0,1 - -#define FSK_TX_FTM_BASEADDR 0x80090000 -#define FSK_TX_FTM_OE FSK_TX_FTM_BASEADDR,12,1 -#define FSK_TX_FTM_TX_EN FSK_TX_FTM_BASEADDR,10,1 -#define FSK_TX_FTM_FORCE_CARRIER_ON FSK_TX_FTM_BASEADDR,1,1 -#define FSK_TX_FTM_FORCE_MARK_SPACE FSK_TX_FTM_BASEADDR,0,1 - -#define FSK_TX_FTM_TX_CNT_BASEADDR 0x80090018 -#define FSK_TX_FTM_TX_CNT_INT FSK_TX_FTM_TX_CNT_BASEADDR,8,4 -#define FSK_TX_FTM_TX_INT_EN FSK_TX_FTM_TX_CNT_BASEADDR,4,1 -#define FSK_TX_FTM_TX_INT_SRC_SEL FSK_TX_FTM_TX_CNT_BASEADDR,0,2 - -#define AFE_REG_D2A_FSK_BIAS_BASEADDR 0x90200040 -#define AFE_REG_D2A_FSK_BIAS_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,0,1 -#define AFE_REG_D2A_FSK_TEST_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,10,1 -#define AFE_REG_D2A_FSK_TEST_MODE AFE_REG_D2A_FSK_BIAS_BASEADDR,11,4 -#define AFE_REG_D2A_FSK_TERM_INT_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,15,1 -#define AFE_REG_D2A_FSK_RESETB_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,16,1 -#define AFE_REG_D2A_FSK_REG_EN_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,17,1 -#define AFE_REG_D2A_FSK_REG_EN_LKG_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,18,1 -#define AFE_REG_D2A_FSK_REG_AMP_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,19,3 -#define AFE_REG_D2A_FSK_REG_TEST_CTRL_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,22,2 -#define AFE_REG_D2A_DSQ_RX_MODE AFE_REG_D2A_FSK_BIAS_BASEADDR,24,1 -#define AFE_REG_D2A_DSQ_RX_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,25,1 -#define AFE_REG_D2A_DSQ_HYST AFE_REG_D2A_FSK_BIAS_BASEADDR,26,2 -#define AFE_REG_D2A_DSQ_RESETB_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,28,1 -#define AFE_REG_D2A_FSK_CLKRX_ENA AFE_REG_D2A_FSK_BIAS_BASEADDR,29,1 - -#define DMD_TEI_BASEADDR 0x3FFFEBE0 -#define DMD_TEI_ENA DMD_TEI_BASEADDR,0,1 - -#define xpt_shm_input_control0 0x90700270,0,8 -#define xpt_shm_input_control1 0x90700270,8,8 -#define xpt_shm_input_control2 0x90700270,16,8 -#define xpt_shm_input_control3 0x90700270,24,8 -#define xpt_shm_input_control4 0x90700274,0,8 -#define xpt_shm_input_control5 0x90700274,8,8 -#define xpt_shm_input_control6 0x90700274,16,8 -#define xpt_shm_input_control7 0x90700274,24,8 - - -#define xpt_shm_output_control0 0x90700278,0,8 -#define xpt_shm_output_control1 0x90700278,8,8 -#define xpt_shm_output_control2 0x90700278,16,8 -#define xpt_shm_output_control3 0x90700278,24,8 -#define xpt_shm_output_control4 0x9070027C,0,8 -#define xpt_shm_output_control5 0x9070027C,8,8 -#define xpt_shm_output_control6 0x9070027C,16,8 -#define xpt_shm_output_control7 0x9070027C,24,8 - -#define xpt_mode_27mhz 0x90700184,0,1 -#define xpt_enable_pcr_count 0x90700184,1,1 - -#define xcpu_ctrl_003c_reg 0x9072003C,0,4 - -#ifdef __cplusplus -} -#endif - -#endif //__MXL58X_REGISTERS_H__ +/* +* Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved +* +* License type: GPLv2 +* +* This program is free software; you can redistribute it and/or modify it under +* the terms of the GNU General Public License as published by the Free Software +* Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA +* +* This program may alternatively be licensed under a proprietary license from +* MaxLinear, Inc. +* +* See terms and conditions defined in file 'LICENSE.txt', which is part of this +* source code package. +*/ + +#ifndef __MXL58X_REGISTERS_H__ +#define __MXL58X_REGISTERS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HYDRA_INTR_STATUS_REG 0x80030008 +#define HYDRA_INTR_MASK_REG 0x8003000C + +#define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 // 0 - 24 MHz & 1 - 27 MHz +#define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 // 0 - 24 MHz & 1 - 27 MHz + +#define HYDRA_CPU_RESET_REG 0x8003003C +#define HYDRA_CPU_RESET_DATA 0x00000400 + +#define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028 +#define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000 + +#define HYDRA_RESET_BBAND_REG 0x80030024 +#define HYDRA_RESET_BBAND_DATA 0x00000000 + +#define HYDRA_RESET_XBAR_REG 0x80030020 +#define HYDRA_RESET_XBAR_DATA 0x00000000 + +#define HYDRA_MODULES_CLK_1_REG 0x80030014 +#define HYDRA_DISABLE_CLK_1 0x00000000 + +#define HYDRA_MODULES_CLK_2_REG 0x8003001C +#define HYDRA_DISABLE_CLK_2 0x0000000B + +#define HYDRA_PRCM_ROOT_CLK_REG 0x80030018 +#define HYDRA_PRCM_ROOT_CLK_DISABLE 0x00000000 + +#define HYDRA_CPU_RESET_CHECK_REG 0x80030008 +#define HYDRA_CPU_RESET_CHECK_OFFSET 0x40000000 // + +#define HYDRA_SKU_ID_REG 0x90000190 + +#define FW_DL_SIGN_ADDR 0x3FFFEAE0 + +// Register to check if FW is running or not +#define HYDRA_HEAR_BEAT 0x3FFFEDDC + +// Firmware version +#define HYDRA_FIRMWARE_VERSION 0x3FFFEDB8 +#define HYDRA_FW_RC_VERSION 0x3FFFCFAC + +// Firmware patch version +#define HYDRA_FIRMWARE_PATCH_VERSION 0x3FFFEDC2 + +// SOC operating temperature in C +#define HYDRA_TEMPARATURE 0x3FFFEDB4 + +// Demod & Tuner status registers +// Demod 0 status base address +#define HYDRA_DEMOD_0_BASE_ADDR 0x3FFFC64C + +// Tuner 0 status base address +#define HYDRA_TUNER_0_BASE_ADDR 0x3FFFCE4C + +#define POWER_FROM_ADCRSSI_READBACK 0x3FFFEB6C + +// Macros to determine base address of respective demod or tuner +#define HYDRA_DMD_STATUS_OFFSET(demodID) ((demodID) * 0x100) +#define HYDRA_TUNER_STATUS_OFFSET(tunerID) ((tunerID) * 0x40) + +// Demod status address offset from respective demod's base address +#define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET 0x3FFFC64C +#define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET 0x3FFFC650 +#define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET 0x3FFFC654 + +#define HYDRA_DMD_STANDARD_ADDR_OFFSET 0x3FFFC658 +#define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET 0x3FFFC65C +#define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET 0x3FFFC660 +#define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET 0x3FFFC664 +#define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET 0x3FFFC668 +#define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET 0x3FFFC66C + +#define HYDRA_DMD_SNR_ADDR_OFFSET 0x3FFFC670 +#define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC674 +#define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC678 +#define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67C +#define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC680 +#define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET 0x3FFFC684 +#define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET 0x3FFFC688 + +#define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET 0x3FFFC68C +#define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET 0x3FFFC68E + +#define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET 0x3FFFC690 +#define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET 0x3FFFC694 +#define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET 0x3FFFC698 + +#define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC69C +#define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6A0 +#define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET 0x3FFFC6A4 +#define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET 0x3FFFC6A8 + +// Debug-purpose DVB-S DMD 0 +#define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6C8 // corrected RS Errors: 1st iteration +#define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6CC // uncorrected RS Errors: 1st iteration +#define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET 0x3FFFC6D0 +#define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET 0x3FFFC6D4 + +#define HYDRA_DMD_TUNER_ID_ADDR_OFFSET 0x3FFFC6AC +#define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET 0x3FFFC6B0 +#define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET 0x3FFFC6B4 +#define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET 0x3FFFC6B8 +#define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR 0x3FFFC704 +#define HYDRA_DMD_STATUS_INPUT_POWER_ADDR 0x3FFFC708 + +// DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information" +#define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR 0x3FFFC710 // DMD 0: 1st iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR +#define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR 0x3FFFC714 // DMD 0: 2nd iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR + +#define DMD0_SPECTRUM_MIN_GAIN_STATUS 0x3FFFC73C +#define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE 0x3FFFC740 +#define DMD0_SPECTRUM_ MIN_GAIN_NB_SAGC_VALUE 0x3FFFC744 + +#define HYDRA_DMD_STATUS_END_ADDR_OFFSET 0x3FFFC748 + +// Tuner status address offset from respective tuners's base address +#define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET 0x3FFFCE4C +#define HYDRA_TUNER_AGC_LOCK_OFFSET 0x3FFFCE50 +#define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET 0x3FFFCE54 +#define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET 0x3FFFCE58 +#define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET 0x3FFFCE5C +#define HYDRA_TUNER_ENABLE_COMPLETE 0x3FFFEB78 + +#define HYDRA_DEMOD_STATUS_LOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES) +#define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO) + +#define HYDRA_TUNER_STATUS_LOCK(devId,tunerId) MxLWare_HYDRA_WriteRegister(devId,(HYDRA_TUNER_STATUS_LOCK_ADDR_OFFSET + HYDRA_TUNER_STATUS_OFFSET(tunerId)), MXL_YES) +#define HYDRA_TUNER_STATUS_UNLOCK(devId,tunerId) MxLWare_HYDRA_WriteRegister(devId,(HYDRA_TUNER_STATUS_LOCK_ADDR_OFFSET + HYDRA_TUNER_STATUS_OFFSET(tunerId)), MXL_NO) + +#define HYDRA_VERSION 0x3FFFEDB8 +#define HYDRA_DEMOD0_VERSION 0x3FFFEDBC +#define HYDRA_DEMOD1_VERSION 0x3FFFEDC0 +#define HYDRA_DEMOD2_VERSION 0x3FFFEDC4 +#define HYDRA_DEMOD3_VERSION 0x3FFFEDC8 +#define HYDRA_DEMOD4_VERSION 0x3FFFEDCC +#define HYDRA_DEMOD5_VERSION 0x3FFFEDD0 +#define HYDRA_DEMOD6_VERSION 0x3FFFEDD4 +#define HYDRA_DEMOD7_VERSION 0x3FFFEDD8 +#define HYDRA_HEAR_BEAT 0x3FFFEDDC +#define HYDRA_SKU_MGMT 0x3FFFEBC0 + +#define MXL_HYDRA_FPGA_A_ADDRESS 0x91C00000 +#define MXL_HYDRA_FPGA_B_ADDRESS 0x91D00000 + +// TS control base address +#define HYDRA_TS_CTRL_BASE_ADDR 0x90700000 + +#define MPEG_MUX_MODE_SLICE0_REG HYDRA_TS_CTRL_BASE_ADDR + 0x08 +#define MPEG_MUX_MODE_SLICE0_OFFSET (0),(2) + +#define MPEG_MUX_MODE_SLICE1_REG HYDRA_TS_CTRL_BASE_ADDR + 0x08 +#define MPEG_MUX_MODE_SLICE1_OFFSET (2),(2) + +#define PID_BANK_SEL_SLICE0_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190 +#define PID_BANK_SEL_SLICE1_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0 + +#define SW_REGULAR_PID_SW_BANK_OFFSET 0,1 +#define SW_FIXED_PID_SW_BANK_OFFSET 1,1 + +#define HW_REGULAR_PID_BANK_OFFSET 8,4 +#define HW_FIXED_PID_BANK_OFFSET 4,4 + +#define MPEG_CLK_GATED_REG HYDRA_TS_CTRL_BASE_ADDR + 0x20 +#define MPEG_CLK_GATED_OFFSET 0,1 + +#define MPEG_CLK_ALWAYS_ON_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1D4 +#define MPEG_CLK_ALWAYS_ON_OFFSET 0,1 + +#define HYDRA_REGULAR_PID_BANK_A_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190 +#define HYDRA_REGULAR_PID_BAN K_A_OFFSET 0,1 + +#define HYDRA_FIXED_PID_BANK_A_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190 +#define HYDRA_FIXED_PID_BANK_A_OFFSET 1,1 + +#define HYDRA_REGULAR_PID_BANK_B_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0 +#define HYDRA_REGULAR_PID_BANK_B_OFFSET 0,1 + +#define HYDRA_FIXED_PID_BANK_B_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0 +#define HYDRA_FIXED_PID_BANK_B_OFFSET 1,1 + +#define FIXED_PID_TBL_REG_ADDRESS_0 HYDRA_TS_CTRL_BASE_ADDR + 0x9000 +#define FIXED_PID_TBL_REG_ADDRESS_1 HYDRA_TS_CTRL_BASE_ADDR + 0x9100 +#define FIXED_PID_TBL_REG_ADDRESS_2 HYDRA_TS_CTRL_BASE_ADDR + 0x9200 +#define FIXED_PID_TBL_REG_ADDRESS_3 HYDRA_TS_CTRL_BASE_ADDR + 0x9300 + +#define FIXED_PID_TBL_REG_ADDRESS_4 HYDRA_TS_CTRL_BASE_ADDR + 0xB000 +#define FIXED_PID_TBL_REG_ADDRESS_5 HYDRA_TS_CTRL_BASE_ADDR + 0xB100 +#define FIXED_PID_TBL_REG_ADDRESS_6 HYDRA_TS_CTRL_BASE_ADDR + 0xB200 +#define FIXED_PID_TBL_REG_ADDRESS_7 HYDRA_TS_CTRL_BASE_ADDR + 0xB300 + +#define REGULAR_PID_TBL_REG_ADDRESS_0 HYDRA_TS_CTRL_BASE_ADDR + 0x8000 +#define REGULAR_PID_TBL_REG_ADDRESS_1 HYDRA_TS_CTRL_BASE_ADDR + 0x8200 +#define REGULAR_PID_TBL_REG_ADDRESS_2 HYDRA_TS_CTRL_BASE_ADDR + 0x8400 +#define REGULAR_PID_TBL_REG_ADDRESS_3 HYDRA_TS_CTRL_BASE_ADDR + 0x8600 + +#define REGULAR_PID_TBL_REG_ADDRESS_4 HYDRA_TS_CTRL_BASE_ADDR + 0xA000 +#define REGULAR_PID_TBL_REG_ADDRESS_5 HYDRA_TS_CTRL_BASE_ADDR + 0xA200 +#define REGULAR_PID_TBL_REG_ADDRESS_6 HYDRA_TS_CTRL_BASE_ADDR + 0xA400 +#define REGULAR_PID_TBL_REG_ADDRESS_7 HYDRA_TS_CTRL_BASE_ADDR + 0xA600 + +#define PID_VALID_OFFSET 0,1 +#define PID_DROP_OFFSET 1,1 +#define PID_REMAP_ENABLE_OFFSET 2,1 +#define PID_VALUE_OFFSET 4,13 +#define PID_MASK_OFFSET 19,13 + +#define REGULAR_PID_REMAP_VALUE_OFFSET 0,13 +#define FIXED_PID_REMAP_VALUE_OFFSET 0,16 +#define PID_DEMODID_OFFSET 16,3 + + +/////////////////////////////////////////////// + +#if 0 +#define AFE_REG_D2A_TA_ADC_CLK_OUT_FLIP 0x90200004,12,1 +#define AFE_REG_D2A_TA_RFFE_LNACAPLOAD_1P8 0x90200028,24,4 +#define AFE_REG_D2A_TA_RFFE_RF1_EN_1P8 0x90200028,5,1 +#define AFE_REG_D2A_TA_RFFE_SPARE_1P8 0x90200028,8,8 +#define AFE_REG_D2A_TB_ADC_CLK_OUT_FLIP 0x9020000C,23,1 +#define AFE_REG_D2A_TB_RFFE_LNACAPLOAD_1P8 0x90200030,16,4 +#define AFE_REG_D2A_TB_RFFE_RF1_EN_1P8 0x9020002C,21,1 +#define AFE_REG_D2A_TB_RFFE_SPARE_1P8 0x90200030,0,8 +#define AFE_REG_D2A_TC_ADC_CLK_OUT_FLIP 0x90200018,7,1 +#define AFE_REG_D2A_TC_RFFE_LNACAPLOAD_1P8 0x90200038,2,4 +#define AFE_REG_D2A_TC_RFFE_RF1_EN_1P8 0x90200034,14,1 +#define AFE_REG_D2A_TC_RFFE_SPARE_1P8 0x90200034,17,8 +#define AFE_REG_D2A_TD_ADC_CLK_OUT_FLIP 0x90200020,18,1 +#define AFE_REG_D2A_TD_RFFE_LNACAPLOAD_1P8 0x9020003C,17,4 +#define AFE_REG_D2A_TD_RFFE_RF1_EN_1P8 0x90200038,29,1 +#define AFE_REG_D2A_TD_RFFE_SPARE_1P8 0x9020003C,1,8 +#endif +#define AFE_REG_D2A_XTAL_EN_CLKOUT_1P8 0x90200054,23,1 + +#define PAD_MUX_TS0_IN_CLK_PINMUX_SEL 0x90000018,0,3 +#define PAD_MUX_TS0_IN_DATA_PINMUX_SEL 0x90000018,4,3 +#define PAD_MUX_TS1_IN_CLK_PINMUX_SEL 0x90000018,8,3 +#define PAD_MUX_TS1_IN_DATA_PINMUX_SEL 0x90000018,12,3 +#define PAD_MUX_TS2_IN_CLK_PINMUX_SEL 0x90000018,16,3 +#define PAD_MUX_TS2_IN_DATA_PINMUX_SEL 0x90000018,20,3 +#define PAD_MUX_TS3_IN_CLK_PINMUX_SEL 0x90000018,24,3 +#define PAD_MUX_TS3_IN_DATA_PINMUX_SEL 0x90000018,28,3 + +#define PAD_MUX_GPIO_00_SYNC_BASEADDR 0x90000188 +#define PAD_MUX_GPIO_01_SYNC_IN PAD_MUX_GPIO_00_SYNC_BASEADDR,1,1 + +#define PRCM_AFE_SOC_ID 0x80030004,24,8 + +#define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C +#define PAD_MUX_UART_RX_C_PINMUX_SEL PAD_MUX_UART_RX_C_PINMUX_BASEADDR,0,3 +#define PAD_MUX_UART_RX_D_PINMUX_SEL PAD_MUX_UART_RX_C_PINMUX_BASEADDR,4,3 +#define PAD_MUX_BOND_OPTION 0x90000190,0,3 +#define PAD_MUX_DIGIO_01_PINMUX_SEL 0x9000016C,4,3 +#define PAD_MUX_DIGIO_02_PINMUX_SEL 0x9000016C,8,3 +#define PAD_MUX_DIGIO_03_PINMUX_SEL 0x9000016C,12,3 +#define PAD_MUX_DIGIO_04_PINMUX_SEL 0x9000016C,16,3 +#define PAD_MUX_DIGIO_05_PINMUX_SEL 0x9000016C,20,3 +#define PAD_MUX_DIGIO_06_PINMUX_SEL 0x9000016C,24,3 +#define PAD_MUX_DIGIO_07_PINMUX_SEL 0x9000016C,28,3 +#define PAD_MUX_DIGIO_08_PINMUX_SEL 0x90000170,0,3 +#define PAD_MUX_DIGIO_09_PINMUX_SEL 0x90000170,4,3 +#define PAD_MUX_DIGIO_10_PINMUX_SEL 0x90000170,8,3 +#define PAD_MUX_DIGIO_11_PINMUX_SEL 0x90000170,12,3 +#define PAD_MUX_DIGIO_12_PINMUX_SEL 0x90000170,16,3 +#define PAD_MUX_DIGIO_13_PINMUX_SEL 0x90000170,20,3 +#define PAD_MUX_DIGIO_14_PINMUX_SEL 0x90000170,24,3 +#define PAD_MUX_DIGIO_15_PINMUX_SEL 0x90000170,28,3 +#define PAD_MUX_DIGIO_16_PINMUX_SEL 0x90000174,0,3 +#define PAD_MUX_DIGIO_17_PINMUX_SEL 0x90000174,4,3 +#define PAD_MUX_DIGIO_18_PINMUX_SEL 0x90000174,8,3 +#define PAD_MUX_DIGIO_19_PINMUX_SEL 0x90000174,12,3 +#define PAD_MUX_DIGIO_20_PINMUX_SEL 0x90000174,16,3 +#define PAD_MUX_DIGIO_21_PINMUX_SEL 0x90000174,20,3 +#define PAD_MUX_DIGIO_22_PINMUX_SEL 0x90000174,24,3 +#define PAD_MUX_DIGIO_23_PINMUX_SEL 0x90000174,28,3 +#define PAD_MUX_DIGIO_24_PINMUX_SEL 0x90000178,0,3 +#define PAD_MUX_DIGIO_25_PINMUX_SEL 0x90000178,4,3 +#define PAD_MUX_DIGIO_26_PINMUX_SEL 0x90000178,8,3 +#define PAD_MUX_DIGIO_27_PINMUX_SEL 0x90000178,12,3 +#define PAD_MUX_DIGIO_28_PINMUX_SEL 0x90000178,16,3 +#define PAD_MUX_DIGIO_29_PINMUX_SEL 0x90000178,20,3 +#define PAD_MUX_DIGIO_30_PINMUX_SEL 0x90000178,24,3 +#define PAD_MUX_DIGIO_31_PINMUX_SEL 0x90000178,28,3 +#define PAD_MUX_DIGIO_32_PINMUX_SEL 0x9000017C,0,3 +#define PAD_MUX_DIGIO_33_PINMUX_SEL 0x9000017C,4,3 +#define PAD_MUX_DIGIO_34_PINMUX_SEL 0x9000017C,8,3 +#define PAD_MUX_EJTAG_TCK_PINMUX_SEL 0x90000020,0,3 +#define PAD_MUX_EJTAG_TDI_PINMUX_SEL 0x90000020,8,3 +#define PAD_MUX_EJTAG_TMS_PINMUX_SEL 0x90000020,4,3 +#define PAD_MUX_EJTAG_TRSTN_PINMUX_SEL 0x90000020,12,3 +#define PAD_MUX_PAD_DRV_DIGIO_00 0x90000194,0,3 +#define PAD_MUX_PAD_DRV_DIGIO_05 0x90000194,20,3 +#define PAD_MUX_PAD_DRV_DIGIO_06 0x90000194,24,3 +#define PAD_MUX_PAD_DRV_DIGIO_11 0x90000198,12,3 +#define PAD_MUX_PAD_DRV_DIGIO_12 0x90000198,16,3 +#define PAD_MUX_PAD_DRV_DIGIO_13 0x90000198,20,3 +#define PAD_MUX_PAD_DRV_DIGIO_14 0x90000198,24,3 +#define PAD_MUX_PAD_DRV_DIGIO_16 0x9000019C,0,3 +#define PAD_MUX_PAD_DRV_DIGIO_17 0x9000019C,4,3 +#define PAD_MUX_PAD_DRV_DIGIO_18 0x9000019C,8,3 +#define PAD_MUX_PAD_DRV_DIGIO_22 0x9000019C,24,3 +#define PAD_MUX_PAD_DRV_DIGIO_23 0x9000019C,28,3 +#define PAD_MUX_PAD_DRV_DIGIO_24 0x900001A0,0,3 +#define PAD_MUX_PAD_DRV_DIGIO_25 0x900001A0,4,3 +#define PAD_MUX_PAD_DRV_DIGIO_29 0x900001A0,20,3 +#define PAD_MUX_PAD_DRV_DIGIO_30 0x900001A0,24,3 +#define PAD_MUX_PAD_DRV_DIGIO_31 0x900001A0,28,3 +#define PRCM_AFE_REG_CLOCK_ENABLE 0x80030014,9,1 +#define PRCM_CHIP_VERSION 0x80030000,12,4 +#define PRCM_AFE_CHIP_MMSK_VER 0x80030004,8,8 +#define PRCM_PRCM_AFE_REG_SOFT_RST_N 0x8003003C,12,1 +#define PRCM_PRCM_CPU_SOFT_RST_N 0x8003003C,0,1 +#define PRCM_PRCM_DIGRF_APB_DATA_BB0 0x80030074,0,20 +#define PRCM_PRCM_DIGRF_APB_DATA_BB1 0x80030078,0,20 +#define PRCM_PRCM_DIGRF_APB_DATA_BB2 0x8003007C,0,20 +#define PRCM_PRCM_DIGRF_APB_DATA_BB3 0x80030080,0,20 +#define PRCM_PRCM_DIGRF_APB_DATA_BB4 0x80030084,0,20 +#define PRCM_PRCM_DIGRF_APB_DATA_BB5 0x80030088,0,20 +#define PRCM_PRCM_DIGRF_APB_DATA_BB6 0x8003008C,0,20 +#define PRCM_PRCM_DIGRF_APB_DATA_BB7 0x80030090,0,20 +#define PRCM_PRCM_DIGRF_CAPT_DONE 0x80030070,24,8 +#define PRCM_PRCM_DIGRF_START_CAPT 0x80030064,2,1 +#define PRCM_PRCM_PAD_MUX_SOFT_RST_N 0x8003003C,11,1 +#define PRCM_PRCM_XPT_PARALLEL_FIFO_RST_N 0x80030028,20,1 +#define XPT_APPEND_BYTES0 0x90700008,4,2 +#define XPT_APPEND_BYTES1 0x90700008,6,2 +#define XPT_CLOCK_POLARITY0 0x90700010,16,1 +#define XPT_CLOCK_POLARITY1 0x90700010,17,1 +#define XPT_CLOCK_POLARITY2 0x90700010,18,1 +#define XPT_CLOCK_POLARITY3 0x90700010,19,1 +#define XPT_CLOCK_POLARITY4 0x90700010,20,1 +#define XPT_CLOCK_POLARITY5 0x90700010,21,1 +#define XPT_CLOCK_POLARITY6 0x90700010,22,1 +#define XPT_CLOCK_POLARITY7 0x90700010,23,1 +#define XPT_DSS_DVB_ENCAP_EN0 0x90700000,16,1 +#define XPT_DSS_DVB_ENCAP_EN1 0x90700000,17,1 +#define XPT_DSS_DVB_ENCAP_EN2 0x90700000,18,1 +#define XPT_DSS_DVB_ENCAP_EN3 0x90700000,19,1 +#define XPT_DSS_DVB_ENCAP_EN4 0x90700000,20,1 +#define XPT_DSS_DVB_ENCAP_EN5 0x90700000,21,1 +#define XPT_DSS_DVB_ENCAP_EN6 0x90700000,22,1 +#define XPT_DSS_DVB_ENCAP_EN7 0x90700000,23,1 +#define XPT_DVB_MATCH_BYTE 0x9070017C,16,8 +#define XPT_DVB_PACKET_SIZE0 0x90700180,0,8 +#define XPT_DVB_PACKET_SIZE1 0x90700180,8,8 +#define XPT_DVB_PACKET_SIZE2 0x90700180,16,8 +#define XPT_DVB_PACKET_SIZE3 0x90700180,24,8 +#define XPT_ENABLE_DVB_INPUT0 0x90700178,0,1 +#define XPT_ENABLE_DVB_INPUT1 0x90700178,1,1 +#define XPT_ENABLE_DVB_INPUT2 0x90700178,2,1 +#define XPT_ENABLE_DVB_INPUT3 0x90700178,3,1 +#define XPT_ENABLE_INPUT0 0x90700000,0,1 +#define XPT_ENABLE_INPUT1 0x90700000,1,1 +#define XPT_ENABLE_INPUT2 0x90700000,2,1 +#define XPT_ENABLE_INPUT3 0x90700000,3,1 +#define XPT_ENABLE_INPUT4 0x90700000,4,1 +#define XPT_ENABLE_INPUT5 0x90700000,5,1 +#define XPT_ENABLE_INPUT6 0x90700000,6,1 +#define XPT_ENABLE_INPUT7 0x90700000,7,1 +#define XPT_ENABLE_OUTPUT0 0x9070000C,0,1 +#define XPT_ENABLE_OUTPUT1 0x9070000C,1,1 +#define XPT_ENABLE_OUTPUT2 0x9070000C,2,1 +#define XPT_ENABLE_OUTPUT3 0x9070000C,3,1 +#define XPT_ENABLE_OUTPUT4 0x9070000C,4,1 +#define XPT_ENABLE_OUTPUT5 0x9070000C,5,1 +#define XPT_ENABLE_OUTPUT6 0x9070000C,6,1 +#define XPT_ENABLE_OUTPUT7 0x9070000C,7,1 +#define XPT_ENABLE_PARALLEL_OUTPUT 0x90700010,27,1 +#define XPT_ENABLE_PCR_COUNT 0x90700184,1,1 +#define XPT_ERROR_REPLACE_SYNC0 0x9070000C,24,1 +#define XPT_ERROR_REPLACE_SYNC1 0x9070000C,25,1 +#define XPT_ERROR_REPLACE_SYNC2 0x9070000C,26,1 +#define XPT_ERROR_REPLACE_SYNC3 0x9070000C,27,1 +#define XPT_ERROR_REPLACE_SYNC4 0x9070000C,28,1 +#define XPT_ERROR_REPLACE_SYNC5 0x9070000C,29,1 +#define XPT_ERROR_REPLACE_SYNC6 0x9070000C,30,1 +#define XPT_ERROR_REPLACE_SYNC7 0x9070000C,31,1 +#define XPT_ERROR_REPLACE_VALID0 0x90700014,8,1 +#define XPT_ERROR_REPLACE_VALID1 0x90700014,9,1 +#define XPT_ERROR_REPLACE_VALID2 0x90700014,10,1 +#define XPT_ERROR_REPLACE_VALID3 0x90700014,11,1 +#define XPT_ERROR_REPLACE_VALID4 0x90700014,12,1 +#define XPT_ERROR_REPLACE_VALID5 0x90700014,13,1 +#define XPT_ERROR_REPLACE_VALID6 0x90700014,14,1 +#define XPT_ERROR_REPLACE_VALID7 0x90700014,15,1 +#define XPT_INP0_MERGE_HDR0 0x90700058,0,32 +#define XPT_INP0_MERGE_HDR1 0x9070005C,0,32 +#define XPT_INP0_MERGE_HDR2 0x90700060,0,32 +#define XPT_INP1_MERGE_HDR0 0x90700064,0,32 +#define XPT_INP1_MERGE_HDR1 0x90700068,0,32 +#define XPT_INP1_MERGE_HDR2 0x9070006C,0,32 +#define XPT_INP2_MERGE_HDR0 0x90700070,0,32 +#define XPT_INP2_MERGE_HDR1 0x90700074,0,32 +#define XPT_INP2_MERGE_HDR2 0x90700078,0,32 +#define XPT_INP3_MERGE_HDR0 0x9070007C,0,32 +#define XPT_INP3_MERGE_HDR1 0x90700080,0,32 +#define XPT_INP3_MERGE_HDR2 0x90700084,0,32 +#define XPT_INP4_MERGE_HDR0 0x90700088,0,32 +#define XPT_INP4_MERGE_HDR1 0x9070008C,0,32 +#define XPT_INP4_MERGE_HDR2 0x90700090,0,32 +#define XPT_INP5_MERGE_HDR0 0x90700094,0,32 +#define XPT_INP5_MERGE_HDR1 0x90700098,0,32 +#define XPT_INP5_MERGE_HDR2 0x9070009C,0,32 +#define XPT_INP6_MERGE_HDR0 0x907000A0,0,32 +#define XPT_INP6_MERGE_HDR1 0x907000A4,0,32 +#define XPT_INP6_MERGE_HDR2 0x907000A8,0,32 +#define XPT_INP7_MERGE_HDR0 0x907000AC,0,32 +#define XPT_INP7_MERGE_HDR1 0x907000B0,0,32 +#define XPT_INP7_MERGE_HDR2 0x907000B4,0,32 +#define XPT_INP_MODE_DSS0 0x90700000,8,1 +#define XPT_INP_MODE_DSS1 0x90700000,9,1 +#define XPT_INP_MODE_DSS2 0x90700000,10,1 +#define XPT_INP_MODE_DSS3 0x90700000,11,1 +#define XPT_INP_MODE_DSS4 0x90700000,12,1 +#define XPT_INP_MODE_DSS5 0x90700000,13,1 +#define XPT_INP_MODE_DSS6 0x90700000,14,1 +#define XPT_INP_MODE_DSS7 0x90700000,15,1 +#define XPT_KNOWN_PID_MUX_SELECT0 0x90700190,8,4 +#define XPT_KNOWN_PID_MUX_SELECT1 0x907001B0,8,4 +#define XPT_LSB_FIRST0 0x9070000C,16,1 +#define XPT_LSB_FIRST1 0x9070000C,17,1 +#define XPT_LSB_FIRST2 0x9070000C,18,1 +#define XPT_LSB_FIRST3 0x9070000C,19,1 +#define XPT_LSB_FIRST4 0x9070000C,20,1 +#define XPT_LSB_FIRST5 0x9070000C,21,1 +#define XPT_LSB_FIRST6 0x9070000C,22,1 +#define XPT_LSB_FIRST7 0x9070000C,23,1 +#define XPT_MODE_27MHZ 0x90700184,0,1 +#define XPT_NCO_COUNT_MIN 0x90700044,16,8 +#define XPT_OUTPUT_MODE_DSS0 0x9070000C,8,1 +#define XPT_OUTPUT_MODE_DSS1 0x9070000C,9,1 +#define XPT_OUTPUT_MODE_DSS2 0x9070000C,10,1 +#define XPT_OUTPUT_MODE_DSS3 0x9070000C,11,1 +#define XPT_OUTPUT_MODE_DSS4 0x9070000C,12,1 +#define XPT_OUTPUT_MODE_DSS5 0x9070000C,13,1 +#define XPT_OUTPUT_MODE_DSS6 0x9070000C,14,1 +#define XPT_OUTPUT_MODE_DSS7 0x9070000C,15,1 +#define XPT_OUTPUT_MODE_MUXGATING0 0x90700020,0,1 +#define XPT_OUTPUT_MODE_MUXGATING1 0x90700020,1,1 +#define XPT_OUTPUT_MODE_MUXGATING2 0x90700020,2,1 +#define XPT_OUTPUT_MODE_MUXGATING3 0x90700020,3,1 +#define XPT_OUTPUT_MODE_MUXGATING4 0x90700020,4,1 +#define XPT_OUTPUT_MODE_MUXGATING5 0x90700020,5,1 +#define XPT_OUTPUT_MODE_MUXGATING6 0x90700020,6,1 +#define XPT_OUTPUT_MODE_MUXGATING7 0x90700020,7,1 +#define XPT_OUTPUT_MUXSELECT0 0x9070001C,0,3 +#define XPT_OUTPUT_MUXSELECT1 0x9070001C,4,3 +#define XPT_OUTPUT_MUXSELECT2 0x9070001C,8,3 +#define XPT_OUTPUT_MUXSELECT3 0x9070001C,12,3 +#define XPT_OUTPUT_MUXSELECT4 0x9070001C,16,3 +#define XPT_OUTPUT_MUXSELECT5 0x9070001C,20,3 +#define XPT_PCR_RTS_CORRECTION_ENABLE 0x90700008,14,1 +#define XPT_PID_DEFAULT_DROP0 0x90700190,12,1 +#define XPT_PID_DEFAULT_DROP1 0x90700190,13,1 +#define XPT_PID_DEFAULT_DROP2 0x90700190,14,1 +#define XPT_PID_DEFAULT_DROP3 0x90700190,15,1 +#define XPT_PID_DEFAULT_DROP4 0x907001B0,12,1 +#define XPT_PID_DEFAULT_DROP5 0x907001B0,13,1 +#define XPT_PID_DEFAULT_DROP6 0x907001B0,14,1 +#define XPT_PID_DEFAULT_DROP7 0x907001B0,15,1 +#define XPT_PID_MUX_SELECT0 0x90700190,4,4 +#define XPT_PID_MUX_SELECT1 0x907001B0,4,4 +#define XPT_STREAM_MUXMODE0 0x90700008,0,2 +#define XPT_STREAM_MUXMODE1 0x90700008,2,2 +#define XPT_SYNC_FULL_BYTE0 0x90700010,0,1 +#define XPT_SYNC_FULL_BYTE1 0x90700010,1,1 +#define XPT_SYNC_FULL_BYTE2 0x90700010,2,1 +#define XPT_SYNC_FULL_BYTE3 0x90700010,3,1 +#define XPT_SYNC_FULL_BYTE4 0x90700010,4,1 +#define XPT_SYNC_FULL_BYTE5 0x90700010,5,1 +#define XPT_SYNC_FULL_BYTE6 0x90700010,6,1 +#define XPT_SYNC_FULL_BYTE7 0x90700010,7,1 +#define XPT_SYNC_LOCK_THRESHOLD 0x9070017C,0,8 +#define XPT_SYNC_MISS_THRESHOLD 0x9070017C,8,8 +#define XPT_SYNC_POLARITY0 0x90700010,8,1 +#define XPT_SYNC_POLARITY1 0x90700010,9,1 +#define XPT_SYNC_POLARITY2 0x90700010,10,1 +#define XPT_SYNC_POLARITY3 0x90700010,11,1 +#define XPT_SYNC_POLARITY4 0x90700010,12,1 +#define XPT_SYNC_POLARITY5 0x90700010,13,1 +#define XPT_SYNC_POLARITY6 0x90700010,14,1 +#define XPT_SYNC_POLARITY7 0x90700010,15,1 +#define XPT_TS_CLK_OUT_EN0 0x907001D4,0,1 +#define XPT_TS_CLK_OUT_EN1 0x907001D4,1,1 +#define XPT_TS_CLK_OUT_EN2 0x907001D4,2,1 +#define XPT_TS_CLK_OUT_EN3 0x907001D4,3,1 +#define XPT_TS_CLK_OUT_EN4 0x907001D4,4,1 +#define XPT_TS_CLK_OUT_EN5 0x907001D4,5,1 +#define XPT_TS_CLK_OUT_EN6 0x907001D4,6,1 +#define XPT_TS_CLK_OUT_EN7 0x907001D4,7,1 +#define XPT_TS_CLK_OUT_EN_PARALLEL 0x907001D4,8,1 +#define XPT_TS_CLK_PHASE0 0x90700018,0,3 +#define XPT_TS_CLK_PHASE1 0x90700018,4,3 +#define XPT_TS_CLK_PHASE2 0x90700018,8,3 +#define XPT_TS_CLK_PHASE3 0x90700018,12,3 +#define XPT_TS_CLK_PHASE4 0x90700018,16,3 +#define XPT_TS_CLK_PHASE5 0x90700018,20,3 +#define XPT_TS_CLK_PHASE6 0x90700018,24,3 +#define XPT_TS_CLK_PHASE7 0x90700018,28,3 +#define XPT_VALID_POLARITY0 0x90700014,0,1 +#define XPT_VALID_POLARITY1 0x90700014,1,1 +#define XPT_VALID_POLARITY2 0x90700014,2,1 +#define XPT_VALID_POLARITY3 0x90700014,3,1 +#define XPT_VALID_POLARITY4 0x90700014,4,1 +#define XPT_VALID_POLARITY5 0x90700014,5,1 +#define XPT_VALID_POLARITY6 0x90700014,6,1 +#define XPT_VALID_POLARITY7 0x90700014,7,1 +#define XPT_ZERO_FILL_COUNT 0x90700008,8,6 + +#define XPT_PACKET_GAP_MIN_BASEADDR 0x90700044 +#define XPT_PACKET_GAP_MIN_TIMER XPT_PACKET_GAP_MIN_BASEADDR,0,16 +#define XPT_NCO_COUNT_MIN0 XPT_PACKET_GAP_MIN_BASEADDR,16,8 +#define XPT_NCO_COUNT_BASEADDR 0x90700238 +#define XPT_NCO_COUNT_MIN1 XPT_NCO_COUNT_BASEADDR,0,8 +#define XPT_NCO_COUNT_MIN2 XPT_NCO_COUNT_BASEADDR,8,8 +#define XPT_NCO_COUNT_MIN3 XPT_NCO_COUNT_BASEADDR,16,8 +#define XPT_NCO_COUNT_MIN4 XPT_NCO_COUNT_BASEADDR,24,8 + +#define XPT_NCO_COUNT_BASEADDR1 0x9070023C +#define XPT_NCO_COUNT_MIN5 XPT_NCO_COUNT_BASEADDR1,0,8 +#define XPT_NCO_COUNT_MIN6 XPT_NCO_COUNT_BASEADDR1,8,8 +#define XPT_NCO_COUNT_MIN7 XPT_NCO_COUNT_BASEADDR1,16,8 + +// V2 DigRF status register +#define BB0_DIGRF_CAPT_DONE 0x908000CC,0,1 +#define PRCM_PRCM_CHIP_ID 0x80030000,0,12 + +#define XPT_PID_BASEADDR 0x90708000 +#define XPT_PID_VALID0 XPT_PID_BASEADDR,0,1 +#define XPT_PID_DROP0 XPT_PID_BASEADDR,1,1 +#define XPT_PID_REMAP0 XPT_PID_BASEADDR,2,1 +#define XPT_PID_VALUE0 XPT_PID_BASEADDR,4,13 +#define XPT_PID_MASK0 XPT_PID_BASEADDR,19,13 + +#define XPT_PID_REMAP_BASEADDR 0x90708004 +#define XPT_PID_REMAP_VALUE0 XPT_PID_REMAP_BASEADDR,0,13 +#define XPT_PID_PORT_ID0 XPT_PID_REMAP_BASEADDR,16,3 + +#define XPT_KNOWN_PID_BASEADDR 0x90709000 +#define XPT_KNOWN_PID_VALID0 XPT_KNOWN_PID_BASEADDR,0,1 +#define XPT_KNOWN_PID_DROP0 XPT_KNOWN_PID_BASEADDR,1,1 +#define XPT_KNOWN_PID_REMAP0 XPT_KNOWN_PID_BASEADDR,2,1 +#define XPT_KNOWN_PID_REMAP_VALUE0 XPT_KNOWN_PID_BASEADDR,16,13 + +#define XPT_PID_BASEADDR1 0x9070A000 +#define XPT_PID_VALID1 XPT_PID_BASEADDR1,0,1 +#define XPT_PID_DROP1 XPT_PID_BASEADDR1,1,1 +#define XPT_PID_REMAP1 XPT_PID_BASEADDR1,2,1 +#define XPT_PID_VALUE1 XPT_PID_BASEADDR1,4,13 +#define XPT_PID_MASK1 XPT_PID_BASEADDR1,19,13 + +#define XPT_PID_REMAP_BASEADDR1 0x9070A004 +#define XPT_PID_REMAP_VALUE1 XPT_PID_REMAP_BASEADDR1,0,13 + +#define XPT_KNOWN_PID_BASEADDR1 0x9070B000 +#define XPT_KNOWN_PID_VALID1 XPT_KNOWN_PID_BASEADDR1,0,1 +#define XPT_KNOWN_PID_DROP1 XPT_KNOWN_PID_BASEADDR1,1,1 +#define XPT_KNOWN_PID_REMAP1 XPT_KNOWN_PID_BASEADDR1,2,1 +#define XPT_KNOWN_PID_REMAP_VALUE1 XPT_KNOWN_PID_BASEADDR1,16,13 + +#define XPT_BERT_LOCK_BASEADDR 0x907000B8 +#define XPT_BERT_LOCK_THRESHOLD XPT_BERT_LOCK_BASEADDR,0,8 +#define XPT_BERT_LOCK_WINDOW XPT_BERT_LOCK_BASEADDR,8,8 + +#define XPT_BERT_BASEADDR 0x907000BC +#define XPT_BERT_ENABLE0 XPT_BERT_BASEADDR,0,1 +#define XPT_BERT_ENABLE1 XPT_BERT_BASEADDR,1,1 +#define XPT_BERT_ENABLE2 XPT_BERT_BASEADDR,2,1 +#define XPT_BERT_ENABLE3 XPT_BERT_BASEADDR,3,1 +#define XPT_BERT_ENABLE4 XPT_BERT_BASEADDR,4,1 +#define XPT_BERT_ENABLE5 XPT_BERT_BASEADDR,5,1 +#define XPT_BERT_ENABLE6 XPT_BERT_BASEADDR,6,1 +#define XPT_BERT_ENABLE7 XPT_BERT_BASEADDR,7,1 +#define XPT_BERT_SEQUENCE_PN23_0 XPT_BERT_BASEADDR,8,1 +#define XPT_BERT_SEQUENCE_PN23_1 XPT_BERT_BASEADDR,9,1 +#define XPT_BERT_SEQUENCE_PN23_2 XPT_BERT_BASEADDR,10,1 +#define XPT_BERT_SEQUENCE_PN23_3 XPT_BERT_BASEADDR,11,1 +#define XPT_BERT_SEQUENCE_PN23_4 XPT_BERT_BASEADDR,12,1 +#define XPT_BERT_SEQUENCE_PN23_5 XPT_BERT_BASEADDR,13,1 +#define XPT_BERT_SEQUENCE_PN23_6 XPT_BERT_BASEADDR,14,1 +#define XPT_BERT_SEQUENCE_PN23_7 XPT_BERT_BASEADDR,15,1 +#define XPT_LOCK_RESYNC0 XPT_BERT_BASEADDR,16,1 +#define XPT_LOCK_RESYNC1 XPT_BERT_BASEADDR,17,1 +#define XPT_LOCK_RESYNC2 XPT_BERT_BASEADDR,18,1 +#define XPT_LOCK_RESYNC3 XPT_BERT_BASEADDR,19,1 +#define XPT_LOCK_RESYNC4 XPT_BERT_BASEADDR,20,1 +#define XPT_LOCK_RESYNC5 XPT_BERT_BASEADDR,21,1 +#define XPT_LOCK_RESYNC6 XPT_BERT_BASEADDR,22,1 +#define XPT_LOCK_RESYNC7 XPT_BERT_BASEADDR,23,1 +#define XPT_BERT_DATA_POLARITY0 XPT_BERT_BASEADDR,24,1 +#define XPT_BERT_DATA_POLARITY1 XPT_BERT_BASEADDR,25,1 +#define XPT_BERT_DATA_POLARITY2 XPT_BERT_BASEADDR,26,1 +#define XPT_BERT_DATA_POLARITY3 XPT_BERT_BASEADDR,27,1 +#define XPT_BERT_DATA_POLARITY4 XPT_BERT_BASEADDR,28,1 +#define XPT_BERT_DATA_POLARITY5 XPT_BERT_BASEADDR,29,1 +#define XPT_BERT_DATA_POLARITY6 XPT_BERT_BASEADDR,30,1 +#define XPT_BERT_DATA_POLARITY7 XPT_BERT_BASEADDR,31,1 + +#define XPT_BERT_INVERT_BASEADDR 0x907000C0 +#define XPT_BERT_INVERT_DATA0 XPT_BERT_INVERT_BASEADDR,0,1 +#define XPT_BERT_INVERT_DATA1 XPT_BERT_INVERT_BASEADDR,1,1 +#define XPT_BERT_INVERT_DATA2 XPT_BERT_INVERT_BASEADDR,2,1 +#define XPT_BERT_INVERT_DATA3 XPT_BERT_INVERT_BASEADDR,3,1 +#define XPT_BERT_INVERT_DATA4 XPT_BERT_INVERT_BASEADDR,4,1 +#define XPT_BERT_INVERT_DATA5 XPT_BERT_INVERT_BASEADDR,5,1 +#define XPT_BERT_INVERT_DATA6 XPT_BERT_INVERT_BASEADDR,6,1 +#define XPT_BERT_INVERT_DATA7 XPT_BERT_INVERT_BASEADDR,7,1 +#define XPT_BERT_INVERT_SEQUENCE0 XPT_BERT_INVERT_BASEADDR,8,1 +#define XPT_BERT_INVERT_SEQUENCE1 XPT_BERT_INVERT_BASEADDR,9,1 +#define XPT_BERT_INVERT_SEQUENCE2 XPT_BERT_INVERT_BASEADDR,10,1 +#define XPT_BERT_INVERT_SEQUENCE3 XPT_BERT_INVERT_BASEADDR,11,1 +#define XPT_BERT_INVERT_SEQUENCE4 XPT_BERT_INVERT_BASEADDR,12,1 +#define XPT_BERT_INVERT_SEQUENCE5 XPT_BERT_INVERT_BASEADDR,13,1 +#define XPT_BERT_INVERT_SEQUENCE6 XPT_BERT_INVERT_BASEADDR,14,1 +#define XPT_BERT_INVERT_SEQUENCE7 XPT_BERT_INVERT_BASEADDR,15,1 +#define XPT_BERT_OUTPUT_POLARITY0 XPT_BERT_INVERT_BASEADDR,16,1 +#define XPT_BERT_OUTPUT_POLARITY1 XPT_BERT_INVERT_BASEADDR,17,1 +#define XPT_BERT_OUTPUT_POLARITY2 XPT_BERT_INVERT_BASEADDR,18,1 +#define XPT_BERT_OUTPUT_POLARITY3 XPT_BERT_INVERT_BASEADDR,19,1 +#define XPT_BERT_OUTPUT_POLARITY4 XPT_BERT_INVERT_BASEADDR,20,1 +#define XPT_BERT_OUTPUT_POLARITY5 XPT_BERT_INVERT_BASEADDR,21,1 +#define XPT_BERT_OUTPUT_POLARITY6 XPT_BERT_INVERT_BASEADDR,22,1 +#define XPT_BERT_OUTPUT_POLARITY7 XPT_BERT_INVERT_BASEADDR,23,1 + +#define XPT_BERT_HEADER_BASEADDR 0x907000C4 +#define XPT_BERT_HEADER_MODE0 XPT_BERT_HEADER_BASEADDR,0,2 +#define XPT_BERT_HEADER_MODE1 XPT_BERT_HEADER_BASEADDR,2,2 +#define XPT_BERT_HEADER_MODE2 XPT_BERT_HEADER_BASEADDR,4,2 +#define XPT_BERT_HEADER_MODE3 XPT_BERT_HEADER_BASEADDR,6,2 +#define XPT_BERT_HEADER_MODE4 XPT_BERT_HEADER_BASEADDR,8,2 +#define XPT_BERT_HEADER_MODE5 XPT_BERT_HEADER_BASEADDR,10,2 +#define XPT_BERT_HEADER_MODE6 XPT_BERT_HEADER_BASEADDR,12,2 +#define XPT_BERT_HEADER_MODE7 XPT_BERT_HEADER_BASEADDR,14,2 + +#define XPT_BERT_BASEADDR1 0x907000C8 +#define XPT_BERT_LOCKED0 XPT_BERT_BASEADDR1,0,1 +#define XPT_BERT_LOCKED1 XPT_BERT_BASEADDR1,1,1 +#define XPT_BERT_LOCKED2 XPT_BERT_BASEADDR1,2,1 +#define XPT_BERT_LOCKED3 XPT_BERT_BASEADDR1,3,1 +#define XPT_BERT_LOCKED4 XPT_BERT_BASEADDR1,4,1 +#define XPT_BERT_LOCKED5 XPT_BERT_BASEADDR1,5,1 +#define XPT_BERT_LOCKED6 XPT_BERT_BASEADDR1,6,1 +#define XPT_BERT_LOCKED7 XPT_BERT_BASEADDR1,7,1 +#define XPT_BERT_BIT_COUNT_SAT0 XPT_BERT_BASEADDR1,8,1 +#define XPT_BERT_BIT_COUNT_SAT1 XPT_BERT_BASEADDR1,9,1 +#define XPT_BERT_BIT_COUNT_SAT2 XPT_BERT_BASEADDR1,10,1 +#define XPT_BERT_BIT_COUNT_SAT3 XPT_BERT_BASEADDR1,11,1 +#define XPT_BERT_BIT_COUNT_SAT4 XPT_BERT_BASEADDR1,12,1 +#define XPT_BERT_BIT_COUNT_SAT5 XPT_BERT_BASEADDR1,13,1 +#define XPT_BERT_BIT_COUNT_SAT6 XPT_BERT_BASEADDR1,14,1 +#define XPT_BERT_BIT_COUNT_SAT7 XPT_BERT_BASEADDR1,15,1 + +#define XPT_BERT_BIT_COUNT0_BASEADDR 0x907000CC +#define XPT_BERT_BIT_COUNT0_LO XPT_BERT_BIT_COUNT0_BASEADDR,0,32 + +#define XPT_BERT_BIT_COUNT0_BASEADDR1 0x907000D0 +#define XPT_BERT_BIT_COUNT0_HI XPT_BERT_BIT_COUNT0_BASEADDR1,0,18 + +#define XPT_BERT_BIT_COUNT1_BASEADDR 0x907000D4 +#define XPT_BERT_BIT_COUNT1_LO XPT_BERT_BIT_COUNT1_BASEADDR,0,32 + +#define XPT_BERT_BIT_COUNT1_BASEADDR1 0x907000D8 +#define XPT_BERT_BIT_COUNT1_HI XPT_BERT_BIT_COUNT1_BASEADDR1,0,18 + +#define XPT_BERT_BIT_COUNT2_BASEADDR 0x907000DC +#define XPT_BERT_BIT_COUNT2_LO XPT_BERT_BIT_COUNT2_BASEADDR,0,32 + +#define XPT_BERT_BIT_COUNT2_BASEADDR1 0x907000E0 +#define XPT_BERT_BIT_COUNT2_HI XPT_BERT_BIT_COUNT2_BASEADDR1,0,18 + +#define XPT_BERT_BIT_COUNT3_BASEADDR 0x907000E4 +#define XPT_BERT_BIT_COUNT3_LO XPT_BERT_BIT_COUNT3_BASEADDR,0,32 + +#define XPT_BERT_BIT_COUNT3_BASEADDR1 0x907000E8 +#define XPT_BERT_BIT_COUNT3_HI XPT_BERT_BIT_COUNT3_BASEADDR1,0,18 + +#define XPT_BERT_BIT_COUNT4_BASEADDR 0x907000EC +#define XPT_BERT_BIT_COUNT4_LO XPT_BERT_BIT_COUNT4_BASEADDR,0,32 + +#define XPT_BERT_BIT_COUNT4_BASEADDR1 0x907000F0 +#define XPT_BERT_BIT_COUNT4_HI XPT_BERT_BIT_COUNT4_BASEADDR1,0,18 + +#define XPT_BERT_BIT_COUNT5_BASEADDR 0x907000F4 +#define XPT_BERT_BIT_COUNT5_LO XPT_BERT_BIT_COUNT5_BASEADDR,0,32 + +#define XPT_BERT_BIT_COUNT5_BASEADDR1 0x907000F8 +#define XPT_BERT_BIT_COUNT5_HI XPT_BERT_BIT_COUNT5_BASEADDR1,0,18 + +#define XPT_BERT_BIT_COUNT6_BASEADDR 0x907000FC +#define XPT_BERT_BIT_COUNT6_LO XPT_BERT_BIT_COUNT6_BASEADDR,0,32 + +#define XPT_BERT_BIT_COUNT6_BASEADDR1 0x90700100 +#define XPT_BERT_BIT_COUNT6_HI XPT_BERT_BIT_COUNT6_BASEADDR1,0,18 + +#define XPT_BERT_BIT_COUNT7_BASEADDR 0x90700104 +#define XPT_BERT_BIT_COUNT7_LO XPT_BERT_BIT_COUNT7_BASEADDR,0,32 + +#define XPT_BERT_BIT_COUNT7_BASEADDR1 0x90700108 +#define XPT_BERT_BIT_COUNT7_HI XPT_BERT_BIT_COUNT7_BASEADDR1,0,18 + +#define XPT_BERT_ERR_COUNT0_BASEADDR 0x9070010C +#define XPT_BERT_ERR_COUNT0_LO XPT_BERT_ERR_COUNT0_BASEADDR,0,32 + +#define XPT_BERT_ERR_COUNT0_BASEADDR1 0x90700110 +#define XPT_BERT_ERR_COUNT0_HI XPT_BERT_ERR_COUNT0_BASEADDR1,0,8 + +#define XPT_BERT_ERR_COUNT1_BASEADDR 0x90700114 +#define XPT_BERT_ERR_COUNT1_LO XPT_BERT_ERR_COUNT1_BASEADDR,0,32 + +#define XPT_BERT_ERR_COUNT1_BASEADDR1 0x90700118 +#define XPT_BERT_ERR_COUNT1_HI XPT_BERT_ERR_COUNT1_BASEADDR1,0,8 + +#define XPT_BERT_ERR_COUNT2_BASEADDR 0x9070011C +#define XPT_BERT_ERR_COUNT2_LO XPT_BERT_ERR_COUNT2_BASEADDR,0,32 + +#define XPT_BERT_ERR_COUNT2_BASEADDR1 0x90700120 +#define XPT_BERT_ERR_COUNT2_HI XPT_BERT_ERR_COUNT2_BASEADDR1,0,8 + +#define XPT_BERT_ERR_COUNT3_BASEADDR 0x90700124 +#define XPT_BERT_ERR_COUNT3_LO XPT_BERT_ERR_COUNT3_BASEADDR,0,32 + +#define XPT_BERT_ERR_COUNT3_BASEADDR1 0x90700128 +#define XPT_BERT_ERR_COUNT3_HI XPT_BERT_ERR_COUNT3_BASEADDR1,0,8 + +#define XPT_BERT_ERR_COUNT4_BASEADDR 0x9070012C +#define XPT_BERT_ERR_COUNT4_LO XPT_BERT_ERR_COUNT4_BASEADDR,0,32 + +#define XPT_BERT_ERR_COUNT4_BASEADDR1 0x90700130 +#define XPT_BERT_ERR_COUNT4_HI XPT_BERT_ERR_COUNT4_BASEADDR1,0,8 + +#define XPT_BERT_ERR_COUNT5_BASEADDR 0x90700134 +#define XPT_BERT_ERR_COUNT5_LO XPT_BERT_ERR_COUNT5_BASEADDR,0,32 + +#define XPT_BERT_ERR_COUNT5_BASEADDR1 0x90700138 +#define XPT_BERT_ERR_COUNT5_HI XPT_BERT_ERR_COUNT5_BASEADDR1,0,8 + +#define XPT_BERT_ERR_COUNT6_BASEADDR 0x9070013C +#define XPT_BERT_ERR_COUNT6_LO XPT_BERT_ERR_COUNT6_BASEADDR,0,32 + +#define XPT_BERT_ERR_COUNT6_BASEADDR1 0x90700140 +#define XPT_BERT_ERR_COUNT6_HI XPT_BERT_ERR_COUNT6_BASEADDR1,0,8 + +#define XPT_BERT_ERR_COUNT7_BASEADDR 0x90700144 +#define XPT_BERT_ERR_COUNT7_LO XPT_BERT_ERR_COUNT7_BASEADDR,0,32 + +#define XPT_BERT_ERR_COUNT7_BASEADDR1 0x90700148 +#define XPT_BERT_ERR_COUNT7_HI XPT_BERT_ERR_COUNT7_BASEADDR1,0,8 + +#define XPT_BERT_ERROR_BASEADDR 0x9070014C +#define XPT_BERT_ERROR_INSERT XPT_BERT_ERROR_BASEADDR,0,24 + +#define XPT_BERT_ANALYZER_BASEADDR 0x90700150 +#define XPT_BERT_ANALYZER_ENABLE XPT_BERT_ANALYZER_BASEADDR,0,1 +#define XPT_BERT_ANALYZER_PORT XPT_BERT_ANALYZER_BASEADDR,4,3 +#define XPT_BERT_ANALYZER_ERR_THRES XPT_BERT_ANALYZER_BASEADDR,15,17 + +#define XPT_BERT_ANALYZER_BASEADDR1 0x90700154 +#define XPT_BERT_ANALYZER_START XPT_BERT_ANALYZER_BASEADDR1,0,32 + +#define XPT_BERT_ANALYZER_BASEADDR2 0x90700158 +#define XPT_BERT_ANALYZER_TSTAMP0 XPT_BERT_ANALYZER_BASEADDR2,0,32 + +#define XPT_BERT_ANALYZER_BASEADDR3 0x9070015C +#define XPT_BERT_ANALYZER_TSTAMP1 XPT_BERT_ANALYZER_BASEADDR3,0,32 + +#define XPT_BERT_ANALYZER_BASEADDR4 0x90700160 +#define XPT_BERT_ANALYZER_TSTAMP2 XPT_BERT_ANALYZER_BASEADDR4,0,32 + +#define XPT_BERT_ANALYZER_BASEADDR5 0x90700164 +#define XPT_BERT_ANALYZER_TSTAMP3 XPT_BERT_ANALYZER_BASEADDR5,0,32 + +#define XPT_BERT_ANALYZER_BASEADDR6 0x90700168 +#define XPT_BERT_ANALYZER_TSTAMP4 XPT_BERT_ANALYZER_BASEADDR6,0,32 + +#define XPT_BERT_ANALYZER_BASEADDR7 0x9070016C +#define XPT_BERT_ANALYZER_TSTAMP5 XPT_BERT_ANALYZER_BASEADDR7,0,32 + +#define XPT_BERT_ANALYZER_BASEADDR8 0x90700170 +#define XPT_BERT_ANALYZER_TSTAMP6 XPT_BERT_ANALYZER_BASEADDR8,0,32 + +#define XPT_BERT_ANALYZER_BASEADDR9 0x90700174 +#define XPT_BERT_ANALYZER_TSTAMP7 XPT_BERT_ANALYZER_BASEADDR9,0,32 + +#define XPT_DMD0_BASEADDR 0x9070024C +#define XPT_DMD0_SEL XPT_DMD0_BASEADDR,0,3 +#define XPT_DMD1_SEL XPT_DMD0_BASEADDR,4,3 +#define XPT_DMD2_SEL XPT_DMD0_BASEADDR,8,3 +#define XPT_DMD3_SEL XPT_DMD0_BASEADDR,12,3 +#define XPT_DMD4_SEL XPT_DMD0_BASEADDR,16,3 +#define XPT_DMD5_SEL XPT_DMD0_BASEADDR,20,3 +#define XPT_DMD6_SEL XPT_DMD0_BASEADDR,24,3 +#define XPT_DMD7_SEL XPT_DMD0_BASEADDR,28,3 + +// V2 AGC Gain Freeze & step +#define DBG_ENABLE_DISABLE_AGC (0x3FFFCF60) // 1: DISABLE, 0:ENABLE +#define WB_DFE0_DFE_FB_RF1_BASEADDR 0x903004A4 +#define WB_DFE0_DFE_FB_RF1_BO WB_DFE0_DFE_FB_RF1_BASEADDR,0,3 +#define WB_DFE0_DFE_FB_RF2_BO WB_DFE0_DFE_FB_RF1_BASEADDR,4,4 +#define WB_DFE0_DFE_FB_LNA_BO WB_DFE0_DFE_FB_RF1_BASEADDR,8,2 + +#define WB_DFE1_DFE_FB_RF1_BASEADDR 0x904004A4 +#define WB_DFE1_DFE_FB_RF1_BO WB_DFE1_DFE_FB_RF1_BASEADDR,0,3 +#define WB_DFE1_DFE_FB_RF2_BO WB_DFE1_DFE_FB_RF1_BASEADDR,4,4 +#define WB_DFE1_DFE_FB_LNA_BO WB_DFE1_DFE_FB_RF1_BASEADDR,8,2 + +#define WB_DFE2_DFE_FB_RF1_BASEADDR 0x905004A4 +#define WB_DFE2_DFE_FB_RF1_BO WB_DFE2_DFE_FB_RF1_BASEADDR,0,3 +#define WB_DFE2_DFE_FB_RF2_BO WB_DFE2_DFE_FB_RF1_BASEADDR,4,4 +#define WB_DFE2_DFE_FB_LNA_BO WB_DFE2_DFE_FB_RF1_BASEADDR,8,2 + +#define WB_DFE3_DFE_FB_RF1_BASEADDR 0x906004A4 +#define WB_DFE3_DFE_FB_RF1_BO WB_DFE3_DFE_FB_RF1_BASEADDR,0,3 +#define WB_DFE3_DFE_FB_RF2_BO WB_DFE3_DFE_FB_RF1_BASEADDR,4,4 +#define WB_DFE3_DFE_FB_LNA_BO WB_DFE3_DFE_FB_RF1_BASEADDR,8,2 + +#define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR 0x90200104 +#define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,0,1 +#define AFE_REG_D2A_TA_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,1,1 +#define AFE_REG_D2A_TB_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,2,1 +#define AFE_REG_D2A_TB_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,3,1 +#define AFE_REG_D2A_TC_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,4,1 +#define AFE_REG_D2A_TC_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,5,1 +#define AFE_REG_D2A_TD_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,6,1 +#define AFE_REG_D2A_TD_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,7,1 + +#define AFE_REG_AFE_REG_SPARE_BASEADDR 0x902000A0 +#define AFE_REG_D2A_TA_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR,13,5 + +#define AFE_REG_AFE_REG_SPARE_BASEADDR1 0x902000B4 +#define AFE_REG_D2A_TB_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR1,13,5 + +#define AFE_REG_AFE_REG_SPARE_BASEADDR2 0x902000C4 +#define AFE_REG_D2A_TC_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR2,13,5 + +#define AFE_REG_AFE_REG_SPARE_BASEADDR3 0x902000D4 +#define AFE_REG_D2A_TD_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR3,13,5 + +#define WB_DFE0_DFE_FB_AGC_BASEADDR 0x90300498 +#define WB_DFE0_DFE_FB_AGC_APPLY WB_DFE0_DFE_FB_AGC_BASEADDR,0,1 + +#define WB_DFE1_DFE_FB_AGC_BASEADDR 0x90400498 +#define WB_DFE1_DFE_FB_AGC_APPLY WB_DFE1_DFE_FB_AGC_BASEADDR,0,1 + +#define WB_DFE2_DFE_FB_AGC_BASEADDR 0x90500498 +#define WB_DFE2_DFE_FB_AGC_APPLY WB_DFE2_DFE_FB_AGC_BASEADDR,0,1 + +#define WB_DFE3_DFE_FB_AGC_BASEADDR 0x90600498 +#define WB_DFE3_DFE_FB_AGC_APPLY WB_DFE3_DFE_FB_AGC_BASEADDR,0,1 + +#define WDT_WD_INT_BASEADDR 0x8002000C +#define WDT_WD_INT_STATUS WDT_WD_INT_BASEADDR,0,1 + +#define FSK_TX_FTM_BASEADDR 0x80090000 +#define FSK_TX_FTM_OE FSK_TX_FTM_BASEADDR,12,1 +#define FSK_TX_FTM_TX_EN FSK_TX_FTM_BASEADDR,10,1 +#define FSK_TX_FTM_FORCE_CARRIER_ON FSK_TX_FTM_BASEADDR,1,1 +#define FSK_TX_FTM_FORCE_MARK_SPACE FSK_TX_FTM_BASEADDR,0,1 + +#define FSK_TX_FTM_TX_CNT_BASEADDR 0x80090018 +#define FSK_TX_FTM_TX_CNT_INT FSK_TX_FTM_TX_CNT_BASEADDR,8,4 +#define FSK_TX_FTM_TX_INT_EN FSK_TX_FTM_TX_CNT_BASEADDR,4,1 +#define FSK_TX_FTM_TX_INT_SRC_SEL FSK_TX_FTM_TX_CNT_BASEADDR,0,2 + +#define AFE_REG_D2A_FSK_BIAS_BASEADDR 0x90200040 +#define AFE_REG_D2A_FSK_BIAS_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,0,1 +#define AFE_REG_D2A_FSK_TEST_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,10,1 +#define AFE_REG_D2A_FSK_TEST_MODE AFE_REG_D2A_FSK_BIAS_BASEADDR,11,4 +#define AFE_REG_D2A_FSK_TERM_INT_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,15,1 +#define AFE_REG_D2A_FSK_RESETB_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,16,1 +#define AFE_REG_D2A_FSK_REG_EN_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,17,1 +#define AFE_REG_D2A_FSK_REG_EN_LKG_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,18,1 +#define AFE_REG_D2A_FSK_REG_AMP_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,19,3 +#define AFE_REG_D2A_FSK_REG_TEST_CTRL_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,22,2 +#define AFE_REG_D2A_DSQ_RX_MODE AFE_REG_D2A_FSK_BIAS_BASEADDR,24,1 +#define AFE_REG_D2A_DSQ_RX_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,25,1 +#define AFE_REG_D2A_DSQ_HYST AFE_REG_D2A_FSK_BIAS_BASEADDR,26,2 +#define AFE_REG_D2A_DSQ_RESETB_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,28,1 +#define AFE_REG_D2A_FSK_CLKRX_ENA AFE_REG_D2A_FSK_BIAS_BASEADDR,29,1 + +#define DMD_TEI_BASEADDR 0x3FFFEBE0 +#define DMD_TEI_ENA DMD_TEI_BASEADDR,0,1 + +#define xpt_shm_input_control0 0x90700270,0,8 +#define xpt_shm_input_control1 0x90700270,8,8 +#define xpt_shm_input_control2 0x90700270,16,8 +#define xpt_shm_input_control3 0x90700270,24,8 +#define xpt_shm_input_control4 0x90700274,0,8 +#define xpt_shm_input_control5 0x90700274,8,8 +#define xpt_shm_input_control6 0x90700274,16,8 +#define xpt_shm_input_control7 0x90700274,24,8 + + +#define xpt_shm_output_control0 0x90700278,0,8 +#define xpt_shm_output_control1 0x90700278,8,8 +#define xpt_shm_output_control2 0x90700278,16,8 +#define xpt_shm_output_control3 0x90700278,24,8 +#define xpt_shm_output_control4 0x9070027C,0,8 +#define xpt_shm_output_control5 0x9070027C,8,8 +#define xpt_shm_output_control6 0x9070027C,16,8 +#define xpt_shm_output_control7 0x9070027C,24,8 + +#define xpt_mode_27mhz 0x90700184,0,1 +#define xpt_enable_pcr_count 0x90700184,1,1 + +#define xcpu_ctrl_003c_reg 0x9072003C,0,4 + +#ifdef __cplusplus +} +#endif + +#endif //__MXL58X_REGISTERS_H__ diff --git a/frontends/stv0367dd.c b/frontends/stv0367dd.c index 0d64181..ab74cf3 100644 --- a/frontends/stv0367dd.c +++ b/frontends/stv0367dd.c @@ -1,2161 +1,2161 @@ -/* - * stv0367dd: STV0367 DVB-C/T demodulator driver - * - * Copyright (C) 2011 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_frontend.h" -#include "stv0367dd.h" -#include "stv0367dd_regs.h" - -enum omode { OM_NONE, OM_DVBT, OM_DVBC, OM_QAM_ITU_C }; -enum { QAM_MOD_QAM4 = 0, - QAM_MOD_QAM16, - QAM_MOD_QAM32, - QAM_MOD_QAM64, - QAM_MOD_QAM128, - QAM_MOD_QAM256, - QAM_MOD_QAM512, - QAM_MOD_QAM1024 -}; - -enum {QAM_SPECT_NORMAL, QAM_SPECT_INVERTED }; - -enum { - QAM_FEC_A = 1, /* J83 Annex A */ - QAM_FEC_B = (1<<1), /* J83 Annex B */ - QAM_FEC_C = (1<<2) /* J83 Annex C */ -}; - -enum EDemodState { Off, QAMSet, OFDMSet, QAMStarted, OFDMStarted }; - -struct stv_state { - struct dvb_frontend frontend; - fe_modulation_t modulation; - u32 symbol_rate; - u32 bandwidth; - struct device *dev; - - struct i2c_adapter *i2c; - u8 adr; - u8 cont_clock; - void *priv; - - struct mutex mutex; - struct mutex ctlock; - - u32 master_clock; - u32 adc_clock; - u8 ID; - u8 I2CRPT; - u32 omode; - u8 qam_inversion; - - s32 IF; - - s32 m_FECTimeOut; - s32 m_DemodTimeOut; - s32 m_SignalTimeOut; - s32 m_DemodLockTime; - s32 m_FFTTimeOut; - s32 m_TSTimeOut; - - bool m_bFirstTimeLock; - - u8 m_Save_QAM_AGC_CTL; - - enum EDemodState demod_state; - - u8 m_OFDM_FFTMode; // 0 = 2k, 1 = 8k, 2 = 4k - u8 m_OFDM_Modulation; // - u8 m_OFDM_FEC; // - u8 m_OFDM_Guard; - - u32 ucblocks; - u32 ber; -}; - -struct init_table { - u16 adr; - u8 data; -}; - -struct init_table base_init[] = { - { R367_IOCFG0, 0x80 }, - { R367_DAC0R, 0x00 }, - { R367_IOCFG1, 0x00 }, - { R367_DAC1R, 0x00 }, - { R367_IOCFG2, 0x00 }, - { R367_SDFR, 0x00 }, - { R367_AUX_CLK, 0x00 }, - { R367_FREESYS1, 0x00 }, - { R367_FREESYS2, 0x00 }, - { R367_FREESYS3, 0x00 }, - { R367_GPIO_CFG, 0x55 }, - { R367_GPIO_CMD, 0x01 }, - { R367_TSTRES, 0x00 }, - { R367_ANACTRL, 0x00 }, - { R367_TSTBUS, 0x00 }, - { R367_RF_AGC2, 0x20 }, - { R367_ANADIGCTRL, 0x0b }, - { R367_PLLMDIV, 0x01 }, - { R367_PLLNDIV, 0x08 }, - { R367_PLLSETUP, 0x18 }, - { R367_DUAL_AD12, 0x04 }, - { R367_TSTBIST, 0x00 }, - { 0x0000, 0x00 } -}; - -struct init_table qam_init[] = { - { R367_QAM_CTRL_1, 0x06 },// Orginal 0x04 - { R367_QAM_CTRL_2, 0x03 }, - { R367_QAM_IT_STATUS1, 0x2b }, - { R367_QAM_IT_STATUS2, 0x08 }, - { R367_QAM_IT_EN1, 0x00 }, - { R367_QAM_IT_EN2, 0x00 }, - { R367_QAM_CTRL_STATUS, 0x04 }, - { R367_QAM_TEST_CTL, 0x00 }, - { R367_QAM_AGC_CTL, 0x73 }, - { R367_QAM_AGC_IF_CFG, 0x50 }, - { R367_QAM_AGC_RF_CFG, 0x02 },// RF Freeze - { R367_QAM_AGC_PWM_CFG, 0x03 }, - { R367_QAM_AGC_PWR_REF_L, 0x5a }, - { R367_QAM_AGC_PWR_REF_H, 0x00 }, - { R367_QAM_AGC_RF_TH_L, 0xff }, - { R367_QAM_AGC_RF_TH_H, 0x07 }, - { R367_QAM_AGC_IF_LTH_L, 0x00 }, - { R367_QAM_AGC_IF_LTH_H, 0x08 }, - { R367_QAM_AGC_IF_HTH_L, 0xff }, - { R367_QAM_AGC_IF_HTH_H, 0x07 }, - { R367_QAM_AGC_PWR_RD_L, 0xa0 }, - { R367_QAM_AGC_PWR_RD_M, 0xe9 }, - { R367_QAM_AGC_PWR_RD_H, 0x03 }, - { R367_QAM_AGC_PWM_IFCMD_L, 0xe4 }, - { R367_QAM_AGC_PWM_IFCMD_H, 0x00 }, - { R367_QAM_AGC_PWM_RFCMD_L, 0xff }, - { R367_QAM_AGC_PWM_RFCMD_H, 0x07 }, - { R367_QAM_IQDEM_CFG, 0x01 }, - { R367_QAM_MIX_NCO_LL, 0x22 }, - { R367_QAM_MIX_NCO_HL, 0x96 }, - { R367_QAM_MIX_NCO_HH, 0x55 }, - { R367_QAM_SRC_NCO_LL, 0xff }, - { R367_QAM_SRC_NCO_LH, 0x0c }, - { R367_QAM_SRC_NCO_HL, 0xf5 }, - { R367_QAM_SRC_NCO_HH, 0x20 }, - { R367_QAM_IQDEM_GAIN_SRC_L, 0x06 }, - { R367_QAM_IQDEM_GAIN_SRC_H, 0x01 }, - { R367_QAM_IQDEM_DCRM_CFG_LL, 0xfe }, - { R367_QAM_IQDEM_DCRM_CFG_LH, 0xff }, - { R367_QAM_IQDEM_DCRM_CFG_HL, 0x0f }, - { R367_QAM_IQDEM_DCRM_CFG_HH, 0x00 }, - { R367_QAM_IQDEM_ADJ_COEFF0, 0x34 }, - { R367_QAM_IQDEM_ADJ_COEFF1, 0xae }, - { R367_QAM_IQDEM_ADJ_COEFF2, 0x46 }, - { R367_QAM_IQDEM_ADJ_COEFF3, 0x77 }, - { R367_QAM_IQDEM_ADJ_COEFF4, 0x96 }, - { R367_QAM_IQDEM_ADJ_COEFF5, 0x69 }, - { R367_QAM_IQDEM_ADJ_COEFF6, 0xc7 }, - { R367_QAM_IQDEM_ADJ_COEFF7, 0x01 }, - { R367_QAM_IQDEM_ADJ_EN, 0x04 }, - { R367_QAM_IQDEM_ADJ_AGC_REF, 0x94 }, - { R367_QAM_ALLPASSFILT1, 0xc9 }, - { R367_QAM_ALLPASSFILT2, 0x2d }, - { R367_QAM_ALLPASSFILT3, 0xa3 }, - { R367_QAM_ALLPASSFILT4, 0xfb }, - { R367_QAM_ALLPASSFILT5, 0xf6 }, - { R367_QAM_ALLPASSFILT6, 0x45 }, - { R367_QAM_ALLPASSFILT7, 0x6f }, - { R367_QAM_ALLPASSFILT8, 0x7e }, - { R367_QAM_ALLPASSFILT9, 0x05 }, - { R367_QAM_ALLPASSFILT10, 0x0a }, - { R367_QAM_ALLPASSFILT11, 0x51 }, - { R367_QAM_TRL_AGC_CFG, 0x20 }, - { R367_QAM_TRL_LPF_CFG, 0x28 }, - { R367_QAM_TRL_LPF_ACQ_GAIN, 0x44 }, - { R367_QAM_TRL_LPF_TRK_GAIN, 0x22 }, - { R367_QAM_TRL_LPF_OUT_GAIN, 0x03 }, - { R367_QAM_TRL_LOCKDET_LTH, 0x04 }, - { R367_QAM_TRL_LOCKDET_HTH, 0x11 }, - { R367_QAM_TRL_LOCKDET_TRGVAL, 0x20 }, - { R367_QAM_IQ_QAM, 0x01 }, - { R367_QAM_FSM_STATE, 0xa0 }, - { R367_QAM_FSM_CTL, 0x08 }, - { R367_QAM_FSM_STS, 0x0c }, - { R367_QAM_FSM_SNR0_HTH, 0x00 }, - { R367_QAM_FSM_SNR1_HTH, 0x00 }, - { R367_QAM_FSM_SNR2_HTH, 0x00 }, - { R367_QAM_FSM_SNR0_LTH, 0x00 }, - { R367_QAM_FSM_SNR1_LTH, 0x00 }, - { R367_QAM_FSM_EQA1_HTH, 0x00 }, - { R367_QAM_FSM_TEMPO, 0x32 }, - { R367_QAM_FSM_CONFIG, 0x03 }, - { R367_QAM_EQU_I_TESTTAP_L, 0x11 }, - { R367_QAM_EQU_I_TESTTAP_M, 0x00 }, - { R367_QAM_EQU_I_TESTTAP_H, 0x00 }, - { R367_QAM_EQU_TESTAP_CFG, 0x00 }, - { R367_QAM_EQU_Q_TESTTAP_L, 0xff }, - { R367_QAM_EQU_Q_TESTTAP_M, 0x00 }, - { R367_QAM_EQU_Q_TESTTAP_H, 0x00 }, - { R367_QAM_EQU_TAP_CTRL, 0x00 }, - { R367_QAM_EQU_CTR_CRL_CONTROL_L, 0x11 }, - { R367_QAM_EQU_CTR_CRL_CONTROL_H, 0x05 }, - { R367_QAM_EQU_CTR_HIPOW_L, 0x00 }, - { R367_QAM_EQU_CTR_HIPOW_H, 0x00 }, - { R367_QAM_EQU_I_EQU_LO, 0xef }, - { R367_QAM_EQU_I_EQU_HI, 0x00 }, - { R367_QAM_EQU_Q_EQU_LO, 0xee }, - { R367_QAM_EQU_Q_EQU_HI, 0x00 }, - { R367_QAM_EQU_MAPPER, 0xc5 }, - { R367_QAM_EQU_SWEEP_RATE, 0x80 }, - { R367_QAM_EQU_SNR_LO, 0x64 }, - { R367_QAM_EQU_SNR_HI, 0x03 }, - { R367_QAM_EQU_GAMMA_LO, 0x00 }, - { R367_QAM_EQU_GAMMA_HI, 0x00 }, - { R367_QAM_EQU_ERR_GAIN, 0x36 }, - { R367_QAM_EQU_RADIUS, 0xaa }, - { R367_QAM_EQU_FFE_MAINTAP, 0x00 }, - { R367_QAM_EQU_FFE_LEAKAGE, 0x63 }, - { R367_QAM_EQU_FFE_MAINTAP_POS, 0xdf }, - { R367_QAM_EQU_GAIN_WIDE, 0x88 }, - { R367_QAM_EQU_GAIN_NARROW, 0x41 }, - { R367_QAM_EQU_CTR_LPF_GAIN, 0xd1 }, - { R367_QAM_EQU_CRL_LPF_GAIN, 0xa7 }, - { R367_QAM_EQU_GLOBAL_GAIN, 0x06 }, - { R367_QAM_EQU_CRL_LD_SEN, 0x85 }, - { R367_QAM_EQU_CRL_LD_VAL, 0xe2 }, - { R367_QAM_EQU_CRL_TFR, 0x20 }, - { R367_QAM_EQU_CRL_BISTH_LO, 0x00 }, - { R367_QAM_EQU_CRL_BISTH_HI, 0x00 }, - { R367_QAM_EQU_SWEEP_RANGE_LO, 0x00 }, - { R367_QAM_EQU_SWEEP_RANGE_HI, 0x00 }, - { R367_QAM_EQU_CRL_LIMITER, 0x40 }, - { R367_QAM_EQU_MODULUS_MAP, 0x90 }, - { R367_QAM_EQU_PNT_GAIN, 0xa7 }, - { R367_QAM_FEC_AC_CTR_0, 0x16 }, - { R367_QAM_FEC_AC_CTR_1, 0x0b }, - { R367_QAM_FEC_AC_CTR_2, 0x88 }, - { R367_QAM_FEC_AC_CTR_3, 0x02 }, - { R367_QAM_FEC_STATUS, 0x12 }, - { R367_QAM_RS_COUNTER_0, 0x7d }, - { R367_QAM_RS_COUNTER_1, 0xd0 }, - { R367_QAM_RS_COUNTER_2, 0x19 }, - { R367_QAM_RS_COUNTER_3, 0x0b }, - { R367_QAM_RS_COUNTER_4, 0xa3 }, - { R367_QAM_RS_COUNTER_5, 0x00 }, - { R367_QAM_BERT_0, 0x01 }, - { R367_QAM_BERT_1, 0x25 }, - { R367_QAM_BERT_2, 0x41 }, - { R367_QAM_BERT_3, 0x39 }, - { R367_QAM_OUTFORMAT_0, 0xc2 }, - { R367_QAM_OUTFORMAT_1, 0x22 }, - { R367_QAM_SMOOTHER_2, 0x28 }, - { R367_QAM_TSMF_CTRL_0, 0x01 }, - { R367_QAM_TSMF_CTRL_1, 0xc6 }, - { R367_QAM_TSMF_CTRL_3, 0x43 }, - { R367_QAM_TS_ON_ID_0, 0x00 }, - { R367_QAM_TS_ON_ID_1, 0x00 }, - { R367_QAM_TS_ON_ID_2, 0x00 }, - { R367_QAM_TS_ON_ID_3, 0x00 }, - { R367_QAM_RE_STATUS_0, 0x00 }, - { R367_QAM_RE_STATUS_1, 0x00 }, - { R367_QAM_RE_STATUS_2, 0x00 }, - { R367_QAM_RE_STATUS_3, 0x00 }, - { R367_QAM_TS_STATUS_0, 0x00 }, - { R367_QAM_TS_STATUS_1, 0x00 }, - { R367_QAM_TS_STATUS_2, 0xa0 }, - { R367_QAM_TS_STATUS_3, 0x00 }, - { R367_QAM_T_O_ID_0, 0x00 }, - { R367_QAM_T_O_ID_1, 0x00 }, - { R367_QAM_T_O_ID_2, 0x00 }, - { R367_QAM_T_O_ID_3, 0x00 }, - { 0x0000, 0x00 } // EOT -}; - -struct init_table ofdm_init[] = { - //{R367_OFDM_ID ,0x60}, - //{R367_OFDM_I2CRPT ,0x22}, - //{R367_OFDM_TOPCTRL ,0x02}, - //{R367_OFDM_IOCFG0 ,0x40}, - //{R367_OFDM_DAC0R ,0x00}, - //{R367_OFDM_IOCFG1 ,0x00}, - //{R367_OFDM_DAC1R ,0x00}, - //{R367_OFDM_IOCFG2 ,0x62}, - //{R367_OFDM_SDFR ,0x00}, - //{R367_OFDM_STATUS ,0xf8}, - //{R367_OFDM_AUX_CLK ,0x0a}, - //{R367_OFDM_FREESYS1 ,0x00}, - //{R367_OFDM_FREESYS2 ,0x00}, - //{R367_OFDM_FREESYS3 ,0x00}, - //{R367_OFDM_GPIO_CFG ,0x55}, - //{R367_OFDM_GPIO_CMD ,0x00}, - {R367_OFDM_AGC2MAX ,0xff}, - {R367_OFDM_AGC2MIN ,0x00}, - {R367_OFDM_AGC1MAX ,0xff}, - {R367_OFDM_AGC1MIN ,0x00}, - {R367_OFDM_AGCR ,0xbc}, - {R367_OFDM_AGC2TH ,0x00}, - //{R367_OFDM_AGC12C ,0x01}, //Note: This defines AGC pins, also needed for QAM - {R367_OFDM_AGCCTRL1 ,0x85}, - {R367_OFDM_AGCCTRL2 ,0x1f}, - {R367_OFDM_AGC1VAL1 ,0x00}, - {R367_OFDM_AGC1VAL2 ,0x00}, - {R367_OFDM_AGC2VAL1 ,0x6f}, - {R367_OFDM_AGC2VAL2 ,0x05}, - {R367_OFDM_AGC2PGA ,0x00}, - {R367_OFDM_OVF_RATE1 ,0x00}, - {R367_OFDM_OVF_RATE2 ,0x00}, - {R367_OFDM_GAIN_SRC1 ,0x2b}, - {R367_OFDM_GAIN_SRC2 ,0x04}, - {R367_OFDM_INC_DEROT1 ,0x55}, - {R367_OFDM_INC_DEROT2 ,0x55}, - {R367_OFDM_PPM_CPAMP_DIR ,0x2c}, - {R367_OFDM_PPM_CPAMP_INV ,0x00}, - {R367_OFDM_FREESTFE_1 ,0x00}, - {R367_OFDM_FREESTFE_2 ,0x1c}, - {R367_OFDM_DCOFFSET ,0x00}, - {R367_OFDM_EN_PROCESS ,0x05}, - {R367_OFDM_SDI_SMOOTHER ,0x80}, - {R367_OFDM_FE_LOOP_OPEN ,0x1c}, - {R367_OFDM_FREQOFF1 ,0x00}, - {R367_OFDM_FREQOFF2 ,0x00}, - {R367_OFDM_FREQOFF3 ,0x00}, - {R367_OFDM_TIMOFF1 ,0x00}, - {R367_OFDM_TIMOFF2 ,0x00}, - {R367_OFDM_EPQ ,0x02}, - {R367_OFDM_EPQAUTO ,0x01}, - {R367_OFDM_SYR_UPDATE ,0xf5}, - {R367_OFDM_CHPFREE ,0x00}, - {R367_OFDM_PPM_STATE_MAC ,0x23}, - {R367_OFDM_INR_THRESHOLD ,0xff}, - {R367_OFDM_EPQ_TPS_ID_CELL ,0xf9}, - {R367_OFDM_EPQ_CFG ,0x00}, - {R367_OFDM_EPQ_STATUS ,0x01}, - {R367_OFDM_AUTORELOCK ,0x81}, - {R367_OFDM_BER_THR_VMSB ,0x00}, - {R367_OFDM_BER_THR_MSB ,0x00}, - {R367_OFDM_BER_THR_LSB ,0x00}, - {R367_OFDM_CCD ,0x83}, - {R367_OFDM_SPECTR_CFG ,0x00}, - {R367_OFDM_CHC_DUMMY ,0x18}, - {R367_OFDM_INC_CTL ,0x88}, - {R367_OFDM_INCTHRES_COR1 ,0xb4}, - {R367_OFDM_INCTHRES_COR2 ,0x96}, - {R367_OFDM_INCTHRES_DET1 ,0x0e}, - {R367_OFDM_INCTHRES_DET2 ,0x11}, - {R367_OFDM_IIR_CELLNB ,0x8d}, - {R367_OFDM_IIRCX_COEFF1_MSB ,0x00}, - {R367_OFDM_IIRCX_COEFF1_LSB ,0x00}, - {R367_OFDM_IIRCX_COEFF2_MSB ,0x09}, - {R367_OFDM_IIRCX_COEFF2_LSB ,0x18}, - {R367_OFDM_IIRCX_COEFF3_MSB ,0x14}, - {R367_OFDM_IIRCX_COEFF3_LSB ,0x9c}, - {R367_OFDM_IIRCX_COEFF4_MSB ,0x00}, - {R367_OFDM_IIRCX_COEFF4_LSB ,0x00}, - {R367_OFDM_IIRCX_COEFF5_MSB ,0x36}, - {R367_OFDM_IIRCX_COEFF5_LSB ,0x42}, - {R367_OFDM_FEPATH_CFG ,0x00}, - {R367_OFDM_PMC1_FUNC ,0x65}, - {R367_OFDM_PMC1_FOR ,0x00}, - {R367_OFDM_PMC2_FUNC ,0x00}, - {R367_OFDM_STATUS_ERR_DA ,0xe0}, - {R367_OFDM_DIG_AGC_R ,0xfe}, - {R367_OFDM_COMAGC_TARMSB ,0x0b}, - {R367_OFDM_COM_AGC_TAR_ENMODE ,0x41}, - {R367_OFDM_COM_AGC_CFG ,0x3e}, - {R367_OFDM_COM_AGC_GAIN1 ,0x39}, - {R367_OFDM_AUT_AGC_TARGETMSB ,0x0b}, - {R367_OFDM_LOCK_DET_MSB ,0x01}, - {R367_OFDM_AGCTAR_LOCK_LSBS ,0x40}, - {R367_OFDM_AUT_GAIN_EN ,0xf4}, - {R367_OFDM_AUT_CFG ,0xf0}, - {R367_OFDM_LOCKN ,0x23}, - {R367_OFDM_INT_X_3 ,0x00}, - {R367_OFDM_INT_X_2 ,0x03}, - {R367_OFDM_INT_X_1 ,0x8d}, - {R367_OFDM_INT_X_0 ,0xa0}, - {R367_OFDM_MIN_ERRX_MSB ,0x00}, - {R367_OFDM_COR_CTL ,0x00}, - {R367_OFDM_COR_STAT ,0xf6}, - {R367_OFDM_COR_INTEN ,0x00}, - {R367_OFDM_COR_INTSTAT ,0x3f}, - {R367_OFDM_COR_MODEGUARD ,0x03}, - {R367_OFDM_AGC_CTL ,0x08}, - {R367_OFDM_AGC_MANUAL1 ,0x00}, - {R367_OFDM_AGC_MANUAL2 ,0x00}, - {R367_OFDM_AGC_TARG ,0x16}, - {R367_OFDM_AGC_GAIN1 ,0x53}, - {R367_OFDM_AGC_GAIN2 ,0x1d}, - {R367_OFDM_RESERVED_1 ,0x00}, - {R367_OFDM_RESERVED_2 ,0x00}, - {R367_OFDM_RESERVED_3 ,0x00}, - {R367_OFDM_CAS_CTL ,0x44}, - {R367_OFDM_CAS_FREQ ,0xb3}, - {R367_OFDM_CAS_DAGCGAIN ,0x12}, - {R367_OFDM_SYR_CTL ,0x04}, - {R367_OFDM_SYR_STAT ,0x10}, - {R367_OFDM_SYR_NCO1 ,0x00}, - {R367_OFDM_SYR_NCO2 ,0x00}, - {R367_OFDM_SYR_OFFSET1 ,0x00}, - {R367_OFDM_SYR_OFFSET2 ,0x00}, - {R367_OFDM_FFT_CTL ,0x00}, - {R367_OFDM_SCR_CTL ,0x70}, - {R367_OFDM_PPM_CTL1 ,0xf8}, - {R367_OFDM_TRL_CTL ,0xac}, - {R367_OFDM_TRL_NOMRATE1 ,0x1e}, - {R367_OFDM_TRL_NOMRATE2 ,0x58}, - {R367_OFDM_TRL_TIME1 ,0x1d}, - {R367_OFDM_TRL_TIME2 ,0xfc}, - {R367_OFDM_CRL_CTL ,0x24}, - {R367_OFDM_CRL_FREQ1 ,0xad}, - {R367_OFDM_CRL_FREQ2 ,0x9d}, - {R367_OFDM_CRL_FREQ3 ,0xff}, - {R367_OFDM_CHC_CTL ,0x01}, - {R367_OFDM_CHC_SNR ,0xf0}, - {R367_OFDM_BDI_CTL ,0x00}, - {R367_OFDM_DMP_CTL ,0x00}, - {R367_OFDM_TPS_RCVD1 ,0x30}, - {R367_OFDM_TPS_RCVD2 ,0x02}, - {R367_OFDM_TPS_RCVD3 ,0x01}, - {R367_OFDM_TPS_RCVD4 ,0x00}, - {R367_OFDM_TPS_ID_CELL1 ,0x00}, - {R367_OFDM_TPS_ID_CELL2 ,0x00}, - {R367_OFDM_TPS_RCVD5_SET1 ,0x02}, - {R367_OFDM_TPS_SET2 ,0x02}, - {R367_OFDM_TPS_SET3 ,0x01}, - {R367_OFDM_TPS_CTL ,0x00}, - {R367_OFDM_CTL_FFTOSNUM ,0x34}, - {R367_OFDM_TESTSELECT ,0x09}, - {R367_OFDM_MSC_REV ,0x0a}, - {R367_OFDM_PIR_CTL ,0x00}, - {R367_OFDM_SNR_CARRIER1 ,0xa1}, - {R367_OFDM_SNR_CARRIER2 ,0x9a}, - {R367_OFDM_PPM_CPAMP ,0x2c}, - {R367_OFDM_TSM_AP0 ,0x00}, - {R367_OFDM_TSM_AP1 ,0x00}, - {R367_OFDM_TSM_AP2 ,0x00}, - {R367_OFDM_TSM_AP3 ,0x00}, - {R367_OFDM_TSM_AP4 ,0x00}, - {R367_OFDM_TSM_AP5 ,0x00}, - {R367_OFDM_TSM_AP6 ,0x00}, - {R367_OFDM_TSM_AP7 ,0x00}, - //{R367_OFDM_TSTRES ,0x00}, - //{R367_OFDM_ANACTRL ,0x0D},/*caution PLL stopped, to be restarted at init!!!*/ - //{R367_OFDM_TSTBUS ,0x00}, - //{R367_OFDM_TSTRATE ,0x00}, - {R367_OFDM_CONSTMODE ,0x01}, - {R367_OFDM_CONSTCARR1 ,0x00}, - {R367_OFDM_CONSTCARR2 ,0x00}, - {R367_OFDM_ICONSTEL ,0x0a}, - {R367_OFDM_QCONSTEL ,0x15}, - {R367_OFDM_TSTBISTRES0 ,0x00}, - {R367_OFDM_TSTBISTRES1 ,0x00}, - {R367_OFDM_TSTBISTRES2 ,0x28}, - {R367_OFDM_TSTBISTRES3 ,0x00}, - //{R367_OFDM_RF_AGC1 ,0xff}, - //{R367_OFDM_RF_AGC2 ,0x83}, - //{R367_OFDM_ANADIGCTRL ,0x19}, - //{R367_OFDM_PLLMDIV ,0x0c}, - //{R367_OFDM_PLLNDIV ,0x55}, - //{R367_OFDM_PLLSETUP ,0x18}, - //{R367_OFDM_DUAL_AD12 ,0x00}, - //{R367_OFDM_TSTBIST ,0x00}, - //{R367_OFDM_PAD_COMP_CTRL ,0x00}, - //{R367_OFDM_PAD_COMP_WR ,0x00}, - //{R367_OFDM_PAD_COMP_RD ,0xe0}, - {R367_OFDM_SYR_TARGET_FFTADJT_MSB ,0x00}, - {R367_OFDM_SYR_TARGET_FFTADJT_LSB ,0x00}, - {R367_OFDM_SYR_TARGET_CHCADJT_MSB ,0x00}, - {R367_OFDM_SYR_TARGET_CHCADJT_LSB ,0x00}, - {R367_OFDM_SYR_FLAG ,0x00}, - {R367_OFDM_CRL_TARGET1 ,0x00}, - {R367_OFDM_CRL_TARGET2 ,0x00}, - {R367_OFDM_CRL_TARGET3 ,0x00}, - {R367_OFDM_CRL_TARGET4 ,0x00}, - {R367_OFDM_CRL_FLAG ,0x00}, - {R367_OFDM_TRL_TARGET1 ,0x00}, - {R367_OFDM_TRL_TARGET2 ,0x00}, - {R367_OFDM_TRL_CHC ,0x00}, - {R367_OFDM_CHC_SNR_TARG ,0x00}, - {R367_OFDM_TOP_TRACK ,0x00}, - {R367_OFDM_TRACKER_FREE1 ,0x00}, - {R367_OFDM_ERROR_CRL1 ,0x00}, - {R367_OFDM_ERROR_CRL2 ,0x00}, - {R367_OFDM_ERROR_CRL3 ,0x00}, - {R367_OFDM_ERROR_CRL4 ,0x00}, - {R367_OFDM_DEC_NCO1 ,0x2c}, - {R367_OFDM_DEC_NCO2 ,0x0f}, - {R367_OFDM_DEC_NCO3 ,0x20}, - {R367_OFDM_SNR ,0xf1}, - {R367_OFDM_SYR_FFTADJ1 ,0x00}, - {R367_OFDM_SYR_FFTADJ2 ,0x00}, - {R367_OFDM_SYR_CHCADJ1 ,0x00}, - {R367_OFDM_SYR_CHCADJ2 ,0x00}, - {R367_OFDM_SYR_OFF ,0x00}, - {R367_OFDM_PPM_OFFSET1 ,0x00}, - {R367_OFDM_PPM_OFFSET2 ,0x03}, - {R367_OFDM_TRACKER_FREE2 ,0x00}, - {R367_OFDM_DEBG_LT10 ,0x00}, - {R367_OFDM_DEBG_LT11 ,0x00}, - {R367_OFDM_DEBG_LT12 ,0x00}, - {R367_OFDM_DEBG_LT13 ,0x00}, - {R367_OFDM_DEBG_LT14 ,0x00}, - {R367_OFDM_DEBG_LT15 ,0x00}, - {R367_OFDM_DEBG_LT16 ,0x00}, - {R367_OFDM_DEBG_LT17 ,0x00}, - {R367_OFDM_DEBG_LT18 ,0x00}, - {R367_OFDM_DEBG_LT19 ,0x00}, - {R367_OFDM_DEBG_LT1A ,0x00}, - {R367_OFDM_DEBG_LT1B ,0x00}, - {R367_OFDM_DEBG_LT1C ,0x00}, - {R367_OFDM_DEBG_LT1D ,0x00}, - {R367_OFDM_DEBG_LT1E ,0x00}, - {R367_OFDM_DEBG_LT1F ,0x00}, - {R367_OFDM_RCCFGH ,0x00}, - {R367_OFDM_RCCFGM ,0x00}, - {R367_OFDM_RCCFGL ,0x00}, - {R367_OFDM_RCINSDELH ,0x00}, - {R367_OFDM_RCINSDELM ,0x00}, - {R367_OFDM_RCINSDELL ,0x00}, - {R367_OFDM_RCSTATUS ,0x00}, - {R367_OFDM_RCSPEED ,0x6f}, - {R367_OFDM_RCDEBUGM ,0xe7}, - {R367_OFDM_RCDEBUGL ,0x9b}, - {R367_OFDM_RCOBSCFG ,0x00}, - {R367_OFDM_RCOBSM ,0x00}, - {R367_OFDM_RCOBSL ,0x00}, - {R367_OFDM_RCFECSPY ,0x00}, - {R367_OFDM_RCFSPYCFG ,0x00}, - {R367_OFDM_RCFSPYDATA ,0x00}, - {R367_OFDM_RCFSPYOUT ,0x00}, - {R367_OFDM_RCFSTATUS ,0x00}, - {R367_OFDM_RCFGOODPACK ,0x00}, - {R367_OFDM_RCFPACKCNT ,0x00}, - {R367_OFDM_RCFSPYMISC ,0x00}, - {R367_OFDM_RCFBERCPT4 ,0x00}, - {R367_OFDM_RCFBERCPT3 ,0x00}, - {R367_OFDM_RCFBERCPT2 ,0x00}, - {R367_OFDM_RCFBERCPT1 ,0x00}, - {R367_OFDM_RCFBERCPT0 ,0x00}, - {R367_OFDM_RCFBERERR2 ,0x00}, - {R367_OFDM_RCFBERERR1 ,0x00}, - {R367_OFDM_RCFBERERR0 ,0x00}, - {R367_OFDM_RCFSTATESM ,0x00}, - {R367_OFDM_RCFSTATESL ,0x00}, - {R367_OFDM_RCFSPYBER ,0x00}, - {R367_OFDM_RCFSPYDISTM ,0x00}, - {R367_OFDM_RCFSPYDISTL ,0x00}, - {R367_OFDM_RCFSPYOBS7 ,0x00}, - {R367_OFDM_RCFSPYOBS6 ,0x00}, - {R367_OFDM_RCFSPYOBS5 ,0x00}, - {R367_OFDM_RCFSPYOBS4 ,0x00}, - {R367_OFDM_RCFSPYOBS3 ,0x00}, - {R367_OFDM_RCFSPYOBS2 ,0x00}, - {R367_OFDM_RCFSPYOBS1 ,0x00}, - {R367_OFDM_RCFSPYOBS0 ,0x00}, - //{R367_OFDM_TSGENERAL ,0x00}, - //{R367_OFDM_RC1SPEED ,0x6f}, - //{R367_OFDM_TSGSTATUS ,0x18}, - {R367_OFDM_FECM ,0x01}, - {R367_OFDM_VTH12 ,0xff}, - {R367_OFDM_VTH23 ,0xa1}, - {R367_OFDM_VTH34 ,0x64}, - {R367_OFDM_VTH56 ,0x40}, - {R367_OFDM_VTH67 ,0x00}, - {R367_OFDM_VTH78 ,0x2c}, - {R367_OFDM_VITCURPUN ,0x12}, - {R367_OFDM_VERROR ,0x01}, - {R367_OFDM_PRVIT ,0x3f}, - {R367_OFDM_VAVSRVIT ,0x00}, - {R367_OFDM_VSTATUSVIT ,0xbd}, - {R367_OFDM_VTHINUSE ,0xa1}, - {R367_OFDM_KDIV12 ,0x20}, - {R367_OFDM_KDIV23 ,0x40}, - {R367_OFDM_KDIV34 ,0x20}, - {R367_OFDM_KDIV56 ,0x30}, - {R367_OFDM_KDIV67 ,0x00}, - {R367_OFDM_KDIV78 ,0x30}, - {R367_OFDM_SIGPOWER ,0x54}, - {R367_OFDM_DEMAPVIT ,0x40}, - {R367_OFDM_VITSCALE ,0x00}, - {R367_OFDM_FFEC1PRG ,0x00}, - {R367_OFDM_FVITCURPUN ,0x12}, - {R367_OFDM_FVERROR ,0x01}, - {R367_OFDM_FVSTATUSVIT ,0xbd}, - {R367_OFDM_DEBUG_LT1 ,0x00}, - {R367_OFDM_DEBUG_LT2 ,0x00}, - {R367_OFDM_DEBUG_LT3 ,0x00}, - {R367_OFDM_TSTSFMET ,0x00}, - {R367_OFDM_SELOUT ,0x00}, - {R367_OFDM_TSYNC ,0x00}, - {R367_OFDM_TSTERR ,0x00}, - {R367_OFDM_TSFSYNC ,0x00}, - {R367_OFDM_TSTSFERR ,0x00}, - {R367_OFDM_TSTTSSF1 ,0x01}, - {R367_OFDM_TSTTSSF2 ,0x1f}, - {R367_OFDM_TSTTSSF3 ,0x00}, - {R367_OFDM_TSTTS1 ,0x00}, - {R367_OFDM_TSTTS2 ,0x1f}, - {R367_OFDM_TSTTS3 ,0x01}, - {R367_OFDM_TSTTS4 ,0x00}, - {R367_OFDM_TSTTSRC ,0x00}, - {R367_OFDM_TSTTSRS ,0x00}, - {R367_OFDM_TSSTATEM ,0xb0}, - {R367_OFDM_TSSTATEL ,0x40}, - {R367_OFDM_TSCFGH ,0x80}, - {R367_OFDM_TSCFGM ,0x00}, - {R367_OFDM_TSCFGL ,0x20}, - {R367_OFDM_TSSYNC ,0x00}, - {R367_OFDM_TSINSDELH ,0x00}, - {R367_OFDM_TSINSDELM ,0x00}, - {R367_OFDM_TSINSDELL ,0x00}, - {R367_OFDM_TSDIVN ,0x03}, - {R367_OFDM_TSDIVPM ,0x00}, - {R367_OFDM_TSDIVPL ,0x00}, - {R367_OFDM_TSDIVQM ,0x00}, - {R367_OFDM_TSDIVQL ,0x00}, - {R367_OFDM_TSDILSTKM ,0x00}, - {R367_OFDM_TSDILSTKL ,0x00}, - {R367_OFDM_TSSPEED ,0x6f}, - {R367_OFDM_TSSTATUS ,0x81}, - {R367_OFDM_TSSTATUS2 ,0x6a}, - {R367_OFDM_TSBITRATEM ,0x0f}, - {R367_OFDM_TSBITRATEL ,0xc6}, - {R367_OFDM_TSPACKLENM ,0x00}, - {R367_OFDM_TSPACKLENL ,0xfc}, - {R367_OFDM_TSBLOCLENM ,0x0a}, - {R367_OFDM_TSBLOCLENL ,0x80}, - {R367_OFDM_TSDLYH ,0x90}, - {R367_OFDM_TSDLYM ,0x68}, - {R367_OFDM_TSDLYL ,0x01}, - {R367_OFDM_TSNPDAV ,0x00}, - {R367_OFDM_TSBUFSTATH ,0x00}, - {R367_OFDM_TSBUFSTATM ,0x00}, - {R367_OFDM_TSBUFSTATL ,0x00}, - {R367_OFDM_TSDEBUGM ,0xcf}, - {R367_OFDM_TSDEBUGL ,0x1e}, - {R367_OFDM_TSDLYSETH ,0x00}, - {R367_OFDM_TSDLYSETM ,0x68}, - {R367_OFDM_TSDLYSETL ,0x00}, - {R367_OFDM_TSOBSCFG ,0x00}, - {R367_OFDM_TSOBSM ,0x47}, - {R367_OFDM_TSOBSL ,0x1f}, - {R367_OFDM_ERRCTRL1 ,0x95}, - {R367_OFDM_ERRCNT1H ,0x80}, - {R367_OFDM_ERRCNT1M ,0x00}, - {R367_OFDM_ERRCNT1L ,0x00}, - {R367_OFDM_ERRCTRL2 ,0x95}, - {R367_OFDM_ERRCNT2H ,0x00}, - {R367_OFDM_ERRCNT2M ,0x00}, - {R367_OFDM_ERRCNT2L ,0x00}, - {R367_OFDM_FECSPY ,0x88}, - {R367_OFDM_FSPYCFG ,0x2c}, - {R367_OFDM_FSPYDATA ,0x3a}, - {R367_OFDM_FSPYOUT ,0x06}, - {R367_OFDM_FSTATUS ,0x61}, - {R367_OFDM_FGOODPACK ,0xff}, - {R367_OFDM_FPACKCNT ,0xff}, - {R367_OFDM_FSPYMISC ,0x66}, - {R367_OFDM_FBERCPT4 ,0x00}, - {R367_OFDM_FBERCPT3 ,0x00}, - {R367_OFDM_FBERCPT2 ,0x36}, - {R367_OFDM_FBERCPT1 ,0x36}, - {R367_OFDM_FBERCPT0 ,0x14}, - {R367_OFDM_FBERERR2 ,0x00}, - {R367_OFDM_FBERERR1 ,0x03}, - {R367_OFDM_FBERERR0 ,0x28}, - {R367_OFDM_FSTATESM ,0x00}, - {R367_OFDM_FSTATESL ,0x02}, - {R367_OFDM_FSPYBER ,0x00}, - {R367_OFDM_FSPYDISTM ,0x01}, - {R367_OFDM_FSPYDISTL ,0x9f}, - {R367_OFDM_FSPYOBS7 ,0xc9}, - {R367_OFDM_FSPYOBS6 ,0x99}, - {R367_OFDM_FSPYOBS5 ,0x08}, - {R367_OFDM_FSPYOBS4 ,0xec}, - {R367_OFDM_FSPYOBS3 ,0x01}, - {R367_OFDM_FSPYOBS2 ,0x0f}, - {R367_OFDM_FSPYOBS1 ,0xf5}, - {R367_OFDM_FSPYOBS0 ,0x08}, - {R367_OFDM_SFDEMAP ,0x40}, - {R367_OFDM_SFERROR ,0x00}, - {R367_OFDM_SFAVSR ,0x30}, - {R367_OFDM_SFECSTATUS ,0xcc}, - {R367_OFDM_SFKDIV12 ,0x20}, - {R367_OFDM_SFKDIV23 ,0x40}, - {R367_OFDM_SFKDIV34 ,0x20}, - {R367_OFDM_SFKDIV56 ,0x20}, - {R367_OFDM_SFKDIV67 ,0x00}, - {R367_OFDM_SFKDIV78 ,0x20}, - {R367_OFDM_SFDILSTKM ,0x00}, - {R367_OFDM_SFDILSTKL ,0x00}, - {R367_OFDM_SFSTATUS ,0xb5}, - {R367_OFDM_SFDLYH ,0x90}, - {R367_OFDM_SFDLYM ,0x60}, - {R367_OFDM_SFDLYL ,0x01}, - {R367_OFDM_SFDLYSETH ,0xc0}, - {R367_OFDM_SFDLYSETM ,0x60}, - {R367_OFDM_SFDLYSETL ,0x00}, - {R367_OFDM_SFOBSCFG ,0x00}, - {R367_OFDM_SFOBSM ,0x47}, - {R367_OFDM_SFOBSL ,0x05}, - {R367_OFDM_SFECINFO ,0x40}, - {R367_OFDM_SFERRCTRL ,0x74}, - {R367_OFDM_SFERRCNTH ,0x80}, - {R367_OFDM_SFERRCNTM ,0x00}, - {R367_OFDM_SFERRCNTL ,0x00}, - {R367_OFDM_SYMBRATEM ,0x2f}, - {R367_OFDM_SYMBRATEL ,0x50}, - {R367_OFDM_SYMBSTATUS ,0x7f}, - {R367_OFDM_SYMBCFG ,0x00}, - {R367_OFDM_SYMBFIFOM ,0xf4}, - {R367_OFDM_SYMBFIFOL ,0x0d}, - {R367_OFDM_SYMBOFFSM ,0xf0}, - {R367_OFDM_SYMBOFFSL ,0x2d}, - //{R367_OFDM_DEBUG_LT4 ,0x00}, - //{R367_OFDM_DEBUG_LT5 ,0x00}, - //{R367_OFDM_DEBUG_LT6 ,0x00}, - //{R367_OFDM_DEBUG_LT7 ,0x00}, - //{R367_OFDM_DEBUG_LT8 ,0x00}, - //{R367_OFDM_DEBUG_LT9 ,0x00}, - { 0x0000, 0x00 } // EOT -}; - -static inline u32 MulDiv32(u32 a, u32 b, u32 c) -{ - u64 tmp64; - - tmp64 = (u64)a * (u64)b; - do_div(tmp64, c); - - return (u32) tmp64; -} - -static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -{ - struct i2c_msg msg = - {.addr = adr, .flags = 0, .buf = data, .len = len}; - - if (i2c_transfer(adap, &msg, 1) != 1) { - printk("stv0367: i2c_write error\n"); - return -1; - } - return 0; -} - -#if 0 -static int i2c_read(struct i2c_adapter *adap, - u8 adr, u8 *msg, int len, u8 *answ, int alen) -{ - struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, - .buf = msg, .len = len}, - { .addr = adr, .flags = I2C_M_RD, - .buf = answ, .len = alen } }; - if (i2c_transfer(adap, msgs, 2) != 2) { - printk("stv0367: i2c_read error\n"); - return -1; - } - return 0; -} -#endif - -static int writereg(struct stv_state *state, u16 reg, u8 dat) -{ - u8 mm[3] = { (reg >> 8), reg & 0xff, dat }; - - return i2c_write(state->i2c, state->adr, mm, 3); -} - -static int readreg(struct stv_state *state, u16 reg, u8 *val) -{ - u8 msg[2] = {reg >> 8, reg & 0xff}; - struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, - .buf = msg, .len = 2}, - {.addr = state->adr, .flags = I2C_M_RD, - .buf = val, .len = 1}}; - return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; -} - -static int readregs(struct stv_state *state, u16 reg, u8 *val, int count) -{ - u8 msg[2] = {reg >> 8, reg & 0xff}; - struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, - .buf = msg, .len = 2}, - {.addr = state->adr, .flags = I2C_M_RD, - .buf = val, .len = count}}; - return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; -} - -static int write_init_table(struct stv_state *state, struct init_table *tab) -{ - while (1) { - if (!tab->adr) - break; - if (writereg(state, tab->adr, tab->data) < 0) - return -1; - tab++; - } - return 0; -} - -static int qam_set_modulation(struct stv_state *state) -{ - int stat = 0; - - switch(state->modulation) { - case QAM_16: - writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM16 ); - writereg(state, R367_QAM_AGC_PWR_REF_L,0x64); /* Set analog AGC reference */ - writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ - writereg(state, R367_QAM_FSM_STATE,0x90); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); - writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); - writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); - writereg(state, R367_QAM_EQU_PNT_GAIN,0x8a); - break; - case QAM_32: - writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM32 ); - writereg(state, R367_QAM_AGC_PWR_REF_L,0x6e); /* Set analog AGC reference */ - writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ - writereg(state, R367_QAM_FSM_STATE,0xb0); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xb7); - writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x9d); - writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); - writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); - break; - case QAM_64: - writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM64 ); - writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ - writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x82); /* Set digital AGC reference */ - if(state->symbol_rate>4500000) - { - writereg(state, R367_QAM_FSM_STATE,0xb0); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa5); - } - else if(state->symbol_rate>2500000) // 25000000 - { - writereg(state, R367_QAM_FSM_STATE,0xa0); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); - } - else - { - writereg(state, R367_QAM_FSM_STATE,0xa0); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); - } - writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); - writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); - writereg(state, R367_QAM_EQU_PNT_GAIN,0x99); - break; - case QAM_128: - writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM128 ); - writereg(state, R367_QAM_AGC_PWR_REF_L,0x76); /* Set analog AGC reference */ - writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ - writereg(state, R367_QAM_FSM_STATE,0x90); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xb1); - if(state->symbol_rate>4500000) // 45000000 - { - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); - } - else if(state->symbol_rate>2500000) // 25000000 - { - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); - } - else - { - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0x97); - } - writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x8e); - writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); - writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); - break; - case QAM_256: - writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM256 ); - writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ - writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x94); /* Set digital AGC reference */ - writereg(state, R367_QAM_FSM_STATE,0xa0); - if(state->symbol_rate>4500000) // 45000000 - { - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - } - else if(state->symbol_rate>2500000) // 25000000 - { - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - } - else - { - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); - } - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); - writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x85); - writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); - writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); - break; - default: - stat = -EINVAL; - break; - } - return stat; -} - - -static int QAM_SetSymbolRate(struct stv_state *state) -{ - int status = 0; - u32 sr = state->symbol_rate; - u32 Corr = 0; - u32 Temp, Temp1, AdpClk; - - switch(state->modulation) { - default: - case QAM_16: Corr = 1032; break; - case QAM_32: Corr = 954; break; - case QAM_64: Corr = 983; break; - case QAM_128: Corr = 957; break; - case QAM_256: Corr = 948; break; - } - - // Transfer ration - Temp = (256*sr) / state->adc_clock; - writereg(state, R367_QAM_EQU_CRL_TFR,(Temp)); - - /* Symbol rate and SRC gain calculation */ - AdpClk = (state->master_clock) / 2000; /* TRL works at half the system clock */ - - Temp = state->symbol_rate; - Temp1 = sr; - - if(sr < 2097152) /* 2097152 = 2^21 */ - { - Temp = ((((sr * 2048) / AdpClk) * 16384 ) / 125 ) * 8; - Temp1 = (((((sr * 2048) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 10000000; - } - else if(sr < 4194304) /* 4194304 = 2**22 */ - { - Temp = ((((sr * 1024) / AdpClk) * 16384 ) / 125 ) * 16; - Temp1 = (((((sr * 1024) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 5000000; - } - else if(sr < 8388608) /* 8388608 = 2**23 */ - { - Temp = ((((sr * 512) / AdpClk) * 16384 ) / 125 ) * 32; - Temp1 = (((((sr * 512) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 2500000; - } - else - { - Temp = ((((sr * 256) / AdpClk) * 16384 ) / 125 ) * 64; - Temp1 = (((((sr * 256) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 1250000; - } - - ///* Filters' coefficients are calculated and written into registers only if the filters are enabled */ - //if (ChipGetField(hChip,F367qam_ADJ_EN)) // Is disabled from init! - //{ - // FE_367qam_SetIirAdjacentcoefficient(hChip, MasterClk_Hz, SymbolRate); - //} - ///* AllPass filter is never used on this IC */ - //ChipSetField(hChip,F367qam_ALLPASSFILT_EN,0); // should be disabled from init! - - writereg(state, R367_QAM_SRC_NCO_LL,(Temp)); - writereg(state, R367_QAM_SRC_NCO_LH,(Temp>>8)); - writereg(state, R367_QAM_SRC_NCO_HL,(Temp>>16)); - writereg(state, R367_QAM_SRC_NCO_HH,(Temp>>24)); - - writereg(state, R367_QAM_IQDEM_GAIN_SRC_L,(Temp1)); - writereg(state, R367_QAM_IQDEM_GAIN_SRC_H,(Temp1>>8)); - return status; -} - - -static int QAM_SetDerotFrequency(struct stv_state *state, u32 DerotFrequency) -{ - int status = 0; - u32 Sampled_IF; - - do { - //if (DerotFrequency < 1000000) - // DerotFrequency = state->adc_clock/4; /* ZIF operation */ - if (DerotFrequency > state->adc_clock) - DerotFrequency = DerotFrequency - state->adc_clock; // User Alias - - Sampled_IF = ((32768 * (DerotFrequency/1000)) / (state->adc_clock/1000)) * 256; - if(Sampled_IF > 8388607) - Sampled_IF = 8388607; - - writereg(state, R367_QAM_MIX_NCO_LL, (Sampled_IF)); - writereg(state, R367_QAM_MIX_NCO_HL, (Sampled_IF>>8)); - writereg(state, R367_QAM_MIX_NCO_HH, (Sampled_IF>>16)); - } while(0); - - return status; -} - - - -static int QAM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) -{ - int status = 0; - u32 AGCTimeOut = 25; - u32 TRLTimeOut = 100000000 / state->symbol_rate; - u32 CRLSymbols = 0; - u32 EQLTimeOut = 100; - u32 SearchRange = state->symbol_rate / 25; - u32 CRLTimeOut; - u8 Temp; - - if( state->demod_state != QAMSet ) { - writereg(state, R367_DEBUG_LT4,0x00); - writereg(state, R367_DEBUG_LT5,0x01); - writereg(state, R367_DEBUG_LT6,0x06);// R367_QAM_CTRL_1 - writereg(state, R367_DEBUG_LT7,0x03);// R367_QAM_CTRL_2 - writereg(state, R367_DEBUG_LT8,0x00); - writereg(state, R367_DEBUG_LT9,0x00); - - // Tuner Setup - writereg(state, R367_ANADIGCTRL,0x8B); /* Buffer Q disabled, I Enabled, signed ADC */ - writereg(state, R367_DUAL_AD12,0x04); /* ADCQ disabled */ - - // Clock setup - writereg(state, R367_ANACTRL,0x0D); /* PLL bypassed and disabled */ - writereg(state, R367_TOPCTRL,0x10); // Set QAM - - writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ - writereg(state, R367_PLLNDIV,232); - writereg(state, R367_PLLSETUP,0x18); /* ADC clock is equal to system clock */ - - msleep(50); - writereg(state, R367_ANACTRL,0x00); /* PLL enabled and used */ - - state->master_clock = 58000000; - state->adc_clock = 58000000; - - state->demod_state = QAMSet; - } - - state->m_bFirstTimeLock = true; - state->m_DemodLockTime = -1; - - qam_set_modulation(state); - QAM_SetSymbolRate(state); - - // Will make problems on low symbol rates ( < 2500000 ) - - switch(state->modulation) { - default: - case QAM_16: CRLSymbols = 150000; break; - case QAM_32: CRLSymbols = 250000; break; - case QAM_64: CRLSymbols = 200000; break; - case QAM_128: CRLSymbols = 250000; break; - case QAM_256: CRLSymbols = 250000; break; - } - - CRLTimeOut = (25 * CRLSymbols * (SearchRange/1000)) / (state->symbol_rate/1000); - CRLTimeOut = (1000 * CRLTimeOut) / state->symbol_rate; - if( CRLTimeOut < 50 ) CRLTimeOut = 50; - - state->m_FECTimeOut = 20; - state->m_DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; - state->m_SignalTimeOut = AGCTimeOut + TRLTimeOut; - - // QAM_AGC_ACCUMRSTSEL = 0; - readreg(state, R367_QAM_AGC_CTL,&state->m_Save_QAM_AGC_CTL); - writereg(state, R367_QAM_AGC_CTL,state->m_Save_QAM_AGC_CTL & ~0x0F); - - // QAM_MODULUSMAP_EN = 0 - readreg(state, R367_QAM_EQU_PNT_GAIN,&Temp); - writereg(state, R367_QAM_EQU_PNT_GAIN,Temp & ~0x40); - - // QAM_SWEEP_EN = 0 - readreg(state, R367_QAM_EQU_CTR_LPF_GAIN,&Temp); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,Temp & ~0x08); - - QAM_SetDerotFrequency(state, IntermediateFrequency); - - // Release TRL - writereg(state, R367_QAM_CTRL_1,0x00); - - state->IF = IntermediateFrequency; - state->demod_state = QAMStarted; - - return status; -} - -static int OFDM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) -{ - int status = 0; - u8 GAIN_SRC1; - u32 Derot; - u8 SYR_CTL; - u8 tmp1; - u8 tmp2; - - if ( state->demod_state != OFDMSet ) { - // QAM Disable - writereg(state, R367_DEBUG_LT4, 0x00); - writereg(state, R367_DEBUG_LT5, 0x00); - writereg(state, R367_DEBUG_LT6, 0x00);// R367_QAM_CTRL_1 - writereg(state, R367_DEBUG_LT7, 0x00);// R367_QAM_CTRL_2 - writereg(state, R367_DEBUG_LT8, 0x00); - writereg(state, R367_DEBUG_LT9, 0x00); - - // Tuner Setup - writereg(state, R367_ANADIGCTRL, 0x89); /* Buffer Q disabled, I Enabled, unsigned ADC */ - writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ - - // Clock setup - writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ - writereg(state, R367_TOPCTRL, 0x00); // Set OFDM - - writereg(state, R367_PLLMDIV, 1); /* IC runs at 54 MHz with a 27 MHz crystal */ - writereg(state, R367_PLLNDIV, 8); - writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ - - msleep(50); - writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ - - state->master_clock = 54000000; - state->adc_clock = 54000000; - - state->demod_state = OFDMSet; - } - - state->m_bFirstTimeLock = true; - state->m_DemodLockTime = -1; - - // Set inversion in GAIN_SRC1 (fixed from init) - // is in GAIN_SRC1, see below - - GAIN_SRC1 = 0xA0; - // Bandwidth - - // Fixed values for 54 MHz - switch(state->bandwidth) { - case 0: - case 8000000: - // Normrate = 44384; - writereg(state, R367_OFDM_TRL_CTL,0x14); - writereg(state, R367_OFDM_TRL_NOMRATE1,0xB0); - writereg(state, R367_OFDM_TRL_NOMRATE2,0x56); - // Gain SRC = 2774 - writereg(state, R367_OFDM_GAIN_SRC1,0x0A | GAIN_SRC1); - writereg(state, R367_OFDM_GAIN_SRC2,0xD6); - break; - case 7000000: - // Normrate = 38836; - writereg(state, R367_OFDM_TRL_CTL,0x14); - writereg(state, R367_OFDM_TRL_NOMRATE1,0xDA); - writereg(state, R367_OFDM_TRL_NOMRATE2,0x4B); - // Gain SRC = 2427 - writereg(state, R367_OFDM_GAIN_SRC1,0x09 | GAIN_SRC1); - writereg(state, R367_OFDM_GAIN_SRC2,0x7B); - break; - case 6000000: - // Normrate = 33288; - writereg(state, R367_OFDM_TRL_CTL,0x14); - writereg(state, R367_OFDM_TRL_NOMRATE1,0x04); - writereg(state, R367_OFDM_TRL_NOMRATE2,0x41); - // Gain SRC = 2080 - writereg(state, R367_OFDM_GAIN_SRC1,0x08 | GAIN_SRC1); - writereg(state, R367_OFDM_GAIN_SRC2,0x20); - break; - default: - return -EINVAL; - break; - } - - Derot = ((IntermediateFrequency / 1000) * 65536) / (state->master_clock / 1000); - - writereg(state, R367_OFDM_INC_DEROT1,(Derot>>8)); - writereg(state, R367_OFDM_INC_DEROT2,(Derot)); - - readreg(state, R367_OFDM_SYR_CTL,&SYR_CTL); - SYR_CTL &= ~0x78; - writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // EchoPos = 0 - - - writereg(state, R367_OFDM_COR_MODEGUARD,0x03); // Force = 0, Mode = 0, Guard = 3 - SYR_CTL &= 0x01; - writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // SYR_TR_DIS = 0 - - msleep(5); - - writereg(state, R367_OFDM_COR_CTL,0x20); // Start core - - // -- Begin M.V. - // Reset FEC and Read Solomon - readreg(state, R367_OFDM_SFDLYSETH,&tmp1); - readreg(state, R367_TSGENERAL,&tmp2); - writereg(state, R367_OFDM_SFDLYSETH,tmp1 | 0x08); - writereg(state, R367_TSGENERAL,tmp2 | 0x01); - // -- End M.V. - - state->m_SignalTimeOut = 200; - state->IF = IntermediateFrequency; - state->demod_state = OFDMStarted; - state->m_DemodTimeOut = 0; - state->m_FECTimeOut = 0; - state->m_TSTimeOut = 0; - - return status; -} - -#if 0 -static int Stop(struct stv_state *state) -{ - int status = 0; - - switch(state->demod_state) - { - case QAMStarted: - status = writereg(state, R367_QAM_CTRL_1,0x06); - state->demod_state = QAMSet; - break; - case OFDMStarted: - status = writereg(state, R367_OFDM_COR_CTL,0x00); - state->demod_state = OFDMSet; - break; - default: - break; - } - return status; -} -#endif - -static s32 Log10x100(u32 x) -{ - static u32 LookupTable[100] = { - 101157945, 103514217, 105925373, 108392691, 110917482, - 113501082, 116144861, 118850223, 121618600, 124451461, // 800.5 - 809.5 - 127350308, 130316678, 133352143, 136458314, 139636836, - 142889396, 146217717, 149623566, 153108746, 156675107, // 810.5 - 819.5 - 160324539, 164058977, 167880402, 171790839, 175792361, - 179887092, 184077200, 188364909, 192752491, 197242274, // 820.5 - 829.5 - 201836636, 206538016, 211348904, 216271852, 221309471, - 226464431, 231739465, 237137371, 242661010, 248313311, // 830.5 - 839.5 - 254097271, 260015956, 266072506, 272270131, 278612117, - 285101827, 291742701, 298538262, 305492111, 312607937, // 840.5 - 849.5 - 319889511, 327340695, 334965439, 342767787, 350751874, - 358921935, 367282300, 375837404, 384591782, 393550075, // 850.5 - 859.5 - 402717034, 412097519, 421696503, 431519077, 441570447, - 451855944, 462381021, 473151259, 484172368, 495450191, // 860.5 - 869.5 - 506990708, 518800039, 530884444, 543250331, 555904257, - 568852931, 582103218, 595662144, 609536897, 623734835, // 870.5 - 879.5 - 638263486, 653130553, 668343918, 683911647, 699841996, - 716143410, 732824533, 749894209, 767361489, 785235635, // 880.5 - 889.5 - 803526122, 822242650, 841395142, 860993752, 881048873, - 901571138, 922571427, 944060876, 966050879, 988553095, // 890.5 - 899.5 - }; - s32 y; - int i; - - if (x == 0) - return 0; - y = 800; - if (x >= 1000000000) { - x /= 10; - y += 100; - } - - while (x < 100000000) { - x *= 10; - y -= 100; - } - i = 0; - while (i < 100 && x > LookupTable[i]) - i += 1; - y += i; - return y; -} - -static int QAM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) -{ - u32 RegValAvg = 0; - u8 RegVal[2]; - int status = 0, i; - - *pSignalToNoise = 0; - for (i = 0; i < 10; i += 1 ) { - readregs(state, R367_QAM_EQU_SNR_LO, RegVal, 2); - RegValAvg += RegVal[0] + 256 * RegVal[1]; - } - if (RegValAvg != 0) { - s32 Power = 1; - switch(state->modulation) { - case QAM_16: - Power = 20480; - break; - case QAM_32: - Power = 23040; - break; - case QAM_64: - Power = 21504; - break; - case QAM_128: - Power = 23616; - break; - case QAM_256: - Power = 21760; - break; - default: - break; - } - *pSignalToNoise = Log10x100((Power * 320) / RegValAvg); - } else { - *pSignalToNoise = 380; - } - return status; -} - -static int OFDM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) -{ - u8 CHC_SNR = 0; - - int status = readreg(state, R367_OFDM_CHC_SNR, &CHC_SNR); - if (status >= 0) { - // Note: very unclear documentation on this. - // Datasheet states snr = CHC_SNR/4 dB -> way to high values! - // Software snr = ( 1000 * CHC_SNR ) / 8 / 32 / 10; -> to low values - // Comment in SW states this should be ( 1000 * CHC_SNR ) / 4 / 32 / 10; for the 367 - // 361/362 Datasheet: snr = CHC_SNR/8 dB -> this looks best - *pSignalToNoise = ( (s32)CHC_SNR * 10) / 8; - } - //printk("SNR %d\n", *pSignalToNoise); - return status; -} - -#if 0 -static int DVBC_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -{ - *pQuality = 100; - return 0; -}; - -static int DVBT_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -{ - static s32 QE_SN[] = { - 51, // QPSK 1/2 - 69, // QPSK 2/3 - 79, // QPSK 3/4 - 89, // QPSK 5/6 - 97, // QPSK 7/8 - 108, // 16-QAM 1/2 - 131, // 16-QAM 2/3 - 146, // 16-QAM 3/4 - 156, // 16-QAM 5/6 - 160, // 16-QAM 7/8 - 165, // 64-QAM 1/2 - 187, // 64-QAM 2/3 - 202, // 64-QAM 3/4 - 216, // 64-QAM 5/6 - 225, // 64-QAM 7/8 - }; - u8 TPS_Received[2]; - int Constellation; - int CodeRate; - s32 SignalToNoiseRel, BERQuality; - - *pQuality = 0; - readregs(state, R367_OFDM_TPS_RCVD2, TPS_Received, sizeof(TPS_Received)); - Constellation = TPS_Received[0] & 0x03; - CodeRate = TPS_Received[1] & 0x07; - - if( Constellation > 2 || CodeRate > 5 ) - return -1; - SignalToNoiseRel = SignalToNoise - QE_SN[Constellation * 5 + CodeRate]; - BERQuality = 100; - - if( SignalToNoiseRel < -70 ) - *pQuality = 0; - else if( SignalToNoiseRel < 30 ) { - *pQuality = ((SignalToNoiseRel + 70) * BERQuality)/100; - } else - *pQuality = BERQuality; - return 0; -}; - -static s32 DVBCQuality(struct stv_state *state, s32 SignalToNoise) -{ - s32 SignalToNoiseRel = 0; - s32 Quality = 0; - s32 BERQuality = 100; - - switch(state->modulation) { - case QAM_16: SignalToNoiseRel = SignalToNoise - 200 ; break; - case QAM_32: SignalToNoiseRel = SignalToNoise - 230 ; break; // Not in NorDig - case QAM_64: SignalToNoiseRel = SignalToNoise - 260 ; break; - case QAM_128: SignalToNoiseRel = SignalToNoise - 290 ; break; - case QAM_256: SignalToNoiseRel = SignalToNoise - 320 ; break; - } - - if( SignalToNoiseRel < -70 ) Quality = 0; - else if( SignalToNoiseRel < 30 ) - { - Quality = ((SignalToNoiseRel + 70) * BERQuality)/100; - } - else - Quality = BERQuality; - - return Quality; -} - -static int GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -{ - *pQuality = 0; - switch(state->demod_state) - { - case QAMStarted: - *pQuality = DVBCQuality(state, SignalToNoise); - break; - case OFDMStarted: - return DVBT_GetQuality(state, SignalToNoise, pQuality); - } - return 0; -}; -#endif - -static int attach_init(struct stv_state *state) -{ - int stat = 0; - - stat = readreg(state, R367_ID, &state->ID); - if ( stat < 0 || state->ID != 0x60 ) - return -ENODEV; - printk("stv0367 found\n"); - - writereg(state, R367_TOPCTRL, 0x10); - write_init_table(state, base_init); - write_init_table(state, qam_init); - - writereg(state, R367_TOPCTRL, 0x00); - write_init_table(state, ofdm_init); - - writereg(state, R367_OFDM_GAIN_SRC1, 0x2A); - writereg(state, R367_OFDM_GAIN_SRC2, 0xD6); - writereg(state, R367_OFDM_INC_DEROT1, 0x55); - writereg(state, R367_OFDM_INC_DEROT2, 0x55); - writereg(state, R367_OFDM_TRL_CTL, 0x14); - writereg(state, R367_OFDM_TRL_NOMRATE1, 0xAE); - writereg(state, R367_OFDM_TRL_NOMRATE2, 0x56); - writereg(state, R367_OFDM_FEPATH_CFG, 0x0); - - // OFDM TS Setup - - writereg(state, R367_OFDM_TSCFGH, 0x70); - writereg(state, R367_OFDM_TSCFGM, 0xC0); - writereg(state, R367_OFDM_TSCFGL, 0x20); - writereg(state, R367_OFDM_TSSPEED, 0x40); // Fixed at 54 MHz - //writereg(state, R367_TSTBUS, 0x80); // Invert CLK - - writereg(state, R367_OFDM_TSCFGH, 0x71); - - if (state->cont_clock) - writereg(state, R367_OFDM_TSCFGH, 0xf0); - else - writereg(state, R367_OFDM_TSCFGH, 0x70); - - writereg(state, R367_TOPCTRL, 0x10); - - // Also needed for QAM - writereg(state, R367_OFDM_AGC12C, 0x01); // AGC Pin setup - - writereg(state, R367_OFDM_AGCCTRL1, 0x8A); // - - // QAM TS setup, note exact format also depends on descrambler settings - writereg(state, R367_QAM_OUTFORMAT_0, 0x85); // Inverted Clock, Swap, serial - // writereg(state, R367_QAM_OUTFORMAT_1, 0x00); // - - // Clock setup - writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ - - if( state->master_clock == 58000000 ) { - writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ - writereg(state, R367_PLLNDIV,232); - } else { - writereg(state, R367_PLLMDIV,1); /* IC runs at 54 MHz with a 27 MHz crystal */ - writereg(state, R367_PLLNDIV,8); - } - writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ - - // Tuner setup - writereg(state, R367_ANADIGCTRL, 0x8b); /* Buffer Q disabled, I Enabled, signed ADC */ - writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ - - writereg(state, R367_QAM_FSM_SNR2_HTH, 0x23); /* Improves the C/N lock limit */ - writereg(state, R367_QAM_IQ_QAM, 0x01); /* ZIF/IF Automatic mode */ - writereg(state, R367_QAM_EQU_FFE_LEAKAGE, 0x83); /* Improving burst noise performances */ - writereg(state, R367_QAM_IQDEM_ADJ_EN, 0x05); /* Improving ACI performances */ - - writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ - - writereg(state, R367_I2CRPT, state->I2CRPT); - state->demod_state = QAMSet; - return stat; -} - -static void release(struct dvb_frontend* fe) -{ - struct stv_state *state=fe->demodulator_priv; - printk("%s\n", __FUNCTION__); - kfree(state); -} - -static int gate_ctrl(struct dvb_frontend *fe, int enable) -{ - struct stv_state *state = fe->demodulator_priv; - u8 i2crpt = state->I2CRPT & ~0x80; - - if (enable) - i2crpt |= 0x80; - if (writereg(state, R367_I2CRPT, i2crpt) < 0) - return -1; - state->I2CRPT = i2crpt; - return 0; -} - -#if 0 -static int c_track(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -{ - return DVBFE_ALGO_SEARCH_AGAIN; -} -#endif - -#if 0 -int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -#endif - -static int ofdm_lock(struct stv_state *state) -{ - int status = 0; - u8 OFDM_Status; - s32 DemodTimeOut = 10; - s32 FECTimeOut = 0; - s32 TSTimeOut = 0; - u8 CPAMPMin = 255; - u8 CPAMPValue; - u8 SYR_STAT; - u8 FFTMode; - u8 TSStatus; - - msleep(state->m_SignalTimeOut); - readreg(state, R367_OFDM_STATUS,&OFDM_Status); - - if (!(OFDM_Status & 0x40)) - return -1; - //printk("lock 1\n"); - - readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); - FFTMode = (SYR_STAT & 0x0C) >> 2; - - switch(FFTMode) - { - case 0: // 2K - DemodTimeOut = 10; - FECTimeOut = 150; - TSTimeOut = 125; - CPAMPMin = 20; - break; - case 1: // 8K - DemodTimeOut = 55; - FECTimeOut = 600; - TSTimeOut = 500; - CPAMPMin = 80; - break; - case 2: // 4K - DemodTimeOut = 40; - FECTimeOut = 300; - TSTimeOut = 250; - CPAMPMin = 30; - break; - } - state->m_OFDM_FFTMode = FFTMode; - readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); - msleep(DemodTimeOut); - { - // Release FEC and Read Solomon Reset - u8 tmp1; - u8 tmp2; - readreg(state, R367_OFDM_SFDLYSETH,&tmp1); - readreg(state, R367_TSGENERAL,&tmp2); - writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); - writereg(state, R367_TSGENERAL,tmp2 & ~0x01); - } - msleep(FECTimeOut); - if( (OFDM_Status & 0x98) != 0x98 ) - ;//return -1; - //printk("lock 2\n"); - - { - u8 Guard = (SYR_STAT & 0x03); - if(Guard < 2) - { - u8 tmp; - readreg(state, R367_OFDM_SYR_CTL,&tmp); - writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN - readreg(state, R367_OFDM_SYR_UPDATE,&tmp); - writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER - } else { - u8 tmp; - readreg(state, R367_OFDM_SYR_CTL,&tmp); - writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN - readreg(state, R367_OFDM_SYR_UPDATE,&tmp); - writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER - } - - // apply Sfec workaround if 8K 64QAM CR!=1/2 - if( FFTMode == 1) - { - u8 tmp[2]; - readregs(state, R367_OFDM_TPS_RCVD2, tmp, 2); - if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) - { - writereg(state, R367_OFDM_SFDLYSETH,0xc0); - writereg(state, R367_OFDM_SFDLYSETM,0x60); - writereg(state, R367_OFDM_SFDLYSETL,0x00); - } - else - { - writereg(state, R367_OFDM_SFDLYSETH,0x00); - } - } - } - msleep(TSTimeOut); - readreg(state, R367_OFDM_TSSTATUS,&TSStatus); - if( (TSStatus & 0x80) != 0x80 ) - return -1; - //printk("lock 3\n"); - return status; -} - - -static int set_parameters(struct dvb_frontend *fe) -{ - int stat; - struct stv_state *state = fe->demodulator_priv; - u32 OF = 0; - u32 IF; - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBC_ANNEX_A: - state->omode = OM_DVBC; - /* symbol rate 0 might cause an oops */ - if (fe->dtv_property_cache.symbol_rate == 0) { - printk(KERN_ERR "stv0367dd: Invalid symbol rate\n"); - return -EINVAL; - } - break; - case SYS_DVBT: - state->omode = OM_DVBT; - break; - default: - return -EINVAL; - } - if (fe->ops.tuner_ops.set_params) - fe->ops.tuner_ops.set_params(fe); - state->modulation = fe->dtv_property_cache.modulation; - state->symbol_rate = fe->dtv_property_cache.symbol_rate; - state->bandwidth = fe->dtv_property_cache.bandwidth_hz; - fe->ops.tuner_ops.get_if_frequency(fe, &IF); - //fe->ops.tuner_ops.get_frequency(fe, &IF); - - switch(state->omode) { - case OM_DVBT: - stat = OFDM_Start(state, OF, IF); - ofdm_lock(state); - break; - case OM_DVBC: - case OM_QAM_ITU_C: - stat = QAM_Start(state, OF, IF); - break; - default: - stat = -EINVAL; - } - //printk("%s IF=%d OF=%d done\n", __FUNCTION__, IF, OF); - return stat; -} - -#if 0 -static int c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -{ - //struct stv_state *state = fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - return 0; -} - -static int OFDM_GetLockStatus(struct stv_state *state, LOCK_STATUS* pLockStatus, s32 Time) -{ - int status = STATUS_SUCCESS; - u8 OFDM_Status; - s32 DemodTimeOut = 0; - s32 FECTimeOut = 0; - s32 TSTimeOut = 0; - u8 CPAMPMin = 255; - u8 CPAMPValue; - bool SYRLock; - u8 SYR_STAT; - u8 FFTMode; - u8 TSStatus; - - readreg(state, R367_OFDM_STATUS,&OFDM_Status); - - SYRLock = (OFDM_Status & 0x40) != 0; - - if( Time > m_SignalTimeOut && !SYRLock ) - { - *pLockStatus = NEVER_LOCK; - break; - } - - if( !SYRLock ) break; - - *pLockStatus = SIGNAL_PRESENT; - - // Check Mode - - readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); - FFTMode = (SYR_STAT & 0x0C) >> 2; - - switch(FFTMode) - { - case 0: // 2K - DemodTimeOut = 10; - FECTimeOut = 150; - TSTimeOut = 125; - CPAMPMin = 20; - break; - case 1: // 8K - DemodTimeOut = 55; - FECTimeOut = 600; - TSTimeOut = 500; - CPAMPMin = 80; - break; - case 2: // 4K - DemodTimeOut = 40; - FECTimeOut = 300; - TSTimeOut = 250; - CPAMPMin = 30; - break; - } - - m_OFDM_FFTMode = FFTMode; - - if( m_DemodTimeOut == 0 && m_bFirstTimeLock ) - { - m_DemodTimeOut = Time + DemodTimeOut; - //break; - } - - readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); - - if( Time <= m_DemodTimeOut && CPAMPValue < CPAMPMin ) - { - break; - } - - if( CPAMPValue < CPAMPMin && m_bFirstTimeLock ) - { - // initiate retry - *pLockStatus = NEVER_LOCK; - break; - } - - if( CPAMPValue < CPAMPMin ) break; - - *pLockStatus = DEMOD_LOCK; - - if( m_FECTimeOut == 0 && m_bFirstTimeLock ) - { - // Release FEC and Read Solomon Reset - u8 tmp1; - u8 tmp2; - readreg(state, R367_OFDM_SFDLYSETH,&tmp1); - readreg(state, R367_TSGENERAL,&tmp2); - writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); - writereg(state, R367_TSGENERAL,tmp2 & ~0x01); - - m_FECTimeOut = Time + FECTimeOut; - } - - // Wait for TSP_LOCK, LK, PRF - if( (OFDM_Status & 0x98) != 0x98 ) - { - if( Time > m_FECTimeOut ) *pLockStatus = NEVER_LOCK; - break; - } - - if( m_bFirstTimeLock && m_TSTimeOut == 0) - { - u8 Guard = (SYR_STAT & 0x03); - if(Guard < 2) - { - u8 tmp; - readreg(state, R367_OFDM_SYR_CTL,&tmp); - writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN - readreg(state, R367_OFDM_SYR_UPDATE,&tmp); - writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER - } else { - u8 tmp; - readreg(state, R367_OFDM_SYR_CTL,&tmp); - writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN - readreg(state, R367_OFDM_SYR_UPDATE,&tmp); - writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER - } - - // apply Sfec workaround if 8K 64QAM CR!=1/2 - if( FFTMode == 1) - { - u8 tmp[2]; - readreg(state, R367_OFDM_TPS_RCVD2,tmp,2); - if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) - { - writereg(state, R367_OFDM_SFDLYSETH,0xc0); - writereg(state, R367_OFDM_SFDLYSETM,0x60); - writereg(state, R367_OFDM_SFDLYSETL,0x00); - } - else - { - writereg(state, R367_OFDM_SFDLYSETH,0x00); - } - } - - m_TSTimeOut = Time + TSTimeOut; - } - readreg(state, R367_OFDM_TSSTATUS,&TSStatus); - if( (TSStatus & 0x80) != 0x80 ) - { - if( Time > m_TSTimeOut ) *pLockStatus = NEVER_LOCK; - break; - } - *pLockStatus = MPEG_LOCK; - m_bFirstTimeLock = false; - return status; -} - -#endif - -static int read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct stv_state *state = fe->demodulator_priv; - *status=0; - - switch(state->demod_state) { - case QAMStarted: - { - u8 FEC_Lock; - u8 QAM_Lock; - - readreg(state, R367_QAM_FSM_STS, &QAM_Lock); - QAM_Lock &= 0x0F; - if (QAM_Lock >10) - *status|=0x07; - readreg(state, R367_QAM_FEC_STATUS,&FEC_Lock); - if (FEC_Lock&2) - *status|=0x1f; - if (state->m_bFirstTimeLock) { - state->m_bFirstTimeLock = false; - // QAM_AGC_ACCUMRSTSEL to Tracking; - writereg(state, R367_QAM_AGC_CTL, state->m_Save_QAM_AGC_CTL); - } - break; - } - case OFDMStarted: - { - u8 OFDM_Status; - u8 TSStatus; - - readreg(state, R367_OFDM_TSSTATUS, &TSStatus); - - readreg(state, R367_OFDM_STATUS, &OFDM_Status); - if (OFDM_Status & 0x40) - *status |= FE_HAS_SIGNAL; - - if ((OFDM_Status & 0x98) == 0x98) - *status|=0x0f; - - if (TSStatus & 0x80) - *status |= 0x1f; - break; - } - default: - break; - } - return 0; -} - -static int read_ber_ter(struct dvb_frontend *fe, u32 *ber) -{ - struct stv_state *state = fe->demodulator_priv; - u32 err; - u8 cnth, cntm, cntl; - -#if 1 - readreg(state, R367_OFDM_SFERRCNTH, &cnth); - - if (cnth & 0x80) { - *ber = state->ber; - return 0; - } - - readreg(state, R367_OFDM_SFERRCNTM, &cntm); - readreg(state, R367_OFDM_SFERRCNTL, &cntl); - - err = ((cnth & 0x7f) << 16) | (cntm << 8) | cntl; - -#if 0 - { - u64 err64; - err64 = (u64) err; - err64 *= 1000000000ULL; - err64 >>= 21; - err = err64; - } -#endif -#else - readreg(state, R367_OFDM_ERRCNT1HM, &cnth); - -#endif - *ber = state->ber = err; - return 0; -} - -static int read_ber_cab(struct dvb_frontend *fe, u32 *ber) -{ - struct stv_state *state = fe->demodulator_priv; - u32 err; - u8 cntm, cntl, ctrl; - - readreg(state, R367_QAM_BERT_1, &ctrl); - if (!(ctrl & 0x20)) { - readreg(state, R367_QAM_BERT_2, &cntl); - readreg(state, R367_QAM_BERT_3, &cntm); - err = (cntm << 8) | cntl; - //printk("err %04x\n", err); - state->ber = err; - writereg(state, R367_QAM_BERT_1, 0x27); - } - *ber = (u32) state->ber; - return 0; -} - -static int read_ber(struct dvb_frontend *fe, u32 *ber) -{ - struct stv_state *state = fe->demodulator_priv; - - if (state->demod_state == QAMStarted) - return read_ber_cab(fe, ber); - if (state->demod_state == OFDMStarted) - return read_ber_ter(fe, ber); - *ber = 0; - return 0; -} - -static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) -{ - if (fe->ops.tuner_ops.get_rf_strength) - fe->ops.tuner_ops.get_rf_strength(fe, strength); - else - *strength = 0; - return 0; -} - -static int read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct stv_state *state = fe->demodulator_priv; - s32 snr2 = 0; - - switch(state->demod_state) { - case QAMStarted: - QAM_GetSignalToNoise(state, &snr2); - break; - case OFDMStarted: - OFDM_GetSignalToNoise(state, &snr2); - break; - default: - break; - } - *snr = snr2&0xffff; - return 0; -} - -static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct stv_state *state = fe->demodulator_priv; - u8 errl, errm, errh; - u8 val; - - switch(state->demod_state) { - case QAMStarted: - readreg(state, R367_QAM_RS_COUNTER_4, &errl); - readreg(state, R367_QAM_RS_COUNTER_5, &errm); - *ucblocks = (errm << 8) | errl; - break; - case OFDMStarted: - readreg(state, R367_OFDM_SFERRCNTH, &val); - if ((val & 0x80) == 0) { - readreg(state, R367_OFDM_ERRCNT1H, &errh); - readreg(state, R367_OFDM_ERRCNT1M, &errl); - readreg(state, R367_OFDM_ERRCNT1L, &errm); - state->ucblocks = (errh <<16) | (errm << 8) | errl; - } - *ucblocks = state->ucblocks; - break; - default: - *ucblocks = 0; - break; - } - return 0; -} - -static int c_get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *sets) -{ - sets->min_delay_ms=3000; - sets->max_drift=0; - sets->step_size=0; - return 0; -} - -static int get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *sets) -{ - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBC_ANNEX_A: - case SYS_DVBC_ANNEX_C: - return c_get_tune_settings(fe, sets); - default: - /* DVB-T: Use info.frequency_stepsize. */ - return -EINVAL; - } -} - -#if 0 -static int t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -{ - //struct stv_state *state = fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - return 0; -} - -static enum dvbfe_algo algo(struct dvb_frontend *fe) -{ - return DVBFE_ALGO_CUSTOM; -} -#endif - -static struct dvb_frontend_ops common_ops = { - .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT }, - .info = { - .name = "STV0367 DVB-C DVB-T", - .frequency_stepsize = 166667, /* DVB-T only */ - .frequency_min = 47000000, /* DVB-T: 47125000 */ - .frequency_max = 865000000, /* DVB-C: 862000000 */ - .symbol_rate_min = 870000, - .symbol_rate_max = 11700000, - .caps = /* DVB-C */ - FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | - FE_CAN_QAM_128 | FE_CAN_QAM_256 | - FE_CAN_FEC_AUTO | - /* DVB-T */ - FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | - FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | - FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | - FE_CAN_RECOVER | FE_CAN_MUTE_TS - }, - .release = release, - .i2c_gate_ctrl = gate_ctrl, - - .get_tune_settings = get_tune_settings, - - .set_frontend = set_parameters, - - .read_status = read_status, - .read_ber = read_ber, - .read_signal_strength = read_signal_strength, - .read_snr = read_snr, - .read_ucblocks = read_ucblocks, -}; - - -static void init_state(struct stv_state *state, struct stv0367_cfg *cfg) -{ - u32 ulENARPTLEVEL = 5; - u32 ulQAMInversion = 2; - state->omode = OM_NONE; - state->adr = cfg->adr; - state->cont_clock = cfg->cont_clock; - - mutex_init(&state->mutex); - mutex_init(&state->ctlock); - - memcpy(&state->frontend.ops, &common_ops, sizeof(struct dvb_frontend_ops)); - state->frontend.demodulator_priv = state; - - state->master_clock = 58000000; - state->adc_clock = 58000000; - state->I2CRPT = 0x08 | ((ulENARPTLEVEL & 0x07) << 4); - state->qam_inversion = ((ulQAMInversion & 3) << 6 ); - state->demod_state = Off; -} - - -struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, struct stv0367_cfg *cfg, - struct dvb_frontend **fe_t) -{ - struct stv_state *state = NULL; - - state = kzalloc(sizeof(struct stv_state), GFP_KERNEL); - if (!state) - return NULL; - - state->i2c = i2c; - init_state(state, cfg); - - if (attach_init(state)<0) - goto error; - return &state->frontend; - -error: - printk("stv0367: not found\n"); - kfree(state); - return NULL; -} - - -MODULE_DESCRIPTION("STV0367DD driver"); -MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); -MODULE_LICENSE("GPL"); - -EXPORT_SYMBOL(stv0367_attach); - - - +/* + * stv0367dd: STV0367 DVB-C/T demodulator driver + * + * Copyright (C) 2011 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "stv0367dd.h" +#include "stv0367dd_regs.h" + +enum omode { OM_NONE, OM_DVBT, OM_DVBC, OM_QAM_ITU_C }; +enum { QAM_MOD_QAM4 = 0, + QAM_MOD_QAM16, + QAM_MOD_QAM32, + QAM_MOD_QAM64, + QAM_MOD_QAM128, + QAM_MOD_QAM256, + QAM_MOD_QAM512, + QAM_MOD_QAM1024 +}; + +enum {QAM_SPECT_NORMAL, QAM_SPECT_INVERTED }; + +enum { + QAM_FEC_A = 1, /* J83 Annex A */ + QAM_FEC_B = (1<<1), /* J83 Annex B */ + QAM_FEC_C = (1<<2) /* J83 Annex C */ +}; + +enum EDemodState { Off, QAMSet, OFDMSet, QAMStarted, OFDMStarted }; + +struct stv_state { + struct dvb_frontend frontend; + fe_modulation_t modulation; + u32 symbol_rate; + u32 bandwidth; + struct device *dev; + + struct i2c_adapter *i2c; + u8 adr; + u8 cont_clock; + void *priv; + + struct mutex mutex; + struct mutex ctlock; + + u32 master_clock; + u32 adc_clock; + u8 ID; + u8 I2CRPT; + u32 omode; + u8 qam_inversion; + + s32 IF; + + s32 m_FECTimeOut; + s32 m_DemodTimeOut; + s32 m_SignalTimeOut; + s32 m_DemodLockTime; + s32 m_FFTTimeOut; + s32 m_TSTimeOut; + + bool m_bFirstTimeLock; + + u8 m_Save_QAM_AGC_CTL; + + enum EDemodState demod_state; + + u8 m_OFDM_FFTMode; // 0 = 2k, 1 = 8k, 2 = 4k + u8 m_OFDM_Modulation; // + u8 m_OFDM_FEC; // + u8 m_OFDM_Guard; + + u32 ucblocks; + u32 ber; +}; + +struct init_table { + u16 adr; + u8 data; +}; + +struct init_table base_init[] = { + { R367_IOCFG0, 0x80 }, + { R367_DAC0R, 0x00 }, + { R367_IOCFG1, 0x00 }, + { R367_DAC1R, 0x00 }, + { R367_IOCFG2, 0x00 }, + { R367_SDFR, 0x00 }, + { R367_AUX_CLK, 0x00 }, + { R367_FREESYS1, 0x00 }, + { R367_FREESYS2, 0x00 }, + { R367_FREESYS3, 0x00 }, + { R367_GPIO_CFG, 0x55 }, + { R367_GPIO_CMD, 0x01 }, + { R367_TSTRES, 0x00 }, + { R367_ANACTRL, 0x00 }, + { R367_TSTBUS, 0x00 }, + { R367_RF_AGC2, 0x20 }, + { R367_ANADIGCTRL, 0x0b }, + { R367_PLLMDIV, 0x01 }, + { R367_PLLNDIV, 0x08 }, + { R367_PLLSETUP, 0x18 }, + { R367_DUAL_AD12, 0x04 }, + { R367_TSTBIST, 0x00 }, + { 0x0000, 0x00 } +}; + +struct init_table qam_init[] = { + { R367_QAM_CTRL_1, 0x06 },// Orginal 0x04 + { R367_QAM_CTRL_2, 0x03 }, + { R367_QAM_IT_STATUS1, 0x2b }, + { R367_QAM_IT_STATUS2, 0x08 }, + { R367_QAM_IT_EN1, 0x00 }, + { R367_QAM_IT_EN2, 0x00 }, + { R367_QAM_CTRL_STATUS, 0x04 }, + { R367_QAM_TEST_CTL, 0x00 }, + { R367_QAM_AGC_CTL, 0x73 }, + { R367_QAM_AGC_IF_CFG, 0x50 }, + { R367_QAM_AGC_RF_CFG, 0x02 },// RF Freeze + { R367_QAM_AGC_PWM_CFG, 0x03 }, + { R367_QAM_AGC_PWR_REF_L, 0x5a }, + { R367_QAM_AGC_PWR_REF_H, 0x00 }, + { R367_QAM_AGC_RF_TH_L, 0xff }, + { R367_QAM_AGC_RF_TH_H, 0x07 }, + { R367_QAM_AGC_IF_LTH_L, 0x00 }, + { R367_QAM_AGC_IF_LTH_H, 0x08 }, + { R367_QAM_AGC_IF_HTH_L, 0xff }, + { R367_QAM_AGC_IF_HTH_H, 0x07 }, + { R367_QAM_AGC_PWR_RD_L, 0xa0 }, + { R367_QAM_AGC_PWR_RD_M, 0xe9 }, + { R367_QAM_AGC_PWR_RD_H, 0x03 }, + { R367_QAM_AGC_PWM_IFCMD_L, 0xe4 }, + { R367_QAM_AGC_PWM_IFCMD_H, 0x00 }, + { R367_QAM_AGC_PWM_RFCMD_L, 0xff }, + { R367_QAM_AGC_PWM_RFCMD_H, 0x07 }, + { R367_QAM_IQDEM_CFG, 0x01 }, + { R367_QAM_MIX_NCO_LL, 0x22 }, + { R367_QAM_MIX_NCO_HL, 0x96 }, + { R367_QAM_MIX_NCO_HH, 0x55 }, + { R367_QAM_SRC_NCO_LL, 0xff }, + { R367_QAM_SRC_NCO_LH, 0x0c }, + { R367_QAM_SRC_NCO_HL, 0xf5 }, + { R367_QAM_SRC_NCO_HH, 0x20 }, + { R367_QAM_IQDEM_GAIN_SRC_L, 0x06 }, + { R367_QAM_IQDEM_GAIN_SRC_H, 0x01 }, + { R367_QAM_IQDEM_DCRM_CFG_LL, 0xfe }, + { R367_QAM_IQDEM_DCRM_CFG_LH, 0xff }, + { R367_QAM_IQDEM_DCRM_CFG_HL, 0x0f }, + { R367_QAM_IQDEM_DCRM_CFG_HH, 0x00 }, + { R367_QAM_IQDEM_ADJ_COEFF0, 0x34 }, + { R367_QAM_IQDEM_ADJ_COEFF1, 0xae }, + { R367_QAM_IQDEM_ADJ_COEFF2, 0x46 }, + { R367_QAM_IQDEM_ADJ_COEFF3, 0x77 }, + { R367_QAM_IQDEM_ADJ_COEFF4, 0x96 }, + { R367_QAM_IQDEM_ADJ_COEFF5, 0x69 }, + { R367_QAM_IQDEM_ADJ_COEFF6, 0xc7 }, + { R367_QAM_IQDEM_ADJ_COEFF7, 0x01 }, + { R367_QAM_IQDEM_ADJ_EN, 0x04 }, + { R367_QAM_IQDEM_ADJ_AGC_REF, 0x94 }, + { R367_QAM_ALLPASSFILT1, 0xc9 }, + { R367_QAM_ALLPASSFILT2, 0x2d }, + { R367_QAM_ALLPASSFILT3, 0xa3 }, + { R367_QAM_ALLPASSFILT4, 0xfb }, + { R367_QAM_ALLPASSFILT5, 0xf6 }, + { R367_QAM_ALLPASSFILT6, 0x45 }, + { R367_QAM_ALLPASSFILT7, 0x6f }, + { R367_QAM_ALLPASSFILT8, 0x7e }, + { R367_QAM_ALLPASSFILT9, 0x05 }, + { R367_QAM_ALLPASSFILT10, 0x0a }, + { R367_QAM_ALLPASSFILT11, 0x51 }, + { R367_QAM_TRL_AGC_CFG, 0x20 }, + { R367_QAM_TRL_LPF_CFG, 0x28 }, + { R367_QAM_TRL_LPF_ACQ_GAIN, 0x44 }, + { R367_QAM_TRL_LPF_TRK_GAIN, 0x22 }, + { R367_QAM_TRL_LPF_OUT_GAIN, 0x03 }, + { R367_QAM_TRL_LOCKDET_LTH, 0x04 }, + { R367_QAM_TRL_LOCKDET_HTH, 0x11 }, + { R367_QAM_TRL_LOCKDET_TRGVAL, 0x20 }, + { R367_QAM_IQ_QAM, 0x01 }, + { R367_QAM_FSM_STATE, 0xa0 }, + { R367_QAM_FSM_CTL, 0x08 }, + { R367_QAM_FSM_STS, 0x0c }, + { R367_QAM_FSM_SNR0_HTH, 0x00 }, + { R367_QAM_FSM_SNR1_HTH, 0x00 }, + { R367_QAM_FSM_SNR2_HTH, 0x00 }, + { R367_QAM_FSM_SNR0_LTH, 0x00 }, + { R367_QAM_FSM_SNR1_LTH, 0x00 }, + { R367_QAM_FSM_EQA1_HTH, 0x00 }, + { R367_QAM_FSM_TEMPO, 0x32 }, + { R367_QAM_FSM_CONFIG, 0x03 }, + { R367_QAM_EQU_I_TESTTAP_L, 0x11 }, + { R367_QAM_EQU_I_TESTTAP_M, 0x00 }, + { R367_QAM_EQU_I_TESTTAP_H, 0x00 }, + { R367_QAM_EQU_TESTAP_CFG, 0x00 }, + { R367_QAM_EQU_Q_TESTTAP_L, 0xff }, + { R367_QAM_EQU_Q_TESTTAP_M, 0x00 }, + { R367_QAM_EQU_Q_TESTTAP_H, 0x00 }, + { R367_QAM_EQU_TAP_CTRL, 0x00 }, + { R367_QAM_EQU_CTR_CRL_CONTROL_L, 0x11 }, + { R367_QAM_EQU_CTR_CRL_CONTROL_H, 0x05 }, + { R367_QAM_EQU_CTR_HIPOW_L, 0x00 }, + { R367_QAM_EQU_CTR_HIPOW_H, 0x00 }, + { R367_QAM_EQU_I_EQU_LO, 0xef }, + { R367_QAM_EQU_I_EQU_HI, 0x00 }, + { R367_QAM_EQU_Q_EQU_LO, 0xee }, + { R367_QAM_EQU_Q_EQU_HI, 0x00 }, + { R367_QAM_EQU_MAPPER, 0xc5 }, + { R367_QAM_EQU_SWEEP_RATE, 0x80 }, + { R367_QAM_EQU_SNR_LO, 0x64 }, + { R367_QAM_EQU_SNR_HI, 0x03 }, + { R367_QAM_EQU_GAMMA_LO, 0x00 }, + { R367_QAM_EQU_GAMMA_HI, 0x00 }, + { R367_QAM_EQU_ERR_GAIN, 0x36 }, + { R367_QAM_EQU_RADIUS, 0xaa }, + { R367_QAM_EQU_FFE_MAINTAP, 0x00 }, + { R367_QAM_EQU_FFE_LEAKAGE, 0x63 }, + { R367_QAM_EQU_FFE_MAINTAP_POS, 0xdf }, + { R367_QAM_EQU_GAIN_WIDE, 0x88 }, + { R367_QAM_EQU_GAIN_NARROW, 0x41 }, + { R367_QAM_EQU_CTR_LPF_GAIN, 0xd1 }, + { R367_QAM_EQU_CRL_LPF_GAIN, 0xa7 }, + { R367_QAM_EQU_GLOBAL_GAIN, 0x06 }, + { R367_QAM_EQU_CRL_LD_SEN, 0x85 }, + { R367_QAM_EQU_CRL_LD_VAL, 0xe2 }, + { R367_QAM_EQU_CRL_TFR, 0x20 }, + { R367_QAM_EQU_CRL_BISTH_LO, 0x00 }, + { R367_QAM_EQU_CRL_BISTH_HI, 0x00 }, + { R367_QAM_EQU_SWEEP_RANGE_LO, 0x00 }, + { R367_QAM_EQU_SWEEP_RANGE_HI, 0x00 }, + { R367_QAM_EQU_CRL_LIMITER, 0x40 }, + { R367_QAM_EQU_MODULUS_MAP, 0x90 }, + { R367_QAM_EQU_PNT_GAIN, 0xa7 }, + { R367_QAM_FEC_AC_CTR_0, 0x16 }, + { R367_QAM_FEC_AC_CTR_1, 0x0b }, + { R367_QAM_FEC_AC_CTR_2, 0x88 }, + { R367_QAM_FEC_AC_CTR_3, 0x02 }, + { R367_QAM_FEC_STATUS, 0x12 }, + { R367_QAM_RS_COUNTER_0, 0x7d }, + { R367_QAM_RS_COUNTER_1, 0xd0 }, + { R367_QAM_RS_COUNTER_2, 0x19 }, + { R367_QAM_RS_COUNTER_3, 0x0b }, + { R367_QAM_RS_COUNTER_4, 0xa3 }, + { R367_QAM_RS_COUNTER_5, 0x00 }, + { R367_QAM_BERT_0, 0x01 }, + { R367_QAM_BERT_1, 0x25 }, + { R367_QAM_BERT_2, 0x41 }, + { R367_QAM_BERT_3, 0x39 }, + { R367_QAM_OUTFORMAT_0, 0xc2 }, + { R367_QAM_OUTFORMAT_1, 0x22 }, + { R367_QAM_SMOOTHER_2, 0x28 }, + { R367_QAM_TSMF_CTRL_0, 0x01 }, + { R367_QAM_TSMF_CTRL_1, 0xc6 }, + { R367_QAM_TSMF_CTRL_3, 0x43 }, + { R367_QAM_TS_ON_ID_0, 0x00 }, + { R367_QAM_TS_ON_ID_1, 0x00 }, + { R367_QAM_TS_ON_ID_2, 0x00 }, + { R367_QAM_TS_ON_ID_3, 0x00 }, + { R367_QAM_RE_STATUS_0, 0x00 }, + { R367_QAM_RE_STATUS_1, 0x00 }, + { R367_QAM_RE_STATUS_2, 0x00 }, + { R367_QAM_RE_STATUS_3, 0x00 }, + { R367_QAM_TS_STATUS_0, 0x00 }, + { R367_QAM_TS_STATUS_1, 0x00 }, + { R367_QAM_TS_STATUS_2, 0xa0 }, + { R367_QAM_TS_STATUS_3, 0x00 }, + { R367_QAM_T_O_ID_0, 0x00 }, + { R367_QAM_T_O_ID_1, 0x00 }, + { R367_QAM_T_O_ID_2, 0x00 }, + { R367_QAM_T_O_ID_3, 0x00 }, + { 0x0000, 0x00 } // EOT +}; + +struct init_table ofdm_init[] = { + //{R367_OFDM_ID ,0x60}, + //{R367_OFDM_I2CRPT ,0x22}, + //{R367_OFDM_TOPCTRL ,0x02}, + //{R367_OFDM_IOCFG0 ,0x40}, + //{R367_OFDM_DAC0R ,0x00}, + //{R367_OFDM_IOCFG1 ,0x00}, + //{R367_OFDM_DAC1R ,0x00}, + //{R367_OFDM_IOCFG2 ,0x62}, + //{R367_OFDM_SDFR ,0x00}, + //{R367_OFDM_STATUS ,0xf8}, + //{R367_OFDM_AUX_CLK ,0x0a}, + //{R367_OFDM_FREESYS1 ,0x00}, + //{R367_OFDM_FREESYS2 ,0x00}, + //{R367_OFDM_FREESYS3 ,0x00}, + //{R367_OFDM_GPIO_CFG ,0x55}, + //{R367_OFDM_GPIO_CMD ,0x00}, + {R367_OFDM_AGC2MAX ,0xff}, + {R367_OFDM_AGC2MIN ,0x00}, + {R367_OFDM_AGC1MAX ,0xff}, + {R367_OFDM_AGC1MIN ,0x00}, + {R367_OFDM_AGCR ,0xbc}, + {R367_OFDM_AGC2TH ,0x00}, + //{R367_OFDM_AGC12C ,0x01}, //Note: This defines AGC pins, also needed for QAM + {R367_OFDM_AGCCTRL1 ,0x85}, + {R367_OFDM_AGCCTRL2 ,0x1f}, + {R367_OFDM_AGC1VAL1 ,0x00}, + {R367_OFDM_AGC1VAL2 ,0x00}, + {R367_OFDM_AGC2VAL1 ,0x6f}, + {R367_OFDM_AGC2VAL2 ,0x05}, + {R367_OFDM_AGC2PGA ,0x00}, + {R367_OFDM_OVF_RATE1 ,0x00}, + {R367_OFDM_OVF_RATE2 ,0x00}, + {R367_OFDM_GAIN_SRC1 ,0x2b}, + {R367_OFDM_GAIN_SRC2 ,0x04}, + {R367_OFDM_INC_DEROT1 ,0x55}, + {R367_OFDM_INC_DEROT2 ,0x55}, + {R367_OFDM_PPM_CPAMP_DIR ,0x2c}, + {R367_OFDM_PPM_CPAMP_INV ,0x00}, + {R367_OFDM_FREESTFE_1 ,0x00}, + {R367_OFDM_FREESTFE_2 ,0x1c}, + {R367_OFDM_DCOFFSET ,0x00}, + {R367_OFDM_EN_PROCESS ,0x05}, + {R367_OFDM_SDI_SMOOTHER ,0x80}, + {R367_OFDM_FE_LOOP_OPEN ,0x1c}, + {R367_OFDM_FREQOFF1 ,0x00}, + {R367_OFDM_FREQOFF2 ,0x00}, + {R367_OFDM_FREQOFF3 ,0x00}, + {R367_OFDM_TIMOFF1 ,0x00}, + {R367_OFDM_TIMOFF2 ,0x00}, + {R367_OFDM_EPQ ,0x02}, + {R367_OFDM_EPQAUTO ,0x01}, + {R367_OFDM_SYR_UPDATE ,0xf5}, + {R367_OFDM_CHPFREE ,0x00}, + {R367_OFDM_PPM_STATE_MAC ,0x23}, + {R367_OFDM_INR_THRESHOLD ,0xff}, + {R367_OFDM_EPQ_TPS_ID_CELL ,0xf9}, + {R367_OFDM_EPQ_CFG ,0x00}, + {R367_OFDM_EPQ_STATUS ,0x01}, + {R367_OFDM_AUTORELOCK ,0x81}, + {R367_OFDM_BER_THR_VMSB ,0x00}, + {R367_OFDM_BER_THR_MSB ,0x00}, + {R367_OFDM_BER_THR_LSB ,0x00}, + {R367_OFDM_CCD ,0x83}, + {R367_OFDM_SPECTR_CFG ,0x00}, + {R367_OFDM_CHC_DUMMY ,0x18}, + {R367_OFDM_INC_CTL ,0x88}, + {R367_OFDM_INCTHRES_COR1 ,0xb4}, + {R367_OFDM_INCTHRES_COR2 ,0x96}, + {R367_OFDM_INCTHRES_DET1 ,0x0e}, + {R367_OFDM_INCTHRES_DET2 ,0x11}, + {R367_OFDM_IIR_CELLNB ,0x8d}, + {R367_OFDM_IIRCX_COEFF1_MSB ,0x00}, + {R367_OFDM_IIRCX_COEFF1_LSB ,0x00}, + {R367_OFDM_IIRCX_COEFF2_MSB ,0x09}, + {R367_OFDM_IIRCX_COEFF2_LSB ,0x18}, + {R367_OFDM_IIRCX_COEFF3_MSB ,0x14}, + {R367_OFDM_IIRCX_COEFF3_LSB ,0x9c}, + {R367_OFDM_IIRCX_COEFF4_MSB ,0x00}, + {R367_OFDM_IIRCX_COEFF4_LSB ,0x00}, + {R367_OFDM_IIRCX_COEFF5_MSB ,0x36}, + {R367_OFDM_IIRCX_COEFF5_LSB ,0x42}, + {R367_OFDM_FEPATH_CFG ,0x00}, + {R367_OFDM_PMC1_FUNC ,0x65}, + {R367_OFDM_PMC1_FOR ,0x00}, + {R367_OFDM_PMC2_FUNC ,0x00}, + {R367_OFDM_STATUS_ERR_DA ,0xe0}, + {R367_OFDM_DIG_AGC_R ,0xfe}, + {R367_OFDM_COMAGC_TARMSB ,0x0b}, + {R367_OFDM_COM_AGC_TAR_ENMODE ,0x41}, + {R367_OFDM_COM_AGC_CFG ,0x3e}, + {R367_OFDM_COM_AGC_GAIN1 ,0x39}, + {R367_OFDM_AUT_AGC_TARGETMSB ,0x0b}, + {R367_OFDM_LOCK_DET_MSB ,0x01}, + {R367_OFDM_AGCTAR_LOCK_LSBS ,0x40}, + {R367_OFDM_AUT_GAIN_EN ,0xf4}, + {R367_OFDM_AUT_CFG ,0xf0}, + {R367_OFDM_LOCKN ,0x23}, + {R367_OFDM_INT_X_3 ,0x00}, + {R367_OFDM_INT_X_2 ,0x03}, + {R367_OFDM_INT_X_1 ,0x8d}, + {R367_OFDM_INT_X_0 ,0xa0}, + {R367_OFDM_MIN_ERRX_MSB ,0x00}, + {R367_OFDM_COR_CTL ,0x00}, + {R367_OFDM_COR_STAT ,0xf6}, + {R367_OFDM_COR_INTEN ,0x00}, + {R367_OFDM_COR_INTSTAT ,0x3f}, + {R367_OFDM_COR_MODEGUARD ,0x03}, + {R367_OFDM_AGC_CTL ,0x08}, + {R367_OFDM_AGC_MANUAL1 ,0x00}, + {R367_OFDM_AGC_MANUAL2 ,0x00}, + {R367_OFDM_AGC_TARG ,0x16}, + {R367_OFDM_AGC_GAIN1 ,0x53}, + {R367_OFDM_AGC_GAIN2 ,0x1d}, + {R367_OFDM_RESERVED_1 ,0x00}, + {R367_OFDM_RESERVED_2 ,0x00}, + {R367_OFDM_RESERVED_3 ,0x00}, + {R367_OFDM_CAS_CTL ,0x44}, + {R367_OFDM_CAS_FREQ ,0xb3}, + {R367_OFDM_CAS_DAGCGAIN ,0x12}, + {R367_OFDM_SYR_CTL ,0x04}, + {R367_OFDM_SYR_STAT ,0x10}, + {R367_OFDM_SYR_NCO1 ,0x00}, + {R367_OFDM_SYR_NCO2 ,0x00}, + {R367_OFDM_SYR_OFFSET1 ,0x00}, + {R367_OFDM_SYR_OFFSET2 ,0x00}, + {R367_OFDM_FFT_CTL ,0x00}, + {R367_OFDM_SCR_CTL ,0x70}, + {R367_OFDM_PPM_CTL1 ,0xf8}, + {R367_OFDM_TRL_CTL ,0xac}, + {R367_OFDM_TRL_NOMRATE1 ,0x1e}, + {R367_OFDM_TRL_NOMRATE2 ,0x58}, + {R367_OFDM_TRL_TIME1 ,0x1d}, + {R367_OFDM_TRL_TIME2 ,0xfc}, + {R367_OFDM_CRL_CTL ,0x24}, + {R367_OFDM_CRL_FREQ1 ,0xad}, + {R367_OFDM_CRL_FREQ2 ,0x9d}, + {R367_OFDM_CRL_FREQ3 ,0xff}, + {R367_OFDM_CHC_CTL ,0x01}, + {R367_OFDM_CHC_SNR ,0xf0}, + {R367_OFDM_BDI_CTL ,0x00}, + {R367_OFDM_DMP_CTL ,0x00}, + {R367_OFDM_TPS_RCVD1 ,0x30}, + {R367_OFDM_TPS_RCVD2 ,0x02}, + {R367_OFDM_TPS_RCVD3 ,0x01}, + {R367_OFDM_TPS_RCVD4 ,0x00}, + {R367_OFDM_TPS_ID_CELL1 ,0x00}, + {R367_OFDM_TPS_ID_CELL2 ,0x00}, + {R367_OFDM_TPS_RCVD5_SET1 ,0x02}, + {R367_OFDM_TPS_SET2 ,0x02}, + {R367_OFDM_TPS_SET3 ,0x01}, + {R367_OFDM_TPS_CTL ,0x00}, + {R367_OFDM_CTL_FFTOSNUM ,0x34}, + {R367_OFDM_TESTSELECT ,0x09}, + {R367_OFDM_MSC_REV ,0x0a}, + {R367_OFDM_PIR_CTL ,0x00}, + {R367_OFDM_SNR_CARRIER1 ,0xa1}, + {R367_OFDM_SNR_CARRIER2 ,0x9a}, + {R367_OFDM_PPM_CPAMP ,0x2c}, + {R367_OFDM_TSM_AP0 ,0x00}, + {R367_OFDM_TSM_AP1 ,0x00}, + {R367_OFDM_TSM_AP2 ,0x00}, + {R367_OFDM_TSM_AP3 ,0x00}, + {R367_OFDM_TSM_AP4 ,0x00}, + {R367_OFDM_TSM_AP5 ,0x00}, + {R367_OFDM_TSM_AP6 ,0x00}, + {R367_OFDM_TSM_AP7 ,0x00}, + //{R367_OFDM_TSTRES ,0x00}, + //{R367_OFDM_ANACTRL ,0x0D},/*caution PLL stopped, to be restarted at init!!!*/ + //{R367_OFDM_TSTBUS ,0x00}, + //{R367_OFDM_TSTRATE ,0x00}, + {R367_OFDM_CONSTMODE ,0x01}, + {R367_OFDM_CONSTCARR1 ,0x00}, + {R367_OFDM_CONSTCARR2 ,0x00}, + {R367_OFDM_ICONSTEL ,0x0a}, + {R367_OFDM_QCONSTEL ,0x15}, + {R367_OFDM_TSTBISTRES0 ,0x00}, + {R367_OFDM_TSTBISTRES1 ,0x00}, + {R367_OFDM_TSTBISTRES2 ,0x28}, + {R367_OFDM_TSTBISTRES3 ,0x00}, + //{R367_OFDM_RF_AGC1 ,0xff}, + //{R367_OFDM_RF_AGC2 ,0x83}, + //{R367_OFDM_ANADIGCTRL ,0x19}, + //{R367_OFDM_PLLMDIV ,0x0c}, + //{R367_OFDM_PLLNDIV ,0x55}, + //{R367_OFDM_PLLSETUP ,0x18}, + //{R367_OFDM_DUAL_AD12 ,0x00}, + //{R367_OFDM_TSTBIST ,0x00}, + //{R367_OFDM_PAD_COMP_CTRL ,0x00}, + //{R367_OFDM_PAD_COMP_WR ,0x00}, + //{R367_OFDM_PAD_COMP_RD ,0xe0}, + {R367_OFDM_SYR_TARGET_FFTADJT_MSB ,0x00}, + {R367_OFDM_SYR_TARGET_FFTADJT_LSB ,0x00}, + {R367_OFDM_SYR_TARGET_CHCADJT_MSB ,0x00}, + {R367_OFDM_SYR_TARGET_CHCADJT_LSB ,0x00}, + {R367_OFDM_SYR_FLAG ,0x00}, + {R367_OFDM_CRL_TARGET1 ,0x00}, + {R367_OFDM_CRL_TARGET2 ,0x00}, + {R367_OFDM_CRL_TARGET3 ,0x00}, + {R367_OFDM_CRL_TARGET4 ,0x00}, + {R367_OFDM_CRL_FLAG ,0x00}, + {R367_OFDM_TRL_TARGET1 ,0x00}, + {R367_OFDM_TRL_TARGET2 ,0x00}, + {R367_OFDM_TRL_CHC ,0x00}, + {R367_OFDM_CHC_SNR_TARG ,0x00}, + {R367_OFDM_TOP_TRACK ,0x00}, + {R367_OFDM_TRACKER_FREE1 ,0x00}, + {R367_OFDM_ERROR_CRL1 ,0x00}, + {R367_OFDM_ERROR_CRL2 ,0x00}, + {R367_OFDM_ERROR_CRL3 ,0x00}, + {R367_OFDM_ERROR_CRL4 ,0x00}, + {R367_OFDM_DEC_NCO1 ,0x2c}, + {R367_OFDM_DEC_NCO2 ,0x0f}, + {R367_OFDM_DEC_NCO3 ,0x20}, + {R367_OFDM_SNR ,0xf1}, + {R367_OFDM_SYR_FFTADJ1 ,0x00}, + {R367_OFDM_SYR_FFTADJ2 ,0x00}, + {R367_OFDM_SYR_CHCADJ1 ,0x00}, + {R367_OFDM_SYR_CHCADJ2 ,0x00}, + {R367_OFDM_SYR_OFF ,0x00}, + {R367_OFDM_PPM_OFFSET1 ,0x00}, + {R367_OFDM_PPM_OFFSET2 ,0x03}, + {R367_OFDM_TRACKER_FREE2 ,0x00}, + {R367_OFDM_DEBG_LT10 ,0x00}, + {R367_OFDM_DEBG_LT11 ,0x00}, + {R367_OFDM_DEBG_LT12 ,0x00}, + {R367_OFDM_DEBG_LT13 ,0x00}, + {R367_OFDM_DEBG_LT14 ,0x00}, + {R367_OFDM_DEBG_LT15 ,0x00}, + {R367_OFDM_DEBG_LT16 ,0x00}, + {R367_OFDM_DEBG_LT17 ,0x00}, + {R367_OFDM_DEBG_LT18 ,0x00}, + {R367_OFDM_DEBG_LT19 ,0x00}, + {R367_OFDM_DEBG_LT1A ,0x00}, + {R367_OFDM_DEBG_LT1B ,0x00}, + {R367_OFDM_DEBG_LT1C ,0x00}, + {R367_OFDM_DEBG_LT1D ,0x00}, + {R367_OFDM_DEBG_LT1E ,0x00}, + {R367_OFDM_DEBG_LT1F ,0x00}, + {R367_OFDM_RCCFGH ,0x00}, + {R367_OFDM_RCCFGM ,0x00}, + {R367_OFDM_RCCFGL ,0x00}, + {R367_OFDM_RCINSDELH ,0x00}, + {R367_OFDM_RCINSDELM ,0x00}, + {R367_OFDM_RCINSDELL ,0x00}, + {R367_OFDM_RCSTATUS ,0x00}, + {R367_OFDM_RCSPEED ,0x6f}, + {R367_OFDM_RCDEBUGM ,0xe7}, + {R367_OFDM_RCDEBUGL ,0x9b}, + {R367_OFDM_RCOBSCFG ,0x00}, + {R367_OFDM_RCOBSM ,0x00}, + {R367_OFDM_RCOBSL ,0x00}, + {R367_OFDM_RCFECSPY ,0x00}, + {R367_OFDM_RCFSPYCFG ,0x00}, + {R367_OFDM_RCFSPYDATA ,0x00}, + {R367_OFDM_RCFSPYOUT ,0x00}, + {R367_OFDM_RCFSTATUS ,0x00}, + {R367_OFDM_RCFGOODPACK ,0x00}, + {R367_OFDM_RCFPACKCNT ,0x00}, + {R367_OFDM_RCFSPYMISC ,0x00}, + {R367_OFDM_RCFBERCPT4 ,0x00}, + {R367_OFDM_RCFBERCPT3 ,0x00}, + {R367_OFDM_RCFBERCPT2 ,0x00}, + {R367_OFDM_RCFBERCPT1 ,0x00}, + {R367_OFDM_RCFBERCPT0 ,0x00}, + {R367_OFDM_RCFBERERR2 ,0x00}, + {R367_OFDM_RCFBERERR1 ,0x00}, + {R367_OFDM_RCFBERERR0 ,0x00}, + {R367_OFDM_RCFSTATESM ,0x00}, + {R367_OFDM_RCFSTATESL ,0x00}, + {R367_OFDM_RCFSPYBER ,0x00}, + {R367_OFDM_RCFSPYDISTM ,0x00}, + {R367_OFDM_RCFSPYDISTL ,0x00}, + {R367_OFDM_RCFSPYOBS7 ,0x00}, + {R367_OFDM_RCFSPYOBS6 ,0x00}, + {R367_OFDM_RCFSPYOBS5 ,0x00}, + {R367_OFDM_RCFSPYOBS4 ,0x00}, + {R367_OFDM_RCFSPYOBS3 ,0x00}, + {R367_OFDM_RCFSPYOBS2 ,0x00}, + {R367_OFDM_RCFSPYOBS1 ,0x00}, + {R367_OFDM_RCFSPYOBS0 ,0x00}, + //{R367_OFDM_TSGENERAL ,0x00}, + //{R367_OFDM_RC1SPEED ,0x6f}, + //{R367_OFDM_TSGSTATUS ,0x18}, + {R367_OFDM_FECM ,0x01}, + {R367_OFDM_VTH12 ,0xff}, + {R367_OFDM_VTH23 ,0xa1}, + {R367_OFDM_VTH34 ,0x64}, + {R367_OFDM_VTH56 ,0x40}, + {R367_OFDM_VTH67 ,0x00}, + {R367_OFDM_VTH78 ,0x2c}, + {R367_OFDM_VITCURPUN ,0x12}, + {R367_OFDM_VERROR ,0x01}, + {R367_OFDM_PRVIT ,0x3f}, + {R367_OFDM_VAVSRVIT ,0x00}, + {R367_OFDM_VSTATUSVIT ,0xbd}, + {R367_OFDM_VTHINUSE ,0xa1}, + {R367_OFDM_KDIV12 ,0x20}, + {R367_OFDM_KDIV23 ,0x40}, + {R367_OFDM_KDIV34 ,0x20}, + {R367_OFDM_KDIV56 ,0x30}, + {R367_OFDM_KDIV67 ,0x00}, + {R367_OFDM_KDIV78 ,0x30}, + {R367_OFDM_SIGPOWER ,0x54}, + {R367_OFDM_DEMAPVIT ,0x40}, + {R367_OFDM_VITSCALE ,0x00}, + {R367_OFDM_FFEC1PRG ,0x00}, + {R367_OFDM_FVITCURPUN ,0x12}, + {R367_OFDM_FVERROR ,0x01}, + {R367_OFDM_FVSTATUSVIT ,0xbd}, + {R367_OFDM_DEBUG_LT1 ,0x00}, + {R367_OFDM_DEBUG_LT2 ,0x00}, + {R367_OFDM_DEBUG_LT3 ,0x00}, + {R367_OFDM_TSTSFMET ,0x00}, + {R367_OFDM_SELOUT ,0x00}, + {R367_OFDM_TSYNC ,0x00}, + {R367_OFDM_TSTERR ,0x00}, + {R367_OFDM_TSFSYNC ,0x00}, + {R367_OFDM_TSTSFERR ,0x00}, + {R367_OFDM_TSTTSSF1 ,0x01}, + {R367_OFDM_TSTTSSF2 ,0x1f}, + {R367_OFDM_TSTTSSF3 ,0x00}, + {R367_OFDM_TSTTS1 ,0x00}, + {R367_OFDM_TSTTS2 ,0x1f}, + {R367_OFDM_TSTTS3 ,0x01}, + {R367_OFDM_TSTTS4 ,0x00}, + {R367_OFDM_TSTTSRC ,0x00}, + {R367_OFDM_TSTTSRS ,0x00}, + {R367_OFDM_TSSTATEM ,0xb0}, + {R367_OFDM_TSSTATEL ,0x40}, + {R367_OFDM_TSCFGH ,0x80}, + {R367_OFDM_TSCFGM ,0x00}, + {R367_OFDM_TSCFGL ,0x20}, + {R367_OFDM_TSSYNC ,0x00}, + {R367_OFDM_TSINSDELH ,0x00}, + {R367_OFDM_TSINSDELM ,0x00}, + {R367_OFDM_TSINSDELL ,0x00}, + {R367_OFDM_TSDIVN ,0x03}, + {R367_OFDM_TSDIVPM ,0x00}, + {R367_OFDM_TSDIVPL ,0x00}, + {R367_OFDM_TSDIVQM ,0x00}, + {R367_OFDM_TSDIVQL ,0x00}, + {R367_OFDM_TSDILSTKM ,0x00}, + {R367_OFDM_TSDILSTKL ,0x00}, + {R367_OFDM_TSSPEED ,0x6f}, + {R367_OFDM_TSSTATUS ,0x81}, + {R367_OFDM_TSSTATUS2 ,0x6a}, + {R367_OFDM_TSBITRATEM ,0x0f}, + {R367_OFDM_TSBITRATEL ,0xc6}, + {R367_OFDM_TSPACKLENM ,0x00}, + {R367_OFDM_TSPACKLENL ,0xfc}, + {R367_OFDM_TSBLOCLENM ,0x0a}, + {R367_OFDM_TSBLOCLENL ,0x80}, + {R367_OFDM_TSDLYH ,0x90}, + {R367_OFDM_TSDLYM ,0x68}, + {R367_OFDM_TSDLYL ,0x01}, + {R367_OFDM_TSNPDAV ,0x00}, + {R367_OFDM_TSBUFSTATH ,0x00}, + {R367_OFDM_TSBUFSTATM ,0x00}, + {R367_OFDM_TSBUFSTATL ,0x00}, + {R367_OFDM_TSDEBUGM ,0xcf}, + {R367_OFDM_TSDEBUGL ,0x1e}, + {R367_OFDM_TSDLYSETH ,0x00}, + {R367_OFDM_TSDLYSETM ,0x68}, + {R367_OFDM_TSDLYSETL ,0x00}, + {R367_OFDM_TSOBSCFG ,0x00}, + {R367_OFDM_TSOBSM ,0x47}, + {R367_OFDM_TSOBSL ,0x1f}, + {R367_OFDM_ERRCTRL1 ,0x95}, + {R367_OFDM_ERRCNT1H ,0x80}, + {R367_OFDM_ERRCNT1M ,0x00}, + {R367_OFDM_ERRCNT1L ,0x00}, + {R367_OFDM_ERRCTRL2 ,0x95}, + {R367_OFDM_ERRCNT2H ,0x00}, + {R367_OFDM_ERRCNT2M ,0x00}, + {R367_OFDM_ERRCNT2L ,0x00}, + {R367_OFDM_FECSPY ,0x88}, + {R367_OFDM_FSPYCFG ,0x2c}, + {R367_OFDM_FSPYDATA ,0x3a}, + {R367_OFDM_FSPYOUT ,0x06}, + {R367_OFDM_FSTATUS ,0x61}, + {R367_OFDM_FGOODPACK ,0xff}, + {R367_OFDM_FPACKCNT ,0xff}, + {R367_OFDM_FSPYMISC ,0x66}, + {R367_OFDM_FBERCPT4 ,0x00}, + {R367_OFDM_FBERCPT3 ,0x00}, + {R367_OFDM_FBERCPT2 ,0x36}, + {R367_OFDM_FBERCPT1 ,0x36}, + {R367_OFDM_FBERCPT0 ,0x14}, + {R367_OFDM_FBERERR2 ,0x00}, + {R367_OFDM_FBERERR1 ,0x03}, + {R367_OFDM_FBERERR0 ,0x28}, + {R367_OFDM_FSTATESM ,0x00}, + {R367_OFDM_FSTATESL ,0x02}, + {R367_OFDM_FSPYBER ,0x00}, + {R367_OFDM_FSPYDISTM ,0x01}, + {R367_OFDM_FSPYDISTL ,0x9f}, + {R367_OFDM_FSPYOBS7 ,0xc9}, + {R367_OFDM_FSPYOBS6 ,0x99}, + {R367_OFDM_FSPYOBS5 ,0x08}, + {R367_OFDM_FSPYOBS4 ,0xec}, + {R367_OFDM_FSPYOBS3 ,0x01}, + {R367_OFDM_FSPYOBS2 ,0x0f}, + {R367_OFDM_FSPYOBS1 ,0xf5}, + {R367_OFDM_FSPYOBS0 ,0x08}, + {R367_OFDM_SFDEMAP ,0x40}, + {R367_OFDM_SFERROR ,0x00}, + {R367_OFDM_SFAVSR ,0x30}, + {R367_OFDM_SFECSTATUS ,0xcc}, + {R367_OFDM_SFKDIV12 ,0x20}, + {R367_OFDM_SFKDIV23 ,0x40}, + {R367_OFDM_SFKDIV34 ,0x20}, + {R367_OFDM_SFKDIV56 ,0x20}, + {R367_OFDM_SFKDIV67 ,0x00}, + {R367_OFDM_SFKDIV78 ,0x20}, + {R367_OFDM_SFDILSTKM ,0x00}, + {R367_OFDM_SFDILSTKL ,0x00}, + {R367_OFDM_SFSTATUS ,0xb5}, + {R367_OFDM_SFDLYH ,0x90}, + {R367_OFDM_SFDLYM ,0x60}, + {R367_OFDM_SFDLYL ,0x01}, + {R367_OFDM_SFDLYSETH ,0xc0}, + {R367_OFDM_SFDLYSETM ,0x60}, + {R367_OFDM_SFDLYSETL ,0x00}, + {R367_OFDM_SFOBSCFG ,0x00}, + {R367_OFDM_SFOBSM ,0x47}, + {R367_OFDM_SFOBSL ,0x05}, + {R367_OFDM_SFECINFO ,0x40}, + {R367_OFDM_SFERRCTRL ,0x74}, + {R367_OFDM_SFERRCNTH ,0x80}, + {R367_OFDM_SFERRCNTM ,0x00}, + {R367_OFDM_SFERRCNTL ,0x00}, + {R367_OFDM_SYMBRATEM ,0x2f}, + {R367_OFDM_SYMBRATEL ,0x50}, + {R367_OFDM_SYMBSTATUS ,0x7f}, + {R367_OFDM_SYMBCFG ,0x00}, + {R367_OFDM_SYMBFIFOM ,0xf4}, + {R367_OFDM_SYMBFIFOL ,0x0d}, + {R367_OFDM_SYMBOFFSM ,0xf0}, + {R367_OFDM_SYMBOFFSL ,0x2d}, + //{R367_OFDM_DEBUG_LT4 ,0x00}, + //{R367_OFDM_DEBUG_LT5 ,0x00}, + //{R367_OFDM_DEBUG_LT6 ,0x00}, + //{R367_OFDM_DEBUG_LT7 ,0x00}, + //{R367_OFDM_DEBUG_LT8 ,0x00}, + //{R367_OFDM_DEBUG_LT9 ,0x00}, + { 0x0000, 0x00 } // EOT +}; + +static inline u32 MulDiv32(u32 a, u32 b, u32 c) +{ + u64 tmp64; + + tmp64 = (u64)a * (u64)b; + do_div(tmp64, c); + + return (u32) tmp64; +} + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = + {.addr = adr, .flags = 0, .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { + printk("stv0367: i2c_write error\n"); + return -1; + } + return 0; +} + +#if 0 +static int i2c_read(struct i2c_adapter *adap, + u8 adr, u8 *msg, int len, u8 *answ, int alen) +{ + struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, + .buf = msg, .len = len}, + { .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) { + printk("stv0367: i2c_read error\n"); + return -1; + } + return 0; +} +#endif + +static int writereg(struct stv_state *state, u16 reg, u8 dat) +{ + u8 mm[3] = { (reg >> 8), reg & 0xff, dat }; + + return i2c_write(state->i2c, state->adr, mm, 3); +} + +static int readreg(struct stv_state *state, u16 reg, u8 *val) +{ + u8 msg[2] = {reg >> 8, reg & 0xff}; + struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, + .buf = msg, .len = 2}, + {.addr = state->adr, .flags = I2C_M_RD, + .buf = val, .len = 1}}; + return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; +} + +static int readregs(struct stv_state *state, u16 reg, u8 *val, int count) +{ + u8 msg[2] = {reg >> 8, reg & 0xff}; + struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, + .buf = msg, .len = 2}, + {.addr = state->adr, .flags = I2C_M_RD, + .buf = val, .len = count}}; + return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; +} + +static int write_init_table(struct stv_state *state, struct init_table *tab) +{ + while (1) { + if (!tab->adr) + break; + if (writereg(state, tab->adr, tab->data) < 0) + return -1; + tab++; + } + return 0; +} + +static int qam_set_modulation(struct stv_state *state) +{ + int stat = 0; + + switch(state->modulation) { + case QAM_16: + writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM16 ); + writereg(state, R367_QAM_AGC_PWR_REF_L,0x64); /* Set analog AGC reference */ + writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ + writereg(state, R367_QAM_FSM_STATE,0x90); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); + writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); + writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); + writereg(state, R367_QAM_EQU_PNT_GAIN,0x8a); + break; + case QAM_32: + writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM32 ); + writereg(state, R367_QAM_AGC_PWR_REF_L,0x6e); /* Set analog AGC reference */ + writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ + writereg(state, R367_QAM_FSM_STATE,0xb0); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xb7); + writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x9d); + writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); + writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); + break; + case QAM_64: + writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM64 ); + writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ + writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x82); /* Set digital AGC reference */ + if(state->symbol_rate>4500000) + { + writereg(state, R367_QAM_FSM_STATE,0xb0); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa5); + } + else if(state->symbol_rate>2500000) // 25000000 + { + writereg(state, R367_QAM_FSM_STATE,0xa0); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); + } + else + { + writereg(state, R367_QAM_FSM_STATE,0xa0); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); + } + writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); + writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); + writereg(state, R367_QAM_EQU_PNT_GAIN,0x99); + break; + case QAM_128: + writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM128 ); + writereg(state, R367_QAM_AGC_PWR_REF_L,0x76); /* Set analog AGC reference */ + writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ + writereg(state, R367_QAM_FSM_STATE,0x90); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xb1); + if(state->symbol_rate>4500000) // 45000000 + { + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); + } + else if(state->symbol_rate>2500000) // 25000000 + { + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); + } + else + { + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0x97); + } + writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x8e); + writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); + writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); + break; + case QAM_256: + writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM256 ); + writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ + writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x94); /* Set digital AGC reference */ + writereg(state, R367_QAM_FSM_STATE,0xa0); + if(state->symbol_rate>4500000) // 45000000 + { + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + } + else if(state->symbol_rate>2500000) // 25000000 + { + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + } + else + { + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); + } + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); + writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x85); + writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); + writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); + break; + default: + stat = -EINVAL; + break; + } + return stat; +} + + +static int QAM_SetSymbolRate(struct stv_state *state) +{ + int status = 0; + u32 sr = state->symbol_rate; + u32 Corr = 0; + u32 Temp, Temp1, AdpClk; + + switch(state->modulation) { + default: + case QAM_16: Corr = 1032; break; + case QAM_32: Corr = 954; break; + case QAM_64: Corr = 983; break; + case QAM_128: Corr = 957; break; + case QAM_256: Corr = 948; break; + } + + // Transfer ration + Temp = (256*sr) / state->adc_clock; + writereg(state, R367_QAM_EQU_CRL_TFR,(Temp)); + + /* Symbol rate and SRC gain calculation */ + AdpClk = (state->master_clock) / 2000; /* TRL works at half the system clock */ + + Temp = state->symbol_rate; + Temp1 = sr; + + if(sr < 2097152) /* 2097152 = 2^21 */ + { + Temp = ((((sr * 2048) / AdpClk) * 16384 ) / 125 ) * 8; + Temp1 = (((((sr * 2048) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 10000000; + } + else if(sr < 4194304) /* 4194304 = 2**22 */ + { + Temp = ((((sr * 1024) / AdpClk) * 16384 ) / 125 ) * 16; + Temp1 = (((((sr * 1024) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 5000000; + } + else if(sr < 8388608) /* 8388608 = 2**23 */ + { + Temp = ((((sr * 512) / AdpClk) * 16384 ) / 125 ) * 32; + Temp1 = (((((sr * 512) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 2500000; + } + else + { + Temp = ((((sr * 256) / AdpClk) * 16384 ) / 125 ) * 64; + Temp1 = (((((sr * 256) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 1250000; + } + + ///* Filters' coefficients are calculated and written into registers only if the filters are enabled */ + //if (ChipGetField(hChip,F367qam_ADJ_EN)) // Is disabled from init! + //{ + // FE_367qam_SetIirAdjacentcoefficient(hChip, MasterClk_Hz, SymbolRate); + //} + ///* AllPass filter is never used on this IC */ + //ChipSetField(hChip,F367qam_ALLPASSFILT_EN,0); // should be disabled from init! + + writereg(state, R367_QAM_SRC_NCO_LL,(Temp)); + writereg(state, R367_QAM_SRC_NCO_LH,(Temp>>8)); + writereg(state, R367_QAM_SRC_NCO_HL,(Temp>>16)); + writereg(state, R367_QAM_SRC_NCO_HH,(Temp>>24)); + + writereg(state, R367_QAM_IQDEM_GAIN_SRC_L,(Temp1)); + writereg(state, R367_QAM_IQDEM_GAIN_SRC_H,(Temp1>>8)); + return status; +} + + +static int QAM_SetDerotFrequency(struct stv_state *state, u32 DerotFrequency) +{ + int status = 0; + u32 Sampled_IF; + + do { + //if (DerotFrequency < 1000000) + // DerotFrequency = state->adc_clock/4; /* ZIF operation */ + if (DerotFrequency > state->adc_clock) + DerotFrequency = DerotFrequency - state->adc_clock; // User Alias + + Sampled_IF = ((32768 * (DerotFrequency/1000)) / (state->adc_clock/1000)) * 256; + if(Sampled_IF > 8388607) + Sampled_IF = 8388607; + + writereg(state, R367_QAM_MIX_NCO_LL, (Sampled_IF)); + writereg(state, R367_QAM_MIX_NCO_HL, (Sampled_IF>>8)); + writereg(state, R367_QAM_MIX_NCO_HH, (Sampled_IF>>16)); + } while(0); + + return status; +} + + + +static int QAM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) +{ + int status = 0; + u32 AGCTimeOut = 25; + u32 TRLTimeOut = 100000000 / state->symbol_rate; + u32 CRLSymbols = 0; + u32 EQLTimeOut = 100; + u32 SearchRange = state->symbol_rate / 25; + u32 CRLTimeOut; + u8 Temp; + + if( state->demod_state != QAMSet ) { + writereg(state, R367_DEBUG_LT4,0x00); + writereg(state, R367_DEBUG_LT5,0x01); + writereg(state, R367_DEBUG_LT6,0x06);// R367_QAM_CTRL_1 + writereg(state, R367_DEBUG_LT7,0x03);// R367_QAM_CTRL_2 + writereg(state, R367_DEBUG_LT8,0x00); + writereg(state, R367_DEBUG_LT9,0x00); + + // Tuner Setup + writereg(state, R367_ANADIGCTRL,0x8B); /* Buffer Q disabled, I Enabled, signed ADC */ + writereg(state, R367_DUAL_AD12,0x04); /* ADCQ disabled */ + + // Clock setup + writereg(state, R367_ANACTRL,0x0D); /* PLL bypassed and disabled */ + writereg(state, R367_TOPCTRL,0x10); // Set QAM + + writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ + writereg(state, R367_PLLNDIV,232); + writereg(state, R367_PLLSETUP,0x18); /* ADC clock is equal to system clock */ + + msleep(50); + writereg(state, R367_ANACTRL,0x00); /* PLL enabled and used */ + + state->master_clock = 58000000; + state->adc_clock = 58000000; + + state->demod_state = QAMSet; + } + + state->m_bFirstTimeLock = true; + state->m_DemodLockTime = -1; + + qam_set_modulation(state); + QAM_SetSymbolRate(state); + + // Will make problems on low symbol rates ( < 2500000 ) + + switch(state->modulation) { + default: + case QAM_16: CRLSymbols = 150000; break; + case QAM_32: CRLSymbols = 250000; break; + case QAM_64: CRLSymbols = 200000; break; + case QAM_128: CRLSymbols = 250000; break; + case QAM_256: CRLSymbols = 250000; break; + } + + CRLTimeOut = (25 * CRLSymbols * (SearchRange/1000)) / (state->symbol_rate/1000); + CRLTimeOut = (1000 * CRLTimeOut) / state->symbol_rate; + if( CRLTimeOut < 50 ) CRLTimeOut = 50; + + state->m_FECTimeOut = 20; + state->m_DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; + state->m_SignalTimeOut = AGCTimeOut + TRLTimeOut; + + // QAM_AGC_ACCUMRSTSEL = 0; + readreg(state, R367_QAM_AGC_CTL,&state->m_Save_QAM_AGC_CTL); + writereg(state, R367_QAM_AGC_CTL,state->m_Save_QAM_AGC_CTL & ~0x0F); + + // QAM_MODULUSMAP_EN = 0 + readreg(state, R367_QAM_EQU_PNT_GAIN,&Temp); + writereg(state, R367_QAM_EQU_PNT_GAIN,Temp & ~0x40); + + // QAM_SWEEP_EN = 0 + readreg(state, R367_QAM_EQU_CTR_LPF_GAIN,&Temp); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,Temp & ~0x08); + + QAM_SetDerotFrequency(state, IntermediateFrequency); + + // Release TRL + writereg(state, R367_QAM_CTRL_1,0x00); + + state->IF = IntermediateFrequency; + state->demod_state = QAMStarted; + + return status; +} + +static int OFDM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) +{ + int status = 0; + u8 GAIN_SRC1; + u32 Derot; + u8 SYR_CTL; + u8 tmp1; + u8 tmp2; + + if ( state->demod_state != OFDMSet ) { + // QAM Disable + writereg(state, R367_DEBUG_LT4, 0x00); + writereg(state, R367_DEBUG_LT5, 0x00); + writereg(state, R367_DEBUG_LT6, 0x00);// R367_QAM_CTRL_1 + writereg(state, R367_DEBUG_LT7, 0x00);// R367_QAM_CTRL_2 + writereg(state, R367_DEBUG_LT8, 0x00); + writereg(state, R367_DEBUG_LT9, 0x00); + + // Tuner Setup + writereg(state, R367_ANADIGCTRL, 0x89); /* Buffer Q disabled, I Enabled, unsigned ADC */ + writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ + + // Clock setup + writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ + writereg(state, R367_TOPCTRL, 0x00); // Set OFDM + + writereg(state, R367_PLLMDIV, 1); /* IC runs at 54 MHz with a 27 MHz crystal */ + writereg(state, R367_PLLNDIV, 8); + writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ + + msleep(50); + writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ + + state->master_clock = 54000000; + state->adc_clock = 54000000; + + state->demod_state = OFDMSet; + } + + state->m_bFirstTimeLock = true; + state->m_DemodLockTime = -1; + + // Set inversion in GAIN_SRC1 (fixed from init) + // is in GAIN_SRC1, see below + + GAIN_SRC1 = 0xA0; + // Bandwidth + + // Fixed values for 54 MHz + switch(state->bandwidth) { + case 0: + case 8000000: + // Normrate = 44384; + writereg(state, R367_OFDM_TRL_CTL,0x14); + writereg(state, R367_OFDM_TRL_NOMRATE1,0xB0); + writereg(state, R367_OFDM_TRL_NOMRATE2,0x56); + // Gain SRC = 2774 + writereg(state, R367_OFDM_GAIN_SRC1,0x0A | GAIN_SRC1); + writereg(state, R367_OFDM_GAIN_SRC2,0xD6); + break; + case 7000000: + // Normrate = 38836; + writereg(state, R367_OFDM_TRL_CTL,0x14); + writereg(state, R367_OFDM_TRL_NOMRATE1,0xDA); + writereg(state, R367_OFDM_TRL_NOMRATE2,0x4B); + // Gain SRC = 2427 + writereg(state, R367_OFDM_GAIN_SRC1,0x09 | GAIN_SRC1); + writereg(state, R367_OFDM_GAIN_SRC2,0x7B); + break; + case 6000000: + // Normrate = 33288; + writereg(state, R367_OFDM_TRL_CTL,0x14); + writereg(state, R367_OFDM_TRL_NOMRATE1,0x04); + writereg(state, R367_OFDM_TRL_NOMRATE2,0x41); + // Gain SRC = 2080 + writereg(state, R367_OFDM_GAIN_SRC1,0x08 | GAIN_SRC1); + writereg(state, R367_OFDM_GAIN_SRC2,0x20); + break; + default: + return -EINVAL; + break; + } + + Derot = ((IntermediateFrequency / 1000) * 65536) / (state->master_clock / 1000); + + writereg(state, R367_OFDM_INC_DEROT1,(Derot>>8)); + writereg(state, R367_OFDM_INC_DEROT2,(Derot)); + + readreg(state, R367_OFDM_SYR_CTL,&SYR_CTL); + SYR_CTL &= ~0x78; + writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // EchoPos = 0 + + + writereg(state, R367_OFDM_COR_MODEGUARD,0x03); // Force = 0, Mode = 0, Guard = 3 + SYR_CTL &= 0x01; + writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // SYR_TR_DIS = 0 + + msleep(5); + + writereg(state, R367_OFDM_COR_CTL,0x20); // Start core + + // -- Begin M.V. + // Reset FEC and Read Solomon + readreg(state, R367_OFDM_SFDLYSETH,&tmp1); + readreg(state, R367_TSGENERAL,&tmp2); + writereg(state, R367_OFDM_SFDLYSETH,tmp1 | 0x08); + writereg(state, R367_TSGENERAL,tmp2 | 0x01); + // -- End M.V. + + state->m_SignalTimeOut = 200; + state->IF = IntermediateFrequency; + state->demod_state = OFDMStarted; + state->m_DemodTimeOut = 0; + state->m_FECTimeOut = 0; + state->m_TSTimeOut = 0; + + return status; +} + +#if 0 +static int Stop(struct stv_state *state) +{ + int status = 0; + + switch(state->demod_state) + { + case QAMStarted: + status = writereg(state, R367_QAM_CTRL_1,0x06); + state->demod_state = QAMSet; + break; + case OFDMStarted: + status = writereg(state, R367_OFDM_COR_CTL,0x00); + state->demod_state = OFDMSet; + break; + default: + break; + } + return status; +} +#endif + +static s32 Log10x100(u32 x) +{ + static u32 LookupTable[100] = { + 101157945, 103514217, 105925373, 108392691, 110917482, + 113501082, 116144861, 118850223, 121618600, 124451461, // 800.5 - 809.5 + 127350308, 130316678, 133352143, 136458314, 139636836, + 142889396, 146217717, 149623566, 153108746, 156675107, // 810.5 - 819.5 + 160324539, 164058977, 167880402, 171790839, 175792361, + 179887092, 184077200, 188364909, 192752491, 197242274, // 820.5 - 829.5 + 201836636, 206538016, 211348904, 216271852, 221309471, + 226464431, 231739465, 237137371, 242661010, 248313311, // 830.5 - 839.5 + 254097271, 260015956, 266072506, 272270131, 278612117, + 285101827, 291742701, 298538262, 305492111, 312607937, // 840.5 - 849.5 + 319889511, 327340695, 334965439, 342767787, 350751874, + 358921935, 367282300, 375837404, 384591782, 393550075, // 850.5 - 859.5 + 402717034, 412097519, 421696503, 431519077, 441570447, + 451855944, 462381021, 473151259, 484172368, 495450191, // 860.5 - 869.5 + 506990708, 518800039, 530884444, 543250331, 555904257, + 568852931, 582103218, 595662144, 609536897, 623734835, // 870.5 - 879.5 + 638263486, 653130553, 668343918, 683911647, 699841996, + 716143410, 732824533, 749894209, 767361489, 785235635, // 880.5 - 889.5 + 803526122, 822242650, 841395142, 860993752, 881048873, + 901571138, 922571427, 944060876, 966050879, 988553095, // 890.5 - 899.5 + }; + s32 y; + int i; + + if (x == 0) + return 0; + y = 800; + if (x >= 1000000000) { + x /= 10; + y += 100; + } + + while (x < 100000000) { + x *= 10; + y -= 100; + } + i = 0; + while (i < 100 && x > LookupTable[i]) + i += 1; + y += i; + return y; +} + +static int QAM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) +{ + u32 RegValAvg = 0; + u8 RegVal[2]; + int status = 0, i; + + *pSignalToNoise = 0; + for (i = 0; i < 10; i += 1 ) { + readregs(state, R367_QAM_EQU_SNR_LO, RegVal, 2); + RegValAvg += RegVal[0] + 256 * RegVal[1]; + } + if (RegValAvg != 0) { + s32 Power = 1; + switch(state->modulation) { + case QAM_16: + Power = 20480; + break; + case QAM_32: + Power = 23040; + break; + case QAM_64: + Power = 21504; + break; + case QAM_128: + Power = 23616; + break; + case QAM_256: + Power = 21760; + break; + default: + break; + } + *pSignalToNoise = Log10x100((Power * 320) / RegValAvg); + } else { + *pSignalToNoise = 380; + } + return status; +} + +static int OFDM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) +{ + u8 CHC_SNR = 0; + + int status = readreg(state, R367_OFDM_CHC_SNR, &CHC_SNR); + if (status >= 0) { + // Note: very unclear documentation on this. + // Datasheet states snr = CHC_SNR/4 dB -> way to high values! + // Software snr = ( 1000 * CHC_SNR ) / 8 / 32 / 10; -> to low values + // Comment in SW states this should be ( 1000 * CHC_SNR ) / 4 / 32 / 10; for the 367 + // 361/362 Datasheet: snr = CHC_SNR/8 dB -> this looks best + *pSignalToNoise = ( (s32)CHC_SNR * 10) / 8; + } + //printk("SNR %d\n", *pSignalToNoise); + return status; +} + +#if 0 +static int DVBC_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) +{ + *pQuality = 100; + return 0; +}; + +static int DVBT_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) +{ + static s32 QE_SN[] = { + 51, // QPSK 1/2 + 69, // QPSK 2/3 + 79, // QPSK 3/4 + 89, // QPSK 5/6 + 97, // QPSK 7/8 + 108, // 16-QAM 1/2 + 131, // 16-QAM 2/3 + 146, // 16-QAM 3/4 + 156, // 16-QAM 5/6 + 160, // 16-QAM 7/8 + 165, // 64-QAM 1/2 + 187, // 64-QAM 2/3 + 202, // 64-QAM 3/4 + 216, // 64-QAM 5/6 + 225, // 64-QAM 7/8 + }; + u8 TPS_Received[2]; + int Constellation; + int CodeRate; + s32 SignalToNoiseRel, BERQuality; + + *pQuality = 0; + readregs(state, R367_OFDM_TPS_RCVD2, TPS_Received, sizeof(TPS_Received)); + Constellation = TPS_Received[0] & 0x03; + CodeRate = TPS_Received[1] & 0x07; + + if( Constellation > 2 || CodeRate > 5 ) + return -1; + SignalToNoiseRel = SignalToNoise - QE_SN[Constellation * 5 + CodeRate]; + BERQuality = 100; + + if( SignalToNoiseRel < -70 ) + *pQuality = 0; + else if( SignalToNoiseRel < 30 ) { + *pQuality = ((SignalToNoiseRel + 70) * BERQuality)/100; + } else + *pQuality = BERQuality; + return 0; +}; + +static s32 DVBCQuality(struct stv_state *state, s32 SignalToNoise) +{ + s32 SignalToNoiseRel = 0; + s32 Quality = 0; + s32 BERQuality = 100; + + switch(state->modulation) { + case QAM_16: SignalToNoiseRel = SignalToNoise - 200 ; break; + case QAM_32: SignalToNoiseRel = SignalToNoise - 230 ; break; // Not in NorDig + case QAM_64: SignalToNoiseRel = SignalToNoise - 260 ; break; + case QAM_128: SignalToNoiseRel = SignalToNoise - 290 ; break; + case QAM_256: SignalToNoiseRel = SignalToNoise - 320 ; break; + } + + if( SignalToNoiseRel < -70 ) Quality = 0; + else if( SignalToNoiseRel < 30 ) + { + Quality = ((SignalToNoiseRel + 70) * BERQuality)/100; + } + else + Quality = BERQuality; + + return Quality; +} + +static int GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) +{ + *pQuality = 0; + switch(state->demod_state) + { + case QAMStarted: + *pQuality = DVBCQuality(state, SignalToNoise); + break; + case OFDMStarted: + return DVBT_GetQuality(state, SignalToNoise, pQuality); + } + return 0; +}; +#endif + +static int attach_init(struct stv_state *state) +{ + int stat = 0; + + stat = readreg(state, R367_ID, &state->ID); + if ( stat < 0 || state->ID != 0x60 ) + return -ENODEV; + printk("stv0367 found\n"); + + writereg(state, R367_TOPCTRL, 0x10); + write_init_table(state, base_init); + write_init_table(state, qam_init); + + writereg(state, R367_TOPCTRL, 0x00); + write_init_table(state, ofdm_init); + + writereg(state, R367_OFDM_GAIN_SRC1, 0x2A); + writereg(state, R367_OFDM_GAIN_SRC2, 0xD6); + writereg(state, R367_OFDM_INC_DEROT1, 0x55); + writereg(state, R367_OFDM_INC_DEROT2, 0x55); + writereg(state, R367_OFDM_TRL_CTL, 0x14); + writereg(state, R367_OFDM_TRL_NOMRATE1, 0xAE); + writereg(state, R367_OFDM_TRL_NOMRATE2, 0x56); + writereg(state, R367_OFDM_FEPATH_CFG, 0x0); + + // OFDM TS Setup + + writereg(state, R367_OFDM_TSCFGH, 0x70); + writereg(state, R367_OFDM_TSCFGM, 0xC0); + writereg(state, R367_OFDM_TSCFGL, 0x20); + writereg(state, R367_OFDM_TSSPEED, 0x40); // Fixed at 54 MHz + //writereg(state, R367_TSTBUS, 0x80); // Invert CLK + + writereg(state, R367_OFDM_TSCFGH, 0x71); + + if (state->cont_clock) + writereg(state, R367_OFDM_TSCFGH, 0xf0); + else + writereg(state, R367_OFDM_TSCFGH, 0x70); + + writereg(state, R367_TOPCTRL, 0x10); + + // Also needed for QAM + writereg(state, R367_OFDM_AGC12C, 0x01); // AGC Pin setup + + writereg(state, R367_OFDM_AGCCTRL1, 0x8A); // + + // QAM TS setup, note exact format also depends on descrambler settings + writereg(state, R367_QAM_OUTFORMAT_0, 0x85); // Inverted Clock, Swap, serial + // writereg(state, R367_QAM_OUTFORMAT_1, 0x00); // + + // Clock setup + writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ + + if( state->master_clock == 58000000 ) { + writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ + writereg(state, R367_PLLNDIV,232); + } else { + writereg(state, R367_PLLMDIV,1); /* IC runs at 54 MHz with a 27 MHz crystal */ + writereg(state, R367_PLLNDIV,8); + } + writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ + + // Tuner setup + writereg(state, R367_ANADIGCTRL, 0x8b); /* Buffer Q disabled, I Enabled, signed ADC */ + writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ + + writereg(state, R367_QAM_FSM_SNR2_HTH, 0x23); /* Improves the C/N lock limit */ + writereg(state, R367_QAM_IQ_QAM, 0x01); /* ZIF/IF Automatic mode */ + writereg(state, R367_QAM_EQU_FFE_LEAKAGE, 0x83); /* Improving burst noise performances */ + writereg(state, R367_QAM_IQDEM_ADJ_EN, 0x05); /* Improving ACI performances */ + + writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ + + writereg(state, R367_I2CRPT, state->I2CRPT); + state->demod_state = QAMSet; + return stat; +} + +static void release(struct dvb_frontend* fe) +{ + struct stv_state *state=fe->demodulator_priv; + printk("%s\n", __FUNCTION__); + kfree(state); +} + +static int gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct stv_state *state = fe->demodulator_priv; + u8 i2crpt = state->I2CRPT & ~0x80; + + if (enable) + i2crpt |= 0x80; + if (writereg(state, R367_I2CRPT, i2crpt) < 0) + return -1; + state->I2CRPT = i2crpt; + return 0; +} + +#if 0 +static int c_track(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + return DVBFE_ALGO_SEARCH_AGAIN; +} +#endif + +#if 0 +int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); +int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); +#endif + +static int ofdm_lock(struct stv_state *state) +{ + int status = 0; + u8 OFDM_Status; + s32 DemodTimeOut = 10; + s32 FECTimeOut = 0; + s32 TSTimeOut = 0; + u8 CPAMPMin = 255; + u8 CPAMPValue; + u8 SYR_STAT; + u8 FFTMode; + u8 TSStatus; + + msleep(state->m_SignalTimeOut); + readreg(state, R367_OFDM_STATUS,&OFDM_Status); + + if (!(OFDM_Status & 0x40)) + return -1; + //printk("lock 1\n"); + + readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); + FFTMode = (SYR_STAT & 0x0C) >> 2; + + switch(FFTMode) + { + case 0: // 2K + DemodTimeOut = 10; + FECTimeOut = 150; + TSTimeOut = 125; + CPAMPMin = 20; + break; + case 1: // 8K + DemodTimeOut = 55; + FECTimeOut = 600; + TSTimeOut = 500; + CPAMPMin = 80; + break; + case 2: // 4K + DemodTimeOut = 40; + FECTimeOut = 300; + TSTimeOut = 250; + CPAMPMin = 30; + break; + } + state->m_OFDM_FFTMode = FFTMode; + readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); + msleep(DemodTimeOut); + { + // Release FEC and Read Solomon Reset + u8 tmp1; + u8 tmp2; + readreg(state, R367_OFDM_SFDLYSETH,&tmp1); + readreg(state, R367_TSGENERAL,&tmp2); + writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); + writereg(state, R367_TSGENERAL,tmp2 & ~0x01); + } + msleep(FECTimeOut); + if( (OFDM_Status & 0x98) != 0x98 ) + ;//return -1; + //printk("lock 2\n"); + + { + u8 Guard = (SYR_STAT & 0x03); + if(Guard < 2) + { + u8 tmp; + readreg(state, R367_OFDM_SYR_CTL,&tmp); + writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN + readreg(state, R367_OFDM_SYR_UPDATE,&tmp); + writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER + } else { + u8 tmp; + readreg(state, R367_OFDM_SYR_CTL,&tmp); + writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN + readreg(state, R367_OFDM_SYR_UPDATE,&tmp); + writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER + } + + // apply Sfec workaround if 8K 64QAM CR!=1/2 + if( FFTMode == 1) + { + u8 tmp[2]; + readregs(state, R367_OFDM_TPS_RCVD2, tmp, 2); + if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) + { + writereg(state, R367_OFDM_SFDLYSETH,0xc0); + writereg(state, R367_OFDM_SFDLYSETM,0x60); + writereg(state, R367_OFDM_SFDLYSETL,0x00); + } + else + { + writereg(state, R367_OFDM_SFDLYSETH,0x00); + } + } + } + msleep(TSTimeOut); + readreg(state, R367_OFDM_TSSTATUS,&TSStatus); + if( (TSStatus & 0x80) != 0x80 ) + return -1; + //printk("lock 3\n"); + return status; +} + + +static int set_parameters(struct dvb_frontend *fe) +{ + int stat; + struct stv_state *state = fe->demodulator_priv; + u32 OF = 0; + u32 IF; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBC_ANNEX_A: + state->omode = OM_DVBC; + /* symbol rate 0 might cause an oops */ + if (fe->dtv_property_cache.symbol_rate == 0) { + printk(KERN_ERR "stv0367dd: Invalid symbol rate\n"); + return -EINVAL; + } + break; + case SYS_DVBT: + state->omode = OM_DVBT; + break; + default: + return -EINVAL; + } + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe); + state->modulation = fe->dtv_property_cache.modulation; + state->symbol_rate = fe->dtv_property_cache.symbol_rate; + state->bandwidth = fe->dtv_property_cache.bandwidth_hz; + fe->ops.tuner_ops.get_if_frequency(fe, &IF); + //fe->ops.tuner_ops.get_frequency(fe, &IF); + + switch(state->omode) { + case OM_DVBT: + stat = OFDM_Start(state, OF, IF); + ofdm_lock(state); + break; + case OM_DVBC: + case OM_QAM_ITU_C: + stat = QAM_Start(state, OF, IF); + break; + default: + stat = -EINVAL; + } + //printk("%s IF=%d OF=%d done\n", __FUNCTION__, IF, OF); + return stat; +} + +#if 0 +static int c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + //struct stv_state *state = fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + return 0; +} + +static int OFDM_GetLockStatus(struct stv_state *state, LOCK_STATUS* pLockStatus, s32 Time) +{ + int status = STATUS_SUCCESS; + u8 OFDM_Status; + s32 DemodTimeOut = 0; + s32 FECTimeOut = 0; + s32 TSTimeOut = 0; + u8 CPAMPMin = 255; + u8 CPAMPValue; + bool SYRLock; + u8 SYR_STAT; + u8 FFTMode; + u8 TSStatus; + + readreg(state, R367_OFDM_STATUS,&OFDM_Status); + + SYRLock = (OFDM_Status & 0x40) != 0; + + if( Time > m_SignalTimeOut && !SYRLock ) + { + *pLockStatus = NEVER_LOCK; + break; + } + + if( !SYRLock ) break; + + *pLockStatus = SIGNAL_PRESENT; + + // Check Mode + + readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); + FFTMode = (SYR_STAT & 0x0C) >> 2; + + switch(FFTMode) + { + case 0: // 2K + DemodTimeOut = 10; + FECTimeOut = 150; + TSTimeOut = 125; + CPAMPMin = 20; + break; + case 1: // 8K + DemodTimeOut = 55; + FECTimeOut = 600; + TSTimeOut = 500; + CPAMPMin = 80; + break; + case 2: // 4K + DemodTimeOut = 40; + FECTimeOut = 300; + TSTimeOut = 250; + CPAMPMin = 30; + break; + } + + m_OFDM_FFTMode = FFTMode; + + if( m_DemodTimeOut == 0 && m_bFirstTimeLock ) + { + m_DemodTimeOut = Time + DemodTimeOut; + //break; + } + + readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); + + if( Time <= m_DemodTimeOut && CPAMPValue < CPAMPMin ) + { + break; + } + + if( CPAMPValue < CPAMPMin && m_bFirstTimeLock ) + { + // initiate retry + *pLockStatus = NEVER_LOCK; + break; + } + + if( CPAMPValue < CPAMPMin ) break; + + *pLockStatus = DEMOD_LOCK; + + if( m_FECTimeOut == 0 && m_bFirstTimeLock ) + { + // Release FEC and Read Solomon Reset + u8 tmp1; + u8 tmp2; + readreg(state, R367_OFDM_SFDLYSETH,&tmp1); + readreg(state, R367_TSGENERAL,&tmp2); + writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); + writereg(state, R367_TSGENERAL,tmp2 & ~0x01); + + m_FECTimeOut = Time + FECTimeOut; + } + + // Wait for TSP_LOCK, LK, PRF + if( (OFDM_Status & 0x98) != 0x98 ) + { + if( Time > m_FECTimeOut ) *pLockStatus = NEVER_LOCK; + break; + } + + if( m_bFirstTimeLock && m_TSTimeOut == 0) + { + u8 Guard = (SYR_STAT & 0x03); + if(Guard < 2) + { + u8 tmp; + readreg(state, R367_OFDM_SYR_CTL,&tmp); + writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN + readreg(state, R367_OFDM_SYR_UPDATE,&tmp); + writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER + } else { + u8 tmp; + readreg(state, R367_OFDM_SYR_CTL,&tmp); + writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN + readreg(state, R367_OFDM_SYR_UPDATE,&tmp); + writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER + } + + // apply Sfec workaround if 8K 64QAM CR!=1/2 + if( FFTMode == 1) + { + u8 tmp[2]; + readreg(state, R367_OFDM_TPS_RCVD2,tmp,2); + if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) + { + writereg(state, R367_OFDM_SFDLYSETH,0xc0); + writereg(state, R367_OFDM_SFDLYSETM,0x60); + writereg(state, R367_OFDM_SFDLYSETL,0x00); + } + else + { + writereg(state, R367_OFDM_SFDLYSETH,0x00); + } + } + + m_TSTimeOut = Time + TSTimeOut; + } + readreg(state, R367_OFDM_TSSTATUS,&TSStatus); + if( (TSStatus & 0x80) != 0x80 ) + { + if( Time > m_TSTimeOut ) *pLockStatus = NEVER_LOCK; + break; + } + *pLockStatus = MPEG_LOCK; + m_bFirstTimeLock = false; + return status; +} + +#endif + +static int read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct stv_state *state = fe->demodulator_priv; + *status=0; + + switch(state->demod_state) { + case QAMStarted: + { + u8 FEC_Lock; + u8 QAM_Lock; + + readreg(state, R367_QAM_FSM_STS, &QAM_Lock); + QAM_Lock &= 0x0F; + if (QAM_Lock >10) + *status|=0x07; + readreg(state, R367_QAM_FEC_STATUS,&FEC_Lock); + if (FEC_Lock&2) + *status|=0x1f; + if (state->m_bFirstTimeLock) { + state->m_bFirstTimeLock = false; + // QAM_AGC_ACCUMRSTSEL to Tracking; + writereg(state, R367_QAM_AGC_CTL, state->m_Save_QAM_AGC_CTL); + } + break; + } + case OFDMStarted: + { + u8 OFDM_Status; + u8 TSStatus; + + readreg(state, R367_OFDM_TSSTATUS, &TSStatus); + + readreg(state, R367_OFDM_STATUS, &OFDM_Status); + if (OFDM_Status & 0x40) + *status |= FE_HAS_SIGNAL; + + if ((OFDM_Status & 0x98) == 0x98) + *status|=0x0f; + + if (TSStatus & 0x80) + *status |= 0x1f; + break; + } + default: + break; + } + return 0; +} + +static int read_ber_ter(struct dvb_frontend *fe, u32 *ber) +{ + struct stv_state *state = fe->demodulator_priv; + u32 err; + u8 cnth, cntm, cntl; + +#if 1 + readreg(state, R367_OFDM_SFERRCNTH, &cnth); + + if (cnth & 0x80) { + *ber = state->ber; + return 0; + } + + readreg(state, R367_OFDM_SFERRCNTM, &cntm); + readreg(state, R367_OFDM_SFERRCNTL, &cntl); + + err = ((cnth & 0x7f) << 16) | (cntm << 8) | cntl; + +#if 0 + { + u64 err64; + err64 = (u64) err; + err64 *= 1000000000ULL; + err64 >>= 21; + err = err64; + } +#endif +#else + readreg(state, R367_OFDM_ERRCNT1HM, &cnth); + +#endif + *ber = state->ber = err; + return 0; +} + +static int read_ber_cab(struct dvb_frontend *fe, u32 *ber) +{ + struct stv_state *state = fe->demodulator_priv; + u32 err; + u8 cntm, cntl, ctrl; + + readreg(state, R367_QAM_BERT_1, &ctrl); + if (!(ctrl & 0x20)) { + readreg(state, R367_QAM_BERT_2, &cntl); + readreg(state, R367_QAM_BERT_3, &cntm); + err = (cntm << 8) | cntl; + //printk("err %04x\n", err); + state->ber = err; + writereg(state, R367_QAM_BERT_1, 0x27); + } + *ber = (u32) state->ber; + return 0; +} + +static int read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct stv_state *state = fe->demodulator_priv; + + if (state->demod_state == QAMStarted) + return read_ber_cab(fe, ber); + if (state->demod_state == OFDMStarted) + return read_ber_ter(fe, ber); + *ber = 0; + return 0; +} + +static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + if (fe->ops.tuner_ops.get_rf_strength) + fe->ops.tuner_ops.get_rf_strength(fe, strength); + else + *strength = 0; + return 0; +} + +static int read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct stv_state *state = fe->demodulator_priv; + s32 snr2 = 0; + + switch(state->demod_state) { + case QAMStarted: + QAM_GetSignalToNoise(state, &snr2); + break; + case OFDMStarted: + OFDM_GetSignalToNoise(state, &snr2); + break; + default: + break; + } + *snr = snr2&0xffff; + return 0; +} + +static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct stv_state *state = fe->demodulator_priv; + u8 errl, errm, errh; + u8 val; + + switch(state->demod_state) { + case QAMStarted: + readreg(state, R367_QAM_RS_COUNTER_4, &errl); + readreg(state, R367_QAM_RS_COUNTER_5, &errm); + *ucblocks = (errm << 8) | errl; + break; + case OFDMStarted: + readreg(state, R367_OFDM_SFERRCNTH, &val); + if ((val & 0x80) == 0) { + readreg(state, R367_OFDM_ERRCNT1H, &errh); + readreg(state, R367_OFDM_ERRCNT1M, &errl); + readreg(state, R367_OFDM_ERRCNT1L, &errm); + state->ucblocks = (errh <<16) | (errm << 8) | errl; + } + *ucblocks = state->ucblocks; + break; + default: + *ucblocks = 0; + break; + } + return 0; +} + +static int c_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ + sets->min_delay_ms=3000; + sets->max_drift=0; + sets->step_size=0; + return 0; +} + +static int get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBC_ANNEX_A: + case SYS_DVBC_ANNEX_C: + return c_get_tune_settings(fe, sets); + default: + /* DVB-T: Use info.frequency_stepsize. */ + return -EINVAL; + } +} + +#if 0 +static int t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + //struct stv_state *state = fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + return 0; +} + +static enum dvbfe_algo algo(struct dvb_frontend *fe) +{ + return DVBFE_ALGO_CUSTOM; +} +#endif + +static struct dvb_frontend_ops common_ops = { + .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT }, + .info = { + .name = "STV0367 DVB-C DVB-T", + .frequency_stepsize = 166667, /* DVB-T only */ + .frequency_min = 47000000, /* DVB-T: 47125000 */ + .frequency_max = 865000000, /* DVB-C: 862000000 */ + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, + .caps = /* DVB-C */ + FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | + FE_CAN_FEC_AUTO | + /* DVB-T */ + FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | FE_CAN_MUTE_TS + }, + .release = release, + .i2c_gate_ctrl = gate_ctrl, + + .get_tune_settings = get_tune_settings, + + .set_frontend = set_parameters, + + .read_status = read_status, + .read_ber = read_ber, + .read_signal_strength = read_signal_strength, + .read_snr = read_snr, + .read_ucblocks = read_ucblocks, +}; + + +static void init_state(struct stv_state *state, struct stv0367_cfg *cfg) +{ + u32 ulENARPTLEVEL = 5; + u32 ulQAMInversion = 2; + state->omode = OM_NONE; + state->adr = cfg->adr; + state->cont_clock = cfg->cont_clock; + + mutex_init(&state->mutex); + mutex_init(&state->ctlock); + + memcpy(&state->frontend.ops, &common_ops, sizeof(struct dvb_frontend_ops)); + state->frontend.demodulator_priv = state; + + state->master_clock = 58000000; + state->adc_clock = 58000000; + state->I2CRPT = 0x08 | ((ulENARPTLEVEL & 0x07) << 4); + state->qam_inversion = ((ulQAMInversion & 3) << 6 ); + state->demod_state = Off; +} + + +struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, struct stv0367_cfg *cfg, + struct dvb_frontend **fe_t) +{ + struct stv_state *state = NULL; + + state = kzalloc(sizeof(struct stv_state), GFP_KERNEL); + if (!state) + return NULL; + + state->i2c = i2c; + init_state(state, cfg); + + if (attach_init(state)<0) + goto error; + return &state->frontend; + +error: + printk("stv0367: not found\n"); + kfree(state); + return NULL; +} + + +MODULE_DESCRIPTION("STV0367DD driver"); +MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(stv0367_attach); + + + diff --git a/frontends/stv0367dd_regs.h b/frontends/stv0367dd_regs.h index eec0f57..0f02bea 100644 --- a/frontends/stv0367dd_regs.h +++ b/frontends/stv0367dd_regs.h @@ -1,3431 +1,3431 @@ -// @DVB-C/DVB-T STMicroelectronics STV0367 register defintions -// Author Manfred Völkel, Februar 2011 -// (c) 2010 DigitalDevices GmbH Germany. All rights reserved - -// $Id: DD_STV0367Register.h 357 2011-04-27 02:39:13Z manfred $ - -/* ======================================================================= - -- Registers Declaration - -- ------------------------- - -- Each register (R367_XXXXX) is defined by its address (2 bytes). - -- - -- Each field (F367_XXXXX)is defined as follow: - -- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] - ======================================================================= */ - -/* ID */ -#define R367_ID 0xF000 -#define F367_IDENTIFICATIONREG 0xF00000FF - -/* I2CRPT */ -#define R367_I2CRPT 0xF001 -#define F367_I2CT_ON 0xF0010080 -#define F367_ENARPT_LEVEL 0xF0010070 -#define F367_SCLT_DELAY 0xF0010008 -#define F367_SCLT_NOD 0xF0010004 -#define F367_STOP_ENABLE 0xF0010002 -#define F367_SDAT_NOD 0xF0010001 - -/* TOPCTRL */ -#define R367_TOPCTRL 0xF002 -#define F367_STDBY 0xF0020080 -#define F367_STDBY_FEC 0xF0020040 -#define F367_STDBY_CORE 0xF0020020 -#define F367_QAM_COFDM 0xF0020010 -#define F367_TS_DIS 0xF0020008 -#define F367_DIR_CLK_216 0xF0020004 -#define F367_TUNER_BB 0xF0020002 -#define F367_DVBT_H 0xF0020001 - -/* IOCFG0 */ -#define R367_IOCFG0 0xF003 -#define F367_OP0_SD 0xF0030080 -#define F367_OP0_VAL 0xF0030040 -#define F367_OP0_OD 0xF0030020 -#define F367_OP0_INV 0xF0030010 -#define F367_OP0_DACVALUE_HI 0xF003000F - -/* DAC0R */ -#define R367_DAC0R 0xF004 -#define F367_OP0_DACVALUE_LO 0xF00400FF - -/* IOCFG1 */ -#define R367_IOCFG1 0xF005 -#define F367_IP0 0xF0050040 -#define F367_OP1_OD 0xF0050020 -#define F367_OP1_INV 0xF0050010 -#define F367_OP1_DACVALUE_HI 0xF005000F - -/* DAC1R */ -#define R367_DAC1R 0xF006 -#define F367_OP1_DACVALUE_LO 0xF00600FF - -/* IOCFG2 */ -#define R367_IOCFG2 0xF007 -#define F367_OP2_LOCK_CONF 0xF00700E0 -#define F367_OP2_OD 0xF0070010 -#define F367_OP2_VAL 0xF0070008 -#define F367_OP1_LOCK_CONF 0xF0070007 - -/* SDFR */ -#define R367_SDFR 0xF008 -#define F367_OP0_FREQ 0xF00800F0 -#define F367_OP1_FREQ 0xF008000F - -/* STATUS */ -#define R367_OFDM_STATUS 0xF009 -#define F367_TPS_LOCK 0xF0090080 -#define F367_SYR_LOCK 0xF0090040 -#define F367_AGC_LOCK 0xF0090020 -#define F367_PRF 0xF0090010 -#define F367_LK 0xF0090008 -#define F367_PR 0xF0090007 - -/* AUX_CLK */ -#define R367_AUX_CLK 0xF00A -#define F367_AUXFEC_CTL 0xF00A00C0 -#define F367_DIS_CKX4 0xF00A0020 -#define F367_CKSEL 0xF00A0018 -#define F367_CKDIV_PROG 0xF00A0006 -#define F367_AUXCLK_ENA 0xF00A0001 - -/* FREESYS1 */ -#define R367_FREESYS1 0xF00B -#define F367_FREE_SYS1 0xF00B00FF - -/* FREESYS2 */ -#define R367_FREESYS2 0xF00C -#define F367_FREE_SYS2 0xF00C00FF - -/* FREESYS3 */ -#define R367_FREESYS3 0xF00D -#define F367_FREE_SYS3 0xF00D00FF - -/* GPIO_CFG */ -#define R367_GPIO_CFG 0xF00E -#define F367_GPIO7_NOD 0xF00E0080 -#define F367_GPIO7_CFG 0xF00E0040 -#define F367_GPIO6_NOD 0xF00E0020 -#define F367_GPIO6_CFG 0xF00E0010 -#define F367_GPIO5_NOD 0xF00E0008 -#define F367_GPIO5_CFG 0xF00E0004 -#define F367_GPIO4_NOD 0xF00E0002 -#define F367_GPIO4_CFG 0xF00E0001 - -/* GPIO_CMD */ -#define R367_GPIO_CMD 0xF00F -#define F367_GPIO7_VAL 0xF00F0008 -#define F367_GPIO6_VAL 0xF00F0004 -#define F367_GPIO5_VAL 0xF00F0002 -#define F367_GPIO4_VAL 0xF00F0001 - -/* AGC2MAX */ -#define R367_OFDM_AGC2MAX 0xF010 -#define F367_OFDM_AGC2_MAX 0xF01000FF - -/* AGC2MIN */ -#define R367_OFDM_AGC2MIN 0xF011 -#define F367_OFDM_AGC2_MIN 0xF01100FF - -/* AGC1MAX */ -#define R367_OFDM_AGC1MAX 0xF012 -#define F367_OFDM_AGC1_MAX 0xF01200FF - -/* AGC1MIN */ -#define R367_OFDM_AGC1MIN 0xF013 -#define F367_OFDM_AGC1_MIN 0xF01300FF - -/* AGCR */ -#define R367_OFDM_AGCR 0xF014 -#define F367_OFDM_RATIO_A 0xF01400E0 -#define F367_OFDM_RATIO_B 0xF0140018 -#define F367_OFDM_RATIO_C 0xF0140007 - -/* AGC2TH */ -#define R367_OFDM_AGC2TH 0xF015 -#define F367_OFDM_AGC2_THRES 0xF01500FF - -/* AGC12C */ -#define R367_OFDM_AGC12C 0xF016 -#define F367_OFDM_AGC1_IV 0xF0160080 -#define F367_OFDM_AGC1_OD 0xF0160040 -#define F367_OFDM_AGC1_LOAD 0xF0160020 -#define F367_OFDM_AGC2_IV 0xF0160010 -#define F367_OFDM_AGC2_OD 0xF0160008 -#define F367_OFDM_AGC2_LOAD 0xF0160004 -#define F367_OFDM_AGC12_MODE 0xF0160003 - -/* AGCCTRL1 */ -#define R367_OFDM_AGCCTRL1 0xF017 -#define F367_OFDM_DAGC_ON 0xF0170080 -#define F367_OFDM_INVERT_AGC12 0xF0170040 -#define F367_OFDM_AGC1_MODE 0xF0170008 -#define F367_OFDM_AGC2_MODE 0xF0170007 - -/* AGCCTRL2 */ -#define R367_OFDM_AGCCTRL2 0xF018 -#define F367_OFDM_FRZ2_CTRL 0xF0180060 -#define F367_OFDM_FRZ1_CTRL 0xF0180018 -#define F367_OFDM_TIME_CST 0xF0180007 - -/* AGC1VAL1 */ -#define R367_OFDM_AGC1VAL1 0xF019 -#define F367_OFDM_AGC1_VAL_LO 0xF01900FF - -/* AGC1VAL2 */ -#define R367_OFDM_AGC1VAL2 0xF01A -#define F367_OFDM_AGC1_VAL_HI 0xF01A000F - -/* AGC2VAL1 */ -#define R367_OFDM_AGC2VAL1 0xF01B -#define F367_OFDM_AGC2_VAL_LO 0xF01B00FF - -/* AGC2VAL2 */ -#define R367_OFDM_AGC2VAL2 0xF01C -#define F367_OFDM_AGC2_VAL_HI 0xF01C000F - -/* AGC2PGA */ -#define R367_OFDM_AGC2PGA 0xF01D -#define F367_OFDM_AGC2_PGA 0xF01D00FF - -/* OVF_RATE1 */ -#define R367_OFDM_OVF_RATE1 0xF01E -#define F367_OFDM_OVF_RATE_HI 0xF01E000F - -/* OVF_RATE2 */ -#define R367_OFDM_OVF_RATE2 0xF01F -#define F367_OFDM_OVF_RATE_LO 0xF01F00FF - -/* GAIN_SRC1 */ -#define R367_OFDM_GAIN_SRC1 0xF020 -#define F367_OFDM_INV_SPECTR 0xF0200080 -#define F367_OFDM_IQ_INVERT 0xF0200040 -#define F367_OFDM_INR_BYPASS 0xF0200020 -#define F367_OFDM_STATUS_INV_SPECRUM 0xF0200010 -#define F367_OFDM_GAIN_SRC_HI 0xF020000F - -/* GAIN_SRC2 */ -#define R367_OFDM_GAIN_SRC2 0xF021 -#define F367_OFDM_GAIN_SRC_LO 0xF02100FF - -/* INC_DEROT1 */ -#define R367_OFDM_INC_DEROT1 0xF022 -#define F367_OFDM_INC_DEROT_HI 0xF02200FF - -/* INC_DEROT2 */ -#define R367_OFDM_INC_DEROT2 0xF023 -#define F367_OFDM_INC_DEROT_LO 0xF02300FF - -/* PPM_CPAMP_DIR */ -#define R367_OFDM_PPM_CPAMP_DIR 0xF024 -#define F367_OFDM_PPM_CPAMP_DIRECT 0xF02400FF - -/* PPM_CPAMP_INV */ -#define R367_OFDM_PPM_CPAMP_INV 0xF025 -#define F367_OFDM_PPM_CPAMP_INVER 0xF02500FF - -/* FREESTFE_1 */ -#define R367_OFDM_FREESTFE_1 0xF026 -#define F367_OFDM_SYMBOL_NUMBER_INC 0xF02600C0 -#define F367_OFDM_SEL_LSB 0xF0260004 -#define F367_OFDM_AVERAGE_ON 0xF0260002 -#define F367_OFDM_DC_ADJ 0xF0260001 - -/* FREESTFE_2 */ -#define R367_OFDM_FREESTFE_2 0xF027 -#define F367_OFDM_SEL_SRCOUT 0xF02700C0 -#define F367_OFDM_SEL_SYRTHR 0xF027001F - -/* DCOFFSET */ -#define R367_OFDM_DCOFFSET 0xF028 -#define F367_OFDM_SELECT_I_Q 0xF0280080 -#define F367_OFDM_DC_OFFSET 0xF028007F - -/* EN_PROCESS */ -#define R367_OFDM_EN_PROCESS 0xF029 -#define F367_OFDM_FREE 0xF02900F0 -#define F367_OFDM_ENAB_MANUAL 0xF0290001 - -/* SDI_SMOOTHER */ -#define R367_OFDM_SDI_SMOOTHER 0xF02A -#define F367_OFDM_DIS_SMOOTH 0xF02A0080 -#define F367_OFDM_SDI_INC_SMOOTHER 0xF02A007F - -/* FE_LOOP_OPEN */ -#define R367_OFDM_FE_LOOP_OPEN 0xF02B -#define F367_OFDM_TRL_LOOP_OP 0xF02B0002 -#define F367_OFDM_CRL_LOOP_OP 0xF02B0001 - -/* FREQOFF1 */ -#define R367_OFDM_FREQOFF1 0xF02C -#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_VHI 0xF02C00FF - -/* FREQOFF2 */ -#define R367_OFDM_FREQOFF2 0xF02D -#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_HI 0xF02D00FF - -/* FREQOFF3 */ -#define R367_OFDM_FREQOFF3 0xF02E -#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_LO 0xF02E00FF - -/* TIMOFF1 */ -#define R367_OFDM_TIMOFF1 0xF02F -#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_HI 0xF02F00FF - -/* TIMOFF2 */ -#define R367_OFDM_TIMOFF2 0xF030 -#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_LO 0xF03000FF - -/* EPQ */ -#define R367_OFDM_EPQ 0xF031 -#define F367_OFDM_EPQ1 0xF03100FF - -/* EPQAUTO */ -#define R367_OFDM_EPQAUTO 0xF032 -#define F367_OFDM_EPQ2 0xF03200FF - -/* SYR_UPDATE */ -#define R367_OFDM_SYR_UPDATE 0xF033 -#define F367_OFDM_SYR_PROTV 0xF0330080 -#define F367_OFDM_SYR_PROTV_GAIN 0xF0330060 -#define F367_OFDM_SYR_FILTER 0xF0330010 -#define F367_OFDM_SYR_TRACK_THRES 0xF033000C - -/* CHPFREE */ -#define R367_OFDM_CHPFREE 0xF034 -#define F367_OFDM_CHP_FREE 0xF03400FF - -/* PPM_STATE_MAC */ -#define R367_OFDM_PPM_STATE_MAC 0xF035 -#define F367_OFDM_PPM_STATE_MACHINE_DECODER 0xF035003F - -/* INR_THRESHOLD */ -#define R367_OFDM_INR_THRESHOLD 0xF036 -#define F367_OFDM_INR_THRESH 0xF03600FF - -/* EPQ_TPS_ID_CELL */ -#define R367_OFDM_EPQ_TPS_ID_CELL 0xF037 -#define F367_OFDM_ENABLE_LGTH_TO_CF 0xF0370080 -#define F367_OFDM_DIS_TPS_RSVD 0xF0370040 -#define F367_OFDM_DIS_BCH 0xF0370020 -#define F367_OFDM_DIS_ID_CEL 0xF0370010 -#define F367_OFDM_TPS_ADJUST_SYM 0xF037000F - -/* EPQ_CFG */ -#define R367_OFDM_EPQ_CFG 0xF038 -#define F367_OFDM_EPQ_RANGE 0xF0380002 -#define F367_OFDM_EPQ_SOFT 0xF0380001 - -/* EPQ_STATUS */ -#define R367_OFDM_EPQ_STATUS 0xF039 -#define F367_OFDM_SLOPE_INC 0xF03900FC -#define F367_OFDM_TPS_FIELD 0xF0390003 - -/* AUTORELOCK */ -#define R367_OFDM_AUTORELOCK 0xF03A -#define F367_OFDM_BYPASS_BER_TEMPO 0xF03A0080 -#define F367_OFDM_BER_TEMPO 0xF03A0070 -#define F367_OFDM_BYPASS_COFDM_TEMPO 0xF03A0008 -#define F367_OFDM_COFDM_TEMPO 0xF03A0007 - -/* BER_THR_VMSB */ -#define R367_OFDM_BER_THR_VMSB 0xF03B -#define F367_OFDM_BER_THRESHOLD_HI 0xF03B00FF - -/* BER_THR_MSB */ -#define R367_OFDM_BER_THR_MSB 0xF03C -#define F367_OFDM_BER_THRESHOLD_MID 0xF03C00FF - -/* BER_THR_LSB */ -#define R367_OFDM_BER_THR_LSB 0xF03D -#define F367_OFDM_BER_THRESHOLD_LO 0xF03D00FF - -/* CCD */ -#define R367_OFDM_CCD 0xF03E -#define F367_OFDM_CCD_DETECTED 0xF03E0080 -#define F367_OFDM_CCD_RESET 0xF03E0040 -#define F367_OFDM_CCD_THRESHOLD 0xF03E000F - -/* SPECTR_CFG */ -#define R367_OFDM_SPECTR_CFG 0xF03F -#define F367_OFDM_SPECT_CFG 0xF03F0003 - -/* CONSTMU_MSB */ -#define R367_OFDM_CONSTMU_MSB 0xF040 -#define F367_OFDM_CONSTMU_FREEZE 0xF0400080 -#define F367_OFDM_CONSTNU_FORCE_EN 0xF0400040 -#define F367_OFDM_CONST_MU_MSB 0xF040003F - -/* CONSTMU_LSB */ -#define R367_OFDM_CONSTMU_LSB 0xF041 -#define F367_OFDM_CONST_MU_LSB 0xF04100FF - -/* CONSTMU_MAX_MSB */ -#define R367_OFDM_CONSTMU_MAX_MSB 0xF042 -#define F367_OFDM_CONST_MU_MAX_MSB 0xF042003F - -/* CONSTMU_MAX_LSB */ -#define R367_OFDM_CONSTMU_MAX_LSB 0xF043 -#define F367_OFDM_CONST_MU_MAX_LSB 0xF04300FF - -/* ALPHANOISE */ -#define R367_OFDM_ALPHANOISE 0xF044 -#define F367_OFDM_USE_ALLFILTER 0xF0440080 -#define F367_OFDM_INTER_ON 0xF0440040 -#define F367_OFDM_ALPHA_NOISE 0xF044001F - -/* MAXGP_MSB */ -#define R367_OFDM_MAXGP_MSB 0xF045 -#define F367_OFDM_MUFILTER_LENGTH 0xF04500F0 -#define F367_OFDM_MAX_GP_MSB 0xF045000F - -/* MAXGP_LSB */ -#define R367_OFDM_MAXGP_LSB 0xF046 -#define F367_OFDM_MAX_GP_LSB 0xF04600FF - -/* ALPHAMSB */ -#define R367_OFDM_ALPHAMSB 0xF047 -#define F367_OFDM_CHC_DATARATE 0xF04700C0 -#define F367_OFDM_ALPHA_MSB 0xF047003F - -/* ALPHALSB */ -#define R367_OFDM_ALPHALSB 0xF048 -#define F367_OFDM_ALPHA_LSB 0xF04800FF - -/* PILOT_ACCU */ -#define R367_OFDM_PILOT_ACCU 0xF049 -#define F367_OFDM_USE_SCAT4ADDAPT 0xF0490080 -#define F367_OFDM_PILOT_ACC 0xF049001F - -/* PILOTMU_ACCU */ -#define R367_OFDM_PILOTMU_ACCU 0xF04A -#define F367_OFDM_DISCARD_BAD_SP 0xF04A0080 -#define F367_OFDM_DISCARD_BAD_CP 0xF04A0040 -#define F367_OFDM_PILOT_MU_ACCU 0xF04A001F - -/* FILT_CHANNEL_EST */ -#define R367_OFDM_FILT_CHANNEL_EST 0xF04B -#define F367_OFDM_USE_FILT_PILOT 0xF04B0080 -#define F367_OFDM_FILT_CHANNEL 0xF04B007F - -/* ALPHA_NOPISE_FREQ */ -#define R367_OFDM_ALPHA_NOPISE_FREQ 0xF04C -#define F367_OFDM_NOISE_FREQ_FILT 0xF04C0040 -#define F367_OFDM_ALPHA_NOISE_FREQ 0xF04C003F - -/* RATIO_PILOT */ -#define R367_OFDM_RATIO_PILOT 0xF04D -#define F367_OFDM_RATIO_MEAN_SP 0xF04D00F0 -#define F367_OFDM_RATIO_MEAN_CP 0xF04D000F - -/* CHC_CTL */ -#define R367_OFDM_CHC_CTL 0xF04E -#define F367_OFDM_TRACK_EN 0xF04E0080 -#define F367_OFDM_NOISE_NORM_EN 0xF04E0040 -#define F367_OFDM_FORCE_CHC_RESET 0xF04E0020 -#define F367_OFDM_SHORT_TIME 0xF04E0010 -#define F367_OFDM_FORCE_STATE_EN 0xF04E0008 -#define F367_OFDM_FORCE_STATE 0xF04E0007 - -/* EPQ_ADJUST */ -#define R367_OFDM_EPQ_ADJUST 0xF04F -#define F367_OFDM_ADJUST_SCAT_IND 0xF04F00C0 -#define F367_OFDM_ONE_SYMBOL 0xF04F0010 -#define F367_OFDM_EPQ_DECAY 0xF04F000E -#define F367_OFDM_HOLD_SLOPE 0xF04F0001 - -/* EPQ_THRES */ -#define R367_OFDM_EPQ_THRES 0xF050 -#define F367_OFDM_EPQ_THR 0xF05000FF - -/* OMEGA_CTL */ -#define R367_OFDM_OMEGA_CTL 0xF051 -#define F367_OFDM_OMEGA_RST 0xF0510080 -#define F367_OFDM_FREEZE_OMEGA 0xF0510040 -#define F367_OFDM_OMEGA_SEL 0xF051003F - -/* GP_CTL */ -#define R367_OFDM_GP_CTL 0xF052 -#define F367_OFDM_CHC_STATE 0xF05200E0 -#define F367_OFDM_FREEZE_GP 0xF0520010 -#define F367_OFDM_GP_SEL 0xF052000F - -/* MUMSB */ -#define R367_OFDM_MUMSB 0xF053 -#define F367_OFDM_MU_MSB 0xF053007F - -/* MULSB */ -#define R367_OFDM_MULSB 0xF054 -#define F367_OFDM_MU_LSB 0xF05400FF - -/* GPMSB */ -#define R367_OFDM_GPMSB 0xF055 -#define F367_OFDM_CSI_THRESHOLD 0xF05500E0 -#define F367_OFDM_GP_MSB 0xF055000F - -/* GPLSB */ -#define R367_OFDM_GPLSB 0xF056 -#define F367_OFDM_GP_LSB 0xF05600FF - -/* OMEGAMSB */ -#define R367_OFDM_OMEGAMSB 0xF057 -#define F367_OFDM_OMEGA_MSB 0xF057007F - -/* OMEGALSB */ -#define R367_OFDM_OMEGALSB 0xF058 -#define F367_OFDM_OMEGA_LSB 0xF05800FF - -/* SCAT_NB */ -#define R367_OFDM_SCAT_NB 0xF059 -#define F367_OFDM_CHC_TEST 0xF05900F8 -#define F367_OFDM_SCAT_NUMB 0xF0590003 - -/* CHC_DUMMY */ -#define R367_OFDM_CHC_DUMMY 0xF05A -#define F367_OFDM_CHC_DUM 0xF05A00FF - -/* INC_CTL */ -#define R367_OFDM_INC_CTL 0xF05B -#define F367_OFDM_INC_BYPASS 0xF05B0080 -#define F367_OFDM_INC_NDEPTH 0xF05B000C -#define F367_OFDM_INC_MADEPTH 0xF05B0003 - -/* INCTHRES_COR1 */ -#define R367_OFDM_INCTHRES_COR1 0xF05C -#define F367_OFDM_INC_THRES_COR1 0xF05C00FF - -/* INCTHRES_COR2 */ -#define R367_OFDM_INCTHRES_COR2 0xF05D -#define F367_OFDM_INC_THRES_COR2 0xF05D00FF - -/* INCTHRES_DET1 */ -#define R367_OFDM_INCTHRES_DET1 0xF05E -#define F367_OFDM_INC_THRES_DET1 0xF05E003F - -/* INCTHRES_DET2 */ -#define R367_OFDM_INCTHRES_DET2 0xF05F -#define F367_OFDM_INC_THRES_DET2 0xF05F003F - -/* IIR_CELLNB */ -#define R367_OFDM_IIR_CELLNB 0xF060 -#define F367_OFDM_NRST_IIR 0xF0600080 -#define F367_OFDM_IIR_CELL_NB 0xF0600007 - -/* IIRCX_COEFF1_MSB */ -#define R367_OFDM_IIRCX_COEFF1_MSB 0xF061 -#define F367_OFDM_IIR_CX_COEFF1_MSB 0xF06100FF - -/* IIRCX_COEFF1_LSB */ -#define R367_OFDM_IIRCX_COEFF1_LSB 0xF062 -#define F367_OFDM_IIR_CX_COEFF1_LSB 0xF06200FF - -/* IIRCX_COEFF2_MSB */ -#define R367_OFDM_IIRCX_COEFF2_MSB 0xF063 -#define F367_OFDM_IIR_CX_COEFF2_MSB 0xF06300FF - -/* IIRCX_COEFF2_LSB */ -#define R367_OFDM_IIRCX_COEFF2_LSB 0xF064 -#define F367_OFDM_IIR_CX_COEFF2_LSB 0xF06400FF - -/* IIRCX_COEFF3_MSB */ -#define R367_OFDM_IIRCX_COEFF3_MSB 0xF065 -#define F367_OFDM_IIR_CX_COEFF3_MSB 0xF06500FF - -/* IIRCX_COEFF3_LSB */ -#define R367_OFDM_IIRCX_COEFF3_LSB 0xF066 -#define F367_OFDM_IIR_CX_COEFF3_LSB 0xF06600FF - -/* IIRCX_COEFF4_MSB */ -#define R367_OFDM_IIRCX_COEFF4_MSB 0xF067 -#define F367_OFDM_IIR_CX_COEFF4_MSB 0xF06700FF - -/* IIRCX_COEFF4_LSB */ -#define R367_OFDM_IIRCX_COEFF4_LSB 0xF068 -#define F367_OFDM_IIR_CX_COEFF4_LSB 0xF06800FF - -/* IIRCX_COEFF5_MSB */ -#define R367_OFDM_IIRCX_COEFF5_MSB 0xF069 -#define F367_OFDM_IIR_CX_COEFF5_MSB 0xF06900FF - -/* IIRCX_COEFF5_LSB */ -#define R367_OFDM_IIRCX_COEFF5_LSB 0xF06A -#define F367_OFDM_IIR_CX_COEFF5_LSB 0xF06A00FF - -/* FEPATH_CFG */ -#define R367_OFDM_FEPATH_CFG 0xF06B -#define F367_OFDM_DEMUX_SWAP 0xF06B0004 -#define F367_OFDM_DIGAGC_SWAP 0xF06B0002 -#define F367_OFDM_LONGPATH_IF 0xF06B0001 - -/* PMC1_FUNC */ -#define R367_OFDM_PMC1_FUNC 0xF06C -#define F367_OFDM_SOFT_RSTN 0xF06C0080 -#define F367_OFDM_PMC1_AVERAGE_TIME 0xF06C0078 -#define F367_OFDM_PMC1_WAIT_TIME 0xF06C0006 -#define F367_OFDM_PMC1_2N_SEL 0xF06C0001 - -/* PMC1_FOR */ -#define R367_OFDM_PMC1_FOR 0xF06D -#define F367_OFDM_PMC1_FORCE 0xF06D0080 -#define F367_OFDM_PMC1_FORCE_VALUE 0xF06D007C - -/* PMC2_FUNC */ -#define R367_OFDM_PMC2_FUNC 0xF06E -#define F367_OFDM_PMC2_SOFT_STN 0xF06E0080 -#define F367_OFDM_PMC2_ACCU_TIME 0xF06E0070 -#define F367_OFDM_PMC2_CMDP_MN 0xF06E0008 -#define F367_OFDM_PMC2_SWAP 0xF06E0004 - -/* STATUS_ERR_DA */ -#define R367_OFDM_STATUS_ERR_DA 0xF06F -#define F367_OFDM_COM_USEGAINTRK 0xF06F0080 -#define F367_OFDM_COM_AGCLOCK 0xF06F0040 -#define F367_OFDM_AUT_AGCLOCK 0xF06F0020 -#define F367_OFDM_MIN_ERR_X_LSB 0xF06F000F - -/* DIG_AGC_R */ -#define R367_OFDM_DIG_AGC_R 0xF070 -#define F367_OFDM_COM_SOFT_RSTN 0xF0700080 -#define F367_OFDM_COM_AGC_ON 0xF0700040 -#define F367_OFDM_COM_EARLY 0xF0700020 -#define F367_OFDM_AUT_SOFT_RESETN 0xF0700010 -#define F367_OFDM_AUT_AGC_ON 0xF0700008 -#define F367_OFDM_AUT_EARLY 0xF0700004 -#define F367_OFDM_AUT_ROT_EN 0xF0700002 -#define F367_OFDM_LOCK_SOFT_RESETN 0xF0700001 - -/* COMAGC_TARMSB */ -#define R367_OFDM_COMAGC_TARMSB 0xF071 -#define F367_OFDM_COM_AGC_TARGET_MSB 0xF07100FF - -/* COM_AGC_TAR_ENMODE */ -#define R367_OFDM_COM_AGC_TAR_ENMODE 0xF072 -#define F367_OFDM_COM_AGC_TARGET_LSB 0xF07200F0 -#define F367_OFDM_COM_ENMODE 0xF072000F - -/* COM_AGC_CFG */ -#define R367_OFDM_COM_AGC_CFG 0xF073 -#define F367_OFDM_COM_N 0xF07300F8 -#define F367_OFDM_COM_STABMODE 0xF0730006 -#define F367_OFDM_ERR_SEL 0xF0730001 - -/* COM_AGC_GAIN1 */ -#define R367_OFDM_COM_AGC_GAIN1 0xF074 -#define F367_OFDM_COM_GAIN1ACK 0xF07400F0 -#define F367_OFDM_COM_GAIN1TRK 0xF074000F - -/* AUT_AGC_TARGETMSB */ -#define R367_OFDM_AUT_AGC_TARGETMSB 0xF075 -#define F367_OFDM_AUT_AGC_TARGET_MSB 0xF07500FF - -/* LOCK_DET_MSB */ -#define R367_OFDM_LOCK_DET_MSB 0xF076 -#define F367_OFDM_LOCK_DETECT_MSB 0xF07600FF - -/* AGCTAR_LOCK_LSBS */ -#define R367_OFDM_AGCTAR_LOCK_LSBS 0xF077 -#define F367_OFDM_AUT_AGC_TARGET_LSB 0xF07700F0 -#define F367_OFDM_LOCK_DETECT_LSB 0xF077000F - -/* AUT_GAIN_EN */ -#define R367_OFDM_AUT_GAIN_EN 0xF078 -#define F367_OFDM_AUT_ENMODE 0xF07800F0 -#define F367_OFDM_AUT_GAIN2 0xF078000F - -/* AUT_CFG */ -#define R367_OFDM_AUT_CFG 0xF079 -#define F367_OFDM_AUT_N 0xF07900F8 -#define F367_OFDM_INT_CHOICE 0xF0790006 -#define F367_OFDM_INT_LOAD 0xF0790001 - -/* LOCKN */ -#define R367_OFDM_LOCKN 0xF07A -#define F367_OFDM_LOCK_N 0xF07A00F8 -#define F367_OFDM_SEL_IQNTAR 0xF07A0004 -#define F367_OFDM_LOCK_DETECT_CHOICE 0xF07A0003 - -/* INT_X_3 */ -#define R367_OFDM_INT_X_3 0xF07B -#define F367_OFDM_INT_X3 0xF07B00FF - -/* INT_X_2 */ -#define R367_OFDM_INT_X_2 0xF07C -#define F367_OFDM_INT_X2 0xF07C00FF - -/* INT_X_1 */ -#define R367_OFDM_INT_X_1 0xF07D -#define F367_OFDM_INT_X1 0xF07D00FF - -/* INT_X_0 */ -#define R367_OFDM_INT_X_0 0xF07E -#define F367_OFDM_INT_X0 0xF07E00FF - -/* MIN_ERRX_MSB */ -#define R367_OFDM_MIN_ERRX_MSB 0xF07F -#define F367_OFDM_MIN_ERR_X_MSB 0xF07F00FF - -/* COR_CTL */ -#define R367_OFDM_COR_CTL 0xF080 -#define F367_OFDM_CORE_ACTIVE 0xF0800020 -#define F367_OFDM_HOLD 0xF0800010 -#define F367_OFDM_CORE_STATE_CTL 0xF080000F - -/* COR_STAT */ -#define R367_OFDM_COR_STAT 0xF081 -#define F367_OFDM_SCATT_LOCKED 0xF0810080 -#define F367_OFDM_TPS_LOCKED 0xF0810040 -#define F367_OFDM_SYR_LOCKED_COR 0xF0810020 -#define F367_OFDM_AGC_LOCKED_STAT 0xF0810010 -#define F367_OFDM_CORE_STATE_STAT 0xF081000F - -/* COR_INTEN */ -#define R367_OFDM_COR_INTEN 0xF082 -#define F367_OFDM_INTEN 0xF0820080 -#define F367_OFDM_INTEN_SYR 0xF0820020 -#define F367_OFDM_INTEN_FFT 0xF0820010 -#define F367_OFDM_INTEN_AGC 0xF0820008 -#define F367_OFDM_INTEN_TPS1 0xF0820004 -#define F367_OFDM_INTEN_TPS2 0xF0820002 -#define F367_OFDM_INTEN_TPS3 0xF0820001 - -/* COR_INTSTAT */ -#define R367_OFDM_COR_INTSTAT 0xF083 -#define F367_OFDM_INTSTAT_SYR 0xF0830020 -#define F367_OFDM_INTSTAT_FFT 0xF0830010 -#define F367_OFDM_INTSAT_AGC 0xF0830008 -#define F367_OFDM_INTSTAT_TPS1 0xF0830004 -#define F367_OFDM_INTSTAT_TPS2 0xF0830002 -#define F367_OFDM_INTSTAT_TPS3 0xF0830001 - -/* COR_MODEGUARD */ -#define R367_OFDM_COR_MODEGUARD 0xF084 -#define F367_OFDM_FORCE 0xF0840010 -#define F367_OFDM_MODE 0xF084000C -#define F367_OFDM_GUARD 0xF0840003 - -/* AGC_CTL */ -#define R367_OFDM_AGC_CTL 0xF085 -#define F367_OFDM_AGC_TIMING_FACTOR 0xF08500E0 -#define F367_OFDM_AGC_LAST 0xF0850010 -#define F367_OFDM_AGC_GAIN 0xF085000C -#define F367_OFDM_AGC_NEG 0xF0850002 -#define F367_OFDM_AGC_SET 0xF0850001 - -/* AGC_MANUAL1 */ -#define R367_OFDM_AGC_MANUAL1 0xF086 -#define F367_OFDM_AGC_VAL_LO 0xF08600FF - -/* AGC_MANUAL2 */ -#define R367_OFDM_AGC_MANUAL2 0xF087 -#define F367_OFDM_AGC_VAL_HI 0xF087000F - -/* AGC_TARG */ -#define R367_OFDM_AGC_TARG 0xF088 -#define F367_OFDM_AGC_TARGET 0xF08800FF - -/* AGC_GAIN1 */ -#define R367_OFDM_AGC_GAIN1 0xF089 -#define F367_OFDM_AGC_GAIN_LO 0xF08900FF - -/* AGC_GAIN2 */ -#define R367_OFDM_AGC_GAIN2 0xF08A -#define F367_OFDM_AGC_LOCKED_GAIN2 0xF08A0010 -#define F367_OFDM_AGC_GAIN_HI 0xF08A000F - -/* RESERVED_1 */ -#define R367_OFDM_RESERVED_1 0xF08B -#define F367_OFDM_RESERVED1 0xF08B00FF - -/* RESERVED_2 */ -#define R367_OFDM_RESERVED_2 0xF08C -#define F367_OFDM_RESERVED2 0xF08C00FF - -/* RESERVED_3 */ -#define R367_OFDM_RESERVED_3 0xF08D -#define F367_OFDM_RESERVED3 0xF08D00FF - -/* CAS_CTL */ -#define R367_OFDM_CAS_CTL 0xF08E -#define F367_OFDM_CCS_ENABLE 0xF08E0080 -#define F367_OFDM_ACS_DISABLE 0xF08E0040 -#define F367_OFDM_DAGC_DIS 0xF08E0020 -#define F367_OFDM_DAGC_GAIN 0xF08E0018 -#define F367_OFDM_CCSMU 0xF08E0007 - -/* CAS_FREQ */ -#define R367_OFDM_CAS_FREQ 0xF08F -#define F367_OFDM_CCS_FREQ 0xF08F00FF - -/* CAS_DAGCGAIN */ -#define R367_OFDM_CAS_DAGCGAIN 0xF090 -#define F367_OFDM_CAS_DAGC_GAIN 0xF09000FF - -/* SYR_CTL */ -#define R367_OFDM_SYR_CTL 0xF091 -#define F367_OFDM_SICTH_ENABLE 0xF0910080 -#define F367_OFDM_LONG_ECHO 0xF0910078 -#define F367_OFDM_AUTO_LE_EN 0xF0910004 -#define F367_OFDM_SYR_BYPASS 0xF0910002 -#define F367_OFDM_SYR_TR_DIS 0xF0910001 - -/* SYR_STAT */ -#define R367_OFDM_SYR_STAT 0xF092 -#define F367_OFDM_SYR_LOCKED_STAT 0xF0920010 -#define F367_OFDM_SYR_MODE 0xF092000C -#define F367_OFDM_SYR_GUARD 0xF0920003 - -/* SYR_NCO1 */ -#define R367_OFDM_SYR_NCO1 0xF093 -#define F367_OFDM_SYR_NCO_LO 0xF09300FF - -/* SYR_NCO2 */ -#define R367_OFDM_SYR_NCO2 0xF094 -#define F367_OFDM_SYR_NCO_HI 0xF094003F - -/* SYR_OFFSET1 */ -#define R367_OFDM_SYR_OFFSET1 0xF095 -#define F367_OFDM_SYR_OFFSET_LO 0xF09500FF - -/* SYR_OFFSET2 */ -#define R367_OFDM_SYR_OFFSET2 0xF096 -#define F367_OFDM_SYR_OFFSET_HI 0xF096003F - -/* FFT_CTL */ -#define R367_OFDM_FFT_CTL 0xF097 -#define F367_OFDM_SHIFT_FFT_TRIG 0xF0970018 -#define F367_OFDM_FFT_TRIGGER 0xF0970004 -#define F367_OFDM_FFT_MANUAL 0xF0970002 -#define F367_OFDM_IFFT_MODE 0xF0970001 - -/* SCR_CTL */ -#define R367_OFDM_SCR_CTL 0xF098 -#define F367_OFDM_SYRADJDECAY 0xF0980070 -#define F367_OFDM_SCR_CPEDIS 0xF0980002 -#define F367_OFDM_SCR_DIS 0xF0980001 - -/* PPM_CTL1 */ -#define R367_OFDM_PPM_CTL1 0xF099 -#define F367_OFDM_PPM_MAXFREQ 0xF0990030 -#define F367_OFDM_PPM_MAXTIM 0xF0990008 -#define F367_OFDM_PPM_INVSEL 0xF0990004 -#define F367_OFDM_PPM_SCATDIS 0xF0990002 -#define F367_OFDM_PPM_BYP 0xF0990001 - -/* TRL_CTL */ -#define R367_OFDM_TRL_CTL 0xF09A -#define F367_OFDM_TRL_NOMRATE_LSB 0xF09A0080 -#define F367_OFDM_TRL_GAIN_FACTOR 0xF09A0078 -#define F367_OFDM_TRL_LOOPGAIN 0xF09A0007 - -/* TRL_NOMRATE1 */ -#define R367_OFDM_TRL_NOMRATE1 0xF09B -#define F367_OFDM_TRL_NOMRATE_LO 0xF09B00FF - -/* TRL_NOMRATE2 */ -#define R367_OFDM_TRL_NOMRATE2 0xF09C -#define F367_OFDM_TRL_NOMRATE_HI 0xF09C00FF - -/* TRL_TIME1 */ -#define R367_OFDM_TRL_TIME1 0xF09D -#define F367_OFDM_TRL_TOFFSET_LO 0xF09D00FF - -/* TRL_TIME2 */ -#define R367_OFDM_TRL_TIME2 0xF09E -#define F367_OFDM_TRL_TOFFSET_HI 0xF09E00FF - -/* CRL_CTL */ -#define R367_OFDM_CRL_CTL 0xF09F -#define F367_OFDM_CRL_DIS 0xF09F0080 -#define F367_OFDM_CRL_GAIN_FACTOR 0xF09F0078 -#define F367_OFDM_CRL_LOOPGAIN 0xF09F0007 - -/* CRL_FREQ1 */ -#define R367_OFDM_CRL_FREQ1 0xF0A0 -#define F367_OFDM_CRL_FOFFSET_LO 0xF0A000FF - -/* CRL_FREQ2 */ -#define R367_OFDM_CRL_FREQ2 0xF0A1 -#define F367_OFDM_CRL_FOFFSET_HI 0xF0A100FF - -/* CRL_FREQ3 */ -#define R367_OFDM_CRL_FREQ3 0xF0A2 -#define F367_OFDM_CRL_FOFFSET_VHI 0xF0A200FF - -/* TPS_SFRAME_CTL */ -#define R367_OFDM_TPS_SFRAME_CTL 0xF0A3 -#define F367_OFDM_TPS_SFRAME_SYNC 0xF0A30001 - -/* CHC_SNR */ -#define R367_OFDM_CHC_SNR 0xF0A4 -#define F367_OFDM_CHCSNR 0xF0A400FF - -/* BDI_CTL */ -#define R367_OFDM_BDI_CTL 0xF0A5 -#define F367_OFDM_BDI_LPSEL 0xF0A50002 -#define F367_OFDM_BDI_SERIAL 0xF0A50001 - -/* DMP_CTL */ -#define R367_OFDM_DMP_CTL 0xF0A6 -#define F367_OFDM_DMP_SCALING_FACTOR 0xF0A6001E -#define F367_OFDM_DMP_SDDIS 0xF0A60001 - -/* TPS_RCVD1 */ -#define R367_OFDM_TPS_RCVD1 0xF0A7 -#define F367_OFDM_TPS_CHANGE 0xF0A70040 -#define F367_OFDM_BCH_OK 0xF0A70020 -#define F367_OFDM_TPS_SYNC 0xF0A70010 -#define F367_OFDM_TPS_FRAME 0xF0A70003 - -/* TPS_RCVD2 */ -#define R367_OFDM_TPS_RCVD2 0xF0A8 -#define F367_OFDM_TPS_HIERMODE 0xF0A80070 -#define F367_OFDM_TPS_CONST 0xF0A80003 - -/* TPS_RCVD3 */ -#define R367_OFDM_TPS_RCVD3 0xF0A9 -#define F367_OFDM_TPS_LPCODE 0xF0A90070 -#define F367_OFDM_TPS_HPCODE 0xF0A90007 - -/* TPS_RCVD4 */ -#define R367_OFDM_TPS_RCVD4 0xF0AA -#define F367_OFDM_TPS_GUARD 0xF0AA0030 -#define F367_OFDM_TPS_MODE 0xF0AA0003 - -/* TPS_ID_CELL1 */ -#define R367_OFDM_TPS_ID_CELL1 0xF0AB -#define F367_OFDM_TPS_ID_CELL_LO 0xF0AB00FF - -/* TPS_ID_CELL2 */ -#define R367_OFDM_TPS_ID_CELL2 0xF0AC -#define F367_OFDM_TPS_ID_CELL_HI 0xF0AC00FF - -/* TPS_RCVD5_SET1 */ -#define R367_OFDM_TPS_RCVD5_SET1 0xF0AD -#define F367_OFDM_TPS_NA 0xF0AD00FC -#define F367_OFDM_TPS_SETFRAME 0xF0AD0003 - -/* TPS_SET2 */ -#define R367_OFDM_TPS_SET2 0xF0AE -#define F367_OFDM_TPS_SETHIERMODE 0xF0AE0070 -#define F367_OFDM_TPS_SETCONST 0xF0AE0003 - -/* TPS_SET3 */ -#define R367_OFDM_TPS_SET3 0xF0AF -#define F367_OFDM_TPS_SETLPCODE 0xF0AF0070 -#define F367_OFDM_TPS_SETHPCODE 0xF0AF0007 - -/* TPS_CTL */ -#define R367_OFDM_TPS_CTL 0xF0B0 -#define F367_OFDM_TPS_IMM 0xF0B00004 -#define F367_OFDM_TPS_BCHDIS 0xF0B00002 -#define F367_OFDM_TPS_UPDDIS 0xF0B00001 - -/* CTL_FFTOSNUM */ -#define R367_OFDM_CTL_FFTOSNUM 0xF0B1 -#define F367_OFDM_SYMBOL_NUMBER 0xF0B1007F - -/* TESTSELECT */ -#define R367_OFDM_TESTSELECT 0xF0B2 -#define F367_OFDM_TEST_SELECT 0xF0B2001F - -/* MSC_REV */ -#define R367_OFDM_MSC_REV 0xF0B3 -#define F367_OFDM_REV_NUMBER 0xF0B300FF - -/* PIR_CTL */ -#define R367_OFDM_PIR_CTL 0xF0B4 -#define F367_OFDM_FREEZE 0xF0B40001 - -/* SNR_CARRIER1 */ -#define R367_OFDM_SNR_CARRIER1 0xF0B5 -#define F367_OFDM_SNR_CARRIER_LO 0xF0B500FF - -/* SNR_CARRIER2 */ -#define R367_OFDM_SNR_CARRIER2 0xF0B6 -#define F367_OFDM_MEAN 0xF0B600C0 -#define F367_OFDM_SNR_CARRIER_HI 0xF0B6001F - -/* PPM_CPAMP */ -#define R367_OFDM_PPM_CPAMP 0xF0B7 -#define F367_OFDM_PPM_CPC 0xF0B700FF - -/* TSM_AP0 */ -#define R367_OFDM_TSM_AP0 0xF0B8 -#define F367_OFDM_ADDRESS_BYTE_0 0xF0B800FF - -/* TSM_AP1 */ -#define R367_OFDM_TSM_AP1 0xF0B9 -#define F367_OFDM_ADDRESS_BYTE_1 0xF0B900FF - -/* TSM_AP2 */ -#define R367_OFDM_TSM_AP2 0xF0BA -#define F367_OFDM_DATA_BYTE_0 0xF0BA00FF - -/* TSM_AP3 */ -#define R367_OFDM_TSM_AP3 0xF0BB -#define F367_OFDM_DATA_BYTE_1 0xF0BB00FF - -/* TSM_AP4 */ -#define R367_OFDM_TSM_AP4 0xF0BC -#define F367_OFDM_DATA_BYTE_2 0xF0BC00FF - -/* TSM_AP5 */ -#define R367_OFDM_TSM_AP5 0xF0BD -#define F367_OFDM_DATA_BYTE_3 0xF0BD00FF - -/* TSM_AP6 */ -#define R367_OFDM_TSM_AP6 0xF0BE -#define F367_OFDM_TSM_AP_6 0xF0BE00FF - -/* TSM_AP7 */ -#define R367_OFDM_TSM_AP7 0xF0BF -#define F367_OFDM_MEM_SELECT_BYTE 0xF0BF00FF - -/* TSTRES */ -#define R367_TSTRES 0xF0C0 -#define F367_FRES_DISPLAY 0xF0C00080 -#define F367_FRES_FIFO_AD 0xF0C00020 -#define F367_FRESRS 0xF0C00010 -#define F367_FRESACS 0xF0C00008 -#define F367_FRESFEC 0xF0C00004 -#define F367_FRES_PRIF 0xF0C00002 -#define F367_FRESCORE 0xF0C00001 - -/* ANACTRL */ -#define R367_ANACTRL 0xF0C1 -#define F367_BYPASS_XTAL 0xF0C10040 -#define F367_BYPASS_PLLXN 0xF0C1000C -#define F367_DIS_PAD_OSC 0xF0C10002 -#define F367_STDBY_PLLXN 0xF0C10001 - -/* TSTBUS */ -#define R367_TSTBUS 0xF0C2 -#define F367_TS_BYTE_CLK_INV 0xF0C20080 -#define F367_CFG_IP 0xF0C20070 -#define F367_CFG_TST 0xF0C2000F - -/* TSTRATE */ -#define R367_TSTRATE 0xF0C6 -#define F367_FORCEPHA 0xF0C60080 -#define F367_FNEWPHA 0xF0C60010 -#define F367_FROT90 0xF0C60008 -#define F367_FR 0xF0C60007 - -/* CONSTMODE */ -#define R367_OFDM_CONSTMODE 0xF0CB -#define F367_OFDM_TST_PRIF 0xF0CB00E0 -#define F367_OFDM_CAR_TYPE 0xF0CB0018 -#define F367_OFDM_CONST_MODE 0xF0CB0003 - -/* CONSTCARR1 */ -#define R367_OFDM_CONSTCARR1 0xF0CC -#define F367_OFDM_CONST_CARR_LO 0xF0CC00FF - -/* CONSTCARR2 */ -#define R367_OFDM_CONSTCARR2 0xF0CD -#define F367_OFDM_CONST_CARR_HI 0xF0CD001F - -/* ICONSTEL */ -#define R367_OFDM_ICONSTEL 0xF0CE -#define F367_OFDM_PICONSTEL 0xF0CE00FF - -/* QCONSTEL */ -#define R367_OFDM_QCONSTEL 0xF0CF -#define F367_OFDM_PQCONSTEL 0xF0CF00FF - -/* TSTBISTRES0 */ -#define R367_OFDM_TSTBISTRES0 0xF0D0 -#define F367_OFDM_BEND_PPM 0xF0D00080 -#define F367_OFDM_BBAD_PPM 0xF0D00040 -#define F367_OFDM_BEND_FFTW 0xF0D00020 -#define F367_OFDM_BBAD_FFTW 0xF0D00010 -#define F367_OFDM_BEND_FFT_BUF 0xF0D00008 -#define F367_OFDM_BBAD_FFT_BUF 0xF0D00004 -#define F367_OFDM_BEND_SYR 0xF0D00002 -#define F367_OFDM_BBAD_SYR 0xF0D00001 - -/* TSTBISTRES1 */ -#define R367_OFDM_TSTBISTRES1 0xF0D1 -#define F367_OFDM_BEND_CHC_CP 0xF0D10080 -#define F367_OFDM_BBAD_CHC_CP 0xF0D10040 -#define F367_OFDM_BEND_CHCI 0xF0D10020 -#define F367_OFDM_BBAD_CHCI 0xF0D10010 -#define F367_OFDM_BEND_BDI 0xF0D10008 -#define F367_OFDM_BBAD_BDI 0xF0D10004 -#define F367_OFDM_BEND_SDI 0xF0D10002 -#define F367_OFDM_BBAD_SDI 0xF0D10001 - -/* TSTBISTRES2 */ -#define R367_OFDM_TSTBISTRES2 0xF0D2 -#define F367_OFDM_BEND_CHC_INC 0xF0D20080 -#define F367_OFDM_BBAD_CHC_INC 0xF0D20040 -#define F367_OFDM_BEND_CHC_SPP 0xF0D20020 -#define F367_OFDM_BBAD_CHC_SPP 0xF0D20010 -#define F367_OFDM_BEND_CHC_CPP 0xF0D20008 -#define F367_OFDM_BBAD_CHC_CPP 0xF0D20004 -#define F367_OFDM_BEND_CHC_SP 0xF0D20002 -#define F367_OFDM_BBAD_CHC_SP 0xF0D20001 - -/* TSTBISTRES3 */ -#define R367_OFDM_TSTBISTRES3 0xF0D3 -#define F367_OFDM_BEND_QAM 0xF0D30080 -#define F367_OFDM_BBAD_QAM 0xF0D30040 -#define F367_OFDM_BEND_SFEC_VIT 0xF0D30020 -#define F367_OFDM_BBAD_SFEC_VIT 0xF0D30010 -#define F367_OFDM_BEND_SFEC_DLINE 0xF0D30008 -#define F367_OFDM_BBAD_SFEC_DLINE 0xF0D30004 -#define F367_OFDM_BEND_SFEC_HW 0xF0D30002 -#define F367_OFDM_BBAD_SFEC_HW 0xF0D30001 - -/* RF_AGC1 */ -#define R367_RF_AGC1 0xF0D4 -#define F367_RF_AGC1_LEVEL_HI 0xF0D400FF - -/* RF_AGC2 */ -#define R367_RF_AGC2 0xF0D5 -#define F367_REF_ADGP 0xF0D50080 -#define F367_STDBY_ADCGP 0xF0D50020 -#define F367_CHANNEL_SEL 0xF0D5001C -#define F367_RF_AGC1_LEVEL_LO 0xF0D50003 - -/* ANADIGCTRL */ -#define R367_ANADIGCTRL 0xF0D7 -#define F367_SEL_CLKDEM 0xF0D70020 -#define F367_EN_BUFFER_Q 0xF0D70010 -#define F367_EN_BUFFER_I 0xF0D70008 -#define F367_ADC_RIS_EGDE 0xF0D70004 -#define F367_SGN_ADC 0xF0D70002 -#define F367_SEL_AD12_SYNC 0xF0D70001 - -/* PLLMDIV */ -#define R367_PLLMDIV 0xF0D8 -#define F367_PLL_MDIV 0xF0D800FF - -/* PLLNDIV */ -#define R367_PLLNDIV 0xF0D9 -#define F367_PLL_NDIV 0xF0D900FF - -/* PLLSETUP */ -#define R367_PLLSETUP 0xF0DA -#define F367_PLL_PDIV 0xF0DA0070 -#define F367_PLL_KDIV 0xF0DA000F - -/* DUAL_AD12 */ -#define R367_DUAL_AD12 0xF0DB -#define F367_FS20M 0xF0DB0020 -#define F367_FS50M 0xF0DB0010 -#define F367_INMODE0 0xF0DB0008 -#define F367_POFFQ 0xF0DB0004 -#define F367_POFFI 0xF0DB0002 -#define F367_INMODE1 0xF0DB0001 - -/* TSTBIST */ -#define R367_TSTBIST 0xF0DC -#define F367_TST_BYP_CLK 0xF0DC0080 -#define F367_TST_GCLKENA_STD 0xF0DC0040 -#define F367_TST_GCLKENA 0xF0DC0020 -#define F367_TST_MEMBIST 0xF0DC001F - -/* PAD_COMP_CTRL */ -#define R367_PAD_COMP_CTRL 0xF0DD -#define F367_COMPTQ 0xF0DD0010 -#define F367_COMPEN 0xF0DD0008 -#define F367_FREEZE2 0xF0DD0004 -#define F367_SLEEP_INHBT 0xF0DD0002 -#define F367_CHIP_SLEEP 0xF0DD0001 - -/* PAD_COMP_WR */ -#define R367_PAD_COMP_WR 0xF0DE -#define F367_WR_ASRC 0xF0DE007F - -/* PAD_COMP_RD */ -#define R367_PAD_COMP_RD 0xF0DF -#define F367_COMPOK 0xF0DF0080 -#define F367_RD_ASRC 0xF0DF007F - -/* SYR_TARGET_FFTADJT_MSB */ -#define R367_OFDM_SYR_TARGET_FFTADJT_MSB 0xF100 -#define F367_OFDM_SYR_START 0xF1000080 -#define F367_OFDM_SYR_TARGET_FFTADJ_HI 0xF100000F - -/* SYR_TARGET_FFTADJT_LSB */ -#define R367_OFDM_SYR_TARGET_FFTADJT_LSB 0xF101 -#define F367_OFDM_SYR_TARGET_FFTADJ_LO 0xF10100FF - -/* SYR_TARGET_CHCADJT_MSB */ -#define R367_OFDM_SYR_TARGET_CHCADJT_MSB 0xF102 -#define F367_OFDM_SYR_TARGET_CHCADJ_HI 0xF102000F - -/* SYR_TARGET_CHCADJT_LSB */ -#define R367_OFDM_SYR_TARGET_CHCADJT_LSB 0xF103 -#define F367_OFDM_SYR_TARGET_CHCADJ_LO 0xF10300FF - -/* SYR_FLAG */ -#define R367_OFDM_SYR_FLAG 0xF104 -#define F367_OFDM_TRIG_FLG1 0xF1040080 -#define F367_OFDM_TRIG_FLG0 0xF1040040 -#define F367_OFDM_FFT_FLG1 0xF1040008 -#define F367_OFDM_FFT_FLG0 0xF1040004 -#define F367_OFDM_CHC_FLG1 0xF1040002 -#define F367_OFDM_CHC_FLG0 0xF1040001 - -/* CRL_TARGET1 */ -#define R367_OFDM_CRL_TARGET1 0xF105 -#define F367_OFDM_CRL_START 0xF1050080 -#define F367_OFDM_CRL_TARGET_VHI 0xF105000F - -/* CRL_TARGET2 */ -#define R367_OFDM_CRL_TARGET2 0xF106 -#define F367_OFDM_CRL_TARGET_HI 0xF10600FF - -/* CRL_TARGET3 */ -#define R367_OFDM_CRL_TARGET3 0xF107 -#define F367_OFDM_CRL_TARGET_LO 0xF10700FF - -/* CRL_TARGET4 */ -#define R367_OFDM_CRL_TARGET4 0xF108 -#define F367_OFDM_CRL_TARGET_VLO 0xF10800FF - -/* CRL_FLAG */ -#define R367_OFDM_CRL_FLAG 0xF109 -#define F367_OFDM_CRL_FLAG1 0xF1090002 -#define F367_OFDM_CRL_FLAG0 0xF1090001 - -/* TRL_TARGET1 */ -#define R367_OFDM_TRL_TARGET1 0xF10A -#define F367_OFDM_TRL_TARGET_HI 0xF10A00FF - -/* TRL_TARGET2 */ -#define R367_OFDM_TRL_TARGET2 0xF10B -#define F367_OFDM_TRL_TARGET_LO 0xF10B00FF - -/* TRL_CHC */ -#define R367_OFDM_TRL_CHC 0xF10C -#define F367_OFDM_TRL_START 0xF10C0080 -#define F367_OFDM_CHC_START 0xF10C0040 -#define F367_OFDM_TRL_FLAG1 0xF10C0002 -#define F367_OFDM_TRL_FLAG0 0xF10C0001 - -/* CHC_SNR_TARG */ -#define R367_OFDM_CHC_SNR_TARG 0xF10D -#define F367_OFDM_CHC_SNR_TARGET 0xF10D00FF - -/* TOP_TRACK */ -#define R367_OFDM_TOP_TRACK 0xF10E -#define F367_OFDM_TOP_START 0xF10E0080 -#define F367_OFDM_FIRST_FLAG 0xF10E0070 -#define F367_OFDM_TOP_FLAG1 0xF10E0008 -#define F367_OFDM_TOP_FLAG0 0xF10E0004 -#define F367_OFDM_CHC_FLAG1 0xF10E0002 -#define F367_OFDM_CHC_FLAG0 0xF10E0001 - -/* TRACKER_FREE1 */ -#define R367_OFDM_TRACKER_FREE1 0xF10F -#define F367_OFDM_TRACKER_FREE_1 0xF10F00FF - -/* ERROR_CRL1 */ -#define R367_OFDM_ERROR_CRL1 0xF110 -#define F367_OFDM_ERROR_CRL_VHI 0xF11000FF - -/* ERROR_CRL2 */ -#define R367_OFDM_ERROR_CRL2 0xF111 -#define F367_OFDM_ERROR_CRL_HI 0xF11100FF - -/* ERROR_CRL3 */ -#define R367_OFDM_ERROR_CRL3 0xF112 -#define F367_OFDM_ERROR_CRL_LOI 0xF11200FF - -/* ERROR_CRL4 */ -#define R367_OFDM_ERROR_CRL4 0xF113 -#define F367_OFDM_ERROR_CRL_VLO 0xF11300FF - -/* DEC_NCO1 */ -#define R367_OFDM_DEC_NCO1 0xF114 -#define F367_OFDM_DEC_NCO_VHI 0xF11400FF - -/* DEC_NCO2 */ -#define R367_OFDM_DEC_NCO2 0xF115 -#define F367_OFDM_DEC_NCO_HI 0xF11500FF - -/* DEC_NCO3 */ -#define R367_OFDM_DEC_NCO3 0xF116 -#define F367_OFDM_DEC_NCO_LO 0xF11600FF - -/* SNR */ -#define R367_OFDM_SNR 0xF117 -#define F367_OFDM_SNRATIO 0xF11700FF - -/* SYR_FFTADJ1 */ -#define R367_OFDM_SYR_FFTADJ1 0xF118 -#define F367_OFDM_SYR_FFTADJ_HI 0xF11800FF - -/* SYR_FFTADJ2 */ -#define R367_OFDM_SYR_FFTADJ2 0xF119 -#define F367_OFDM_SYR_FFTADJ_LO 0xF11900FF - -/* SYR_CHCADJ1 */ -#define R367_OFDM_SYR_CHCADJ1 0xF11A -#define F367_OFDM_SYR_CHCADJ_HI 0xF11A00FF - -/* SYR_CHCADJ2 */ -#define R367_OFDM_SYR_CHCADJ2 0xF11B -#define F367_OFDM_SYR_CHCADJ_LO 0xF11B00FF - -/* SYR_OFF */ -#define R367_OFDM_SYR_OFF 0xF11C -#define F367_OFDM_SYR_OFFSET 0xF11C00FF - -/* PPM_OFFSET1 */ -#define R367_OFDM_PPM_OFFSET1 0xF11D -#define F367_OFDM_PPM_OFFSET_HI 0xF11D00FF - -/* PPM_OFFSET2 */ -#define R367_OFDM_PPM_OFFSET2 0xF11E -#define F367_OFDM_PPM_OFFSET_LO 0xF11E00FF - -/* TRACKER_FREE2 */ -#define R367_OFDM_TRACKER_FREE2 0xF11F -#define F367_OFDM_TRACKER_FREE_2 0xF11F00FF - -/* DEBG_LT10 */ -#define R367_OFDM_DEBG_LT10 0xF120 -#define F367_OFDM_DEBUG_LT10 0xF12000FF - -/* DEBG_LT11 */ -#define R367_OFDM_DEBG_LT11 0xF121 -#define F367_OFDM_DEBUG_LT11 0xF12100FF - -/* DEBG_LT12 */ -#define R367_OFDM_DEBG_LT12 0xF122 -#define F367_OFDM_DEBUG_LT12 0xF12200FF - -/* DEBG_LT13 */ -#define R367_OFDM_DEBG_LT13 0xF123 -#define F367_OFDM_DEBUG_LT13 0xF12300FF - -/* DEBG_LT14 */ -#define R367_OFDM_DEBG_LT14 0xF124 -#define F367_OFDM_DEBUG_LT14 0xF12400FF - -/* DEBG_LT15 */ -#define R367_OFDM_DEBG_LT15 0xF125 -#define F367_OFDM_DEBUG_LT15 0xF12500FF - -/* DEBG_LT16 */ -#define R367_OFDM_DEBG_LT16 0xF126 -#define F367_OFDM_DEBUG_LT16 0xF12600FF - -/* DEBG_LT17 */ -#define R367_OFDM_DEBG_LT17 0xF127 -#define F367_OFDM_DEBUG_LT17 0xF12700FF - -/* DEBG_LT18 */ -#define R367_OFDM_DEBG_LT18 0xF128 -#define F367_OFDM_DEBUG_LT18 0xF12800FF - -/* DEBG_LT19 */ -#define R367_OFDM_DEBG_LT19 0xF129 -#define F367_OFDM_DEBUG_LT19 0xF12900FF - -/* DEBG_LT1A */ -#define R367_OFDM_DEBG_LT1A 0xF12A -#define F367_OFDM_DEBUG_LT1A 0xF12A00FF - -/* DEBG_LT1B */ -#define R367_OFDM_DEBG_LT1B 0xF12B -#define F367_OFDM_DEBUG_LT1B 0xF12B00FF - -/* DEBG_LT1C */ -#define R367_OFDM_DEBG_LT1C 0xF12C -#define F367_OFDM_DEBUG_LT1C 0xF12C00FF - -/* DEBG_LT1D */ -#define R367_OFDM_DEBG_LT1D 0xF12D -#define F367_OFDM_DEBUG_LT1D 0xF12D00FF - -/* DEBG_LT1E */ -#define R367_OFDM_DEBG_LT1E 0xF12E -#define F367_OFDM_DEBUG_LT1E 0xF12E00FF - -/* DEBG_LT1F */ -#define R367_OFDM_DEBG_LT1F 0xF12F -#define F367_OFDM_DEBUG_LT1F 0xF12F00FF - -/* RCCFGH */ -#define R367_OFDM_RCCFGH 0xF200 -#define F367_OFDM_TSRCFIFO_DVBCI 0xF2000080 -#define F367_OFDM_TSRCFIFO_SERIAL 0xF2000040 -#define F367_OFDM_TSRCFIFO_DISABLE 0xF2000020 -#define F367_OFDM_TSFIFO_2TORC 0xF2000010 -#define F367_OFDM_TSRCFIFO_HSGNLOUT 0xF2000008 -#define F367_OFDM_TSRCFIFO_ERRMODE 0xF2000006 -#define F367_OFDM_RCCFGH_0 0xF2000001 - -/* RCCFGM */ -#define R367_OFDM_RCCFGM 0xF201 -#define F367_OFDM_TSRCFIFO_MANSPEED 0xF20100C0 -#define F367_OFDM_TSRCFIFO_PERMDATA 0xF2010020 -#define F367_OFDM_TSRCFIFO_NONEWSGNL 0xF2010010 -#define F367_OFDM_RCBYTE_OVERSAMPLING 0xF201000E -#define F367_OFDM_TSRCFIFO_INVDATA 0xF2010001 - -/* RCCFGL */ -#define R367_OFDM_RCCFGL 0xF202 -#define F367_OFDM_TSRCFIFO_BCLKDEL1CK 0xF20200C0 -#define F367_OFDM_RCCFGL_5 0xF2020020 -#define F367_OFDM_TSRCFIFO_DUTY50 0xF2020010 -#define F367_OFDM_TSRCFIFO_NSGNL2DATA 0xF2020008 -#define F367_OFDM_TSRCFIFO_DISSERMUX 0xF2020004 -#define F367_OFDM_RCCFGL_1 0xF2020002 -#define F367_OFDM_TSRCFIFO_STOPCKDIS 0xF2020001 - -/* RCINSDELH */ -#define R367_OFDM_RCINSDELH 0xF203 -#define F367_OFDM_TSRCDEL_SYNCBYTE 0xF2030080 -#define F367_OFDM_TSRCDEL_XXHEADER 0xF2030040 -#define F367_OFDM_TSRCDEL_BBHEADER 0xF2030020 -#define F367_OFDM_TSRCDEL_DATAFIELD 0xF2030010 -#define F367_OFDM_TSRCINSDEL_ISCR 0xF2030008 -#define F367_OFDM_TSRCINSDEL_NPD 0xF2030004 -#define F367_OFDM_TSRCINSDEL_RSPARITY 0xF2030002 -#define F367_OFDM_TSRCINSDEL_CRC8 0xF2030001 - -/* RCINSDELM */ -#define R367_OFDM_RCINSDELM 0xF204 -#define F367_OFDM_TSRCINS_BBPADDING 0xF2040080 -#define F367_OFDM_TSRCINS_BCHFEC 0xF2040040 -#define F367_OFDM_TSRCINS_LDPCFEC 0xF2040020 -#define F367_OFDM_TSRCINS_EMODCOD 0xF2040010 -#define F367_OFDM_TSRCINS_TOKEN 0xF2040008 -#define F367_OFDM_TSRCINS_XXXERR 0xF2040004 -#define F367_OFDM_TSRCINS_MATYPE 0xF2040002 -#define F367_OFDM_TSRCINS_UPL 0xF2040001 - -/* RCINSDELL */ -#define R367_OFDM_RCINSDELL 0xF205 -#define F367_OFDM_TSRCINS_DFL 0xF2050080 -#define F367_OFDM_TSRCINS_SYNCD 0xF2050040 -#define F367_OFDM_TSRCINS_BLOCLEN 0xF2050020 -#define F367_OFDM_TSRCINS_SIGPCOUNT 0xF2050010 -#define F367_OFDM_TSRCINS_FIFO 0xF2050008 -#define F367_OFDM_TSRCINS_REALPACK 0xF2050004 -#define F367_OFDM_TSRCINS_TSCONFIG 0xF2050002 -#define F367_OFDM_TSRCINS_LATENCY 0xF2050001 - -/* RCSTATUS */ -#define R367_OFDM_RCSTATUS 0xF206 -#define F367_OFDM_TSRCFIFO_LINEOK 0xF2060080 -#define F367_OFDM_TSRCFIFO_ERROR 0xF2060040 -#define F367_OFDM_TSRCFIFO_DATA7 0xF2060020 -#define F367_OFDM_RCSTATUS_4 0xF2060010 -#define F367_OFDM_TSRCFIFO_DEMODSEL 0xF2060008 -#define F367_OFDM_TSRC1FIFOSPEED_STORE 0xF2060004 -#define F367_OFDM_RCSTATUS_1 0xF2060002 -#define F367_OFDM_TSRCSERIAL_IMPOSSIBLE 0xF2060001 - -/* RCSPEED */ -#define R367_OFDM_RCSPEED 0xF207 -#define F367_OFDM_TSRCFIFO_OUTSPEED 0xF20700FF - -/* RCDEBUGM */ -#define R367_OFDM_RCDEBUGM 0xF208 -#define F367_OFDM_SD_UNSYNC 0xF2080080 -#define F367_OFDM_ULFLOCK_DETECTM 0xF2080040 -#define F367_OFDM_SUL_SELECTOS 0xF2080020 -#define F367_OFDM_DILUL_NOSCRBLE 0xF2080010 -#define F367_OFDM_NUL_SCRB 0xF2080008 -#define F367_OFDM_UL_SCRB 0xF2080004 -#define F367_OFDM_SCRAULBAD 0xF2080002 -#define F367_OFDM_SCRAUL_UNSYNC 0xF2080001 - -/* RCDEBUGL */ -#define R367_OFDM_RCDEBUGL 0xF209 -#define F367_OFDM_RS_ERR 0xF2090080 -#define F367_OFDM_LLFLOCK_DETECTM 0xF2090040 -#define F367_OFDM_NOT_SUL_SELECTOS 0xF2090020 -#define F367_OFDM_DILLL_NOSCRBLE 0xF2090010 -#define F367_OFDM_NLL_SCRB 0xF2090008 -#define F367_OFDM_LL_SCRB 0xF2090004 -#define F367_OFDM_SCRALLBAD 0xF2090002 -#define F367_OFDM_SCRALL_UNSYNC 0xF2090001 - -/* RCOBSCFG */ -#define R367_OFDM_RCOBSCFG 0xF20A -#define F367_OFDM_TSRCFIFO_OBSCFG 0xF20A00FF - -/* RCOBSM */ -#define R367_OFDM_RCOBSM 0xF20B -#define F367_OFDM_TSRCFIFO_OBSDATA_HI 0xF20B00FF - -/* RCOBSL */ -#define R367_OFDM_RCOBSL 0xF20C -#define F367_OFDM_TSRCFIFO_OBSDATA_LO 0xF20C00FF - -/* RCFECSPY */ -#define R367_OFDM_RCFECSPY 0xF210 -#define F367_OFDM_SPYRC_ENABLE 0xF2100080 -#define F367_OFDM_RCNO_SYNCBYTE 0xF2100040 -#define F367_OFDM_RCSERIAL_MODE 0xF2100020 -#define F367_OFDM_RCUNUSUAL_PACKET 0xF2100010 -#define F367_OFDM_BERRCMETER_DATAMODE 0xF210000C -#define F367_OFDM_BERRCMETER_LMODE 0xF2100002 -#define F367_OFDM_BERRCMETER_RESET 0xF2100001 - -/* RCFSPYCFG */ -#define R367_OFDM_RCFSPYCFG 0xF211 -#define F367_OFDM_FECSPYRC_INPUT 0xF21100C0 -#define F367_OFDM_RCRST_ON_ERROR 0xF2110020 -#define F367_OFDM_RCONE_SHOT 0xF2110010 -#define F367_OFDM_RCI2C_MODE 0xF211000C -#define F367_OFDM_SPYRC_HSTERESIS 0xF2110003 - -/* RCFSPYDATA */ -#define R367_OFDM_RCFSPYDATA 0xF212 -#define F367_OFDM_SPYRC_STUFFING 0xF2120080 -#define F367_OFDM_RCNOERR_PKTJITTER 0xF2120040 -#define F367_OFDM_SPYRC_CNULLPKT 0xF2120020 -#define F367_OFDM_SPYRC_OUTDATA_MODE 0xF212001F - -/* RCFSPYOUT */ -#define R367_OFDM_RCFSPYOUT 0xF213 -#define F367_OFDM_FSPYRC_DIRECT 0xF2130080 -#define F367_OFDM_RCFSPYOUT_6 0xF2130040 -#define F367_OFDM_SPYRC_OUTDATA_BUS 0xF2130038 -#define F367_OFDM_RCSTUFF_MODE 0xF2130007 - -/* RCFSTATUS */ -#define R367_OFDM_RCFSTATUS 0xF214 -#define F367_OFDM_SPYRC_ENDSIM 0xF2140080 -#define F367_OFDM_RCVALID_SIM 0xF2140040 -#define F367_OFDM_RCFOUND_SIGNAL 0xF2140020 -#define F367_OFDM_RCDSS_SYNCBYTE 0xF2140010 -#define F367_OFDM_RCRESULT_STATE 0xF214000F - -/* RCFGOODPACK */ -#define R367_OFDM_RCFGOODPACK 0xF215 -#define F367_OFDM_RCGOOD_PACKET 0xF21500FF - -/* RCFPACKCNT */ -#define R367_OFDM_RCFPACKCNT 0xF216 -#define F367_OFDM_RCPACKET_COUNTER 0xF21600FF - -/* RCFSPYMISC */ -#define R367_OFDM_RCFSPYMISC 0xF217 -#define F367_OFDM_RCLABEL_COUNTER 0xF21700FF - -/* RCFBERCPT4 */ -#define R367_OFDM_RCFBERCPT4 0xF218 -#define F367_OFDM_FBERRCMETER_CPT_MMMMSB 0xF21800FF - -/* RCFBERCPT3 */ -#define R367_OFDM_RCFBERCPT3 0xF219 -#define F367_OFDM_FBERRCMETER_CPT_MMMSB 0xF21900FF - -/* RCFBERCPT2 */ -#define R367_OFDM_RCFBERCPT2 0xF21A -#define F367_OFDM_FBERRCMETER_CPT_MMSB 0xF21A00FF - -/* RCFBERCPT1 */ -#define R367_OFDM_RCFBERCPT1 0xF21B -#define F367_OFDM_FBERRCMETER_CPT_MSB 0xF21B00FF - -/* RCFBERCPT0 */ -#define R367_OFDM_RCFBERCPT0 0xF21C -#define F367_OFDM_FBERRCMETER_CPT_LSB 0xF21C00FF - -/* RCFBERERR2 */ -#define R367_OFDM_RCFBERERR2 0xF21D -#define F367_OFDM_FBERRCMETER_ERR_HI 0xF21D00FF - -/* RCFBERERR1 */ -#define R367_OFDM_RCFBERERR1 0xF21E -#define F367_OFDM_FBERRCMETER_ERR 0xF21E00FF - -/* RCFBERERR0 */ -#define R367_OFDM_RCFBERERR0 0xF21F -#define F367_OFDM_FBERRCMETER_ERR_LO 0xF21F00FF - -/* RCFSTATESM */ -#define R367_OFDM_RCFSTATESM 0xF220 -#define F367_OFDM_RCRSTATE_F 0xF2200080 -#define F367_OFDM_RCRSTATE_E 0xF2200040 -#define F367_OFDM_RCRSTATE_D 0xF2200020 -#define F367_OFDM_RCRSTATE_C 0xF2200010 -#define F367_OFDM_RCRSTATE_B 0xF2200008 -#define F367_OFDM_RCRSTATE_A 0xF2200004 -#define F367_OFDM_RCRSTATE_9 0xF2200002 -#define F367_OFDM_RCRSTATE_8 0xF2200001 - -/* RCFSTATESL */ -#define R367_OFDM_RCFSTATESL 0xF221 -#define F367_OFDM_RCRSTATE_7 0xF2210080 -#define F367_OFDM_RCRSTATE_6 0xF2210040 -#define F367_OFDM_RCRSTATE_5 0xF2210020 -#define F367_OFDM_RCRSTATE_4 0xF2210010 -#define F367_OFDM_RCRSTATE_3 0xF2210008 -#define F367_OFDM_RCRSTATE_2 0xF2210004 -#define F367_OFDM_RCRSTATE_1 0xF2210002 -#define F367_OFDM_RCRSTATE_0 0xF2210001 - -/* RCFSPYBER */ -#define R367_OFDM_RCFSPYBER 0xF222 -#define F367_OFDM_RCFSPYBER_7 0xF2220080 -#define F367_OFDM_SPYRCOBS_XORREAD 0xF2220040 -#define F367_OFDM_FSPYRCBER_OBSMODE 0xF2220020 -#define F367_OFDM_FSPYRCBER_SYNCBYT 0xF2220010 -#define F367_OFDM_FSPYRCBER_UNSYNC 0xF2220008 -#define F367_OFDM_FSPYRCBER_CTIME 0xF2220007 - -/* RCFSPYDISTM */ -#define R367_OFDM_RCFSPYDISTM 0xF223 -#define F367_OFDM_RCPKTTIME_DISTANCE_HI 0xF22300FF - -/* RCFSPYDISTL */ -#define R367_OFDM_RCFSPYDISTL 0xF224 -#define F367_OFDM_RCPKTTIME_DISTANCE_LO 0xF22400FF - -/* RCFSPYOBS7 */ -#define R367_OFDM_RCFSPYOBS7 0xF228 -#define F367_OFDM_RCSPYOBS_SPYFAIL 0xF2280080 -#define F367_OFDM_RCSPYOBS_SPYFAIL1 0xF2280040 -#define F367_OFDM_RCSPYOBS_ERROR 0xF2280020 -#define F367_OFDM_RCSPYOBS_STROUT 0xF2280010 -#define F367_OFDM_RCSPYOBS_RESULTSTATE1 0xF228000F - -/* RCFSPYOBS6 */ -#define R367_OFDM_RCFSPYOBS6 0xF229 -#define F367_OFDM_RCSPYOBS_RESULTSTATE0 0xF22900F0 -#define F367_OFDM_RCSPYOBS_RESULTSTATEM1 0xF229000F - -/* RCFSPYOBS5 */ -#define R367_OFDM_RCFSPYOBS5 0xF22A -#define F367_OFDM_RCSPYOBS_BYTEOFPACKET1 0xF22A00FF - -/* RCFSPYOBS4 */ -#define R367_OFDM_RCFSPYOBS4 0xF22B -#define F367_OFDM_RCSPYOBS_BYTEVALUE1 0xF22B00FF - -/* RCFSPYOBS3 */ -#define R367_OFDM_RCFSPYOBS3 0xF22C -#define F367_OFDM_RCSPYOBS_DATA1 0xF22C00FF - -/* RCFSPYOBS2 */ -#define R367_OFDM_RCFSPYOBS2 0xF22D -#define F367_OFDM_RCSPYOBS_DATA0 0xF22D00FF - -/* RCFSPYOBS1 */ -#define R367_OFDM_RCFSPYOBS1 0xF22E -#define F367_OFDM_RCSPYOBS_DATAM1 0xF22E00FF - -/* RCFSPYOBS0 */ -#define R367_OFDM_RCFSPYOBS0 0xF22F -#define F367_OFDM_RCSPYOBS_DATAM2 0xF22F00FF - -/* TSGENERAL */ -#define R367_TSGENERAL 0xF230 -#define F367_TSGENERAL_7 0xF2300080 -#define F367_TSGENERAL_6 0xF2300040 -#define F367_TSFIFO_BCLK1ALL 0xF2300020 -#define F367_TSGENERAL_4 0xF2300010 -#define F367_MUXSTREAM_OUTMODE 0xF2300008 -#define F367_TSFIFO_PERMPARAL 0xF2300006 -#define F367_RST_REEDSOLO 0xF2300001 - -/* RC1SPEED */ -#define R367_RC1SPEED 0xF231 -#define F367_TSRCFIFO1_OUTSPEED 0xF23100FF - -/* TSGSTATUS */ -#define R367_TSGSTATUS 0xF232 -#define F367_TSGSTATUS_7 0xF2320080 -#define F367_TSGSTATUS_6 0xF2320040 -#define F367_RSMEM_FULL 0xF2320020 -#define F367_RS_MULTCALC 0xF2320010 -#define F367_RSIN_OVERTIME 0xF2320008 -#define F367_TSFIFO3_DEMODSEL 0xF2320004 -#define F367_TSFIFO2_DEMODSEL 0xF2320002 -#define F367_TSFIFO1_DEMODSEL 0xF2320001 - - -/* FECM */ -#define R367_OFDM_FECM 0xF233 -#define F367_OFDM_DSS_DVB 0xF2330080 -#define F367_OFDM_DEMOD_BYPASS 0xF2330040 -#define F367_OFDM_CMP_SLOWMODE 0xF2330020 -#define F367_OFDM_DSS_SRCH 0xF2330010 -#define F367_OFDM_FECM_3 0xF2330008 -#define F367_OFDM_DIFF_MODEVIT 0xF2330004 -#define F367_OFDM_SYNCVIT 0xF2330002 -#define F367_OFDM_I2CSYM 0xF2330001 - -/* VTH12 */ -#define R367_OFDM_VTH12 0xF234 -#define F367_OFDM_VTH_12 0xF23400FF - -/* VTH23 */ -#define R367_OFDM_VTH23 0xF235 -#define F367_OFDM_VTH_23 0xF23500FF - -/* VTH34 */ -#define R367_OFDM_VTH34 0xF236 -#define F367_OFDM_VTH_34 0xF23600FF - -/* VTH56 */ -#define R367_OFDM_VTH56 0xF237 -#define F367_OFDM_VTH_56 0xF23700FF - -/* VTH67 */ -#define R367_OFDM_VTH67 0xF238 -#define F367_OFDM_VTH_67 0xF23800FF - -/* VTH78 */ -#define R367_OFDM_VTH78 0xF239 -#define F367_OFDM_VTH_78 0xF23900FF - -/* VITCURPUN */ -#define R367_OFDM_VITCURPUN 0xF23A -#define F367_OFDM_VIT_MAPPING 0xF23A00E0 -#define F367_OFDM_VIT_CURPUN 0xF23A001F - -/* VERROR */ -#define R367_OFDM_VERROR 0xF23B -#define F367_OFDM_REGERR_VIT 0xF23B00FF - -/* PRVIT */ -#define R367_OFDM_PRVIT 0xF23C -#define F367_OFDM_PRVIT_7 0xF23C0080 -#define F367_OFDM_DIS_VTHLOCK 0xF23C0040 -#define F367_OFDM_E7_8VIT 0xF23C0020 -#define F367_OFDM_E6_7VIT 0xF23C0010 -#define F367_OFDM_E5_6VIT 0xF23C0008 -#define F367_OFDM_E3_4VIT 0xF23C0004 -#define F367_OFDM_E2_3VIT 0xF23C0002 -#define F367_OFDM_E1_2VIT 0xF23C0001 - -/* VAVSRVIT */ -#define R367_OFDM_VAVSRVIT 0xF23D -#define F367_OFDM_AMVIT 0xF23D0080 -#define F367_OFDM_FROZENVIT 0xF23D0040 -#define F367_OFDM_SNVIT 0xF23D0030 -#define F367_OFDM_TOVVIT 0xF23D000C -#define F367_OFDM_HYPVIT 0xF23D0003 - -/* VSTATUSVIT */ -#define R367_OFDM_VSTATUSVIT 0xF23E -#define F367_OFDM_VITERBI_ON 0xF23E0080 -#define F367_OFDM_END_LOOPVIT 0xF23E0040 -#define F367_OFDM_VITERBI_DEPRF 0xF23E0020 -#define F367_OFDM_PRFVIT 0xF23E0010 -#define F367_OFDM_LOCKEDVIT 0xF23E0008 -#define F367_OFDM_VITERBI_DELOCK 0xF23E0004 -#define F367_OFDM_VIT_DEMODSEL 0xF23E0002 -#define F367_OFDM_VITERBI_COMPOUT 0xF23E0001 - -/* VTHINUSE */ -#define R367_OFDM_VTHINUSE 0xF23F -#define F367_OFDM_VIT_INUSE 0xF23F00FF - -/* KDIV12 */ -#define R367_OFDM_KDIV12 0xF240 -#define F367_OFDM_KDIV12_MANUAL 0xF2400080 -#define F367_OFDM_K_DIVIDER_12 0xF240007F - -/* KDIV23 */ -#define R367_OFDM_KDIV23 0xF241 -#define F367_OFDM_KDIV23_MANUAL 0xF2410080 -#define F367_OFDM_K_DIVIDER_23 0xF241007F - -/* KDIV34 */ -#define R367_OFDM_KDIV34 0xF242 -#define F367_OFDM_KDIV34_MANUAL 0xF2420080 -#define F367_OFDM_K_DIVIDER_34 0xF242007F - -/* KDIV56 */ -#define R367_OFDM_KDIV56 0xF243 -#define F367_OFDM_KDIV56_MANUAL 0xF2430080 -#define F367_OFDM_K_DIVIDER_56 0xF243007F - -/* KDIV67 */ -#define R367_OFDM_KDIV67 0xF244 -#define F367_OFDM_KDIV67_MANUAL 0xF2440080 -#define F367_OFDM_K_DIVIDER_67 0xF244007F - -/* KDIV78 */ -#define R367_OFDM_KDIV78 0xF245 -#define F367_OFDM_KDIV78_MANUAL 0xF2450080 -#define F367_OFDM_K_DIVIDER_78 0xF245007F - -/* SIGPOWER */ -#define R367_OFDM_SIGPOWER 0xF246 -#define F367_OFDM_SIGPOWER_MANUAL 0xF2460080 -#define F367_OFDM_SIG_POWER 0xF246007F - -/* DEMAPVIT */ -#define R367_OFDM_DEMAPVIT 0xF247 -#define F367_OFDM_DEMAPVIT_7 0xF2470080 -#define F367_OFDM_K_DIVIDER_VIT 0xF247007F - -/* VITSCALE */ -#define R367_OFDM_VITSCALE 0xF248 -#define F367_OFDM_NVTH_NOSRANGE 0xF2480080 -#define F367_OFDM_VERROR_MAXMODE 0xF2480040 -#define F367_OFDM_KDIV_MODE 0xF2480030 -#define F367_OFDM_NSLOWSN_LOCKED 0xF2480008 -#define F367_OFDM_DELOCK_PRFLOSS 0xF2480004 -#define F367_OFDM_DIS_RSFLOCK 0xF2480002 -#define F367_OFDM_VITSCALE_0 0xF2480001 - -/* FFEC1PRG */ -#define R367_OFDM_FFEC1PRG 0xF249 -#define F367_OFDM_FDSS_DVB 0xF2490080 -#define F367_OFDM_FDSS_SRCH 0xF2490040 -#define F367_OFDM_FFECPROG_5 0xF2490020 -#define F367_OFDM_FFECPROG_4 0xF2490010 -#define F367_OFDM_FFECPROG_3 0xF2490008 -#define F367_OFDM_FFECPROG_2 0xF2490004 -#define F367_OFDM_FTS1_DISABLE 0xF2490002 -#define F367_OFDM_FTS2_DISABLE 0xF2490001 - -/* FVITCURPUN */ -#define R367_OFDM_FVITCURPUN 0xF24A -#define F367_OFDM_FVIT_MAPPING 0xF24A00E0 -#define F367_OFDM_FVIT_CURPUN 0xF24A001F - -/* FVERROR */ -#define R367_OFDM_FVERROR 0xF24B -#define F367_OFDM_FREGERR_VIT 0xF24B00FF - -/* FVSTATUSVIT */ -#define R367_OFDM_FVSTATUSVIT 0xF24C -#define F367_OFDM_FVITERBI_ON 0xF24C0080 -#define F367_OFDM_F1END_LOOPVIT 0xF24C0040 -#define F367_OFDM_FVITERBI_DEPRF 0xF24C0020 -#define F367_OFDM_FPRFVIT 0xF24C0010 -#define F367_OFDM_FLOCKEDVIT 0xF24C0008 -#define F367_OFDM_FVITERBI_DELOCK 0xF24C0004 -#define F367_OFDM_FVIT_DEMODSEL 0xF24C0002 -#define F367_OFDM_FVITERBI_COMPOUT 0xF24C0001 - -/* DEBUG_LT1 */ -#define R367_OFDM_DEBUG_LT1 0xF24D -#define F367_OFDM_DBG_LT1 0xF24D00FF - -/* DEBUG_LT2 */ -#define R367_OFDM_DEBUG_LT2 0xF24E -#define F367_OFDM_DBG_LT2 0xF24E00FF - -/* DEBUG_LT3 */ -#define R367_OFDM_DEBUG_LT3 0xF24F -#define F367_OFDM_DBG_LT3 0xF24F00FF - - /* TSTSFMET */ -#define R367_OFDM_TSTSFMET 0xF250 -#define F367_OFDM_TSTSFEC_METRIQUES 0xF25000FF - - /* SELOUT */ -#define R367_OFDM_SELOUT 0xF252 -#define F367_OFDM_EN_SYNC 0xF2520080 -#define F367_OFDM_EN_TBUSDEMAP 0xF2520040 -#define F367_OFDM_SELOUT_5 0xF2520020 -#define F367_OFDM_SELOUT_4 0xF2520010 -#define F367_OFDM_TSTSYNCHRO_MODE 0xF2520002 - - /* TSYNC */ -#define R367_OFDM_TSYNC 0xF253 -#define F367_OFDM_CURPUN_INCMODE 0xF2530080 -#define F367_OFDM_CERR_TSTMODE 0xF2530040 -#define F367_OFDM_SHIFTSOF_MODE 0xF2530030 -#define F367_OFDM_SLOWPHA_MODE 0xF2530008 -#define F367_OFDM_PXX_BYPALL 0xF2530004 -#define F367_OFDM_FROTA45_FIRST 0xF2530002 -#define F367_OFDM_TST_BCHERROR 0xF2530001 - - /* TSTERR */ -#define R367_OFDM_TSTERR 0xF254 -#define F367_OFDM_TST_LONGPKT 0xF2540080 -#define F367_OFDM_TST_ISSYION 0xF2540040 -#define F367_OFDM_TST_NPDON 0xF2540020 -#define F367_OFDM_TSTERR_4 0xF2540010 -#define F367_OFDM_TRACEBACK_MODE 0xF2540008 -#define F367_OFDM_TST_RSPARITY 0xF2540004 -#define F367_OFDM_METRIQUE_MODE 0xF2540003 - - /* TSFSYNC */ -#define R367_OFDM_TSFSYNC 0xF255 -#define F367_OFDM_EN_SFECSYNC 0xF2550080 -#define F367_OFDM_EN_SFECDEMAP 0xF2550040 -#define F367_OFDM_SFCERR_TSTMODE 0xF2550020 -#define F367_OFDM_SFECPXX_BYPALL 0xF2550010 -#define F367_OFDM_SFECTSTSYNCHRO_MODE 0xF255000F - - /* TSTSFERR */ -#define R367_OFDM_TSTSFERR 0xF256 -#define F367_OFDM_TSTSTERR_7 0xF2560080 -#define F367_OFDM_TSTSTERR_6 0xF2560040 -#define F367_OFDM_TSTSTERR_5 0xF2560020 -#define F367_OFDM_TSTSTERR_4 0xF2560010 -#define F367_OFDM_SFECTRACEBACK_MODE 0xF2560008 -#define F367_OFDM_SFEC_NCONVPROG 0xF2560004 -#define F367_OFDM_SFECMETRIQUE_MODE 0xF2560003 - - /* TSTTSSF1 */ -#define R367_OFDM_TSTTSSF1 0xF258 -#define F367_OFDM_TSTERSSF 0xF2580080 -#define F367_OFDM_TSTTSSFEN 0xF2580040 -#define F367_OFDM_SFEC_OUTMODE 0xF2580030 -#define F367_OFDM_XLSF_NOFTHRESHOLD 0xF2580008 -#define F367_OFDM_TSTTSSF_STACKSEL 0xF2580007 - - /* TSTTSSF2 */ -#define R367_OFDM_TSTTSSF2 0xF259 -#define F367_OFDM_DILSF_DBBHEADER 0xF2590080 -#define F367_OFDM_TSTTSSF_DISBUG 0xF2590040 -#define F367_OFDM_TSTTSSF_NOBADSTART 0xF2590020 -#define F367_OFDM_TSTTSSF_SELECT 0xF259001F - - /* TSTTSSF3 */ -#define R367_OFDM_TSTTSSF3 0xF25A -#define F367_OFDM_TSTTSSF3_7 0xF25A0080 -#define F367_OFDM_TSTTSSF3_6 0xF25A0040 -#define F367_OFDM_TSTTSSF3_5 0xF25A0020 -#define F367_OFDM_TSTTSSF3_4 0xF25A0010 -#define F367_OFDM_TSTTSSF3_3 0xF25A0008 -#define F367_OFDM_TSTTSSF3_2 0xF25A0004 -#define F367_OFDM_TSTTSSF3_1 0xF25A0002 -#define F367_OFDM_DISSF_CLKENABLE 0xF25A0001 - - /* TSTTS1 */ -#define R367_OFDM_TSTTS1 0xF25C -#define F367_OFDM_TSTERS 0xF25C0080 -#define F367_OFDM_TSFIFO_DSSSYNCB 0xF25C0040 -#define F367_OFDM_TSTTS_FSPYBEFRS 0xF25C0020 -#define F367_OFDM_NFORCE_SYNCBYTE 0xF25C0010 -#define F367_OFDM_XL_NOFTHRESHOLD 0xF25C0008 -#define F367_OFDM_TSTTS_FRFORCEPKT 0xF25C0004 -#define F367_OFDM_DESCR_NOTAUTO 0xF25C0002 -#define F367_OFDM_TSTTSEN 0xF25C0001 - - /* TSTTS2 */ -#define R367_OFDM_TSTTS2 0xF25D -#define F367_OFDM_DIL_DBBHEADER 0xF25D0080 -#define F367_OFDM_TSTTS_NOBADXXX 0xF25D0040 -#define F367_OFDM_TSFIFO_DELSPEEDUP 0xF25D0020 -#define F367_OFDM_TSTTS_SELECT 0xF25D001F - - /* TSTTS3 */ -#define R367_OFDM_TSTTS3 0xF25E -#define F367_OFDM_TSTTS_NOPKTGAIN 0xF25E0080 -#define F367_OFDM_TSTTS_NOPKTENE 0xF25E0040 -#define F367_OFDM_TSTTS_ISOLATION 0xF25E0020 -#define F367_OFDM_TSTTS_DISBUG 0xF25E0010 -#define F367_OFDM_TSTTS_NOBADSTART 0xF25E0008 -#define F367_OFDM_TSTTS_STACKSEL 0xF25E0007 - - /* TSTTS4 */ -#define R367_OFDM_TSTTS4 0xF25F -#define F367_OFDM_TSTTS4_7 0xF25F0080 -#define F367_OFDM_TSTTS4_6 0xF25F0040 -#define F367_OFDM_TSTTS4_5 0xF25F0020 -#define F367_OFDM_TSTTS_DISDSTATE 0xF25F0010 -#define F367_OFDM_TSTTS_FASTNOSYNC 0xF25F0008 -#define F367_OFDM_EXT_FECSPYIN 0xF25F0004 -#define F367_OFDM_TSTTS_NODPZERO 0xF25F0002 -#define F367_OFDM_TSTTS_NODIV3 0xF25F0001 - - /* TSTTSRC */ -#define R367_OFDM_TSTTSRC 0xF26C -#define F367_OFDM_TSTTSRC_7 0xF26C0080 -#define F367_OFDM_TSRCFIFO_DSSSYNCB 0xF26C0040 -#define F367_OFDM_TSRCFIFO_DPUNACTIVE 0xF26C0020 -#define F367_OFDM_TSRCFIFO_DELSPEEDUP 0xF26C0010 -#define F367_OFDM_TSTTSRC_NODIV3 0xF26C0008 -#define F367_OFDM_TSTTSRC_FRFORCEPKT 0xF26C0004 -#define F367_OFDM_SAT25_SDDORIGINE 0xF26C0002 -#define F367_OFDM_TSTTSRC_INACTIVE 0xF26C0001 - - /* TSTTSRS */ -#define R367_OFDM_TSTTSRS 0xF26D -#define F367_OFDM_TSTTSRS_7 0xF26D0080 -#define F367_OFDM_TSTTSRS_6 0xF26D0040 -#define F367_OFDM_TSTTSRS_5 0xF26D0020 -#define F367_OFDM_TSTTSRS_4 0xF26D0010 -#define F367_OFDM_TSTTSRS_3 0xF26D0008 -#define F367_OFDM_TSTTSRS_2 0xF26D0004 -#define F367_OFDM_TSTRS_DISRS2 0xF26D0002 -#define F367_OFDM_TSTRS_DISRS1 0xF26D0001 - -/* TSSTATEM */ -#define R367_OFDM_TSSTATEM 0xF270 -#define F367_OFDM_TSDIL_ON 0xF2700080 -#define F367_OFDM_TSSKIPRS_ON 0xF2700040 -#define F367_OFDM_TSRS_ON 0xF2700020 -#define F367_OFDM_TSDESCRAMB_ON 0xF2700010 -#define F367_OFDM_TSFRAME_MODE 0xF2700008 -#define F367_OFDM_TS_DISABLE 0xF2700004 -#define F367_OFDM_TSACM_MODE 0xF2700002 -#define F367_OFDM_TSOUT_NOSYNC 0xF2700001 - -/* TSSTATEL */ -#define R367_OFDM_TSSTATEL 0xF271 -#define F367_OFDM_TSNOSYNCBYTE 0xF2710080 -#define F367_OFDM_TSPARITY_ON 0xF2710040 -#define F367_OFDM_TSSYNCOUTRS_ON 0xF2710020 -#define F367_OFDM_TSDVBS2_MODE 0xF2710010 -#define F367_OFDM_TSISSYI_ON 0xF2710008 -#define F367_OFDM_TSNPD_ON 0xF2710004 -#define F367_OFDM_TSCRC8_ON 0xF2710002 -#define F367_OFDM_TSDSS_PACKET 0xF2710001 - -/* TSCFGH */ -#define R367_OFDM_TSCFGH 0xF272 -#define F367_OFDM_TSFIFO_DVBCI 0xF2720080 -#define F367_OFDM_TSFIFO_SERIAL 0xF2720040 -#define F367_OFDM_TSFIFO_TEIUPDATE 0xF2720020 -#define F367_OFDM_TSFIFO_DUTY50 0xF2720010 -#define F367_OFDM_TSFIFO_HSGNLOUT 0xF2720008 -#define F367_OFDM_TSFIFO_ERRMODE 0xF2720006 -#define F367_OFDM_RST_HWARE 0xF2720001 - -/* TSCFGM */ -#define R367_OFDM_TSCFGM 0xF273 -#define F367_OFDM_TSFIFO_MANSPEED 0xF27300C0 -#define F367_OFDM_TSFIFO_PERMDATA 0xF2730020 -#define F367_OFDM_TSFIFO_NONEWSGNL 0xF2730010 -#define F367_OFDM_TSFIFO_BITSPEED 0xF2730008 -#define F367_OFDM_NPD_SPECDVBS2 0xF2730004 -#define F367_OFDM_TSFIFO_STOPCKDIS 0xF2730002 -#define F367_OFDM_TSFIFO_INVDATA 0xF2730001 - -/* TSCFGL */ -#define R367_OFDM_TSCFGL 0xF274 -#define F367_OFDM_TSFIFO_BCLKDEL1CK 0xF27400C0 -#define F367_OFDM_BCHERROR_MODE 0xF2740030 -#define F367_OFDM_TSFIFO_NSGNL2DATA 0xF2740008 -#define F367_OFDM_TSFIFO_EMBINDVB 0xF2740004 -#define F367_OFDM_TSFIFO_DPUNACT 0xF2740002 -#define F367_OFDM_TSFIFO_NPDOFF 0xF2740001 - -/* TSSYNC */ -#define R367_OFDM_TSSYNC 0xF275 -#define F367_OFDM_TSFIFO_PERMUTE 0xF2750080 -#define F367_OFDM_TSFIFO_FISCR3B 0xF2750060 -#define F367_OFDM_TSFIFO_SYNCMODE 0xF2750018 -#define F367_OFDM_TSFIFO_SYNCSEL 0xF2750007 - -/* TSINSDELH */ -#define R367_OFDM_TSINSDELH 0xF276 -#define F367_OFDM_TSDEL_SYNCBYTE 0xF2760080 -#define F367_OFDM_TSDEL_XXHEADER 0xF2760040 -#define F367_OFDM_TSDEL_BBHEADER 0xF2760020 -#define F367_OFDM_TSDEL_DATAFIELD 0xF2760010 -#define F367_OFDM_TSINSDEL_ISCR 0xF2760008 -#define F367_OFDM_TSINSDEL_NPD 0xF2760004 -#define F367_OFDM_TSINSDEL_RSPARITY 0xF2760002 -#define F367_OFDM_TSINSDEL_CRC8 0xF2760001 - -/* TSINSDELM */ -#define R367_OFDM_TSINSDELM 0xF277 -#define F367_OFDM_TSINS_BBPADDING 0xF2770080 -#define F367_OFDM_TSINS_BCHFEC 0xF2770040 -#define F367_OFDM_TSINS_LDPCFEC 0xF2770020 -#define F367_OFDM_TSINS_EMODCOD 0xF2770010 -#define F367_OFDM_TSINS_TOKEN 0xF2770008 -#define F367_OFDM_TSINS_XXXERR 0xF2770004 -#define F367_OFDM_TSINS_MATYPE 0xF2770002 -#define F367_OFDM_TSINS_UPL 0xF2770001 - -/* TSINSDELL */ -#define R367_OFDM_TSINSDELL 0xF278 -#define F367_OFDM_TSINS_DFL 0xF2780080 -#define F367_OFDM_TSINS_SYNCD 0xF2780040 -#define F367_OFDM_TSINS_BLOCLEN 0xF2780020 -#define F367_OFDM_TSINS_SIGPCOUNT 0xF2780010 -#define F367_OFDM_TSINS_FIFO 0xF2780008 -#define F367_OFDM_TSINS_REALPACK 0xF2780004 -#define F367_OFDM_TSINS_TSCONFIG 0xF2780002 -#define F367_OFDM_TSINS_LATENCY 0xF2780001 - -/* TSDIVN */ -#define R367_OFDM_TSDIVN 0xF279 -#define F367_OFDM_TSFIFO_LOWSPEED 0xF2790080 -#define F367_OFDM_BYTE_OVERSAMPLING 0xF2790070 -#define F367_OFDM_TSMANUAL_PACKETNBR 0xF279000F - -/* TSDIVPM */ -#define R367_OFDM_TSDIVPM 0xF27A -#define F367_OFDM_TSMANUAL_P_HI 0xF27A00FF - -/* TSDIVPL */ -#define R367_OFDM_TSDIVPL 0xF27B -#define F367_OFDM_TSMANUAL_P_LO 0xF27B00FF - -/* TSDIVQM */ -#define R367_OFDM_TSDIVQM 0xF27C -#define F367_OFDM_TSMANUAL_Q_HI 0xF27C00FF - -/* TSDIVQL */ -#define R367_OFDM_TSDIVQL 0xF27D -#define F367_OFDM_TSMANUAL_Q_LO 0xF27D00FF - -/* TSDILSTKM */ -#define R367_OFDM_TSDILSTKM 0xF27E -#define F367_OFDM_TSFIFO_DILSTK_HI 0xF27E00FF - -/* TSDILSTKL */ -#define R367_OFDM_TSDILSTKL 0xF27F -#define F367_OFDM_TSFIFO_DILSTK_LO 0xF27F00FF - -/* TSSPEED */ -#define R367_OFDM_TSSPEED 0xF280 -#define F367_OFDM_TSFIFO_OUTSPEED 0xF28000FF - -/* TSSTATUS */ -#define R367_OFDM_TSSTATUS 0xF281 -#define F367_OFDM_TSFIFO_LINEOK 0xF2810080 -#define F367_OFDM_TSFIFO_ERROR 0xF2810040 -#define F367_OFDM_TSFIFO_DATA7 0xF2810020 -#define F367_OFDM_TSFIFO_NOSYNC 0xF2810010 -#define F367_OFDM_ISCR_INITIALIZED 0xF2810008 -#define F367_OFDM_ISCR_UPDATED 0xF2810004 -#define F367_OFDM_SOFFIFO_UNREGUL 0xF2810002 -#define F367_OFDM_DIL_READY 0xF2810001 - -/* TSSTATUS2 */ -#define R367_OFDM_TSSTATUS2 0xF282 -#define F367_OFDM_TSFIFO_DEMODSEL 0xF2820080 -#define F367_OFDM_TSFIFOSPEED_STORE 0xF2820040 -#define F367_OFDM_DILXX_RESET 0xF2820020 -#define F367_OFDM_TSSERIAL_IMPOSSIBLE 0xF2820010 -#define F367_OFDM_TSFIFO_UNDERSPEED 0xF2820008 -#define F367_OFDM_BITSPEED_EVENT 0xF2820004 -#define F367_OFDM_UL_SCRAMBDETECT 0xF2820002 -#define F367_OFDM_ULDTV67_FALSELOCK 0xF2820001 - -/* TSBITRATEM */ -#define R367_OFDM_TSBITRATEM 0xF283 -#define F367_OFDM_TSFIFO_BITRATE_HI 0xF28300FF - -/* TSBITRATEL */ -#define R367_OFDM_TSBITRATEL 0xF284 -#define F367_OFDM_TSFIFO_BITRATE_LO 0xF28400FF - -/* TSPACKLENM */ -#define R367_OFDM_TSPACKLENM 0xF285 -#define F367_OFDM_TSFIFO_PACKCPT 0xF28500E0 -#define F367_OFDM_DIL_RPLEN_HI 0xF285001F - -/* TSPACKLENL */ -#define R367_OFDM_TSPACKLENL 0xF286 -#define F367_OFDM_DIL_RPLEN_LO 0xF28600FF - -/* TSBLOCLENM */ -#define R367_OFDM_TSBLOCLENM 0xF287 -#define F367_OFDM_TSFIFO_PFLEN_HI 0xF28700FF - -/* TSBLOCLENL */ -#define R367_OFDM_TSBLOCLENL 0xF288 -#define F367_OFDM_TSFIFO_PFLEN_LO 0xF28800FF - -/* TSDLYH */ -#define R367_OFDM_TSDLYH 0xF289 -#define F367_OFDM_SOFFIFO_TSTIMEVALID 0xF2890080 -#define F367_OFDM_SOFFIFO_SPEEDUP 0xF2890040 -#define F367_OFDM_SOFFIFO_STOP 0xF2890020 -#define F367_OFDM_SOFFIFO_REGULATED 0xF2890010 -#define F367_OFDM_SOFFIFO_REALSBOFF_HI 0xF289000F - -/* TSDLYM */ -#define R367_OFDM_TSDLYM 0xF28A -#define F367_OFDM_SOFFIFO_REALSBOFF_MED 0xF28A00FF - -/* TSDLYL */ -#define R367_OFDM_TSDLYL 0xF28B -#define F367_OFDM_SOFFIFO_REALSBOFF_LO 0xF28B00FF - -/* TSNPDAV */ -#define R367_OFDM_TSNPDAV 0xF28C -#define F367_OFDM_TSNPD_AVERAGE 0xF28C00FF - -/* TSBUFSTATH */ -#define R367_OFDM_TSBUFSTATH 0xF28D -#define F367_OFDM_TSISCR_3BYTES 0xF28D0080 -#define F367_OFDM_TSISCR_NEWDATA 0xF28D0040 -#define F367_OFDM_TSISCR_BUFSTAT_HI 0xF28D003F - -/* TSBUFSTATM */ -#define R367_OFDM_TSBUFSTATM 0xF28E -#define F367_OFDM_TSISCR_BUFSTAT_MED 0xF28E00FF - -/* TSBUFSTATL */ -#define R367_OFDM_TSBUFSTATL 0xF28F -#define F367_OFDM_TSISCR_BUFSTAT_LO 0xF28F00FF - -/* TSDEBUGM */ -#define R367_OFDM_TSDEBUGM 0xF290 -#define F367_OFDM_TSFIFO_ILLPACKET 0xF2900080 -#define F367_OFDM_DIL_NOSYNC 0xF2900040 -#define F367_OFDM_DIL_ISCR 0xF2900020 -#define F367_OFDM_DILOUT_BSYNCB 0xF2900010 -#define F367_OFDM_TSFIFO_EMPTYPKT 0xF2900008 -#define F367_OFDM_TSFIFO_EMPTYRD 0xF2900004 -#define F367_OFDM_SOFFIFO_STOPM 0xF2900002 -#define F367_OFDM_SOFFIFO_SPEEDUPM 0xF2900001 - -/* TSDEBUGL */ -#define R367_OFDM_TSDEBUGL 0xF291 -#define F367_OFDM_TSFIFO_PACKLENFAIL 0xF2910080 -#define F367_OFDM_TSFIFO_SYNCBFAIL 0xF2910040 -#define F367_OFDM_TSFIFO_VITLIBRE 0xF2910020 -#define F367_OFDM_TSFIFO_BOOSTSPEEDM 0xF2910010 -#define F367_OFDM_TSFIFO_UNDERSPEEDM 0xF2910008 -#define F367_OFDM_TSFIFO_ERROR_EVNT 0xF2910004 -#define F367_OFDM_TSFIFO_FULL 0xF2910002 -#define F367_OFDM_TSFIFO_OVERFLOWM 0xF2910001 - -/* TSDLYSETH */ -#define R367_OFDM_TSDLYSETH 0xF292 -#define F367_OFDM_SOFFIFO_OFFSET 0xF29200E0 -#define F367_OFDM_SOFFIFO_SYMBOFFSET_HI 0xF292001F - -/* TSDLYSETM */ -#define R367_OFDM_TSDLYSETM 0xF293 -#define F367_OFDM_SOFFIFO_SYMBOFFSET_MED 0xF29300FF - -/* TSDLYSETL */ -#define R367_OFDM_TSDLYSETL 0xF294 -#define F367_OFDM_SOFFIFO_SYMBOFFSET_LO 0xF29400FF - -/* TSOBSCFG */ -#define R367_OFDM_TSOBSCFG 0xF295 -#define F367_OFDM_TSFIFO_OBSCFG 0xF29500FF - -/* TSOBSM */ -#define R367_OFDM_TSOBSM 0xF296 -#define F367_OFDM_TSFIFO_OBSDATA_HI 0xF29600FF - -/* TSOBSL */ -#define R367_OFDM_TSOBSL 0xF297 -#define F367_OFDM_TSFIFO_OBSDATA_LO 0xF29700FF - -/* ERRCTRL1 */ -#define R367_OFDM_ERRCTRL1 0xF298 -#define F367_OFDM_ERR_SRC1 0xF29800F0 -#define F367_OFDM_ERRCTRL1_3 0xF2980008 -#define F367_OFDM_NUM_EVT1 0xF2980007 - -/* ERRCNT1H */ -#define R367_OFDM_ERRCNT1H 0xF299 -#define F367_OFDM_ERRCNT1_OLDVALUE 0xF2990080 -#define F367_OFDM_ERR_CNT1 0xF299007F - -/* ERRCNT1M */ -#define R367_OFDM_ERRCNT1M 0xF29A -#define F367_OFDM_ERR_CNT1_HI 0xF29A00FF - -/* ERRCNT1L */ -#define R367_OFDM_ERRCNT1L 0xF29B -#define F367_OFDM_ERR_CNT1_LO 0xF29B00FF - -/* ERRCTRL2 */ -#define R367_OFDM_ERRCTRL2 0xF29C -#define F367_OFDM_ERR_SRC2 0xF29C00F0 -#define F367_OFDM_ERRCTRL2_3 0xF29C0008 -#define F367_OFDM_NUM_EVT2 0xF29C0007 - -/* ERRCNT2H */ -#define R367_OFDM_ERRCNT2H 0xF29D -#define F367_OFDM_ERRCNT2_OLDVALUE 0xF29D0080 -#define F367_OFDM_ERR_CNT2_HI 0xF29D007F - -/* ERRCNT2M */ -#define R367_OFDM_ERRCNT2M 0xF29E -#define F367_OFDM_ERR_CNT2_MED 0xF29E00FF - -/* ERRCNT2L */ -#define R367_OFDM_ERRCNT2L 0xF29F -#define F367_OFDM_ERR_CNT2_LO 0xF29F00FF - -/* FECSPY */ -#define R367_OFDM_FECSPY 0xF2A0 -#define F367_OFDM_SPY_ENABLE 0xF2A00080 -#define F367_OFDM_NO_SYNCBYTE 0xF2A00040 -#define F367_OFDM_SERIAL_MODE 0xF2A00020 -#define F367_OFDM_UNUSUAL_PACKET 0xF2A00010 -#define F367_OFDM_BERMETER_DATAMODE 0xF2A0000C -#define F367_OFDM_BERMETER_LMODE 0xF2A00002 -#define F367_OFDM_BERMETER_RESET 0xF2A00001 - -/* FSPYCFG */ -#define R367_OFDM_FSPYCFG 0xF2A1 -#define F367_OFDM_FECSPY_INPUT 0xF2A100C0 -#define F367_OFDM_RST_ON_ERROR 0xF2A10020 -#define F367_OFDM_ONE_SHOT 0xF2A10010 -#define F367_OFDM_I2C_MOD 0xF2A1000C -#define F367_OFDM_SPY_HYSTERESIS 0xF2A10003 - -/* FSPYDATA */ -#define R367_OFDM_FSPYDATA 0xF2A2 -#define F367_OFDM_SPY_STUFFING 0xF2A20080 -#define F367_OFDM_NOERROR_PKTJITTER 0xF2A20040 -#define F367_OFDM_SPY_CNULLPKT 0xF2A20020 -#define F367_OFDM_SPY_OUTDATA_MODE 0xF2A2001F - -/* FSPYOUT */ -#define R367_OFDM_FSPYOUT 0xF2A3 -#define F367_OFDM_FSPY_DIRECT 0xF2A30080 -#define F367_OFDM_FSPYOUT_6 0xF2A30040 -#define F367_OFDM_SPY_OUTDATA_BUS 0xF2A30038 -#define F367_OFDM_STUFF_MODE 0xF2A30007 - -/* FSTATUS */ -#define R367_OFDM_FSTATUS 0xF2A4 -#define F367_OFDM_SPY_ENDSIM 0xF2A40080 -#define F367_OFDM_VALID_SIM 0xF2A40040 -#define F367_OFDM_FOUND_SIGNAL 0xF2A40020 -#define F367_OFDM_DSS_SYNCBYTE 0xF2A40010 -#define F367_OFDM_RESULT_STATE 0xF2A4000F - -/* FGOODPACK */ -#define R367_OFDM_FGOODPACK 0xF2A5 -#define F367_OFDM_FGOOD_PACKET 0xF2A500FF - -/* FPACKCNT */ -#define R367_OFDM_FPACKCNT 0xF2A6 -#define F367_OFDM_FPACKET_COUNTER 0xF2A600FF - -/* FSPYMISC */ -#define R367_OFDM_FSPYMISC 0xF2A7 -#define F367_OFDM_FLABEL_COUNTER 0xF2A700FF - -/* FBERCPT4 */ -#define R367_OFDM_FBERCPT4 0xF2A8 -#define F367_OFDM_FBERMETER_CPT5 0xF2A800FF - -/* FBERCPT3 */ -#define R367_OFDM_FBERCPT3 0xF2A9 -#define F367_OFDM_FBERMETER_CPT4 0xF2A900FF - -/* FBERCPT2 */ -#define R367_OFDM_FBERCPT2 0xF2AA -#define F367_OFDM_FBERMETER_CPT3 0xF2AA00FF - -/* FBERCPT1 */ -#define R367_OFDM_FBERCPT1 0xF2AB -#define F367_OFDM_FBERMETER_CPT2 0xF2AB00FF - -/* FBERCPT0 */ -#define R367_OFDM_FBERCPT0 0xF2AC -#define F367_OFDM_FBERMETER_CPT1 0xF2AC00FF - -/* FBERERR2 */ -#define R367_OFDM_FBERERR2 0xF2AD -#define F367_OFDM_FBERMETER_ERR_HI 0xF2AD00FF - -/* FBERERR1 */ -#define R367_OFDM_FBERERR1 0xF2AE -#define F367_OFDM_FBERMETER_ERR_MED 0xF2AE00FF - -/* FBERERR0 */ -#define R367_OFDM_FBERERR0 0xF2AF -#define F367_OFDM_FBERMETER_ERR_LO 0xF2AF00FF - -/* FSTATESM */ -#define R367_OFDM_FSTATESM 0xF2B0 -#define F367_OFDM_RSTATE_F 0xF2B00080 -#define F367_OFDM_RSTATE_E 0xF2B00040 -#define F367_OFDM_RSTATE_D 0xF2B00020 -#define F367_OFDM_RSTATE_C 0xF2B00010 -#define F367_OFDM_RSTATE_B 0xF2B00008 -#define F367_OFDM_RSTATE_A 0xF2B00004 -#define F367_OFDM_RSTATE_9 0xF2B00002 -#define F367_OFDM_RSTATE_8 0xF2B00001 - -/* FSTATESL */ -#define R367_OFDM_FSTATESL 0xF2B1 -#define F367_OFDM_RSTATE_7 0xF2B10080 -#define F367_OFDM_RSTATE_6 0xF2B10040 -#define F367_OFDM_RSTATE_5 0xF2B10020 -#define F367_OFDM_RSTATE_4 0xF2B10010 -#define F367_OFDM_RSTATE_3 0xF2B10008 -#define F367_OFDM_RSTATE_2 0xF2B10004 -#define F367_OFDM_RSTATE_1 0xF2B10002 -#define F367_OFDM_RSTATE_0 0xF2B10001 - -/* FSPYBER */ -#define R367_OFDM_FSPYBER 0xF2B2 -#define F367_OFDM_FSPYBER_7 0xF2B20080 -#define F367_OFDM_FSPYOBS_XORREAD 0xF2B20040 -#define F367_OFDM_FSPYBER_OBSMODE 0xF2B20020 -#define F367_OFDM_FSPYBER_SYNCBYTE 0xF2B20010 -#define F367_OFDM_FSPYBER_UNSYNC 0xF2B20008 -#define F367_OFDM_FSPYBER_CTIME 0xF2B20007 - -/* FSPYDISTM */ -#define R367_OFDM_FSPYDISTM 0xF2B3 -#define F367_OFDM_PKTTIME_DISTANCE_HI 0xF2B300FF - -/* FSPYDISTL */ -#define R367_OFDM_FSPYDISTL 0xF2B4 -#define F367_OFDM_PKTTIME_DISTANCE_LO 0xF2B400FF - -/* FSPYOBS7 */ -#define R367_OFDM_FSPYOBS7 0xF2B8 -#define F367_OFDM_FSPYOBS_SPYFAIL 0xF2B80080 -#define F367_OFDM_FSPYOBS_SPYFAIL1 0xF2B80040 -#define F367_OFDM_FSPYOBS_ERROR 0xF2B80020 -#define F367_OFDM_FSPYOBS_STROUT 0xF2B80010 -#define F367_OFDM_FSPYOBS_RESULTSTATE1 0xF2B8000F - -/* FSPYOBS6 */ -#define R367_OFDM_FSPYOBS6 0xF2B9 -#define F367_OFDM_FSPYOBS_RESULTSTATE0 0xF2B900F0 -#define F367_OFDM_FSPYOBS_RESULTSTATEM1 0xF2B9000F - -/* FSPYOBS5 */ -#define R367_OFDM_FSPYOBS5 0xF2BA -#define F367_OFDM_FSPYOBS_BYTEOFPACKET1 0xF2BA00FF - -/* FSPYOBS4 */ -#define R367_OFDM_FSPYOBS4 0xF2BB -#define F367_OFDM_FSPYOBS_BYTEVALUE1 0xF2BB00FF - -/* FSPYOBS3 */ -#define R367_OFDM_FSPYOBS3 0xF2BC -#define F367_OFDM_FSPYOBS_DATA1 0xF2BC00FF - -/* FSPYOBS2 */ -#define R367_OFDM_FSPYOBS2 0xF2BD -#define F367_OFDM_FSPYOBS_DATA0 0xF2BD00FF - -/* FSPYOBS1 */ -#define R367_OFDM_FSPYOBS1 0xF2BE -#define F367_OFDM_FSPYOBS_DATAM1 0xF2BE00FF - -/* FSPYOBS0 */ -#define R367_OFDM_FSPYOBS0 0xF2BF -#define F367_OFDM_FSPYOBS_DATAM2 0xF2BF00FF - -/* SFDEMAP */ -#define R367_OFDM_SFDEMAP 0xF2C0 -#define F367_OFDM_SFDEMAP_7 0xF2C00080 -#define F367_OFDM_SFEC_K_DIVIDER_VIT 0xF2C0007F - -/* SFERROR */ -#define R367_OFDM_SFERROR 0xF2C1 -#define F367_OFDM_SFEC_REGERR_VIT 0xF2C100FF - -/* SFAVSR */ -#define R367_OFDM_SFAVSR 0xF2C2 -#define F367_OFDM_SFEC_SUMERRORS 0xF2C20080 -#define F367_OFDM_SERROR_MAXMODE 0xF2C20040 -#define F367_OFDM_SN_SFEC 0xF2C20030 -#define F367_OFDM_KDIV_MODE_SFEC 0xF2C2000C -#define F367_OFDM_SFAVSR_1 0xF2C20002 -#define F367_OFDM_SFAVSR_0 0xF2C20001 - -/* SFECSTATUS */ -#define R367_OFDM_SFECSTATUS 0xF2C3 -#define F367_OFDM_SFEC_ON 0xF2C30080 -#define F367_OFDM_SFSTATUS_6 0xF2C30040 -#define F367_OFDM_SFSTATUS_5 0xF2C30020 -#define F367_OFDM_SFSTATUS_4 0xF2C30010 -#define F367_OFDM_LOCKEDSFEC 0xF2C30008 -#define F367_OFDM_SFEC_DELOCK 0xF2C30004 -#define F367_OFDM_SFEC_DEMODSEL1 0xF2C30002 -#define F367_OFDM_SFEC_OVFON 0xF2C30001 - -/* SFKDIV12 */ -#define R367_OFDM_SFKDIV12 0xF2C4 -#define F367_OFDM_SFECKDIV12_MAN 0xF2C40080 -#define F367_OFDM_SFEC_K_DIVIDER_12 0xF2C4007F - -/* SFKDIV23 */ -#define R367_OFDM_SFKDIV23 0xF2C5 -#define F367_OFDM_SFECKDIV23_MAN 0xF2C50080 -#define F367_OFDM_SFEC_K_DIVIDER_23 0xF2C5007F - -/* SFKDIV34 */ -#define R367_OFDM_SFKDIV34 0xF2C6 -#define F367_OFDM_SFECKDIV34_MAN 0xF2C60080 -#define F367_OFDM_SFEC_K_DIVIDER_34 0xF2C6007F - -/* SFKDIV56 */ -#define R367_OFDM_SFKDIV56 0xF2C7 -#define F367_OFDM_SFECKDIV56_MAN 0xF2C70080 -#define F367_OFDM_SFEC_K_DIVIDER_56 0xF2C7007F - -/* SFKDIV67 */ -#define R367_OFDM_SFKDIV67 0xF2C8 -#define F367_OFDM_SFECKDIV67_MAN 0xF2C80080 -#define F367_OFDM_SFEC_K_DIVIDER_67 0xF2C8007F - -/* SFKDIV78 */ -#define R367_OFDM_SFKDIV78 0xF2C9 -#define F367_OFDM_SFECKDIV78_MAN 0xF2C90080 -#define F367_OFDM_SFEC_K_DIVIDER_78 0xF2C9007F - -/* SFDILSTKM */ -#define R367_OFDM_SFDILSTKM 0xF2CA -#define F367_OFDM_SFEC_PACKCPT 0xF2CA00E0 -#define F367_OFDM_SFEC_DILSTK_HI 0xF2CA001F - -/* SFDILSTKL */ -#define R367_OFDM_SFDILSTKL 0xF2CB -#define F367_OFDM_SFEC_DILSTK_LO 0xF2CB00FF - -/* SFSTATUS */ -#define R367_OFDM_SFSTATUS 0xF2CC -#define F367_OFDM_SFEC_LINEOK 0xF2CC0080 -#define F367_OFDM_SFEC_ERROR 0xF2CC0040 -#define F367_OFDM_SFEC_DATA7 0xF2CC0020 -#define F367_OFDM_SFEC_OVERFLOW 0xF2CC0010 -#define F367_OFDM_SFEC_DEMODSEL2 0xF2CC0008 -#define F367_OFDM_SFEC_NOSYNC 0xF2CC0004 -#define F367_OFDM_SFEC_UNREGULA 0xF2CC0002 -#define F367_OFDM_SFEC_READY 0xF2CC0001 - -/* SFDLYH */ -#define R367_OFDM_SFDLYH 0xF2CD -#define F367_OFDM_SFEC_TSTIMEVALID 0xF2CD0080 -#define F367_OFDM_SFEC_SPEEDUP 0xF2CD0040 -#define F367_OFDM_SFEC_STOP 0xF2CD0020 -#define F367_OFDM_SFEC_REGULATED 0xF2CD0010 -#define F367_OFDM_SFEC_REALSYMBOFFSET 0xF2CD000F - -/* SFDLYM */ -#define R367_OFDM_SFDLYM 0xF2CE -#define F367_OFDM_SFEC_REALSYMBOFFSET_HI 0xF2CE00FF - -/* SFDLYL */ -#define R367_OFDM_SFDLYL 0xF2CF -#define F367_OFDM_SFEC_REALSYMBOFFSET_LO 0xF2CF00FF - -/* SFDLYSETH */ -#define R367_OFDM_SFDLYSETH 0xF2D0 -#define F367_OFDM_SFEC_OFFSET 0xF2D000E0 -#define F367_OFDM_SFECDLYSETH_4 0xF2D00010 -#define F367_OFDM_RST_SFEC 0xF2D00008 -#define F367_OFDM_SFECDLYSETH_2 0xF2D00004 -#define F367_OFDM_SFEC_DISABLE 0xF2D00002 -#define F367_OFDM_SFEC_UNREGUL 0xF2D00001 - -/* SFDLYSETM */ -#define R367_OFDM_SFDLYSETM 0xF2D1 -#define F367_OFDM_SFECDLYSETM_7 0xF2D10080 -#define F367_OFDM_SFEC_SYMBOFFSET_HI 0xF2D1007F - -/* SFDLYSETL */ -#define R367_OFDM_SFDLYSETL 0xF2D2 -#define F367_OFDM_SFEC_SYMBOFFSET_LO 0xF2D200FF - -/* SFOBSCFG */ -#define R367_OFDM_SFOBSCFG 0xF2D3 -#define F367_OFDM_SFEC_OBSCFG 0xF2D300FF - -/* SFOBSM */ -#define R367_OFDM_SFOBSM 0xF2D4 -#define F367_OFDM_SFEC_OBSDATA_HI 0xF2D400FF - -/* SFOBSL */ -#define R367_OFDM_SFOBSL 0xF2D5 -#define F367_OFDM_SFEC_OBSDATA_LO 0xF2D500FF - -/* SFECINFO */ -#define R367_OFDM_SFECINFO 0xF2D6 -#define F367_OFDM_SFECINFO_7 0xF2D60080 -#define F367_OFDM_SFEC_SYNCDLSB 0xF2D60070 -#define F367_OFDM_SFCE_S1CPHASE 0xF2D6000F - -/* SFERRCTRL */ -#define R367_OFDM_SFERRCTRL 0xF2D8 -#define F367_OFDM_SFEC_ERR_SOURCE 0xF2D800F0 -#define F367_OFDM_SFERRCTRL_3 0xF2D80008 -#define F367_OFDM_SFEC_NUM_EVENT 0xF2D80007 - -/* SFERRCNTH */ -#define R367_OFDM_SFERRCNTH 0xF2D9 -#define F367_OFDM_SFERRC_OLDVALUE 0xF2D90080 -#define F367_OFDM_SFEC_ERR_CNT 0xF2D9007F - -/* SFERRCNTM */ -#define R367_OFDM_SFERRCNTM 0xF2DA -#define F367_OFDM_SFEC_ERR_CNT_HI 0xF2DA00FF - -/* SFERRCNTL */ -#define R367_OFDM_SFERRCNTL 0xF2DB -#define F367_OFDM_SFEC_ERR_CNT_LO 0xF2DB00FF - -/* SYMBRATEM */ -#define R367_OFDM_SYMBRATEM 0xF2E0 -#define F367_OFDM_DEFGEN_SYMBRATE_HI 0xF2E000FF - -/* SYMBRATEL */ -#define R367_OFDM_SYMBRATEL 0xF2E1 -#define F367_OFDM_DEFGEN_SYMBRATE_LO 0xF2E100FF - -/* SYMBSTATUS */ -#define R367_OFDM_SYMBSTATUS 0xF2E2 -#define F367_OFDM_SYMBDLINE2_OFF 0xF2E20080 -#define F367_OFDM_SDDL_REINIT1 0xF2E20040 -#define F367_OFDM_SDD_REINIT1 0xF2E20020 -#define F367_OFDM_TOKENID_ERROR 0xF2E20010 -#define F367_OFDM_SYMBRATE_OVERFLOW 0xF2E20008 -#define F367_OFDM_SYMBRATE_UNDERFLOW 0xF2E20004 -#define F367_OFDM_TOKENID_RSTEVENT 0xF2E20002 -#define F367_OFDM_TOKENID_RESET1 0xF2E20001 - -/* SYMBCFG */ -#define R367_OFDM_SYMBCFG 0xF2E3 -#define F367_OFDM_SYMBCFG_7 0xF2E30080 -#define F367_OFDM_SYMBCFG_6 0xF2E30040 -#define F367_OFDM_SYMBCFG_5 0xF2E30020 -#define F367_OFDM_SYMBCFG_4 0xF2E30010 -#define F367_OFDM_SYMRATE_FSPEED 0xF2E3000C -#define F367_OFDM_SYMRATE_SSPEED 0xF2E30003 - -/* SYMBFIFOM */ -#define R367_OFDM_SYMBFIFOM 0xF2E4 -#define F367_OFDM_SYMBFIFOM_7 0xF2E40080 -#define F367_OFDM_SYMBFIFOM_6 0xF2E40040 -#define F367_OFDM_DEFGEN_SYMFIFO_HI 0xF2E4003F - -/* SYMBFIFOL */ -#define R367_OFDM_SYMBFIFOL 0xF2E5 -#define F367_OFDM_DEFGEN_SYMFIFO_LO 0xF2E500FF - -/* SYMBOFFSM */ -#define R367_OFDM_SYMBOFFSM 0xF2E6 -#define F367_OFDM_TOKENID_RESET2 0xF2E60080 -#define F367_OFDM_SDDL_REINIT2 0xF2E60040 -#define F367_OFDM_SDD_REINIT2 0xF2E60020 -#define F367_OFDM_SYMBOFFSM_4 0xF2E60010 -#define F367_OFDM_SYMBOFFSM_3 0xF2E60008 -#define F367_OFDM_DEFGEN_SYMBOFFSET_HI 0xF2E60007 - -/* SYMBOFFSL */ -#define R367_OFDM_SYMBOFFSL 0xF2E7 -#define F367_OFDM_DEFGEN_SYMBOFFSET_LO 0xF2E700FF - -/* DEBUG_LT4 */ -#define R367_DEBUG_LT4 0xF400 -#define F367_F_DEBUG_LT4 0xF40000FF - -/* DEBUG_LT5 */ -#define R367_DEBUG_LT5 0xF401 -#define F367_F_DEBUG_LT5 0xF40100FF - -/* DEBUG_LT6 */ -#define R367_DEBUG_LT6 0xF402 -#define F367_F_DEBUG_LT6 0xF40200FF - -/* DEBUG_LT7 */ -#define R367_DEBUG_LT7 0xF403 -#define F367_F_DEBUG_LT7 0xF40300FF - -/* DEBUG_LT8 */ -#define R367_DEBUG_LT8 0xF404 -#define F367_F_DEBUG_LT8 0xF40400FF - -/* DEBUG_LT9 */ -#define R367_DEBUG_LT9 0xF405 -#define F367_F_DEBUG_LT9 0xF40500FF - -/* CTRL_1 */ -#define R367_QAM_CTRL_1 0xF402 -#define F367_QAM_SOFT_RST 0xF4020080 -#define F367_QAM_EQU_RST 0xF4020008 -#define F367_QAM_CRL_RST 0xF4020004 -#define F367_QAM_TRL_RST 0xF4020002 -#define F367_QAM_AGC_RST 0xF4020001 - -/* CTRL_2 */ -#define R367_QAM_CTRL_2 0xF403 -#define F367_QAM_DEINT_RST 0xF4030008 -#define F367_QAM_RS_RST 0xF4030004 - -/* IT_STATUS1 */ -#define R367_QAM_IT_STATUS1 0xF408 -#define F367_QAM_SWEEP_OUT 0xF4080080 -#define F367_QAM_FSM_CRL 0xF4080040 -#define F367_QAM_CRL_LOCK 0xF4080020 -#define F367_QAM_MFSM 0xF4080010 -#define F367_QAM_TRL_LOCK 0xF4080008 -#define F367_QAM_TRL_AGC_LIMIT 0xF4080004 -#define F367_QAM_ADJ_AGC_LOCK 0xF4080002 -#define F367_QAM_AGC_QAM_LOCK 0xF4080001 - -/* IT_STATUS2 */ -#define R367_QAM_IT_STATUS2 0xF409 -#define F367_QAM_TSMF_CNT 0xF4090080 -#define F367_QAM_TSMF_EOF 0xF4090040 -#define F367_QAM_TSMF_RDY 0xF4090020 -#define F367_QAM_FEC_NOCORR 0xF4090010 -#define F367_QAM_SYNCSTATE 0xF4090008 -#define F367_QAM_DEINT_LOCK 0xF4090004 -#define F367_QAM_FADDING_FRZ 0xF4090002 -#define F367_QAM_TAPMON_ALARM 0xF4090001 - -/* IT_EN1 */ -#define R367_QAM_IT_EN1 0xF40A -#define F367_QAM_SWEEP_OUTE 0xF40A0080 -#define F367_QAM_FSM_CRLE 0xF40A0040 -#define F367_QAM_CRL_LOCKE 0xF40A0020 -#define F367_QAM_MFSME 0xF40A0010 -#define F367_QAM_TRL_LOCKE 0xF40A0008 -#define F367_QAM_TRL_AGC_LIMITE 0xF40A0004 -#define F367_QAM_ADJ_AGC_LOCKE 0xF40A0002 -#define F367_QAM_AGC_LOCKE 0xF40A0001 - -/* IT_EN2 */ -#define R367_QAM_IT_EN2 0xF40B -#define F367_QAM_TSMF_CNTE 0xF40B0080 -#define F367_QAM_TSMF_EOFE 0xF40B0040 -#define F367_QAM_TSMF_RDYE 0xF40B0020 -#define F367_QAM_FEC_NOCORRE 0xF40B0010 -#define F367_QAM_SYNCSTATEE 0xF40B0008 -#define F367_QAM_DEINT_LOCKE 0xF40B0004 -#define F367_QAM_FADDING_FRZE 0xF40B0002 -#define F367_QAM_TAPMON_ALARME 0xF40B0001 - -/* CTRL_STATUS */ -#define R367_QAM_CTRL_STATUS 0xF40C -#define F367_QAM_QAMFEC_LOCK 0xF40C0004 -#define F367_QAM_TSMF_LOCK 0xF40C0002 -#define F367_QAM_TSMF_ERROR 0xF40C0001 - -/* TEST_CTL */ -#define R367_QAM_TEST_CTL 0xF40F -#define F367_QAM_TST_BLK_SEL 0xF40F0060 -#define F367_QAM_TST_BUS_SEL 0xF40F001F - -/* AGC_CTL */ -#define R367_QAM_AGC_CTL 0xF410 -#define F367_QAM_AGC_LCK_TH 0xF41000F0 -#define F367_QAM_AGC_ACCUMRSTSEL 0xF4100007 - -/* AGC_IF_CFG */ -#define R367_QAM_AGC_IF_CFG 0xF411 -#define F367_QAM_AGC_IF_BWSEL 0xF41100F0 -#define F367_QAM_AGC_IF_FREEZE 0xF4110002 - -/* AGC_RF_CFG */ -#define R367_QAM_AGC_RF_CFG 0xF412 -#define F367_QAM_AGC_RF_BWSEL 0xF4120070 -#define F367_QAM_AGC_RF_FREEZE 0xF4120002 - -/* AGC_PWM_CFG */ -#define R367_QAM_AGC_PWM_CFG 0xF413 -#define F367_QAM_AGC_RF_PWM_TST 0xF4130080 -#define F367_QAM_AGC_RF_PWM_INV 0xF4130040 -#define F367_QAM_AGC_IF_PWM_TST 0xF4130008 -#define F367_QAM_AGC_IF_PWM_INV 0xF4130004 -#define F367_QAM_AGC_PWM_CLKDIV 0xF4130003 - -/* AGC_PWR_REF_L */ -#define R367_QAM_AGC_PWR_REF_L 0xF414 -#define F367_QAM_AGC_PWRREF_LO 0xF41400FF - -/* AGC_PWR_REF_H */ -#define R367_QAM_AGC_PWR_REF_H 0xF415 -#define F367_QAM_AGC_PWRREF_HI 0xF4150003 - -/* AGC_RF_TH_L */ -#define R367_QAM_AGC_RF_TH_L 0xF416 -#define F367_QAM_AGC_RF_TH_LO 0xF41600FF - -/* AGC_RF_TH_H */ -#define R367_QAM_AGC_RF_TH_H 0xF417 -#define F367_QAM_AGC_RF_TH_HI 0xF417000F - -/* AGC_IF_LTH_L */ -#define R367_QAM_AGC_IF_LTH_L 0xF418 -#define F367_QAM_AGC_IF_THLO_LO 0xF41800FF - -/* AGC_IF_LTH_H */ -#define R367_QAM_AGC_IF_LTH_H 0xF419 -#define F367_QAM_AGC_IF_THLO_HI 0xF419000F - -/* AGC_IF_HTH_L */ -#define R367_QAM_AGC_IF_HTH_L 0xF41A -#define F367_QAM_AGC_IF_THHI_LO 0xF41A00FF - -/* AGC_IF_HTH_H */ -#define R367_QAM_AGC_IF_HTH_H 0xF41B -#define F367_QAM_AGC_IF_THHI_HI 0xF41B000F - -/* AGC_PWR_RD_L */ -#define R367_QAM_AGC_PWR_RD_L 0xF41C -#define F367_QAM_AGC_PWR_WORD_LO 0xF41C00FF - -/* AGC_PWR_RD_M */ -#define R367_QAM_AGC_PWR_RD_M 0xF41D -#define F367_QAM_AGC_PWR_WORD_ME 0xF41D00FF - -/* AGC_PWR_RD_H */ -#define R367_QAM_AGC_PWR_RD_H 0xF41E -#define F367_QAM_AGC_PWR_WORD_HI 0xF41E0003 - -/* AGC_PWM_IFCMD_L */ -#define R367_QAM_AGC_PWM_IFCMD_L 0xF420 -#define F367_QAM_AGC_IF_PWMCMD_LO 0xF42000FF - -/* AGC_PWM_IFCMD_H */ -#define R367_QAM_AGC_PWM_IFCMD_H 0xF421 -#define F367_QAM_AGC_IF_PWMCMD_HI 0xF421000F - -/* AGC_PWM_RFCMD_L */ -#define R367_QAM_AGC_PWM_RFCMD_L 0xF422 -#define F367_QAM_AGC_RF_PWMCMD_LO 0xF42200FF - -/* AGC_PWM_RFCMD_H */ -#define R367_QAM_AGC_PWM_RFCMD_H 0xF423 -#define F367_QAM_AGC_RF_PWMCMD_HI 0xF423000F - -/* IQDEM_CFG */ -#define R367_QAM_IQDEM_CFG 0xF424 -#define F367_QAM_IQDEM_CLK_SEL 0xF4240004 -#define F367_QAM_IQDEM_INVIQ 0xF4240002 -#define F367_QAM_IQDEM_A2DTYPE 0xF4240001 - -/* MIX_NCO_LL */ -#define R367_QAM_MIX_NCO_LL 0xF425 -#define F367_QAM_MIX_NCO_INC_LL 0xF42500FF - -/* MIX_NCO_HL */ -#define R367_QAM_MIX_NCO_HL 0xF426 -#define F367_QAM_MIX_NCO_INC_HL 0xF42600FF - -/* MIX_NCO_HH */ -#define R367_QAM_MIX_NCO_HH 0xF427 -#define F367_QAM_MIX_NCO_INVCNST 0xF4270080 -#define F367_QAM_MIX_NCO_INC_HH 0xF427007F - -/* SRC_NCO_LL */ -#define R367_QAM_SRC_NCO_LL 0xF428 -#define F367_QAM_SRC_NCO_INC_LL 0xF42800FF - -/* SRC_NCO_LH */ -#define R367_QAM_SRC_NCO_LH 0xF429 -#define F367_QAM_SRC_NCO_INC_LH 0xF42900FF - -/* SRC_NCO_HL */ -#define R367_QAM_SRC_NCO_HL 0xF42A -#define F367_QAM_SRC_NCO_INC_HL 0xF42A00FF - -/* SRC_NCO_HH */ -#define R367_QAM_SRC_NCO_HH 0xF42B -#define F367_QAM_SRC_NCO_INC_HH 0xF42B007F - -/* IQDEM_GAIN_SRC_L */ -#define R367_QAM_IQDEM_GAIN_SRC_L 0xF42C -#define F367_QAM_GAIN_SRC_LO 0xF42C00FF - -/* IQDEM_GAIN_SRC_H */ -#define R367_QAM_IQDEM_GAIN_SRC_H 0xF42D -#define F367_QAM_GAIN_SRC_HI 0xF42D0003 - -/* IQDEM_DCRM_CFG_LL */ -#define R367_QAM_IQDEM_DCRM_CFG_LL 0xF430 -#define F367_QAM_DCRM0_DCIN_L 0xF43000FF - -/* IQDEM_DCRM_CFG_LH */ -#define R367_QAM_IQDEM_DCRM_CFG_LH 0xF431 -#define F367_QAM_DCRM1_I_DCIN_L 0xF43100FC -#define F367_QAM_DCRM0_DCIN_H 0xF4310003 - -/* IQDEM_DCRM_CFG_HL */ -#define R367_QAM_IQDEM_DCRM_CFG_HL 0xF432 -#define F367_QAM_DCRM1_Q_DCIN_L 0xF43200F0 -#define F367_QAM_DCRM1_I_DCIN_H 0xF432000F - -/* IQDEM_DCRM_CFG_HH */ -#define R367_QAM_IQDEM_DCRM_CFG_HH 0xF433 -#define F367_QAM_DCRM1_FRZ 0xF4330080 -#define F367_QAM_DCRM0_FRZ 0xF4330040 -#define F367_QAM_DCRM1_Q_DCIN_H 0xF433003F - -/* IQDEM_ADJ_COEFF0 */ -#define R367_QAM_IQDEM_ADJ_COEFF0 0xF434 -#define F367_QAM_ADJIIR_COEFF10_L 0xF43400FF - -/* IQDEM_ADJ_COEFF1 */ -#define R367_QAM_IQDEM_ADJ_COEFF1 0xF435 -#define F367_QAM_ADJIIR_COEFF11_L 0xF43500FC -#define F367_QAM_ADJIIR_COEFF10_H 0xF4350003 - -/* IQDEM_ADJ_COEFF2 */ -#define R367_QAM_IQDEM_ADJ_COEFF2 0xF436 -#define F367_QAM_ADJIIR_COEFF12_L 0xF43600F0 -#define F367_QAM_ADJIIR_COEFF11_H 0xF436000F - -/* IQDEM_ADJ_COEFF3 */ -#define R367_QAM_IQDEM_ADJ_COEFF3 0xF437 -#define F367_QAM_ADJIIR_COEFF20_L 0xF43700C0 -#define F367_QAM_ADJIIR_COEFF12_H 0xF437003F - -/* IQDEM_ADJ_COEFF4 */ -#define R367_QAM_IQDEM_ADJ_COEFF4 0xF438 -#define F367_QAM_ADJIIR_COEFF20_H 0xF43800FF - -/* IQDEM_ADJ_COEFF5 */ -#define R367_QAM_IQDEM_ADJ_COEFF5 0xF439 -#define F367_QAM_ADJIIR_COEFF21_L 0xF43900FF - -/* IQDEM_ADJ_COEFF6 */ -#define R367_QAM_IQDEM_ADJ_COEFF6 0xF43A -#define F367_QAM_ADJIIR_COEFF22_L 0xF43A00FC -#define F367_QAM_ADJIIR_COEFF21_H 0xF43A0003 - -/* IQDEM_ADJ_COEFF7 */ -#define R367_QAM_IQDEM_ADJ_COEFF7 0xF43B -#define F367_QAM_ADJIIR_COEFF22_H 0xF43B000F - -/* IQDEM_ADJ_EN */ -#define R367_QAM_IQDEM_ADJ_EN 0xF43C -#define F367_QAM_ALLPASSFILT_EN 0xF43C0008 -#define F367_QAM_ADJ_AGC_EN 0xF43C0004 -#define F367_QAM_ADJ_COEFF_FRZ 0xF43C0002 -#define F367_QAM_ADJ_EN 0xF43C0001 - -/* IQDEM_ADJ_AGC_REF */ -#define R367_QAM_IQDEM_ADJ_AGC_REF 0xF43D -#define F367_QAM_ADJ_AGC_REF 0xF43D00FF - -/* ALLPASSFILT1 */ -#define R367_QAM_ALLPASSFILT1 0xF440 -#define F367_QAM_ALLPASSFILT_COEFF1_LO 0xF44000FF - -/* ALLPASSFILT2 */ -#define R367_QAM_ALLPASSFILT2 0xF441 -#define F367_QAM_ALLPASSFILT_COEFF1_ME 0xF44100FF - -/* ALLPASSFILT3 */ -#define R367_QAM_ALLPASSFILT3 0xF442 -#define F367_QAM_ALLPASSFILT_COEFF2_LO 0xF44200C0 -#define F367_QAM_ALLPASSFILT_COEFF1_HI 0xF442003F - -/* ALLPASSFILT4 */ -#define R367_QAM_ALLPASSFILT4 0xF443 -#define F367_QAM_ALLPASSFILT_COEFF2_MEL 0xF44300FF - -/* ALLPASSFILT5 */ -#define R367_QAM_ALLPASSFILT5 0xF444 -#define F367_QAM_ALLPASSFILT_COEFF2_MEH 0xF44400FF - -/* ALLPASSFILT6 */ -#define R367_QAM_ALLPASSFILT6 0xF445 -#define F367_QAM_ALLPASSFILT_COEFF3_LO 0xF44500F0 -#define F367_QAM_ALLPASSFILT_COEFF2_HI 0xF445000F - -/* ALLPASSFILT7 */ -#define R367_QAM_ALLPASSFILT7 0xF446 -#define F367_QAM_ALLPASSFILT_COEFF3_MEL 0xF44600FF - -/* ALLPASSFILT8 */ -#define R367_QAM_ALLPASSFILT8 0xF447 -#define F367_QAM_ALLPASSFILT_COEFF3_MEH 0xF44700FF - -/* ALLPASSFILT9 */ -#define R367_QAM_ALLPASSFILT9 0xF448 -#define F367_QAM_ALLPASSFILT_COEFF4_LO 0xF44800FC -#define F367_QAM_ALLPASSFILT_COEFF3_HI 0xF4480003 - -/* ALLPASSFILT10 */ -#define R367_QAM_ALLPASSFILT10 0xF449 -#define F367_QAM_ALLPASSFILT_COEFF4_ME 0xF44900FF - -/* ALLPASSFILT11 */ -#define R367_QAM_ALLPASSFILT11 0xF44A -#define F367_QAM_ALLPASSFILT_COEFF4_HI 0xF44A00FF - -/* TRL_AGC_CFG */ -#define R367_QAM_TRL_AGC_CFG 0xF450 -#define F367_QAM_TRL_AGC_FREEZE 0xF4500080 -#define F367_QAM_TRL_AGC_REF 0xF450007F - -/* TRL_LPF_CFG */ -#define R367_QAM_TRL_LPF_CFG 0xF454 -#define F367_QAM_NYQPOINT_INV 0xF4540040 -#define F367_QAM_TRL_SHIFT 0xF4540030 -#define F367_QAM_NYQ_COEFF_SEL 0xF454000C -#define F367_QAM_TRL_LPF_FREEZE 0xF4540002 -#define F367_QAM_TRL_LPF_CRT 0xF4540001 - -/* TRL_LPF_ACQ_GAIN */ -#define R367_QAM_TRL_LPF_ACQ_GAIN 0xF455 -#define F367_QAM_TRL_GDIR_ACQ 0xF4550070 -#define F367_QAM_TRL_GINT_ACQ 0xF4550007 - -/* TRL_LPF_TRK_GAIN */ -#define R367_QAM_TRL_LPF_TRK_GAIN 0xF456 -#define F367_QAM_TRL_GDIR_TRK 0xF4560070 -#define F367_QAM_TRL_GINT_TRK 0xF4560007 - -/* TRL_LPF_OUT_GAIN */ -#define R367_QAM_TRL_LPF_OUT_GAIN 0xF457 -#define F367_QAM_TRL_GAIN_OUT 0xF4570007 - -/* TRL_LOCKDET_LTH */ -#define R367_QAM_TRL_LOCKDET_LTH 0xF458 -#define F367_QAM_TRL_LCK_THLO 0xF4580007 - -/* TRL_LOCKDET_HTH */ -#define R367_QAM_TRL_LOCKDET_HTH 0xF459 -#define F367_QAM_TRL_LCK_THHI 0xF45900FF - -/* TRL_LOCKDET_TRGVAL */ -#define R367_QAM_TRL_LOCKDET_TRGVAL 0xF45A -#define F367_QAM_TRL_LCK_TRG 0xF45A00FF - -/* IQ_QAM */ -#define R367_QAM_IQ_QAM 0xF45C -#define F367_QAM_IQ_INPUT 0xF45C0008 -#define F367_QAM_DETECT_MODE 0xF45C0007 - -/* FSM_STATE */ -#define R367_QAM_FSM_STATE 0xF460 -#define F367_QAM_CRL_DFE 0xF4600080 -#define F367_QAM_DFE_START 0xF4600040 -#define F367_QAM_CTRLG_START 0xF4600030 -#define F367_QAM_FSM_FORCESTATE 0xF460000F - -/* FSM_CTL */ -#define R367_QAM_FSM_CTL 0xF461 -#define F367_QAM_FEC2_EN 0xF4610040 -#define F367_QAM_SIT_EN 0xF4610020 -#define F367_QAM_TRL_AHEAD 0xF4610010 -#define F367_QAM_TRL2_EN 0xF4610008 -#define F367_QAM_FSM_EQA1_EN 0xF4610004 -#define F367_QAM_FSM_BKP_DIS 0xF4610002 -#define F367_QAM_FSM_FORCE_EN 0xF4610001 - -/* FSM_STS */ -#define R367_QAM_FSM_STS 0xF462 -#define F367_QAM_FSM_STATUS 0xF462000F - -/* FSM_SNR0_HTH */ -#define R367_QAM_FSM_SNR0_HTH 0xF463 -#define F367_QAM_SNR0_HTH 0xF46300FF - -/* FSM_SNR1_HTH */ -#define R367_QAM_FSM_SNR1_HTH 0xF464 -#define F367_QAM_SNR1_HTH 0xF46400FF - -/* FSM_SNR2_HTH */ -#define R367_QAM_FSM_SNR2_HTH 0xF465 -#define F367_QAM_SNR2_HTH 0xF46500FF - -/* FSM_SNR0_LTH */ -#define R367_QAM_FSM_SNR0_LTH 0xF466 -#define F367_QAM_SNR0_LTH 0xF46600FF - -/* FSM_SNR1_LTH */ -#define R367_QAM_FSM_SNR1_LTH 0xF467 -#define F367_QAM_SNR1_LTH 0xF46700FF - -/* FSM_EQA1_HTH */ -#define R367_QAM_FSM_EQA1_HTH 0xF468 -#define F367_QAM_SNR3_HTH_LO 0xF46800F0 -#define F367_QAM_EQA1_HTH 0xF468000F - -/* FSM_TEMPO */ -#define R367_QAM_FSM_TEMPO 0xF469 -#define F367_QAM_SIT 0xF46900C0 -#define F367_QAM_WST 0xF4690038 -#define F367_QAM_ELT 0xF4690006 -#define F367_QAM_SNR3_HTH_HI 0xF4690001 - -/* FSM_CONFIG */ -#define R367_QAM_FSM_CONFIG 0xF46A -#define F367_QAM_FEC2_DFEOFF 0xF46A0004 -#define F367_QAM_PRIT_STATE 0xF46A0002 -#define F367_QAM_MODMAP_STATE 0xF46A0001 - -/* EQU_I_TESTTAP_L */ -#define R367_QAM_EQU_I_TESTTAP_L 0xF474 -#define F367_QAM_I_TEST_TAP_L 0xF47400FF - -/* EQU_I_TESTTAP_M */ -#define R367_QAM_EQU_I_TESTTAP_M 0xF475 -#define F367_QAM_I_TEST_TAP_M 0xF47500FF - -/* EQU_I_TESTTAP_H */ -#define R367_QAM_EQU_I_TESTTAP_H 0xF476 -#define F367_QAM_I_TEST_TAP_H 0xF476001F - -/* EQU_TESTAP_CFG */ -#define R367_QAM_EQU_TESTAP_CFG 0xF477 -#define F367_QAM_TEST_FFE_DFE_SEL 0xF4770040 -#define F367_QAM_TEST_TAP_SELECT 0xF477003F - -/* EQU_Q_TESTTAP_L */ -#define R367_QAM_EQU_Q_TESTTAP_L 0xF478 -#define F367_QAM_Q_TEST_TAP_L 0xF47800FF - -/* EQU_Q_TESTTAP_M */ -#define R367_QAM_EQU_Q_TESTTAP_M 0xF479 -#define F367_QAM_Q_TEST_TAP_M 0xF47900FF - -/* EQU_Q_TESTTAP_H */ -#define R367_QAM_EQU_Q_TESTTAP_H 0xF47A -#define F367_QAM_Q_TEST_TAP_H 0xF47A001F - -/* EQU_TAP_CTRL */ -#define R367_QAM_EQU_TAP_CTRL 0xF47B -#define F367_QAM_MTAP_FRZ 0xF47B0010 -#define F367_QAM_PRE_FREEZE 0xF47B0008 -#define F367_QAM_DFE_TAPMON_EN 0xF47B0004 -#define F367_QAM_FFE_TAPMON_EN 0xF47B0002 -#define F367_QAM_MTAP_ONLY 0xF47B0001 - -/* EQU_CTR_CRL_CONTROL_L */ -#define R367_QAM_EQU_CTR_CRL_CONTROL_L 0xF47C -#define F367_QAM_EQU_CTR_CRL_CONTROL_LO 0xF47C00FF - -/* EQU_CTR_CRL_CONTROL_H */ -#define R367_QAM_EQU_CTR_CRL_CONTROL_H 0xF47D -#define F367_QAM_EQU_CTR_CRL_CONTROL_HI 0xF47D00FF - -/* EQU_CTR_HIPOW_L */ -#define R367_QAM_EQU_CTR_HIPOW_L 0xF47E -#define F367_QAM_CTR_HIPOW_L 0xF47E00FF - -/* EQU_CTR_HIPOW_H */ -#define R367_QAM_EQU_CTR_HIPOW_H 0xF47F -#define F367_QAM_CTR_HIPOW_H 0xF47F00FF - -/* EQU_I_EQU_LO */ -#define R367_QAM_EQU_I_EQU_LO 0xF480 -#define F367_QAM_EQU_I_EQU_L 0xF48000FF - -/* EQU_I_EQU_HI */ -#define R367_QAM_EQU_I_EQU_HI 0xF481 -#define F367_QAM_EQU_I_EQU_H 0xF4810003 - -/* EQU_Q_EQU_LO */ -#define R367_QAM_EQU_Q_EQU_LO 0xF482 -#define F367_QAM_EQU_Q_EQU_L 0xF48200FF - -/* EQU_Q_EQU_HI */ -#define R367_QAM_EQU_Q_EQU_HI 0xF483 -#define F367_QAM_EQU_Q_EQU_H 0xF4830003 - -/* EQU_MAPPER */ -#define R367_QAM_EQU_MAPPER 0xF484 -#define F367_QAM_QUAD_AUTO 0xF4840080 -#define F367_QAM_QUAD_INV 0xF4840040 -#define F367_QAM_QAM_MODE 0xF4840007 - -/* EQU_SWEEP_RATE */ -#define R367_QAM_EQU_SWEEP_RATE 0xF485 -#define F367_QAM_SNR_PER 0xF48500C0 -#define F367_QAM_SWEEP_RATE 0xF485003F - -/* EQU_SNR_LO */ -#define R367_QAM_EQU_SNR_LO 0xF486 -#define F367_QAM_SNR_LO 0xF48600FF - -/* EQU_SNR_HI */ -#define R367_QAM_EQU_SNR_HI 0xF487 -#define F367_QAM_SNR_HI 0xF48700FF - -/* EQU_GAMMA_LO */ -#define R367_QAM_EQU_GAMMA_LO 0xF488 -#define F367_QAM_GAMMA_LO 0xF48800FF - -/* EQU_GAMMA_HI */ -#define R367_QAM_EQU_GAMMA_HI 0xF489 -#define F367_QAM_GAMMA_ME 0xF48900FF - -/* EQU_ERR_GAIN */ -#define R367_QAM_EQU_ERR_GAIN 0xF48A -#define F367_QAM_EQA1MU 0xF48A0070 -#define F367_QAM_CRL2MU 0xF48A000E -#define F367_QAM_GAMMA_HI 0xF48A0001 - -/* EQU_RADIUS */ -#define R367_QAM_EQU_RADIUS 0xF48B -#define F367_QAM_RADIUS 0xF48B00FF - -/* EQU_FFE_MAINTAP */ -#define R367_QAM_EQU_FFE_MAINTAP 0xF48C -#define F367_QAM_FFE_MAINTAP_INIT 0xF48C00FF - -/* EQU_FFE_LEAKAGE */ -#define R367_QAM_EQU_FFE_LEAKAGE 0xF48E -#define F367_QAM_LEAK_PER 0xF48E00F0 -#define F367_QAM_EQU_OUTSEL 0xF48E0002 -#define F367_QAM_PNT2DFE 0xF48E0001 - -/* EQU_FFE_MAINTAP_POS */ -#define R367_QAM_EQU_FFE_MAINTAP_POS 0xF48F -#define F367_QAM_FFE_LEAK_EN 0xF48F0080 -#define F367_QAM_DFE_LEAK_EN 0xF48F0040 -#define F367_QAM_FFE_MAINTAP_POS 0xF48F003F - -/* EQU_GAIN_WIDE */ -#define R367_QAM_EQU_GAIN_WIDE 0xF490 -#define F367_QAM_DFE_GAIN_WIDE 0xF49000F0 -#define F367_QAM_FFE_GAIN_WIDE 0xF490000F - -/* EQU_GAIN_NARROW */ -#define R367_QAM_EQU_GAIN_NARROW 0xF491 -#define F367_QAM_DFE_GAIN_NARROW 0xF49100F0 -#define F367_QAM_FFE_GAIN_NARROW 0xF491000F - -/* EQU_CTR_LPF_GAIN */ -#define R367_QAM_EQU_CTR_LPF_GAIN 0xF492 -#define F367_QAM_CTR_GTO 0xF4920080 -#define F367_QAM_CTR_GDIR 0xF4920070 -#define F367_QAM_SWEEP_EN 0xF4920008 -#define F367_QAM_CTR_GINT 0xF4920007 - -/* EQU_CRL_LPF_GAIN */ -#define R367_QAM_EQU_CRL_LPF_GAIN 0xF493 -#define F367_QAM_CRL_GTO 0xF4930080 -#define F367_QAM_CRL_GDIR 0xF4930070 -#define F367_QAM_SWEEP_DIR 0xF4930008 -#define F367_QAM_CRL_GINT 0xF4930007 - -/* EQU_GLOBAL_GAIN */ -#define R367_QAM_EQU_GLOBAL_GAIN 0xF494 -#define F367_QAM_CRL_GAIN 0xF49400F8 -#define F367_QAM_CTR_INC_GAIN 0xF4940004 -#define F367_QAM_CTR_FRAC 0xF4940003 - -/* EQU_CRL_LD_SEN */ -#define R367_QAM_EQU_CRL_LD_SEN 0xF495 -#define F367_QAM_CTR_BADPOINT_EN 0xF4950080 -#define F367_QAM_CTR_GAIN 0xF4950070 -#define F367_QAM_LIMANEN 0xF4950008 -#define F367_QAM_CRL_LD_SEN 0xF4950007 - -/* EQU_CRL_LD_VAL */ -#define R367_QAM_EQU_CRL_LD_VAL 0xF496 -#define F367_QAM_CRL_BISTH_LIMIT 0xF4960080 -#define F367_QAM_CARE_EN 0xF4960040 -#define F367_QAM_CRL_LD_PER 0xF4960030 -#define F367_QAM_CRL_LD_WST 0xF496000C -#define F367_QAM_CRL_LD_TFS 0xF4960003 - -/* EQU_CRL_TFR */ -#define R367_QAM_EQU_CRL_TFR 0xF497 -#define F367_QAM_CRL_LD_TFR 0xF49700FF - -/* EQU_CRL_BISTH_LO */ -#define R367_QAM_EQU_CRL_BISTH_LO 0xF498 -#define F367_QAM_CRL_BISTH_LO 0xF49800FF - -/* EQU_CRL_BISTH_HI */ -#define R367_QAM_EQU_CRL_BISTH_HI 0xF499 -#define F367_QAM_CRL_BISTH_HI 0xF49900FF - -/* EQU_SWEEP_RANGE_LO */ -#define R367_QAM_EQU_SWEEP_RANGE_LO 0xF49A -#define F367_QAM_SWEEP_RANGE_LO 0xF49A00FF - -/* EQU_SWEEP_RANGE_HI */ -#define R367_QAM_EQU_SWEEP_RANGE_HI 0xF49B -#define F367_QAM_SWEEP_RANGE_HI 0xF49B00FF - -/* EQU_CRL_LIMITER */ -#define R367_QAM_EQU_CRL_LIMITER 0xF49C -#define F367_QAM_BISECTOR_EN 0xF49C0080 -#define F367_QAM_PHEST128_EN 0xF49C0040 -#define F367_QAM_CRL_LIM 0xF49C003F - -/* EQU_MODULUS_MAP */ -#define R367_QAM_EQU_MODULUS_MAP 0xF49D -#define F367_QAM_PNT_DEPTH 0xF49D00E0 -#define F367_QAM_MODULUS_CMP 0xF49D001F - -/* EQU_PNT_GAIN */ -#define R367_QAM_EQU_PNT_GAIN 0xF49E -#define F367_QAM_PNT_EN 0xF49E0080 -#define F367_QAM_MODULUSMAP_EN 0xF49E0040 -#define F367_QAM_PNT_GAIN 0xF49E003F - -/* FEC_AC_CTR_0 */ -#define R367_QAM_FEC_AC_CTR_0 0xF4A8 -#define F367_QAM_BE_BYPASS 0xF4A80020 -#define F367_QAM_REFRESH47 0xF4A80010 -#define F367_QAM_CT_NBST 0xF4A80008 -#define F367_QAM_TEI_ENA 0xF4A80004 -#define F367_QAM_DS_ENA 0xF4A80002 -#define F367_QAM_TSMF_EN 0xF4A80001 - -/* FEC_AC_CTR_1 */ -#define R367_QAM_FEC_AC_CTR_1 0xF4A9 -#define F367_QAM_DEINT_DEPTH 0xF4A900FF - -/* FEC_AC_CTR_2 */ -#define R367_QAM_FEC_AC_CTR_2 0xF4AA -#define F367_QAM_DEINT_M 0xF4AA00F8 -#define F367_QAM_DIS_UNLOCK 0xF4AA0004 -#define F367_QAM_DESCR_MODE 0xF4AA0003 - -/* FEC_AC_CTR_3 */ -#define R367_QAM_FEC_AC_CTR_3 0xF4AB -#define F367_QAM_DI_UNLOCK 0xF4AB0080 -#define F367_QAM_DI_FREEZE 0xF4AB0040 -#define F367_QAM_MISMATCH 0xF4AB0030 -#define F367_QAM_ACQ_MODE 0xF4AB000C -#define F367_QAM_TRK_MODE 0xF4AB0003 - -/* FEC_STATUS */ -#define R367_QAM_FEC_STATUS 0xF4AC -#define F367_QAM_DEINT_SMCNTR 0xF4AC00E0 -#define F367_QAM_DEINT_SYNCSTATE 0xF4AC0018 -#define F367_QAM_DEINT_SYNLOST 0xF4AC0004 -#define F367_QAM_DESCR_SYNCSTATE 0xF4AC0002 - -/* RS_COUNTER_0 */ -#define R367_QAM_RS_COUNTER_0 0xF4AE -#define F367_QAM_BK_CT_L 0xF4AE00FF - -/* RS_COUNTER_1 */ -#define R367_QAM_RS_COUNTER_1 0xF4AF -#define F367_QAM_BK_CT_H 0xF4AF00FF - -/* RS_COUNTER_2 */ -#define R367_QAM_RS_COUNTER_2 0xF4B0 -#define F367_QAM_CORR_CT_L 0xF4B000FF - -/* RS_COUNTER_3 */ -#define R367_QAM_RS_COUNTER_3 0xF4B1 -#define F367_QAM_CORR_CT_H 0xF4B100FF - -/* RS_COUNTER_4 */ -#define R367_QAM_RS_COUNTER_4 0xF4B2 -#define F367_QAM_UNCORR_CT_L 0xF4B200FF - -/* RS_COUNTER_5 */ -#define R367_QAM_RS_COUNTER_5 0xF4B3 -#define F367_QAM_UNCORR_CT_H 0xF4B300FF - -/* BERT_0 */ -#define R367_QAM_BERT_0 0xF4B4 -#define F367_QAM_RS_NOCORR 0xF4B40004 -#define F367_QAM_CT_HOLD 0xF4B40002 -#define F367_QAM_CT_CLEAR 0xF4B40001 - -/* BERT_1 */ -#define R367_QAM_BERT_1 0xF4B5 -#define F367_QAM_BERT_ON 0xF4B50020 -#define F367_QAM_BERT_ERR_SRC 0xF4B50010 -#define F367_QAM_BERT_ERR_MODE 0xF4B50008 -#define F367_QAM_BERT_NBYTE 0xF4B50007 - -/* BERT_2 */ -#define R367_QAM_BERT_2 0xF4B6 -#define F367_QAM_BERT_ERRCOUNT_L 0xF4B600FF - -/* BERT_3 */ -#define R367_QAM_BERT_3 0xF4B7 -#define F367_QAM_BERT_ERRCOUNT_H 0xF4B700FF - -/* OUTFORMAT_0 */ -#define R367_QAM_OUTFORMAT_0 0xF4B8 -#define F367_QAM_CLK_POLARITY 0xF4B80080 -#define F367_QAM_FEC_TYPE 0xF4B80040 -#define F367_QAM_SYNC_STRIP 0xF4B80008 -#define F367_QAM_TS_SWAP 0xF4B80004 -#define F367_QAM_OUTFORMAT 0xF4B80003 - -/* OUTFORMAT_1 */ -#define R367_QAM_OUTFORMAT_1 0xF4B9 -#define F367_QAM_CI_DIVRANGE 0xF4B900FF - -/* SMOOTHER_2 */ -#define R367_QAM_SMOOTHER_2 0xF4BE -#define F367_QAM_FIFO_BYPASS 0xF4BE0020 - -/* TSMF_CTRL_0 */ -#define R367_QAM_TSMF_CTRL_0 0xF4C0 -#define F367_QAM_TS_NUMBER 0xF4C0001E -#define F367_QAM_SEL_MODE 0xF4C00001 - -/* TSMF_CTRL_1 */ -#define R367_QAM_TSMF_CTRL_1 0xF4C1 -#define F367_QAM_CHECK_ERROR_BIT 0xF4C10080 -#define F367_QAM_CHCK_F_SYNC 0xF4C10040 -#define F367_QAM_H_MODE 0xF4C10008 -#define F367_QAM_D_V_MODE 0xF4C10004 -#define F367_QAM_MODE 0xF4C10003 - -/* TSMF_CTRL_3 */ -#define R367_QAM_TSMF_CTRL_3 0xF4C3 -#define F367_QAM_SYNC_IN_COUNT 0xF4C300F0 -#define F367_QAM_SYNC_OUT_COUNT 0xF4C3000F - -/* TS_ON_ID_0 */ -#define R367_QAM_TS_ON_ID_0 0xF4C4 -#define F367_QAM_TS_ID_L 0xF4C400FF - -/* TS_ON_ID_1 */ -#define R367_QAM_TS_ON_ID_1 0xF4C5 -#define F367_QAM_TS_ID_H 0xF4C500FF - -/* TS_ON_ID_2 */ -#define R367_QAM_TS_ON_ID_2 0xF4C6 -#define F367_QAM_ON_ID_L 0xF4C600FF - -/* TS_ON_ID_3 */ -#define R367_QAM_TS_ON_ID_3 0xF4C7 -#define F367_QAM_ON_ID_H 0xF4C700FF - -/* RE_STATUS_0 */ -#define R367_QAM_RE_STATUS_0 0xF4C8 -#define F367_QAM_RECEIVE_STATUS_L 0xF4C800FF - -/* RE_STATUS_1 */ -#define R367_QAM_RE_STATUS_1 0xF4C9 -#define F367_QAM_RECEIVE_STATUS_LH 0xF4C900FF - -/* RE_STATUS_2 */ -#define R367_QAM_RE_STATUS_2 0xF4CA -#define F367_QAM_RECEIVE_STATUS_HL 0xF4CA00FF - -/* RE_STATUS_3 */ -#define R367_QAM_RE_STATUS_3 0xF4CB -#define F367_QAM_RECEIVE_STATUS_HH 0xF4CB003F - -/* TS_STATUS_0 */ -#define R367_QAM_TS_STATUS_0 0xF4CC -#define F367_QAM_TS_STATUS_L 0xF4CC00FF - -/* TS_STATUS_1 */ -#define R367_QAM_TS_STATUS_1 0xF4CD -#define F367_QAM_TS_STATUS_H 0xF4CD007F - -/* TS_STATUS_2 */ -#define R367_QAM_TS_STATUS_2 0xF4CE -#define F367_QAM_ERROR 0xF4CE0080 -#define F367_QAM_EMERGENCY 0xF4CE0040 -#define F367_QAM_CRE_TS 0xF4CE0030 -#define F367_QAM_VER 0xF4CE000E -#define F367_QAM_M_LOCK 0xF4CE0001 - -/* TS_STATUS_3 */ -#define R367_QAM_TS_STATUS_3 0xF4CF -#define F367_QAM_UPDATE_READY 0xF4CF0080 -#define F367_QAM_END_FRAME_HEADER 0xF4CF0040 -#define F367_QAM_CONTCNT 0xF4CF0020 -#define F367_QAM_TS_IDENTIFIER_SEL 0xF4CF000F - -/* T_O_ID_0 */ -#define R367_QAM_T_O_ID_0 0xF4D0 -#define F367_QAM_ON_ID_I_L 0xF4D000FF - -/* T_O_ID_1 */ -#define R367_QAM_T_O_ID_1 0xF4D1 -#define F367_QAM_ON_ID_I_H 0xF4D100FF - -/* T_O_ID_2 */ -#define R367_QAM_T_O_ID_2 0xF4D2 -#define F367_QAM_TS_ID_I_L 0xF4D200FF - -/* T_O_ID_3 */ -#define R367_QAM_T_O_ID_3 0xF4D3 -#define F367_QAM_TS_ID_I_H 0xF4D300FF - +// @DVB-C/DVB-T STMicroelectronics STV0367 register defintions +// Author Manfred Völkel, Februar 2011 +// (c) 2010 DigitalDevices GmbH Germany. All rights reserved + +// $Id: DD_STV0367Register.h 357 2011-04-27 02:39:13Z manfred $ + +/* ======================================================================= + -- Registers Declaration + -- ------------------------- + -- Each register (R367_XXXXX) is defined by its address (2 bytes). + -- + -- Each field (F367_XXXXX)is defined as follow: + -- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] + ======================================================================= */ + +/* ID */ +#define R367_ID 0xF000 +#define F367_IDENTIFICATIONREG 0xF00000FF + +/* I2CRPT */ +#define R367_I2CRPT 0xF001 +#define F367_I2CT_ON 0xF0010080 +#define F367_ENARPT_LEVEL 0xF0010070 +#define F367_SCLT_DELAY 0xF0010008 +#define F367_SCLT_NOD 0xF0010004 +#define F367_STOP_ENABLE 0xF0010002 +#define F367_SDAT_NOD 0xF0010001 + +/* TOPCTRL */ +#define R367_TOPCTRL 0xF002 +#define F367_STDBY 0xF0020080 +#define F367_STDBY_FEC 0xF0020040 +#define F367_STDBY_CORE 0xF0020020 +#define F367_QAM_COFDM 0xF0020010 +#define F367_TS_DIS 0xF0020008 +#define F367_DIR_CLK_216 0xF0020004 +#define F367_TUNER_BB 0xF0020002 +#define F367_DVBT_H 0xF0020001 + +/* IOCFG0 */ +#define R367_IOCFG0 0xF003 +#define F367_OP0_SD 0xF0030080 +#define F367_OP0_VAL 0xF0030040 +#define F367_OP0_OD 0xF0030020 +#define F367_OP0_INV 0xF0030010 +#define F367_OP0_DACVALUE_HI 0xF003000F + +/* DAC0R */ +#define R367_DAC0R 0xF004 +#define F367_OP0_DACVALUE_LO 0xF00400FF + +/* IOCFG1 */ +#define R367_IOCFG1 0xF005 +#define F367_IP0 0xF0050040 +#define F367_OP1_OD 0xF0050020 +#define F367_OP1_INV 0xF0050010 +#define F367_OP1_DACVALUE_HI 0xF005000F + +/* DAC1R */ +#define R367_DAC1R 0xF006 +#define F367_OP1_DACVALUE_LO 0xF00600FF + +/* IOCFG2 */ +#define R367_IOCFG2 0xF007 +#define F367_OP2_LOCK_CONF 0xF00700E0 +#define F367_OP2_OD 0xF0070010 +#define F367_OP2_VAL 0xF0070008 +#define F367_OP1_LOCK_CONF 0xF0070007 + +/* SDFR */ +#define R367_SDFR 0xF008 +#define F367_OP0_FREQ 0xF00800F0 +#define F367_OP1_FREQ 0xF008000F + +/* STATUS */ +#define R367_OFDM_STATUS 0xF009 +#define F367_TPS_LOCK 0xF0090080 +#define F367_SYR_LOCK 0xF0090040 +#define F367_AGC_LOCK 0xF0090020 +#define F367_PRF 0xF0090010 +#define F367_LK 0xF0090008 +#define F367_PR 0xF0090007 + +/* AUX_CLK */ +#define R367_AUX_CLK 0xF00A +#define F367_AUXFEC_CTL 0xF00A00C0 +#define F367_DIS_CKX4 0xF00A0020 +#define F367_CKSEL 0xF00A0018 +#define F367_CKDIV_PROG 0xF00A0006 +#define F367_AUXCLK_ENA 0xF00A0001 + +/* FREESYS1 */ +#define R367_FREESYS1 0xF00B +#define F367_FREE_SYS1 0xF00B00FF + +/* FREESYS2 */ +#define R367_FREESYS2 0xF00C +#define F367_FREE_SYS2 0xF00C00FF + +/* FREESYS3 */ +#define R367_FREESYS3 0xF00D +#define F367_FREE_SYS3 0xF00D00FF + +/* GPIO_CFG */ +#define R367_GPIO_CFG 0xF00E +#define F367_GPIO7_NOD 0xF00E0080 +#define F367_GPIO7_CFG 0xF00E0040 +#define F367_GPIO6_NOD 0xF00E0020 +#define F367_GPIO6_CFG 0xF00E0010 +#define F367_GPIO5_NOD 0xF00E0008 +#define F367_GPIO5_CFG 0xF00E0004 +#define F367_GPIO4_NOD 0xF00E0002 +#define F367_GPIO4_CFG 0xF00E0001 + +/* GPIO_CMD */ +#define R367_GPIO_CMD 0xF00F +#define F367_GPIO7_VAL 0xF00F0008 +#define F367_GPIO6_VAL 0xF00F0004 +#define F367_GPIO5_VAL 0xF00F0002 +#define F367_GPIO4_VAL 0xF00F0001 + +/* AGC2MAX */ +#define R367_OFDM_AGC2MAX 0xF010 +#define F367_OFDM_AGC2_MAX 0xF01000FF + +/* AGC2MIN */ +#define R367_OFDM_AGC2MIN 0xF011 +#define F367_OFDM_AGC2_MIN 0xF01100FF + +/* AGC1MAX */ +#define R367_OFDM_AGC1MAX 0xF012 +#define F367_OFDM_AGC1_MAX 0xF01200FF + +/* AGC1MIN */ +#define R367_OFDM_AGC1MIN 0xF013 +#define F367_OFDM_AGC1_MIN 0xF01300FF + +/* AGCR */ +#define R367_OFDM_AGCR 0xF014 +#define F367_OFDM_RATIO_A 0xF01400E0 +#define F367_OFDM_RATIO_B 0xF0140018 +#define F367_OFDM_RATIO_C 0xF0140007 + +/* AGC2TH */ +#define R367_OFDM_AGC2TH 0xF015 +#define F367_OFDM_AGC2_THRES 0xF01500FF + +/* AGC12C */ +#define R367_OFDM_AGC12C 0xF016 +#define F367_OFDM_AGC1_IV 0xF0160080 +#define F367_OFDM_AGC1_OD 0xF0160040 +#define F367_OFDM_AGC1_LOAD 0xF0160020 +#define F367_OFDM_AGC2_IV 0xF0160010 +#define F367_OFDM_AGC2_OD 0xF0160008 +#define F367_OFDM_AGC2_LOAD 0xF0160004 +#define F367_OFDM_AGC12_MODE 0xF0160003 + +/* AGCCTRL1 */ +#define R367_OFDM_AGCCTRL1 0xF017 +#define F367_OFDM_DAGC_ON 0xF0170080 +#define F367_OFDM_INVERT_AGC12 0xF0170040 +#define F367_OFDM_AGC1_MODE 0xF0170008 +#define F367_OFDM_AGC2_MODE 0xF0170007 + +/* AGCCTRL2 */ +#define R367_OFDM_AGCCTRL2 0xF018 +#define F367_OFDM_FRZ2_CTRL 0xF0180060 +#define F367_OFDM_FRZ1_CTRL 0xF0180018 +#define F367_OFDM_TIME_CST 0xF0180007 + +/* AGC1VAL1 */ +#define R367_OFDM_AGC1VAL1 0xF019 +#define F367_OFDM_AGC1_VAL_LO 0xF01900FF + +/* AGC1VAL2 */ +#define R367_OFDM_AGC1VAL2 0xF01A +#define F367_OFDM_AGC1_VAL_HI 0xF01A000F + +/* AGC2VAL1 */ +#define R367_OFDM_AGC2VAL1 0xF01B +#define F367_OFDM_AGC2_VAL_LO 0xF01B00FF + +/* AGC2VAL2 */ +#define R367_OFDM_AGC2VAL2 0xF01C +#define F367_OFDM_AGC2_VAL_HI 0xF01C000F + +/* AGC2PGA */ +#define R367_OFDM_AGC2PGA 0xF01D +#define F367_OFDM_AGC2_PGA 0xF01D00FF + +/* OVF_RATE1 */ +#define R367_OFDM_OVF_RATE1 0xF01E +#define F367_OFDM_OVF_RATE_HI 0xF01E000F + +/* OVF_RATE2 */ +#define R367_OFDM_OVF_RATE2 0xF01F +#define F367_OFDM_OVF_RATE_LO 0xF01F00FF + +/* GAIN_SRC1 */ +#define R367_OFDM_GAIN_SRC1 0xF020 +#define F367_OFDM_INV_SPECTR 0xF0200080 +#define F367_OFDM_IQ_INVERT 0xF0200040 +#define F367_OFDM_INR_BYPASS 0xF0200020 +#define F367_OFDM_STATUS_INV_SPECRUM 0xF0200010 +#define F367_OFDM_GAIN_SRC_HI 0xF020000F + +/* GAIN_SRC2 */ +#define R367_OFDM_GAIN_SRC2 0xF021 +#define F367_OFDM_GAIN_SRC_LO 0xF02100FF + +/* INC_DEROT1 */ +#define R367_OFDM_INC_DEROT1 0xF022 +#define F367_OFDM_INC_DEROT_HI 0xF02200FF + +/* INC_DEROT2 */ +#define R367_OFDM_INC_DEROT2 0xF023 +#define F367_OFDM_INC_DEROT_LO 0xF02300FF + +/* PPM_CPAMP_DIR */ +#define R367_OFDM_PPM_CPAMP_DIR 0xF024 +#define F367_OFDM_PPM_CPAMP_DIRECT 0xF02400FF + +/* PPM_CPAMP_INV */ +#define R367_OFDM_PPM_CPAMP_INV 0xF025 +#define F367_OFDM_PPM_CPAMP_INVER 0xF02500FF + +/* FREESTFE_1 */ +#define R367_OFDM_FREESTFE_1 0xF026 +#define F367_OFDM_SYMBOL_NUMBER_INC 0xF02600C0 +#define F367_OFDM_SEL_LSB 0xF0260004 +#define F367_OFDM_AVERAGE_ON 0xF0260002 +#define F367_OFDM_DC_ADJ 0xF0260001 + +/* FREESTFE_2 */ +#define R367_OFDM_FREESTFE_2 0xF027 +#define F367_OFDM_SEL_SRCOUT 0xF02700C0 +#define F367_OFDM_SEL_SYRTHR 0xF027001F + +/* DCOFFSET */ +#define R367_OFDM_DCOFFSET 0xF028 +#define F367_OFDM_SELECT_I_Q 0xF0280080 +#define F367_OFDM_DC_OFFSET 0xF028007F + +/* EN_PROCESS */ +#define R367_OFDM_EN_PROCESS 0xF029 +#define F367_OFDM_FREE 0xF02900F0 +#define F367_OFDM_ENAB_MANUAL 0xF0290001 + +/* SDI_SMOOTHER */ +#define R367_OFDM_SDI_SMOOTHER 0xF02A +#define F367_OFDM_DIS_SMOOTH 0xF02A0080 +#define F367_OFDM_SDI_INC_SMOOTHER 0xF02A007F + +/* FE_LOOP_OPEN */ +#define R367_OFDM_FE_LOOP_OPEN 0xF02B +#define F367_OFDM_TRL_LOOP_OP 0xF02B0002 +#define F367_OFDM_CRL_LOOP_OP 0xF02B0001 + +/* FREQOFF1 */ +#define R367_OFDM_FREQOFF1 0xF02C +#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_VHI 0xF02C00FF + +/* FREQOFF2 */ +#define R367_OFDM_FREQOFF2 0xF02D +#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_HI 0xF02D00FF + +/* FREQOFF3 */ +#define R367_OFDM_FREQOFF3 0xF02E +#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_LO 0xF02E00FF + +/* TIMOFF1 */ +#define R367_OFDM_TIMOFF1 0xF02F +#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_HI 0xF02F00FF + +/* TIMOFF2 */ +#define R367_OFDM_TIMOFF2 0xF030 +#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_LO 0xF03000FF + +/* EPQ */ +#define R367_OFDM_EPQ 0xF031 +#define F367_OFDM_EPQ1 0xF03100FF + +/* EPQAUTO */ +#define R367_OFDM_EPQAUTO 0xF032 +#define F367_OFDM_EPQ2 0xF03200FF + +/* SYR_UPDATE */ +#define R367_OFDM_SYR_UPDATE 0xF033 +#define F367_OFDM_SYR_PROTV 0xF0330080 +#define F367_OFDM_SYR_PROTV_GAIN 0xF0330060 +#define F367_OFDM_SYR_FILTER 0xF0330010 +#define F367_OFDM_SYR_TRACK_THRES 0xF033000C + +/* CHPFREE */ +#define R367_OFDM_CHPFREE 0xF034 +#define F367_OFDM_CHP_FREE 0xF03400FF + +/* PPM_STATE_MAC */ +#define R367_OFDM_PPM_STATE_MAC 0xF035 +#define F367_OFDM_PPM_STATE_MACHINE_DECODER 0xF035003F + +/* INR_THRESHOLD */ +#define R367_OFDM_INR_THRESHOLD 0xF036 +#define F367_OFDM_INR_THRESH 0xF03600FF + +/* EPQ_TPS_ID_CELL */ +#define R367_OFDM_EPQ_TPS_ID_CELL 0xF037 +#define F367_OFDM_ENABLE_LGTH_TO_CF 0xF0370080 +#define F367_OFDM_DIS_TPS_RSVD 0xF0370040 +#define F367_OFDM_DIS_BCH 0xF0370020 +#define F367_OFDM_DIS_ID_CEL 0xF0370010 +#define F367_OFDM_TPS_ADJUST_SYM 0xF037000F + +/* EPQ_CFG */ +#define R367_OFDM_EPQ_CFG 0xF038 +#define F367_OFDM_EPQ_RANGE 0xF0380002 +#define F367_OFDM_EPQ_SOFT 0xF0380001 + +/* EPQ_STATUS */ +#define R367_OFDM_EPQ_STATUS 0xF039 +#define F367_OFDM_SLOPE_INC 0xF03900FC +#define F367_OFDM_TPS_FIELD 0xF0390003 + +/* AUTORELOCK */ +#define R367_OFDM_AUTORELOCK 0xF03A +#define F367_OFDM_BYPASS_BER_TEMPO 0xF03A0080 +#define F367_OFDM_BER_TEMPO 0xF03A0070 +#define F367_OFDM_BYPASS_COFDM_TEMPO 0xF03A0008 +#define F367_OFDM_COFDM_TEMPO 0xF03A0007 + +/* BER_THR_VMSB */ +#define R367_OFDM_BER_THR_VMSB 0xF03B +#define F367_OFDM_BER_THRESHOLD_HI 0xF03B00FF + +/* BER_THR_MSB */ +#define R367_OFDM_BER_THR_MSB 0xF03C +#define F367_OFDM_BER_THRESHOLD_MID 0xF03C00FF + +/* BER_THR_LSB */ +#define R367_OFDM_BER_THR_LSB 0xF03D +#define F367_OFDM_BER_THRESHOLD_LO 0xF03D00FF + +/* CCD */ +#define R367_OFDM_CCD 0xF03E +#define F367_OFDM_CCD_DETECTED 0xF03E0080 +#define F367_OFDM_CCD_RESET 0xF03E0040 +#define F367_OFDM_CCD_THRESHOLD 0xF03E000F + +/* SPECTR_CFG */ +#define R367_OFDM_SPECTR_CFG 0xF03F +#define F367_OFDM_SPECT_CFG 0xF03F0003 + +/* CONSTMU_MSB */ +#define R367_OFDM_CONSTMU_MSB 0xF040 +#define F367_OFDM_CONSTMU_FREEZE 0xF0400080 +#define F367_OFDM_CONSTNU_FORCE_EN 0xF0400040 +#define F367_OFDM_CONST_MU_MSB 0xF040003F + +/* CONSTMU_LSB */ +#define R367_OFDM_CONSTMU_LSB 0xF041 +#define F367_OFDM_CONST_MU_LSB 0xF04100FF + +/* CONSTMU_MAX_MSB */ +#define R367_OFDM_CONSTMU_MAX_MSB 0xF042 +#define F367_OFDM_CONST_MU_MAX_MSB 0xF042003F + +/* CONSTMU_MAX_LSB */ +#define R367_OFDM_CONSTMU_MAX_LSB 0xF043 +#define F367_OFDM_CONST_MU_MAX_LSB 0xF04300FF + +/* ALPHANOISE */ +#define R367_OFDM_ALPHANOISE 0xF044 +#define F367_OFDM_USE_ALLFILTER 0xF0440080 +#define F367_OFDM_INTER_ON 0xF0440040 +#define F367_OFDM_ALPHA_NOISE 0xF044001F + +/* MAXGP_MSB */ +#define R367_OFDM_MAXGP_MSB 0xF045 +#define F367_OFDM_MUFILTER_LENGTH 0xF04500F0 +#define F367_OFDM_MAX_GP_MSB 0xF045000F + +/* MAXGP_LSB */ +#define R367_OFDM_MAXGP_LSB 0xF046 +#define F367_OFDM_MAX_GP_LSB 0xF04600FF + +/* ALPHAMSB */ +#define R367_OFDM_ALPHAMSB 0xF047 +#define F367_OFDM_CHC_DATARATE 0xF04700C0 +#define F367_OFDM_ALPHA_MSB 0xF047003F + +/* ALPHALSB */ +#define R367_OFDM_ALPHALSB 0xF048 +#define F367_OFDM_ALPHA_LSB 0xF04800FF + +/* PILOT_ACCU */ +#define R367_OFDM_PILOT_ACCU 0xF049 +#define F367_OFDM_USE_SCAT4ADDAPT 0xF0490080 +#define F367_OFDM_PILOT_ACC 0xF049001F + +/* PILOTMU_ACCU */ +#define R367_OFDM_PILOTMU_ACCU 0xF04A +#define F367_OFDM_DISCARD_BAD_SP 0xF04A0080 +#define F367_OFDM_DISCARD_BAD_CP 0xF04A0040 +#define F367_OFDM_PILOT_MU_ACCU 0xF04A001F + +/* FILT_CHANNEL_EST */ +#define R367_OFDM_FILT_CHANNEL_EST 0xF04B +#define F367_OFDM_USE_FILT_PILOT 0xF04B0080 +#define F367_OFDM_FILT_CHANNEL 0xF04B007F + +/* ALPHA_NOPISE_FREQ */ +#define R367_OFDM_ALPHA_NOPISE_FREQ 0xF04C +#define F367_OFDM_NOISE_FREQ_FILT 0xF04C0040 +#define F367_OFDM_ALPHA_NOISE_FREQ 0xF04C003F + +/* RATIO_PILOT */ +#define R367_OFDM_RATIO_PILOT 0xF04D +#define F367_OFDM_RATIO_MEAN_SP 0xF04D00F0 +#define F367_OFDM_RATIO_MEAN_CP 0xF04D000F + +/* CHC_CTL */ +#define R367_OFDM_CHC_CTL 0xF04E +#define F367_OFDM_TRACK_EN 0xF04E0080 +#define F367_OFDM_NOISE_NORM_EN 0xF04E0040 +#define F367_OFDM_FORCE_CHC_RESET 0xF04E0020 +#define F367_OFDM_SHORT_TIME 0xF04E0010 +#define F367_OFDM_FORCE_STATE_EN 0xF04E0008 +#define F367_OFDM_FORCE_STATE 0xF04E0007 + +/* EPQ_ADJUST */ +#define R367_OFDM_EPQ_ADJUST 0xF04F +#define F367_OFDM_ADJUST_SCAT_IND 0xF04F00C0 +#define F367_OFDM_ONE_SYMBOL 0xF04F0010 +#define F367_OFDM_EPQ_DECAY 0xF04F000E +#define F367_OFDM_HOLD_SLOPE 0xF04F0001 + +/* EPQ_THRES */ +#define R367_OFDM_EPQ_THRES 0xF050 +#define F367_OFDM_EPQ_THR 0xF05000FF + +/* OMEGA_CTL */ +#define R367_OFDM_OMEGA_CTL 0xF051 +#define F367_OFDM_OMEGA_RST 0xF0510080 +#define F367_OFDM_FREEZE_OMEGA 0xF0510040 +#define F367_OFDM_OMEGA_SEL 0xF051003F + +/* GP_CTL */ +#define R367_OFDM_GP_CTL 0xF052 +#define F367_OFDM_CHC_STATE 0xF05200E0 +#define F367_OFDM_FREEZE_GP 0xF0520010 +#define F367_OFDM_GP_SEL 0xF052000F + +/* MUMSB */ +#define R367_OFDM_MUMSB 0xF053 +#define F367_OFDM_MU_MSB 0xF053007F + +/* MULSB */ +#define R367_OFDM_MULSB 0xF054 +#define F367_OFDM_MU_LSB 0xF05400FF + +/* GPMSB */ +#define R367_OFDM_GPMSB 0xF055 +#define F367_OFDM_CSI_THRESHOLD 0xF05500E0 +#define F367_OFDM_GP_MSB 0xF055000F + +/* GPLSB */ +#define R367_OFDM_GPLSB 0xF056 +#define F367_OFDM_GP_LSB 0xF05600FF + +/* OMEGAMSB */ +#define R367_OFDM_OMEGAMSB 0xF057 +#define F367_OFDM_OMEGA_MSB 0xF057007F + +/* OMEGALSB */ +#define R367_OFDM_OMEGALSB 0xF058 +#define F367_OFDM_OMEGA_LSB 0xF05800FF + +/* SCAT_NB */ +#define R367_OFDM_SCAT_NB 0xF059 +#define F367_OFDM_CHC_TEST 0xF05900F8 +#define F367_OFDM_SCAT_NUMB 0xF0590003 + +/* CHC_DUMMY */ +#define R367_OFDM_CHC_DUMMY 0xF05A +#define F367_OFDM_CHC_DUM 0xF05A00FF + +/* INC_CTL */ +#define R367_OFDM_INC_CTL 0xF05B +#define F367_OFDM_INC_BYPASS 0xF05B0080 +#define F367_OFDM_INC_NDEPTH 0xF05B000C +#define F367_OFDM_INC_MADEPTH 0xF05B0003 + +/* INCTHRES_COR1 */ +#define R367_OFDM_INCTHRES_COR1 0xF05C +#define F367_OFDM_INC_THRES_COR1 0xF05C00FF + +/* INCTHRES_COR2 */ +#define R367_OFDM_INCTHRES_COR2 0xF05D +#define F367_OFDM_INC_THRES_COR2 0xF05D00FF + +/* INCTHRES_DET1 */ +#define R367_OFDM_INCTHRES_DET1 0xF05E +#define F367_OFDM_INC_THRES_DET1 0xF05E003F + +/* INCTHRES_DET2 */ +#define R367_OFDM_INCTHRES_DET2 0xF05F +#define F367_OFDM_INC_THRES_DET2 0xF05F003F + +/* IIR_CELLNB */ +#define R367_OFDM_IIR_CELLNB 0xF060 +#define F367_OFDM_NRST_IIR 0xF0600080 +#define F367_OFDM_IIR_CELL_NB 0xF0600007 + +/* IIRCX_COEFF1_MSB */ +#define R367_OFDM_IIRCX_COEFF1_MSB 0xF061 +#define F367_OFDM_IIR_CX_COEFF1_MSB 0xF06100FF + +/* IIRCX_COEFF1_LSB */ +#define R367_OFDM_IIRCX_COEFF1_LSB 0xF062 +#define F367_OFDM_IIR_CX_COEFF1_LSB 0xF06200FF + +/* IIRCX_COEFF2_MSB */ +#define R367_OFDM_IIRCX_COEFF2_MSB 0xF063 +#define F367_OFDM_IIR_CX_COEFF2_MSB 0xF06300FF + +/* IIRCX_COEFF2_LSB */ +#define R367_OFDM_IIRCX_COEFF2_LSB 0xF064 +#define F367_OFDM_IIR_CX_COEFF2_LSB 0xF06400FF + +/* IIRCX_COEFF3_MSB */ +#define R367_OFDM_IIRCX_COEFF3_MSB 0xF065 +#define F367_OFDM_IIR_CX_COEFF3_MSB 0xF06500FF + +/* IIRCX_COEFF3_LSB */ +#define R367_OFDM_IIRCX_COEFF3_LSB 0xF066 +#define F367_OFDM_IIR_CX_COEFF3_LSB 0xF06600FF + +/* IIRCX_COEFF4_MSB */ +#define R367_OFDM_IIRCX_COEFF4_MSB 0xF067 +#define F367_OFDM_IIR_CX_COEFF4_MSB 0xF06700FF + +/* IIRCX_COEFF4_LSB */ +#define R367_OFDM_IIRCX_COEFF4_LSB 0xF068 +#define F367_OFDM_IIR_CX_COEFF4_LSB 0xF06800FF + +/* IIRCX_COEFF5_MSB */ +#define R367_OFDM_IIRCX_COEFF5_MSB 0xF069 +#define F367_OFDM_IIR_CX_COEFF5_MSB 0xF06900FF + +/* IIRCX_COEFF5_LSB */ +#define R367_OFDM_IIRCX_COEFF5_LSB 0xF06A +#define F367_OFDM_IIR_CX_COEFF5_LSB 0xF06A00FF + +/* FEPATH_CFG */ +#define R367_OFDM_FEPATH_CFG 0xF06B +#define F367_OFDM_DEMUX_SWAP 0xF06B0004 +#define F367_OFDM_DIGAGC_SWAP 0xF06B0002 +#define F367_OFDM_LONGPATH_IF 0xF06B0001 + +/* PMC1_FUNC */ +#define R367_OFDM_PMC1_FUNC 0xF06C +#define F367_OFDM_SOFT_RSTN 0xF06C0080 +#define F367_OFDM_PMC1_AVERAGE_TIME 0xF06C0078 +#define F367_OFDM_PMC1_WAIT_TIME 0xF06C0006 +#define F367_OFDM_PMC1_2N_SEL 0xF06C0001 + +/* PMC1_FOR */ +#define R367_OFDM_PMC1_FOR 0xF06D +#define F367_OFDM_PMC1_FORCE 0xF06D0080 +#define F367_OFDM_PMC1_FORCE_VALUE 0xF06D007C + +/* PMC2_FUNC */ +#define R367_OFDM_PMC2_FUNC 0xF06E +#define F367_OFDM_PMC2_SOFT_STN 0xF06E0080 +#define F367_OFDM_PMC2_ACCU_TIME 0xF06E0070 +#define F367_OFDM_PMC2_CMDP_MN 0xF06E0008 +#define F367_OFDM_PMC2_SWAP 0xF06E0004 + +/* STATUS_ERR_DA */ +#define R367_OFDM_STATUS_ERR_DA 0xF06F +#define F367_OFDM_COM_USEGAINTRK 0xF06F0080 +#define F367_OFDM_COM_AGCLOCK 0xF06F0040 +#define F367_OFDM_AUT_AGCLOCK 0xF06F0020 +#define F367_OFDM_MIN_ERR_X_LSB 0xF06F000F + +/* DIG_AGC_R */ +#define R367_OFDM_DIG_AGC_R 0xF070 +#define F367_OFDM_COM_SOFT_RSTN 0xF0700080 +#define F367_OFDM_COM_AGC_ON 0xF0700040 +#define F367_OFDM_COM_EARLY 0xF0700020 +#define F367_OFDM_AUT_SOFT_RESETN 0xF0700010 +#define F367_OFDM_AUT_AGC_ON 0xF0700008 +#define F367_OFDM_AUT_EARLY 0xF0700004 +#define F367_OFDM_AUT_ROT_EN 0xF0700002 +#define F367_OFDM_LOCK_SOFT_RESETN 0xF0700001 + +/* COMAGC_TARMSB */ +#define R367_OFDM_COMAGC_TARMSB 0xF071 +#define F367_OFDM_COM_AGC_TARGET_MSB 0xF07100FF + +/* COM_AGC_TAR_ENMODE */ +#define R367_OFDM_COM_AGC_TAR_ENMODE 0xF072 +#define F367_OFDM_COM_AGC_TARGET_LSB 0xF07200F0 +#define F367_OFDM_COM_ENMODE 0xF072000F + +/* COM_AGC_CFG */ +#define R367_OFDM_COM_AGC_CFG 0xF073 +#define F367_OFDM_COM_N 0xF07300F8 +#define F367_OFDM_COM_STABMODE 0xF0730006 +#define F367_OFDM_ERR_SEL 0xF0730001 + +/* COM_AGC_GAIN1 */ +#define R367_OFDM_COM_AGC_GAIN1 0xF074 +#define F367_OFDM_COM_GAIN1ACK 0xF07400F0 +#define F367_OFDM_COM_GAIN1TRK 0xF074000F + +/* AUT_AGC_TARGETMSB */ +#define R367_OFDM_AUT_AGC_TARGETMSB 0xF075 +#define F367_OFDM_AUT_AGC_TARGET_MSB 0xF07500FF + +/* LOCK_DET_MSB */ +#define R367_OFDM_LOCK_DET_MSB 0xF076 +#define F367_OFDM_LOCK_DETECT_MSB 0xF07600FF + +/* AGCTAR_LOCK_LSBS */ +#define R367_OFDM_AGCTAR_LOCK_LSBS 0xF077 +#define F367_OFDM_AUT_AGC_TARGET_LSB 0xF07700F0 +#define F367_OFDM_LOCK_DETECT_LSB 0xF077000F + +/* AUT_GAIN_EN */ +#define R367_OFDM_AUT_GAIN_EN 0xF078 +#define F367_OFDM_AUT_ENMODE 0xF07800F0 +#define F367_OFDM_AUT_GAIN2 0xF078000F + +/* AUT_CFG */ +#define R367_OFDM_AUT_CFG 0xF079 +#define F367_OFDM_AUT_N 0xF07900F8 +#define F367_OFDM_INT_CHOICE 0xF0790006 +#define F367_OFDM_INT_LOAD 0xF0790001 + +/* LOCKN */ +#define R367_OFDM_LOCKN 0xF07A +#define F367_OFDM_LOCK_N 0xF07A00F8 +#define F367_OFDM_SEL_IQNTAR 0xF07A0004 +#define F367_OFDM_LOCK_DETECT_CHOICE 0xF07A0003 + +/* INT_X_3 */ +#define R367_OFDM_INT_X_3 0xF07B +#define F367_OFDM_INT_X3 0xF07B00FF + +/* INT_X_2 */ +#define R367_OFDM_INT_X_2 0xF07C +#define F367_OFDM_INT_X2 0xF07C00FF + +/* INT_X_1 */ +#define R367_OFDM_INT_X_1 0xF07D +#define F367_OFDM_INT_X1 0xF07D00FF + +/* INT_X_0 */ +#define R367_OFDM_INT_X_0 0xF07E +#define F367_OFDM_INT_X0 0xF07E00FF + +/* MIN_ERRX_MSB */ +#define R367_OFDM_MIN_ERRX_MSB 0xF07F +#define F367_OFDM_MIN_ERR_X_MSB 0xF07F00FF + +/* COR_CTL */ +#define R367_OFDM_COR_CTL 0xF080 +#define F367_OFDM_CORE_ACTIVE 0xF0800020 +#define F367_OFDM_HOLD 0xF0800010 +#define F367_OFDM_CORE_STATE_CTL 0xF080000F + +/* COR_STAT */ +#define R367_OFDM_COR_STAT 0xF081 +#define F367_OFDM_SCATT_LOCKED 0xF0810080 +#define F367_OFDM_TPS_LOCKED 0xF0810040 +#define F367_OFDM_SYR_LOCKED_COR 0xF0810020 +#define F367_OFDM_AGC_LOCKED_STAT 0xF0810010 +#define F367_OFDM_CORE_STATE_STAT 0xF081000F + +/* COR_INTEN */ +#define R367_OFDM_COR_INTEN 0xF082 +#define F367_OFDM_INTEN 0xF0820080 +#define F367_OFDM_INTEN_SYR 0xF0820020 +#define F367_OFDM_INTEN_FFT 0xF0820010 +#define F367_OFDM_INTEN_AGC 0xF0820008 +#define F367_OFDM_INTEN_TPS1 0xF0820004 +#define F367_OFDM_INTEN_TPS2 0xF0820002 +#define F367_OFDM_INTEN_TPS3 0xF0820001 + +/* COR_INTSTAT */ +#define R367_OFDM_COR_INTSTAT 0xF083 +#define F367_OFDM_INTSTAT_SYR 0xF0830020 +#define F367_OFDM_INTSTAT_FFT 0xF0830010 +#define F367_OFDM_INTSAT_AGC 0xF0830008 +#define F367_OFDM_INTSTAT_TPS1 0xF0830004 +#define F367_OFDM_INTSTAT_TPS2 0xF0830002 +#define F367_OFDM_INTSTAT_TPS3 0xF0830001 + +/* COR_MODEGUARD */ +#define R367_OFDM_COR_MODEGUARD 0xF084 +#define F367_OFDM_FORCE 0xF0840010 +#define F367_OFDM_MODE 0xF084000C +#define F367_OFDM_GUARD 0xF0840003 + +/* AGC_CTL */ +#define R367_OFDM_AGC_CTL 0xF085 +#define F367_OFDM_AGC_TIMING_FACTOR 0xF08500E0 +#define F367_OFDM_AGC_LAST 0xF0850010 +#define F367_OFDM_AGC_GAIN 0xF085000C +#define F367_OFDM_AGC_NEG 0xF0850002 +#define F367_OFDM_AGC_SET 0xF0850001 + +/* AGC_MANUAL1 */ +#define R367_OFDM_AGC_MANUAL1 0xF086 +#define F367_OFDM_AGC_VAL_LO 0xF08600FF + +/* AGC_MANUAL2 */ +#define R367_OFDM_AGC_MANUAL2 0xF087 +#define F367_OFDM_AGC_VAL_HI 0xF087000F + +/* AGC_TARG */ +#define R367_OFDM_AGC_TARG 0xF088 +#define F367_OFDM_AGC_TARGET 0xF08800FF + +/* AGC_GAIN1 */ +#define R367_OFDM_AGC_GAIN1 0xF089 +#define F367_OFDM_AGC_GAIN_LO 0xF08900FF + +/* AGC_GAIN2 */ +#define R367_OFDM_AGC_GAIN2 0xF08A +#define F367_OFDM_AGC_LOCKED_GAIN2 0xF08A0010 +#define F367_OFDM_AGC_GAIN_HI 0xF08A000F + +/* RESERVED_1 */ +#define R367_OFDM_RESERVED_1 0xF08B +#define F367_OFDM_RESERVED1 0xF08B00FF + +/* RESERVED_2 */ +#define R367_OFDM_RESERVED_2 0xF08C +#define F367_OFDM_RESERVED2 0xF08C00FF + +/* RESERVED_3 */ +#define R367_OFDM_RESERVED_3 0xF08D +#define F367_OFDM_RESERVED3 0xF08D00FF + +/* CAS_CTL */ +#define R367_OFDM_CAS_CTL 0xF08E +#define F367_OFDM_CCS_ENABLE 0xF08E0080 +#define F367_OFDM_ACS_DISABLE 0xF08E0040 +#define F367_OFDM_DAGC_DIS 0xF08E0020 +#define F367_OFDM_DAGC_GAIN 0xF08E0018 +#define F367_OFDM_CCSMU 0xF08E0007 + +/* CAS_FREQ */ +#define R367_OFDM_CAS_FREQ 0xF08F +#define F367_OFDM_CCS_FREQ 0xF08F00FF + +/* CAS_DAGCGAIN */ +#define R367_OFDM_CAS_DAGCGAIN 0xF090 +#define F367_OFDM_CAS_DAGC_GAIN 0xF09000FF + +/* SYR_CTL */ +#define R367_OFDM_SYR_CTL 0xF091 +#define F367_OFDM_SICTH_ENABLE 0xF0910080 +#define F367_OFDM_LONG_ECHO 0xF0910078 +#define F367_OFDM_AUTO_LE_EN 0xF0910004 +#define F367_OFDM_SYR_BYPASS 0xF0910002 +#define F367_OFDM_SYR_TR_DIS 0xF0910001 + +/* SYR_STAT */ +#define R367_OFDM_SYR_STAT 0xF092 +#define F367_OFDM_SYR_LOCKED_STAT 0xF0920010 +#define F367_OFDM_SYR_MODE 0xF092000C +#define F367_OFDM_SYR_GUARD 0xF0920003 + +/* SYR_NCO1 */ +#define R367_OFDM_SYR_NCO1 0xF093 +#define F367_OFDM_SYR_NCO_LO 0xF09300FF + +/* SYR_NCO2 */ +#define R367_OFDM_SYR_NCO2 0xF094 +#define F367_OFDM_SYR_NCO_HI 0xF094003F + +/* SYR_OFFSET1 */ +#define R367_OFDM_SYR_OFFSET1 0xF095 +#define F367_OFDM_SYR_OFFSET_LO 0xF09500FF + +/* SYR_OFFSET2 */ +#define R367_OFDM_SYR_OFFSET2 0xF096 +#define F367_OFDM_SYR_OFFSET_HI 0xF096003F + +/* FFT_CTL */ +#define R367_OFDM_FFT_CTL 0xF097 +#define F367_OFDM_SHIFT_FFT_TRIG 0xF0970018 +#define F367_OFDM_FFT_TRIGGER 0xF0970004 +#define F367_OFDM_FFT_MANUAL 0xF0970002 +#define F367_OFDM_IFFT_MODE 0xF0970001 + +/* SCR_CTL */ +#define R367_OFDM_SCR_CTL 0xF098 +#define F367_OFDM_SYRADJDECAY 0xF0980070 +#define F367_OFDM_SCR_CPEDIS 0xF0980002 +#define F367_OFDM_SCR_DIS 0xF0980001 + +/* PPM_CTL1 */ +#define R367_OFDM_PPM_CTL1 0xF099 +#define F367_OFDM_PPM_MAXFREQ 0xF0990030 +#define F367_OFDM_PPM_MAXTIM 0xF0990008 +#define F367_OFDM_PPM_INVSEL 0xF0990004 +#define F367_OFDM_PPM_SCATDIS 0xF0990002 +#define F367_OFDM_PPM_BYP 0xF0990001 + +/* TRL_CTL */ +#define R367_OFDM_TRL_CTL 0xF09A +#define F367_OFDM_TRL_NOMRATE_LSB 0xF09A0080 +#define F367_OFDM_TRL_GAIN_FACTOR 0xF09A0078 +#define F367_OFDM_TRL_LOOPGAIN 0xF09A0007 + +/* TRL_NOMRATE1 */ +#define R367_OFDM_TRL_NOMRATE1 0xF09B +#define F367_OFDM_TRL_NOMRATE_LO 0xF09B00FF + +/* TRL_NOMRATE2 */ +#define R367_OFDM_TRL_NOMRATE2 0xF09C +#define F367_OFDM_TRL_NOMRATE_HI 0xF09C00FF + +/* TRL_TIME1 */ +#define R367_OFDM_TRL_TIME1 0xF09D +#define F367_OFDM_TRL_TOFFSET_LO 0xF09D00FF + +/* TRL_TIME2 */ +#define R367_OFDM_TRL_TIME2 0xF09E +#define F367_OFDM_TRL_TOFFSET_HI 0xF09E00FF + +/* CRL_CTL */ +#define R367_OFDM_CRL_CTL 0xF09F +#define F367_OFDM_CRL_DIS 0xF09F0080 +#define F367_OFDM_CRL_GAIN_FACTOR 0xF09F0078 +#define F367_OFDM_CRL_LOOPGAIN 0xF09F0007 + +/* CRL_FREQ1 */ +#define R367_OFDM_CRL_FREQ1 0xF0A0 +#define F367_OFDM_CRL_FOFFSET_LO 0xF0A000FF + +/* CRL_FREQ2 */ +#define R367_OFDM_CRL_FREQ2 0xF0A1 +#define F367_OFDM_CRL_FOFFSET_HI 0xF0A100FF + +/* CRL_FREQ3 */ +#define R367_OFDM_CRL_FREQ3 0xF0A2 +#define F367_OFDM_CRL_FOFFSET_VHI 0xF0A200FF + +/* TPS_SFRAME_CTL */ +#define R367_OFDM_TPS_SFRAME_CTL 0xF0A3 +#define F367_OFDM_TPS_SFRAME_SYNC 0xF0A30001 + +/* CHC_SNR */ +#define R367_OFDM_CHC_SNR 0xF0A4 +#define F367_OFDM_CHCSNR 0xF0A400FF + +/* BDI_CTL */ +#define R367_OFDM_BDI_CTL 0xF0A5 +#define F367_OFDM_BDI_LPSEL 0xF0A50002 +#define F367_OFDM_BDI_SERIAL 0xF0A50001 + +/* DMP_CTL */ +#define R367_OFDM_DMP_CTL 0xF0A6 +#define F367_OFDM_DMP_SCALING_FACTOR 0xF0A6001E +#define F367_OFDM_DMP_SDDIS 0xF0A60001 + +/* TPS_RCVD1 */ +#define R367_OFDM_TPS_RCVD1 0xF0A7 +#define F367_OFDM_TPS_CHANGE 0xF0A70040 +#define F367_OFDM_BCH_OK 0xF0A70020 +#define F367_OFDM_TPS_SYNC 0xF0A70010 +#define F367_OFDM_TPS_FRAME 0xF0A70003 + +/* TPS_RCVD2 */ +#define R367_OFDM_TPS_RCVD2 0xF0A8 +#define F367_OFDM_TPS_HIERMODE 0xF0A80070 +#define F367_OFDM_TPS_CONST 0xF0A80003 + +/* TPS_RCVD3 */ +#define R367_OFDM_TPS_RCVD3 0xF0A9 +#define F367_OFDM_TPS_LPCODE 0xF0A90070 +#define F367_OFDM_TPS_HPCODE 0xF0A90007 + +/* TPS_RCVD4 */ +#define R367_OFDM_TPS_RCVD4 0xF0AA +#define F367_OFDM_TPS_GUARD 0xF0AA0030 +#define F367_OFDM_TPS_MODE 0xF0AA0003 + +/* TPS_ID_CELL1 */ +#define R367_OFDM_TPS_ID_CELL1 0xF0AB +#define F367_OFDM_TPS_ID_CELL_LO 0xF0AB00FF + +/* TPS_ID_CELL2 */ +#define R367_OFDM_TPS_ID_CELL2 0xF0AC +#define F367_OFDM_TPS_ID_CELL_HI 0xF0AC00FF + +/* TPS_RCVD5_SET1 */ +#define R367_OFDM_TPS_RCVD5_SET1 0xF0AD +#define F367_OFDM_TPS_NA 0xF0AD00FC +#define F367_OFDM_TPS_SETFRAME 0xF0AD0003 + +/* TPS_SET2 */ +#define R367_OFDM_TPS_SET2 0xF0AE +#define F367_OFDM_TPS_SETHIERMODE 0xF0AE0070 +#define F367_OFDM_TPS_SETCONST 0xF0AE0003 + +/* TPS_SET3 */ +#define R367_OFDM_TPS_SET3 0xF0AF +#define F367_OFDM_TPS_SETLPCODE 0xF0AF0070 +#define F367_OFDM_TPS_SETHPCODE 0xF0AF0007 + +/* TPS_CTL */ +#define R367_OFDM_TPS_CTL 0xF0B0 +#define F367_OFDM_TPS_IMM 0xF0B00004 +#define F367_OFDM_TPS_BCHDIS 0xF0B00002 +#define F367_OFDM_TPS_UPDDIS 0xF0B00001 + +/* CTL_FFTOSNUM */ +#define R367_OFDM_CTL_FFTOSNUM 0xF0B1 +#define F367_OFDM_SYMBOL_NUMBER 0xF0B1007F + +/* TESTSELECT */ +#define R367_OFDM_TESTSELECT 0xF0B2 +#define F367_OFDM_TEST_SELECT 0xF0B2001F + +/* MSC_REV */ +#define R367_OFDM_MSC_REV 0xF0B3 +#define F367_OFDM_REV_NUMBER 0xF0B300FF + +/* PIR_CTL */ +#define R367_OFDM_PIR_CTL 0xF0B4 +#define F367_OFDM_FREEZE 0xF0B40001 + +/* SNR_CARRIER1 */ +#define R367_OFDM_SNR_CARRIER1 0xF0B5 +#define F367_OFDM_SNR_CARRIER_LO 0xF0B500FF + +/* SNR_CARRIER2 */ +#define R367_OFDM_SNR_CARRIER2 0xF0B6 +#define F367_OFDM_MEAN 0xF0B600C0 +#define F367_OFDM_SNR_CARRIER_HI 0xF0B6001F + +/* PPM_CPAMP */ +#define R367_OFDM_PPM_CPAMP 0xF0B7 +#define F367_OFDM_PPM_CPC 0xF0B700FF + +/* TSM_AP0 */ +#define R367_OFDM_TSM_AP0 0xF0B8 +#define F367_OFDM_ADDRESS_BYTE_0 0xF0B800FF + +/* TSM_AP1 */ +#define R367_OFDM_TSM_AP1 0xF0B9 +#define F367_OFDM_ADDRESS_BYTE_1 0xF0B900FF + +/* TSM_AP2 */ +#define R367_OFDM_TSM_AP2 0xF0BA +#define F367_OFDM_DATA_BYTE_0 0xF0BA00FF + +/* TSM_AP3 */ +#define R367_OFDM_TSM_AP3 0xF0BB +#define F367_OFDM_DATA_BYTE_1 0xF0BB00FF + +/* TSM_AP4 */ +#define R367_OFDM_TSM_AP4 0xF0BC +#define F367_OFDM_DATA_BYTE_2 0xF0BC00FF + +/* TSM_AP5 */ +#define R367_OFDM_TSM_AP5 0xF0BD +#define F367_OFDM_DATA_BYTE_3 0xF0BD00FF + +/* TSM_AP6 */ +#define R367_OFDM_TSM_AP6 0xF0BE +#define F367_OFDM_TSM_AP_6 0xF0BE00FF + +/* TSM_AP7 */ +#define R367_OFDM_TSM_AP7 0xF0BF +#define F367_OFDM_MEM_SELECT_BYTE 0xF0BF00FF + +/* TSTRES */ +#define R367_TSTRES 0xF0C0 +#define F367_FRES_DISPLAY 0xF0C00080 +#define F367_FRES_FIFO_AD 0xF0C00020 +#define F367_FRESRS 0xF0C00010 +#define F367_FRESACS 0xF0C00008 +#define F367_FRESFEC 0xF0C00004 +#define F367_FRES_PRIF 0xF0C00002 +#define F367_FRESCORE 0xF0C00001 + +/* ANACTRL */ +#define R367_ANACTRL 0xF0C1 +#define F367_BYPASS_XTAL 0xF0C10040 +#define F367_BYPASS_PLLXN 0xF0C1000C +#define F367_DIS_PAD_OSC 0xF0C10002 +#define F367_STDBY_PLLXN 0xF0C10001 + +/* TSTBUS */ +#define R367_TSTBUS 0xF0C2 +#define F367_TS_BYTE_CLK_INV 0xF0C20080 +#define F367_CFG_IP 0xF0C20070 +#define F367_CFG_TST 0xF0C2000F + +/* TSTRATE */ +#define R367_TSTRATE 0xF0C6 +#define F367_FORCEPHA 0xF0C60080 +#define F367_FNEWPHA 0xF0C60010 +#define F367_FROT90 0xF0C60008 +#define F367_FR 0xF0C60007 + +/* CONSTMODE */ +#define R367_OFDM_CONSTMODE 0xF0CB +#define F367_OFDM_TST_PRIF 0xF0CB00E0 +#define F367_OFDM_CAR_TYPE 0xF0CB0018 +#define F367_OFDM_CONST_MODE 0xF0CB0003 + +/* CONSTCARR1 */ +#define R367_OFDM_CONSTCARR1 0xF0CC +#define F367_OFDM_CONST_CARR_LO 0xF0CC00FF + +/* CONSTCARR2 */ +#define R367_OFDM_CONSTCARR2 0xF0CD +#define F367_OFDM_CONST_CARR_HI 0xF0CD001F + +/* ICONSTEL */ +#define R367_OFDM_ICONSTEL 0xF0CE +#define F367_OFDM_PICONSTEL 0xF0CE00FF + +/* QCONSTEL */ +#define R367_OFDM_QCONSTEL 0xF0CF +#define F367_OFDM_PQCONSTEL 0xF0CF00FF + +/* TSTBISTRES0 */ +#define R367_OFDM_TSTBISTRES0 0xF0D0 +#define F367_OFDM_BEND_PPM 0xF0D00080 +#define F367_OFDM_BBAD_PPM 0xF0D00040 +#define F367_OFDM_BEND_FFTW 0xF0D00020 +#define F367_OFDM_BBAD_FFTW 0xF0D00010 +#define F367_OFDM_BEND_FFT_BUF 0xF0D00008 +#define F367_OFDM_BBAD_FFT_BUF 0xF0D00004 +#define F367_OFDM_BEND_SYR 0xF0D00002 +#define F367_OFDM_BBAD_SYR 0xF0D00001 + +/* TSTBISTRES1 */ +#define R367_OFDM_TSTBISTRES1 0xF0D1 +#define F367_OFDM_BEND_CHC_CP 0xF0D10080 +#define F367_OFDM_BBAD_CHC_CP 0xF0D10040 +#define F367_OFDM_BEND_CHCI 0xF0D10020 +#define F367_OFDM_BBAD_CHCI 0xF0D10010 +#define F367_OFDM_BEND_BDI 0xF0D10008 +#define F367_OFDM_BBAD_BDI 0xF0D10004 +#define F367_OFDM_BEND_SDI 0xF0D10002 +#define F367_OFDM_BBAD_SDI 0xF0D10001 + +/* TSTBISTRES2 */ +#define R367_OFDM_TSTBISTRES2 0xF0D2 +#define F367_OFDM_BEND_CHC_INC 0xF0D20080 +#define F367_OFDM_BBAD_CHC_INC 0xF0D20040 +#define F367_OFDM_BEND_CHC_SPP 0xF0D20020 +#define F367_OFDM_BBAD_CHC_SPP 0xF0D20010 +#define F367_OFDM_BEND_CHC_CPP 0xF0D20008 +#define F367_OFDM_BBAD_CHC_CPP 0xF0D20004 +#define F367_OFDM_BEND_CHC_SP 0xF0D20002 +#define F367_OFDM_BBAD_CHC_SP 0xF0D20001 + +/* TSTBISTRES3 */ +#define R367_OFDM_TSTBISTRES3 0xF0D3 +#define F367_OFDM_BEND_QAM 0xF0D30080 +#define F367_OFDM_BBAD_QAM 0xF0D30040 +#define F367_OFDM_BEND_SFEC_VIT 0xF0D30020 +#define F367_OFDM_BBAD_SFEC_VIT 0xF0D30010 +#define F367_OFDM_BEND_SFEC_DLINE 0xF0D30008 +#define F367_OFDM_BBAD_SFEC_DLINE 0xF0D30004 +#define F367_OFDM_BEND_SFEC_HW 0xF0D30002 +#define F367_OFDM_BBAD_SFEC_HW 0xF0D30001 + +/* RF_AGC1 */ +#define R367_RF_AGC1 0xF0D4 +#define F367_RF_AGC1_LEVEL_HI 0xF0D400FF + +/* RF_AGC2 */ +#define R367_RF_AGC2 0xF0D5 +#define F367_REF_ADGP 0xF0D50080 +#define F367_STDBY_ADCGP 0xF0D50020 +#define F367_CHANNEL_SEL 0xF0D5001C +#define F367_RF_AGC1_LEVEL_LO 0xF0D50003 + +/* ANADIGCTRL */ +#define R367_ANADIGCTRL 0xF0D7 +#define F367_SEL_CLKDEM 0xF0D70020 +#define F367_EN_BUFFER_Q 0xF0D70010 +#define F367_EN_BUFFER_I 0xF0D70008 +#define F367_ADC_RIS_EGDE 0xF0D70004 +#define F367_SGN_ADC 0xF0D70002 +#define F367_SEL_AD12_SYNC 0xF0D70001 + +/* PLLMDIV */ +#define R367_PLLMDIV 0xF0D8 +#define F367_PLL_MDIV 0xF0D800FF + +/* PLLNDIV */ +#define R367_PLLNDIV 0xF0D9 +#define F367_PLL_NDIV 0xF0D900FF + +/* PLLSETUP */ +#define R367_PLLSETUP 0xF0DA +#define F367_PLL_PDIV 0xF0DA0070 +#define F367_PLL_KDIV 0xF0DA000F + +/* DUAL_AD12 */ +#define R367_DUAL_AD12 0xF0DB +#define F367_FS20M 0xF0DB0020 +#define F367_FS50M 0xF0DB0010 +#define F367_INMODE0 0xF0DB0008 +#define F367_POFFQ 0xF0DB0004 +#define F367_POFFI 0xF0DB0002 +#define F367_INMODE1 0xF0DB0001 + +/* TSTBIST */ +#define R367_TSTBIST 0xF0DC +#define F367_TST_BYP_CLK 0xF0DC0080 +#define F367_TST_GCLKENA_STD 0xF0DC0040 +#define F367_TST_GCLKENA 0xF0DC0020 +#define F367_TST_MEMBIST 0xF0DC001F + +/* PAD_COMP_CTRL */ +#define R367_PAD_COMP_CTRL 0xF0DD +#define F367_COMPTQ 0xF0DD0010 +#define F367_COMPEN 0xF0DD0008 +#define F367_FREEZE2 0xF0DD0004 +#define F367_SLEEP_INHBT 0xF0DD0002 +#define F367_CHIP_SLEEP 0xF0DD0001 + +/* PAD_COMP_WR */ +#define R367_PAD_COMP_WR 0xF0DE +#define F367_WR_ASRC 0xF0DE007F + +/* PAD_COMP_RD */ +#define R367_PAD_COMP_RD 0xF0DF +#define F367_COMPOK 0xF0DF0080 +#define F367_RD_ASRC 0xF0DF007F + +/* SYR_TARGET_FFTADJT_MSB */ +#define R367_OFDM_SYR_TARGET_FFTADJT_MSB 0xF100 +#define F367_OFDM_SYR_START 0xF1000080 +#define F367_OFDM_SYR_TARGET_FFTADJ_HI 0xF100000F + +/* SYR_TARGET_FFTADJT_LSB */ +#define R367_OFDM_SYR_TARGET_FFTADJT_LSB 0xF101 +#define F367_OFDM_SYR_TARGET_FFTADJ_LO 0xF10100FF + +/* SYR_TARGET_CHCADJT_MSB */ +#define R367_OFDM_SYR_TARGET_CHCADJT_MSB 0xF102 +#define F367_OFDM_SYR_TARGET_CHCADJ_HI 0xF102000F + +/* SYR_TARGET_CHCADJT_LSB */ +#define R367_OFDM_SYR_TARGET_CHCADJT_LSB 0xF103 +#define F367_OFDM_SYR_TARGET_CHCADJ_LO 0xF10300FF + +/* SYR_FLAG */ +#define R367_OFDM_SYR_FLAG 0xF104 +#define F367_OFDM_TRIG_FLG1 0xF1040080 +#define F367_OFDM_TRIG_FLG0 0xF1040040 +#define F367_OFDM_FFT_FLG1 0xF1040008 +#define F367_OFDM_FFT_FLG0 0xF1040004 +#define F367_OFDM_CHC_FLG1 0xF1040002 +#define F367_OFDM_CHC_FLG0 0xF1040001 + +/* CRL_TARGET1 */ +#define R367_OFDM_CRL_TARGET1 0xF105 +#define F367_OFDM_CRL_START 0xF1050080 +#define F367_OFDM_CRL_TARGET_VHI 0xF105000F + +/* CRL_TARGET2 */ +#define R367_OFDM_CRL_TARGET2 0xF106 +#define F367_OFDM_CRL_TARGET_HI 0xF10600FF + +/* CRL_TARGET3 */ +#define R367_OFDM_CRL_TARGET3 0xF107 +#define F367_OFDM_CRL_TARGET_LO 0xF10700FF + +/* CRL_TARGET4 */ +#define R367_OFDM_CRL_TARGET4 0xF108 +#define F367_OFDM_CRL_TARGET_VLO 0xF10800FF + +/* CRL_FLAG */ +#define R367_OFDM_CRL_FLAG 0xF109 +#define F367_OFDM_CRL_FLAG1 0xF1090002 +#define F367_OFDM_CRL_FLAG0 0xF1090001 + +/* TRL_TARGET1 */ +#define R367_OFDM_TRL_TARGET1 0xF10A +#define F367_OFDM_TRL_TARGET_HI 0xF10A00FF + +/* TRL_TARGET2 */ +#define R367_OFDM_TRL_TARGET2 0xF10B +#define F367_OFDM_TRL_TARGET_LO 0xF10B00FF + +/* TRL_CHC */ +#define R367_OFDM_TRL_CHC 0xF10C +#define F367_OFDM_TRL_START 0xF10C0080 +#define F367_OFDM_CHC_START 0xF10C0040 +#define F367_OFDM_TRL_FLAG1 0xF10C0002 +#define F367_OFDM_TRL_FLAG0 0xF10C0001 + +/* CHC_SNR_TARG */ +#define R367_OFDM_CHC_SNR_TARG 0xF10D +#define F367_OFDM_CHC_SNR_TARGET 0xF10D00FF + +/* TOP_TRACK */ +#define R367_OFDM_TOP_TRACK 0xF10E +#define F367_OFDM_TOP_START 0xF10E0080 +#define F367_OFDM_FIRST_FLAG 0xF10E0070 +#define F367_OFDM_TOP_FLAG1 0xF10E0008 +#define F367_OFDM_TOP_FLAG0 0xF10E0004 +#define F367_OFDM_CHC_FLAG1 0xF10E0002 +#define F367_OFDM_CHC_FLAG0 0xF10E0001 + +/* TRACKER_FREE1 */ +#define R367_OFDM_TRACKER_FREE1 0xF10F +#define F367_OFDM_TRACKER_FREE_1 0xF10F00FF + +/* ERROR_CRL1 */ +#define R367_OFDM_ERROR_CRL1 0xF110 +#define F367_OFDM_ERROR_CRL_VHI 0xF11000FF + +/* ERROR_CRL2 */ +#define R367_OFDM_ERROR_CRL2 0xF111 +#define F367_OFDM_ERROR_CRL_HI 0xF11100FF + +/* ERROR_CRL3 */ +#define R367_OFDM_ERROR_CRL3 0xF112 +#define F367_OFDM_ERROR_CRL_LOI 0xF11200FF + +/* ERROR_CRL4 */ +#define R367_OFDM_ERROR_CRL4 0xF113 +#define F367_OFDM_ERROR_CRL_VLO 0xF11300FF + +/* DEC_NCO1 */ +#define R367_OFDM_DEC_NCO1 0xF114 +#define F367_OFDM_DEC_NCO_VHI 0xF11400FF + +/* DEC_NCO2 */ +#define R367_OFDM_DEC_NCO2 0xF115 +#define F367_OFDM_DEC_NCO_HI 0xF11500FF + +/* DEC_NCO3 */ +#define R367_OFDM_DEC_NCO3 0xF116 +#define F367_OFDM_DEC_NCO_LO 0xF11600FF + +/* SNR */ +#define R367_OFDM_SNR 0xF117 +#define F367_OFDM_SNRATIO 0xF11700FF + +/* SYR_FFTADJ1 */ +#define R367_OFDM_SYR_FFTADJ1 0xF118 +#define F367_OFDM_SYR_FFTADJ_HI 0xF11800FF + +/* SYR_FFTADJ2 */ +#define R367_OFDM_SYR_FFTADJ2 0xF119 +#define F367_OFDM_SYR_FFTADJ_LO 0xF11900FF + +/* SYR_CHCADJ1 */ +#define R367_OFDM_SYR_CHCADJ1 0xF11A +#define F367_OFDM_SYR_CHCADJ_HI 0xF11A00FF + +/* SYR_CHCADJ2 */ +#define R367_OFDM_SYR_CHCADJ2 0xF11B +#define F367_OFDM_SYR_CHCADJ_LO 0xF11B00FF + +/* SYR_OFF */ +#define R367_OFDM_SYR_OFF 0xF11C +#define F367_OFDM_SYR_OFFSET 0xF11C00FF + +/* PPM_OFFSET1 */ +#define R367_OFDM_PPM_OFFSET1 0xF11D +#define F367_OFDM_PPM_OFFSET_HI 0xF11D00FF + +/* PPM_OFFSET2 */ +#define R367_OFDM_PPM_OFFSET2 0xF11E +#define F367_OFDM_PPM_OFFSET_LO 0xF11E00FF + +/* TRACKER_FREE2 */ +#define R367_OFDM_TRACKER_FREE2 0xF11F +#define F367_OFDM_TRACKER_FREE_2 0xF11F00FF + +/* DEBG_LT10 */ +#define R367_OFDM_DEBG_LT10 0xF120 +#define F367_OFDM_DEBUG_LT10 0xF12000FF + +/* DEBG_LT11 */ +#define R367_OFDM_DEBG_LT11 0xF121 +#define F367_OFDM_DEBUG_LT11 0xF12100FF + +/* DEBG_LT12 */ +#define R367_OFDM_DEBG_LT12 0xF122 +#define F367_OFDM_DEBUG_LT12 0xF12200FF + +/* DEBG_LT13 */ +#define R367_OFDM_DEBG_LT13 0xF123 +#define F367_OFDM_DEBUG_LT13 0xF12300FF + +/* DEBG_LT14 */ +#define R367_OFDM_DEBG_LT14 0xF124 +#define F367_OFDM_DEBUG_LT14 0xF12400FF + +/* DEBG_LT15 */ +#define R367_OFDM_DEBG_LT15 0xF125 +#define F367_OFDM_DEBUG_LT15 0xF12500FF + +/* DEBG_LT16 */ +#define R367_OFDM_DEBG_LT16 0xF126 +#define F367_OFDM_DEBUG_LT16 0xF12600FF + +/* DEBG_LT17 */ +#define R367_OFDM_DEBG_LT17 0xF127 +#define F367_OFDM_DEBUG_LT17 0xF12700FF + +/* DEBG_LT18 */ +#define R367_OFDM_DEBG_LT18 0xF128 +#define F367_OFDM_DEBUG_LT18 0xF12800FF + +/* DEBG_LT19 */ +#define R367_OFDM_DEBG_LT19 0xF129 +#define F367_OFDM_DEBUG_LT19 0xF12900FF + +/* DEBG_LT1A */ +#define R367_OFDM_DEBG_LT1A 0xF12A +#define F367_OFDM_DEBUG_LT1A 0xF12A00FF + +/* DEBG_LT1B */ +#define R367_OFDM_DEBG_LT1B 0xF12B +#define F367_OFDM_DEBUG_LT1B 0xF12B00FF + +/* DEBG_LT1C */ +#define R367_OFDM_DEBG_LT1C 0xF12C +#define F367_OFDM_DEBUG_LT1C 0xF12C00FF + +/* DEBG_LT1D */ +#define R367_OFDM_DEBG_LT1D 0xF12D +#define F367_OFDM_DEBUG_LT1D 0xF12D00FF + +/* DEBG_LT1E */ +#define R367_OFDM_DEBG_LT1E 0xF12E +#define F367_OFDM_DEBUG_LT1E 0xF12E00FF + +/* DEBG_LT1F */ +#define R367_OFDM_DEBG_LT1F 0xF12F +#define F367_OFDM_DEBUG_LT1F 0xF12F00FF + +/* RCCFGH */ +#define R367_OFDM_RCCFGH 0xF200 +#define F367_OFDM_TSRCFIFO_DVBCI 0xF2000080 +#define F367_OFDM_TSRCFIFO_SERIAL 0xF2000040 +#define F367_OFDM_TSRCFIFO_DISABLE 0xF2000020 +#define F367_OFDM_TSFIFO_2TORC 0xF2000010 +#define F367_OFDM_TSRCFIFO_HSGNLOUT 0xF2000008 +#define F367_OFDM_TSRCFIFO_ERRMODE 0xF2000006 +#define F367_OFDM_RCCFGH_0 0xF2000001 + +/* RCCFGM */ +#define R367_OFDM_RCCFGM 0xF201 +#define F367_OFDM_TSRCFIFO_MANSPEED 0xF20100C0 +#define F367_OFDM_TSRCFIFO_PERMDATA 0xF2010020 +#define F367_OFDM_TSRCFIFO_NONEWSGNL 0xF2010010 +#define F367_OFDM_RCBYTE_OVERSAMPLING 0xF201000E +#define F367_OFDM_TSRCFIFO_INVDATA 0xF2010001 + +/* RCCFGL */ +#define R367_OFDM_RCCFGL 0xF202 +#define F367_OFDM_TSRCFIFO_BCLKDEL1CK 0xF20200C0 +#define F367_OFDM_RCCFGL_5 0xF2020020 +#define F367_OFDM_TSRCFIFO_DUTY50 0xF2020010 +#define F367_OFDM_TSRCFIFO_NSGNL2DATA 0xF2020008 +#define F367_OFDM_TSRCFIFO_DISSERMUX 0xF2020004 +#define F367_OFDM_RCCFGL_1 0xF2020002 +#define F367_OFDM_TSRCFIFO_STOPCKDIS 0xF2020001 + +/* RCINSDELH */ +#define R367_OFDM_RCINSDELH 0xF203 +#define F367_OFDM_TSRCDEL_SYNCBYTE 0xF2030080 +#define F367_OFDM_TSRCDEL_XXHEADER 0xF2030040 +#define F367_OFDM_TSRCDEL_BBHEADER 0xF2030020 +#define F367_OFDM_TSRCDEL_DATAFIELD 0xF2030010 +#define F367_OFDM_TSRCINSDEL_ISCR 0xF2030008 +#define F367_OFDM_TSRCINSDEL_NPD 0xF2030004 +#define F367_OFDM_TSRCINSDEL_RSPARITY 0xF2030002 +#define F367_OFDM_TSRCINSDEL_CRC8 0xF2030001 + +/* RCINSDELM */ +#define R367_OFDM_RCINSDELM 0xF204 +#define F367_OFDM_TSRCINS_BBPADDING 0xF2040080 +#define F367_OFDM_TSRCINS_BCHFEC 0xF2040040 +#define F367_OFDM_TSRCINS_LDPCFEC 0xF2040020 +#define F367_OFDM_TSRCINS_EMODCOD 0xF2040010 +#define F367_OFDM_TSRCINS_TOKEN 0xF2040008 +#define F367_OFDM_TSRCINS_XXXERR 0xF2040004 +#define F367_OFDM_TSRCINS_MATYPE 0xF2040002 +#define F367_OFDM_TSRCINS_UPL 0xF2040001 + +/* RCINSDELL */ +#define R367_OFDM_RCINSDELL 0xF205 +#define F367_OFDM_TSRCINS_DFL 0xF2050080 +#define F367_OFDM_TSRCINS_SYNCD 0xF2050040 +#define F367_OFDM_TSRCINS_BLOCLEN 0xF2050020 +#define F367_OFDM_TSRCINS_SIGPCOUNT 0xF2050010 +#define F367_OFDM_TSRCINS_FIFO 0xF2050008 +#define F367_OFDM_TSRCINS_REALPACK 0xF2050004 +#define F367_OFDM_TSRCINS_TSCONFIG 0xF2050002 +#define F367_OFDM_TSRCINS_LATENCY 0xF2050001 + +/* RCSTATUS */ +#define R367_OFDM_RCSTATUS 0xF206 +#define F367_OFDM_TSRCFIFO_LINEOK 0xF2060080 +#define F367_OFDM_TSRCFIFO_ERROR 0xF2060040 +#define F367_OFDM_TSRCFIFO_DATA7 0xF2060020 +#define F367_OFDM_RCSTATUS_4 0xF2060010 +#define F367_OFDM_TSRCFIFO_DEMODSEL 0xF2060008 +#define F367_OFDM_TSRC1FIFOSPEED_STORE 0xF2060004 +#define F367_OFDM_RCSTATUS_1 0xF2060002 +#define F367_OFDM_TSRCSERIAL_IMPOSSIBLE 0xF2060001 + +/* RCSPEED */ +#define R367_OFDM_RCSPEED 0xF207 +#define F367_OFDM_TSRCFIFO_OUTSPEED 0xF20700FF + +/* RCDEBUGM */ +#define R367_OFDM_RCDEBUGM 0xF208 +#define F367_OFDM_SD_UNSYNC 0xF2080080 +#define F367_OFDM_ULFLOCK_DETECTM 0xF2080040 +#define F367_OFDM_SUL_SELECTOS 0xF2080020 +#define F367_OFDM_DILUL_NOSCRBLE 0xF2080010 +#define F367_OFDM_NUL_SCRB 0xF2080008 +#define F367_OFDM_UL_SCRB 0xF2080004 +#define F367_OFDM_SCRAULBAD 0xF2080002 +#define F367_OFDM_SCRAUL_UNSYNC 0xF2080001 + +/* RCDEBUGL */ +#define R367_OFDM_RCDEBUGL 0xF209 +#define F367_OFDM_RS_ERR 0xF2090080 +#define F367_OFDM_LLFLOCK_DETECTM 0xF2090040 +#define F367_OFDM_NOT_SUL_SELECTOS 0xF2090020 +#define F367_OFDM_DILLL_NOSCRBLE 0xF2090010 +#define F367_OFDM_NLL_SCRB 0xF2090008 +#define F367_OFDM_LL_SCRB 0xF2090004 +#define F367_OFDM_SCRALLBAD 0xF2090002 +#define F367_OFDM_SCRALL_UNSYNC 0xF2090001 + +/* RCOBSCFG */ +#define R367_OFDM_RCOBSCFG 0xF20A +#define F367_OFDM_TSRCFIFO_OBSCFG 0xF20A00FF + +/* RCOBSM */ +#define R367_OFDM_RCOBSM 0xF20B +#define F367_OFDM_TSRCFIFO_OBSDATA_HI 0xF20B00FF + +/* RCOBSL */ +#define R367_OFDM_RCOBSL 0xF20C +#define F367_OFDM_TSRCFIFO_OBSDATA_LO 0xF20C00FF + +/* RCFECSPY */ +#define R367_OFDM_RCFECSPY 0xF210 +#define F367_OFDM_SPYRC_ENABLE 0xF2100080 +#define F367_OFDM_RCNO_SYNCBYTE 0xF2100040 +#define F367_OFDM_RCSERIAL_MODE 0xF2100020 +#define F367_OFDM_RCUNUSUAL_PACKET 0xF2100010 +#define F367_OFDM_BERRCMETER_DATAMODE 0xF210000C +#define F367_OFDM_BERRCMETER_LMODE 0xF2100002 +#define F367_OFDM_BERRCMETER_RESET 0xF2100001 + +/* RCFSPYCFG */ +#define R367_OFDM_RCFSPYCFG 0xF211 +#define F367_OFDM_FECSPYRC_INPUT 0xF21100C0 +#define F367_OFDM_RCRST_ON_ERROR 0xF2110020 +#define F367_OFDM_RCONE_SHOT 0xF2110010 +#define F367_OFDM_RCI2C_MODE 0xF211000C +#define F367_OFDM_SPYRC_HSTERESIS 0xF2110003 + +/* RCFSPYDATA */ +#define R367_OFDM_RCFSPYDATA 0xF212 +#define F367_OFDM_SPYRC_STUFFING 0xF2120080 +#define F367_OFDM_RCNOERR_PKTJITTER 0xF2120040 +#define F367_OFDM_SPYRC_CNULLPKT 0xF2120020 +#define F367_OFDM_SPYRC_OUTDATA_MODE 0xF212001F + +/* RCFSPYOUT */ +#define R367_OFDM_RCFSPYOUT 0xF213 +#define F367_OFDM_FSPYRC_DIRECT 0xF2130080 +#define F367_OFDM_RCFSPYOUT_6 0xF2130040 +#define F367_OFDM_SPYRC_OUTDATA_BUS 0xF2130038 +#define F367_OFDM_RCSTUFF_MODE 0xF2130007 + +/* RCFSTATUS */ +#define R367_OFDM_RCFSTATUS 0xF214 +#define F367_OFDM_SPYRC_ENDSIM 0xF2140080 +#define F367_OFDM_RCVALID_SIM 0xF2140040 +#define F367_OFDM_RCFOUND_SIGNAL 0xF2140020 +#define F367_OFDM_RCDSS_SYNCBYTE 0xF2140010 +#define F367_OFDM_RCRESULT_STATE 0xF214000F + +/* RCFGOODPACK */ +#define R367_OFDM_RCFGOODPACK 0xF215 +#define F367_OFDM_RCGOOD_PACKET 0xF21500FF + +/* RCFPACKCNT */ +#define R367_OFDM_RCFPACKCNT 0xF216 +#define F367_OFDM_RCPACKET_COUNTER 0xF21600FF + +/* RCFSPYMISC */ +#define R367_OFDM_RCFSPYMISC 0xF217 +#define F367_OFDM_RCLABEL_COUNTER 0xF21700FF + +/* RCFBERCPT4 */ +#define R367_OFDM_RCFBERCPT4 0xF218 +#define F367_OFDM_FBERRCMETER_CPT_MMMMSB 0xF21800FF + +/* RCFBERCPT3 */ +#define R367_OFDM_RCFBERCPT3 0xF219 +#define F367_OFDM_FBERRCMETER_CPT_MMMSB 0xF21900FF + +/* RCFBERCPT2 */ +#define R367_OFDM_RCFBERCPT2 0xF21A +#define F367_OFDM_FBERRCMETER_CPT_MMSB 0xF21A00FF + +/* RCFBERCPT1 */ +#define R367_OFDM_RCFBERCPT1 0xF21B +#define F367_OFDM_FBERRCMETER_CPT_MSB 0xF21B00FF + +/* RCFBERCPT0 */ +#define R367_OFDM_RCFBERCPT0 0xF21C +#define F367_OFDM_FBERRCMETER_CPT_LSB 0xF21C00FF + +/* RCFBERERR2 */ +#define R367_OFDM_RCFBERERR2 0xF21D +#define F367_OFDM_FBERRCMETER_ERR_HI 0xF21D00FF + +/* RCFBERERR1 */ +#define R367_OFDM_RCFBERERR1 0xF21E +#define F367_OFDM_FBERRCMETER_ERR 0xF21E00FF + +/* RCFBERERR0 */ +#define R367_OFDM_RCFBERERR0 0xF21F +#define F367_OFDM_FBERRCMETER_ERR_LO 0xF21F00FF + +/* RCFSTATESM */ +#define R367_OFDM_RCFSTATESM 0xF220 +#define F367_OFDM_RCRSTATE_F 0xF2200080 +#define F367_OFDM_RCRSTATE_E 0xF2200040 +#define F367_OFDM_RCRSTATE_D 0xF2200020 +#define F367_OFDM_RCRSTATE_C 0xF2200010 +#define F367_OFDM_RCRSTATE_B 0xF2200008 +#define F367_OFDM_RCRSTATE_A 0xF2200004 +#define F367_OFDM_RCRSTATE_9 0xF2200002 +#define F367_OFDM_RCRSTATE_8 0xF2200001 + +/* RCFSTATESL */ +#define R367_OFDM_RCFSTATESL 0xF221 +#define F367_OFDM_RCRSTATE_7 0xF2210080 +#define F367_OFDM_RCRSTATE_6 0xF2210040 +#define F367_OFDM_RCRSTATE_5 0xF2210020 +#define F367_OFDM_RCRSTATE_4 0xF2210010 +#define F367_OFDM_RCRSTATE_3 0xF2210008 +#define F367_OFDM_RCRSTATE_2 0xF2210004 +#define F367_OFDM_RCRSTATE_1 0xF2210002 +#define F367_OFDM_RCRSTATE_0 0xF2210001 + +/* RCFSPYBER */ +#define R367_OFDM_RCFSPYBER 0xF222 +#define F367_OFDM_RCFSPYBER_7 0xF2220080 +#define F367_OFDM_SPYRCOBS_XORREAD 0xF2220040 +#define F367_OFDM_FSPYRCBER_OBSMODE 0xF2220020 +#define F367_OFDM_FSPYRCBER_SYNCBYT 0xF2220010 +#define F367_OFDM_FSPYRCBER_UNSYNC 0xF2220008 +#define F367_OFDM_FSPYRCBER_CTIME 0xF2220007 + +/* RCFSPYDISTM */ +#define R367_OFDM_RCFSPYDISTM 0xF223 +#define F367_OFDM_RCPKTTIME_DISTANCE_HI 0xF22300FF + +/* RCFSPYDISTL */ +#define R367_OFDM_RCFSPYDISTL 0xF224 +#define F367_OFDM_RCPKTTIME_DISTANCE_LO 0xF22400FF + +/* RCFSPYOBS7 */ +#define R367_OFDM_RCFSPYOBS7 0xF228 +#define F367_OFDM_RCSPYOBS_SPYFAIL 0xF2280080 +#define F367_OFDM_RCSPYOBS_SPYFAIL1 0xF2280040 +#define F367_OFDM_RCSPYOBS_ERROR 0xF2280020 +#define F367_OFDM_RCSPYOBS_STROUT 0xF2280010 +#define F367_OFDM_RCSPYOBS_RESULTSTATE1 0xF228000F + +/* RCFSPYOBS6 */ +#define R367_OFDM_RCFSPYOBS6 0xF229 +#define F367_OFDM_RCSPYOBS_RESULTSTATE0 0xF22900F0 +#define F367_OFDM_RCSPYOBS_RESULTSTATEM1 0xF229000F + +/* RCFSPYOBS5 */ +#define R367_OFDM_RCFSPYOBS5 0xF22A +#define F367_OFDM_RCSPYOBS_BYTEOFPACKET1 0xF22A00FF + +/* RCFSPYOBS4 */ +#define R367_OFDM_RCFSPYOBS4 0xF22B +#define F367_OFDM_RCSPYOBS_BYTEVALUE1 0xF22B00FF + +/* RCFSPYOBS3 */ +#define R367_OFDM_RCFSPYOBS3 0xF22C +#define F367_OFDM_RCSPYOBS_DATA1 0xF22C00FF + +/* RCFSPYOBS2 */ +#define R367_OFDM_RCFSPYOBS2 0xF22D +#define F367_OFDM_RCSPYOBS_DATA0 0xF22D00FF + +/* RCFSPYOBS1 */ +#define R367_OFDM_RCFSPYOBS1 0xF22E +#define F367_OFDM_RCSPYOBS_DATAM1 0xF22E00FF + +/* RCFSPYOBS0 */ +#define R367_OFDM_RCFSPYOBS0 0xF22F +#define F367_OFDM_RCSPYOBS_DATAM2 0xF22F00FF + +/* TSGENERAL */ +#define R367_TSGENERAL 0xF230 +#define F367_TSGENERAL_7 0xF2300080 +#define F367_TSGENERAL_6 0xF2300040 +#define F367_TSFIFO_BCLK1ALL 0xF2300020 +#define F367_TSGENERAL_4 0xF2300010 +#define F367_MUXSTREAM_OUTMODE 0xF2300008 +#define F367_TSFIFO_PERMPARAL 0xF2300006 +#define F367_RST_REEDSOLO 0xF2300001 + +/* RC1SPEED */ +#define R367_RC1SPEED 0xF231 +#define F367_TSRCFIFO1_OUTSPEED 0xF23100FF + +/* TSGSTATUS */ +#define R367_TSGSTATUS 0xF232 +#define F367_TSGSTATUS_7 0xF2320080 +#define F367_TSGSTATUS_6 0xF2320040 +#define F367_RSMEM_FULL 0xF2320020 +#define F367_RS_MULTCALC 0xF2320010 +#define F367_RSIN_OVERTIME 0xF2320008 +#define F367_TSFIFO3_DEMODSEL 0xF2320004 +#define F367_TSFIFO2_DEMODSEL 0xF2320002 +#define F367_TSFIFO1_DEMODSEL 0xF2320001 + + +/* FECM */ +#define R367_OFDM_FECM 0xF233 +#define F367_OFDM_DSS_DVB 0xF2330080 +#define F367_OFDM_DEMOD_BYPASS 0xF2330040 +#define F367_OFDM_CMP_SLOWMODE 0xF2330020 +#define F367_OFDM_DSS_SRCH 0xF2330010 +#define F367_OFDM_FECM_3 0xF2330008 +#define F367_OFDM_DIFF_MODEVIT 0xF2330004 +#define F367_OFDM_SYNCVIT 0xF2330002 +#define F367_OFDM_I2CSYM 0xF2330001 + +/* VTH12 */ +#define R367_OFDM_VTH12 0xF234 +#define F367_OFDM_VTH_12 0xF23400FF + +/* VTH23 */ +#define R367_OFDM_VTH23 0xF235 +#define F367_OFDM_VTH_23 0xF23500FF + +/* VTH34 */ +#define R367_OFDM_VTH34 0xF236 +#define F367_OFDM_VTH_34 0xF23600FF + +/* VTH56 */ +#define R367_OFDM_VTH56 0xF237 +#define F367_OFDM_VTH_56 0xF23700FF + +/* VTH67 */ +#define R367_OFDM_VTH67 0xF238 +#define F367_OFDM_VTH_67 0xF23800FF + +/* VTH78 */ +#define R367_OFDM_VTH78 0xF239 +#define F367_OFDM_VTH_78 0xF23900FF + +/* VITCURPUN */ +#define R367_OFDM_VITCURPUN 0xF23A +#define F367_OFDM_VIT_MAPPING 0xF23A00E0 +#define F367_OFDM_VIT_CURPUN 0xF23A001F + +/* VERROR */ +#define R367_OFDM_VERROR 0xF23B +#define F367_OFDM_REGERR_VIT 0xF23B00FF + +/* PRVIT */ +#define R367_OFDM_PRVIT 0xF23C +#define F367_OFDM_PRVIT_7 0xF23C0080 +#define F367_OFDM_DIS_VTHLOCK 0xF23C0040 +#define F367_OFDM_E7_8VIT 0xF23C0020 +#define F367_OFDM_E6_7VIT 0xF23C0010 +#define F367_OFDM_E5_6VIT 0xF23C0008 +#define F367_OFDM_E3_4VIT 0xF23C0004 +#define F367_OFDM_E2_3VIT 0xF23C0002 +#define F367_OFDM_E1_2VIT 0xF23C0001 + +/* VAVSRVIT */ +#define R367_OFDM_VAVSRVIT 0xF23D +#define F367_OFDM_AMVIT 0xF23D0080 +#define F367_OFDM_FROZENVIT 0xF23D0040 +#define F367_OFDM_SNVIT 0xF23D0030 +#define F367_OFDM_TOVVIT 0xF23D000C +#define F367_OFDM_HYPVIT 0xF23D0003 + +/* VSTATUSVIT */ +#define R367_OFDM_VSTATUSVIT 0xF23E +#define F367_OFDM_VITERBI_ON 0xF23E0080 +#define F367_OFDM_END_LOOPVIT 0xF23E0040 +#define F367_OFDM_VITERBI_DEPRF 0xF23E0020 +#define F367_OFDM_PRFVIT 0xF23E0010 +#define F367_OFDM_LOCKEDVIT 0xF23E0008 +#define F367_OFDM_VITERBI_DELOCK 0xF23E0004 +#define F367_OFDM_VIT_DEMODSEL 0xF23E0002 +#define F367_OFDM_VITERBI_COMPOUT 0xF23E0001 + +/* VTHINUSE */ +#define R367_OFDM_VTHINUSE 0xF23F +#define F367_OFDM_VIT_INUSE 0xF23F00FF + +/* KDIV12 */ +#define R367_OFDM_KDIV12 0xF240 +#define F367_OFDM_KDIV12_MANUAL 0xF2400080 +#define F367_OFDM_K_DIVIDER_12 0xF240007F + +/* KDIV23 */ +#define R367_OFDM_KDIV23 0xF241 +#define F367_OFDM_KDIV23_MANUAL 0xF2410080 +#define F367_OFDM_K_DIVIDER_23 0xF241007F + +/* KDIV34 */ +#define R367_OFDM_KDIV34 0xF242 +#define F367_OFDM_KDIV34_MANUAL 0xF2420080 +#define F367_OFDM_K_DIVIDER_34 0xF242007F + +/* KDIV56 */ +#define R367_OFDM_KDIV56 0xF243 +#define F367_OFDM_KDIV56_MANUAL 0xF2430080 +#define F367_OFDM_K_DIVIDER_56 0xF243007F + +/* KDIV67 */ +#define R367_OFDM_KDIV67 0xF244 +#define F367_OFDM_KDIV67_MANUAL 0xF2440080 +#define F367_OFDM_K_DIVIDER_67 0xF244007F + +/* KDIV78 */ +#define R367_OFDM_KDIV78 0xF245 +#define F367_OFDM_KDIV78_MANUAL 0xF2450080 +#define F367_OFDM_K_DIVIDER_78 0xF245007F + +/* SIGPOWER */ +#define R367_OFDM_SIGPOWER 0xF246 +#define F367_OFDM_SIGPOWER_MANUAL 0xF2460080 +#define F367_OFDM_SIG_POWER 0xF246007F + +/* DEMAPVIT */ +#define R367_OFDM_DEMAPVIT 0xF247 +#define F367_OFDM_DEMAPVIT_7 0xF2470080 +#define F367_OFDM_K_DIVIDER_VIT 0xF247007F + +/* VITSCALE */ +#define R367_OFDM_VITSCALE 0xF248 +#define F367_OFDM_NVTH_NOSRANGE 0xF2480080 +#define F367_OFDM_VERROR_MAXMODE 0xF2480040 +#define F367_OFDM_KDIV_MODE 0xF2480030 +#define F367_OFDM_NSLOWSN_LOCKED 0xF2480008 +#define F367_OFDM_DELOCK_PRFLOSS 0xF2480004 +#define F367_OFDM_DIS_RSFLOCK 0xF2480002 +#define F367_OFDM_VITSCALE_0 0xF2480001 + +/* FFEC1PRG */ +#define R367_OFDM_FFEC1PRG 0xF249 +#define F367_OFDM_FDSS_DVB 0xF2490080 +#define F367_OFDM_FDSS_SRCH 0xF2490040 +#define F367_OFDM_FFECPROG_5 0xF2490020 +#define F367_OFDM_FFECPROG_4 0xF2490010 +#define F367_OFDM_FFECPROG_3 0xF2490008 +#define F367_OFDM_FFECPROG_2 0xF2490004 +#define F367_OFDM_FTS1_DISABLE 0xF2490002 +#define F367_OFDM_FTS2_DISABLE 0xF2490001 + +/* FVITCURPUN */ +#define R367_OFDM_FVITCURPUN 0xF24A +#define F367_OFDM_FVIT_MAPPING 0xF24A00E0 +#define F367_OFDM_FVIT_CURPUN 0xF24A001F + +/* FVERROR */ +#define R367_OFDM_FVERROR 0xF24B +#define F367_OFDM_FREGERR_VIT 0xF24B00FF + +/* FVSTATUSVIT */ +#define R367_OFDM_FVSTATUSVIT 0xF24C +#define F367_OFDM_FVITERBI_ON 0xF24C0080 +#define F367_OFDM_F1END_LOOPVIT 0xF24C0040 +#define F367_OFDM_FVITERBI_DEPRF 0xF24C0020 +#define F367_OFDM_FPRFVIT 0xF24C0010 +#define F367_OFDM_FLOCKEDVIT 0xF24C0008 +#define F367_OFDM_FVITERBI_DELOCK 0xF24C0004 +#define F367_OFDM_FVIT_DEMODSEL 0xF24C0002 +#define F367_OFDM_FVITERBI_COMPOUT 0xF24C0001 + +/* DEBUG_LT1 */ +#define R367_OFDM_DEBUG_LT1 0xF24D +#define F367_OFDM_DBG_LT1 0xF24D00FF + +/* DEBUG_LT2 */ +#define R367_OFDM_DEBUG_LT2 0xF24E +#define F367_OFDM_DBG_LT2 0xF24E00FF + +/* DEBUG_LT3 */ +#define R367_OFDM_DEBUG_LT3 0xF24F +#define F367_OFDM_DBG_LT3 0xF24F00FF + + /* TSTSFMET */ +#define R367_OFDM_TSTSFMET 0xF250 +#define F367_OFDM_TSTSFEC_METRIQUES 0xF25000FF + + /* SELOUT */ +#define R367_OFDM_SELOUT 0xF252 +#define F367_OFDM_EN_SYNC 0xF2520080 +#define F367_OFDM_EN_TBUSDEMAP 0xF2520040 +#define F367_OFDM_SELOUT_5 0xF2520020 +#define F367_OFDM_SELOUT_4 0xF2520010 +#define F367_OFDM_TSTSYNCHRO_MODE 0xF2520002 + + /* TSYNC */ +#define R367_OFDM_TSYNC 0xF253 +#define F367_OFDM_CURPUN_INCMODE 0xF2530080 +#define F367_OFDM_CERR_TSTMODE 0xF2530040 +#define F367_OFDM_SHIFTSOF_MODE 0xF2530030 +#define F367_OFDM_SLOWPHA_MODE 0xF2530008 +#define F367_OFDM_PXX_BYPALL 0xF2530004 +#define F367_OFDM_FROTA45_FIRST 0xF2530002 +#define F367_OFDM_TST_BCHERROR 0xF2530001 + + /* TSTERR */ +#define R367_OFDM_TSTERR 0xF254 +#define F367_OFDM_TST_LONGPKT 0xF2540080 +#define F367_OFDM_TST_ISSYION 0xF2540040 +#define F367_OFDM_TST_NPDON 0xF2540020 +#define F367_OFDM_TSTERR_4 0xF2540010 +#define F367_OFDM_TRACEBACK_MODE 0xF2540008 +#define F367_OFDM_TST_RSPARITY 0xF2540004 +#define F367_OFDM_METRIQUE_MODE 0xF2540003 + + /* TSFSYNC */ +#define R367_OFDM_TSFSYNC 0xF255 +#define F367_OFDM_EN_SFECSYNC 0xF2550080 +#define F367_OFDM_EN_SFECDEMAP 0xF2550040 +#define F367_OFDM_SFCERR_TSTMODE 0xF2550020 +#define F367_OFDM_SFECPXX_BYPALL 0xF2550010 +#define F367_OFDM_SFECTSTSYNCHRO_MODE 0xF255000F + + /* TSTSFERR */ +#define R367_OFDM_TSTSFERR 0xF256 +#define F367_OFDM_TSTSTERR_7 0xF2560080 +#define F367_OFDM_TSTSTERR_6 0xF2560040 +#define F367_OFDM_TSTSTERR_5 0xF2560020 +#define F367_OFDM_TSTSTERR_4 0xF2560010 +#define F367_OFDM_SFECTRACEBACK_MODE 0xF2560008 +#define F367_OFDM_SFEC_NCONVPROG 0xF2560004 +#define F367_OFDM_SFECMETRIQUE_MODE 0xF2560003 + + /* TSTTSSF1 */ +#define R367_OFDM_TSTTSSF1 0xF258 +#define F367_OFDM_TSTERSSF 0xF2580080 +#define F367_OFDM_TSTTSSFEN 0xF2580040 +#define F367_OFDM_SFEC_OUTMODE 0xF2580030 +#define F367_OFDM_XLSF_NOFTHRESHOLD 0xF2580008 +#define F367_OFDM_TSTTSSF_STACKSEL 0xF2580007 + + /* TSTTSSF2 */ +#define R367_OFDM_TSTTSSF2 0xF259 +#define F367_OFDM_DILSF_DBBHEADER 0xF2590080 +#define F367_OFDM_TSTTSSF_DISBUG 0xF2590040 +#define F367_OFDM_TSTTSSF_NOBADSTART 0xF2590020 +#define F367_OFDM_TSTTSSF_SELECT 0xF259001F + + /* TSTTSSF3 */ +#define R367_OFDM_TSTTSSF3 0xF25A +#define F367_OFDM_TSTTSSF3_7 0xF25A0080 +#define F367_OFDM_TSTTSSF3_6 0xF25A0040 +#define F367_OFDM_TSTTSSF3_5 0xF25A0020 +#define F367_OFDM_TSTTSSF3_4 0xF25A0010 +#define F367_OFDM_TSTTSSF3_3 0xF25A0008 +#define F367_OFDM_TSTTSSF3_2 0xF25A0004 +#define F367_OFDM_TSTTSSF3_1 0xF25A0002 +#define F367_OFDM_DISSF_CLKENABLE 0xF25A0001 + + /* TSTTS1 */ +#define R367_OFDM_TSTTS1 0xF25C +#define F367_OFDM_TSTERS 0xF25C0080 +#define F367_OFDM_TSFIFO_DSSSYNCB 0xF25C0040 +#define F367_OFDM_TSTTS_FSPYBEFRS 0xF25C0020 +#define F367_OFDM_NFORCE_SYNCBYTE 0xF25C0010 +#define F367_OFDM_XL_NOFTHRESHOLD 0xF25C0008 +#define F367_OFDM_TSTTS_FRFORCEPKT 0xF25C0004 +#define F367_OFDM_DESCR_NOTAUTO 0xF25C0002 +#define F367_OFDM_TSTTSEN 0xF25C0001 + + /* TSTTS2 */ +#define R367_OFDM_TSTTS2 0xF25D +#define F367_OFDM_DIL_DBBHEADER 0xF25D0080 +#define F367_OFDM_TSTTS_NOBADXXX 0xF25D0040 +#define F367_OFDM_TSFIFO_DELSPEEDUP 0xF25D0020 +#define F367_OFDM_TSTTS_SELECT 0xF25D001F + + /* TSTTS3 */ +#define R367_OFDM_TSTTS3 0xF25E +#define F367_OFDM_TSTTS_NOPKTGAIN 0xF25E0080 +#define F367_OFDM_TSTTS_NOPKTENE 0xF25E0040 +#define F367_OFDM_TSTTS_ISOLATION 0xF25E0020 +#define F367_OFDM_TSTTS_DISBUG 0xF25E0010 +#define F367_OFDM_TSTTS_NOBADSTART 0xF25E0008 +#define F367_OFDM_TSTTS_STACKSEL 0xF25E0007 + + /* TSTTS4 */ +#define R367_OFDM_TSTTS4 0xF25F +#define F367_OFDM_TSTTS4_7 0xF25F0080 +#define F367_OFDM_TSTTS4_6 0xF25F0040 +#define F367_OFDM_TSTTS4_5 0xF25F0020 +#define F367_OFDM_TSTTS_DISDSTATE 0xF25F0010 +#define F367_OFDM_TSTTS_FASTNOSYNC 0xF25F0008 +#define F367_OFDM_EXT_FECSPYIN 0xF25F0004 +#define F367_OFDM_TSTTS_NODPZERO 0xF25F0002 +#define F367_OFDM_TSTTS_NODIV3 0xF25F0001 + + /* TSTTSRC */ +#define R367_OFDM_TSTTSRC 0xF26C +#define F367_OFDM_TSTTSRC_7 0xF26C0080 +#define F367_OFDM_TSRCFIFO_DSSSYNCB 0xF26C0040 +#define F367_OFDM_TSRCFIFO_DPUNACTIVE 0xF26C0020 +#define F367_OFDM_TSRCFIFO_DELSPEEDUP 0xF26C0010 +#define F367_OFDM_TSTTSRC_NODIV3 0xF26C0008 +#define F367_OFDM_TSTTSRC_FRFORCEPKT 0xF26C0004 +#define F367_OFDM_SAT25_SDDORIGINE 0xF26C0002 +#define F367_OFDM_TSTTSRC_INACTIVE 0xF26C0001 + + /* TSTTSRS */ +#define R367_OFDM_TSTTSRS 0xF26D +#define F367_OFDM_TSTTSRS_7 0xF26D0080 +#define F367_OFDM_TSTTSRS_6 0xF26D0040 +#define F367_OFDM_TSTTSRS_5 0xF26D0020 +#define F367_OFDM_TSTTSRS_4 0xF26D0010 +#define F367_OFDM_TSTTSRS_3 0xF26D0008 +#define F367_OFDM_TSTTSRS_2 0xF26D0004 +#define F367_OFDM_TSTRS_DISRS2 0xF26D0002 +#define F367_OFDM_TSTRS_DISRS1 0xF26D0001 + +/* TSSTATEM */ +#define R367_OFDM_TSSTATEM 0xF270 +#define F367_OFDM_TSDIL_ON 0xF2700080 +#define F367_OFDM_TSSKIPRS_ON 0xF2700040 +#define F367_OFDM_TSRS_ON 0xF2700020 +#define F367_OFDM_TSDESCRAMB_ON 0xF2700010 +#define F367_OFDM_TSFRAME_MODE 0xF2700008 +#define F367_OFDM_TS_DISABLE 0xF2700004 +#define F367_OFDM_TSACM_MODE 0xF2700002 +#define F367_OFDM_TSOUT_NOSYNC 0xF2700001 + +/* TSSTATEL */ +#define R367_OFDM_TSSTATEL 0xF271 +#define F367_OFDM_TSNOSYNCBYTE 0xF2710080 +#define F367_OFDM_TSPARITY_ON 0xF2710040 +#define F367_OFDM_TSSYNCOUTRS_ON 0xF2710020 +#define F367_OFDM_TSDVBS2_MODE 0xF2710010 +#define F367_OFDM_TSISSYI_ON 0xF2710008 +#define F367_OFDM_TSNPD_ON 0xF2710004 +#define F367_OFDM_TSCRC8_ON 0xF2710002 +#define F367_OFDM_TSDSS_PACKET 0xF2710001 + +/* TSCFGH */ +#define R367_OFDM_TSCFGH 0xF272 +#define F367_OFDM_TSFIFO_DVBCI 0xF2720080 +#define F367_OFDM_TSFIFO_SERIAL 0xF2720040 +#define F367_OFDM_TSFIFO_TEIUPDATE 0xF2720020 +#define F367_OFDM_TSFIFO_DUTY50 0xF2720010 +#define F367_OFDM_TSFIFO_HSGNLOUT 0xF2720008 +#define F367_OFDM_TSFIFO_ERRMODE 0xF2720006 +#define F367_OFDM_RST_HWARE 0xF2720001 + +/* TSCFGM */ +#define R367_OFDM_TSCFGM 0xF273 +#define F367_OFDM_TSFIFO_MANSPEED 0xF27300C0 +#define F367_OFDM_TSFIFO_PERMDATA 0xF2730020 +#define F367_OFDM_TSFIFO_NONEWSGNL 0xF2730010 +#define F367_OFDM_TSFIFO_BITSPEED 0xF2730008 +#define F367_OFDM_NPD_SPECDVBS2 0xF2730004 +#define F367_OFDM_TSFIFO_STOPCKDIS 0xF2730002 +#define F367_OFDM_TSFIFO_INVDATA 0xF2730001 + +/* TSCFGL */ +#define R367_OFDM_TSCFGL 0xF274 +#define F367_OFDM_TSFIFO_BCLKDEL1CK 0xF27400C0 +#define F367_OFDM_BCHERROR_MODE 0xF2740030 +#define F367_OFDM_TSFIFO_NSGNL2DATA 0xF2740008 +#define F367_OFDM_TSFIFO_EMBINDVB 0xF2740004 +#define F367_OFDM_TSFIFO_DPUNACT 0xF2740002 +#define F367_OFDM_TSFIFO_NPDOFF 0xF2740001 + +/* TSSYNC */ +#define R367_OFDM_TSSYNC 0xF275 +#define F367_OFDM_TSFIFO_PERMUTE 0xF2750080 +#define F367_OFDM_TSFIFO_FISCR3B 0xF2750060 +#define F367_OFDM_TSFIFO_SYNCMODE 0xF2750018 +#define F367_OFDM_TSFIFO_SYNCSEL 0xF2750007 + +/* TSINSDELH */ +#define R367_OFDM_TSINSDELH 0xF276 +#define F367_OFDM_TSDEL_SYNCBYTE 0xF2760080 +#define F367_OFDM_TSDEL_XXHEADER 0xF2760040 +#define F367_OFDM_TSDEL_BBHEADER 0xF2760020 +#define F367_OFDM_TSDEL_DATAFIELD 0xF2760010 +#define F367_OFDM_TSINSDEL_ISCR 0xF2760008 +#define F367_OFDM_TSINSDEL_NPD 0xF2760004 +#define F367_OFDM_TSINSDEL_RSPARITY 0xF2760002 +#define F367_OFDM_TSINSDEL_CRC8 0xF2760001 + +/* TSINSDELM */ +#define R367_OFDM_TSINSDELM 0xF277 +#define F367_OFDM_TSINS_BBPADDING 0xF2770080 +#define F367_OFDM_TSINS_BCHFEC 0xF2770040 +#define F367_OFDM_TSINS_LDPCFEC 0xF2770020 +#define F367_OFDM_TSINS_EMODCOD 0xF2770010 +#define F367_OFDM_TSINS_TOKEN 0xF2770008 +#define F367_OFDM_TSINS_XXXERR 0xF2770004 +#define F367_OFDM_TSINS_MATYPE 0xF2770002 +#define F367_OFDM_TSINS_UPL 0xF2770001 + +/* TSINSDELL */ +#define R367_OFDM_TSINSDELL 0xF278 +#define F367_OFDM_TSINS_DFL 0xF2780080 +#define F367_OFDM_TSINS_SYNCD 0xF2780040 +#define F367_OFDM_TSINS_BLOCLEN 0xF2780020 +#define F367_OFDM_TSINS_SIGPCOUNT 0xF2780010 +#define F367_OFDM_TSINS_FIFO 0xF2780008 +#define F367_OFDM_TSINS_REALPACK 0xF2780004 +#define F367_OFDM_TSINS_TSCONFIG 0xF2780002 +#define F367_OFDM_TSINS_LATENCY 0xF2780001 + +/* TSDIVN */ +#define R367_OFDM_TSDIVN 0xF279 +#define F367_OFDM_TSFIFO_LOWSPEED 0xF2790080 +#define F367_OFDM_BYTE_OVERSAMPLING 0xF2790070 +#define F367_OFDM_TSMANUAL_PACKETNBR 0xF279000F + +/* TSDIVPM */ +#define R367_OFDM_TSDIVPM 0xF27A +#define F367_OFDM_TSMANUAL_P_HI 0xF27A00FF + +/* TSDIVPL */ +#define R367_OFDM_TSDIVPL 0xF27B +#define F367_OFDM_TSMANUAL_P_LO 0xF27B00FF + +/* TSDIVQM */ +#define R367_OFDM_TSDIVQM 0xF27C +#define F367_OFDM_TSMANUAL_Q_HI 0xF27C00FF + +/* TSDIVQL */ +#define R367_OFDM_TSDIVQL 0xF27D +#define F367_OFDM_TSMANUAL_Q_LO 0xF27D00FF + +/* TSDILSTKM */ +#define R367_OFDM_TSDILSTKM 0xF27E +#define F367_OFDM_TSFIFO_DILSTK_HI 0xF27E00FF + +/* TSDILSTKL */ +#define R367_OFDM_TSDILSTKL 0xF27F +#define F367_OFDM_TSFIFO_DILSTK_LO 0xF27F00FF + +/* TSSPEED */ +#define R367_OFDM_TSSPEED 0xF280 +#define F367_OFDM_TSFIFO_OUTSPEED 0xF28000FF + +/* TSSTATUS */ +#define R367_OFDM_TSSTATUS 0xF281 +#define F367_OFDM_TSFIFO_LINEOK 0xF2810080 +#define F367_OFDM_TSFIFO_ERROR 0xF2810040 +#define F367_OFDM_TSFIFO_DATA7 0xF2810020 +#define F367_OFDM_TSFIFO_NOSYNC 0xF2810010 +#define F367_OFDM_ISCR_INITIALIZED 0xF2810008 +#define F367_OFDM_ISCR_UPDATED 0xF2810004 +#define F367_OFDM_SOFFIFO_UNREGUL 0xF2810002 +#define F367_OFDM_DIL_READY 0xF2810001 + +/* TSSTATUS2 */ +#define R367_OFDM_TSSTATUS2 0xF282 +#define F367_OFDM_TSFIFO_DEMODSEL 0xF2820080 +#define F367_OFDM_TSFIFOSPEED_STORE 0xF2820040 +#define F367_OFDM_DILXX_RESET 0xF2820020 +#define F367_OFDM_TSSERIAL_IMPOSSIBLE 0xF2820010 +#define F367_OFDM_TSFIFO_UNDERSPEED 0xF2820008 +#define F367_OFDM_BITSPEED_EVENT 0xF2820004 +#define F367_OFDM_UL_SCRAMBDETECT 0xF2820002 +#define F367_OFDM_ULDTV67_FALSELOCK 0xF2820001 + +/* TSBITRATEM */ +#define R367_OFDM_TSBITRATEM 0xF283 +#define F367_OFDM_TSFIFO_BITRATE_HI 0xF28300FF + +/* TSBITRATEL */ +#define R367_OFDM_TSBITRATEL 0xF284 +#define F367_OFDM_TSFIFO_BITRATE_LO 0xF28400FF + +/* TSPACKLENM */ +#define R367_OFDM_TSPACKLENM 0xF285 +#define F367_OFDM_TSFIFO_PACKCPT 0xF28500E0 +#define F367_OFDM_DIL_RPLEN_HI 0xF285001F + +/* TSPACKLENL */ +#define R367_OFDM_TSPACKLENL 0xF286 +#define F367_OFDM_DIL_RPLEN_LO 0xF28600FF + +/* TSBLOCLENM */ +#define R367_OFDM_TSBLOCLENM 0xF287 +#define F367_OFDM_TSFIFO_PFLEN_HI 0xF28700FF + +/* TSBLOCLENL */ +#define R367_OFDM_TSBLOCLENL 0xF288 +#define F367_OFDM_TSFIFO_PFLEN_LO 0xF28800FF + +/* TSDLYH */ +#define R367_OFDM_TSDLYH 0xF289 +#define F367_OFDM_SOFFIFO_TSTIMEVALID 0xF2890080 +#define F367_OFDM_SOFFIFO_SPEEDUP 0xF2890040 +#define F367_OFDM_SOFFIFO_STOP 0xF2890020 +#define F367_OFDM_SOFFIFO_REGULATED 0xF2890010 +#define F367_OFDM_SOFFIFO_REALSBOFF_HI 0xF289000F + +/* TSDLYM */ +#define R367_OFDM_TSDLYM 0xF28A +#define F367_OFDM_SOFFIFO_REALSBOFF_MED 0xF28A00FF + +/* TSDLYL */ +#define R367_OFDM_TSDLYL 0xF28B +#define F367_OFDM_SOFFIFO_REALSBOFF_LO 0xF28B00FF + +/* TSNPDAV */ +#define R367_OFDM_TSNPDAV 0xF28C +#define F367_OFDM_TSNPD_AVERAGE 0xF28C00FF + +/* TSBUFSTATH */ +#define R367_OFDM_TSBUFSTATH 0xF28D +#define F367_OFDM_TSISCR_3BYTES 0xF28D0080 +#define F367_OFDM_TSISCR_NEWDATA 0xF28D0040 +#define F367_OFDM_TSISCR_BUFSTAT_HI 0xF28D003F + +/* TSBUFSTATM */ +#define R367_OFDM_TSBUFSTATM 0xF28E +#define F367_OFDM_TSISCR_BUFSTAT_MED 0xF28E00FF + +/* TSBUFSTATL */ +#define R367_OFDM_TSBUFSTATL 0xF28F +#define F367_OFDM_TSISCR_BUFSTAT_LO 0xF28F00FF + +/* TSDEBUGM */ +#define R367_OFDM_TSDEBUGM 0xF290 +#define F367_OFDM_TSFIFO_ILLPACKET 0xF2900080 +#define F367_OFDM_DIL_NOSYNC 0xF2900040 +#define F367_OFDM_DIL_ISCR 0xF2900020 +#define F367_OFDM_DILOUT_BSYNCB 0xF2900010 +#define F367_OFDM_TSFIFO_EMPTYPKT 0xF2900008 +#define F367_OFDM_TSFIFO_EMPTYRD 0xF2900004 +#define F367_OFDM_SOFFIFO_STOPM 0xF2900002 +#define F367_OFDM_SOFFIFO_SPEEDUPM 0xF2900001 + +/* TSDEBUGL */ +#define R367_OFDM_TSDEBUGL 0xF291 +#define F367_OFDM_TSFIFO_PACKLENFAIL 0xF2910080 +#define F367_OFDM_TSFIFO_SYNCBFAIL 0xF2910040 +#define F367_OFDM_TSFIFO_VITLIBRE 0xF2910020 +#define F367_OFDM_TSFIFO_BOOSTSPEEDM 0xF2910010 +#define F367_OFDM_TSFIFO_UNDERSPEEDM 0xF2910008 +#define F367_OFDM_TSFIFO_ERROR_EVNT 0xF2910004 +#define F367_OFDM_TSFIFO_FULL 0xF2910002 +#define F367_OFDM_TSFIFO_OVERFLOWM 0xF2910001 + +/* TSDLYSETH */ +#define R367_OFDM_TSDLYSETH 0xF292 +#define F367_OFDM_SOFFIFO_OFFSET 0xF29200E0 +#define F367_OFDM_SOFFIFO_SYMBOFFSET_HI 0xF292001F + +/* TSDLYSETM */ +#define R367_OFDM_TSDLYSETM 0xF293 +#define F367_OFDM_SOFFIFO_SYMBOFFSET_MED 0xF29300FF + +/* TSDLYSETL */ +#define R367_OFDM_TSDLYSETL 0xF294 +#define F367_OFDM_SOFFIFO_SYMBOFFSET_LO 0xF29400FF + +/* TSOBSCFG */ +#define R367_OFDM_TSOBSCFG 0xF295 +#define F367_OFDM_TSFIFO_OBSCFG 0xF29500FF + +/* TSOBSM */ +#define R367_OFDM_TSOBSM 0xF296 +#define F367_OFDM_TSFIFO_OBSDATA_HI 0xF29600FF + +/* TSOBSL */ +#define R367_OFDM_TSOBSL 0xF297 +#define F367_OFDM_TSFIFO_OBSDATA_LO 0xF29700FF + +/* ERRCTRL1 */ +#define R367_OFDM_ERRCTRL1 0xF298 +#define F367_OFDM_ERR_SRC1 0xF29800F0 +#define F367_OFDM_ERRCTRL1_3 0xF2980008 +#define F367_OFDM_NUM_EVT1 0xF2980007 + +/* ERRCNT1H */ +#define R367_OFDM_ERRCNT1H 0xF299 +#define F367_OFDM_ERRCNT1_OLDVALUE 0xF2990080 +#define F367_OFDM_ERR_CNT1 0xF299007F + +/* ERRCNT1M */ +#define R367_OFDM_ERRCNT1M 0xF29A +#define F367_OFDM_ERR_CNT1_HI 0xF29A00FF + +/* ERRCNT1L */ +#define R367_OFDM_ERRCNT1L 0xF29B +#define F367_OFDM_ERR_CNT1_LO 0xF29B00FF + +/* ERRCTRL2 */ +#define R367_OFDM_ERRCTRL2 0xF29C +#define F367_OFDM_ERR_SRC2 0xF29C00F0 +#define F367_OFDM_ERRCTRL2_3 0xF29C0008 +#define F367_OFDM_NUM_EVT2 0xF29C0007 + +/* ERRCNT2H */ +#define R367_OFDM_ERRCNT2H 0xF29D +#define F367_OFDM_ERRCNT2_OLDVALUE 0xF29D0080 +#define F367_OFDM_ERR_CNT2_HI 0xF29D007F + +/* ERRCNT2M */ +#define R367_OFDM_ERRCNT2M 0xF29E +#define F367_OFDM_ERR_CNT2_MED 0xF29E00FF + +/* ERRCNT2L */ +#define R367_OFDM_ERRCNT2L 0xF29F +#define F367_OFDM_ERR_CNT2_LO 0xF29F00FF + +/* FECSPY */ +#define R367_OFDM_FECSPY 0xF2A0 +#define F367_OFDM_SPY_ENABLE 0xF2A00080 +#define F367_OFDM_NO_SYNCBYTE 0xF2A00040 +#define F367_OFDM_SERIAL_MODE 0xF2A00020 +#define F367_OFDM_UNUSUAL_PACKET 0xF2A00010 +#define F367_OFDM_BERMETER_DATAMODE 0xF2A0000C +#define F367_OFDM_BERMETER_LMODE 0xF2A00002 +#define F367_OFDM_BERMETER_RESET 0xF2A00001 + +/* FSPYCFG */ +#define R367_OFDM_FSPYCFG 0xF2A1 +#define F367_OFDM_FECSPY_INPUT 0xF2A100C0 +#define F367_OFDM_RST_ON_ERROR 0xF2A10020 +#define F367_OFDM_ONE_SHOT 0xF2A10010 +#define F367_OFDM_I2C_MOD 0xF2A1000C +#define F367_OFDM_SPY_HYSTERESIS 0xF2A10003 + +/* FSPYDATA */ +#define R367_OFDM_FSPYDATA 0xF2A2 +#define F367_OFDM_SPY_STUFFING 0xF2A20080 +#define F367_OFDM_NOERROR_PKTJITTER 0xF2A20040 +#define F367_OFDM_SPY_CNULLPKT 0xF2A20020 +#define F367_OFDM_SPY_OUTDATA_MODE 0xF2A2001F + +/* FSPYOUT */ +#define R367_OFDM_FSPYOUT 0xF2A3 +#define F367_OFDM_FSPY_DIRECT 0xF2A30080 +#define F367_OFDM_FSPYOUT_6 0xF2A30040 +#define F367_OFDM_SPY_OUTDATA_BUS 0xF2A30038 +#define F367_OFDM_STUFF_MODE 0xF2A30007 + +/* FSTATUS */ +#define R367_OFDM_FSTATUS 0xF2A4 +#define F367_OFDM_SPY_ENDSIM 0xF2A40080 +#define F367_OFDM_VALID_SIM 0xF2A40040 +#define F367_OFDM_FOUND_SIGNAL 0xF2A40020 +#define F367_OFDM_DSS_SYNCBYTE 0xF2A40010 +#define F367_OFDM_RESULT_STATE 0xF2A4000F + +/* FGOODPACK */ +#define R367_OFDM_FGOODPACK 0xF2A5 +#define F367_OFDM_FGOOD_PACKET 0xF2A500FF + +/* FPACKCNT */ +#define R367_OFDM_FPACKCNT 0xF2A6 +#define F367_OFDM_FPACKET_COUNTER 0xF2A600FF + +/* FSPYMISC */ +#define R367_OFDM_FSPYMISC 0xF2A7 +#define F367_OFDM_FLABEL_COUNTER 0xF2A700FF + +/* FBERCPT4 */ +#define R367_OFDM_FBERCPT4 0xF2A8 +#define F367_OFDM_FBERMETER_CPT5 0xF2A800FF + +/* FBERCPT3 */ +#define R367_OFDM_FBERCPT3 0xF2A9 +#define F367_OFDM_FBERMETER_CPT4 0xF2A900FF + +/* FBERCPT2 */ +#define R367_OFDM_FBERCPT2 0xF2AA +#define F367_OFDM_FBERMETER_CPT3 0xF2AA00FF + +/* FBERCPT1 */ +#define R367_OFDM_FBERCPT1 0xF2AB +#define F367_OFDM_FBERMETER_CPT2 0xF2AB00FF + +/* FBERCPT0 */ +#define R367_OFDM_FBERCPT0 0xF2AC +#define F367_OFDM_FBERMETER_CPT1 0xF2AC00FF + +/* FBERERR2 */ +#define R367_OFDM_FBERERR2 0xF2AD +#define F367_OFDM_FBERMETER_ERR_HI 0xF2AD00FF + +/* FBERERR1 */ +#define R367_OFDM_FBERERR1 0xF2AE +#define F367_OFDM_FBERMETER_ERR_MED 0xF2AE00FF + +/* FBERERR0 */ +#define R367_OFDM_FBERERR0 0xF2AF +#define F367_OFDM_FBERMETER_ERR_LO 0xF2AF00FF + +/* FSTATESM */ +#define R367_OFDM_FSTATESM 0xF2B0 +#define F367_OFDM_RSTATE_F 0xF2B00080 +#define F367_OFDM_RSTATE_E 0xF2B00040 +#define F367_OFDM_RSTATE_D 0xF2B00020 +#define F367_OFDM_RSTATE_C 0xF2B00010 +#define F367_OFDM_RSTATE_B 0xF2B00008 +#define F367_OFDM_RSTATE_A 0xF2B00004 +#define F367_OFDM_RSTATE_9 0xF2B00002 +#define F367_OFDM_RSTATE_8 0xF2B00001 + +/* FSTATESL */ +#define R367_OFDM_FSTATESL 0xF2B1 +#define F367_OFDM_RSTATE_7 0xF2B10080 +#define F367_OFDM_RSTATE_6 0xF2B10040 +#define F367_OFDM_RSTATE_5 0xF2B10020 +#define F367_OFDM_RSTATE_4 0xF2B10010 +#define F367_OFDM_RSTATE_3 0xF2B10008 +#define F367_OFDM_RSTATE_2 0xF2B10004 +#define F367_OFDM_RSTATE_1 0xF2B10002 +#define F367_OFDM_RSTATE_0 0xF2B10001 + +/* FSPYBER */ +#define R367_OFDM_FSPYBER 0xF2B2 +#define F367_OFDM_FSPYBER_7 0xF2B20080 +#define F367_OFDM_FSPYOBS_XORREAD 0xF2B20040 +#define F367_OFDM_FSPYBER_OBSMODE 0xF2B20020 +#define F367_OFDM_FSPYBER_SYNCBYTE 0xF2B20010 +#define F367_OFDM_FSPYBER_UNSYNC 0xF2B20008 +#define F367_OFDM_FSPYBER_CTIME 0xF2B20007 + +/* FSPYDISTM */ +#define R367_OFDM_FSPYDISTM 0xF2B3 +#define F367_OFDM_PKTTIME_DISTANCE_HI 0xF2B300FF + +/* FSPYDISTL */ +#define R367_OFDM_FSPYDISTL 0xF2B4 +#define F367_OFDM_PKTTIME_DISTANCE_LO 0xF2B400FF + +/* FSPYOBS7 */ +#define R367_OFDM_FSPYOBS7 0xF2B8 +#define F367_OFDM_FSPYOBS_SPYFAIL 0xF2B80080 +#define F367_OFDM_FSPYOBS_SPYFAIL1 0xF2B80040 +#define F367_OFDM_FSPYOBS_ERROR 0xF2B80020 +#define F367_OFDM_FSPYOBS_STROUT 0xF2B80010 +#define F367_OFDM_FSPYOBS_RESULTSTATE1 0xF2B8000F + +/* FSPYOBS6 */ +#define R367_OFDM_FSPYOBS6 0xF2B9 +#define F367_OFDM_FSPYOBS_RESULTSTATE0 0xF2B900F0 +#define F367_OFDM_FSPYOBS_RESULTSTATEM1 0xF2B9000F + +/* FSPYOBS5 */ +#define R367_OFDM_FSPYOBS5 0xF2BA +#define F367_OFDM_FSPYOBS_BYTEOFPACKET1 0xF2BA00FF + +/* FSPYOBS4 */ +#define R367_OFDM_FSPYOBS4 0xF2BB +#define F367_OFDM_FSPYOBS_BYTEVALUE1 0xF2BB00FF + +/* FSPYOBS3 */ +#define R367_OFDM_FSPYOBS3 0xF2BC +#define F367_OFDM_FSPYOBS_DATA1 0xF2BC00FF + +/* FSPYOBS2 */ +#define R367_OFDM_FSPYOBS2 0xF2BD +#define F367_OFDM_FSPYOBS_DATA0 0xF2BD00FF + +/* FSPYOBS1 */ +#define R367_OFDM_FSPYOBS1 0xF2BE +#define F367_OFDM_FSPYOBS_DATAM1 0xF2BE00FF + +/* FSPYOBS0 */ +#define R367_OFDM_FSPYOBS0 0xF2BF +#define F367_OFDM_FSPYOBS_DATAM2 0xF2BF00FF + +/* SFDEMAP */ +#define R367_OFDM_SFDEMAP 0xF2C0 +#define F367_OFDM_SFDEMAP_7 0xF2C00080 +#define F367_OFDM_SFEC_K_DIVIDER_VIT 0xF2C0007F + +/* SFERROR */ +#define R367_OFDM_SFERROR 0xF2C1 +#define F367_OFDM_SFEC_REGERR_VIT 0xF2C100FF + +/* SFAVSR */ +#define R367_OFDM_SFAVSR 0xF2C2 +#define F367_OFDM_SFEC_SUMERRORS 0xF2C20080 +#define F367_OFDM_SERROR_MAXMODE 0xF2C20040 +#define F367_OFDM_SN_SFEC 0xF2C20030 +#define F367_OFDM_KDIV_MODE_SFEC 0xF2C2000C +#define F367_OFDM_SFAVSR_1 0xF2C20002 +#define F367_OFDM_SFAVSR_0 0xF2C20001 + +/* SFECSTATUS */ +#define R367_OFDM_SFECSTATUS 0xF2C3 +#define F367_OFDM_SFEC_ON 0xF2C30080 +#define F367_OFDM_SFSTATUS_6 0xF2C30040 +#define F367_OFDM_SFSTATUS_5 0xF2C30020 +#define F367_OFDM_SFSTATUS_4 0xF2C30010 +#define F367_OFDM_LOCKEDSFEC 0xF2C30008 +#define F367_OFDM_SFEC_DELOCK 0xF2C30004 +#define F367_OFDM_SFEC_DEMODSEL1 0xF2C30002 +#define F367_OFDM_SFEC_OVFON 0xF2C30001 + +/* SFKDIV12 */ +#define R367_OFDM_SFKDIV12 0xF2C4 +#define F367_OFDM_SFECKDIV12_MAN 0xF2C40080 +#define F367_OFDM_SFEC_K_DIVIDER_12 0xF2C4007F + +/* SFKDIV23 */ +#define R367_OFDM_SFKDIV23 0xF2C5 +#define F367_OFDM_SFECKDIV23_MAN 0xF2C50080 +#define F367_OFDM_SFEC_K_DIVIDER_23 0xF2C5007F + +/* SFKDIV34 */ +#define R367_OFDM_SFKDIV34 0xF2C6 +#define F367_OFDM_SFECKDIV34_MAN 0xF2C60080 +#define F367_OFDM_SFEC_K_DIVIDER_34 0xF2C6007F + +/* SFKDIV56 */ +#define R367_OFDM_SFKDIV56 0xF2C7 +#define F367_OFDM_SFECKDIV56_MAN 0xF2C70080 +#define F367_OFDM_SFEC_K_DIVIDER_56 0xF2C7007F + +/* SFKDIV67 */ +#define R367_OFDM_SFKDIV67 0xF2C8 +#define F367_OFDM_SFECKDIV67_MAN 0xF2C80080 +#define F367_OFDM_SFEC_K_DIVIDER_67 0xF2C8007F + +/* SFKDIV78 */ +#define R367_OFDM_SFKDIV78 0xF2C9 +#define F367_OFDM_SFECKDIV78_MAN 0xF2C90080 +#define F367_OFDM_SFEC_K_DIVIDER_78 0xF2C9007F + +/* SFDILSTKM */ +#define R367_OFDM_SFDILSTKM 0xF2CA +#define F367_OFDM_SFEC_PACKCPT 0xF2CA00E0 +#define F367_OFDM_SFEC_DILSTK_HI 0xF2CA001F + +/* SFDILSTKL */ +#define R367_OFDM_SFDILSTKL 0xF2CB +#define F367_OFDM_SFEC_DILSTK_LO 0xF2CB00FF + +/* SFSTATUS */ +#define R367_OFDM_SFSTATUS 0xF2CC +#define F367_OFDM_SFEC_LINEOK 0xF2CC0080 +#define F367_OFDM_SFEC_ERROR 0xF2CC0040 +#define F367_OFDM_SFEC_DATA7 0xF2CC0020 +#define F367_OFDM_SFEC_OVERFLOW 0xF2CC0010 +#define F367_OFDM_SFEC_DEMODSEL2 0xF2CC0008 +#define F367_OFDM_SFEC_NOSYNC 0xF2CC0004 +#define F367_OFDM_SFEC_UNREGULA 0xF2CC0002 +#define F367_OFDM_SFEC_READY 0xF2CC0001 + +/* SFDLYH */ +#define R367_OFDM_SFDLYH 0xF2CD +#define F367_OFDM_SFEC_TSTIMEVALID 0xF2CD0080 +#define F367_OFDM_SFEC_SPEEDUP 0xF2CD0040 +#define F367_OFDM_SFEC_STOP 0xF2CD0020 +#define F367_OFDM_SFEC_REGULATED 0xF2CD0010 +#define F367_OFDM_SFEC_REALSYMBOFFSET 0xF2CD000F + +/* SFDLYM */ +#define R367_OFDM_SFDLYM 0xF2CE +#define F367_OFDM_SFEC_REALSYMBOFFSET_HI 0xF2CE00FF + +/* SFDLYL */ +#define R367_OFDM_SFDLYL 0xF2CF +#define F367_OFDM_SFEC_REALSYMBOFFSET_LO 0xF2CF00FF + +/* SFDLYSETH */ +#define R367_OFDM_SFDLYSETH 0xF2D0 +#define F367_OFDM_SFEC_OFFSET 0xF2D000E0 +#define F367_OFDM_SFECDLYSETH_4 0xF2D00010 +#define F367_OFDM_RST_SFEC 0xF2D00008 +#define F367_OFDM_SFECDLYSETH_2 0xF2D00004 +#define F367_OFDM_SFEC_DISABLE 0xF2D00002 +#define F367_OFDM_SFEC_UNREGUL 0xF2D00001 + +/* SFDLYSETM */ +#define R367_OFDM_SFDLYSETM 0xF2D1 +#define F367_OFDM_SFECDLYSETM_7 0xF2D10080 +#define F367_OFDM_SFEC_SYMBOFFSET_HI 0xF2D1007F + +/* SFDLYSETL */ +#define R367_OFDM_SFDLYSETL 0xF2D2 +#define F367_OFDM_SFEC_SYMBOFFSET_LO 0xF2D200FF + +/* SFOBSCFG */ +#define R367_OFDM_SFOBSCFG 0xF2D3 +#define F367_OFDM_SFEC_OBSCFG 0xF2D300FF + +/* SFOBSM */ +#define R367_OFDM_SFOBSM 0xF2D4 +#define F367_OFDM_SFEC_OBSDATA_HI 0xF2D400FF + +/* SFOBSL */ +#define R367_OFDM_SFOBSL 0xF2D5 +#define F367_OFDM_SFEC_OBSDATA_LO 0xF2D500FF + +/* SFECINFO */ +#define R367_OFDM_SFECINFO 0xF2D6 +#define F367_OFDM_SFECINFO_7 0xF2D60080 +#define F367_OFDM_SFEC_SYNCDLSB 0xF2D60070 +#define F367_OFDM_SFCE_S1CPHASE 0xF2D6000F + +/* SFERRCTRL */ +#define R367_OFDM_SFERRCTRL 0xF2D8 +#define F367_OFDM_SFEC_ERR_SOURCE 0xF2D800F0 +#define F367_OFDM_SFERRCTRL_3 0xF2D80008 +#define F367_OFDM_SFEC_NUM_EVENT 0xF2D80007 + +/* SFERRCNTH */ +#define R367_OFDM_SFERRCNTH 0xF2D9 +#define F367_OFDM_SFERRC_OLDVALUE 0xF2D90080 +#define F367_OFDM_SFEC_ERR_CNT 0xF2D9007F + +/* SFERRCNTM */ +#define R367_OFDM_SFERRCNTM 0xF2DA +#define F367_OFDM_SFEC_ERR_CNT_HI 0xF2DA00FF + +/* SFERRCNTL */ +#define R367_OFDM_SFERRCNTL 0xF2DB +#define F367_OFDM_SFEC_ERR_CNT_LO 0xF2DB00FF + +/* SYMBRATEM */ +#define R367_OFDM_SYMBRATEM 0xF2E0 +#define F367_OFDM_DEFGEN_SYMBRATE_HI 0xF2E000FF + +/* SYMBRATEL */ +#define R367_OFDM_SYMBRATEL 0xF2E1 +#define F367_OFDM_DEFGEN_SYMBRATE_LO 0xF2E100FF + +/* SYMBSTATUS */ +#define R367_OFDM_SYMBSTATUS 0xF2E2 +#define F367_OFDM_SYMBDLINE2_OFF 0xF2E20080 +#define F367_OFDM_SDDL_REINIT1 0xF2E20040 +#define F367_OFDM_SDD_REINIT1 0xF2E20020 +#define F367_OFDM_TOKENID_ERROR 0xF2E20010 +#define F367_OFDM_SYMBRATE_OVERFLOW 0xF2E20008 +#define F367_OFDM_SYMBRATE_UNDERFLOW 0xF2E20004 +#define F367_OFDM_TOKENID_RSTEVENT 0xF2E20002 +#define F367_OFDM_TOKENID_RESET1 0xF2E20001 + +/* SYMBCFG */ +#define R367_OFDM_SYMBCFG 0xF2E3 +#define F367_OFDM_SYMBCFG_7 0xF2E30080 +#define F367_OFDM_SYMBCFG_6 0xF2E30040 +#define F367_OFDM_SYMBCFG_5 0xF2E30020 +#define F367_OFDM_SYMBCFG_4 0xF2E30010 +#define F367_OFDM_SYMRATE_FSPEED 0xF2E3000C +#define F367_OFDM_SYMRATE_SSPEED 0xF2E30003 + +/* SYMBFIFOM */ +#define R367_OFDM_SYMBFIFOM 0xF2E4 +#define F367_OFDM_SYMBFIFOM_7 0xF2E40080 +#define F367_OFDM_SYMBFIFOM_6 0xF2E40040 +#define F367_OFDM_DEFGEN_SYMFIFO_HI 0xF2E4003F + +/* SYMBFIFOL */ +#define R367_OFDM_SYMBFIFOL 0xF2E5 +#define F367_OFDM_DEFGEN_SYMFIFO_LO 0xF2E500FF + +/* SYMBOFFSM */ +#define R367_OFDM_SYMBOFFSM 0xF2E6 +#define F367_OFDM_TOKENID_RESET2 0xF2E60080 +#define F367_OFDM_SDDL_REINIT2 0xF2E60040 +#define F367_OFDM_SDD_REINIT2 0xF2E60020 +#define F367_OFDM_SYMBOFFSM_4 0xF2E60010 +#define F367_OFDM_SYMBOFFSM_3 0xF2E60008 +#define F367_OFDM_DEFGEN_SYMBOFFSET_HI 0xF2E60007 + +/* SYMBOFFSL */ +#define R367_OFDM_SYMBOFFSL 0xF2E7 +#define F367_OFDM_DEFGEN_SYMBOFFSET_LO 0xF2E700FF + +/* DEBUG_LT4 */ +#define R367_DEBUG_LT4 0xF400 +#define F367_F_DEBUG_LT4 0xF40000FF + +/* DEBUG_LT5 */ +#define R367_DEBUG_LT5 0xF401 +#define F367_F_DEBUG_LT5 0xF40100FF + +/* DEBUG_LT6 */ +#define R367_DEBUG_LT6 0xF402 +#define F367_F_DEBUG_LT6 0xF40200FF + +/* DEBUG_LT7 */ +#define R367_DEBUG_LT7 0xF403 +#define F367_F_DEBUG_LT7 0xF40300FF + +/* DEBUG_LT8 */ +#define R367_DEBUG_LT8 0xF404 +#define F367_F_DEBUG_LT8 0xF40400FF + +/* DEBUG_LT9 */ +#define R367_DEBUG_LT9 0xF405 +#define F367_F_DEBUG_LT9 0xF40500FF + +/* CTRL_1 */ +#define R367_QAM_CTRL_1 0xF402 +#define F367_QAM_SOFT_RST 0xF4020080 +#define F367_QAM_EQU_RST 0xF4020008 +#define F367_QAM_CRL_RST 0xF4020004 +#define F367_QAM_TRL_RST 0xF4020002 +#define F367_QAM_AGC_RST 0xF4020001 + +/* CTRL_2 */ +#define R367_QAM_CTRL_2 0xF403 +#define F367_QAM_DEINT_RST 0xF4030008 +#define F367_QAM_RS_RST 0xF4030004 + +/* IT_STATUS1 */ +#define R367_QAM_IT_STATUS1 0xF408 +#define F367_QAM_SWEEP_OUT 0xF4080080 +#define F367_QAM_FSM_CRL 0xF4080040 +#define F367_QAM_CRL_LOCK 0xF4080020 +#define F367_QAM_MFSM 0xF4080010 +#define F367_QAM_TRL_LOCK 0xF4080008 +#define F367_QAM_TRL_AGC_LIMIT 0xF4080004 +#define F367_QAM_ADJ_AGC_LOCK 0xF4080002 +#define F367_QAM_AGC_QAM_LOCK 0xF4080001 + +/* IT_STATUS2 */ +#define R367_QAM_IT_STATUS2 0xF409 +#define F367_QAM_TSMF_CNT 0xF4090080 +#define F367_QAM_TSMF_EOF 0xF4090040 +#define F367_QAM_TSMF_RDY 0xF4090020 +#define F367_QAM_FEC_NOCORR 0xF4090010 +#define F367_QAM_SYNCSTATE 0xF4090008 +#define F367_QAM_DEINT_LOCK 0xF4090004 +#define F367_QAM_FADDING_FRZ 0xF4090002 +#define F367_QAM_TAPMON_ALARM 0xF4090001 + +/* IT_EN1 */ +#define R367_QAM_IT_EN1 0xF40A +#define F367_QAM_SWEEP_OUTE 0xF40A0080 +#define F367_QAM_FSM_CRLE 0xF40A0040 +#define F367_QAM_CRL_LOCKE 0xF40A0020 +#define F367_QAM_MFSME 0xF40A0010 +#define F367_QAM_TRL_LOCKE 0xF40A0008 +#define F367_QAM_TRL_AGC_LIMITE 0xF40A0004 +#define F367_QAM_ADJ_AGC_LOCKE 0xF40A0002 +#define F367_QAM_AGC_LOCKE 0xF40A0001 + +/* IT_EN2 */ +#define R367_QAM_IT_EN2 0xF40B +#define F367_QAM_TSMF_CNTE 0xF40B0080 +#define F367_QAM_TSMF_EOFE 0xF40B0040 +#define F367_QAM_TSMF_RDYE 0xF40B0020 +#define F367_QAM_FEC_NOCORRE 0xF40B0010 +#define F367_QAM_SYNCSTATEE 0xF40B0008 +#define F367_QAM_DEINT_LOCKE 0xF40B0004 +#define F367_QAM_FADDING_FRZE 0xF40B0002 +#define F367_QAM_TAPMON_ALARME 0xF40B0001 + +/* CTRL_STATUS */ +#define R367_QAM_CTRL_STATUS 0xF40C +#define F367_QAM_QAMFEC_LOCK 0xF40C0004 +#define F367_QAM_TSMF_LOCK 0xF40C0002 +#define F367_QAM_TSMF_ERROR 0xF40C0001 + +/* TEST_CTL */ +#define R367_QAM_TEST_CTL 0xF40F +#define F367_QAM_TST_BLK_SEL 0xF40F0060 +#define F367_QAM_TST_BUS_SEL 0xF40F001F + +/* AGC_CTL */ +#define R367_QAM_AGC_CTL 0xF410 +#define F367_QAM_AGC_LCK_TH 0xF41000F0 +#define F367_QAM_AGC_ACCUMRSTSEL 0xF4100007 + +/* AGC_IF_CFG */ +#define R367_QAM_AGC_IF_CFG 0xF411 +#define F367_QAM_AGC_IF_BWSEL 0xF41100F0 +#define F367_QAM_AGC_IF_FREEZE 0xF4110002 + +/* AGC_RF_CFG */ +#define R367_QAM_AGC_RF_CFG 0xF412 +#define F367_QAM_AGC_RF_BWSEL 0xF4120070 +#define F367_QAM_AGC_RF_FREEZE 0xF4120002 + +/* AGC_PWM_CFG */ +#define R367_QAM_AGC_PWM_CFG 0xF413 +#define F367_QAM_AGC_RF_PWM_TST 0xF4130080 +#define F367_QAM_AGC_RF_PWM_INV 0xF4130040 +#define F367_QAM_AGC_IF_PWM_TST 0xF4130008 +#define F367_QAM_AGC_IF_PWM_INV 0xF4130004 +#define F367_QAM_AGC_PWM_CLKDIV 0xF4130003 + +/* AGC_PWR_REF_L */ +#define R367_QAM_AGC_PWR_REF_L 0xF414 +#define F367_QAM_AGC_PWRREF_LO 0xF41400FF + +/* AGC_PWR_REF_H */ +#define R367_QAM_AGC_PWR_REF_H 0xF415 +#define F367_QAM_AGC_PWRREF_HI 0xF4150003 + +/* AGC_RF_TH_L */ +#define R367_QAM_AGC_RF_TH_L 0xF416 +#define F367_QAM_AGC_RF_TH_LO 0xF41600FF + +/* AGC_RF_TH_H */ +#define R367_QAM_AGC_RF_TH_H 0xF417 +#define F367_QAM_AGC_RF_TH_HI 0xF417000F + +/* AGC_IF_LTH_L */ +#define R367_QAM_AGC_IF_LTH_L 0xF418 +#define F367_QAM_AGC_IF_THLO_LO 0xF41800FF + +/* AGC_IF_LTH_H */ +#define R367_QAM_AGC_IF_LTH_H 0xF419 +#define F367_QAM_AGC_IF_THLO_HI 0xF419000F + +/* AGC_IF_HTH_L */ +#define R367_QAM_AGC_IF_HTH_L 0xF41A +#define F367_QAM_AGC_IF_THHI_LO 0xF41A00FF + +/* AGC_IF_HTH_H */ +#define R367_QAM_AGC_IF_HTH_H 0xF41B +#define F367_QAM_AGC_IF_THHI_HI 0xF41B000F + +/* AGC_PWR_RD_L */ +#define R367_QAM_AGC_PWR_RD_L 0xF41C +#define F367_QAM_AGC_PWR_WORD_LO 0xF41C00FF + +/* AGC_PWR_RD_M */ +#define R367_QAM_AGC_PWR_RD_M 0xF41D +#define F367_QAM_AGC_PWR_WORD_ME 0xF41D00FF + +/* AGC_PWR_RD_H */ +#define R367_QAM_AGC_PWR_RD_H 0xF41E +#define F367_QAM_AGC_PWR_WORD_HI 0xF41E0003 + +/* AGC_PWM_IFCMD_L */ +#define R367_QAM_AGC_PWM_IFCMD_L 0xF420 +#define F367_QAM_AGC_IF_PWMCMD_LO 0xF42000FF + +/* AGC_PWM_IFCMD_H */ +#define R367_QAM_AGC_PWM_IFCMD_H 0xF421 +#define F367_QAM_AGC_IF_PWMCMD_HI 0xF421000F + +/* AGC_PWM_RFCMD_L */ +#define R367_QAM_AGC_PWM_RFCMD_L 0xF422 +#define F367_QAM_AGC_RF_PWMCMD_LO 0xF42200FF + +/* AGC_PWM_RFCMD_H */ +#define R367_QAM_AGC_PWM_RFCMD_H 0xF423 +#define F367_QAM_AGC_RF_PWMCMD_HI 0xF423000F + +/* IQDEM_CFG */ +#define R367_QAM_IQDEM_CFG 0xF424 +#define F367_QAM_IQDEM_CLK_SEL 0xF4240004 +#define F367_QAM_IQDEM_INVIQ 0xF4240002 +#define F367_QAM_IQDEM_A2DTYPE 0xF4240001 + +/* MIX_NCO_LL */ +#define R367_QAM_MIX_NCO_LL 0xF425 +#define F367_QAM_MIX_NCO_INC_LL 0xF42500FF + +/* MIX_NCO_HL */ +#define R367_QAM_MIX_NCO_HL 0xF426 +#define F367_QAM_MIX_NCO_INC_HL 0xF42600FF + +/* MIX_NCO_HH */ +#define R367_QAM_MIX_NCO_HH 0xF427 +#define F367_QAM_MIX_NCO_INVCNST 0xF4270080 +#define F367_QAM_MIX_NCO_INC_HH 0xF427007F + +/* SRC_NCO_LL */ +#define R367_QAM_SRC_NCO_LL 0xF428 +#define F367_QAM_SRC_NCO_INC_LL 0xF42800FF + +/* SRC_NCO_LH */ +#define R367_QAM_SRC_NCO_LH 0xF429 +#define F367_QAM_SRC_NCO_INC_LH 0xF42900FF + +/* SRC_NCO_HL */ +#define R367_QAM_SRC_NCO_HL 0xF42A +#define F367_QAM_SRC_NCO_INC_HL 0xF42A00FF + +/* SRC_NCO_HH */ +#define R367_QAM_SRC_NCO_HH 0xF42B +#define F367_QAM_SRC_NCO_INC_HH 0xF42B007F + +/* IQDEM_GAIN_SRC_L */ +#define R367_QAM_IQDEM_GAIN_SRC_L 0xF42C +#define F367_QAM_GAIN_SRC_LO 0xF42C00FF + +/* IQDEM_GAIN_SRC_H */ +#define R367_QAM_IQDEM_GAIN_SRC_H 0xF42D +#define F367_QAM_GAIN_SRC_HI 0xF42D0003 + +/* IQDEM_DCRM_CFG_LL */ +#define R367_QAM_IQDEM_DCRM_CFG_LL 0xF430 +#define F367_QAM_DCRM0_DCIN_L 0xF43000FF + +/* IQDEM_DCRM_CFG_LH */ +#define R367_QAM_IQDEM_DCRM_CFG_LH 0xF431 +#define F367_QAM_DCRM1_I_DCIN_L 0xF43100FC +#define F367_QAM_DCRM0_DCIN_H 0xF4310003 + +/* IQDEM_DCRM_CFG_HL */ +#define R367_QAM_IQDEM_DCRM_CFG_HL 0xF432 +#define F367_QAM_DCRM1_Q_DCIN_L 0xF43200F0 +#define F367_QAM_DCRM1_I_DCIN_H 0xF432000F + +/* IQDEM_DCRM_CFG_HH */ +#define R367_QAM_IQDEM_DCRM_CFG_HH 0xF433 +#define F367_QAM_DCRM1_FRZ 0xF4330080 +#define F367_QAM_DCRM0_FRZ 0xF4330040 +#define F367_QAM_DCRM1_Q_DCIN_H 0xF433003F + +/* IQDEM_ADJ_COEFF0 */ +#define R367_QAM_IQDEM_ADJ_COEFF0 0xF434 +#define F367_QAM_ADJIIR_COEFF10_L 0xF43400FF + +/* IQDEM_ADJ_COEFF1 */ +#define R367_QAM_IQDEM_ADJ_COEFF1 0xF435 +#define F367_QAM_ADJIIR_COEFF11_L 0xF43500FC +#define F367_QAM_ADJIIR_COEFF10_H 0xF4350003 + +/* IQDEM_ADJ_COEFF2 */ +#define R367_QAM_IQDEM_ADJ_COEFF2 0xF436 +#define F367_QAM_ADJIIR_COEFF12_L 0xF43600F0 +#define F367_QAM_ADJIIR_COEFF11_H 0xF436000F + +/* IQDEM_ADJ_COEFF3 */ +#define R367_QAM_IQDEM_ADJ_COEFF3 0xF437 +#define F367_QAM_ADJIIR_COEFF20_L 0xF43700C0 +#define F367_QAM_ADJIIR_COEFF12_H 0xF437003F + +/* IQDEM_ADJ_COEFF4 */ +#define R367_QAM_IQDEM_ADJ_COEFF4 0xF438 +#define F367_QAM_ADJIIR_COEFF20_H 0xF43800FF + +/* IQDEM_ADJ_COEFF5 */ +#define R367_QAM_IQDEM_ADJ_COEFF5 0xF439 +#define F367_QAM_ADJIIR_COEFF21_L 0xF43900FF + +/* IQDEM_ADJ_COEFF6 */ +#define R367_QAM_IQDEM_ADJ_COEFF6 0xF43A +#define F367_QAM_ADJIIR_COEFF22_L 0xF43A00FC +#define F367_QAM_ADJIIR_COEFF21_H 0xF43A0003 + +/* IQDEM_ADJ_COEFF7 */ +#define R367_QAM_IQDEM_ADJ_COEFF7 0xF43B +#define F367_QAM_ADJIIR_COEFF22_H 0xF43B000F + +/* IQDEM_ADJ_EN */ +#define R367_QAM_IQDEM_ADJ_EN 0xF43C +#define F367_QAM_ALLPASSFILT_EN 0xF43C0008 +#define F367_QAM_ADJ_AGC_EN 0xF43C0004 +#define F367_QAM_ADJ_COEFF_FRZ 0xF43C0002 +#define F367_QAM_ADJ_EN 0xF43C0001 + +/* IQDEM_ADJ_AGC_REF */ +#define R367_QAM_IQDEM_ADJ_AGC_REF 0xF43D +#define F367_QAM_ADJ_AGC_REF 0xF43D00FF + +/* ALLPASSFILT1 */ +#define R367_QAM_ALLPASSFILT1 0xF440 +#define F367_QAM_ALLPASSFILT_COEFF1_LO 0xF44000FF + +/* ALLPASSFILT2 */ +#define R367_QAM_ALLPASSFILT2 0xF441 +#define F367_QAM_ALLPASSFILT_COEFF1_ME 0xF44100FF + +/* ALLPASSFILT3 */ +#define R367_QAM_ALLPASSFILT3 0xF442 +#define F367_QAM_ALLPASSFILT_COEFF2_LO 0xF44200C0 +#define F367_QAM_ALLPASSFILT_COEFF1_HI 0xF442003F + +/* ALLPASSFILT4 */ +#define R367_QAM_ALLPASSFILT4 0xF443 +#define F367_QAM_ALLPASSFILT_COEFF2_MEL 0xF44300FF + +/* ALLPASSFILT5 */ +#define R367_QAM_ALLPASSFILT5 0xF444 +#define F367_QAM_ALLPASSFILT_COEFF2_MEH 0xF44400FF + +/* ALLPASSFILT6 */ +#define R367_QAM_ALLPASSFILT6 0xF445 +#define F367_QAM_ALLPASSFILT_COEFF3_LO 0xF44500F0 +#define F367_QAM_ALLPASSFILT_COEFF2_HI 0xF445000F + +/* ALLPASSFILT7 */ +#define R367_QAM_ALLPASSFILT7 0xF446 +#define F367_QAM_ALLPASSFILT_COEFF3_MEL 0xF44600FF + +/* ALLPASSFILT8 */ +#define R367_QAM_ALLPASSFILT8 0xF447 +#define F367_QAM_ALLPASSFILT_COEFF3_MEH 0xF44700FF + +/* ALLPASSFILT9 */ +#define R367_QAM_ALLPASSFILT9 0xF448 +#define F367_QAM_ALLPASSFILT_COEFF4_LO 0xF44800FC +#define F367_QAM_ALLPASSFILT_COEFF3_HI 0xF4480003 + +/* ALLPASSFILT10 */ +#define R367_QAM_ALLPASSFILT10 0xF449 +#define F367_QAM_ALLPASSFILT_COEFF4_ME 0xF44900FF + +/* ALLPASSFILT11 */ +#define R367_QAM_ALLPASSFILT11 0xF44A +#define F367_QAM_ALLPASSFILT_COEFF4_HI 0xF44A00FF + +/* TRL_AGC_CFG */ +#define R367_QAM_TRL_AGC_CFG 0xF450 +#define F367_QAM_TRL_AGC_FREEZE 0xF4500080 +#define F367_QAM_TRL_AGC_REF 0xF450007F + +/* TRL_LPF_CFG */ +#define R367_QAM_TRL_LPF_CFG 0xF454 +#define F367_QAM_NYQPOINT_INV 0xF4540040 +#define F367_QAM_TRL_SHIFT 0xF4540030 +#define F367_QAM_NYQ_COEFF_SEL 0xF454000C +#define F367_QAM_TRL_LPF_FREEZE 0xF4540002 +#define F367_QAM_TRL_LPF_CRT 0xF4540001 + +/* TRL_LPF_ACQ_GAIN */ +#define R367_QAM_TRL_LPF_ACQ_GAIN 0xF455 +#define F367_QAM_TRL_GDIR_ACQ 0xF4550070 +#define F367_QAM_TRL_GINT_ACQ 0xF4550007 + +/* TRL_LPF_TRK_GAIN */ +#define R367_QAM_TRL_LPF_TRK_GAIN 0xF456 +#define F367_QAM_TRL_GDIR_TRK 0xF4560070 +#define F367_QAM_TRL_GINT_TRK 0xF4560007 + +/* TRL_LPF_OUT_GAIN */ +#define R367_QAM_TRL_LPF_OUT_GAIN 0xF457 +#define F367_QAM_TRL_GAIN_OUT 0xF4570007 + +/* TRL_LOCKDET_LTH */ +#define R367_QAM_TRL_LOCKDET_LTH 0xF458 +#define F367_QAM_TRL_LCK_THLO 0xF4580007 + +/* TRL_LOCKDET_HTH */ +#define R367_QAM_TRL_LOCKDET_HTH 0xF459 +#define F367_QAM_TRL_LCK_THHI 0xF45900FF + +/* TRL_LOCKDET_TRGVAL */ +#define R367_QAM_TRL_LOCKDET_TRGVAL 0xF45A +#define F367_QAM_TRL_LCK_TRG 0xF45A00FF + +/* IQ_QAM */ +#define R367_QAM_IQ_QAM 0xF45C +#define F367_QAM_IQ_INPUT 0xF45C0008 +#define F367_QAM_DETECT_MODE 0xF45C0007 + +/* FSM_STATE */ +#define R367_QAM_FSM_STATE 0xF460 +#define F367_QAM_CRL_DFE 0xF4600080 +#define F367_QAM_DFE_START 0xF4600040 +#define F367_QAM_CTRLG_START 0xF4600030 +#define F367_QAM_FSM_FORCESTATE 0xF460000F + +/* FSM_CTL */ +#define R367_QAM_FSM_CTL 0xF461 +#define F367_QAM_FEC2_EN 0xF4610040 +#define F367_QAM_SIT_EN 0xF4610020 +#define F367_QAM_TRL_AHEAD 0xF4610010 +#define F367_QAM_TRL2_EN 0xF4610008 +#define F367_QAM_FSM_EQA1_EN 0xF4610004 +#define F367_QAM_FSM_BKP_DIS 0xF4610002 +#define F367_QAM_FSM_FORCE_EN 0xF4610001 + +/* FSM_STS */ +#define R367_QAM_FSM_STS 0xF462 +#define F367_QAM_FSM_STATUS 0xF462000F + +/* FSM_SNR0_HTH */ +#define R367_QAM_FSM_SNR0_HTH 0xF463 +#define F367_QAM_SNR0_HTH 0xF46300FF + +/* FSM_SNR1_HTH */ +#define R367_QAM_FSM_SNR1_HTH 0xF464 +#define F367_QAM_SNR1_HTH 0xF46400FF + +/* FSM_SNR2_HTH */ +#define R367_QAM_FSM_SNR2_HTH 0xF465 +#define F367_QAM_SNR2_HTH 0xF46500FF + +/* FSM_SNR0_LTH */ +#define R367_QAM_FSM_SNR0_LTH 0xF466 +#define F367_QAM_SNR0_LTH 0xF46600FF + +/* FSM_SNR1_LTH */ +#define R367_QAM_FSM_SNR1_LTH 0xF467 +#define F367_QAM_SNR1_LTH 0xF46700FF + +/* FSM_EQA1_HTH */ +#define R367_QAM_FSM_EQA1_HTH 0xF468 +#define F367_QAM_SNR3_HTH_LO 0xF46800F0 +#define F367_QAM_EQA1_HTH 0xF468000F + +/* FSM_TEMPO */ +#define R367_QAM_FSM_TEMPO 0xF469 +#define F367_QAM_SIT 0xF46900C0 +#define F367_QAM_WST 0xF4690038 +#define F367_QAM_ELT 0xF4690006 +#define F367_QAM_SNR3_HTH_HI 0xF4690001 + +/* FSM_CONFIG */ +#define R367_QAM_FSM_CONFIG 0xF46A +#define F367_QAM_FEC2_DFEOFF 0xF46A0004 +#define F367_QAM_PRIT_STATE 0xF46A0002 +#define F367_QAM_MODMAP_STATE 0xF46A0001 + +/* EQU_I_TESTTAP_L */ +#define R367_QAM_EQU_I_TESTTAP_L 0xF474 +#define F367_QAM_I_TEST_TAP_L 0xF47400FF + +/* EQU_I_TESTTAP_M */ +#define R367_QAM_EQU_I_TESTTAP_M 0xF475 +#define F367_QAM_I_TEST_TAP_M 0xF47500FF + +/* EQU_I_TESTTAP_H */ +#define R367_QAM_EQU_I_TESTTAP_H 0xF476 +#define F367_QAM_I_TEST_TAP_H 0xF476001F + +/* EQU_TESTAP_CFG */ +#define R367_QAM_EQU_TESTAP_CFG 0xF477 +#define F367_QAM_TEST_FFE_DFE_SEL 0xF4770040 +#define F367_QAM_TEST_TAP_SELECT 0xF477003F + +/* EQU_Q_TESTTAP_L */ +#define R367_QAM_EQU_Q_TESTTAP_L 0xF478 +#define F367_QAM_Q_TEST_TAP_L 0xF47800FF + +/* EQU_Q_TESTTAP_M */ +#define R367_QAM_EQU_Q_TESTTAP_M 0xF479 +#define F367_QAM_Q_TEST_TAP_M 0xF47900FF + +/* EQU_Q_TESTTAP_H */ +#define R367_QAM_EQU_Q_TESTTAP_H 0xF47A +#define F367_QAM_Q_TEST_TAP_H 0xF47A001F + +/* EQU_TAP_CTRL */ +#define R367_QAM_EQU_TAP_CTRL 0xF47B +#define F367_QAM_MTAP_FRZ 0xF47B0010 +#define F367_QAM_PRE_FREEZE 0xF47B0008 +#define F367_QAM_DFE_TAPMON_EN 0xF47B0004 +#define F367_QAM_FFE_TAPMON_EN 0xF47B0002 +#define F367_QAM_MTAP_ONLY 0xF47B0001 + +/* EQU_CTR_CRL_CONTROL_L */ +#define R367_QAM_EQU_CTR_CRL_CONTROL_L 0xF47C +#define F367_QAM_EQU_CTR_CRL_CONTROL_LO 0xF47C00FF + +/* EQU_CTR_CRL_CONTROL_H */ +#define R367_QAM_EQU_CTR_CRL_CONTROL_H 0xF47D +#define F367_QAM_EQU_CTR_CRL_CONTROL_HI 0xF47D00FF + +/* EQU_CTR_HIPOW_L */ +#define R367_QAM_EQU_CTR_HIPOW_L 0xF47E +#define F367_QAM_CTR_HIPOW_L 0xF47E00FF + +/* EQU_CTR_HIPOW_H */ +#define R367_QAM_EQU_CTR_HIPOW_H 0xF47F +#define F367_QAM_CTR_HIPOW_H 0xF47F00FF + +/* EQU_I_EQU_LO */ +#define R367_QAM_EQU_I_EQU_LO 0xF480 +#define F367_QAM_EQU_I_EQU_L 0xF48000FF + +/* EQU_I_EQU_HI */ +#define R367_QAM_EQU_I_EQU_HI 0xF481 +#define F367_QAM_EQU_I_EQU_H 0xF4810003 + +/* EQU_Q_EQU_LO */ +#define R367_QAM_EQU_Q_EQU_LO 0xF482 +#define F367_QAM_EQU_Q_EQU_L 0xF48200FF + +/* EQU_Q_EQU_HI */ +#define R367_QAM_EQU_Q_EQU_HI 0xF483 +#define F367_QAM_EQU_Q_EQU_H 0xF4830003 + +/* EQU_MAPPER */ +#define R367_QAM_EQU_MAPPER 0xF484 +#define F367_QAM_QUAD_AUTO 0xF4840080 +#define F367_QAM_QUAD_INV 0xF4840040 +#define F367_QAM_QAM_MODE 0xF4840007 + +/* EQU_SWEEP_RATE */ +#define R367_QAM_EQU_SWEEP_RATE 0xF485 +#define F367_QAM_SNR_PER 0xF48500C0 +#define F367_QAM_SWEEP_RATE 0xF485003F + +/* EQU_SNR_LO */ +#define R367_QAM_EQU_SNR_LO 0xF486 +#define F367_QAM_SNR_LO 0xF48600FF + +/* EQU_SNR_HI */ +#define R367_QAM_EQU_SNR_HI 0xF487 +#define F367_QAM_SNR_HI 0xF48700FF + +/* EQU_GAMMA_LO */ +#define R367_QAM_EQU_GAMMA_LO 0xF488 +#define F367_QAM_GAMMA_LO 0xF48800FF + +/* EQU_GAMMA_HI */ +#define R367_QAM_EQU_GAMMA_HI 0xF489 +#define F367_QAM_GAMMA_ME 0xF48900FF + +/* EQU_ERR_GAIN */ +#define R367_QAM_EQU_ERR_GAIN 0xF48A +#define F367_QAM_EQA1MU 0xF48A0070 +#define F367_QAM_CRL2MU 0xF48A000E +#define F367_QAM_GAMMA_HI 0xF48A0001 + +/* EQU_RADIUS */ +#define R367_QAM_EQU_RADIUS 0xF48B +#define F367_QAM_RADIUS 0xF48B00FF + +/* EQU_FFE_MAINTAP */ +#define R367_QAM_EQU_FFE_MAINTAP 0xF48C +#define F367_QAM_FFE_MAINTAP_INIT 0xF48C00FF + +/* EQU_FFE_LEAKAGE */ +#define R367_QAM_EQU_FFE_LEAKAGE 0xF48E +#define F367_QAM_LEAK_PER 0xF48E00F0 +#define F367_QAM_EQU_OUTSEL 0xF48E0002 +#define F367_QAM_PNT2DFE 0xF48E0001 + +/* EQU_FFE_MAINTAP_POS */ +#define R367_QAM_EQU_FFE_MAINTAP_POS 0xF48F +#define F367_QAM_FFE_LEAK_EN 0xF48F0080 +#define F367_QAM_DFE_LEAK_EN 0xF48F0040 +#define F367_QAM_FFE_MAINTAP_POS 0xF48F003F + +/* EQU_GAIN_WIDE */ +#define R367_QAM_EQU_GAIN_WIDE 0xF490 +#define F367_QAM_DFE_GAIN_WIDE 0xF49000F0 +#define F367_QAM_FFE_GAIN_WIDE 0xF490000F + +/* EQU_GAIN_NARROW */ +#define R367_QAM_EQU_GAIN_NARROW 0xF491 +#define F367_QAM_DFE_GAIN_NARROW 0xF49100F0 +#define F367_QAM_FFE_GAIN_NARROW 0xF491000F + +/* EQU_CTR_LPF_GAIN */ +#define R367_QAM_EQU_CTR_LPF_GAIN 0xF492 +#define F367_QAM_CTR_GTO 0xF4920080 +#define F367_QAM_CTR_GDIR 0xF4920070 +#define F367_QAM_SWEEP_EN 0xF4920008 +#define F367_QAM_CTR_GINT 0xF4920007 + +/* EQU_CRL_LPF_GAIN */ +#define R367_QAM_EQU_CRL_LPF_GAIN 0xF493 +#define F367_QAM_CRL_GTO 0xF4930080 +#define F367_QAM_CRL_GDIR 0xF4930070 +#define F367_QAM_SWEEP_DIR 0xF4930008 +#define F367_QAM_CRL_GINT 0xF4930007 + +/* EQU_GLOBAL_GAIN */ +#define R367_QAM_EQU_GLOBAL_GAIN 0xF494 +#define F367_QAM_CRL_GAIN 0xF49400F8 +#define F367_QAM_CTR_INC_GAIN 0xF4940004 +#define F367_QAM_CTR_FRAC 0xF4940003 + +/* EQU_CRL_LD_SEN */ +#define R367_QAM_EQU_CRL_LD_SEN 0xF495 +#define F367_QAM_CTR_BADPOINT_EN 0xF4950080 +#define F367_QAM_CTR_GAIN 0xF4950070 +#define F367_QAM_LIMANEN 0xF4950008 +#define F367_QAM_CRL_LD_SEN 0xF4950007 + +/* EQU_CRL_LD_VAL */ +#define R367_QAM_EQU_CRL_LD_VAL 0xF496 +#define F367_QAM_CRL_BISTH_LIMIT 0xF4960080 +#define F367_QAM_CARE_EN 0xF4960040 +#define F367_QAM_CRL_LD_PER 0xF4960030 +#define F367_QAM_CRL_LD_WST 0xF496000C +#define F367_QAM_CRL_LD_TFS 0xF4960003 + +/* EQU_CRL_TFR */ +#define R367_QAM_EQU_CRL_TFR 0xF497 +#define F367_QAM_CRL_LD_TFR 0xF49700FF + +/* EQU_CRL_BISTH_LO */ +#define R367_QAM_EQU_CRL_BISTH_LO 0xF498 +#define F367_QAM_CRL_BISTH_LO 0xF49800FF + +/* EQU_CRL_BISTH_HI */ +#define R367_QAM_EQU_CRL_BISTH_HI 0xF499 +#define F367_QAM_CRL_BISTH_HI 0xF49900FF + +/* EQU_SWEEP_RANGE_LO */ +#define R367_QAM_EQU_SWEEP_RANGE_LO 0xF49A +#define F367_QAM_SWEEP_RANGE_LO 0xF49A00FF + +/* EQU_SWEEP_RANGE_HI */ +#define R367_QAM_EQU_SWEEP_RANGE_HI 0xF49B +#define F367_QAM_SWEEP_RANGE_HI 0xF49B00FF + +/* EQU_CRL_LIMITER */ +#define R367_QAM_EQU_CRL_LIMITER 0xF49C +#define F367_QAM_BISECTOR_EN 0xF49C0080 +#define F367_QAM_PHEST128_EN 0xF49C0040 +#define F367_QAM_CRL_LIM 0xF49C003F + +/* EQU_MODULUS_MAP */ +#define R367_QAM_EQU_MODULUS_MAP 0xF49D +#define F367_QAM_PNT_DEPTH 0xF49D00E0 +#define F367_QAM_MODULUS_CMP 0xF49D001F + +/* EQU_PNT_GAIN */ +#define R367_QAM_EQU_PNT_GAIN 0xF49E +#define F367_QAM_PNT_EN 0xF49E0080 +#define F367_QAM_MODULUSMAP_EN 0xF49E0040 +#define F367_QAM_PNT_GAIN 0xF49E003F + +/* FEC_AC_CTR_0 */ +#define R367_QAM_FEC_AC_CTR_0 0xF4A8 +#define F367_QAM_BE_BYPASS 0xF4A80020 +#define F367_QAM_REFRESH47 0xF4A80010 +#define F367_QAM_CT_NBST 0xF4A80008 +#define F367_QAM_TEI_ENA 0xF4A80004 +#define F367_QAM_DS_ENA 0xF4A80002 +#define F367_QAM_TSMF_EN 0xF4A80001 + +/* FEC_AC_CTR_1 */ +#define R367_QAM_FEC_AC_CTR_1 0xF4A9 +#define F367_QAM_DEINT_DEPTH 0xF4A900FF + +/* FEC_AC_CTR_2 */ +#define R367_QAM_FEC_AC_CTR_2 0xF4AA +#define F367_QAM_DEINT_M 0xF4AA00F8 +#define F367_QAM_DIS_UNLOCK 0xF4AA0004 +#define F367_QAM_DESCR_MODE 0xF4AA0003 + +/* FEC_AC_CTR_3 */ +#define R367_QAM_FEC_AC_CTR_3 0xF4AB +#define F367_QAM_DI_UNLOCK 0xF4AB0080 +#define F367_QAM_DI_FREEZE 0xF4AB0040 +#define F367_QAM_MISMATCH 0xF4AB0030 +#define F367_QAM_ACQ_MODE 0xF4AB000C +#define F367_QAM_TRK_MODE 0xF4AB0003 + +/* FEC_STATUS */ +#define R367_QAM_FEC_STATUS 0xF4AC +#define F367_QAM_DEINT_SMCNTR 0xF4AC00E0 +#define F367_QAM_DEINT_SYNCSTATE 0xF4AC0018 +#define F367_QAM_DEINT_SYNLOST 0xF4AC0004 +#define F367_QAM_DESCR_SYNCSTATE 0xF4AC0002 + +/* RS_COUNTER_0 */ +#define R367_QAM_RS_COUNTER_0 0xF4AE +#define F367_QAM_BK_CT_L 0xF4AE00FF + +/* RS_COUNTER_1 */ +#define R367_QAM_RS_COUNTER_1 0xF4AF +#define F367_QAM_BK_CT_H 0xF4AF00FF + +/* RS_COUNTER_2 */ +#define R367_QAM_RS_COUNTER_2 0xF4B0 +#define F367_QAM_CORR_CT_L 0xF4B000FF + +/* RS_COUNTER_3 */ +#define R367_QAM_RS_COUNTER_3 0xF4B1 +#define F367_QAM_CORR_CT_H 0xF4B100FF + +/* RS_COUNTER_4 */ +#define R367_QAM_RS_COUNTER_4 0xF4B2 +#define F367_QAM_UNCORR_CT_L 0xF4B200FF + +/* RS_COUNTER_5 */ +#define R367_QAM_RS_COUNTER_5 0xF4B3 +#define F367_QAM_UNCORR_CT_H 0xF4B300FF + +/* BERT_0 */ +#define R367_QAM_BERT_0 0xF4B4 +#define F367_QAM_RS_NOCORR 0xF4B40004 +#define F367_QAM_CT_HOLD 0xF4B40002 +#define F367_QAM_CT_CLEAR 0xF4B40001 + +/* BERT_1 */ +#define R367_QAM_BERT_1 0xF4B5 +#define F367_QAM_BERT_ON 0xF4B50020 +#define F367_QAM_BERT_ERR_SRC 0xF4B50010 +#define F367_QAM_BERT_ERR_MODE 0xF4B50008 +#define F367_QAM_BERT_NBYTE 0xF4B50007 + +/* BERT_2 */ +#define R367_QAM_BERT_2 0xF4B6 +#define F367_QAM_BERT_ERRCOUNT_L 0xF4B600FF + +/* BERT_3 */ +#define R367_QAM_BERT_3 0xF4B7 +#define F367_QAM_BERT_ERRCOUNT_H 0xF4B700FF + +/* OUTFORMAT_0 */ +#define R367_QAM_OUTFORMAT_0 0xF4B8 +#define F367_QAM_CLK_POLARITY 0xF4B80080 +#define F367_QAM_FEC_TYPE 0xF4B80040 +#define F367_QAM_SYNC_STRIP 0xF4B80008 +#define F367_QAM_TS_SWAP 0xF4B80004 +#define F367_QAM_OUTFORMAT 0xF4B80003 + +/* OUTFORMAT_1 */ +#define R367_QAM_OUTFORMAT_1 0xF4B9 +#define F367_QAM_CI_DIVRANGE 0xF4B900FF + +/* SMOOTHER_2 */ +#define R367_QAM_SMOOTHER_2 0xF4BE +#define F367_QAM_FIFO_BYPASS 0xF4BE0020 + +/* TSMF_CTRL_0 */ +#define R367_QAM_TSMF_CTRL_0 0xF4C0 +#define F367_QAM_TS_NUMBER 0xF4C0001E +#define F367_QAM_SEL_MODE 0xF4C00001 + +/* TSMF_CTRL_1 */ +#define R367_QAM_TSMF_CTRL_1 0xF4C1 +#define F367_QAM_CHECK_ERROR_BIT 0xF4C10080 +#define F367_QAM_CHCK_F_SYNC 0xF4C10040 +#define F367_QAM_H_MODE 0xF4C10008 +#define F367_QAM_D_V_MODE 0xF4C10004 +#define F367_QAM_MODE 0xF4C10003 + +/* TSMF_CTRL_3 */ +#define R367_QAM_TSMF_CTRL_3 0xF4C3 +#define F367_QAM_SYNC_IN_COUNT 0xF4C300F0 +#define F367_QAM_SYNC_OUT_COUNT 0xF4C3000F + +/* TS_ON_ID_0 */ +#define R367_QAM_TS_ON_ID_0 0xF4C4 +#define F367_QAM_TS_ID_L 0xF4C400FF + +/* TS_ON_ID_1 */ +#define R367_QAM_TS_ON_ID_1 0xF4C5 +#define F367_QAM_TS_ID_H 0xF4C500FF + +/* TS_ON_ID_2 */ +#define R367_QAM_TS_ON_ID_2 0xF4C6 +#define F367_QAM_ON_ID_L 0xF4C600FF + +/* TS_ON_ID_3 */ +#define R367_QAM_TS_ON_ID_3 0xF4C7 +#define F367_QAM_ON_ID_H 0xF4C700FF + +/* RE_STATUS_0 */ +#define R367_QAM_RE_STATUS_0 0xF4C8 +#define F367_QAM_RECEIVE_STATUS_L 0xF4C800FF + +/* RE_STATUS_1 */ +#define R367_QAM_RE_STATUS_1 0xF4C9 +#define F367_QAM_RECEIVE_STATUS_LH 0xF4C900FF + +/* RE_STATUS_2 */ +#define R367_QAM_RE_STATUS_2 0xF4CA +#define F367_QAM_RECEIVE_STATUS_HL 0xF4CA00FF + +/* RE_STATUS_3 */ +#define R367_QAM_RE_STATUS_3 0xF4CB +#define F367_QAM_RECEIVE_STATUS_HH 0xF4CB003F + +/* TS_STATUS_0 */ +#define R367_QAM_TS_STATUS_0 0xF4CC +#define F367_QAM_TS_STATUS_L 0xF4CC00FF + +/* TS_STATUS_1 */ +#define R367_QAM_TS_STATUS_1 0xF4CD +#define F367_QAM_TS_STATUS_H 0xF4CD007F + +/* TS_STATUS_2 */ +#define R367_QAM_TS_STATUS_2 0xF4CE +#define F367_QAM_ERROR 0xF4CE0080 +#define F367_QAM_EMERGENCY 0xF4CE0040 +#define F367_QAM_CRE_TS 0xF4CE0030 +#define F367_QAM_VER 0xF4CE000E +#define F367_QAM_M_LOCK 0xF4CE0001 + +/* TS_STATUS_3 */ +#define R367_QAM_TS_STATUS_3 0xF4CF +#define F367_QAM_UPDATE_READY 0xF4CF0080 +#define F367_QAM_END_FRAME_HEADER 0xF4CF0040 +#define F367_QAM_CONTCNT 0xF4CF0020 +#define F367_QAM_TS_IDENTIFIER_SEL 0xF4CF000F + +/* T_O_ID_0 */ +#define R367_QAM_T_O_ID_0 0xF4D0 +#define F367_QAM_ON_ID_I_L 0xF4D000FF + +/* T_O_ID_1 */ +#define R367_QAM_T_O_ID_1 0xF4D1 +#define F367_QAM_ON_ID_I_H 0xF4D100FF + +/* T_O_ID_2 */ +#define R367_QAM_T_O_ID_2 0xF4D2 +#define F367_QAM_TS_ID_I_L 0xF4D200FF + +/* T_O_ID_3 */ +#define R367_QAM_T_O_ID_3 0xF4D3 +#define F367_QAM_TS_ID_I_H 0xF4D300FF + diff --git a/frontends/stv0910_regs.h b/frontends/stv0910_regs.h index 16e922f..305f5da 100644 --- a/frontends/stv0910_regs.h +++ b/frontends/stv0910_regs.h @@ -1,3998 +1,3998 @@ -// @DVB-S/DVB-S2 STMicroelectronics STV0900 register defintions -// Author Manfred Völkel, August 2013 -// (c) 2013 Digital Devices GmbH Germany. All rights reserved - -// $Id: DD_STV0910Register.h 504 2013-09-02 23:02:14Z manfred $ - -/* ======================================================================= --- Registers Declaration (Internal ST, All Applications ) --- ------------------------- --- Each register (RSTV0910__XXXXX) is defined by its address (2 bytes). --- --- Each field (FSTV0910__XXXXX)is defined as follow: --- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] - ======================================================================= */ - -/*MID*/ -#define RSTV0910_MID 0xf100 -#define FSTV0910_MCHIP_IDENT 0xf10000f0 -#define FSTV0910_MRELEASE 0xf100000f - -/*DID*/ -#define RSTV0910_DID 0xf101 -#define FSTV0910_DEVICE_ID 0xf10100ff - -/*DACR1*/ -#define RSTV0910_DACR1 0xf113 -#define FSTV0910_DAC_MODE 0xf11300e0 -#define FSTV0910_DAC_VALUE1 0xf113000f - -/*DACR2*/ -#define RSTV0910_DACR2 0xf114 -#define FSTV0910_DAC_VALUE0 0xf11400ff - -/*PADCFG*/ -#define RSTV0910_PADCFG 0xf11a -#define FSTV0910_AGCRF2_OPD 0xf11a0008 -#define FSTV0910_AGCRF2_XOR 0xf11a0004 -#define FSTV0910_AGCRF1_OPD 0xf11a0002 -#define FSTV0910_AGCRF1_XOR 0xf11a0001 - -/*OUTCFG2*/ -#define RSTV0910_OUTCFG2 0xf11b -#define FSTV0910_TS2_ERROR_XOR 0xf11b0080 -#define FSTV0910_TS2_DPN_XOR 0xf11b0040 -#define FSTV0910_TS2_STROUT_XOR 0xf11b0020 -#define FSTV0910_TS2_CLOCKOUT_XOR 0xf11b0010 -#define FSTV0910_TS1_ERROR_XOR 0xf11b0008 -#define FSTV0910_TS1_DPN_XOR 0xf11b0004 -#define FSTV0910_TS1_STROUT_XOR 0xf11b0002 -#define FSTV0910_TS1_CLOCKOUT_XOR 0xf11b0001 - -/*OUTCFG*/ -#define RSTV0910_OUTCFG 0xf11c -#define FSTV0910_INV_DATA6 0xf11c0080 -#define FSTV0910_TS2_OUTSER_HZ 0xf11c0020 -#define FSTV0910_TS1_OUTSER_HZ 0xf11c0010 -#define FSTV0910_TS2_OUTPAR_HZ 0xf11c0008 -#define FSTV0910_TS1_OUTPAR_HZ 0xf11c0004 -#define FSTV0910_TS_SERDATA0 0xf11c0002 - -/*IRQSTATUS3*/ -#define RSTV0910_IRQSTATUS3 0xf120 -#define FSTV0910_SPLL_LOCK 0xf1200020 -#define FSTV0910_SSTREAM_LCK_1 0xf1200010 -#define FSTV0910_SSTREAM_LCK_2 0xf1200008 -#define FSTV0910_SDVBS1_PRF_2 0xf1200002 -#define FSTV0910_SDVBS1_PRF_1 0xf1200001 - -/*IRQSTATUS2*/ -#define RSTV0910_IRQSTATUS2 0xf121 -#define FSTV0910_SSPY_ENDSIM_1 0xf1210080 -#define FSTV0910_SSPY_ENDSIM_2 0xf1210040 -#define FSTV0910_SPKTDEL_ERROR_2 0xf1210010 -#define FSTV0910_SPKTDEL_LOCKB_2 0xf1210008 -#define FSTV0910_SPKTDEL_LOCK_2 0xf1210004 -#define FSTV0910_SPKTDEL_ERROR_1 0xf1210002 -#define FSTV0910_SPKTDEL_LOCKB_1 0xf1210001 - -/*IRQSTATUS1*/ -#define RSTV0910_IRQSTATUS1 0xf122 -#define FSTV0910_SPKTDEL_LOCK_1 0xf1220080 -#define FSTV0910_SFEC_LOCKB_2 0xf1220040 -#define FSTV0910_SFEC_LOCK_2 0xf1220020 -#define FSTV0910_SFEC_LOCKB_1 0xf1220010 -#define FSTV0910_SFEC_LOCK_1 0xf1220008 -#define FSTV0910_SDEMOD_LOCKB_2 0xf1220004 -#define FSTV0910_SDEMOD_LOCK_2 0xf1220002 -#define FSTV0910_SDEMOD_IRQ_2 0xf1220001 - -/*IRQSTATUS0*/ -#define RSTV0910_IRQSTATUS0 0xf123 -#define FSTV0910_SDEMOD_LOCKB_1 0xf1230080 -#define FSTV0910_SDEMOD_LOCK_1 0xf1230040 -#define FSTV0910_SDEMOD_IRQ_1 0xf1230020 -#define FSTV0910_SBCH_ERRFLAG 0xf1230010 -#define FSTV0910_SECW2_IRQ 0xf1230008 -#define FSTV0910_SDISEQC2_IRQ 0xf1230004 -#define FSTV0910_SECW1_IRQ 0xf1230002 -#define FSTV0910_SDISEQC1_IRQ 0xf1230001 - -/*IRQMASK3*/ -#define RSTV0910_IRQMASK3 0xf124 -#define FSTV0910_MPLL_LOCK 0xf1240020 -#define FSTV0910_MSTREAM_LCK_1 0xf1240010 -#define FSTV0910_MSTREAM_LCK_2 0xf1240008 -#define FSTV0910_MDVBS1_PRF_2 0xf1240002 -#define FSTV0910_MDVBS1_PRF_1 0xf1240001 - -/*IRQMASK2*/ -#define RSTV0910_IRQMASK2 0xf125 -#define FSTV0910_MSPY_ENDSIM_1 0xf1250080 -#define FSTV0910_MSPY_ENDSIM_2 0xf1250040 -#define FSTV0910_MPKTDEL_ERROR_2 0xf1250010 -#define FSTV0910_MPKTDEL_LOCKB_2 0xf1250008 -#define FSTV0910_MPKTDEL_LOCK_2 0xf1250004 -#define FSTV0910_MPKTDEL_ERROR_1 0xf1250002 -#define FSTV0910_MPKTDEL_LOCKB_1 0xf1250001 - -/*IRQMASK1*/ -#define RSTV0910_IRQMASK1 0xf126 -#define FSTV0910_MPKTDEL_LOCK_1 0xf1260080 -#define FSTV0910_MFEC_LOCKB_2 0xf1260040 -#define FSTV0910_MFEC_LOCK_2 0xf1260020 -#define FSTV0910_MFEC_LOCKB_1 0xf1260010 -#define FSTV0910_MFEC_LOCK_1 0xf1260008 -#define FSTV0910_MDEMOD_LOCKB_2 0xf1260004 -#define FSTV0910_MDEMOD_LOCK_2 0xf1260002 -#define FSTV0910_MDEMOD_IRQ_2 0xf1260001 - -/*IRQMASK0*/ -#define RSTV0910_IRQMASK0 0xf127 -#define FSTV0910_MDEMOD_LOCKB_1 0xf1270080 -#define FSTV0910_MDEMOD_LOCK_1 0xf1270040 -#define FSTV0910_MDEMOD_IRQ_1 0xf1270020 -#define FSTV0910_MBCH_ERRFLAG 0xf1270010 -#define FSTV0910_MECW2_IRQ 0xf1270008 -#define FSTV0910_MDISEQC2_IRQ 0xf1270004 -#define FSTV0910_MECW1_IRQ 0xf1270002 -#define FSTV0910_MDISEQC1_IRQ 0xf1270001 - -/*I2CCFG*/ -#define RSTV0910_I2CCFG 0xf129 -#define FSTV0910_I2C2_FASTMODE 0xf1290080 -#define FSTV0910_STATUS_WR2 0xf1290040 -#define FSTV0910_I2C2ADDR_INC 0xf1290030 -#define FSTV0910_I2C_FASTMODE 0xf1290008 -#define FSTV0910_STATUS_WR 0xf1290004 -#define FSTV0910_I2CADDR_INC 0xf1290003 - -/*P1_I2CRPT*/ -#define RSTV0910_P1_I2CRPT 0xf12a -#define FSTV0910_P1_I2CT_ON 0xf12a0080 -#define FSTV0910_P1_ENARPT_LEVEL 0xf12a0070 -#define FSTV0910_P1_SCLT_DELAY 0xf12a0008 -#define FSTV0910_P1_STOP_ENABLE 0xf12a0004 -#define FSTV0910_P1_STOP_SDAT2SDA 0xf12a0002 - -/*P2_I2CRPT*/ -#define RSTV0910_P2_I2CRPT 0xf12b -#define FSTV0910_P2_I2CT_ON 0xf12b0080 -#define FSTV0910_P2_ENARPT_LEVEL 0xf12b0070 -#define FSTV0910_P2_SCLT_DELAY 0xf12b0008 -#define FSTV0910_P2_STOP_ENABLE 0xf12b0004 -#define FSTV0910_P2_STOP_SDAT2SDA 0xf12b0002 - -/*GPIO0CFG*/ -#define RSTV0910_GPIO0CFG 0xf140 -#define FSTV0910_GPIO0_OPD 0xf1400080 -#define FSTV0910_GPIO0_CONFIG 0xf140007e -#define FSTV0910_GPIO0_XOR 0xf1400001 - -/*GPIO1CFG*/ -#define RSTV0910_GPIO1CFG 0xf141 -#define FSTV0910_GPIO1_OPD 0xf1410080 -#define FSTV0910_GPIO1_CONFIG 0xf141007e -#define FSTV0910_GPIO1_XOR 0xf1410001 - -/*GPIO2CFG*/ -#define RSTV0910_GPIO2CFG 0xf142 -#define FSTV0910_GPIO2_OPD 0xf1420080 -#define FSTV0910_GPIO2_CONFIG 0xf142007e -#define FSTV0910_GPIO2_XOR 0xf1420001 - -/*GPIO3CFG*/ -#define RSTV0910_GPIO3CFG 0xf143 -#define FSTV0910_GPIO3_OPD 0xf1430080 -#define FSTV0910_GPIO3_CONFIG 0xf143007e -#define FSTV0910_GPIO3_XOR 0xf1430001 - -/*GPIO4CFG*/ -#define RSTV0910_GPIO4CFG 0xf144 -#define FSTV0910_GPIO4_OPD 0xf1440080 -#define FSTV0910_GPIO4_CONFIG 0xf144007e -#define FSTV0910_GPIO4_XOR 0xf1440001 - -/*GPIO5CFG*/ -#define RSTV0910_GPIO5CFG 0xf145 -#define FSTV0910_GPIO5_OPD 0xf1450080 -#define FSTV0910_GPIO5_CONFIG 0xf145007e -#define FSTV0910_GPIO5_XOR 0xf1450001 - -/*GPIO6CFG*/ -#define RSTV0910_GPIO6CFG 0xf146 -#define FSTV0910_GPIO6_OPD 0xf1460080 -#define FSTV0910_GPIO6_CONFIG 0xf146007e -#define FSTV0910_GPIO6_XOR 0xf1460001 - -/*GPIO7CFG*/ -#define RSTV0910_GPIO7CFG 0xf147 -#define FSTV0910_GPIO7_OPD 0xf1470080 -#define FSTV0910_GPIO7_CONFIG 0xf147007e -#define FSTV0910_GPIO7_XOR 0xf1470001 - -/*GPIO8CFG*/ -#define RSTV0910_GPIO8CFG 0xf148 -#define FSTV0910_GPIO8_OPD 0xf1480080 -#define FSTV0910_GPIO8_CONFIG 0xf148007e -#define FSTV0910_GPIO8_XOR 0xf1480001 - -/*GPIO9CFG*/ -#define RSTV0910_GPIO9CFG 0xf149 -#define FSTV0910_GPIO9_OPD 0xf1490080 -#define FSTV0910_GPIO9_CONFIG 0xf149007e -#define FSTV0910_GPIO9_XOR 0xf1490001 - -/*GPIO10CFG*/ -#define RSTV0910_GPIO10CFG 0xf14a -#define FSTV0910_GPIO10_OPD 0xf14a0080 -#define FSTV0910_GPIO10_CONFIG 0xf14a007e -#define FSTV0910_GPIO10_XOR 0xf14a0001 - -/*GPIO11CFG*/ -#define RSTV0910_GPIO11CFG 0xf14b -#define FSTV0910_GPIO11_OPD 0xf14b0080 -#define FSTV0910_GPIO11_CONFIG 0xf14b007e -#define FSTV0910_GPIO11_XOR 0xf14b0001 - -/*GPIO12CFG*/ -#define RSTV0910_GPIO12CFG 0xf14c -#define FSTV0910_GPIO12_OPD 0xf14c0080 -#define FSTV0910_GPIO12_CONFIG 0xf14c007e -#define FSTV0910_GPIO12_XOR 0xf14c0001 - -/*GPIO13CFG*/ -#define RSTV0910_GPIO13CFG 0xf14d -#define FSTV0910_GPIO13_OPD 0xf14d0080 -#define FSTV0910_GPIO13_CONFIG 0xf14d007e -#define FSTV0910_GPIO13_XOR 0xf14d0001 - -/*GPIO14CFG*/ -#define RSTV0910_GPIO14CFG 0xf14e -#define FSTV0910_GPIO14_OPD 0xf14e0080 -#define FSTV0910_GPIO14_CONFIG 0xf14e007e -#define FSTV0910_GPIO14_XOR 0xf14e0001 - -/*GPIO15CFG*/ -#define RSTV0910_GPIO15CFG 0xf14f -#define FSTV0910_GPIO15_OPD 0xf14f0080 -#define FSTV0910_GPIO15_CONFIG 0xf14f007e -#define FSTV0910_GPIO15_XOR 0xf14f0001 - -/*GPIO16CFG*/ -#define RSTV0910_GPIO16CFG 0xf150 -#define FSTV0910_GPIO16_OPD 0xf1500080 -#define FSTV0910_GPIO16_CONFIG 0xf150007e -#define FSTV0910_GPIO16_XOR 0xf1500001 - -/*GPIO17CFG*/ -#define RSTV0910_GPIO17CFG 0xf151 -#define FSTV0910_GPIO17_OPD 0xf1510080 -#define FSTV0910_GPIO17_CONFIG 0xf151007e -#define FSTV0910_GPIO17_XOR 0xf1510001 - -/*GPIO18CFG*/ -#define RSTV0910_GPIO18CFG 0xf152 -#define FSTV0910_GPIO18_OPD 0xf1520080 -#define FSTV0910_GPIO18_CONFIG 0xf152007e -#define FSTV0910_GPIO18_XOR 0xf1520001 - -/*GPIO19CFG*/ -#define RSTV0910_GPIO19CFG 0xf153 -#define FSTV0910_GPIO19_OPD 0xf1530080 -#define FSTV0910_GPIO19_CONFIG 0xf153007e -#define FSTV0910_GPIO19_XOR 0xf1530001 - -/*GPIO20CFG*/ -#define RSTV0910_GPIO20CFG 0xf154 -#define FSTV0910_GPIO20_OPD 0xf1540080 -#define FSTV0910_GPIO20_CONFIG 0xf154007e -#define FSTV0910_GPIO20_XOR 0xf1540001 - -/*GPIO21CFG*/ -#define RSTV0910_GPIO21CFG 0xf155 -#define FSTV0910_GPIO21_OPD 0xf1550080 -#define FSTV0910_GPIO21_CONFIG 0xf155007e -#define FSTV0910_GPIO21_XOR 0xf1550001 - -/*GPIO22CFG*/ -#define RSTV0910_GPIO22CFG 0xf156 -#define FSTV0910_GPIO22_OPD 0xf1560080 -#define FSTV0910_GPIO22_CONFIG 0xf156007e -#define FSTV0910_GPIO22_XOR 0xf1560001 - -/*STRSTATUS1*/ -#define RSTV0910_STRSTATUS1 0xf16a -#define FSTV0910_STRSTATUS_SEL2 0xf16a00f0 -#define FSTV0910_STRSTATUS_SEL1 0xf16a000f - -/*STRSTATUS2*/ -#define RSTV0910_STRSTATUS2 0xf16b -#define FSTV0910_STRSTATUS_SEL4 0xf16b00f0 -#define FSTV0910_STRSTATUS_SEL3 0xf16b000f - -/*STRSTATUS3*/ -#define RSTV0910_STRSTATUS3 0xf16c -#define FSTV0910_STRSTATUS_SEL6 0xf16c00f0 -#define FSTV0910_STRSTATUS_SEL5 0xf16c000f - -/*FSKTFC2*/ -#define RSTV0910_FSKTFC2 0xf170 -#define FSTV0910_FSKT_KMOD 0xf17000fc -#define FSTV0910_FSKT_CAR2 0xf1700003 - -/*FSKTFC1*/ -#define RSTV0910_FSKTFC1 0xf171 -#define FSTV0910_FSKT_CAR1 0xf17100ff - -/*FSKTFC0*/ -#define RSTV0910_FSKTFC0 0xf172 -#define FSTV0910_FSKT_CAR0 0xf17200ff - -/*FSKTDELTAF1*/ -#define RSTV0910_FSKTDELTAF1 0xf173 -#define FSTV0910_FSKT_DELTAF1 0xf173000f - -/*FSKTDELTAF0*/ -#define RSTV0910_FSKTDELTAF0 0xf174 -#define FSTV0910_FSKT_DELTAF0 0xf17400ff - -/*FSKTCTRL*/ -#define RSTV0910_FSKTCTRL 0xf175 -#define FSTV0910_FSKT_PINSEL 0xf1750080 -#define FSTV0910_FSKT_EN_SGN 0xf1750040 -#define FSTV0910_FSKT_MOD_SGN 0xf1750020 -#define FSTV0910_FSKT_MOD_EN 0xf175001c -#define FSTV0910_FSKT_DACMODE 0xf1750003 - -/*FSKRFC2*/ -#define RSTV0910_FSKRFC2 0xf176 -#define FSTV0910_FSKR_DETSGN 0xf1760040 -#define FSTV0910_FSKR_OUTSGN 0xf1760020 -#define FSTV0910_FSKR_KAGC 0xf176001c -#define FSTV0910_FSKR_CAR2 0xf1760003 - -/*FSKRFC1*/ -#define RSTV0910_FSKRFC1 0xf177 -#define FSTV0910_FSKR_CAR1 0xf17700ff - -/*FSKRFC0*/ -#define RSTV0910_FSKRFC0 0xf178 -#define FSTV0910_FSKR_CAR0 0xf17800ff - -/*FSKRK1*/ -#define RSTV0910_FSKRK1 0xf179 -#define FSTV0910_FSKR_K1_EXP 0xf17900e0 -#define FSTV0910_FSKR_K1_MANT 0xf179001f - -/*FSKRK2*/ -#define RSTV0910_FSKRK2 0xf17a -#define FSTV0910_FSKR_K2_EXP 0xf17a00e0 -#define FSTV0910_FSKR_K2_MANT 0xf17a001f - -/*FSKRAGCR*/ -#define RSTV0910_FSKRAGCR 0xf17b -#define FSTV0910_FSKR_OUTCTL 0xf17b00c0 -#define FSTV0910_FSKR_AGC_REF 0xf17b003f - -/*FSKRAGC*/ -#define RSTV0910_FSKRAGC 0xf17c -#define FSTV0910_FSKR_AGC_ACCU 0xf17c00ff - -/*FSKRALPHA*/ -#define RSTV0910_FSKRALPHA 0xf17d -#define FSTV0910_FSKR_ALPHA_EXP 0xf17d001c -#define FSTV0910_FSKR_ALPHA_M 0xf17d0003 - -/*FSKRPLTH1*/ -#define RSTV0910_FSKRPLTH1 0xf17e -#define FSTV0910_FSKR_BETA 0xf17e00f0 -#define FSTV0910_FSKR_PLL_TRESH1 0xf17e000f - -/*FSKRPLTH0*/ -#define RSTV0910_FSKRPLTH0 0xf17f -#define FSTV0910_FSKR_PLL_TRESH0 0xf17f00ff - -/*FSKRDF1*/ -#define RSTV0910_FSKRDF1 0xf180 -#define FSTV0910_FSKR_OUT 0xf1800080 -#define FSTV0910_FSKR_STATE 0xf1800060 -#define FSTV0910_FSKR_DELTAF1 0xf180001f - -/*FSKRDF0*/ -#define RSTV0910_FSKRDF0 0xf181 -#define FSTV0910_FSKR_DELTAF0 0xf18100ff - -/*FSKRSTEPP*/ -#define RSTV0910_FSKRSTEPP 0xf182 -#define FSTV0910_FSKR_STEP_PLUS 0xf18200ff - -/*FSKRSTEPM*/ -#define RSTV0910_FSKRSTEPM 0xf183 -#define FSTV0910_FSKR_STEP_MINUS 0xf18300ff - -/*FSKRDET1*/ -#define RSTV0910_FSKRDET1 0xf184 -#define FSTV0910_FSKR_DETECT 0xf1840080 -#define FSTV0910_FSKR_CARDET_ACCU1 0xf184000f - -/*FSKRDET0*/ -#define RSTV0910_FSKRDET0 0xf185 -#define FSTV0910_FSKR_CARDET_ACCU0 0xf18500ff - -/*FSKRDTH1*/ -#define RSTV0910_FSKRDTH1 0xf186 -#define FSTV0910_FSKR_CARLOSS_THRESH1 0xf18600f0 -#define FSTV0910_FSKR_CARDET_THRESH1 0xf186000f - -/*FSKRDTH0*/ -#define RSTV0910_FSKRDTH0 0xf187 -#define FSTV0910_FSKR_CARDET_THRESH0 0xf18700ff - -/*FSKRLOSS*/ -#define RSTV0910_FSKRLOSS 0xf188 -#define FSTV0910_FSKR_CARLOSS_THRESH0 0xf18800ff - -/*NCOARSE*/ -#define RSTV0910_NCOARSE 0xf1b3 -#define FSTV0910_CP 0xf1b300f8 -#define FSTV0910_IDF 0xf1b30007 - -/*NCOARSE1*/ -#define RSTV0910_NCOARSE1 0xf1b4 -#define FSTV0910_N_DIV 0xf1b400ff - -/*NCOARSE2*/ -#define RSTV0910_NCOARSE2 0xf1b5 -#define FSTV0910_ODF 0xf1b5003f - -/*SYNTCTRL*/ -#define RSTV0910_SYNTCTRL 0xf1b6 -#define FSTV0910_STANDBY 0xf1b60080 -#define FSTV0910_BYPASSPLLCORE 0xf1b60040 -#define FSTV0910_STOP_PLL 0xf1b60008 -#define FSTV0910_OSCI_E 0xf1b60002 - -/*FILTCTRL*/ -#define RSTV0910_FILTCTRL 0xf1b7 -#define FSTV0910_INV_CLKFSK 0xf1b70002 -#define FSTV0910_BYPASS_APPLI 0xf1b70001 - -/*PLLSTAT*/ -#define RSTV0910_PLLSTAT 0xf1b8 -#define FSTV0910_PLL_BIST_END 0xf1b80004 -#define FSTV0910_PLLLOCK 0xf1b80001 - -/*STOPCLK1*/ -#define RSTV0910_STOPCLK1 0xf1c2 -#define FSTV0910_INV_CLKADCI2 0xf1c20004 -#define FSTV0910_INV_CLKADCI1 0xf1c20001 - -/*STOPCLK2*/ -#define RSTV0910_STOPCLK2 0xf1c3 -#define FSTV0910_STOP_DVBS2FEC2 0xf1c30020 -#define FSTV0910_STOP_DVBS2FEC 0xf1c30010 -#define FSTV0910_STOP_DVBS1FEC2 0xf1c30008 -#define FSTV0910_STOP_DVBS1FEC 0xf1c30004 -#define FSTV0910_STOP_DEMOD2 0xf1c30002 -#define FSTV0910_STOP_DEMOD 0xf1c30001 - -/*PREGCTL*/ -#define RSTV0910_PREGCTL 0xf1c8 -#define FSTV0910_REG3V3TO2V5_POFF 0xf1c80080 - -/*TSTTNR0*/ -#define RSTV0910_TSTTNR0 0xf1df -#define FSTV0910_FSK_PON 0xf1df0004 -#define FSTV0910_FSK_OPENLOOP 0xf1df0002 - -/*TSTTNR1*/ -#define RSTV0910_TSTTNR1 0xf1e0 -#define FSTV0910_BYPASS_ADC1 0xf1e00080 -#define FSTV0910_INVADC1_CKOUT 0xf1e00040 -#define FSTV0910_SELIQSRC1 0xf1e00030 -#define FSTV0910_DEMOD2_SELADC 0xf1e00008 -#define FSTV0910_DEMOD1_SELADC 0xf1e00004 -#define FSTV0910_ADC1_PON 0xf1e00002 - -/*TSTTNR2*/ -#define RSTV0910_TSTTNR2 0xf1e1 -#define FSTV0910_I2C_DISEQC_BYPASS 0xf1e10080 -#define FSTV0910_I2C_DISEQC_ENCH 0xf1e10040 -#define FSTV0910_I2C_DISEQC_PON 0xf1e10020 -#define FSTV0910_DISEQC_CLKDIV 0xf1e1000f - -/*TSTTNR3*/ -#define RSTV0910_TSTTNR3 0xf1e2 -#define FSTV0910_BYPASS_ADC2 0xf1e20080 -#define FSTV0910_INVADC2_CKOUT 0xf1e20040 -#define FSTV0910_SELIQSRC2 0xf1e20030 -#define FSTV0910_ADC2_PON 0xf1e20002 - -/*P2_IQCONST*/ -#define RSTV0910_P2_IQCONST 0xf200 -#define FSTV0910_P2_CONSTEL_SELECT 0xf2000060 -#define FSTV0910_P2_IQSYMB_SEL 0xf200001f - -/*P2_NOSCFG*/ -#define RSTV0910_P2_NOSCFG 0xf201 -#define FSTV0910_P2_DIS_ACMRATIO 0xf2010080 -#define FSTV0910_P2_NOSIN_EGALSEL 0xf2010040 -#define FSTV0910_P2_DUMMYPL_NOSDATA 0xf2010020 -#define FSTV0910_P2_NOSPLH_BETA 0xf2010018 -#define FSTV0910_P2_NOSDATA_BETA 0xf2010007 - -/*P2_ISYMB*/ -#define RSTV0910_P2_ISYMB 0xf202 -#define FSTV0910_P2_I_SYMBOL 0xf20201ff - -/*P2_QSYMB*/ -#define RSTV0910_P2_QSYMB 0xf203 -#define FSTV0910_P2_Q_SYMBOL 0xf20301ff - -/*P2_AGC1CFG*/ -#define RSTV0910_P2_AGC1CFG 0xf204 -#define FSTV0910_P2_DC_FROZEN 0xf2040080 -#define FSTV0910_P2_DC_CORRECT 0xf2040040 -#define FSTV0910_P2_AMM_FROZEN 0xf2040020 -#define FSTV0910_P2_AMM_CORRECT 0xf2040010 -#define FSTV0910_P2_QUAD_FROZEN 0xf2040008 -#define FSTV0910_P2_QUAD_CORRECT 0xf2040004 -#define FSTV0910_P2_DCCOMP_SLOW 0xf2040002 -#define FSTV0910_P2_IQMISM_SLOW 0xf2040001 - -/*P2_AGC1CN*/ -#define RSTV0910_P2_AGC1CN 0xf206 -#define FSTV0910_P2_AGC1_LOCKED 0xf2060080 -#define FSTV0910_P2_AGC1_OVERFLOW 0xf2060040 -#define FSTV0910_P2_AGC1_NOSLOWLK 0xf2060020 -#define FSTV0910_P2_AGC1_MINPOWER 0xf2060010 -#define FSTV0910_P2_AGCOUT_FAST 0xf2060008 -#define FSTV0910_P2_AGCIQ_BETA 0xf2060007 - -/*P2_AGC1REF*/ -#define RSTV0910_P2_AGC1REF 0xf207 -#define FSTV0910_P2_AGCIQ_REF 0xf20700ff - -/*P2_IDCCOMP*/ -#define RSTV0910_P2_IDCCOMP 0xf208 -#define FSTV0910_P2_IAVERAGE_ADJ 0xf20801ff - -/*P2_QDCCOMP*/ -#define RSTV0910_P2_QDCCOMP 0xf209 -#define FSTV0910_P2_QAVERAGE_ADJ 0xf20901ff - -/*P2_POWERI*/ -#define RSTV0910_P2_POWERI 0xf20a -#define FSTV0910_P2_POWER_I 0xf20a00ff - -/*P2_POWERQ*/ -#define RSTV0910_P2_POWERQ 0xf20b -#define FSTV0910_P2_POWER_Q 0xf20b00ff - -/*P2_AGC1AMM*/ -#define RSTV0910_P2_AGC1AMM 0xf20c -#define FSTV0910_P2_AMM_VALUE 0xf20c00ff - -/*P2_AGC1QUAD*/ -#define RSTV0910_P2_AGC1QUAD 0xf20d -#define FSTV0910_P2_QUAD_VALUE 0xf20d01ff - -/*P2_AGCIQIN1*/ -#define RSTV0910_P2_AGCIQIN1 0xf20e -#define FSTV0910_P2_AGCIQ_VALUE1 0xf20e00ff - -/*P2_AGCIQIN0*/ -#define RSTV0910_P2_AGCIQIN0 0xf20f -#define FSTV0910_P2_AGCIQ_VALUE0 0xf20f00ff - -/*P2_DEMOD*/ -#define RSTV0910_P2_DEMOD 0xf210 -#define FSTV0910_P2_MANUALS2_ROLLOFF 0xf2100080 -#define FSTV0910_P2_SPECINV_CONTROL 0xf2100030 -#define FSTV0910_P2_MANUALSX_ROLLOFF 0xf2100004 -#define FSTV0910_P2_ROLLOFF_CONTROL 0xf2100003 - -/*P2_DMDMODCOD*/ -#define RSTV0910_P2_DMDMODCOD 0xf211 -#define FSTV0910_P2_MANUAL_MODCOD 0xf2110080 -#define FSTV0910_P2_DEMOD_MODCOD 0xf211007c -#define FSTV0910_P2_DEMOD_TYPE 0xf2110003 - -/*P2_DSTATUS*/ -#define RSTV0910_P2_DSTATUS 0xf212 -#define FSTV0910_P2_CAR_LOCK 0xf2120080 -#define FSTV0910_P2_TMGLOCK_QUALITY 0xf2120060 -#define FSTV0910_P2_SDVBS1_ENABLE 0xf2120010 -#define FSTV0910_P2_LOCK_DEFINITIF 0xf2120008 -#define FSTV0910_P2_TIMING_IS_LOCKED 0xf2120004 -#define FSTV0910_P2_DEMOD_SYSCFG 0xf2120002 -#define FSTV0910_P2_OVADC_DETECT 0xf2120001 - -/*P2_DSTATUS2*/ -#define RSTV0910_P2_DSTATUS2 0xf213 -#define FSTV0910_P2_DEMOD_DELOCK 0xf2130080 -#define FSTV0910_P2_DEMOD_TIMEOUT 0xf2130040 -#define FSTV0910_P2_MODCODRQ_SYNCTAG 0xf2130020 -#define FSTV0910_P2_POLYPH_SATEVENT 0xf2130010 -#define FSTV0910_P2_AGC1_NOSIGNALACK 0xf2130008 -#define FSTV0910_P2_AGC2_OVERFLOW 0xf2130004 -#define FSTV0910_P2_CFR_OVERFLOW 0xf2130002 -#define FSTV0910_P2_GAMMA_OVERUNDER 0xf2130001 - -/*P2_DMDCFGMD*/ -#define RSTV0910_P2_DMDCFGMD 0xf214 -#define FSTV0910_P2_DVBS2_ENABLE 0xf2140080 -#define FSTV0910_P2_DVBS1_ENABLE 0xf2140040 -#define FSTV0910_P2_SCAN_ENABLE 0xf2140010 -#define FSTV0910_P2_CFR_AUTOSCAN 0xf2140008 -#define FSTV0910_P2_NOFORCE_RELOCK 0xf2140004 -#define FSTV0910_P2_TUN_RNG 0xf2140003 - -/*P2_DMDCFG2*/ -#define RSTV0910_P2_DMDCFG2 0xf215 -#define FSTV0910_P2_AGC1_WAITLOCK 0xf2150080 -#define FSTV0910_P2_S1S2_SEQUENTIAL 0xf2150040 -#define FSTV0910_P2_BLINDPEA_MODE 0xf2150020 -#define FSTV0910_P2_INFINITE_RELOCK 0xf2150010 -#define FSTV0910_P2_BWOFFSET_COLDWARM 0xf2150008 -#define FSTV0910_P2_TMGLOCK_NSCANSTOP 0xf2150004 -#define FSTV0910_P2_COARSE_LK3MODE 0xf2150002 -#define FSTV0910_P2_COARSE_LK2MODE 0xf2150001 - -/*P2_DMDISTATE*/ -#define RSTV0910_P2_DMDISTATE 0xf216 -#define FSTV0910_P2_I2C_NORESETDMODE 0xf2160080 -#define FSTV0910_P2_FORCE_ETAPED 0xf2160040 -#define FSTV0910_P2_SDMDRST_DIRCLK 0xf2160020 -#define FSTV0910_P2_I2C_DEMOD_MODE 0xf216001f - -/*P2_DMDT0M*/ -#define RSTV0910_P2_DMDT0M 0xf217 -#define FSTV0910_P2_DMDT0_MIN 0xf21700ff - -/*P2_DMDSTATE*/ -#define RSTV0910_P2_DMDSTATE 0xf21b -#define FSTV0910_P2_DEMOD_LOCKED 0xf21b0080 -#define FSTV0910_P2_HEADER_MODE 0xf21b0060 -#define FSTV0910_P2_DEMOD_MODE 0xf21b001f - -/*P2_DMDFLYW*/ -#define RSTV0910_P2_DMDFLYW 0xf21c -#define FSTV0910_P2_I2C_IRQVAL 0xf21c00f0 -#define FSTV0910_P2_FLYWHEEL_CPT 0xf21c000f - -/*P2_DSTATUS3*/ -#define RSTV0910_P2_DSTATUS3 0xf21d -#define FSTV0910_P2_CFR_ZIGZAG 0xf21d0080 -#define FSTV0910_P2_DEMOD_CFGMODE 0xf21d0060 -#define FSTV0910_P2_GAMMA_LOWBAUDRATE 0xf21d0010 -#define FSTV0910_P2_RELOCK_MODE 0xf21d0008 -#define FSTV0910_P2_DEMOD_FAIL 0xf21d0004 -#define FSTV0910_P2_ETAPE1A_DVBXMEM 0xf21d0003 - -/*P2_DMDCFG3*/ -#define RSTV0910_P2_DMDCFG3 0xf21e -#define FSTV0910_P2_DVBS1_TMGWAIT 0xf21e0080 -#define FSTV0910_P2_NO_BWCENTERING 0xf21e0040 -#define FSTV0910_P2_INV_SEQSRCH 0xf21e0020 -#define FSTV0910_P2_DIS_SFRUPLOW_TRK 0xf21e0010 -#define FSTV0910_P2_NOSTOP_FIFOFULL 0xf21e0008 -#define FSTV0910_P2_LOCKTIME_MODE 0xf21e0007 - -/*P2_DMDCFG4*/ -#define RSTV0910_P2_DMDCFG4 0xf21f -#define FSTV0910_P2_DIS_VITLOCK 0xf21f0080 -#define FSTV0910_P2_S1S2TOUT_FAST 0xf21f0040 -#define FSTV0910_P2_DEMOD_FASTLOCK 0xf21f0020 -#define FSTV0910_P2_S1HIER_ENABLE 0xf21f0010 -#define FSTV0910_P2_TUNER_NRELAUNCH 0xf21f0008 -#define FSTV0910_P2_DIS_CLKENABLE 0xf21f0004 -#define FSTV0910_P2_DIS_HDRDIVLOCK 0xf21f0002 -#define FSTV0910_P2_NO_TNRWBINIT 0xf21f0001 - -/*P2_CORRELMANT*/ -#define RSTV0910_P2_CORRELMANT 0xf220 -#define FSTV0910_P2_CORREL_MANT 0xf22000ff - -/*P2_CORRELABS*/ -#define RSTV0910_P2_CORRELABS 0xf221 -#define FSTV0910_P2_CORREL_ABS 0xf22100ff - -/*P2_CORRELEXP*/ -#define RSTV0910_P2_CORRELEXP 0xf222 -#define FSTV0910_P2_CORREL_ABSEXP 0xf22200f0 -#define FSTV0910_P2_CORREL_EXP 0xf222000f - -/*P2_PLHMODCOD*/ -#define RSTV0910_P2_PLHMODCOD 0xf224 -#define FSTV0910_P2_SPECINV_DEMOD 0xf2240080 -#define FSTV0910_P2_PLH_MODCOD 0xf224007c -#define FSTV0910_P2_PLH_TYPE 0xf2240003 - -/*P2_DMDREG*/ -#define RSTV0910_P2_DMDREG 0xf225 -#define FSTV0910_P2_EXTPSK_MODE 0xf2250080 -#define FSTV0910_P2_HIER_SHORTFRAME 0xf2250002 -#define FSTV0910_P2_DECIM_PLFRAMES 0xf2250001 - -/*P2_AGC2O*/ -#define RSTV0910_P2_AGC2O 0xf22c -#define FSTV0910_P2_CSTENV_MODE 0xf22c00c0 -#define FSTV0910_P2_AGC2_LKSQRT 0xf22c0020 -#define FSTV0910_P2_AGC2_LKMODE 0xf22c0010 -#define FSTV0910_P2_AGC2_LKEQUA 0xf22c0008 -#define FSTV0910_P2_AGC2_COEF 0xf22c0007 - -/*P2_AGC2REF*/ -#define RSTV0910_P2_AGC2REF 0xf22d -#define FSTV0910_P2_AGC2_REF 0xf22d00ff - -/*P2_AGC1ADJ*/ -#define RSTV0910_P2_AGC1ADJ 0xf22e -#define FSTV0910_P2_AGC1ADJ_MANUAL 0xf22e0080 -#define FSTV0910_P2_AGC1_ADJUSTED 0xf22e007f - -/*P2_AGC2I1*/ -#define RSTV0910_P2_AGC2I1 0xf236 -#define FSTV0910_P2_AGC2_INTEGRATOR1 0xf23600ff - -/*P2_AGC2I0*/ -#define RSTV0910_P2_AGC2I0 0xf237 -#define FSTV0910_P2_AGC2_INTEGRATOR0 0xf23700ff - -/*P2_CARCFG*/ -#define RSTV0910_P2_CARCFG 0xf238 -#define FSTV0910_P2_CFRUPLOW_AUTO 0xf2380080 -#define FSTV0910_P2_CFRUPLOW_TEST 0xf2380040 -#define FSTV0910_P2_WIDE_FREQDET 0xf2380020 -#define FSTV0910_P2_CARHDR_NODIV8 0xf2380010 -#define FSTV0910_P2_I2C_ROTA 0xf2380008 -#define FSTV0910_P2_ROTAON 0xf2380004 -#define FSTV0910_P2_PH_DET_ALGO 0xf2380003 - -/*P2_ACLC*/ -#define RSTV0910_P2_ACLC 0xf239 -#define FSTV0910_P2_CARS1_ANOSAUTO 0xf2390040 -#define FSTV0910_P2_CAR_ALPHA_MANT 0xf2390030 -#define FSTV0910_P2_CAR_ALPHA_EXP 0xf239000f - -/*P2_BCLC*/ -#define RSTV0910_P2_BCLC 0xf23a -#define FSTV0910_P2_CARS1_BNOSAUTO 0xf23a0040 -#define FSTV0910_P2_CAR_BETA_MANT 0xf23a0030 -#define FSTV0910_P2_CAR_BETA_EXP 0xf23a000f - -/*P2_CARFREQ*/ -#define RSTV0910_P2_CARFREQ 0xf23d -#define FSTV0910_P2_KC_COARSE_EXP 0xf23d00f0 -#define FSTV0910_P2_BETA_FREQ 0xf23d000f - -/*P2_CARHDR*/ -#define RSTV0910_P2_CARHDR 0xf23e -#define FSTV0910_P2_K_FREQ_HDR 0xf23e00ff - -/*P2_LDT*/ -#define RSTV0910_P2_LDT 0xf23f -#define FSTV0910_P2_CARLOCK_THRES 0xf23f01ff - -/*P2_LDT2*/ -#define RSTV0910_P2_LDT2 0xf240 -#define FSTV0910_P2_CARLOCK_THRES2 0xf24001ff - -/*P2_CFRICFG*/ -#define RSTV0910_P2_CFRICFG 0xf241 -#define FSTV0910_P2_CFRINIT_UNVALRNG 0xf2410080 -#define FSTV0910_P2_CFRINIT_LUNVALCPT 0xf2410040 -#define FSTV0910_P2_CFRINIT_ABORTDBL 0xf2410020 -#define FSTV0910_P2_CFRINIT_ABORTPRED 0xf2410010 -#define FSTV0910_P2_CFRINIT_UNVALSKIP 0xf2410008 -#define FSTV0910_P2_CFRINIT_CSTINC 0xf2410004 -#define FSTV0910_P2_CFRIROLL_GARDER 0xf2410002 -#define FSTV0910_P2_NEG_CFRSTEP 0xf2410001 - -/*P2_CFRUP1*/ -#define RSTV0910_P2_CFRUP1 0xf242 -#define FSTV0910_P2_CFR_UP1 0xf24201ff - -/*P2_CFRUP0*/ -#define RSTV0910_P2_CFRUP0 0xf243 -#define FSTV0910_P2_CFR_UP0 0xf24300ff - -/*P2_CFRIBASE1*/ -#define RSTV0910_P2_CFRIBASE1 0xf244 -#define FSTV0910_P2_CFRINIT_BASE1 0xf24400ff - -/*P2_CFRIBASE0*/ -#define RSTV0910_P2_CFRIBASE0 0xf245 -#define FSTV0910_P2_CFRINIT_BASE0 0xf24500ff - -/*P2_CFRLOW1*/ -#define RSTV0910_P2_CFRLOW1 0xf246 -#define FSTV0910_P2_CFR_LOW1 0xf24601ff - -/*P2_CFRLOW0*/ -#define RSTV0910_P2_CFRLOW0 0xf247 -#define FSTV0910_P2_CFR_LOW0 0xf24700ff - -/*P2_CFRINIT1*/ -#define RSTV0910_P2_CFRINIT1 0xf248 -#define FSTV0910_P2_CFR_INIT1 0xf24801ff - -/*P2_CFRINIT0*/ -#define RSTV0910_P2_CFRINIT0 0xf249 -#define FSTV0910_P2_CFR_INIT0 0xf24900ff - -/*P2_CFRINC1*/ -#define RSTV0910_P2_CFRINC1 0xf24a -#define FSTV0910_P2_MANUAL_CFRINC 0xf24a0080 -#define FSTV0910_P2_CFR_INC1 0xf24a003f - -/*P2_CFRINC0*/ -#define RSTV0910_P2_CFRINC0 0xf24b -#define FSTV0910_P2_CFR_INC0 0xf24b00ff - -/*P2_CFR2*/ -#define RSTV0910_P2_CFR2 0xf24c -#define FSTV0910_P2_CAR_FREQ2 0xf24c01ff - -/*P2_CFR1*/ -#define RSTV0910_P2_CFR1 0xf24d -#define FSTV0910_P2_CAR_FREQ1 0xf24d00ff - -/*P2_CFR0*/ -#define RSTV0910_P2_CFR0 0xf24e -#define FSTV0910_P2_CAR_FREQ0 0xf24e00ff - -/*P2_LDI*/ -#define RSTV0910_P2_LDI 0xf24f -#define FSTV0910_P2_LOCK_DET_INTEGR 0xf24f01ff - -/*P2_TMGCFG*/ -#define RSTV0910_P2_TMGCFG 0xf250 -#define FSTV0910_P2_TMGLOCK_BETA 0xf25000c0 -#define FSTV0910_P2_DO_TIMING_CORR 0xf2500010 -#define FSTV0910_P2_MANUAL_SCAN 0xf250000c -#define FSTV0910_P2_TMG_MINFREQ 0xf2500003 - -/*P2_RTC*/ -#define RSTV0910_P2_RTC 0xf251 -#define FSTV0910_P2_TMGALPHA_EXP 0xf25100f0 -#define FSTV0910_P2_TMGBETA_EXP 0xf251000f - -/*P2_RTCS2*/ -#define RSTV0910_P2_RTCS2 0xf252 -#define FSTV0910_P2_TMGALPHAS2_EXP 0xf25200f0 -#define FSTV0910_P2_TMGBETAS2_EXP 0xf252000f - -/*P2_TMGTHRISE*/ -#define RSTV0910_P2_TMGTHRISE 0xf253 -#define FSTV0910_P2_TMGLOCK_THRISE 0xf25300ff - -/*P2_TMGTHFALL*/ -#define RSTV0910_P2_TMGTHFALL 0xf254 -#define FSTV0910_P2_TMGLOCK_THFALL 0xf25400ff - -/*P2_SFRUPRATIO*/ -#define RSTV0910_P2_SFRUPRATIO 0xf255 -#define FSTV0910_P2_SFR_UPRATIO 0xf25500ff - -/*P2_SFRLOWRATIO*/ -#define RSTV0910_P2_SFRLOWRATIO 0xf256 -#define FSTV0910_P2_SFR_LOWRATIO 0xf25600ff - -/*P2_KTTMG*/ -#define RSTV0910_P2_KTTMG 0xf257 -#define FSTV0910_P2_KT_TMG_EXP 0xf25700f0 - -/*P2_KREFTMG*/ -#define RSTV0910_P2_KREFTMG 0xf258 -#define FSTV0910_P2_KREF_TMG 0xf25800ff - -/*P2_SFRSTEP*/ -#define RSTV0910_P2_SFRSTEP 0xf259 -#define FSTV0910_P2_SFR_SCANSTEP 0xf25900f0 -#define FSTV0910_P2_SFR_CENTERSTEP 0xf259000f - -/*P2_TMGCFG2*/ -#define RSTV0910_P2_TMGCFG2 0xf25a -#define FSTV0910_P2_KREFTMG2_DECMODE 0xf25a00c0 -#define FSTV0910_P2_DIS_AUTOSAMP 0xf25a0008 -#define FSTV0910_P2_SCANINIT_QUART 0xf25a0004 -#define FSTV0910_P2_NOTMG_DVBS1DERAT 0xf25a0002 -#define FSTV0910_P2_SFRRATIO_FINE 0xf25a0001 - -/*P2_KREFTMG2*/ -#define RSTV0910_P2_KREFTMG2 0xf25b -#define FSTV0910_P2_KREF_TMG2 0xf25b00ff - -/*P2_TMGCFG3*/ -#define RSTV0910_P2_TMGCFG3 0xf25d -#define FSTV0910_P2_CFRINC_MODE 0xf25d0070 -#define FSTV0910_P2_CONT_TMGCENTER 0xf25d0008 -#define FSTV0910_P2_AUTO_GUP 0xf25d0004 -#define FSTV0910_P2_AUTO_GLOW 0xf25d0002 -#define FSTV0910_P2_SFRVAL_MINMODE 0xf25d0001 - -/*P2_SFRINIT1*/ -#define RSTV0910_P2_SFRINIT1 0xf25e -#define FSTV0910_P2_SFR_INIT1 0xf25e00ff - -/*P2_SFRINIT0*/ -#define RSTV0910_P2_SFRINIT0 0xf25f -#define FSTV0910_P2_SFR_INIT0 0xf25f00ff - -/*P2_SFRUP1*/ -#define RSTV0910_P2_SFRUP1 0xf260 -#define FSTV0910_P2_SYMB_FREQ_UP1 0xf26000ff - -/*P2_SFRUP0*/ -#define RSTV0910_P2_SFRUP0 0xf261 -#define FSTV0910_P2_SYMB_FREQ_UP0 0xf26100ff - -/*P2_SFRLOW1*/ -#define RSTV0910_P2_SFRLOW1 0xf262 -#define FSTV0910_P2_SYMB_FREQ_LOW1 0xf26200ff - -/*P2_SFRLOW0*/ -#define RSTV0910_P2_SFRLOW0 0xf263 -#define FSTV0910_P2_SYMB_FREQ_LOW0 0xf26300ff - -/*P2_SFR3*/ -#define RSTV0910_P2_SFR3 0xf264 -#define FSTV0910_P2_SYMB_FREQ3 0xf26400ff - -/*P2_SFR2*/ -#define RSTV0910_P2_SFR2 0xf265 -#define FSTV0910_P2_SYMB_FREQ2 0xf26500ff - -/*P2_SFR1*/ -#define RSTV0910_P2_SFR1 0xf266 -#define FSTV0910_P2_SYMB_FREQ1 0xf26600ff - -/*P2_SFR0*/ -#define RSTV0910_P2_SFR0 0xf267 -#define FSTV0910_P2_SYMB_FREQ0 0xf26700ff - -/*P2_TMGREG2*/ -#define RSTV0910_P2_TMGREG2 0xf268 -#define FSTV0910_P2_TMGREG2 0xf26800ff - -/*P2_TMGREG1*/ -#define RSTV0910_P2_TMGREG1 0xf269 -#define FSTV0910_P2_TMGREG1 0xf26900ff - -/*P2_TMGREG0*/ -#define RSTV0910_P2_TMGREG0 0xf26a -#define FSTV0910_P2_TMGREG0 0xf26a00ff - -/*P2_TMGLOCK1*/ -#define RSTV0910_P2_TMGLOCK1 0xf26b -#define FSTV0910_P2_TMGLOCK_LEVEL1 0xf26b01ff - -/*P2_TMGLOCK0*/ -#define RSTV0910_P2_TMGLOCK0 0xf26c -#define FSTV0910_P2_TMGLOCK_LEVEL0 0xf26c00ff - -/*P2_TMGOBS*/ -#define RSTV0910_P2_TMGOBS 0xf26d -#define FSTV0910_P2_ROLLOFF_STATUS 0xf26d00c0 -#define FSTV0910_P2_SCAN_SIGN 0xf26d0030 -#define FSTV0910_P2_TMG_SCANNING 0xf26d0008 -#define FSTV0910_P2_CHCENTERING_MODE 0xf26d0004 -#define FSTV0910_P2_TMG_SCANFAIL 0xf26d0002 - -/*P2_EQUALCFG*/ -#define RSTV0910_P2_EQUALCFG 0xf26f -#define FSTV0910_P2_NOTMG_NEGALWAIT 0xf26f0080 -#define FSTV0910_P2_EQUAL_ON 0xf26f0040 -#define FSTV0910_P2_SEL_EQUALCOR 0xf26f0038 -#define FSTV0910_P2_MU_EQUALDFE 0xf26f0007 - -/*P2_EQUAI1*/ -#define RSTV0910_P2_EQUAI1 0xf270 -#define FSTV0910_P2_EQUA_ACCI1 0xf27001ff - -/*P2_EQUAQ1*/ -#define RSTV0910_P2_EQUAQ1 0xf271 -#define FSTV0910_P2_EQUA_ACCQ1 0xf27101ff - -/*P2_EQUAI2*/ -#define RSTV0910_P2_EQUAI2 0xf272 -#define FSTV0910_P2_EQUA_ACCI2 0xf27201ff - -/*P2_EQUAQ2*/ -#define RSTV0910_P2_EQUAQ2 0xf273 -#define FSTV0910_P2_EQUA_ACCQ2 0xf27301ff - -/*P2_EQUAI3*/ -#define RSTV0910_P2_EQUAI3 0xf274 -#define FSTV0910_P2_EQUA_ACCI3 0xf27401ff - -/*P2_EQUAQ3*/ -#define RSTV0910_P2_EQUAQ3 0xf275 -#define FSTV0910_P2_EQUA_ACCQ3 0xf27501ff - -/*P2_EQUAI4*/ -#define RSTV0910_P2_EQUAI4 0xf276 -#define FSTV0910_P2_EQUA_ACCI4 0xf27601ff - -/*P2_EQUAQ4*/ -#define RSTV0910_P2_EQUAQ4 0xf277 -#define FSTV0910_P2_EQUA_ACCQ4 0xf27701ff - -/*P2_EQUAI5*/ -#define RSTV0910_P2_EQUAI5 0xf278 -#define FSTV0910_P2_EQUA_ACCI5 0xf27801ff - -/*P2_EQUAQ5*/ -#define RSTV0910_P2_EQUAQ5 0xf279 -#define FSTV0910_P2_EQUA_ACCQ5 0xf27901ff - -/*P2_EQUAI6*/ -#define RSTV0910_P2_EQUAI6 0xf27a -#define FSTV0910_P2_EQUA_ACCI6 0xf27a01ff - -/*P2_EQUAQ6*/ -#define RSTV0910_P2_EQUAQ6 0xf27b -#define FSTV0910_P2_EQUA_ACCQ6 0xf27b01ff - -/*P2_EQUAI7*/ -#define RSTV0910_P2_EQUAI7 0xf27c -#define FSTV0910_P2_EQUA_ACCI7 0xf27c01ff - -/*P2_EQUAQ7*/ -#define RSTV0910_P2_EQUAQ7 0xf27d -#define FSTV0910_P2_EQUA_ACCQ7 0xf27d01ff - -/*P2_EQUAI8*/ -#define RSTV0910_P2_EQUAI8 0xf27e -#define FSTV0910_P2_EQUA_ACCI8 0xf27e01ff - -/*P2_EQUAQ8*/ -#define RSTV0910_P2_EQUAQ8 0xf27f -#define FSTV0910_P2_EQUA_ACCQ8 0xf27f01ff - -/*P2_NNOSDATAT1*/ -#define RSTV0910_P2_NNOSDATAT1 0xf280 -#define FSTV0910_P2_NOSDATAT_NORMED1 0xf28000ff - -/*P2_NNOSDATAT0*/ -#define RSTV0910_P2_NNOSDATAT0 0xf281 -#define FSTV0910_P2_NOSDATAT_NORMED0 0xf28100ff - -/*P2_NNOSDATA1*/ -#define RSTV0910_P2_NNOSDATA1 0xf282 -#define FSTV0910_P2_NOSDATA_NORMED1 0xf28200ff - -/*P2_NNOSDATA0*/ -#define RSTV0910_P2_NNOSDATA0 0xf283 -#define FSTV0910_P2_NOSDATA_NORMED0 0xf28300ff - -/*P2_NNOSPLHT1*/ -#define RSTV0910_P2_NNOSPLHT1 0xf284 -#define FSTV0910_P2_NOSPLHT_NORMED1 0xf28400ff - -/*P2_NNOSPLHT0*/ -#define RSTV0910_P2_NNOSPLHT0 0xf285 -#define FSTV0910_P2_NOSPLHT_NORMED0 0xf28500ff - -/*P2_NNOSPLH1*/ -#define RSTV0910_P2_NNOSPLH1 0xf286 -#define FSTV0910_P2_NOSPLH_NORMED1 0xf28600ff - -/*P2_NNOSPLH0*/ -#define RSTV0910_P2_NNOSPLH0 0xf287 -#define FSTV0910_P2_NOSPLH_NORMED0 0xf28700ff - -/*P2_NOSDATAT1*/ -#define RSTV0910_P2_NOSDATAT1 0xf288 -#define FSTV0910_P2_NOSDATAT_UNNORMED1 0xf28800ff - -/*P2_NOSDATAT0*/ -#define RSTV0910_P2_NOSDATAT0 0xf289 -#define FSTV0910_P2_NOSDATAT_UNNORMED0 0xf28900ff - -/*P2_NNOSFRAME1*/ -#define RSTV0910_P2_NNOSFRAME1 0xf28a -#define FSTV0910_P2_NOSFRAME_NORMED1 0xf28a00ff - -/*P2_NNOSFRAME0*/ -#define RSTV0910_P2_NNOSFRAME0 0xf28b -#define FSTV0910_P2_NOSFRAME_NORMED0 0xf28b00ff - -/*P2_NNOSRAD1*/ -#define RSTV0910_P2_NNOSRAD1 0xf28c -#define FSTV0910_P2_NOSRADIAL_NORMED1 0xf28c00ff - -/*P2_NNOSRAD0*/ -#define RSTV0910_P2_NNOSRAD0 0xf28d -#define FSTV0910_P2_NOSRADIAL_NORMED0 0xf28d00ff - -/*P2_NOSCFGF1*/ -#define RSTV0910_P2_NOSCFGF1 0xf28e -#define FSTV0910_P2_LOWNOISE_MESURE 0xf28e0080 -#define FSTV0910_P2_NOS_DELFRAME 0xf28e0040 -#define FSTV0910_P2_NOSDATA_MODE 0xf28e0030 -#define FSTV0910_P2_FRAMESEL_TYPESEL 0xf28e000c -#define FSTV0910_P2_FRAMESEL_TYPE 0xf28e0003 - -/*P2_CAR2CFG*/ -#define RSTV0910_P2_CAR2CFG 0xf290 -#define FSTV0910_P2_DESCRAMB_OFF 0xf2900080 -#define FSTV0910_P2_EN_PHNOSRAM 0xf2900020 -#define FSTV0910_P2_STOP_CFR2UPDATE 0xf2900010 -#define FSTV0910_P2_STOP_NCO2UPDATE 0xf2900008 -#define FSTV0910_P2_ROTA2ON 0xf2900004 -#define FSTV0910_P2_PH_DET_ALGO2 0xf2900003 - -/*P2_CFR2CFR1*/ -#define RSTV0910_P2_CFR2CFR1 0xf291 -#define FSTV0910_P2_CFR2_S2CONTROL 0xf29100c0 -#define FSTV0910_P2_EN_S2CAR2CENTER 0xf2910020 -#define FSTV0910_P2_BCHERRCFR2_MODE 0xf2910018 -#define FSTV0910_P2_CFR2TOCFR1_BETA 0xf2910007 - -/*P2_CAR3CFG*/ -#define RSTV0910_P2_CAR3CFG 0xf292 -#define FSTV0910_P2_CARRIER23_MODE 0xf29200c0 -#define FSTV0910_P2_CAR3INTERM_DVBS1 0xf2920020 -#define FSTV0910_P2_ABAMPLIF_MODE 0xf2920018 -#define FSTV0910_P2_CARRIER3_ALPHA3DL 0xf2920007 - -/*P2_CFR22*/ -#define RSTV0910_P2_CFR22 0xf293 -#define FSTV0910_P2_CAR2_FREQ2 0xf29301ff - -/*P2_CFR21*/ -#define RSTV0910_P2_CFR21 0xf294 -#define FSTV0910_P2_CAR2_FREQ1 0xf29400ff - -/*P2_CFR20*/ -#define RSTV0910_P2_CFR20 0xf295 -#define FSTV0910_P2_CAR2_FREQ0 0xf29500ff - -/*P2_ACLC2S2Q*/ -#define RSTV0910_P2_ACLC2S2Q 0xf297 -#define FSTV0910_P2_ENAB_SPSKSYMB 0xf2970080 -#define FSTV0910_P2_CAR2S2_QANOSAUTO 0xf2970040 -#define FSTV0910_P2_CAR2S2_Q_ALPH_M 0xf2970030 -#define FSTV0910_P2_CAR2S2_Q_ALPH_E 0xf297000f - -/*P2_ACLC2S28*/ -#define RSTV0910_P2_ACLC2S28 0xf298 -#define FSTV0910_P2_OLDI3Q_MODE 0xf2980080 -#define FSTV0910_P2_CAR2S2_8ANOSAUTO 0xf2980040 -#define FSTV0910_P2_CAR2S2_8_ALPH_M 0xf2980030 -#define FSTV0910_P2_CAR2S2_8_ALPH_E 0xf298000f - -/*P2_ACLC2S216A*/ -#define RSTV0910_P2_ACLC2S216A 0xf299 -#define FSTV0910_P2_CAR2S2_16ANOSAUTO 0xf2990040 -#define FSTV0910_P2_CAR2S2_16A_ALPH_M 0xf2990030 -#define FSTV0910_P2_CAR2S2_16A_ALPH_E 0xf299000f - -/*P2_ACLC2S232A*/ -#define RSTV0910_P2_ACLC2S232A 0xf29a -#define FSTV0910_P2_CAR2S2_32ANOSUATO 0xf29a0040 -#define FSTV0910_P2_CAR2S2_32A_ALPH_M 0xf29a0030 -#define FSTV0910_P2_CAR2S2_32A_ALPH_E 0xf29a000f - -/*P2_BCLC2S2Q*/ -#define RSTV0910_P2_BCLC2S2Q 0xf29c -#define FSTV0910_P2_DVBS2S2Q_NIP 0xf29c0080 -#define FSTV0910_P2_CAR2S2_QBNOSAUTO 0xf29c0040 -#define FSTV0910_P2_CAR2S2_Q_BETA_M 0xf29c0030 -#define FSTV0910_P2_CAR2S2_Q_BETA_E 0xf29c000f - -/*P2_BCLC2S28*/ -#define RSTV0910_P2_BCLC2S28 0xf29d -#define FSTV0910_P2_DVBS2S28_NIP 0xf29d0080 -#define FSTV0910_P2_CAR2S2_8BNOSAUTO 0xf29d0040 -#define FSTV0910_P2_CAR2S2_8_BETA_M 0xf29d0030 -#define FSTV0910_P2_CAR2S2_8_BETA_E 0xf29d000f - -/*P2_PLROOT2*/ -#define RSTV0910_P2_PLROOT2 0xf2ac -#define FSTV0910_P2_PLHAUTO_DISPLH 0xf2ac0040 -#define FSTV0910_P2_PLHAUTO_FASTMODE 0xf2ac0020 -#define FSTV0910_P2_PLHAUTO_ENABLE 0xf2ac0010 -#define FSTV0910_P2_PLSCRAMB_MODE 0xf2ac000c -#define FSTV0910_P2_PLSCRAMB_ROOT2 0xf2ac0003 - -/*P2_PLROOT1*/ -#define RSTV0910_P2_PLROOT1 0xf2ad -#define FSTV0910_P2_PLSCRAMB_ROOT1 0xf2ad00ff - -/*P2_PLROOT0*/ -#define RSTV0910_P2_PLROOT0 0xf2ae -#define FSTV0910_P2_PLSCRAMB_ROOT0 0xf2ae00ff - -/*P2_MODCODLST7*/ -#define RSTV0910_P2_MODCODLST7 0xf2b7 -#define FSTV0910_P2_MODCOD_NNOSFILTER 0xf2b70080 -#define FSTV0910_P2_MODCODLST_NOSTYPE 0xf2b70040 -#define FSTV0910_P2_DIS_8PSK_9_10 0xf2b70030 -#define FSTV0910_P2_DIS_8P_8_9 0xf2b7000f - -/*P2_MODCODLST8*/ -#define RSTV0910_P2_MODCODLST8 0xf2b8 -#define FSTV0910_P2_DIS_8P_5_6 0xf2b800f0 -#define FSTV0910_P2_DIS_8P_3_4 0xf2b8000f - -/*P2_MODCODLST9*/ -#define RSTV0910_P2_MODCODLST9 0xf2b9 -#define FSTV0910_P2_DIS_8P_2_3 0xf2b900f0 -#define FSTV0910_P2_DIS_8P_3_5 0xf2b9000f - -/*P2_MODCODLSTA*/ -#define RSTV0910_P2_MODCODLSTA 0xf2ba -#define FSTV0910_P2_NOSFILTER_LIMITE 0xf2ba0080 -#define FSTV0910_P2_NOSFILTER_MODE 0xf2ba0040 -#define FSTV0910_P2_DIS_QPSK_9_10 0xf2ba0030 -#define FSTV0910_P2_DIS_QP_8_9 0xf2ba000f - -/*P2_MODCODLSTB*/ -#define RSTV0910_P2_MODCODLSTB 0xf2bb -#define FSTV0910_P2_DIS_QP_5_6 0xf2bb00f0 -#define FSTV0910_P2_DIS_QP_4_5 0xf2bb000f - -/*P2_MODCODLSTC*/ -#define RSTV0910_P2_MODCODLSTC 0xf2bc -#define FSTV0910_P2_DIS_QP_3_4 0xf2bc00f0 -#define FSTV0910_P2_DIS_QP_2_3 0xf2bc000f - -/*P2_MODCODLSTD*/ -#define RSTV0910_P2_MODCODLSTD 0xf2bd -#define FSTV0910_P2_DIS_QPSK_3_5 0xf2bd00f0 -#define FSTV0910_P2_DIS_QPSK_1_2 0xf2bd000f - -/*P2_GAUSSR0*/ -#define RSTV0910_P2_GAUSSR0 0xf2c0 -#define FSTV0910_P2_EN_CCIMODE 0xf2c00080 -#define FSTV0910_P2_R0_GAUSSIEN 0xf2c0007f - -/*P2_CCIR0*/ -#define RSTV0910_P2_CCIR0 0xf2c1 -#define FSTV0910_P2_CCIDETECT_PLHONLY 0xf2c10080 -#define FSTV0910_P2_R0_CCI 0xf2c1007f - -/*P2_CCIQUANT*/ -#define RSTV0910_P2_CCIQUANT 0xf2c2 -#define FSTV0910_P2_CCI_BETA 0xf2c200e0 -#define FSTV0910_P2_CCI_QUANT 0xf2c2001f - -/*P2_CCITHRES*/ -#define RSTV0910_P2_CCITHRES 0xf2c3 -#define FSTV0910_P2_CCI_THRESHOLD 0xf2c300ff - -/*P2_CCIACC*/ -#define RSTV0910_P2_CCIACC 0xf2c4 -#define FSTV0910_P2_CCI_VALUE 0xf2c400ff - -/*P2_DSTATUS4*/ -#define RSTV0910_P2_DSTATUS4 0xf2c5 -#define FSTV0910_P2_RAINFADE_DETECT 0xf2c50080 -#define FSTV0910_P2_NOTHRES2_FAIL 0xf2c50040 -#define FSTV0910_P2_NOTHRES1_FAIL 0xf2c50020 -#define FSTV0910_P2_PILOT_FAILDETECT 0xf2c50010 -#define FSTV0910_P2_HIER_DETECT 0xf2c50008 -#define FSTV0910_P2_DMDPROG_ERROR 0xf2c50004 -#define FSTV0910_P2_CSTENV_DETECT 0xf2c50002 -#define FSTV0910_P2_DETECTION_TRIAX 0xf2c50001 - -/*P2_DMDRESCFG*/ -#define RSTV0910_P2_DMDRESCFG 0xf2c6 -#define FSTV0910_P2_DMDRES_RESET 0xf2c60080 -#define FSTV0910_P2_DMDRES_NOISESQR 0xf2c60010 -#define FSTV0910_P2_DMDRES_STRALL 0xf2c60008 -#define FSTV0910_P2_DMDRES_NEWONLY 0xf2c60004 -#define FSTV0910_P2_DMDRES_NOSTORE 0xf2c60002 -#define FSTV0910_P2_DMDRES_AGC2MEM 0xf2c60001 - -/*P2_DMDRESADR*/ -#define RSTV0910_P2_DMDRESADR 0xf2c7 -#define FSTV0910_P2_SUSP_PREDCANAL 0xf2c70080 -#define FSTV0910_P2_DMDRES_VALIDCFR 0xf2c70040 -#define FSTV0910_P2_DMDRES_MEMFULL 0xf2c70030 -#define FSTV0910_P2_DMDRES_RESNBR 0xf2c7000f - -/*P2_DMDRESDATA7*/ -#define RSTV0910_P2_DMDRESDATA7 0xf2c8 -#define FSTV0910_P2_DMDRES_DATA7 0xf2c800ff - -/*P2_DMDRESDATA6*/ -#define RSTV0910_P2_DMDRESDATA6 0xf2c9 -#define FSTV0910_P2_DMDRES_DATA6 0xf2c900ff - -/*P2_DMDRESDATA5*/ -#define RSTV0910_P2_DMDRESDATA5 0xf2ca -#define FSTV0910_P2_DMDRES_DATA5 0xf2ca00ff - -/*P2_DMDRESDATA4*/ -#define RSTV0910_P2_DMDRESDATA4 0xf2cb -#define FSTV0910_P2_DMDRES_DATA4 0xf2cb00ff - -/*P2_DMDRESDATA3*/ -#define RSTV0910_P2_DMDRESDATA3 0xf2cc -#define FSTV0910_P2_DMDRES_DATA3 0xf2cc00ff - -/*P2_DMDRESDATA2*/ -#define RSTV0910_P2_DMDRESDATA2 0xf2cd -#define FSTV0910_P2_DMDRES_DATA2 0xf2cd00ff - -/*P2_DMDRESDATA1*/ -#define RSTV0910_P2_DMDRESDATA1 0xf2ce -#define FSTV0910_P2_DMDRES_DATA1 0xf2ce00ff - -/*P2_DMDRESDATA0*/ -#define RSTV0910_P2_DMDRESDATA0 0xf2cf -#define FSTV0910_P2_DMDRES_DATA0 0xf2cf00ff - -/*P2_FFEI1*/ -#define RSTV0910_P2_FFEI1 0xf2d0 -#define FSTV0910_P2_FFE_ACCI1 0xf2d001ff - -/*P2_FFEQ1*/ -#define RSTV0910_P2_FFEQ1 0xf2d1 -#define FSTV0910_P2_FFE_ACCQ1 0xf2d101ff - -/*P2_FFEI2*/ -#define RSTV0910_P2_FFEI2 0xf2d2 -#define FSTV0910_P2_FFE_ACCI2 0xf2d201ff - -/*P2_FFEQ2*/ -#define RSTV0910_P2_FFEQ2 0xf2d3 -#define FSTV0910_P2_FFE_ACCQ2 0xf2d301ff - -/*P2_FFEI3*/ -#define RSTV0910_P2_FFEI3 0xf2d4 -#define FSTV0910_P2_FFE_ACCI3 0xf2d401ff - -/*P2_FFEQ3*/ -#define RSTV0910_P2_FFEQ3 0xf2d5 -#define FSTV0910_P2_FFE_ACCQ3 0xf2d501ff - -/*P2_FFEI4*/ -#define RSTV0910_P2_FFEI4 0xf2d6 -#define FSTV0910_P2_FFE_ACCI4 0xf2d601ff - -/*P2_FFEQ4*/ -#define RSTV0910_P2_FFEQ4 0xf2d7 -#define FSTV0910_P2_FFE_ACCQ4 0xf2d701ff - -/*P2_FFECFG*/ -#define RSTV0910_P2_FFECFG 0xf2d8 -#define FSTV0910_P2_EQUALFFE_ON 0xf2d80040 -#define FSTV0910_P2_EQUAL_USEDSYMB 0xf2d80030 -#define FSTV0910_P2_MU_EQUALFFE 0xf2d80007 - -/*P2_TNRCFG2*/ -#define RSTV0910_P2_TNRCFG2 0xf2e1 -#define FSTV0910_P2_TUN_IQSWAP 0xf2e10080 -#define FSTV0910_P2_STB6110_STEP2MHZ 0xf2e10040 -#define FSTV0910_P2_STB6120_DBLI2C 0xf2e10020 -#define FSTV0910_P2_TUNER_WIDEBAND 0xf2e10010 -#define FSTV0910_P2_TUNER_OBSPAGE 0xf2e10008 -#define FSTV0910_P2_DIS_BWCALC 0xf2e10004 -#define FSTV0910_P2_SHORT_WAITSTATES 0xf2e10002 -#define FSTV0910_P2_DIS_2BWAGC1 0xf2e10001 - -/*P2_SMAPCOEF7*/ -#define RSTV0910_P2_SMAPCOEF7 0xf300 -#define FSTV0910_P2_DIS_QSCALE 0xf3000080 -#define FSTV0910_P2_SMAPCOEF_Q_LLR12 0xf300017f - -/*P2_SMAPCOEF6*/ -#define RSTV0910_P2_SMAPCOEF6 0xf301 -#define FSTV0910_P2_DIS_AGC2SCALE 0xf3010080 -#define FSTV0910_P2_DIS_16IQMULT 0xf3010040 -#define FSTV0910_P2_OLD_16APSK47 0xf3010020 -#define FSTV0910_P2_OLD_16APSK12 0xf3010010 -#define FSTV0910_P2_DIS_NEWSCALE 0xf3010008 -#define FSTV0910_P2_ADJ_8PSKLLR1 0xf3010004 -#define FSTV0910_P2_OLD_8PSKLLR1 0xf3010002 -#define FSTV0910_P2_DIS_AB8PSK 0xf3010001 - -/*P2_SMAPCOEF5*/ -#define RSTV0910_P2_SMAPCOEF5 0xf302 -#define FSTV0910_P2_DIS_8SCALE 0xf3020080 -#define FSTV0910_P2_SMAPCOEF_8P_LLR23 0xf302017f - -/*P2_NOSTHRES1*/ -#define RSTV0910_P2_NOSTHRES1 0xf309 -#define FSTV0910_P2_NOS_THRESHOLD1 0xf30900ff - -/*P2_NOSTHRES2*/ -#define RSTV0910_P2_NOSTHRES2 0xf30a -#define FSTV0910_P2_NOS_THRESHOLD2 0xf30a00ff - -/*P2_NOSDIFF1*/ -#define RSTV0910_P2_NOSDIFF1 0xf30b -#define FSTV0910_P2_NOSTHRES1_DIFF 0xf30b00ff - -/*P2_RAINFADE*/ -#define RSTV0910_P2_RAINFADE 0xf30c -#define FSTV0910_P2_NOSTHRES_DATAT 0xf30c0080 -#define FSTV0910_P2_RAINFADE_CNLIMIT 0xf30c0070 -#define FSTV0910_P2_RAINFADE_TIMEOUT 0xf30c0007 - -/*P2_NOSRAMCFG*/ -#define RSTV0910_P2_NOSRAMCFG 0xf30d -#define FSTV0910_P2_NOSRAM_DVBS2DATA 0xf30d0080 -#define FSTV0910_P2_NOSRAM_QUADRAT 0xf30d0040 -#define FSTV0910_P2_NOSRAM_ACTIVATION 0xf30d0030 -#define FSTV0910_P2_NOSRAM_CNRONLY 0xf30d0008 -#define FSTV0910_P2_NOSRAM_LGNCNR1 0xf30d0007 - -/*P2_NOSRAMPOS*/ -#define RSTV0910_P2_NOSRAMPOS 0xf30e -#define FSTV0910_P2_NOSRAM_LGNCNR0 0xf30e00f0 -#define FSTV0910_P2_NOSRAM_VALIDE 0xf30e0004 -#define FSTV0910_P2_NOSRAM_CNRVAL1 0xf30e0003 - -/*P2_NOSRAMVAL*/ -#define RSTV0910_P2_NOSRAMVAL 0xf30f -#define FSTV0910_P2_NOSRAM_CNRVAL0 0xf30f00ff - -/*P2_DMDPLHSTAT*/ -#define RSTV0910_P2_DMDPLHSTAT 0xf320 -#define FSTV0910_P2_PLH_STATISTIC 0xf32000ff - -/*P2_LOCKTIME3*/ -#define RSTV0910_P2_LOCKTIME3 0xf322 -#define FSTV0910_P2_DEMOD_LOCKTIME3 0xf32200ff - -/*P2_LOCKTIME2*/ -#define RSTV0910_P2_LOCKTIME2 0xf323 -#define FSTV0910_P2_DEMOD_LOCKTIME2 0xf32300ff - -/*P2_LOCKTIME1*/ -#define RSTV0910_P2_LOCKTIME1 0xf324 -#define FSTV0910_P2_DEMOD_LOCKTIME1 0xf32400ff - -/*P2_LOCKTIME0*/ -#define RSTV0910_P2_LOCKTIME0 0xf325 -#define FSTV0910_P2_DEMOD_LOCKTIME0 0xf32500ff - -/*P2_VITSCALE*/ -#define RSTV0910_P2_VITSCALE 0xf332 -#define FSTV0910_P2_NVTH_NOSRANGE 0xf3320080 -#define FSTV0910_P2_VERROR_MAXMODE 0xf3320040 -#define FSTV0910_P2_KDIV_MODE 0xf3320030 -#define FSTV0910_P2_NSLOWSN_LOCKED 0xf3320008 -#define FSTV0910_P2_DELOCK_PRFLOSS 0xf3320004 -#define FSTV0910_P2_DIS_RSFLOCK 0xf3320002 - -/*P2_FECM*/ -#define RSTV0910_P2_FECM 0xf333 -#define FSTV0910_P2_DSS_DVB 0xf3330080 -#define FSTV0910_P2_DEMOD_BYPASS 0xf3330040 -#define FSTV0910_P2_CMP_SLOWMODE 0xf3330020 -#define FSTV0910_P2_DSS_SRCH 0xf3330010 -#define FSTV0910_P2_DIFF_MODEVIT 0xf3330004 -#define FSTV0910_P2_SYNCVIT 0xf3330002 -#define FSTV0910_P2_IQINV 0xf3330001 - -/*P2_VTH12*/ -#define RSTV0910_P2_VTH12 0xf334 -#define FSTV0910_P2_VTH12 0xf33400ff - -/*P2_VTH23*/ -#define RSTV0910_P2_VTH23 0xf335 -#define FSTV0910_P2_VTH23 0xf33500ff - -/*P2_VTH34*/ -#define RSTV0910_P2_VTH34 0xf336 -#define FSTV0910_P2_VTH34 0xf33600ff - -/*P2_VTH56*/ -#define RSTV0910_P2_VTH56 0xf337 -#define FSTV0910_P2_VTH56 0xf33700ff - -/*P2_VTH67*/ -#define RSTV0910_P2_VTH67 0xf338 -#define FSTV0910_P2_VTH67 0xf33800ff - -/*P2_VTH78*/ -#define RSTV0910_P2_VTH78 0xf339 -#define FSTV0910_P2_VTH78 0xf33900ff - -/*P2_VITCURPUN*/ -#define RSTV0910_P2_VITCURPUN 0xf33a -#define FSTV0910_P2_CYCLESLIP_VIT 0xf33a0080 -#define FSTV0910_P2_VIT_ROTA180 0xf33a0040 -#define FSTV0910_P2_VIT_ROTA90 0xf33a0020 -#define FSTV0910_P2_VIT_CURPUN 0xf33a001f - -/*P2_VERROR*/ -#define RSTV0910_P2_VERROR 0xf33b -#define FSTV0910_P2_REGERR_VIT 0xf33b00ff - -/*P2_PRVIT*/ -#define RSTV0910_P2_PRVIT 0xf33c -#define FSTV0910_P2_DIS_VTHLOCK 0xf33c0040 -#define FSTV0910_P2_E7_8VIT 0xf33c0020 -#define FSTV0910_P2_E6_7VIT 0xf33c0010 -#define FSTV0910_P2_E5_6VIT 0xf33c0008 -#define FSTV0910_P2_E3_4VIT 0xf33c0004 -#define FSTV0910_P2_E2_3VIT 0xf33c0002 -#define FSTV0910_P2_E1_2VIT 0xf33c0001 - -/*P2_VAVSRVIT*/ -#define RSTV0910_P2_VAVSRVIT 0xf33d -#define FSTV0910_P2_AMVIT 0xf33d0080 -#define FSTV0910_P2_FROZENVIT 0xf33d0040 -#define FSTV0910_P2_SNVIT 0xf33d0030 -#define FSTV0910_P2_TOVVIT 0xf33d000c -#define FSTV0910_P2_HYPVIT 0xf33d0003 - -/*P2_VSTATUSVIT*/ -#define RSTV0910_P2_VSTATUSVIT 0xf33e -#define FSTV0910_P2_VITERBI_ON 0xf33e0080 -#define FSTV0910_P2_END_LOOPVIT 0xf33e0040 -#define FSTV0910_P2_VITERBI_DEPRF 0xf33e0020 -#define FSTV0910_P2_PRFVIT 0xf33e0010 -#define FSTV0910_P2_LOCKEDVIT 0xf33e0008 -#define FSTV0910_P2_VITERBI_DELOCK 0xf33e0004 -#define FSTV0910_P2_VIT_DEMODSEL 0xf33e0002 -#define FSTV0910_P2_VITERBI_COMPOUT 0xf33e0001 - -/*P2_VTHINUSE*/ -#define RSTV0910_P2_VTHINUSE 0xf33f -#define FSTV0910_P2_VIT_INUSE 0xf33f00ff - -/*P2_KDIV12*/ -#define RSTV0910_P2_KDIV12 0xf340 -#define FSTV0910_P2_KDIV12_MANUAL 0xf3400080 -#define FSTV0910_P2_K_DIVIDER_12 0xf340007f - -/*P2_KDIV23*/ -#define RSTV0910_P2_KDIV23 0xf341 -#define FSTV0910_P2_KDIV23_MANUAL 0xf3410080 -#define FSTV0910_P2_K_DIVIDER_23 0xf341007f - -/*P2_KDIV34*/ -#define RSTV0910_P2_KDIV34 0xf342 -#define FSTV0910_P2_KDIV34_MANUAL 0xf3420080 -#define FSTV0910_P2_K_DIVIDER_34 0xf342007f - -/*P2_KDIV56*/ -#define RSTV0910_P2_KDIV56 0xf343 -#define FSTV0910_P2_KDIV56_MANUAL 0xf3430080 -#define FSTV0910_P2_K_DIVIDER_56 0xf343007f - -/*P2_KDIV67*/ -#define RSTV0910_P2_KDIV67 0xf344 -#define FSTV0910_P2_KDIV67_MANUAL 0xf3440080 -#define FSTV0910_P2_K_DIVIDER_67 0xf344007f - -/*P2_KDIV78*/ -#define RSTV0910_P2_KDIV78 0xf345 -#define FSTV0910_P2_KDIV78_MANUAL 0xf3450080 -#define FSTV0910_P2_K_DIVIDER_78 0xf345007f - -/*P2_PDELCTRL0*/ -#define RSTV0910_P2_PDELCTRL0 0xf34f -#define FSTV0910_P2_ISIOBS_MODE 0xf34f0030 -#define FSTV0910_P2_PDELDIS_BITWISE 0xf34f0004 - -/*P2_PDELCTRL1*/ -#define RSTV0910_P2_PDELCTRL1 0xf350 -#define FSTV0910_P2_INV_MISMASK 0xf3500080 -#define FSTV0910_P2_FORCE_ACCEPTED 0xf3500040 -#define FSTV0910_P2_FILTER_EN 0xf3500020 -#define FSTV0910_P2_FORCE_PKTDELINUSE 0xf3500010 -#define FSTV0910_P2_HYSTEN 0xf3500008 -#define FSTV0910_P2_HYSTSWRST 0xf3500004 -#define FSTV0910_P2_EN_MIS00 0xf3500002 -#define FSTV0910_P2_ALGOSWRST 0xf3500001 - -/*P2_PDELCTRL2*/ -#define RSTV0910_P2_PDELCTRL2 0xf351 -#define FSTV0910_P2_FORCE_CONTINUOUS 0xf3510080 -#define FSTV0910_P2_RESET_UPKO_COUNT 0xf3510040 -#define FSTV0910_P2_USER_PKTDELIN_NB 0xf3510020 -#define FSTV0910_P2_DATA_UNBBSCRAMBLED 0xf3510008 -#define FSTV0910_P2_FORCE_LONGPKT 0xf3510004 -#define FSTV0910_P2_FRAME_MODE 0xf3510002 - -/*P2_HYSTTHRESH*/ -#define RSTV0910_P2_HYSTTHRESH 0xf354 -#define FSTV0910_P2_DELIN_LOCKTHRES 0xf35400f0 -#define FSTV0910_P2_DELIN_UNLOCKTHRES 0xf354000f - -/*P2_ISIENTRY*/ -#define RSTV0910_P2_ISIENTRY 0xf35e -#define FSTV0910_P2_ISI_ENTRY 0xf35e00ff - -/*P2_ISIBITENA*/ -#define RSTV0910_P2_ISIBITENA 0xf35f -#define FSTV0910_P2_ISI_BIT_EN 0xf35f00ff - -/*P2_MATSTR1*/ -#define RSTV0910_P2_MATSTR1 0xf360 -#define FSTV0910_P2_MATYPE_CURRENT1 0xf36000ff - -/*P2_MATSTR0*/ -#define RSTV0910_P2_MATSTR0 0xf361 -#define FSTV0910_P2_MATYPE_CURRENT0 0xf36100ff - -/*P2_UPLSTR1*/ -#define RSTV0910_P2_UPLSTR1 0xf362 -#define FSTV0910_P2_UPL_CURRENT1 0xf36200ff - -/*P2_UPLSTR0*/ -#define RSTV0910_P2_UPLSTR0 0xf363 -#define FSTV0910_P2_UPL_CURRENT0 0xf36300ff - -/*P2_DFLSTR1*/ -#define RSTV0910_P2_DFLSTR1 0xf364 -#define FSTV0910_P2_DFL_CURRENT1 0xf36400ff - -/*P2_DFLSTR0*/ -#define RSTV0910_P2_DFLSTR0 0xf365 -#define FSTV0910_P2_DFL_CURRENT0 0xf36500ff - -/*P2_SYNCSTR*/ -#define RSTV0910_P2_SYNCSTR 0xf366 -#define FSTV0910_P2_SYNC_CURRENT 0xf36600ff - -/*P2_SYNCDSTR1*/ -#define RSTV0910_P2_SYNCDSTR1 0xf367 -#define FSTV0910_P2_SYNCD_CURRENT1 0xf36700ff - -/*P2_SYNCDSTR0*/ -#define RSTV0910_P2_SYNCDSTR0 0xf368 -#define FSTV0910_P2_SYNCD_CURRENT0 0xf36800ff - -/*P2_PDELSTATUS1*/ -#define RSTV0910_P2_PDELSTATUS1 0xf369 -#define FSTV0910_P2_PKTDELIN_DELOCK 0xf3690080 -#define FSTV0910_P2_SYNCDUPDFL_BADDFL 0xf3690040 -#define FSTV0910_P2_CONTINUOUS_STREAM 0xf3690020 -#define FSTV0910_P2_UNACCEPTED_STREAM 0xf3690010 -#define FSTV0910_P2_BCH_ERROR_FLAG 0xf3690008 -#define FSTV0910_P2_BBHCRCKO 0xf3690004 -#define FSTV0910_P2_PKTDELIN_LOCK 0xf3690002 -#define FSTV0910_P2_FIRST_LOCK 0xf3690001 - -/*P2_PDELSTATUS2*/ -#define RSTV0910_P2_PDELSTATUS2 0xf36a -#define FSTV0910_P2_PKTDEL_DEMODSEL 0xf36a0080 -#define FSTV0910_P2_FRAME_MODCOD 0xf36a007c -#define FSTV0910_P2_FRAME_TYPE 0xf36a0003 - -/*P2_BBFCRCKO1*/ -#define RSTV0910_P2_BBFCRCKO1 0xf36b -#define FSTV0910_P2_BBHCRC_KOCNT1 0xf36b00ff - -/*P2_BBFCRCKO0*/ -#define RSTV0910_P2_BBFCRCKO0 0xf36c -#define FSTV0910_P2_BBHCRC_KOCNT0 0xf36c00ff - -/*P2_UPCRCKO1*/ -#define RSTV0910_P2_UPCRCKO1 0xf36d -#define FSTV0910_P2_PKTCRC_KOCNT1 0xf36d00ff - -/*P2_UPCRCKO0*/ -#define RSTV0910_P2_UPCRCKO0 0xf36e -#define FSTV0910_P2_PKTCRC_KOCNT0 0xf36e00ff - -/*P2_PDELCTRL3*/ -#define RSTV0910_P2_PDELCTRL3 0xf36f -#define FSTV0910_P2_PKTDEL_CONTFAIL 0xf36f0080 -#define FSTV0910_P2_PKTDEL_ENLONGPKT 0xf36f0040 -#define FSTV0910_P2_NOFIFO_BCHERR 0xf36f0020 -#define FSTV0910_P2_PKTDELIN_DELACMERR 0xf36f0010 -#define FSTV0910_P2_SATURATE_BBPKTKO 0xf36f0004 -#define FSTV0910_P2_PKTDEL_BCHERRCONT 0xf36f0002 -#define FSTV0910_P2_ETHERNET_DISFCS 0xf36f0001 - -/*P2_TSSTATEM*/ -#define RSTV0910_P2_TSSTATEM 0xf370 -#define FSTV0910_P2_TSDIL_ON 0xf3700080 -#define FSTV0910_P2_TSSKIPRS_ON 0xf3700040 -#define FSTV0910_P2_TSRS_ON 0xf3700020 -#define FSTV0910_P2_TSDESCRAMB_ON 0xf3700010 -#define FSTV0910_P2_TSFRAME_MODE 0xf3700008 -#define FSTV0910_P2_TS_DISABLE 0xf3700004 -#define FSTV0910_P2_TSACM_MODE 0xf3700002 -#define FSTV0910_P2_TSOUT_NOSYNC 0xf3700001 - -/*P2_TSCFGH*/ -#define RSTV0910_P2_TSCFGH 0xf372 -#define FSTV0910_P2_TSFIFO_DVBCI 0xf3720080 -#define FSTV0910_P2_TSFIFO_SERIAL 0xf3720040 -#define FSTV0910_P2_TSFIFO_TEIUPDATE 0xf3720020 -#define FSTV0910_P2_TSFIFO_DUTY50 0xf3720010 -#define FSTV0910_P2_TSFIFO_HSGNLOUT 0xf3720008 -#define FSTV0910_P2_TSFIFO_ERRMODE 0xf3720006 -#define FSTV0910_P2_RST_HWARE 0xf3720001 - -/*P2_TSCFGM*/ -#define RSTV0910_P2_TSCFGM 0xf373 -#define FSTV0910_P2_TSFIFO_MANSPEED 0xf37300c0 -#define FSTV0910_P2_TSFIFO_PERMDATA 0xf3730020 -#define FSTV0910_P2_TSFIFO_NONEWSGNL 0xf3730010 -#define FSTV0910_P2_NPD_SPECDVBS2 0xf3730004 -#define FSTV0910_P2_TSFIFO_DPUNACTIVE 0xf3730002 -#define FSTV0910_P2_TSFIFO_INVDATA 0xf3730001 - -/*P2_TSCFGL*/ -#define RSTV0910_P2_TSCFGL 0xf374 -#define FSTV0910_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 -#define FSTV0910_P2_BCHERROR_MODE 0xf3740030 -#define FSTV0910_P2_TSFIFO_NSGNL2DATA 0xf3740008 -#define FSTV0910_P2_TSFIFO_EMBINDVB 0xf3740004 -#define FSTV0910_P2_TSFIFO_BITSPEED 0xf3740003 - -/*P2_TSINSDELH*/ -#define RSTV0910_P2_TSINSDELH 0xf376 -#define FSTV0910_P2_TSDEL_SYNCBYTE 0xf3760080 -#define FSTV0910_P2_TSDEL_XXHEADER 0xf3760040 -#define FSTV0910_P2_TSDEL_BBHEADER 0xf3760020 -#define FSTV0910_P2_TSDEL_DATAFIELD 0xf3760010 -#define FSTV0910_P2_TSINSDEL_ISCR 0xf3760008 -#define FSTV0910_P2_TSINSDEL_NPD 0xf3760004 -#define FSTV0910_P2_TSINSDEL_RSPARITY 0xf3760002 -#define FSTV0910_P2_TSINSDEL_CRC8 0xf3760001 - -/*P2_TSDIVN*/ -#define RSTV0910_P2_TSDIVN 0xf379 -#define FSTV0910_P2_TSFIFO_SPEEDMODE 0xf37900c0 -#define FSTV0910_P2_BYTE_OVERSAMPLING 0xf3790038 -#define FSTV0910_P2_TSFIFO_RISEOK 0xf3790007 - -/*P2_TSCFG4*/ -#define RSTV0910_P2_TSCFG4 0xf37a -#define FSTV0910_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0 -#define FSTV0910_P2_TSFIFO_HIERSEL 0xf37a0020 -#define FSTV0910_P2_TSFIFO_SPECTOKEN 0xf37a0010 -#define FSTV0910_P2_TSFIFO_MAXMODE 0xf37a0008 -#define FSTV0910_P2_TSFIFO_FRFORCEPKT 0xf37a0004 -#define FSTV0910_P2_EXT_FECSPYIN 0xf37a0002 -#define FSTV0910_P2_TSFIFO_DELSPEEDUP 0xf37a0001 - -/*P2_TSSPEED*/ -#define RSTV0910_P2_TSSPEED 0xf380 -#define FSTV0910_P2_TSFIFO_OUTSPEED 0xf38000ff - -/*P2_TSSTATUS*/ -#define RSTV0910_P2_TSSTATUS 0xf381 -#define FSTV0910_P2_TSFIFO_LINEOK 0xf3810080 -#define FSTV0910_P2_TSFIFO_ERROR 0xf3810040 -#define FSTV0910_P2_TSFIFO_DATA7 0xf3810020 -#define FSTV0910_P2_TSFIFO_NOSYNC 0xf3810010 -#define FSTV0910_P2_ISCR_INITIALIZED 0xf3810008 -#define FSTV0910_P2_TSREGUL_ERROR 0xf3810004 -#define FSTV0910_P2_SOFFIFO_UNREGUL 0xf3810002 -#define FSTV0910_P2_DIL_READY 0xf3810001 - -/*P2_TSSTATUS2*/ -#define RSTV0910_P2_TSSTATUS2 0xf382 -#define FSTV0910_P2_TSFIFO_DEMODSEL 0xf3820080 -#define FSTV0910_P2_TSFIFOSPEED_STORE 0xf3820040 -#define FSTV0910_P2_DILXX_RESET 0xf3820020 -#define FSTV0910_P2_TSSPEED_IMPOSSIBLE 0xf3820010 -#define FSTV0910_P2_TSFIFO_LINENOK 0xf3820008 -#define FSTV0910_P2_TSFIFO_MUXSTREAM 0xf3820004 -#define FSTV0910_P2_SCRAMBDETECT 0xf3820002 -#define FSTV0910_P2_ULDTV67_FALSELOCK 0xf3820001 - -/*P2_TSBITRATE1*/ -#define RSTV0910_P2_TSBITRATE1 0xf383 -#define FSTV0910_P2_TSFIFO_BITRATE1 0xf38300ff - -/*P2_TSBITRATE0*/ -#define RSTV0910_P2_TSBITRATE0 0xf384 -#define FSTV0910_P2_TSFIFO_BITRATE0 0xf38400ff - -/*P2_ERRCTRL1*/ -#define RSTV0910_P2_ERRCTRL1 0xf398 -#define FSTV0910_P2_ERR_SOURCE1 0xf39800f0 -#define FSTV0910_P2_NUM_EVENT1 0xf3980007 - -/*P2_ERRCNT12*/ -#define RSTV0910_P2_ERRCNT12 0xf399 -#define FSTV0910_P2_ERRCNT1_OLDVALUE 0xf3990080 -#define FSTV0910_P2_ERR_CNT12 0xf399007f - -/*P2_ERRCNT11*/ -#define RSTV0910_P2_ERRCNT11 0xf39a -#define FSTV0910_P2_ERR_CNT11 0xf39a00ff - -/*P2_ERRCNT10*/ -#define RSTV0910_P2_ERRCNT10 0xf39b -#define FSTV0910_P2_ERR_CNT10 0xf39b00ff - -/*P2_ERRCTRL2*/ -#define RSTV0910_P2_ERRCTRL2 0xf39c -#define FSTV0910_P2_ERR_SOURCE2 0xf39c00f0 -#define FSTV0910_P2_NUM_EVENT2 0xf39c0007 - -/*P2_ERRCNT22*/ -#define RSTV0910_P2_ERRCNT22 0xf39d -#define FSTV0910_P2_ERRCNT2_OLDVALUE 0xf39d0080 -#define FSTV0910_P2_ERR_CNT22 0xf39d007f - -/*P2_ERRCNT21*/ -#define RSTV0910_P2_ERRCNT21 0xf39e -#define FSTV0910_P2_ERR_CNT21 0xf39e00ff - -/*P2_ERRCNT20*/ -#define RSTV0910_P2_ERRCNT20 0xf39f -#define FSTV0910_P2_ERR_CNT20 0xf39f00ff - -/*P2_FECSPY*/ -#define RSTV0910_P2_FECSPY 0xf3a0 -#define FSTV0910_P2_SPY_ENABLE 0xf3a00080 -#define FSTV0910_P2_NO_SYNCBYTE 0xf3a00040 -#define FSTV0910_P2_SERIAL_MODE 0xf3a00020 -#define FSTV0910_P2_UNUSUAL_PACKET 0xf3a00010 -#define FSTV0910_P2_BERMETER_DATAMODE 0xf3a0000c -#define FSTV0910_P2_BERMETER_LMODE 0xf3a00002 -#define FSTV0910_P2_BERMETER_RESET 0xf3a00001 - -/*P2_FSPYCFG*/ -#define RSTV0910_P2_FSPYCFG 0xf3a1 -#define FSTV0910_P2_FECSPY_INPUT 0xf3a100c0 -#define FSTV0910_P2_RST_ON_ERROR 0xf3a10020 -#define FSTV0910_P2_ONE_SHOT 0xf3a10010 -#define FSTV0910_P2_I2C_MODE 0xf3a1000c -#define FSTV0910_P2_SPY_HYSTERESIS 0xf3a10003 - -/*P2_FSPYDATA*/ -#define RSTV0910_P2_FSPYDATA 0xf3a2 -#define FSTV0910_P2_SPY_STUFFING 0xf3a20080 -#define FSTV0910_P2_NOERROR_PKTJITTER 0xf3a20040 -#define FSTV0910_P2_SPY_CNULLPKT 0xf3a20020 -#define FSTV0910_P2_SPY_OUTDATA_MODE 0xf3a2001f - -/*P2_FSPYOUT*/ -#define RSTV0910_P2_FSPYOUT 0xf3a3 -#define FSTV0910_P2_FSPY_DIRECT 0xf3a30080 -#define FSTV0910_P2_SPY_OUTDATA_BUS 0xf3a30038 -#define FSTV0910_P2_STUFF_MODE 0xf3a30007 - -/*P2_FSTATUS*/ -#define RSTV0910_P2_FSTATUS 0xf3a4 -#define FSTV0910_P2_SPY_ENDSIM 0xf3a40080 -#define FSTV0910_P2_VALID_SIM 0xf3a40040 -#define FSTV0910_P2_FOUND_SIGNAL 0xf3a40020 -#define FSTV0910_P2_DSS_SYNCBYTE 0xf3a40010 -#define FSTV0910_P2_RESULT_STATE 0xf3a4000f - -/*P2_FBERCPT4*/ -#define RSTV0910_P2_FBERCPT4 0xf3a8 -#define FSTV0910_P2_FBERMETER_CPT4 0xf3a800ff - -/*P2_FBERCPT3*/ -#define RSTV0910_P2_FBERCPT3 0xf3a9 -#define FSTV0910_P2_FBERMETER_CPT3 0xf3a900ff - -/*P2_FBERCPT2*/ -#define RSTV0910_P2_FBERCPT2 0xf3aa -#define FSTV0910_P2_FBERMETER_CPT2 0xf3aa00ff - -/*P2_FBERCPT1*/ -#define RSTV0910_P2_FBERCPT1 0xf3ab -#define FSTV0910_P2_FBERMETER_CPT1 0xf3ab00ff - -/*P2_FBERCPT0*/ -#define RSTV0910_P2_FBERCPT0 0xf3ac -#define FSTV0910_P2_FBERMETER_CPT0 0xf3ac00ff - -/*P2_FBERERR2*/ -#define RSTV0910_P2_FBERERR2 0xf3ad -#define FSTV0910_P2_FBERMETER_ERR2 0xf3ad00ff - -/*P2_FBERERR1*/ -#define RSTV0910_P2_FBERERR1 0xf3ae -#define FSTV0910_P2_FBERMETER_ERR1 0xf3ae00ff - -/*P2_FBERERR0*/ -#define RSTV0910_P2_FBERERR0 0xf3af -#define FSTV0910_P2_FBERMETER_ERR0 0xf3af00ff - -/*P2_FSPYBER*/ -#define RSTV0910_P2_FSPYBER 0xf3b2 -#define FSTV0910_P2_FSPYOBS_XORREAD 0xf3b20040 -#define FSTV0910_P2_FSPYBER_OBSMODE 0xf3b20020 -#define FSTV0910_P2_FSPYBER_SYNCBYTE 0xf3b20010 -#define FSTV0910_P2_FSPYBER_UNSYNC 0xf3b20008 -#define FSTV0910_P2_FSPYBER_CTIME 0xf3b20007 - -/*P2_SFERROR*/ -#define RSTV0910_P2_SFERROR 0xf3c1 -#define FSTV0910_P2_SFEC_REGERR_VIT 0xf3c100ff - -/*P2_SFECSTATUS*/ -#define RSTV0910_P2_SFECSTATUS 0xf3c3 -#define FSTV0910_P2_SFEC_ON 0xf3c30080 -#define FSTV0910_P2_SFEC_OFF 0xf3c30040 -#define FSTV0910_P2_LOCKEDSFEC 0xf3c30008 -#define FSTV0910_P2_SFEC_DELOCK 0xf3c30004 -#define FSTV0910_P2_SFEC_DEMODSEL 0xf3c30002 -#define FSTV0910_P2_SFEC_OVFON 0xf3c30001 - -/*P2_SFKDIV12*/ -#define RSTV0910_P2_SFKDIV12 0xf3c4 -#define FSTV0910_P2_SFECKDIV12_MAN 0xf3c40080 -#define FSTV0910_P2_SFEC_K_DIVIDER_12 0xf3c4007f - -/*P2_SFKDIV23*/ -#define RSTV0910_P2_SFKDIV23 0xf3c5 -#define FSTV0910_P2_SFECKDIV23_MAN 0xf3c50080 -#define FSTV0910_P2_SFEC_K_DIVIDER_23 0xf3c5007f - -/*P2_SFKDIV34*/ -#define RSTV0910_P2_SFKDIV34 0xf3c6 -#define FSTV0910_P2_SFECKDIV34_MAN 0xf3c60080 -#define FSTV0910_P2_SFEC_K_DIVIDER_34 0xf3c6007f - -/*P2_SFKDIV56*/ -#define RSTV0910_P2_SFKDIV56 0xf3c7 -#define FSTV0910_P2_SFECKDIV56_MAN 0xf3c70080 -#define FSTV0910_P2_SFEC_K_DIVIDER_56 0xf3c7007f - -/*P2_SFKDIV67*/ -#define RSTV0910_P2_SFKDIV67 0xf3c8 -#define FSTV0910_P2_SFECKDIV67_MAN 0xf3c80080 -#define FSTV0910_P2_SFEC_K_DIVIDER_67 0xf3c8007f - -/*P2_SFKDIV78*/ -#define RSTV0910_P2_SFKDIV78 0xf3c9 -#define FSTV0910_P2_SFECKDIV78_MAN 0xf3c90080 -#define FSTV0910_P2_SFEC_K_DIVIDER_78 0xf3c9007f - -/*P2_SFSTATUS*/ -#define RSTV0910_P2_SFSTATUS 0xf3cc -#define FSTV0910_P2_SFEC_LINEOK 0xf3cc0080 -#define FSTV0910_P2_SFEC_ERROR 0xf3cc0040 -#define FSTV0910_P2_SFEC_DATA7 0xf3cc0020 -#define FSTV0910_P2_SFEC_PKTDNBRFAIL 0xf3cc0010 -#define FSTV0910_P2_TSSFEC_DEMODSEL 0xf3cc0008 -#define FSTV0910_P2_SFEC_NOSYNC 0xf3cc0004 -#define FSTV0910_P2_SFEC_UNREGULA 0xf3cc0002 -#define FSTV0910_P2_SFEC_READY 0xf3cc0001 - -/*P2_SFDLYSET2*/ -#define RSTV0910_P2_SFDLYSET2 0xf3d0 -#define FSTV0910_P2_SFEC_OFFSET 0xf3d000c0 -#define FSTV0910_P2_RST_SFEC 0xf3d00008 -#define FSTV0910_P2_DILDLINE_ERROR 0xf3d00004 -#define FSTV0910_P2_SFEC_DISABLE 0xf3d00002 -#define FSTV0910_P2_SFEC_UNREGUL 0xf3d00001 - -/*P2_SFERRCTRL*/ -#define RSTV0910_P2_SFERRCTRL 0xf3d8 -#define FSTV0910_P2_SFEC_ERR_SOURCE 0xf3d800f0 -#define FSTV0910_P2_SFEC_NUM_EVENT 0xf3d80007 - -/*P2_SFERRCNT2*/ -#define RSTV0910_P2_SFERRCNT2 0xf3d9 -#define FSTV0910_P2_SFERRC_OLDVALUE 0xf3d90080 -#define FSTV0910_P2_SFEC_ERR_CNT2 0xf3d9007f - -/*P2_SFERRCNT1*/ -#define RSTV0910_P2_SFERRCNT1 0xf3da -#define FSTV0910_P2_SFEC_ERR_CNT1 0xf3da00ff - -/*P2_SFERRCNT0*/ -#define RSTV0910_P2_SFERRCNT0 0xf3db -#define FSTV0910_P2_SFEC_ERR_CNT0 0xf3db00ff - -/*P1_IQCONST*/ -#define RSTV0910_P1_IQCONST 0xf400 -#define FSTV0910_P1_CONSTEL_SELECT 0xf4000060 -#define FSTV0910_P1_IQSYMB_SEL 0xf400001f - -/*P1_NOSCFG*/ -#define RSTV0910_P1_NOSCFG 0xf401 -#define FSTV0910_P1_DIS_ACMRATIO 0xf4010080 -#define FSTV0910_P1_NOSIN_EGALSEL 0xf4010040 -#define FSTV0910_P1_DUMMYPL_NOSDATA 0xf4010020 -#define FSTV0910_P1_NOSPLH_BETA 0xf4010018 -#define FSTV0910_P1_NOSDATA_BETA 0xf4010007 - -/*P1_ISYMB*/ -#define RSTV0910_P1_ISYMB 0xf402 -#define FSTV0910_P1_I_SYMBOL 0xf40201ff - -/*P1_QSYMB*/ -#define RSTV0910_P1_QSYMB 0xf403 -#define FSTV0910_P1_Q_SYMBOL 0xf40301ff - -/*P1_AGC1CFG*/ -#define RSTV0910_P1_AGC1CFG 0xf404 -#define FSTV0910_P1_DC_FROZEN 0xf4040080 -#define FSTV0910_P1_DC_CORRECT 0xf4040040 -#define FSTV0910_P1_AMM_FROZEN 0xf4040020 -#define FSTV0910_P1_AMM_CORRECT 0xf4040010 -#define FSTV0910_P1_QUAD_FROZEN 0xf4040008 -#define FSTV0910_P1_QUAD_CORRECT 0xf4040004 -#define FSTV0910_P1_DCCOMP_SLOW 0xf4040002 -#define FSTV0910_P1_IQMISM_SLOW 0xf4040001 - -/*P1_AGC1CN*/ -#define RSTV0910_P1_AGC1CN 0xf406 -#define FSTV0910_P1_AGC1_LOCKED 0xf4060080 -#define FSTV0910_P1_AGC1_OVERFLOW 0xf4060040 -#define FSTV0910_P1_AGC1_NOSLOWLK 0xf4060020 -#define FSTV0910_P1_AGC1_MINPOWER 0xf4060010 -#define FSTV0910_P1_AGCOUT_FAST 0xf4060008 -#define FSTV0910_P1_AGCIQ_BETA 0xf4060007 - -/*P1_AGC1REF*/ -#define RSTV0910_P1_AGC1REF 0xf407 -#define FSTV0910_P1_AGCIQ_REF 0xf40700ff - -/*P1_IDCCOMP*/ -#define RSTV0910_P1_IDCCOMP 0xf408 -#define FSTV0910_P1_IAVERAGE_ADJ 0xf40801ff - -/*P1_QDCCOMP*/ -#define RSTV0910_P1_QDCCOMP 0xf409 -#define FSTV0910_P1_QAVERAGE_ADJ 0xf40901ff - -/*P1_POWERI*/ -#define RSTV0910_P1_POWERI 0xf40a -#define FSTV0910_P1_POWER_I 0xf40a00ff - -/*P1_POWERQ*/ -#define RSTV0910_P1_POWERQ 0xf40b -#define FSTV0910_P1_POWER_Q 0xf40b00ff - -/*P1_AGC1AMM*/ -#define RSTV0910_P1_AGC1AMM 0xf40c -#define FSTV0910_P1_AMM_VALUE 0xf40c00ff - -/*P1_AGC1QUAD*/ -#define RSTV0910_P1_AGC1QUAD 0xf40d -#define FSTV0910_P1_QUAD_VALUE 0xf40d01ff - -/*P1_AGCIQIN1*/ -#define RSTV0910_P1_AGCIQIN1 0xf40e -#define FSTV0910_P1_AGCIQ_VALUE1 0xf40e00ff - -/*P1_AGCIQIN0*/ -#define RSTV0910_P1_AGCIQIN0 0xf40f -#define FSTV0910_P1_AGCIQ_VALUE0 0xf40f00ff - -/*P1_DEMOD*/ -#define RSTV0910_P1_DEMOD 0xf410 -#define FSTV0910_P1_MANUALS2_ROLLOFF 0xf4100080 -#define FSTV0910_P1_SPECINV_CONTROL 0xf4100030 -#define FSTV0910_P1_MANUALSX_ROLLOFF 0xf4100004 -#define FSTV0910_P1_ROLLOFF_CONTROL 0xf4100003 - -/*P1_DMDMODCOD*/ -#define RSTV0910_P1_DMDMODCOD 0xf411 -#define FSTV0910_P1_MANUAL_MODCOD 0xf4110080 -#define FSTV0910_P1_DEMOD_MODCOD 0xf411007c -#define FSTV0910_P1_DEMOD_TYPE 0xf4110003 - -/*P1_DSTATUS*/ -#define RSTV0910_P1_DSTATUS 0xf412 -#define FSTV0910_P1_CAR_LOCK 0xf4120080 -#define FSTV0910_P1_TMGLOCK_QUALITY 0xf4120060 -#define FSTV0910_P1_SDVBS1_ENABLE 0xf4120010 -#define FSTV0910_P1_LOCK_DEFINITIF 0xf4120008 -#define FSTV0910_P1_TIMING_IS_LOCKED 0xf4120004 -#define FSTV0910_P1_DEMOD_SYSCFG 0xf4120002 -#define FSTV0910_P1_OVADC_DETECT 0xf4120001 - -/*P1_DSTATUS2*/ -#define RSTV0910_P1_DSTATUS2 0xf413 -#define FSTV0910_P1_DEMOD_DELOCK 0xf4130080 -#define FSTV0910_P1_DEMOD_TIMEOUT 0xf4130040 -#define FSTV0910_P1_MODCODRQ_SYNCTAG 0xf4130020 -#define FSTV0910_P1_POLYPH_SATEVENT 0xf4130010 -#define FSTV0910_P1_AGC1_NOSIGNALACK 0xf4130008 -#define FSTV0910_P1_AGC2_OVERFLOW 0xf4130004 -#define FSTV0910_P1_CFR_OVERFLOW 0xf4130002 -#define FSTV0910_P1_GAMMA_OVERUNDER 0xf4130001 - -/*P1_DMDCFGMD*/ -#define RSTV0910_P1_DMDCFGMD 0xf414 -#define FSTV0910_P1_DVBS2_ENABLE 0xf4140080 -#define FSTV0910_P1_DVBS1_ENABLE 0xf4140040 -#define FSTV0910_P1_SCAN_ENABLE 0xf4140010 -#define FSTV0910_P1_CFR_AUTOSCAN 0xf4140008 -#define FSTV0910_P1_NOFORCE_RELOCK 0xf4140004 -#define FSTV0910_P1_TUN_RNG 0xf4140003 - -/*P1_DMDCFG2*/ -#define RSTV0910_P1_DMDCFG2 0xf415 -#define FSTV0910_P1_AGC1_WAITLOCK 0xf4150080 -#define FSTV0910_P1_S1S2_SEQUENTIAL 0xf4150040 -#define FSTV0910_P1_BLINDPEA_MODE 0xf4150020 -#define FSTV0910_P1_INFINITE_RELOCK 0xf4150010 -#define FSTV0910_P1_BWOFFSET_COLDWARM 0xf4150008 -#define FSTV0910_P1_TMGLOCK_NSCANSTOP 0xf4150004 -#define FSTV0910_P1_COARSE_LK3MODE 0xf4150002 -#define FSTV0910_P1_COARSE_LK2MODE 0xf4150001 - -/*P1_DMDISTATE*/ -#define RSTV0910_P1_DMDISTATE 0xf416 -#define FSTV0910_P1_I2C_NORESETDMODE 0xf4160080 -#define FSTV0910_P1_FORCE_ETAPED 0xf4160040 -#define FSTV0910_P1_SDMDRST_DIRCLK 0xf4160020 -#define FSTV0910_P1_I2C_DEMOD_MODE 0xf416001f - -/*P1_DMDT0M*/ -#define RSTV0910_P1_DMDT0M 0xf417 -#define FSTV0910_P1_DMDT0_MIN 0xf41700ff - -/*P1_DMDSTATE*/ -#define RSTV0910_P1_DMDSTATE 0xf41b -#define FSTV0910_P1_DEMOD_LOCKED 0xf41b0080 -#define FSTV0910_P1_HEADER_MODE 0xf41b0060 -#define FSTV0910_P1_DEMOD_MODE 0xf41b001f - -/*P1_DMDFLYW*/ -#define RSTV0910_P1_DMDFLYW 0xf41c -#define FSTV0910_P1_I2C_IRQVAL 0xf41c00f0 -#define FSTV0910_P1_FLYWHEEL_CPT 0xf41c000f - -/*P1_DSTATUS3*/ -#define RSTV0910_P1_DSTATUS3 0xf41d -#define FSTV0910_P1_CFR_ZIGZAG 0xf41d0080 -#define FSTV0910_P1_DEMOD_CFGMODE 0xf41d0060 -#define FSTV0910_P1_GAMMA_LOWBAUDRATE 0xf41d0010 -#define FSTV0910_P1_RELOCK_MODE 0xf41d0008 -#define FSTV0910_P1_DEMOD_FAIL 0xf41d0004 -#define FSTV0910_P1_ETAPE1A_DVBXMEM 0xf41d0003 - -/*P1_DMDCFG3*/ -#define RSTV0910_P1_DMDCFG3 0xf41e -#define FSTV0910_P1_DVBS1_TMGWAIT 0xf41e0080 -#define FSTV0910_P1_NO_BWCENTERING 0xf41e0040 -#define FSTV0910_P1_INV_SEQSRCH 0xf41e0020 -#define FSTV0910_P1_DIS_SFRUPLOW_TRK 0xf41e0010 -#define FSTV0910_P1_NOSTOP_FIFOFULL 0xf41e0008 -#define FSTV0910_P1_LOCKTIME_MODE 0xf41e0007 - -/*P1_DMDCFG4*/ -#define RSTV0910_P1_DMDCFG4 0xf41f -#define FSTV0910_P1_DIS_VITLOCK 0xf41f0080 -#define FSTV0910_P1_S1S2TOUT_FAST 0xf41f0040 -#define FSTV0910_P1_DEMOD_FASTLOCK 0xf41f0020 -#define FSTV0910_P1_S1HIER_ENABLE 0xf41f0010 -#define FSTV0910_P1_TUNER_NRELAUNCH 0xf41f0008 -#define FSTV0910_P1_DIS_CLKENABLE 0xf41f0004 -#define FSTV0910_P1_DIS_HDRDIVLOCK 0xf41f0002 -#define FSTV0910_P1_NO_TNRWBINIT 0xf41f0001 - -/*P1_CORRELMANT*/ -#define RSTV0910_P1_CORRELMANT 0xf420 -#define FSTV0910_P1_CORREL_MANT 0xf42000ff - -/*P1_CORRELABS*/ -#define RSTV0910_P1_CORRELABS 0xf421 -#define FSTV0910_P1_CORREL_ABS 0xf42100ff - -/*P1_CORRELEXP*/ -#define RSTV0910_P1_CORRELEXP 0xf422 -#define FSTV0910_P1_CORREL_ABSEXP 0xf42200f0 -#define FSTV0910_P1_CORREL_EXP 0xf422000f - -/*P1_PLHMODCOD*/ -#define RSTV0910_P1_PLHMODCOD 0xf424 -#define FSTV0910_P1_SPECINV_DEMOD 0xf4240080 -#define FSTV0910_P1_PLH_MODCOD 0xf424007c -#define FSTV0910_P1_PLH_TYPE 0xf4240003 - -/*P1_DMDREG*/ -#define RSTV0910_P1_DMDREG 0xf425 -#define FSTV0910_P1_EXTPSK_MODE 0xf4250080 -#define FSTV0910_P1_HIER_SHORTFRAME 0xf4250002 -#define FSTV0910_P1_DECIM_PLFRAMES 0xf4250001 - -/*P1_AGC2O*/ -#define RSTV0910_P1_AGC2O 0xf42c -#define FSTV0910_P1_CSTENV_MODE 0xf42c00c0 -#define FSTV0910_P1_AGC2_LKSQRT 0xf42c0020 -#define FSTV0910_P1_AGC2_LKMODE 0xf42c0010 -#define FSTV0910_P1_AGC2_LKEQUA 0xf42c0008 -#define FSTV0910_P1_AGC2_COEF 0xf42c0007 - -/*P1_AGC2REF*/ -#define RSTV0910_P1_AGC2REF 0xf42d -#define FSTV0910_P1_AGC2_REF 0xf42d00ff - -/*P1_AGC1ADJ*/ -#define RSTV0910_P1_AGC1ADJ 0xf42e -#define FSTV0910_P1_AGC1ADJ_MANUAL 0xf42e0080 -#define FSTV0910_P1_AGC1_ADJUSTED 0xf42e007f - -/*P1_AGC2I1*/ -#define RSTV0910_P1_AGC2I1 0xf436 -#define FSTV0910_P1_AGC2_INTEGRATOR1 0xf43600ff - -/*P1_AGC2I0*/ -#define RSTV0910_P1_AGC2I0 0xf437 -#define FSTV0910_P1_AGC2_INTEGRATOR0 0xf43700ff - -/*P1_CARCFG*/ -#define RSTV0910_P1_CARCFG 0xf438 -#define FSTV0910_P1_CFRUPLOW_AUTO 0xf4380080 -#define FSTV0910_P1_CFRUPLOW_TEST 0xf4380040 -#define FSTV0910_P1_WIDE_FREQDET 0xf4380020 -#define FSTV0910_P1_CARHDR_NODIV8 0xf4380010 -#define FSTV0910_P1_I2C_ROTA 0xf4380008 -#define FSTV0910_P1_ROTAON 0xf4380004 -#define FSTV0910_P1_PH_DET_ALGO 0xf4380003 - -/*P1_ACLC*/ -#define RSTV0910_P1_ACLC 0xf439 -#define FSTV0910_P1_CARS1_ANOSAUTO 0xf4390040 -#define FSTV0910_P1_CAR_ALPHA_MANT 0xf4390030 -#define FSTV0910_P1_CAR_ALPHA_EXP 0xf439000f - -/*P1_BCLC*/ -#define RSTV0910_P1_BCLC 0xf43a -#define FSTV0910_P1_CARS1_BNOSAUTO 0xf43a0040 -#define FSTV0910_P1_CAR_BETA_MANT 0xf43a0030 -#define FSTV0910_P1_CAR_BETA_EXP 0xf43a000f - -/*P1_CARFREQ*/ -#define RSTV0910_P1_CARFREQ 0xf43d -#define FSTV0910_P1_KC_COARSE_EXP 0xf43d00f0 -#define FSTV0910_P1_BETA_FREQ 0xf43d000f - -/*P1_CARHDR*/ -#define RSTV0910_P1_CARHDR 0xf43e -#define FSTV0910_P1_K_FREQ_HDR 0xf43e00ff - -/*P1_LDT*/ -#define RSTV0910_P1_LDT 0xf43f -#define FSTV0910_P1_CARLOCK_THRES 0xf43f01ff - -/*P1_LDT2*/ -#define RSTV0910_P1_LDT2 0xf440 -#define FSTV0910_P1_CARLOCK_THRES2 0xf44001ff - -/*P1_CFRICFG*/ -#define RSTV0910_P1_CFRICFG 0xf441 -#define FSTV0910_P1_CFRINIT_UNVALRNG 0xf4410080 -#define FSTV0910_P1_CFRINIT_LUNVALCPT 0xf4410040 -#define FSTV0910_P1_CFRINIT_ABORTDBL 0xf4410020 -#define FSTV0910_P1_CFRINIT_ABORTPRED 0xf4410010 -#define FSTV0910_P1_CFRINIT_UNVALSKIP 0xf4410008 -#define FSTV0910_P1_CFRINIT_CSTINC 0xf4410004 -#define FSTV0910_P1_CFRIROLL_GARDER 0xf4410002 -#define FSTV0910_P1_NEG_CFRSTEP 0xf4410001 - -/*P1_CFRUP1*/ -#define RSTV0910_P1_CFRUP1 0xf442 -#define FSTV0910_P1_CFR_UP1 0xf44201ff - -/*P1_CFRUP0*/ -#define RSTV0910_P1_CFRUP0 0xf443 -#define FSTV0910_P1_CFR_UP0 0xf44300ff - -/*P1_CFRIBASE1*/ -#define RSTV0910_P1_CFRIBASE1 0xf444 -#define FSTV0910_P1_CFRINIT_BASE1 0xf44400ff - -/*P1_CFRIBASE0*/ -#define RSTV0910_P1_CFRIBASE0 0xf445 -#define FSTV0910_P1_CFRINIT_BASE0 0xf44500ff - -/*P1_CFRLOW1*/ -#define RSTV0910_P1_CFRLOW1 0xf446 -#define FSTV0910_P1_CFR_LOW1 0xf44601ff - -/*P1_CFRLOW0*/ -#define RSTV0910_P1_CFRLOW0 0xf447 -#define FSTV0910_P1_CFR_LOW0 0xf44700ff - -/*P1_CFRINIT1*/ -#define RSTV0910_P1_CFRINIT1 0xf448 -#define FSTV0910_P1_CFR_INIT1 0xf44801ff - -/*P1_CFRINIT0*/ -#define RSTV0910_P1_CFRINIT0 0xf449 -#define FSTV0910_P1_CFR_INIT0 0xf44900ff - -/*P1_CFRINC1*/ -#define RSTV0910_P1_CFRINC1 0xf44a -#define FSTV0910_P1_MANUAL_CFRINC 0xf44a0080 -#define FSTV0910_P1_CFR_INC1 0xf44a003f - -/*P1_CFRINC0*/ -#define RSTV0910_P1_CFRINC0 0xf44b -#define FSTV0910_P1_CFR_INC0 0xf44b00ff - -/*P1_CFR2*/ -#define RSTV0910_P1_CFR2 0xf44c -#define FSTV0910_P1_CAR_FREQ2 0xf44c01ff - -/*P1_CFR1*/ -#define RSTV0910_P1_CFR1 0xf44d -#define FSTV0910_P1_CAR_FREQ1 0xf44d00ff - -/*P1_CFR0*/ -#define RSTV0910_P1_CFR0 0xf44e -#define FSTV0910_P1_CAR_FREQ0 0xf44e00ff - -/*P1_LDI*/ -#define RSTV0910_P1_LDI 0xf44f -#define FSTV0910_P1_LOCK_DET_INTEGR 0xf44f01ff - -/*P1_TMGCFG*/ -#define RSTV0910_P1_TMGCFG 0xf450 -#define FSTV0910_P1_TMGLOCK_BETA 0xf45000c0 -#define FSTV0910_P1_DO_TIMING_CORR 0xf4500010 -#define FSTV0910_P1_MANUAL_SCAN 0xf450000c -#define FSTV0910_P1_TMG_MINFREQ 0xf4500003 - -/*P1_RTC*/ -#define RSTV0910_P1_RTC 0xf451 -#define FSTV0910_P1_TMGALPHA_EXP 0xf45100f0 -#define FSTV0910_P1_TMGBETA_EXP 0xf451000f - -/*P1_RTCS2*/ -#define RSTV0910_P1_RTCS2 0xf452 -#define FSTV0910_P1_TMGALPHAS2_EXP 0xf45200f0 -#define FSTV0910_P1_TMGBETAS2_EXP 0xf452000f - -/*P1_TMGTHRISE*/ -#define RSTV0910_P1_TMGTHRISE 0xf453 -#define FSTV0910_P1_TMGLOCK_THRISE 0xf45300ff - -/*P1_TMGTHFALL*/ -#define RSTV0910_P1_TMGTHFALL 0xf454 -#define FSTV0910_P1_TMGLOCK_THFALL 0xf45400ff - -/*P1_SFRUPRATIO*/ -#define RSTV0910_P1_SFRUPRATIO 0xf455 -#define FSTV0910_P1_SFR_UPRATIO 0xf45500ff - -/*P1_SFRLOWRATIO*/ -#define RSTV0910_P1_SFRLOWRATIO 0xf456 -#define FSTV0910_P1_SFR_LOWRATIO 0xf45600ff - -/*P1_KTTMG*/ -#define RSTV0910_P1_KTTMG 0xf457 -#define FSTV0910_P1_KT_TMG_EXP 0xf45700f0 - -/*P1_KREFTMG*/ -#define RSTV0910_P1_KREFTMG 0xf458 -#define FSTV0910_P1_KREF_TMG 0xf45800ff - -/*P1_SFRSTEP*/ -#define RSTV0910_P1_SFRSTEP 0xf459 -#define FSTV0910_P1_SFR_SCANSTEP 0xf45900f0 -#define FSTV0910_P1_SFR_CENTERSTEP 0xf459000f - -/*P1_TMGCFG2*/ -#define RSTV0910_P1_TMGCFG2 0xf45a -#define FSTV0910_P1_KREFTMG2_DECMODE 0xf45a00c0 -#define FSTV0910_P1_DIS_AUTOSAMP 0xf45a0008 -#define FSTV0910_P1_SCANINIT_QUART 0xf45a0004 -#define FSTV0910_P1_NOTMG_DVBS1DERAT 0xf45a0002 -#define FSTV0910_P1_SFRRATIO_FINE 0xf45a0001 - -/*P1_KREFTMG2*/ -#define RSTV0910_P1_KREFTMG2 0xf45b -#define FSTV0910_P1_KREF_TMG2 0xf45b00ff - -/*P1_TMGCFG3*/ -#define RSTV0910_P1_TMGCFG3 0xf45d -#define FSTV0910_P1_CFRINC_MODE 0xf45d0070 -#define FSTV0910_P1_CONT_TMGCENTER 0xf45d0008 -#define FSTV0910_P1_AUTO_GUP 0xf45d0004 -#define FSTV0910_P1_AUTO_GLOW 0xf45d0002 -#define FSTV0910_P1_SFRVAL_MINMODE 0xf45d0001 - -/*P1_SFRINIT1*/ -#define RSTV0910_P1_SFRINIT1 0xf45e -#define FSTV0910_P1_SFR_INIT1 0xf45e00ff - -/*P1_SFRINIT0*/ -#define RSTV0910_P1_SFRINIT0 0xf45f -#define FSTV0910_P1_SFR_INIT0 0xf45f00ff - -/*P1_SFRUP1*/ -#define RSTV0910_P1_SFRUP1 0xf460 -#define FSTV0910_P1_SYMB_FREQ_UP1 0xf46000ff - -/*P1_SFRUP0*/ -#define RSTV0910_P1_SFRUP0 0xf461 -#define FSTV0910_P1_SYMB_FREQ_UP0 0xf46100ff - -/*P1_SFRLOW1*/ -#define RSTV0910_P1_SFRLOW1 0xf462 -#define FSTV0910_P1_SYMB_FREQ_LOW1 0xf46200ff - -/*P1_SFRLOW0*/ -#define RSTV0910_P1_SFRLOW0 0xf463 -#define FSTV0910_P1_SYMB_FREQ_LOW0 0xf46300ff - -/*P1_SFR3*/ -#define RSTV0910_P1_SFR3 0xf464 -#define FSTV0910_P1_SYMB_FREQ3 0xf46400ff - -/*P1_SFR2*/ -#define RSTV0910_P1_SFR2 0xf465 -#define FSTV0910_P1_SYMB_FREQ2 0xf46500ff - -/*P1_SFR1*/ -#define RSTV0910_P1_SFR1 0xf466 -#define FSTV0910_P1_SYMB_FREQ1 0xf46600ff - -/*P1_SFR0*/ -#define RSTV0910_P1_SFR0 0xf467 -#define FSTV0910_P1_SYMB_FREQ0 0xf46700ff - -/*P1_TMGREG2*/ -#define RSTV0910_P1_TMGREG2 0xf468 -#define FSTV0910_P1_TMGREG2 0xf46800ff - -/*P1_TMGREG1*/ -#define RSTV0910_P1_TMGREG1 0xf469 -#define FSTV0910_P1_TMGREG1 0xf46900ff - -/*P1_TMGREG0*/ -#define RSTV0910_P1_TMGREG0 0xf46a -#define FSTV0910_P1_TMGREG0 0xf46a00ff - -/*P1_TMGLOCK1*/ -#define RSTV0910_P1_TMGLOCK1 0xf46b -#define FSTV0910_P1_TMGLOCK_LEVEL1 0xf46b01ff - -/*P1_TMGLOCK0*/ -#define RSTV0910_P1_TMGLOCK0 0xf46c -#define FSTV0910_P1_TMGLOCK_LEVEL0 0xf46c00ff - -/*P1_TMGOBS*/ -#define RSTV0910_P1_TMGOBS 0xf46d -#define FSTV0910_P1_ROLLOFF_STATUS 0xf46d00c0 -#define FSTV0910_P1_SCAN_SIGN 0xf46d0030 -#define FSTV0910_P1_TMG_SCANNING 0xf46d0008 -#define FSTV0910_P1_CHCENTERING_MODE 0xf46d0004 -#define FSTV0910_P1_TMG_SCANFAIL 0xf46d0002 - -/*P1_EQUALCFG*/ -#define RSTV0910_P1_EQUALCFG 0xf46f -#define FSTV0910_P1_NOTMG_NEGALWAIT 0xf46f0080 -#define FSTV0910_P1_EQUAL_ON 0xf46f0040 -#define FSTV0910_P1_SEL_EQUALCOR 0xf46f0038 -#define FSTV0910_P1_MU_EQUALDFE 0xf46f0007 - -/*P1_EQUAI1*/ -#define RSTV0910_P1_EQUAI1 0xf470 -#define FSTV0910_P1_EQUA_ACCI1 0xf47001ff - -/*P1_EQUAQ1*/ -#define RSTV0910_P1_EQUAQ1 0xf471 -#define FSTV0910_P1_EQUA_ACCQ1 0xf47101ff - -/*P1_EQUAI2*/ -#define RSTV0910_P1_EQUAI2 0xf472 -#define FSTV0910_P1_EQUA_ACCI2 0xf47201ff - -/*P1_EQUAQ2*/ -#define RSTV0910_P1_EQUAQ2 0xf473 -#define FSTV0910_P1_EQUA_ACCQ2 0xf47301ff - -/*P1_EQUAI3*/ -#define RSTV0910_P1_EQUAI3 0xf474 -#define FSTV0910_P1_EQUA_ACCI3 0xf47401ff - -/*P1_EQUAQ3*/ -#define RSTV0910_P1_EQUAQ3 0xf475 -#define FSTV0910_P1_EQUA_ACCQ3 0xf47501ff - -/*P1_EQUAI4*/ -#define RSTV0910_P1_EQUAI4 0xf476 -#define FSTV0910_P1_EQUA_ACCI4 0xf47601ff - -/*P1_EQUAQ4*/ -#define RSTV0910_P1_EQUAQ4 0xf477 -#define FSTV0910_P1_EQUA_ACCQ4 0xf47701ff - -/*P1_EQUAI5*/ -#define RSTV0910_P1_EQUAI5 0xf478 -#define FSTV0910_P1_EQUA_ACCI5 0xf47801ff - -/*P1_EQUAQ5*/ -#define RSTV0910_P1_EQUAQ5 0xf479 -#define FSTV0910_P1_EQUA_ACCQ5 0xf47901ff - -/*P1_EQUAI6*/ -#define RSTV0910_P1_EQUAI6 0xf47a -#define FSTV0910_P1_EQUA_ACCI6 0xf47a01ff - -/*P1_EQUAQ6*/ -#define RSTV0910_P1_EQUAQ6 0xf47b -#define FSTV0910_P1_EQUA_ACCQ6 0xf47b01ff - -/*P1_EQUAI7*/ -#define RSTV0910_P1_EQUAI7 0xf47c -#define FSTV0910_P1_EQUA_ACCI7 0xf47c01ff - -/*P1_EQUAQ7*/ -#define RSTV0910_P1_EQUAQ7 0xf47d -#define FSTV0910_P1_EQUA_ACCQ7 0xf47d01ff - -/*P1_EQUAI8*/ -#define RSTV0910_P1_EQUAI8 0xf47e -#define FSTV0910_P1_EQUA_ACCI8 0xf47e01ff - -/*P1_EQUAQ8*/ -#define RSTV0910_P1_EQUAQ8 0xf47f -#define FSTV0910_P1_EQUA_ACCQ8 0xf47f01ff - -/*P1_NNOSDATAT1*/ -#define RSTV0910_P1_NNOSDATAT1 0xf480 -#define FSTV0910_P1_NOSDATAT_NORMED1 0xf48000ff - -/*P1_NNOSDATAT0*/ -#define RSTV0910_P1_NNOSDATAT0 0xf481 -#define FSTV0910_P1_NOSDATAT_NORMED0 0xf48100ff - -/*P1_NNOSDATA1*/ -#define RSTV0910_P1_NNOSDATA1 0xf482 -#define FSTV0910_P1_NOSDATA_NORMED1 0xf48200ff - -/*P1_NNOSDATA0*/ -#define RSTV0910_P1_NNOSDATA0 0xf483 -#define FSTV0910_P1_NOSDATA_NORMED0 0xf48300ff - -/*P1_NNOSPLHT1*/ -#define RSTV0910_P1_NNOSPLHT1 0xf484 -#define FSTV0910_P1_NOSPLHT_NORMED1 0xf48400ff - -/*P1_NNOSPLHT0*/ -#define RSTV0910_P1_NNOSPLHT0 0xf485 -#define FSTV0910_P1_NOSPLHT_NORMED0 0xf48500ff - -/*P1_NNOSPLH1*/ -#define RSTV0910_P1_NNOSPLH1 0xf486 -#define FSTV0910_P1_NOSPLH_NORMED1 0xf48600ff - -/*P1_NNOSPLH0*/ -#define RSTV0910_P1_NNOSPLH0 0xf487 -#define FSTV0910_P1_NOSPLH_NORMED0 0xf48700ff - -/*P1_NOSDATAT1*/ -#define RSTV0910_P1_NOSDATAT1 0xf488 -#define FSTV0910_P1_NOSDATAT_UNNORMED1 0xf48800ff - -/*P1_NOSDATAT0*/ -#define RSTV0910_P1_NOSDATAT0 0xf489 -#define FSTV0910_P1_NOSDATAT_UNNORMED0 0xf48900ff - -/*P1_NNOSFRAME1*/ -#define RSTV0910_P1_NNOSFRAME1 0xf48a -#define FSTV0910_P1_NOSFRAME_NORMED1 0xf48a00ff - -/*P1_NNOSFRAME0*/ -#define RSTV0910_P1_NNOSFRAME0 0xf48b -#define FSTV0910_P1_NOSFRAME_NORMED0 0xf48b00ff - -/*P1_NNOSRAD1*/ -#define RSTV0910_P1_NNOSRAD1 0xf48c -#define FSTV0910_P1_NOSRADIAL_NORMED1 0xf48c00ff - -/*P1_NNOSRAD0*/ -#define RSTV0910_P1_NNOSRAD0 0xf48d -#define FSTV0910_P1_NOSRADIAL_NORMED0 0xf48d00ff - -/*P1_NOSCFGF1*/ -#define RSTV0910_P1_NOSCFGF1 0xf48e -#define FSTV0910_P1_LOWNOISE_MESURE 0xf48e0080 -#define FSTV0910_P1_NOS_DELFRAME 0xf48e0040 -#define FSTV0910_P1_NOSDATA_MODE 0xf48e0030 -#define FSTV0910_P1_FRAMESEL_TYPESEL 0xf48e000c -#define FSTV0910_P1_FRAMESEL_TYPE 0xf48e0003 - -/*P1_CAR2CFG*/ -#define RSTV0910_P1_CAR2CFG 0xf490 -#define FSTV0910_P1_DESCRAMB_OFF 0xf4900080 -#define FSTV0910_P1_EN_PHNOSRAM 0xf4900020 -#define FSTV0910_P1_STOP_CFR2UPDATE 0xf4900010 -#define FSTV0910_P1_STOP_NCO2UPDATE 0xf4900008 -#define FSTV0910_P1_ROTA2ON 0xf4900004 -#define FSTV0910_P1_PH_DET_ALGO2 0xf4900003 - -/*P1_CFR2CFR1*/ -#define RSTV0910_P1_CFR2CFR1 0xf491 -#define FSTV0910_P1_CFR2_S2CONTROL 0xf49100c0 -#define FSTV0910_P1_EN_S2CAR2CENTER 0xf4910020 -#define FSTV0910_P1_BCHERRCFR2_MODE 0xf4910018 -#define FSTV0910_P1_CFR2TOCFR1_BETA 0xf4910007 - -/*P1_CAR3CFG*/ -#define RSTV0910_P1_CAR3CFG 0xf492 -#define FSTV0910_P1_CARRIER23_MODE 0xf49200c0 -#define FSTV0910_P1_CAR3INTERM_DVBS1 0xf4920020 -#define FSTV0910_P1_ABAMPLIF_MODE 0xf4920018 -#define FSTV0910_P1_CARRIER3_ALPHA3DL 0xf4920007 - -/*P1_CFR22*/ -#define RSTV0910_P1_CFR22 0xf493 -#define FSTV0910_P1_CAR2_FREQ2 0xf49301ff - -/*P1_CFR21*/ -#define RSTV0910_P1_CFR21 0xf494 -#define FSTV0910_P1_CAR2_FREQ1 0xf49400ff - -/*P1_CFR20*/ -#define RSTV0910_P1_CFR20 0xf495 -#define FSTV0910_P1_CAR2_FREQ0 0xf49500ff - -/*P1_ACLC2S2Q*/ -#define RSTV0910_P1_ACLC2S2Q 0xf497 -#define FSTV0910_P1_ENAB_SPSKSYMB 0xf4970080 -#define FSTV0910_P1_CAR2S2_QANOSAUTO 0xf4970040 -#define FSTV0910_P1_CAR2S2_Q_ALPH_M 0xf4970030 -#define FSTV0910_P1_CAR2S2_Q_ALPH_E 0xf497000f - -/*P1_ACLC2S28*/ -#define RSTV0910_P1_ACLC2S28 0xf498 -#define FSTV0910_P1_OLDI3Q_MODE 0xf4980080 -#define FSTV0910_P1_CAR2S2_8ANOSAUTO 0xf4980040 -#define FSTV0910_P1_CAR2S2_8_ALPH_M 0xf4980030 -#define FSTV0910_P1_CAR2S2_8_ALPH_E 0xf498000f - -/*P1_ACLC2S216A*/ -#define RSTV0910_P1_ACLC2S216A 0xf499 -#define FSTV0910_P1_CAR2S2_16ANOSAUTO 0xf4990040 -#define FSTV0910_P1_CAR2S2_16A_ALPH_M 0xf4990030 -#define FSTV0910_P1_CAR2S2_16A_ALPH_E 0xf499000f - -/*P1_ACLC2S232A*/ -#define RSTV0910_P1_ACLC2S232A 0xf49a -#define FSTV0910_P1_CAR2S2_32ANOSUATO 0xf49a0040 -#define FSTV0910_P1_CAR2S2_32A_ALPH_M 0xf49a0030 -#define FSTV0910_P1_CAR2S2_32A_ALPH_E 0xf49a000f - -/*P1_BCLC2S2Q*/ -#define RSTV0910_P1_BCLC2S2Q 0xf49c -#define FSTV0910_P1_DVBS2S2Q_NIP 0xf49c0080 -#define FSTV0910_P1_CAR2S2_QBNOSAUTO 0xf49c0040 -#define FSTV0910_P1_CAR2S2_Q_BETA_M 0xf49c0030 -#define FSTV0910_P1_CAR2S2_Q_BETA_E 0xf49c000f - -/*P1_BCLC2S28*/ -#define RSTV0910_P1_BCLC2S28 0xf49d -#define FSTV0910_P1_DVBS2S28_NIP 0xf49d0080 -#define FSTV0910_P1_CAR2S2_8BNOSAUTO 0xf49d0040 -#define FSTV0910_P1_CAR2S2_8_BETA_M 0xf49d0030 -#define FSTV0910_P1_CAR2S2_8_BETA_E 0xf49d000f - -/*P1_PLROOT2*/ -#define RSTV0910_P1_PLROOT2 0xf4ac -#define FSTV0910_P1_PLHAUTO_DISPLH 0xf4ac0040 -#define FSTV0910_P1_PLHAUTO_FASTMODE 0xf4ac0020 -#define FSTV0910_P1_PLHAUTO_ENABLE 0xf4ac0010 -#define FSTV0910_P1_PLSCRAMB_MODE 0xf4ac000c -#define FSTV0910_P1_PLSCRAMB_ROOT2 0xf4ac0003 - -/*P1_PLROOT1*/ -#define RSTV0910_P1_PLROOT1 0xf4ad -#define FSTV0910_P1_PLSCRAMB_ROOT1 0xf4ad00ff - -/*P1_PLROOT0*/ -#define RSTV0910_P1_PLROOT0 0xf4ae -#define FSTV0910_P1_PLSCRAMB_ROOT0 0xf4ae00ff - -/*P1_MODCODLST7*/ -#define RSTV0910_P1_MODCODLST7 0xf4b7 -#define FSTV0910_P1_MODCOD_NNOSFILTER 0xf4b70080 -#define FSTV0910_P1_MODCODLST_NOSTYPE 0xf4b70040 -#define FSTV0910_P1_DIS_8PSK_9_10 0xf4b70030 -#define FSTV0910_P1_DIS_8P_8_9 0xf4b7000f - -/*P1_MODCODLST8*/ -#define RSTV0910_P1_MODCODLST8 0xf4b8 -#define FSTV0910_P1_DIS_8P_5_6 0xf4b800f0 -#define FSTV0910_P1_DIS_8P_3_4 0xf4b8000f - -/*P1_MODCODLST9*/ -#define RSTV0910_P1_MODCODLST9 0xf4b9 -#define FSTV0910_P1_DIS_8P_2_3 0xf4b900f0 -#define FSTV0910_P1_DIS_8P_3_5 0xf4b9000f - -/*P1_MODCODLSTA*/ -#define RSTV0910_P1_MODCODLSTA 0xf4ba -#define FSTV0910_P1_NOSFILTER_LIMITE 0xf4ba0080 -#define FSTV0910_P1_NOSFILTER_MODE 0xf4ba0040 -#define FSTV0910_P1_DIS_QPSK_9_10 0xf4ba0030 -#define FSTV0910_P1_DIS_QP_8_9 0xf4ba000f - -/*P1_MODCODLSTB*/ -#define RSTV0910_P1_MODCODLSTB 0xf4bb -#define FSTV0910_P1_DIS_QP_5_6 0xf4bb00f0 -#define FSTV0910_P1_DIS_QP_4_5 0xf4bb000f - -/*P1_MODCODLSTC*/ -#define RSTV0910_P1_MODCODLSTC 0xf4bc -#define FSTV0910_P1_DIS_QP_3_4 0xf4bc00f0 -#define FSTV0910_P1_DIS_QP_2_3 0xf4bc000f - -/*P1_MODCODLSTD*/ -#define RSTV0910_P1_MODCODLSTD 0xf4bd -#define FSTV0910_P1_DIS_QPSK_3_5 0xf4bd00f0 -#define FSTV0910_P1_DIS_QPSK_1_2 0xf4bd000f - -/*P1_GAUSSR0*/ -#define RSTV0910_P1_GAUSSR0 0xf4c0 -#define FSTV0910_P1_EN_CCIMODE 0xf4c00080 -#define FSTV0910_P1_R0_GAUSSIEN 0xf4c0007f - -/*P1_CCIR0*/ -#define RSTV0910_P1_CCIR0 0xf4c1 -#define FSTV0910_P1_CCIDETECT_PLHONLY 0xf4c10080 -#define FSTV0910_P1_R0_CCI 0xf4c1007f - -/*P1_CCIQUANT*/ -#define RSTV0910_P1_CCIQUANT 0xf4c2 -#define FSTV0910_P1_CCI_BETA 0xf4c200e0 -#define FSTV0910_P1_CCI_QUANT 0xf4c2001f - -/*P1_CCITHRES*/ -#define RSTV0910_P1_CCITHRES 0xf4c3 -#define FSTV0910_P1_CCI_THRESHOLD 0xf4c300ff - -/*P1_CCIACC*/ -#define RSTV0910_P1_CCIACC 0xf4c4 -#define FSTV0910_P1_CCI_VALUE 0xf4c400ff - -/*P1_DSTATUS4*/ -#define RSTV0910_P1_DSTATUS4 0xf4c5 -#define FSTV0910_P1_RAINFADE_DETECT 0xf4c50080 -#define FSTV0910_P1_NOTHRES2_FAIL 0xf4c50040 -#define FSTV0910_P1_NOTHRES1_FAIL 0xf4c50020 -#define FSTV0910_P1_PILOT_FAILDETECT 0xf4c50010 -#define FSTV0910_P1_HIER_DETECT 0xf4c50008 -#define FSTV0910_P1_DMDPROG_ERROR 0xf4c50004 -#define FSTV0910_P1_CSTENV_DETECT 0xf4c50002 -#define FSTV0910_P1_DETECTION_TRIAX 0xf4c50001 - -/*P1_DMDRESCFG*/ -#define RSTV0910_P1_DMDRESCFG 0xf4c6 -#define FSTV0910_P1_DMDRES_RESET 0xf4c60080 -#define FSTV0910_P1_DMDRES_NOISESQR 0xf4c60010 -#define FSTV0910_P1_DMDRES_STRALL 0xf4c60008 -#define FSTV0910_P1_DMDRES_NEWONLY 0xf4c60004 -#define FSTV0910_P1_DMDRES_NOSTORE 0xf4c60002 -#define FSTV0910_P1_DMDRES_AGC2MEM 0xf4c60001 - -/*P1_DMDRESADR*/ -#define RSTV0910_P1_DMDRESADR 0xf4c7 -#define FSTV0910_P1_SUSP_PREDCANAL 0xf4c70080 -#define FSTV0910_P1_DMDRES_VALIDCFR 0xf4c70040 -#define FSTV0910_P1_DMDRES_MEMFULL 0xf4c70030 -#define FSTV0910_P1_DMDRES_RESNBR 0xf4c7000f - -/*P1_DMDRESDATA7*/ -#define RSTV0910_P1_DMDRESDATA7 0xf4c8 -#define FSTV0910_P1_DMDRES_DATA7 0xf4c800ff - -/*P1_DMDRESDATA6*/ -#define RSTV0910_P1_DMDRESDATA6 0xf4c9 -#define FSTV0910_P1_DMDRES_DATA6 0xf4c900ff - -/*P1_DMDRESDATA5*/ -#define RSTV0910_P1_DMDRESDATA5 0xf4ca -#define FSTV0910_P1_DMDRES_DATA5 0xf4ca00ff - -/*P1_DMDRESDATA4*/ -#define RSTV0910_P1_DMDRESDATA4 0xf4cb -#define FSTV0910_P1_DMDRES_DATA4 0xf4cb00ff - -/*P1_DMDRESDATA3*/ -#define RSTV0910_P1_DMDRESDATA3 0xf4cc -#define FSTV0910_P1_DMDRES_DATA3 0xf4cc00ff - -/*P1_DMDRESDATA2*/ -#define RSTV0910_P1_DMDRESDATA2 0xf4cd -#define FSTV0910_P1_DMDRES_DATA2 0xf4cd00ff - -/*P1_DMDRESDATA1*/ -#define RSTV0910_P1_DMDRESDATA1 0xf4ce -#define FSTV0910_P1_DMDRES_DATA1 0xf4ce00ff - -/*P1_DMDRESDATA0*/ -#define RSTV0910_P1_DMDRESDATA0 0xf4cf -#define FSTV0910_P1_DMDRES_DATA0 0xf4cf00ff - -/*P1_FFEI1*/ -#define RSTV0910_P1_FFEI1 0xf4d0 -#define FSTV0910_P1_FFE_ACCI1 0xf4d001ff - -/*P1_FFEQ1*/ -#define RSTV0910_P1_FFEQ1 0xf4d1 -#define FSTV0910_P1_FFE_ACCQ1 0xf4d101ff - -/*P1_FFEI2*/ -#define RSTV0910_P1_FFEI2 0xf4d2 -#define FSTV0910_P1_FFE_ACCI2 0xf4d201ff - -/*P1_FFEQ2*/ -#define RSTV0910_P1_FFEQ2 0xf4d3 -#define FSTV0910_P1_FFE_ACCQ2 0xf4d301ff - -/*P1_FFEI3*/ -#define RSTV0910_P1_FFEI3 0xf4d4 -#define FSTV0910_P1_FFE_ACCI3 0xf4d401ff - -/*P1_FFEQ3*/ -#define RSTV0910_P1_FFEQ3 0xf4d5 -#define FSTV0910_P1_FFE_ACCQ3 0xf4d501ff - -/*P1_FFEI4*/ -#define RSTV0910_P1_FFEI4 0xf4d6 -#define FSTV0910_P1_FFE_ACCI4 0xf4d601ff - -/*P1_FFEQ4*/ -#define RSTV0910_P1_FFEQ4 0xf4d7 -#define FSTV0910_P1_FFE_ACCQ4 0xf4d701ff - -/*P1_FFECFG*/ -#define RSTV0910_P1_FFECFG 0xf4d8 -#define FSTV0910_P1_EQUALFFE_ON 0xf4d80040 -#define FSTV0910_P1_EQUAL_USEDSYMB 0xf4d80030 -#define FSTV0910_P1_MU_EQUALFFE 0xf4d80007 - -/*P1_TNRCFG2*/ -#define RSTV0910_P1_TNRCFG2 0xf4e1 -#define FSTV0910_P1_TUN_IQSWAP 0xf4e10080 -#define FSTV0910_P1_STB6110_STEP2MHZ 0xf4e10040 -#define FSTV0910_P1_STB6120_DBLI2C 0xf4e10020 -#define FSTV0910_P1_TUNER_WIDEBAND 0xf4e10010 -#define FSTV0910_P1_TUNER_OBSPAGE 0xf4e10008 -#define FSTV0910_P1_DIS_BWCALC 0xf4e10004 -#define FSTV0910_P1_SHORT_WAITSTATES 0xf4e10002 -#define FSTV0910_P1_DIS_2BWAGC1 0xf4e10001 - -/*P1_SMAPCOEF7*/ -#define RSTV0910_P1_SMAPCOEF7 0xf500 -#define FSTV0910_P1_DIS_QSCALE 0xf5000080 -#define FSTV0910_P1_SMAPCOEF_Q_LLR12 0xf500017f - -/*P1_SMAPCOEF6*/ -#define RSTV0910_P1_SMAPCOEF6 0xf501 -#define FSTV0910_P1_DIS_AGC2SCALE 0xf5010080 -#define FSTV0910_P1_DIS_16IQMULT 0xf5010040 -#define FSTV0910_P1_OLD_16APSK47 0xf5010020 -#define FSTV0910_P1_OLD_16APSK12 0xf5010010 -#define FSTV0910_P1_DIS_NEWSCALE 0xf5010008 -#define FSTV0910_P1_ADJ_8PSKLLR1 0xf5010004 -#define FSTV0910_P1_OLD_8PSKLLR1 0xf5010002 -#define FSTV0910_P1_DIS_AB8PSK 0xf5010001 - -/*P1_SMAPCOEF5*/ -#define RSTV0910_P1_SMAPCOEF5 0xf502 -#define FSTV0910_P1_DIS_8SCALE 0xf5020080 -#define FSTV0910_P1_SMAPCOEF_8P_LLR23 0xf502017f - -/*P1_NOSTHRES1*/ -#define RSTV0910_P1_NOSTHRES1 0xf509 -#define FSTV0910_P1_NOS_THRESHOLD1 0xf50900ff - -/*P1_NOSTHRES2*/ -#define RSTV0910_P1_NOSTHRES2 0xf50a -#define FSTV0910_P1_NOS_THRESHOLD2 0xf50a00ff - -/*P1_NOSDIFF1*/ -#define RSTV0910_P1_NOSDIFF1 0xf50b -#define FSTV0910_P1_NOSTHRES1_DIFF 0xf50b00ff - -/*P1_RAINFADE*/ -#define RSTV0910_P1_RAINFADE 0xf50c -#define FSTV0910_P1_NOSTHRES_DATAT 0xf50c0080 -#define FSTV0910_P1_RAINFADE_CNLIMIT 0xf50c0070 -#define FSTV0910_P1_RAINFADE_TIMEOUT 0xf50c0007 - -/*P1_NOSRAMCFG*/ -#define RSTV0910_P1_NOSRAMCFG 0xf50d -#define FSTV0910_P1_NOSRAM_DVBS2DATA 0xf50d0080 -#define FSTV0910_P1_NOSRAM_QUADRAT 0xf50d0040 -#define FSTV0910_P1_NOSRAM_ACTIVATION 0xf50d0030 -#define FSTV0910_P1_NOSRAM_CNRONLY 0xf50d0008 -#define FSTV0910_P1_NOSRAM_LGNCNR1 0xf50d0007 - -/*P1_NOSRAMPOS*/ -#define RSTV0910_P1_NOSRAMPOS 0xf50e -#define FSTV0910_P1_NOSRAM_LGNCNR0 0xf50e00f0 -#define FSTV0910_P1_NOSRAM_VALIDE 0xf50e0004 -#define FSTV0910_P1_NOSRAM_CNRVAL1 0xf50e0003 - -/*P1_NOSRAMVAL*/ -#define RSTV0910_P1_NOSRAMVAL 0xf50f -#define FSTV0910_P1_NOSRAM_CNRVAL0 0xf50f00ff - -/*P1_DMDPLHSTAT*/ -#define RSTV0910_P1_DMDPLHSTAT 0xf520 -#define FSTV0910_P1_PLH_STATISTIC 0xf52000ff - -/*P1_LOCKTIME3*/ -#define RSTV0910_P1_LOCKTIME3 0xf522 -#define FSTV0910_P1_DEMOD_LOCKTIME3 0xf52200ff - -/*P1_LOCKTIME2*/ -#define RSTV0910_P1_LOCKTIME2 0xf523 -#define FSTV0910_P1_DEMOD_LOCKTIME2 0xf52300ff - -/*P1_LOCKTIME1*/ -#define RSTV0910_P1_LOCKTIME1 0xf524 -#define FSTV0910_P1_DEMOD_LOCKTIME1 0xf52400ff - -/*P1_LOCKTIME0*/ -#define RSTV0910_P1_LOCKTIME0 0xf525 -#define FSTV0910_P1_DEMOD_LOCKTIME0 0xf52500ff - -/*P1_VITSCALE*/ -#define RSTV0910_P1_VITSCALE 0xf532 -#define FSTV0910_P1_NVTH_NOSRANGE 0xf5320080 -#define FSTV0910_P1_VERROR_MAXMODE 0xf5320040 -#define FSTV0910_P1_KDIV_MODE 0xf5320030 -#define FSTV0910_P1_NSLOWSN_LOCKED 0xf5320008 -#define FSTV0910_P1_DELOCK_PRFLOSS 0xf5320004 -#define FSTV0910_P1_DIS_RSFLOCK 0xf5320002 - -/*P1_FECM*/ -#define RSTV0910_P1_FECM 0xf533 -#define FSTV0910_P1_DSS_DVB 0xf5330080 -#define FSTV0910_P1_DEMOD_BYPASS 0xf5330040 -#define FSTV0910_P1_CMP_SLOWMODE 0xf5330020 -#define FSTV0910_P1_DSS_SRCH 0xf5330010 -#define FSTV0910_P1_DIFF_MODEVIT 0xf5330004 -#define FSTV0910_P1_SYNCVIT 0xf5330002 -#define FSTV0910_P1_IQINV 0xf5330001 - -/*P1_VTH12*/ -#define RSTV0910_P1_VTH12 0xf534 -#define FSTV0910_P1_VTH12 0xf53400ff - -/*P1_VTH23*/ -#define RSTV0910_P1_VTH23 0xf535 -#define FSTV0910_P1_VTH23 0xf53500ff - -/*P1_VTH34*/ -#define RSTV0910_P1_VTH34 0xf536 -#define FSTV0910_P1_VTH34 0xf53600ff - -/*P1_VTH56*/ -#define RSTV0910_P1_VTH56 0xf537 -#define FSTV0910_P1_VTH56 0xf53700ff - -/*P1_VTH67*/ -#define RSTV0910_P1_VTH67 0xf538 -#define FSTV0910_P1_VTH67 0xf53800ff - -/*P1_VTH78*/ -#define RSTV0910_P1_VTH78 0xf539 -#define FSTV0910_P1_VTH78 0xf53900ff - -/*P1_VITCURPUN*/ -#define RSTV0910_P1_VITCURPUN 0xf53a -#define FSTV0910_P1_CYCLESLIP_VIT 0xf53a0080 -#define FSTV0910_P1_VIT_ROTA180 0xf53a0040 -#define FSTV0910_P1_VIT_ROTA90 0xf53a0020 -#define FSTV0910_P1_VIT_CURPUN 0xf53a001f - -/*P1_VERROR*/ -#define RSTV0910_P1_VERROR 0xf53b -#define FSTV0910_P1_REGERR_VIT 0xf53b00ff - -/*P1_PRVIT*/ -#define RSTV0910_P1_PRVIT 0xf53c -#define FSTV0910_P1_DIS_VTHLOCK 0xf53c0040 -#define FSTV0910_P1_E7_8VIT 0xf53c0020 -#define FSTV0910_P1_E6_7VIT 0xf53c0010 -#define FSTV0910_P1_E5_6VIT 0xf53c0008 -#define FSTV0910_P1_E3_4VIT 0xf53c0004 -#define FSTV0910_P1_E2_3VIT 0xf53c0002 -#define FSTV0910_P1_E1_2VIT 0xf53c0001 - -/*P1_VAVSRVIT*/ -#define RSTV0910_P1_VAVSRVIT 0xf53d -#define FSTV0910_P1_AMVIT 0xf53d0080 -#define FSTV0910_P1_FROZENVIT 0xf53d0040 -#define FSTV0910_P1_SNVIT 0xf53d0030 -#define FSTV0910_P1_TOVVIT 0xf53d000c -#define FSTV0910_P1_HYPVIT 0xf53d0003 - -/*P1_VSTATUSVIT*/ -#define RSTV0910_P1_VSTATUSVIT 0xf53e -#define FSTV0910_P1_VITERBI_ON 0xf53e0080 -#define FSTV0910_P1_END_LOOPVIT 0xf53e0040 -#define FSTV0910_P1_VITERBI_DEPRF 0xf53e0020 -#define FSTV0910_P1_PRFVIT 0xf53e0010 -#define FSTV0910_P1_LOCKEDVIT 0xf53e0008 -#define FSTV0910_P1_VITERBI_DELOCK 0xf53e0004 -#define FSTV0910_P1_VIT_DEMODSEL 0xf53e0002 -#define FSTV0910_P1_VITERBI_COMPOUT 0xf53e0001 - -/*P1_VTHINUSE*/ -#define RSTV0910_P1_VTHINUSE 0xf53f -#define FSTV0910_P1_VIT_INUSE 0xf53f00ff - -/*P1_KDIV12*/ -#define RSTV0910_P1_KDIV12 0xf540 -#define FSTV0910_P1_KDIV12_MANUAL 0xf5400080 -#define FSTV0910_P1_K_DIVIDER_12 0xf540007f - -/*P1_KDIV23*/ -#define RSTV0910_P1_KDIV23 0xf541 -#define FSTV0910_P1_KDIV23_MANUAL 0xf5410080 -#define FSTV0910_P1_K_DIVIDER_23 0xf541007f - -/*P1_KDIV34*/ -#define RSTV0910_P1_KDIV34 0xf542 -#define FSTV0910_P1_KDIV34_MANUAL 0xf5420080 -#define FSTV0910_P1_K_DIVIDER_34 0xf542007f - -/*P1_KDIV56*/ -#define RSTV0910_P1_KDIV56 0xf543 -#define FSTV0910_P1_KDIV56_MANUAL 0xf5430080 -#define FSTV0910_P1_K_DIVIDER_56 0xf543007f - -/*P1_KDIV67*/ -#define RSTV0910_P1_KDIV67 0xf544 -#define FSTV0910_P1_KDIV67_MANUAL 0xf5440080 -#define FSTV0910_P1_K_DIVIDER_67 0xf544007f - -/*P1_KDIV78*/ -#define RSTV0910_P1_KDIV78 0xf545 -#define FSTV0910_P1_KDIV78_MANUAL 0xf5450080 -#define FSTV0910_P1_K_DIVIDER_78 0xf545007f - -/*P1_PDELCTRL0*/ -#define RSTV0910_P1_PDELCTRL0 0xf54f -#define FSTV0910_P1_ISIOBS_MODE 0xf54f0030 -#define FSTV0910_P1_PDELDIS_BITWISE 0xf54f0004 - -/*P1_PDELCTRL1*/ -#define RSTV0910_P1_PDELCTRL1 0xf550 -#define FSTV0910_P1_INV_MISMASK 0xf5500080 -#define FSTV0910_P1_FORCE_ACCEPTED 0xf5500040 -#define FSTV0910_P1_FILTER_EN 0xf5500020 -#define FSTV0910_P1_FORCE_PKTDELINUSE 0xf5500010 -#define FSTV0910_P1_HYSTEN 0xf5500008 -#define FSTV0910_P1_HYSTSWRST 0xf5500004 -#define FSTV0910_P1_EN_MIS00 0xf5500002 -#define FSTV0910_P1_ALGOSWRST 0xf5500001 - -/*P1_PDELCTRL2*/ -#define RSTV0910_P1_PDELCTRL2 0xf551 -#define FSTV0910_P1_FORCE_CONTINUOUS 0xf5510080 -#define FSTV0910_P1_RESET_UPKO_COUNT 0xf5510040 -#define FSTV0910_P1_USER_PKTDELIN_NB 0xf5510020 -#define FSTV0910_P1_DATA_UNBBSCRAMBLED 0xf5510008 -#define FSTV0910_P1_FORCE_LONGPKT 0xf5510004 -#define FSTV0910_P1_FRAME_MODE 0xf5510002 - -/*P1_HYSTTHRESH*/ -#define RSTV0910_P1_HYSTTHRESH 0xf554 -#define FSTV0910_P1_DELIN_LOCKTHRES 0xf55400f0 -#define FSTV0910_P1_DELIN_UNLOCKTHRES 0xf554000f - -/*P1_ISIENTRY*/ -#define RSTV0910_P1_ISIENTRY 0xf55e -#define FSTV0910_P1_ISI_ENTRY 0xf55e00ff - -/*P1_ISIBITENA*/ -#define RSTV0910_P1_ISIBITENA 0xf55f -#define FSTV0910_P1_ISI_BIT_EN 0xf55f00ff - -/*P1_MATSTR1*/ -#define RSTV0910_P1_MATSTR1 0xf560 -#define FSTV0910_P1_MATYPE_CURRENT1 0xf56000ff - -/*P1_MATSTR0*/ -#define RSTV0910_P1_MATSTR0 0xf561 -#define FSTV0910_P1_MATYPE_CURRENT0 0xf56100ff - -/*P1_UPLSTR1*/ -#define RSTV0910_P1_UPLSTR1 0xf562 -#define FSTV0910_P1_UPL_CURRENT1 0xf56200ff - -/*P1_UPLSTR0*/ -#define RSTV0910_P1_UPLSTR0 0xf563 -#define FSTV0910_P1_UPL_CURRENT0 0xf56300ff - -/*P1_DFLSTR1*/ -#define RSTV0910_P1_DFLSTR1 0xf564 -#define FSTV0910_P1_DFL_CURRENT1 0xf56400ff - -/*P1_DFLSTR0*/ -#define RSTV0910_P1_DFLSTR0 0xf565 -#define FSTV0910_P1_DFL_CURRENT0 0xf56500ff - -/*P1_SYNCSTR*/ -#define RSTV0910_P1_SYNCSTR 0xf566 -#define FSTV0910_P1_SYNC_CURRENT 0xf56600ff - -/*P1_SYNCDSTR1*/ -#define RSTV0910_P1_SYNCDSTR1 0xf567 -#define FSTV0910_P1_SYNCD_CURRENT1 0xf56700ff - -/*P1_SYNCDSTR0*/ -#define RSTV0910_P1_SYNCDSTR0 0xf568 -#define FSTV0910_P1_SYNCD_CURRENT0 0xf56800ff - -/*P1_PDELSTATUS1*/ -#define RSTV0910_P1_PDELSTATUS1 0xf569 -#define FSTV0910_P1_PKTDELIN_DELOCK 0xf5690080 -#define FSTV0910_P1_SYNCDUPDFL_BADDFL 0xf5690040 -#define FSTV0910_P1_CONTINUOUS_STREAM 0xf5690020 -#define FSTV0910_P1_UNACCEPTED_STREAM 0xf5690010 -#define FSTV0910_P1_BCH_ERROR_FLAG 0xf5690008 -#define FSTV0910_P1_BBHCRCKO 0xf5690004 -#define FSTV0910_P1_PKTDELIN_LOCK 0xf5690002 -#define FSTV0910_P1_FIRST_LOCK 0xf5690001 - -/*P1_PDELSTATUS2*/ -#define RSTV0910_P1_PDELSTATUS2 0xf56a -#define FSTV0910_P1_PKTDEL_DEMODSEL 0xf56a0080 -#define FSTV0910_P1_FRAME_MODCOD 0xf56a007c -#define FSTV0910_P1_FRAME_TYPE 0xf56a0003 - -/*P1_BBFCRCKO1*/ -#define RSTV0910_P1_BBFCRCKO1 0xf56b -#define FSTV0910_P1_BBHCRC_KOCNT1 0xf56b00ff - -/*P1_BBFCRCKO0*/ -#define RSTV0910_P1_BBFCRCKO0 0xf56c -#define FSTV0910_P1_BBHCRC_KOCNT0 0xf56c00ff - -/*P1_UPCRCKO1*/ -#define RSTV0910_P1_UPCRCKO1 0xf56d -#define FSTV0910_P1_PKTCRC_KOCNT1 0xf56d00ff - -/*P1_UPCRCKO0*/ -#define RSTV0910_P1_UPCRCKO0 0xf56e -#define FSTV0910_P1_PKTCRC_KOCNT0 0xf56e00ff - -/*P1_PDELCTRL3*/ -#define RSTV0910_P1_PDELCTRL3 0xf56f -#define FSTV0910_P1_PKTDEL_CONTFAIL 0xf56f0080 -#define FSTV0910_P1_PKTDEL_ENLONGPKT 0xf56f0040 -#define FSTV0910_P1_NOFIFO_BCHERR 0xf56f0020 -#define FSTV0910_P1_PKTDELIN_DELACMERR 0xf56f0010 -#define FSTV0910_P1_SATURATE_BBPKTKO 0xf56f0004 -#define FSTV0910_P1_PKTDEL_BCHERRCONT 0xf56f0002 -#define FSTV0910_P1_ETHERNET_DISFCS 0xf56f0001 - -/*P1_TSSTATEM*/ -#define RSTV0910_P1_TSSTATEM 0xf570 -#define FSTV0910_P1_TSDIL_ON 0xf5700080 -#define FSTV0910_P1_TSSKIPRS_ON 0xf5700040 -#define FSTV0910_P1_TSRS_ON 0xf5700020 -#define FSTV0910_P1_TSDESCRAMB_ON 0xf5700010 -#define FSTV0910_P1_TSFRAME_MODE 0xf5700008 -#define FSTV0910_P1_TS_DISABLE 0xf5700004 -#define FSTV0910_P1_TSACM_MODE 0xf5700002 -#define FSTV0910_P1_TSOUT_NOSYNC 0xf5700001 - -/*P1_TSCFGH*/ -#define RSTV0910_P1_TSCFGH 0xf572 -#define FSTV0910_P1_TSFIFO_DVBCI 0xf5720080 -#define FSTV0910_P1_TSFIFO_SERIAL 0xf5720040 -#define FSTV0910_P1_TSFIFO_TEIUPDATE 0xf5720020 -#define FSTV0910_P1_TSFIFO_DUTY50 0xf5720010 -#define FSTV0910_P1_TSFIFO_HSGNLOUT 0xf5720008 -#define FSTV0910_P1_TSFIFO_ERRMODE 0xf5720006 -#define FSTV0910_P1_RST_HWARE 0xf5720001 - -/*P1_TSCFGM*/ -#define RSTV0910_P1_TSCFGM 0xf573 -#define FSTV0910_P1_TSFIFO_MANSPEED 0xf57300c0 -#define FSTV0910_P1_TSFIFO_PERMDATA 0xf5730020 -#define FSTV0910_P1_TSFIFO_NONEWSGNL 0xf5730010 -#define FSTV0910_P1_NPD_SPECDVBS2 0xf5730004 -#define FSTV0910_P1_TSFIFO_DPUNACTIVE 0xf5730002 -#define FSTV0910_P1_TSFIFO_INVDATA 0xf5730001 - -/*P1_TSCFGL*/ -#define RSTV0910_P1_TSCFGL 0xf574 -#define FSTV0910_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 -#define FSTV0910_P1_BCHERROR_MODE 0xf5740030 -#define FSTV0910_P1_TSFIFO_NSGNL2DATA 0xf5740008 -#define FSTV0910_P1_TSFIFO_EMBINDVB 0xf5740004 -#define FSTV0910_P1_TSFIFO_BITSPEED 0xf5740003 - -/*P1_TSINSDELH*/ -#define RSTV0910_P1_TSINSDELH 0xf576 -#define FSTV0910_P1_TSDEL_SYNCBYTE 0xf5760080 -#define FSTV0910_P1_TSDEL_XXHEADER 0xf5760040 -#define FSTV0910_P1_TSDEL_BBHEADER 0xf5760020 -#define FSTV0910_P1_TSDEL_DATAFIELD 0xf5760010 -#define FSTV0910_P1_TSINSDEL_ISCR 0xf5760008 -#define FSTV0910_P1_TSINSDEL_NPD 0xf5760004 -#define FSTV0910_P1_TSINSDEL_RSPARITY 0xf5760002 -#define FSTV0910_P1_TSINSDEL_CRC8 0xf5760001 - -/*P1_TSDIVN*/ -#define RSTV0910_P1_TSDIVN 0xf579 -#define FSTV0910_P1_TSFIFO_SPEEDMODE 0xf57900c0 -#define FSTV0910_P1_BYTE_OVERSAMPLING 0xf5790038 -#define FSTV0910_P1_TSFIFO_RISEOK 0xf5790007 - -/*P1_TSCFG4*/ -#define RSTV0910_P1_TSCFG4 0xf57a -#define FSTV0910_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0 -#define FSTV0910_P1_TSFIFO_HIERSEL 0xf57a0020 -#define FSTV0910_P1_TSFIFO_SPECTOKEN 0xf57a0010 -#define FSTV0910_P1_TSFIFO_MAXMODE 0xf57a0008 -#define FSTV0910_P1_TSFIFO_FRFORCEPKT 0xf57a0004 -#define FSTV0910_P1_EXT_FECSPYIN 0xf57a0002 -#define FSTV0910_P1_TSFIFO_DELSPEEDUP 0xf57a0001 - -/*P1_TSSPEED*/ -#define RSTV0910_P1_TSSPEED 0xf580 -#define FSTV0910_P1_TSFIFO_OUTSPEED 0xf58000ff - -/*P1_TSSTATUS*/ -#define RSTV0910_P1_TSSTATUS 0xf581 -#define FSTV0910_P1_TSFIFO_LINEOK 0xf5810080 -#define FSTV0910_P1_TSFIFO_ERROR 0xf5810040 -#define FSTV0910_P1_TSFIFO_DATA7 0xf5810020 -#define FSTV0910_P1_TSFIFO_NOSYNC 0xf5810010 -#define FSTV0910_P1_ISCR_INITIALIZED 0xf5810008 -#define FSTV0910_P1_TSREGUL_ERROR 0xf5810004 -#define FSTV0910_P1_SOFFIFO_UNREGUL 0xf5810002 -#define FSTV0910_P1_DIL_READY 0xf5810001 - -/*P1_TSSTATUS2*/ -#define RSTV0910_P1_TSSTATUS2 0xf582 -#define FSTV0910_P1_TSFIFO_DEMODSEL 0xf5820080 -#define FSTV0910_P1_TSFIFOSPEED_STORE 0xf5820040 -#define FSTV0910_P1_DILXX_RESET 0xf5820020 -#define FSTV0910_P1_TSSPEED_IMPOSSIBLE 0xf5820010 -#define FSTV0910_P1_TSFIFO_LINENOK 0xf5820008 -#define FSTV0910_P1_TSFIFO_MUXSTREAM 0xf5820004 -#define FSTV0910_P1_SCRAMBDETECT 0xf5820002 -#define FSTV0910_P1_ULDTV67_FALSELOCK 0xf5820001 - -/*P1_TSBITRATE1*/ -#define RSTV0910_P1_TSBITRATE1 0xf583 -#define FSTV0910_P1_TSFIFO_BITRATE1 0xf58300ff - -/*P1_TSBITRATE0*/ -#define RSTV0910_P1_TSBITRATE0 0xf584 -#define FSTV0910_P1_TSFIFO_BITRATE0 0xf58400ff - -/*P1_ERRCTRL1*/ -#define RSTV0910_P1_ERRCTRL1 0xf598 -#define FSTV0910_P1_ERR_SOURCE1 0xf59800f0 -#define FSTV0910_P1_NUM_EVENT1 0xf5980007 - -/*P1_ERRCNT12*/ -#define RSTV0910_P1_ERRCNT12 0xf599 -#define FSTV0910_P1_ERRCNT1_OLDVALUE 0xf5990080 -#define FSTV0910_P1_ERR_CNT12 0xf599007f - -/*P1_ERRCNT11*/ -#define RSTV0910_P1_ERRCNT11 0xf59a -#define FSTV0910_P1_ERR_CNT11 0xf59a00ff - -/*P1_ERRCNT10*/ -#define RSTV0910_P1_ERRCNT10 0xf59b -#define FSTV0910_P1_ERR_CNT10 0xf59b00ff - -/*P1_ERRCTRL2*/ -#define RSTV0910_P1_ERRCTRL2 0xf59c -#define FSTV0910_P1_ERR_SOURCE2 0xf59c00f0 -#define FSTV0910_P1_NUM_EVENT2 0xf59c0007 - -/*P1_ERRCNT22*/ -#define RSTV0910_P1_ERRCNT22 0xf59d -#define FSTV0910_P1_ERRCNT2_OLDVALUE 0xf59d0080 -#define FSTV0910_P1_ERR_CNT22 0xf59d007f - -/*P1_ERRCNT21*/ -#define RSTV0910_P1_ERRCNT21 0xf59e -#define FSTV0910_P1_ERR_CNT21 0xf59e00ff - -/*P1_ERRCNT20*/ -#define RSTV0910_P1_ERRCNT20 0xf59f -#define FSTV0910_P1_ERR_CNT20 0xf59f00ff - -/*P1_FECSPY*/ -#define RSTV0910_P1_FECSPY 0xf5a0 -#define FSTV0910_P1_SPY_ENABLE 0xf5a00080 -#define FSTV0910_P1_NO_SYNCBYTE 0xf5a00040 -#define FSTV0910_P1_SERIAL_MODE 0xf5a00020 -#define FSTV0910_P1_UNUSUAL_PACKET 0xf5a00010 -#define FSTV0910_P1_BERMETER_DATAMODE 0xf5a0000c -#define FSTV0910_P1_BERMETER_LMODE 0xf5a00002 -#define FSTV0910_P1_BERMETER_RESET 0xf5a00001 - -/*P1_FSPYCFG*/ -#define RSTV0910_P1_FSPYCFG 0xf5a1 -#define FSTV0910_P1_FECSPY_INPUT 0xf5a100c0 -#define FSTV0910_P1_RST_ON_ERROR 0xf5a10020 -#define FSTV0910_P1_ONE_SHOT 0xf5a10010 -#define FSTV0910_P1_I2C_MODE 0xf5a1000c -#define FSTV0910_P1_SPY_HYSTERESIS 0xf5a10003 - -/*P1_FSPYDATA*/ -#define RSTV0910_P1_FSPYDATA 0xf5a2 -#define FSTV0910_P1_SPY_STUFFING 0xf5a20080 -#define FSTV0910_P1_NOERROR_PKTJITTER 0xf5a20040 -#define FSTV0910_P1_SPY_CNULLPKT 0xf5a20020 -#define FSTV0910_P1_SPY_OUTDATA_MODE 0xf5a2001f - -/*P1_FSPYOUT*/ -#define RSTV0910_P1_FSPYOUT 0xf5a3 -#define FSTV0910_P1_FSPY_DIRECT 0xf5a30080 -#define FSTV0910_P1_SPY_OUTDATA_BUS 0xf5a30038 -#define FSTV0910_P1_STUFF_MODE 0xf5a30007 - -/*P1_FSTATUS*/ -#define RSTV0910_P1_FSTATUS 0xf5a4 -#define FSTV0910_P1_SPY_ENDSIM 0xf5a40080 -#define FSTV0910_P1_VALID_SIM 0xf5a40040 -#define FSTV0910_P1_FOUND_SIGNAL 0xf5a40020 -#define FSTV0910_P1_DSS_SYNCBYTE 0xf5a40010 -#define FSTV0910_P1_RESULT_STATE 0xf5a4000f - -/*P1_FBERCPT4*/ -#define RSTV0910_P1_FBERCPT4 0xf5a8 -#define FSTV0910_P1_FBERMETER_CPT4 0xf5a800ff - -/*P1_FBERCPT3*/ -#define RSTV0910_P1_FBERCPT3 0xf5a9 -#define FSTV0910_P1_FBERMETER_CPT3 0xf5a900ff - -/*P1_FBERCPT2*/ -#define RSTV0910_P1_FBERCPT2 0xf5aa -#define FSTV0910_P1_FBERMETER_CPT2 0xf5aa00ff - -/*P1_FBERCPT1*/ -#define RSTV0910_P1_FBERCPT1 0xf5ab -#define FSTV0910_P1_FBERMETER_CPT1 0xf5ab00ff - -/*P1_FBERCPT0*/ -#define RSTV0910_P1_FBERCPT0 0xf5ac -#define FSTV0910_P1_FBERMETER_CPT0 0xf5ac00ff - -/*P1_FBERERR2*/ -#define RSTV0910_P1_FBERERR2 0xf5ad -#define FSTV0910_P1_FBERMETER_ERR2 0xf5ad00ff - -/*P1_FBERERR1*/ -#define RSTV0910_P1_FBERERR1 0xf5ae -#define FSTV0910_P1_FBERMETER_ERR1 0xf5ae00ff - -/*P1_FBERERR0*/ -#define RSTV0910_P1_FBERERR0 0xf5af -#define FSTV0910_P1_FBERMETER_ERR0 0xf5af00ff - -/*P1_FSPYBER*/ -#define RSTV0910_P1_FSPYBER 0xf5b2 -#define FSTV0910_P1_FSPYOBS_XORREAD 0xf5b20040 -#define FSTV0910_P1_FSPYBER_OBSMODE 0xf5b20020 -#define FSTV0910_P1_FSPYBER_SYNCBYTE 0xf5b20010 -#define FSTV0910_P1_FSPYBER_UNSYNC 0xf5b20008 -#define FSTV0910_P1_FSPYBER_CTIME 0xf5b20007 - -/*P1_SFERROR*/ -#define RSTV0910_P1_SFERROR 0xf5c1 -#define FSTV0910_P1_SFEC_REGERR_VIT 0xf5c100ff - -/*P1_SFECSTATUS*/ -#define RSTV0910_P1_SFECSTATUS 0xf5c3 -#define FSTV0910_P1_SFEC_ON 0xf5c30080 -#define FSTV0910_P1_SFEC_OFF 0xf5c30040 -#define FSTV0910_P1_LOCKEDSFEC 0xf5c30008 -#define FSTV0910_P1_SFEC_DELOCK 0xf5c30004 -#define FSTV0910_P1_SFEC_DEMODSEL 0xf5c30002 -#define FSTV0910_P1_SFEC_OVFON 0xf5c30001 - -/*P1_SFKDIV12*/ -#define RSTV0910_P1_SFKDIV12 0xf5c4 -#define FSTV0910_P1_SFECKDIV12_MAN 0xf5c40080 -#define FSTV0910_P1_SFEC_K_DIVIDER_12 0xf5c4007f - -/*P1_SFKDIV23*/ -#define RSTV0910_P1_SFKDIV23 0xf5c5 -#define FSTV0910_P1_SFECKDIV23_MAN 0xf5c50080 -#define FSTV0910_P1_SFEC_K_DIVIDER_23 0xf5c5007f - -/*P1_SFKDIV34*/ -#define RSTV0910_P1_SFKDIV34 0xf5c6 -#define FSTV0910_P1_SFECKDIV34_MAN 0xf5c60080 -#define FSTV0910_P1_SFEC_K_DIVIDER_34 0xf5c6007f - -/*P1_SFKDIV56*/ -#define RSTV0910_P1_SFKDIV56 0xf5c7 -#define FSTV0910_P1_SFECKDIV56_MAN 0xf5c70080 -#define FSTV0910_P1_SFEC_K_DIVIDER_56 0xf5c7007f - -/*P1_SFKDIV67*/ -#define RSTV0910_P1_SFKDIV67 0xf5c8 -#define FSTV0910_P1_SFECKDIV67_MAN 0xf5c80080 -#define FSTV0910_P1_SFEC_K_DIVIDER_67 0xf5c8007f - -/*P1_SFKDIV78*/ -#define RSTV0910_P1_SFKDIV78 0xf5c9 -#define FSTV0910_P1_SFECKDIV78_MAN 0xf5c90080 -#define FSTV0910_P1_SFEC_K_DIVIDER_78 0xf5c9007f - -/*P1_SFSTATUS*/ -#define RSTV0910_P1_SFSTATUS 0xf5cc -#define FSTV0910_P1_SFEC_LINEOK 0xf5cc0080 -#define FSTV0910_P1_SFEC_ERROR 0xf5cc0040 -#define FSTV0910_P1_SFEC_DATA7 0xf5cc0020 -#define FSTV0910_P1_SFEC_PKTDNBRFAIL 0xf5cc0010 -#define FSTV0910_P1_TSSFEC_DEMODSEL 0xf5cc0008 -#define FSTV0910_P1_SFEC_NOSYNC 0xf5cc0004 -#define FSTV0910_P1_SFEC_UNREGULA 0xf5cc0002 -#define FSTV0910_P1_SFEC_READY 0xf5cc0001 - -/*P1_SFDLYSET2*/ -#define RSTV0910_P1_SFDLYSET2 0xf5d0 -#define FSTV0910_P1_SFEC_OFFSET 0xf5d000c0 -#define FSTV0910_P1_RST_SFEC 0xf5d00008 -#define FSTV0910_P1_DILDLINE_ERROR 0xf5d00004 -#define FSTV0910_P1_SFEC_DISABLE 0xf5d00002 -#define FSTV0910_P1_SFEC_UNREGUL 0xf5d00001 - -/*P1_SFERRCTRL*/ -#define RSTV0910_P1_SFERRCTRL 0xf5d8 -#define FSTV0910_P1_SFEC_ERR_SOURCE 0xf5d800f0 -#define FSTV0910_P1_SFEC_NUM_EVENT 0xf5d80007 - -/*P1_SFERRCNT2*/ -#define RSTV0910_P1_SFERRCNT2 0xf5d9 -#define FSTV0910_P1_SFERRC_OLDVALUE 0xf5d90080 -#define FSTV0910_P1_SFEC_ERR_CNT2 0xf5d9007f - -/*P1_SFERRCNT1*/ -#define RSTV0910_P1_SFERRCNT1 0xf5da -#define FSTV0910_P1_SFEC_ERR_CNT1 0xf5da00ff - -/*P1_SFERRCNT0*/ -#define RSTV0910_P1_SFERRCNT0 0xf5db -#define FSTV0910_P1_SFEC_ERR_CNT0 0xf5db00ff - -/*TSGENERAL*/ -#define RSTV0910_TSGENERAL 0xf630 -#define FSTV0910_EN_LGNERROR 0xf6300080 -#define FSTV0910_TSFIFO_DISTS2PAR 0xf6300040 -#define FSTV0910_MUXSTREAM_COMPMOSE 0xf6300030 -#define FSTV0910_MUXSTREAM_OUTMODE 0xf6300008 -#define FSTV0910_TSFIFO_PERMPARAL 0xf6300006 -#define FSTV0910_RST_REEDSOLO 0xf6300001 - -/*P1_DISIRQCFG*/ -#define RSTV0910_P1_DISIRQCFG 0xf700 -#define FSTV0910_P1_ENRXEND 0xf7000040 -#define FSTV0910_P1_ENRXFIFO8B 0xf7000020 -#define FSTV0910_P1_ENTRFINISH 0xf7000010 -#define FSTV0910_P1_ENTIMEOUT 0xf7000008 -#define FSTV0910_P1_ENTXEND 0xf7000004 -#define FSTV0910_P1_ENTXFIFO64B 0xf7000002 -#define FSTV0910_P1_ENGAPBURST 0xf7000001 - -/*P1_DISIRQSTAT*/ -#define RSTV0910_P1_DISIRQSTAT 0xf701 -#define FSTV0910_P1_IRQRXEND 0xf7010040 -#define FSTV0910_P1_IRQRXFIFO8B 0xf7010020 -#define FSTV0910_P1_IRQTRFINISH 0xf7010010 -#define FSTV0910_P1_IRQTIMEOUT 0xf7010008 -#define FSTV0910_P1_IRQTXEND 0xf7010004 -#define FSTV0910_P1_IRQTXFIFO64B 0xf7010002 -#define FSTV0910_P1_IRQGAPBURST 0xf7010001 - -/*P1_DISTXCFG*/ -#define RSTV0910_P1_DISTXCFG 0xf702 -#define FSTV0910_P1_DISTX_RESET 0xf7020080 -#define FSTV0910_P1_TIM_OFF 0xf7020040 -#define FSTV0910_P1_TIM_CMD 0xf7020030 -#define FSTV0910_P1_ENVELOP 0xf7020008 -#define FSTV0910_P1_DIS_PRECHARGE 0xf7020004 -#define FSTV0910_P1_DISEQC_MODE 0xf7020003 - -/*P1_DISTXSTATUS*/ -#define RSTV0910_P1_DISTXSTATUS 0xf703 -#define FSTV0910_P1_TX_FIFO_FULL 0xf7030040 -#define FSTV0910_P1_TX_IDLE 0xf7030020 -#define FSTV0910_P1_GAP_BURST 0xf7030010 -#define FSTV0910_P1_TX_FIFO64B 0xf7030008 -#define FSTV0910_P1_TX_END 0xf7030004 -#define FSTV0910_P1_TR_TIMEOUT 0xf7030002 -#define FSTV0910_P1_TR_FINISH 0xf7030001 - -/*P1_DISTXBYTES*/ -#define RSTV0910_P1_DISTXBYTES 0xf704 -#define FSTV0910_P1_TXFIFO_BYTES 0xf70400ff - -/*P1_DISTXFIFO*/ -#define RSTV0910_P1_DISTXFIFO 0xf705 -#define FSTV0910_P1_DISEQC_TX_FIFO 0xf70500ff - -/*P1_DISTXF22*/ -#define RSTV0910_P1_DISTXF22 0xf706 -#define FSTV0910_P1_F22TX 0xf70600ff - -/*P1_DISTIMEOCFG*/ -#define RSTV0910_P1_DISTIMEOCFG 0xf708 -#define FSTV0910_P1_RXCHOICE 0xf7080006 -#define FSTV0910_P1_TIMEOUT_OFF 0xf7080001 - -/*P1_DISTIMEOUT*/ -#define RSTV0910_P1_DISTIMEOUT 0xf709 -#define FSTV0910_P1_TIMEOUT_COUNT 0xf70900ff - -/*P1_DISRXCFG*/ -#define RSTV0910_P1_DISRXCFG 0xf70a -#define FSTV0910_P1_DISRX_RESET 0xf70a0080 -#define FSTV0910_P1_EXTENVELOP 0xf70a0040 -#define FSTV0910_P1_PINSELECT 0xf70a0038 -#define FSTV0910_P1_IGNORE_SHORT22K 0xf70a0004 -#define FSTV0910_P1_SIGNED_RXIN 0xf70a0002 -#define FSTV0910_P1_DISRX_ON 0xf70a0001 - -/*P1_DISRXSTAT1*/ -#define RSTV0910_P1_DISRXSTAT1 0xf70b -#define FSTV0910_P1_RXEND 0xf70b0080 -#define FSTV0910_P1_RXACTIVE 0xf70b0040 -#define FSTV0910_P1_RXDETECT 0xf70b0020 -#define FSTV0910_P1_CONTTONE 0xf70b0010 -#define FSTV0910_P1_8BFIFOREADY 0xf70b0008 -#define FSTV0910_P1_FIFOEMPTY 0xf70b0004 - -/*P1_DISRXSTAT0*/ -#define RSTV0910_P1_DISRXSTAT0 0xf70c -#define FSTV0910_P1_RXFAIL 0xf70c0080 -#define FSTV0910_P1_FIFOPFAIL 0xf70c0040 -#define FSTV0910_P1_RXNONBYTE 0xf70c0020 -#define FSTV0910_P1_FIFOOVF 0xf70c0010 -#define FSTV0910_P1_SHORT22K 0xf70c0008 -#define FSTV0910_P1_RXMSGLOST 0xf70c0004 - -/*P1_DISRXBYTES*/ -#define RSTV0910_P1_DISRXBYTES 0xf70d -#define FSTV0910_P1_RXFIFO_BYTES 0xf70d001f - -/*P1_DISRXPARITY1*/ -#define RSTV0910_P1_DISRXPARITY1 0xf70e -#define FSTV0910_P1_DISRX_PARITY1 0xf70e00ff - -/*P1_DISRXPARITY0*/ -#define RSTV0910_P1_DISRXPARITY0 0xf70f -#define FSTV0910_P1_DISRX_PARITY0 0xf70f00ff - -/*P1_DISRXFIFO*/ -#define RSTV0910_P1_DISRXFIFO 0xf710 -#define FSTV0910_P1_DISEQC_RX_FIFO 0xf71000ff - -/*P1_DISRXDC1*/ -#define RSTV0910_P1_DISRXDC1 0xf711 -#define FSTV0910_P1_DC_VALUE1 0xf7110103 - -/*P1_DISRXDC0*/ -#define RSTV0910_P1_DISRXDC0 0xf712 -#define FSTV0910_P1_DC_VALUE0 0xf71200ff - -/*P1_DISRXF221*/ -#define RSTV0910_P1_DISRXF221 0xf714 -#define FSTV0910_P1_F22RX1 0xf714000f - -/*P1_DISRXF220*/ -#define RSTV0910_P1_DISRXF220 0xf715 -#define FSTV0910_P1_F22RX0 0xf71500ff - -/*P1_DISRXF100*/ -#define RSTV0910_P1_DISRXF100 0xf716 -#define FSTV0910_P1_F100RX 0xf71600ff - -/*P1_DISRXSHORT22K*/ -#define RSTV0910_P1_DISRXSHORT22K 0xf71c -#define FSTV0910_P1_SHORT22K_LENGTH 0xf71c001f - -/*P1_ACRPRESC*/ -#define RSTV0910_P1_ACRPRESC 0xf71e -#define FSTV0910_P1_ACR_CODFRDY 0xf71e0008 -#define FSTV0910_P1_ACR_PRESC 0xf71e0007 - -/*P1_ACRDIV*/ -#define RSTV0910_P1_ACRDIV 0xf71f -#define FSTV0910_P1_ACR_DIV 0xf71f00ff - -/*P2_DISIRQCFG*/ -#define RSTV0910_P2_DISIRQCFG 0xf740 -#define FSTV0910_P2_ENRXEND 0xf7400040 -#define FSTV0910_P2_ENRXFIFO8B 0xf7400020 -#define FSTV0910_P2_ENTRFINISH 0xf7400010 -#define FSTV0910_P2_ENTIMEOUT 0xf7400008 -#define FSTV0910_P2_ENTXEND 0xf7400004 -#define FSTV0910_P2_ENTXFIFO64B 0xf7400002 -#define FSTV0910_P2_ENGAPBURST 0xf7400001 - -/*P2_DISIRQSTAT*/ -#define RSTV0910_P2_DISIRQSTAT 0xf741 -#define FSTV0910_P2_IRQRXEND 0xf7410040 -#define FSTV0910_P2_IRQRXFIFO8B 0xf7410020 -#define FSTV0910_P2_IRQTRFINISH 0xf7410010 -#define FSTV0910_P2_IRQTIMEOUT 0xf7410008 -#define FSTV0910_P2_IRQTXEND 0xf7410004 -#define FSTV0910_P2_IRQTXFIFO64B 0xf7410002 -#define FSTV0910_P2_IRQGAPBURST 0xf7410001 - -/*P2_DISTXCFG*/ -#define RSTV0910_P2_DISTXCFG 0xf742 -#define FSTV0910_P2_DISTX_RESET 0xf7420080 -#define FSTV0910_P2_TIM_OFF 0xf7420040 -#define FSTV0910_P2_TIM_CMD 0xf7420030 -#define FSTV0910_P2_ENVELOP 0xf7420008 -#define FSTV0910_P2_DIS_PRECHARGE 0xf7420004 -#define FSTV0910_P2_DISEQC_MODE 0xf7420003 - -/*P2_DISTXSTATUS*/ -#define RSTV0910_P2_DISTXSTATUS 0xf743 -#define FSTV0910_P2_TX_FIFO_FULL 0xf7430040 -#define FSTV0910_P2_TX_IDLE 0xf7430020 -#define FSTV0910_P2_GAP_BURST 0xf7430010 -#define FSTV0910_P2_TX_FIFO64B 0xf7430008 -#define FSTV0910_P2_TX_END 0xf7430004 -#define FSTV0910_P2_TR_TIMEOUT 0xf7430002 -#define FSTV0910_P2_TR_FINISH 0xf7430001 - -/*P2_DISTXBYTES*/ -#define RSTV0910_P2_DISTXBYTES 0xf744 -#define FSTV0910_P2_TXFIFO_BYTES 0xf74400ff - -/*P2_DISTXFIFO*/ -#define RSTV0910_P2_DISTXFIFO 0xf745 -#define FSTV0910_P2_DISEQC_TX_FIFO 0xf74500ff - -/*P2_DISTXF22*/ -#define RSTV0910_P2_DISTXF22 0xf746 -#define FSTV0910_P2_F22TX 0xf74600ff - -/*P2_DISTIMEOCFG*/ -#define RSTV0910_P2_DISTIMEOCFG 0xf748 -#define FSTV0910_P2_RXCHOICE 0xf7480006 -#define FSTV0910_P2_TIMEOUT_OFF 0xf7480001 - -/*P2_DISTIMEOUT*/ -#define RSTV0910_P2_DISTIMEOUT 0xf749 -#define FSTV0910_P2_TIMEOUT_COUNT 0xf74900ff - -/*P2_DISRXCFG*/ -#define RSTV0910_P2_DISRXCFG 0xf74a -#define FSTV0910_P2_DISRX_RESET 0xf74a0080 -#define FSTV0910_P2_EXTENVELOP 0xf74a0040 -#define FSTV0910_P2_PINSELECT 0xf74a0038 -#define FSTV0910_P2_IGNORE_SHORT22K 0xf74a0004 -#define FSTV0910_P2_SIGNED_RXIN 0xf74a0002 -#define FSTV0910_P2_DISRX_ON 0xf74a0001 - -/*P2_DISRXSTAT1*/ -#define RSTV0910_P2_DISRXSTAT1 0xf74b -#define FSTV0910_P2_RXEND 0xf74b0080 -#define FSTV0910_P2_RXACTIVE 0xf74b0040 -#define FSTV0910_P2_RXDETECT 0xf74b0020 -#define FSTV0910_P2_CONTTONE 0xf74b0010 -#define FSTV0910_P2_8BFIFOREADY 0xf74b0008 -#define FSTV0910_P2_FIFOEMPTY 0xf74b0004 - -/*P2_DISRXSTAT0*/ -#define RSTV0910_P2_DISRXSTAT0 0xf74c -#define FSTV0910_P2_RXFAIL 0xf74c0080 -#define FSTV0910_P2_FIFOPFAIL 0xf74c0040 -#define FSTV0910_P2_RXNONBYTE 0xf74c0020 -#define FSTV0910_P2_FIFOOVF 0xf74c0010 -#define FSTV0910_P2_SHORT22K 0xf74c0008 -#define FSTV0910_P2_RXMSGLOST 0xf74c0004 - -/*P2_DISRXBYTES*/ -#define RSTV0910_P2_DISRXBYTES 0xf74d -#define FSTV0910_P2_RXFIFO_BYTES 0xf74d001f - -/*P2_DISRXPARITY1*/ -#define RSTV0910_P2_DISRXPARITY1 0xf74e -#define FSTV0910_P2_DISRX_PARITY1 0xf74e00ff - -/*P2_DISRXPARITY0*/ -#define RSTV0910_P2_DISRXPARITY0 0xf74f -#define FSTV0910_P2_DISRX_PARITY0 0xf74f00ff - -/*P2_DISRXFIFO*/ -#define RSTV0910_P2_DISRXFIFO 0xf750 -#define FSTV0910_P2_DISEQC_RX_FIFO 0xf75000ff - -/*P2_DISRXDC1*/ -#define RSTV0910_P2_DISRXDC1 0xf751 -#define FSTV0910_P2_DC_VALUE1 0xf7510103 - -/*P2_DISRXDC0*/ -#define RSTV0910_P2_DISRXDC0 0xf752 -#define FSTV0910_P2_DC_VALUE0 0xf75200ff - -/*P2_DISRXF221*/ -#define RSTV0910_P2_DISRXF221 0xf754 -#define FSTV0910_P2_F22RX1 0xf754000f - -/*P2_DISRXF220*/ -#define RSTV0910_P2_DISRXF220 0xf755 -#define FSTV0910_P2_F22RX0 0xf75500ff - -/*P2_DISRXF100*/ -#define RSTV0910_P2_DISRXF100 0xf756 -#define FSTV0910_P2_F100RX 0xf75600ff - -/*P2_DISRXSHORT22K*/ -#define RSTV0910_P2_DISRXSHORT22K 0xf75c -#define FSTV0910_P2_SHORT22K_LENGTH 0xf75c001f - -/*P2_ACRPRESC*/ -#define RSTV0910_P2_ACRPRESC 0xf75e -#define FSTV0910_P2_ACR_CODFRDY 0xf75e0008 -#define FSTV0910_P2_ACR_PRESC 0xf75e0007 - -/*P2_ACRDIV*/ -#define RSTV0910_P2_ACRDIV 0xf75f -#define FSTV0910_P2_ACR_DIV 0xf75f00ff - -/*P1_NBITER_NF4*/ -#define RSTV0910_P1_NBITER_NF4 0xfa03 -#define FSTV0910_P1_NBITER_NF_QPSK_1_2 0xfa0300ff - -/*P1_NBITER_NF5*/ -#define RSTV0910_P1_NBITER_NF5 0xfa04 -#define FSTV0910_P1_NBITER_NF_QPSK_3_5 0xfa0400ff - -/*P1_NBITER_NF6*/ -#define RSTV0910_P1_NBITER_NF6 0xfa05 -#define FSTV0910_P1_NBITER_NF_QPSK_2_3 0xfa0500ff - -/*P1_NBITER_NF7*/ -#define RSTV0910_P1_NBITER_NF7 0xfa06 -#define FSTV0910_P1_NBITER_NF_QPSK_3_4 0xfa0600ff - -/*P1_NBITER_NF8*/ -#define RSTV0910_P1_NBITER_NF8 0xfa07 -#define FSTV0910_P1_NBITER_NF_QPSK_4_5 0xfa0700ff - -/*P1_NBITER_NF9*/ -#define RSTV0910_P1_NBITER_NF9 0xfa08 -#define FSTV0910_P1_NBITER_NF_QPSK_5_6 0xfa0800ff - -/*P1_NBITER_NF10*/ -#define RSTV0910_P1_NBITER_NF10 0xfa09 -#define FSTV0910_P1_NBITER_NF_QPSK_8_9 0xfa0900ff - -/*P1_NBITER_NF11*/ -#define RSTV0910_P1_NBITER_NF11 0xfa0a -#define FSTV0910_P1_NBITER_NF_QPSK_9_10 0xfa0a00ff - -/*P1_NBITER_NF12*/ -#define RSTV0910_P1_NBITER_NF12 0xfa0b -#define FSTV0910_P1_NBITER_NF_8PSK_3_5 0xfa0b00ff - -/*P1_NBITER_NF13*/ -#define RSTV0910_P1_NBITER_NF13 0xfa0c -#define FSTV0910_P1_NBITER_NF_8PSK_2_3 0xfa0c00ff - -/*P1_NBITER_NF14*/ -#define RSTV0910_P1_NBITER_NF14 0xfa0d -#define FSTV0910_P1_NBITER_NF_8PSK_3_4 0xfa0d00ff - -/*P1_NBITER_NF15*/ -#define RSTV0910_P1_NBITER_NF15 0xfa0e -#define FSTV0910_P1_NBITER_NF_8PSK_5_6 0xfa0e00ff - -/*P1_NBITER_NF16*/ -#define RSTV0910_P1_NBITER_NF16 0xfa0f -#define FSTV0910_P1_NBITER_NF_8PSK_8_9 0xfa0f00ff - -/*P1_NBITER_NF17*/ -#define RSTV0910_P1_NBITER_NF17 0xfa10 -#define FSTV0910_P1_NBITER_NF_8PSK_9_10 0xfa1000ff - -/*GAINLLR_NF4*/ -#define RSTV0910_GAINLLR_NF4 0xfa43 -#define FSTV0910_GAINLLR_NF_QPSK_1_2 0xfa43007f - -/*GAINLLR_NF5*/ -#define RSTV0910_GAINLLR_NF5 0xfa44 -#define FSTV0910_GAINLLR_NF_QPSK_3_5 0xfa44007f - -/*GAINLLR_NF6*/ -#define RSTV0910_GAINLLR_NF6 0xfa45 -#define FSTV0910_GAINLLR_NF_QPSK_2_3 0xfa45007f - -/*GAINLLR_NF7*/ -#define RSTV0910_GAINLLR_NF7 0xfa46 -#define FSTV0910_GAINLLR_NF_QPSK_3_4 0xfa46007f - -/*GAINLLR_NF8*/ -#define RSTV0910_GAINLLR_NF8 0xfa47 -#define FSTV0910_GAINLLR_NF_QPSK_4_5 0xfa47007f - -/*GAINLLR_NF9*/ -#define RSTV0910_GAINLLR_NF9 0xfa48 -#define FSTV0910_GAINLLR_NF_QPSK_5_6 0xfa48007f - -/*GAINLLR_NF10*/ -#define RSTV0910_GAINLLR_NF10 0xfa49 -#define FSTV0910_GAINLLR_NF_QPSK_8_9 0xfa49007f - -/*GAINLLR_NF11*/ -#define RSTV0910_GAINLLR_NF11 0xfa4a -#define FSTV0910_GAINLLR_NF_QPSK_9_10 0xfa4a007f - -/*GAINLLR_NF12*/ -#define RSTV0910_GAINLLR_NF12 0xfa4b -#define FSTV0910_GAINLLR_NF_8PSK_3_5 0xfa4b007f - -/*GAINLLR_NF13*/ -#define RSTV0910_GAINLLR_NF13 0xfa4c -#define FSTV0910_GAINLLR_NF_8PSK_2_3 0xfa4c007f - -/*GAINLLR_NF14*/ -#define RSTV0910_GAINLLR_NF14 0xfa4d -#define FSTV0910_GAINLLR_NF_8PSK_3_4 0xfa4d007f - -/*GAINLLR_NF15*/ -#define RSTV0910_GAINLLR_NF15 0xfa4e -#define FSTV0910_GAINLLR_NF_8PSK_5_6 0xfa4e007f - -/*GAINLLR_NF16*/ -#define RSTV0910_GAINLLR_NF16 0xfa4f -#define FSTV0910_GAINLLR_NF_8PSK_8_9 0xfa4f007f - -/*GAINLLR_NF17*/ -#define RSTV0910_GAINLLR_NF17 0xfa50 -#define FSTV0910_GAINLLR_NF_8PSK_9_10 0xfa50007f - -/*CFGEXT*/ -#define RSTV0910_CFGEXT 0xfa80 -#define FSTV0910_BYPFIFOBCH 0xfa800080 -#define FSTV0910_BYPBCH 0xfa800040 -#define FSTV0910_BYPLDPC 0xfa800020 -#define FSTV0910_BYPFIFOBCHF 0xfa800010 -#define FSTV0910_INVLLRSIGN 0xfa800008 -#define FSTV0910_SHORTMULT 0xfa800004 -#define FSTV0910_ENSTOPDEC 0xfa800002 - -/*GENCFG*/ -#define RSTV0910_GENCFG 0xfa86 -#define FSTV0910_LEG_ITER 0xfa860040 -#define FSTV0910_NOSHFRD1 0xfa860020 -#define FSTV0910_BROADCAST 0xfa860010 -#define FSTV0910_NOSHFRD2 0xfa860008 -#define FSTV0910_BCHERRFLAG 0xfa860004 -#define FSTV0910_CROSSINPUT 0xfa860002 -#define FSTV0910_DDEMOD 0xfa860001 - -/*LDPCERR1*/ -#define RSTV0910_LDPCERR1 0xfa96 -#define FSTV0910_LDPC_ERRORS1 0xfa9600ff - -/*LDPCERR0*/ -#define RSTV0910_LDPCERR0 0xfa97 -#define FSTV0910_LDPC_ERRORS0 0xfa9700ff - -/*BCHERR*/ -#define RSTV0910_BCHERR 0xfa98 -#define FSTV0910_ERRORFLAG 0xfa980010 -#define FSTV0910_BCH_ERRORS_COUNTER 0xfa98000f - -/*P1_MAXEXTRAITER*/ -#define RSTV0910_P1_MAXEXTRAITER 0xfab1 -#define FSTV0910_P1_MAX_EXTRA_ITER 0xfab100ff - -/*P2_MAXEXTRAITER*/ -#define RSTV0910_P2_MAXEXTRAITER 0xfab6 -#define FSTV0910_P2_MAX_EXTRA_ITER 0xfab600ff - -/*P1_STATUSITER*/ -#define RSTV0910_P1_STATUSITER 0xfabc -#define FSTV0910_P1_STATUS_ITER 0xfabc00ff - -/*P1_STATUSMAXITER*/ -#define RSTV0910_P1_STATUSMAXITER 0xfabd -#define FSTV0910_P1_STATUS_MAX_ITER 0xfabd00ff - -/*P2_STATUSITER*/ -#define RSTV0910_P2_STATUSITER 0xfabe -#define FSTV0910_P2_STATUS_ITER 0xfabe00ff - -/*P2_STATUSMAXITER*/ -#define RSTV0910_P2_STATUSMAXITER 0xfabf -#define FSTV0910_P2_STATUS_MAX_ITER 0xfabf00ff - -/*P2_NBITER_NF4*/ -#define RSTV0910_P2_NBITER_NF4 0xfac3 -#define FSTV0910_P2_NBITER_NF_QPSK_1_2 0xfac300ff - -/*P2_NBITER_NF5*/ -#define RSTV0910_P2_NBITER_NF5 0xfac4 -#define FSTV0910_P2_NBITER_NF_QPSK_3_5 0xfac400ff - -/*P2_NBITER_NF6*/ -#define RSTV0910_P2_NBITER_NF6 0xfac5 -#define FSTV0910_P2_NBITER_NF_QPSK_2_3 0xfac500ff - -/*P2_NBITER_NF7*/ -#define RSTV0910_P2_NBITER_NF7 0xfac6 -#define FSTV0910_P2_NBITER_NF_QPSK_3_4 0xfac600ff - -/*P2_NBITER_NF8*/ -#define RSTV0910_P2_NBITER_NF8 0xfac7 -#define FSTV0910_P2_NBITER_NF_QPSK_4_5 0xfac700ff - -/*P2_NBITER_NF9*/ -#define RSTV0910_P2_NBITER_NF9 0xfac8 -#define FSTV0910_P2_NBITER_NF_QPSK_5_6 0xfac800ff - -/*P2_NBITER_NF10*/ -#define RSTV0910_P2_NBITER_NF10 0xfac9 -#define FSTV0910_P2_NBITER_NF_QPSK_8_9 0xfac900ff - -/*P2_NBITER_NF11*/ -#define RSTV0910_P2_NBITER_NF11 0xfaca -#define FSTV0910_P2_NBITER_NF_QPSK_9_10 0xfaca00ff - -/*P2_NBITER_NF12*/ -#define RSTV0910_P2_NBITER_NF12 0xfacb -#define FSTV0910_P2_NBITER_NF_8PSK_3_5 0xfacb00ff - -/*P2_NBITER_NF13*/ -#define RSTV0910_P2_NBITER_NF13 0xfacc -#define FSTV0910_P2_NBITER_NF_8PSK_2_3 0xfacc00ff - -/*P2_NBITER_NF14*/ -#define RSTV0910_P2_NBITER_NF14 0xfacd -#define FSTV0910_P2_NBITER_NF_8PSK_3_4 0xfacd00ff - -/*P2_NBITER_NF15*/ -#define RSTV0910_P2_NBITER_NF15 0xface -#define FSTV0910_P2_NBITER_NF_8PSK_5_6 0xface00ff - -/*P2_NBITER_NF16*/ -#define RSTV0910_P2_NBITER_NF16 0xfacf -#define FSTV0910_P2_NBITER_NF_8PSK_8_9 0xfacf00ff - -/*P2_NBITER_NF17*/ -#define RSTV0910_P2_NBITER_NF17 0xfad0 -#define FSTV0910_P2_NBITER_NF_8PSK_9_10 0xfad000ff - -/*TSTRES0*/ -#define RSTV0910_TSTRES0 0xff11 -#define FSTV0910_FRESFEC 0xff110080 -#define FSTV0910_FRESTS 0xff110040 -#define FSTV0910_FRESVIT1 0xff110020 -#define FSTV0910_FRESVIT2 0xff110010 -#define FSTV0910_FRESSYM1 0xff110008 -#define FSTV0910_FRESSYM2 0xff110004 -#define FSTV0910_FRESMAS 0xff110002 -#define FSTV0910_FRESINT 0xff110001 - -/*P2_TCTL4*/ -#define RSTV0910_P2_TCTL4 0xff28 -#define FSTV0910_P2_CFR2TOCFR1_DVBS1 0xff2800c0 -#define FSTV0910_P2_TSTINV_PHERR 0xff280020 -#define FSTV0910_P2_EN_PLHCALC 0xff280010 -#define FSTV0910_P2_TETA3L_RSTTETA3D 0xff280008 -#define FSTV0910_P2_DIS_FORCEBETA2 0xff280004 -#define FSTV0910_P2_CAR3_NOTRACEBACK 0xff280002 -#define FSTV0910_P2_CAR3_NOFORWARD 0xff280001 - -/*P1_TCTL4*/ -#define RSTV0910_P1_TCTL4 0xff48 -#define FSTV0910_P1_CFR2TOCFR1_DVBS1 0xff4800c0 -#define FSTV0910_P1_TSTINV_PHERR 0xff480020 -#define FSTV0910_P1_EN_PLHCALC 0xff480010 -#define FSTV0910_P1_TETA3L_RSTTETA3D 0xff480008 -#define FSTV0910_P1_DIS_FORCEBETA2 0xff480004 -#define FSTV0910_P1_CAR3_NOTRACEBACK 0xff480002 -#define FSTV0910_P1_CAR3_NOFORWARD 0xff480001 - -#define STV0910_NBREGS 735 -#define STV0910_NBFIELDS 1776 +// @DVB-S/DVB-S2 STMicroelectronics STV0900 register defintions +// Author Manfred Völkel, August 2013 +// (c) 2013 Digital Devices GmbH Germany. All rights reserved + +// $Id: DD_STV0910Register.h 504 2013-09-02 23:02:14Z manfred $ + +/* ======================================================================= +-- Registers Declaration (Internal ST, All Applications ) +-- ------------------------- +-- Each register (RSTV0910__XXXXX) is defined by its address (2 bytes). +-- +-- Each field (FSTV0910__XXXXX)is defined as follow: +-- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] + ======================================================================= */ + +/*MID*/ +#define RSTV0910_MID 0xf100 +#define FSTV0910_MCHIP_IDENT 0xf10000f0 +#define FSTV0910_MRELEASE 0xf100000f + +/*DID*/ +#define RSTV0910_DID 0xf101 +#define FSTV0910_DEVICE_ID 0xf10100ff + +/*DACR1*/ +#define RSTV0910_DACR1 0xf113 +#define FSTV0910_DAC_MODE 0xf11300e0 +#define FSTV0910_DAC_VALUE1 0xf113000f + +/*DACR2*/ +#define RSTV0910_DACR2 0xf114 +#define FSTV0910_DAC_VALUE0 0xf11400ff + +/*PADCFG*/ +#define RSTV0910_PADCFG 0xf11a +#define FSTV0910_AGCRF2_OPD 0xf11a0008 +#define FSTV0910_AGCRF2_XOR 0xf11a0004 +#define FSTV0910_AGCRF1_OPD 0xf11a0002 +#define FSTV0910_AGCRF1_XOR 0xf11a0001 + +/*OUTCFG2*/ +#define RSTV0910_OUTCFG2 0xf11b +#define FSTV0910_TS2_ERROR_XOR 0xf11b0080 +#define FSTV0910_TS2_DPN_XOR 0xf11b0040 +#define FSTV0910_TS2_STROUT_XOR 0xf11b0020 +#define FSTV0910_TS2_CLOCKOUT_XOR 0xf11b0010 +#define FSTV0910_TS1_ERROR_XOR 0xf11b0008 +#define FSTV0910_TS1_DPN_XOR 0xf11b0004 +#define FSTV0910_TS1_STROUT_XOR 0xf11b0002 +#define FSTV0910_TS1_CLOCKOUT_XOR 0xf11b0001 + +/*OUTCFG*/ +#define RSTV0910_OUTCFG 0xf11c +#define FSTV0910_INV_DATA6 0xf11c0080 +#define FSTV0910_TS2_OUTSER_HZ 0xf11c0020 +#define FSTV0910_TS1_OUTSER_HZ 0xf11c0010 +#define FSTV0910_TS2_OUTPAR_HZ 0xf11c0008 +#define FSTV0910_TS1_OUTPAR_HZ 0xf11c0004 +#define FSTV0910_TS_SERDATA0 0xf11c0002 + +/*IRQSTATUS3*/ +#define RSTV0910_IRQSTATUS3 0xf120 +#define FSTV0910_SPLL_LOCK 0xf1200020 +#define FSTV0910_SSTREAM_LCK_1 0xf1200010 +#define FSTV0910_SSTREAM_LCK_2 0xf1200008 +#define FSTV0910_SDVBS1_PRF_2 0xf1200002 +#define FSTV0910_SDVBS1_PRF_1 0xf1200001 + +/*IRQSTATUS2*/ +#define RSTV0910_IRQSTATUS2 0xf121 +#define FSTV0910_SSPY_ENDSIM_1 0xf1210080 +#define FSTV0910_SSPY_ENDSIM_2 0xf1210040 +#define FSTV0910_SPKTDEL_ERROR_2 0xf1210010 +#define FSTV0910_SPKTDEL_LOCKB_2 0xf1210008 +#define FSTV0910_SPKTDEL_LOCK_2 0xf1210004 +#define FSTV0910_SPKTDEL_ERROR_1 0xf1210002 +#define FSTV0910_SPKTDEL_LOCKB_1 0xf1210001 + +/*IRQSTATUS1*/ +#define RSTV0910_IRQSTATUS1 0xf122 +#define FSTV0910_SPKTDEL_LOCK_1 0xf1220080 +#define FSTV0910_SFEC_LOCKB_2 0xf1220040 +#define FSTV0910_SFEC_LOCK_2 0xf1220020 +#define FSTV0910_SFEC_LOCKB_1 0xf1220010 +#define FSTV0910_SFEC_LOCK_1 0xf1220008 +#define FSTV0910_SDEMOD_LOCKB_2 0xf1220004 +#define FSTV0910_SDEMOD_LOCK_2 0xf1220002 +#define FSTV0910_SDEMOD_IRQ_2 0xf1220001 + +/*IRQSTATUS0*/ +#define RSTV0910_IRQSTATUS0 0xf123 +#define FSTV0910_SDEMOD_LOCKB_1 0xf1230080 +#define FSTV0910_SDEMOD_LOCK_1 0xf1230040 +#define FSTV0910_SDEMOD_IRQ_1 0xf1230020 +#define FSTV0910_SBCH_ERRFLAG 0xf1230010 +#define FSTV0910_SECW2_IRQ 0xf1230008 +#define FSTV0910_SDISEQC2_IRQ 0xf1230004 +#define FSTV0910_SECW1_IRQ 0xf1230002 +#define FSTV0910_SDISEQC1_IRQ 0xf1230001 + +/*IRQMASK3*/ +#define RSTV0910_IRQMASK3 0xf124 +#define FSTV0910_MPLL_LOCK 0xf1240020 +#define FSTV0910_MSTREAM_LCK_1 0xf1240010 +#define FSTV0910_MSTREAM_LCK_2 0xf1240008 +#define FSTV0910_MDVBS1_PRF_2 0xf1240002 +#define FSTV0910_MDVBS1_PRF_1 0xf1240001 + +/*IRQMASK2*/ +#define RSTV0910_IRQMASK2 0xf125 +#define FSTV0910_MSPY_ENDSIM_1 0xf1250080 +#define FSTV0910_MSPY_ENDSIM_2 0xf1250040 +#define FSTV0910_MPKTDEL_ERROR_2 0xf1250010 +#define FSTV0910_MPKTDEL_LOCKB_2 0xf1250008 +#define FSTV0910_MPKTDEL_LOCK_2 0xf1250004 +#define FSTV0910_MPKTDEL_ERROR_1 0xf1250002 +#define FSTV0910_MPKTDEL_LOCKB_1 0xf1250001 + +/*IRQMASK1*/ +#define RSTV0910_IRQMASK1 0xf126 +#define FSTV0910_MPKTDEL_LOCK_1 0xf1260080 +#define FSTV0910_MFEC_LOCKB_2 0xf1260040 +#define FSTV0910_MFEC_LOCK_2 0xf1260020 +#define FSTV0910_MFEC_LOCKB_1 0xf1260010 +#define FSTV0910_MFEC_LOCK_1 0xf1260008 +#define FSTV0910_MDEMOD_LOCKB_2 0xf1260004 +#define FSTV0910_MDEMOD_LOCK_2 0xf1260002 +#define FSTV0910_MDEMOD_IRQ_2 0xf1260001 + +/*IRQMASK0*/ +#define RSTV0910_IRQMASK0 0xf127 +#define FSTV0910_MDEMOD_LOCKB_1 0xf1270080 +#define FSTV0910_MDEMOD_LOCK_1 0xf1270040 +#define FSTV0910_MDEMOD_IRQ_1 0xf1270020 +#define FSTV0910_MBCH_ERRFLAG 0xf1270010 +#define FSTV0910_MECW2_IRQ 0xf1270008 +#define FSTV0910_MDISEQC2_IRQ 0xf1270004 +#define FSTV0910_MECW1_IRQ 0xf1270002 +#define FSTV0910_MDISEQC1_IRQ 0xf1270001 + +/*I2CCFG*/ +#define RSTV0910_I2CCFG 0xf129 +#define FSTV0910_I2C2_FASTMODE 0xf1290080 +#define FSTV0910_STATUS_WR2 0xf1290040 +#define FSTV0910_I2C2ADDR_INC 0xf1290030 +#define FSTV0910_I2C_FASTMODE 0xf1290008 +#define FSTV0910_STATUS_WR 0xf1290004 +#define FSTV0910_I2CADDR_INC 0xf1290003 + +/*P1_I2CRPT*/ +#define RSTV0910_P1_I2CRPT 0xf12a +#define FSTV0910_P1_I2CT_ON 0xf12a0080 +#define FSTV0910_P1_ENARPT_LEVEL 0xf12a0070 +#define FSTV0910_P1_SCLT_DELAY 0xf12a0008 +#define FSTV0910_P1_STOP_ENABLE 0xf12a0004 +#define FSTV0910_P1_STOP_SDAT2SDA 0xf12a0002 + +/*P2_I2CRPT*/ +#define RSTV0910_P2_I2CRPT 0xf12b +#define FSTV0910_P2_I2CT_ON 0xf12b0080 +#define FSTV0910_P2_ENARPT_LEVEL 0xf12b0070 +#define FSTV0910_P2_SCLT_DELAY 0xf12b0008 +#define FSTV0910_P2_STOP_ENABLE 0xf12b0004 +#define FSTV0910_P2_STOP_SDAT2SDA 0xf12b0002 + +/*GPIO0CFG*/ +#define RSTV0910_GPIO0CFG 0xf140 +#define FSTV0910_GPIO0_OPD 0xf1400080 +#define FSTV0910_GPIO0_CONFIG 0xf140007e +#define FSTV0910_GPIO0_XOR 0xf1400001 + +/*GPIO1CFG*/ +#define RSTV0910_GPIO1CFG 0xf141 +#define FSTV0910_GPIO1_OPD 0xf1410080 +#define FSTV0910_GPIO1_CONFIG 0xf141007e +#define FSTV0910_GPIO1_XOR 0xf1410001 + +/*GPIO2CFG*/ +#define RSTV0910_GPIO2CFG 0xf142 +#define FSTV0910_GPIO2_OPD 0xf1420080 +#define FSTV0910_GPIO2_CONFIG 0xf142007e +#define FSTV0910_GPIO2_XOR 0xf1420001 + +/*GPIO3CFG*/ +#define RSTV0910_GPIO3CFG 0xf143 +#define FSTV0910_GPIO3_OPD 0xf1430080 +#define FSTV0910_GPIO3_CONFIG 0xf143007e +#define FSTV0910_GPIO3_XOR 0xf1430001 + +/*GPIO4CFG*/ +#define RSTV0910_GPIO4CFG 0xf144 +#define FSTV0910_GPIO4_OPD 0xf1440080 +#define FSTV0910_GPIO4_CONFIG 0xf144007e +#define FSTV0910_GPIO4_XOR 0xf1440001 + +/*GPIO5CFG*/ +#define RSTV0910_GPIO5CFG 0xf145 +#define FSTV0910_GPIO5_OPD 0xf1450080 +#define FSTV0910_GPIO5_CONFIG 0xf145007e +#define FSTV0910_GPIO5_XOR 0xf1450001 + +/*GPIO6CFG*/ +#define RSTV0910_GPIO6CFG 0xf146 +#define FSTV0910_GPIO6_OPD 0xf1460080 +#define FSTV0910_GPIO6_CONFIG 0xf146007e +#define FSTV0910_GPIO6_XOR 0xf1460001 + +/*GPIO7CFG*/ +#define RSTV0910_GPIO7CFG 0xf147 +#define FSTV0910_GPIO7_OPD 0xf1470080 +#define FSTV0910_GPIO7_CONFIG 0xf147007e +#define FSTV0910_GPIO7_XOR 0xf1470001 + +/*GPIO8CFG*/ +#define RSTV0910_GPIO8CFG 0xf148 +#define FSTV0910_GPIO8_OPD 0xf1480080 +#define FSTV0910_GPIO8_CONFIG 0xf148007e +#define FSTV0910_GPIO8_XOR 0xf1480001 + +/*GPIO9CFG*/ +#define RSTV0910_GPIO9CFG 0xf149 +#define FSTV0910_GPIO9_OPD 0xf1490080 +#define FSTV0910_GPIO9_CONFIG 0xf149007e +#define FSTV0910_GPIO9_XOR 0xf1490001 + +/*GPIO10CFG*/ +#define RSTV0910_GPIO10CFG 0xf14a +#define FSTV0910_GPIO10_OPD 0xf14a0080 +#define FSTV0910_GPIO10_CONFIG 0xf14a007e +#define FSTV0910_GPIO10_XOR 0xf14a0001 + +/*GPIO11CFG*/ +#define RSTV0910_GPIO11CFG 0xf14b +#define FSTV0910_GPIO11_OPD 0xf14b0080 +#define FSTV0910_GPIO11_CONFIG 0xf14b007e +#define FSTV0910_GPIO11_XOR 0xf14b0001 + +/*GPIO12CFG*/ +#define RSTV0910_GPIO12CFG 0xf14c +#define FSTV0910_GPIO12_OPD 0xf14c0080 +#define FSTV0910_GPIO12_CONFIG 0xf14c007e +#define FSTV0910_GPIO12_XOR 0xf14c0001 + +/*GPIO13CFG*/ +#define RSTV0910_GPIO13CFG 0xf14d +#define FSTV0910_GPIO13_OPD 0xf14d0080 +#define FSTV0910_GPIO13_CONFIG 0xf14d007e +#define FSTV0910_GPIO13_XOR 0xf14d0001 + +/*GPIO14CFG*/ +#define RSTV0910_GPIO14CFG 0xf14e +#define FSTV0910_GPIO14_OPD 0xf14e0080 +#define FSTV0910_GPIO14_CONFIG 0xf14e007e +#define FSTV0910_GPIO14_XOR 0xf14e0001 + +/*GPIO15CFG*/ +#define RSTV0910_GPIO15CFG 0xf14f +#define FSTV0910_GPIO15_OPD 0xf14f0080 +#define FSTV0910_GPIO15_CONFIG 0xf14f007e +#define FSTV0910_GPIO15_XOR 0xf14f0001 + +/*GPIO16CFG*/ +#define RSTV0910_GPIO16CFG 0xf150 +#define FSTV0910_GPIO16_OPD 0xf1500080 +#define FSTV0910_GPIO16_CONFIG 0xf150007e +#define FSTV0910_GPIO16_XOR 0xf1500001 + +/*GPIO17CFG*/ +#define RSTV0910_GPIO17CFG 0xf151 +#define FSTV0910_GPIO17_OPD 0xf1510080 +#define FSTV0910_GPIO17_CONFIG 0xf151007e +#define FSTV0910_GPIO17_XOR 0xf1510001 + +/*GPIO18CFG*/ +#define RSTV0910_GPIO18CFG 0xf152 +#define FSTV0910_GPIO18_OPD 0xf1520080 +#define FSTV0910_GPIO18_CONFIG 0xf152007e +#define FSTV0910_GPIO18_XOR 0xf1520001 + +/*GPIO19CFG*/ +#define RSTV0910_GPIO19CFG 0xf153 +#define FSTV0910_GPIO19_OPD 0xf1530080 +#define FSTV0910_GPIO19_CONFIG 0xf153007e +#define FSTV0910_GPIO19_XOR 0xf1530001 + +/*GPIO20CFG*/ +#define RSTV0910_GPIO20CFG 0xf154 +#define FSTV0910_GPIO20_OPD 0xf1540080 +#define FSTV0910_GPIO20_CONFIG 0xf154007e +#define FSTV0910_GPIO20_XOR 0xf1540001 + +/*GPIO21CFG*/ +#define RSTV0910_GPIO21CFG 0xf155 +#define FSTV0910_GPIO21_OPD 0xf1550080 +#define FSTV0910_GPIO21_CONFIG 0xf155007e +#define FSTV0910_GPIO21_XOR 0xf1550001 + +/*GPIO22CFG*/ +#define RSTV0910_GPIO22CFG 0xf156 +#define FSTV0910_GPIO22_OPD 0xf1560080 +#define FSTV0910_GPIO22_CONFIG 0xf156007e +#define FSTV0910_GPIO22_XOR 0xf1560001 + +/*STRSTATUS1*/ +#define RSTV0910_STRSTATUS1 0xf16a +#define FSTV0910_STRSTATUS_SEL2 0xf16a00f0 +#define FSTV0910_STRSTATUS_SEL1 0xf16a000f + +/*STRSTATUS2*/ +#define RSTV0910_STRSTATUS2 0xf16b +#define FSTV0910_STRSTATUS_SEL4 0xf16b00f0 +#define FSTV0910_STRSTATUS_SEL3 0xf16b000f + +/*STRSTATUS3*/ +#define RSTV0910_STRSTATUS3 0xf16c +#define FSTV0910_STRSTATUS_SEL6 0xf16c00f0 +#define FSTV0910_STRSTATUS_SEL5 0xf16c000f + +/*FSKTFC2*/ +#define RSTV0910_FSKTFC2 0xf170 +#define FSTV0910_FSKT_KMOD 0xf17000fc +#define FSTV0910_FSKT_CAR2 0xf1700003 + +/*FSKTFC1*/ +#define RSTV0910_FSKTFC1 0xf171 +#define FSTV0910_FSKT_CAR1 0xf17100ff + +/*FSKTFC0*/ +#define RSTV0910_FSKTFC0 0xf172 +#define FSTV0910_FSKT_CAR0 0xf17200ff + +/*FSKTDELTAF1*/ +#define RSTV0910_FSKTDELTAF1 0xf173 +#define FSTV0910_FSKT_DELTAF1 0xf173000f + +/*FSKTDELTAF0*/ +#define RSTV0910_FSKTDELTAF0 0xf174 +#define FSTV0910_FSKT_DELTAF0 0xf17400ff + +/*FSKTCTRL*/ +#define RSTV0910_FSKTCTRL 0xf175 +#define FSTV0910_FSKT_PINSEL 0xf1750080 +#define FSTV0910_FSKT_EN_SGN 0xf1750040 +#define FSTV0910_FSKT_MOD_SGN 0xf1750020 +#define FSTV0910_FSKT_MOD_EN 0xf175001c +#define FSTV0910_FSKT_DACMODE 0xf1750003 + +/*FSKRFC2*/ +#define RSTV0910_FSKRFC2 0xf176 +#define FSTV0910_FSKR_DETSGN 0xf1760040 +#define FSTV0910_FSKR_OUTSGN 0xf1760020 +#define FSTV0910_FSKR_KAGC 0xf176001c +#define FSTV0910_FSKR_CAR2 0xf1760003 + +/*FSKRFC1*/ +#define RSTV0910_FSKRFC1 0xf177 +#define FSTV0910_FSKR_CAR1 0xf17700ff + +/*FSKRFC0*/ +#define RSTV0910_FSKRFC0 0xf178 +#define FSTV0910_FSKR_CAR0 0xf17800ff + +/*FSKRK1*/ +#define RSTV0910_FSKRK1 0xf179 +#define FSTV0910_FSKR_K1_EXP 0xf17900e0 +#define FSTV0910_FSKR_K1_MANT 0xf179001f + +/*FSKRK2*/ +#define RSTV0910_FSKRK2 0xf17a +#define FSTV0910_FSKR_K2_EXP 0xf17a00e0 +#define FSTV0910_FSKR_K2_MANT 0xf17a001f + +/*FSKRAGCR*/ +#define RSTV0910_FSKRAGCR 0xf17b +#define FSTV0910_FSKR_OUTCTL 0xf17b00c0 +#define FSTV0910_FSKR_AGC_REF 0xf17b003f + +/*FSKRAGC*/ +#define RSTV0910_FSKRAGC 0xf17c +#define FSTV0910_FSKR_AGC_ACCU 0xf17c00ff + +/*FSKRALPHA*/ +#define RSTV0910_FSKRALPHA 0xf17d +#define FSTV0910_FSKR_ALPHA_EXP 0xf17d001c +#define FSTV0910_FSKR_ALPHA_M 0xf17d0003 + +/*FSKRPLTH1*/ +#define RSTV0910_FSKRPLTH1 0xf17e +#define FSTV0910_FSKR_BETA 0xf17e00f0 +#define FSTV0910_FSKR_PLL_TRESH1 0xf17e000f + +/*FSKRPLTH0*/ +#define RSTV0910_FSKRPLTH0 0xf17f +#define FSTV0910_FSKR_PLL_TRESH0 0xf17f00ff + +/*FSKRDF1*/ +#define RSTV0910_FSKRDF1 0xf180 +#define FSTV0910_FSKR_OUT 0xf1800080 +#define FSTV0910_FSKR_STATE 0xf1800060 +#define FSTV0910_FSKR_DELTAF1 0xf180001f + +/*FSKRDF0*/ +#define RSTV0910_FSKRDF0 0xf181 +#define FSTV0910_FSKR_DELTAF0 0xf18100ff + +/*FSKRSTEPP*/ +#define RSTV0910_FSKRSTEPP 0xf182 +#define FSTV0910_FSKR_STEP_PLUS 0xf18200ff + +/*FSKRSTEPM*/ +#define RSTV0910_FSKRSTEPM 0xf183 +#define FSTV0910_FSKR_STEP_MINUS 0xf18300ff + +/*FSKRDET1*/ +#define RSTV0910_FSKRDET1 0xf184 +#define FSTV0910_FSKR_DETECT 0xf1840080 +#define FSTV0910_FSKR_CARDET_ACCU1 0xf184000f + +/*FSKRDET0*/ +#define RSTV0910_FSKRDET0 0xf185 +#define FSTV0910_FSKR_CARDET_ACCU0 0xf18500ff + +/*FSKRDTH1*/ +#define RSTV0910_FSKRDTH1 0xf186 +#define FSTV0910_FSKR_CARLOSS_THRESH1 0xf18600f0 +#define FSTV0910_FSKR_CARDET_THRESH1 0xf186000f + +/*FSKRDTH0*/ +#define RSTV0910_FSKRDTH0 0xf187 +#define FSTV0910_FSKR_CARDET_THRESH0 0xf18700ff + +/*FSKRLOSS*/ +#define RSTV0910_FSKRLOSS 0xf188 +#define FSTV0910_FSKR_CARLOSS_THRESH0 0xf18800ff + +/*NCOARSE*/ +#define RSTV0910_NCOARSE 0xf1b3 +#define FSTV0910_CP 0xf1b300f8 +#define FSTV0910_IDF 0xf1b30007 + +/*NCOARSE1*/ +#define RSTV0910_NCOARSE1 0xf1b4 +#define FSTV0910_N_DIV 0xf1b400ff + +/*NCOARSE2*/ +#define RSTV0910_NCOARSE2 0xf1b5 +#define FSTV0910_ODF 0xf1b5003f + +/*SYNTCTRL*/ +#define RSTV0910_SYNTCTRL 0xf1b6 +#define FSTV0910_STANDBY 0xf1b60080 +#define FSTV0910_BYPASSPLLCORE 0xf1b60040 +#define FSTV0910_STOP_PLL 0xf1b60008 +#define FSTV0910_OSCI_E 0xf1b60002 + +/*FILTCTRL*/ +#define RSTV0910_FILTCTRL 0xf1b7 +#define FSTV0910_INV_CLKFSK 0xf1b70002 +#define FSTV0910_BYPASS_APPLI 0xf1b70001 + +/*PLLSTAT*/ +#define RSTV0910_PLLSTAT 0xf1b8 +#define FSTV0910_PLL_BIST_END 0xf1b80004 +#define FSTV0910_PLLLOCK 0xf1b80001 + +/*STOPCLK1*/ +#define RSTV0910_STOPCLK1 0xf1c2 +#define FSTV0910_INV_CLKADCI2 0xf1c20004 +#define FSTV0910_INV_CLKADCI1 0xf1c20001 + +/*STOPCLK2*/ +#define RSTV0910_STOPCLK2 0xf1c3 +#define FSTV0910_STOP_DVBS2FEC2 0xf1c30020 +#define FSTV0910_STOP_DVBS2FEC 0xf1c30010 +#define FSTV0910_STOP_DVBS1FEC2 0xf1c30008 +#define FSTV0910_STOP_DVBS1FEC 0xf1c30004 +#define FSTV0910_STOP_DEMOD2 0xf1c30002 +#define FSTV0910_STOP_DEMOD 0xf1c30001 + +/*PREGCTL*/ +#define RSTV0910_PREGCTL 0xf1c8 +#define FSTV0910_REG3V3TO2V5_POFF 0xf1c80080 + +/*TSTTNR0*/ +#define RSTV0910_TSTTNR0 0xf1df +#define FSTV0910_FSK_PON 0xf1df0004 +#define FSTV0910_FSK_OPENLOOP 0xf1df0002 + +/*TSTTNR1*/ +#define RSTV0910_TSTTNR1 0xf1e0 +#define FSTV0910_BYPASS_ADC1 0xf1e00080 +#define FSTV0910_INVADC1_CKOUT 0xf1e00040 +#define FSTV0910_SELIQSRC1 0xf1e00030 +#define FSTV0910_DEMOD2_SELADC 0xf1e00008 +#define FSTV0910_DEMOD1_SELADC 0xf1e00004 +#define FSTV0910_ADC1_PON 0xf1e00002 + +/*TSTTNR2*/ +#define RSTV0910_TSTTNR2 0xf1e1 +#define FSTV0910_I2C_DISEQC_BYPASS 0xf1e10080 +#define FSTV0910_I2C_DISEQC_ENCH 0xf1e10040 +#define FSTV0910_I2C_DISEQC_PON 0xf1e10020 +#define FSTV0910_DISEQC_CLKDIV 0xf1e1000f + +/*TSTTNR3*/ +#define RSTV0910_TSTTNR3 0xf1e2 +#define FSTV0910_BYPASS_ADC2 0xf1e20080 +#define FSTV0910_INVADC2_CKOUT 0xf1e20040 +#define FSTV0910_SELIQSRC2 0xf1e20030 +#define FSTV0910_ADC2_PON 0xf1e20002 + +/*P2_IQCONST*/ +#define RSTV0910_P2_IQCONST 0xf200 +#define FSTV0910_P2_CONSTEL_SELECT 0xf2000060 +#define FSTV0910_P2_IQSYMB_SEL 0xf200001f + +/*P2_NOSCFG*/ +#define RSTV0910_P2_NOSCFG 0xf201 +#define FSTV0910_P2_DIS_ACMRATIO 0xf2010080 +#define FSTV0910_P2_NOSIN_EGALSEL 0xf2010040 +#define FSTV0910_P2_DUMMYPL_NOSDATA 0xf2010020 +#define FSTV0910_P2_NOSPLH_BETA 0xf2010018 +#define FSTV0910_P2_NOSDATA_BETA 0xf2010007 + +/*P2_ISYMB*/ +#define RSTV0910_P2_ISYMB 0xf202 +#define FSTV0910_P2_I_SYMBOL 0xf20201ff + +/*P2_QSYMB*/ +#define RSTV0910_P2_QSYMB 0xf203 +#define FSTV0910_P2_Q_SYMBOL 0xf20301ff + +/*P2_AGC1CFG*/ +#define RSTV0910_P2_AGC1CFG 0xf204 +#define FSTV0910_P2_DC_FROZEN 0xf2040080 +#define FSTV0910_P2_DC_CORRECT 0xf2040040 +#define FSTV0910_P2_AMM_FROZEN 0xf2040020 +#define FSTV0910_P2_AMM_CORRECT 0xf2040010 +#define FSTV0910_P2_QUAD_FROZEN 0xf2040008 +#define FSTV0910_P2_QUAD_CORRECT 0xf2040004 +#define FSTV0910_P2_DCCOMP_SLOW 0xf2040002 +#define FSTV0910_P2_IQMISM_SLOW 0xf2040001 + +/*P2_AGC1CN*/ +#define RSTV0910_P2_AGC1CN 0xf206 +#define FSTV0910_P2_AGC1_LOCKED 0xf2060080 +#define FSTV0910_P2_AGC1_OVERFLOW 0xf2060040 +#define FSTV0910_P2_AGC1_NOSLOWLK 0xf2060020 +#define FSTV0910_P2_AGC1_MINPOWER 0xf2060010 +#define FSTV0910_P2_AGCOUT_FAST 0xf2060008 +#define FSTV0910_P2_AGCIQ_BETA 0xf2060007 + +/*P2_AGC1REF*/ +#define RSTV0910_P2_AGC1REF 0xf207 +#define FSTV0910_P2_AGCIQ_REF 0xf20700ff + +/*P2_IDCCOMP*/ +#define RSTV0910_P2_IDCCOMP 0xf208 +#define FSTV0910_P2_IAVERAGE_ADJ 0xf20801ff + +/*P2_QDCCOMP*/ +#define RSTV0910_P2_QDCCOMP 0xf209 +#define FSTV0910_P2_QAVERAGE_ADJ 0xf20901ff + +/*P2_POWERI*/ +#define RSTV0910_P2_POWERI 0xf20a +#define FSTV0910_P2_POWER_I 0xf20a00ff + +/*P2_POWERQ*/ +#define RSTV0910_P2_POWERQ 0xf20b +#define FSTV0910_P2_POWER_Q 0xf20b00ff + +/*P2_AGC1AMM*/ +#define RSTV0910_P2_AGC1AMM 0xf20c +#define FSTV0910_P2_AMM_VALUE 0xf20c00ff + +/*P2_AGC1QUAD*/ +#define RSTV0910_P2_AGC1QUAD 0xf20d +#define FSTV0910_P2_QUAD_VALUE 0xf20d01ff + +/*P2_AGCIQIN1*/ +#define RSTV0910_P2_AGCIQIN1 0xf20e +#define FSTV0910_P2_AGCIQ_VALUE1 0xf20e00ff + +/*P2_AGCIQIN0*/ +#define RSTV0910_P2_AGCIQIN0 0xf20f +#define FSTV0910_P2_AGCIQ_VALUE0 0xf20f00ff + +/*P2_DEMOD*/ +#define RSTV0910_P2_DEMOD 0xf210 +#define FSTV0910_P2_MANUALS2_ROLLOFF 0xf2100080 +#define FSTV0910_P2_SPECINV_CONTROL 0xf2100030 +#define FSTV0910_P2_MANUALSX_ROLLOFF 0xf2100004 +#define FSTV0910_P2_ROLLOFF_CONTROL 0xf2100003 + +/*P2_DMDMODCOD*/ +#define RSTV0910_P2_DMDMODCOD 0xf211 +#define FSTV0910_P2_MANUAL_MODCOD 0xf2110080 +#define FSTV0910_P2_DEMOD_MODCOD 0xf211007c +#define FSTV0910_P2_DEMOD_TYPE 0xf2110003 + +/*P2_DSTATUS*/ +#define RSTV0910_P2_DSTATUS 0xf212 +#define FSTV0910_P2_CAR_LOCK 0xf2120080 +#define FSTV0910_P2_TMGLOCK_QUALITY 0xf2120060 +#define FSTV0910_P2_SDVBS1_ENABLE 0xf2120010 +#define FSTV0910_P2_LOCK_DEFINITIF 0xf2120008 +#define FSTV0910_P2_TIMING_IS_LOCKED 0xf2120004 +#define FSTV0910_P2_DEMOD_SYSCFG 0xf2120002 +#define FSTV0910_P2_OVADC_DETECT 0xf2120001 + +/*P2_DSTATUS2*/ +#define RSTV0910_P2_DSTATUS2 0xf213 +#define FSTV0910_P2_DEMOD_DELOCK 0xf2130080 +#define FSTV0910_P2_DEMOD_TIMEOUT 0xf2130040 +#define FSTV0910_P2_MODCODRQ_SYNCTAG 0xf2130020 +#define FSTV0910_P2_POLYPH_SATEVENT 0xf2130010 +#define FSTV0910_P2_AGC1_NOSIGNALACK 0xf2130008 +#define FSTV0910_P2_AGC2_OVERFLOW 0xf2130004 +#define FSTV0910_P2_CFR_OVERFLOW 0xf2130002 +#define FSTV0910_P2_GAMMA_OVERUNDER 0xf2130001 + +/*P2_DMDCFGMD*/ +#define RSTV0910_P2_DMDCFGMD 0xf214 +#define FSTV0910_P2_DVBS2_ENABLE 0xf2140080 +#define FSTV0910_P2_DVBS1_ENABLE 0xf2140040 +#define FSTV0910_P2_SCAN_ENABLE 0xf2140010 +#define FSTV0910_P2_CFR_AUTOSCAN 0xf2140008 +#define FSTV0910_P2_NOFORCE_RELOCK 0xf2140004 +#define FSTV0910_P2_TUN_RNG 0xf2140003 + +/*P2_DMDCFG2*/ +#define RSTV0910_P2_DMDCFG2 0xf215 +#define FSTV0910_P2_AGC1_WAITLOCK 0xf2150080 +#define FSTV0910_P2_S1S2_SEQUENTIAL 0xf2150040 +#define FSTV0910_P2_BLINDPEA_MODE 0xf2150020 +#define FSTV0910_P2_INFINITE_RELOCK 0xf2150010 +#define FSTV0910_P2_BWOFFSET_COLDWARM 0xf2150008 +#define FSTV0910_P2_TMGLOCK_NSCANSTOP 0xf2150004 +#define FSTV0910_P2_COARSE_LK3MODE 0xf2150002 +#define FSTV0910_P2_COARSE_LK2MODE 0xf2150001 + +/*P2_DMDISTATE*/ +#define RSTV0910_P2_DMDISTATE 0xf216 +#define FSTV0910_P2_I2C_NORESETDMODE 0xf2160080 +#define FSTV0910_P2_FORCE_ETAPED 0xf2160040 +#define FSTV0910_P2_SDMDRST_DIRCLK 0xf2160020 +#define FSTV0910_P2_I2C_DEMOD_MODE 0xf216001f + +/*P2_DMDT0M*/ +#define RSTV0910_P2_DMDT0M 0xf217 +#define FSTV0910_P2_DMDT0_MIN 0xf21700ff + +/*P2_DMDSTATE*/ +#define RSTV0910_P2_DMDSTATE 0xf21b +#define FSTV0910_P2_DEMOD_LOCKED 0xf21b0080 +#define FSTV0910_P2_HEADER_MODE 0xf21b0060 +#define FSTV0910_P2_DEMOD_MODE 0xf21b001f + +/*P2_DMDFLYW*/ +#define RSTV0910_P2_DMDFLYW 0xf21c +#define FSTV0910_P2_I2C_IRQVAL 0xf21c00f0 +#define FSTV0910_P2_FLYWHEEL_CPT 0xf21c000f + +/*P2_DSTATUS3*/ +#define RSTV0910_P2_DSTATUS3 0xf21d +#define FSTV0910_P2_CFR_ZIGZAG 0xf21d0080 +#define FSTV0910_P2_DEMOD_CFGMODE 0xf21d0060 +#define FSTV0910_P2_GAMMA_LOWBAUDRATE 0xf21d0010 +#define FSTV0910_P2_RELOCK_MODE 0xf21d0008 +#define FSTV0910_P2_DEMOD_FAIL 0xf21d0004 +#define FSTV0910_P2_ETAPE1A_DVBXMEM 0xf21d0003 + +/*P2_DMDCFG3*/ +#define RSTV0910_P2_DMDCFG3 0xf21e +#define FSTV0910_P2_DVBS1_TMGWAIT 0xf21e0080 +#define FSTV0910_P2_NO_BWCENTERING 0xf21e0040 +#define FSTV0910_P2_INV_SEQSRCH 0xf21e0020 +#define FSTV0910_P2_DIS_SFRUPLOW_TRK 0xf21e0010 +#define FSTV0910_P2_NOSTOP_FIFOFULL 0xf21e0008 +#define FSTV0910_P2_LOCKTIME_MODE 0xf21e0007 + +/*P2_DMDCFG4*/ +#define RSTV0910_P2_DMDCFG4 0xf21f +#define FSTV0910_P2_DIS_VITLOCK 0xf21f0080 +#define FSTV0910_P2_S1S2TOUT_FAST 0xf21f0040 +#define FSTV0910_P2_DEMOD_FASTLOCK 0xf21f0020 +#define FSTV0910_P2_S1HIER_ENABLE 0xf21f0010 +#define FSTV0910_P2_TUNER_NRELAUNCH 0xf21f0008 +#define FSTV0910_P2_DIS_CLKENABLE 0xf21f0004 +#define FSTV0910_P2_DIS_HDRDIVLOCK 0xf21f0002 +#define FSTV0910_P2_NO_TNRWBINIT 0xf21f0001 + +/*P2_CORRELMANT*/ +#define RSTV0910_P2_CORRELMANT 0xf220 +#define FSTV0910_P2_CORREL_MANT 0xf22000ff + +/*P2_CORRELABS*/ +#define RSTV0910_P2_CORRELABS 0xf221 +#define FSTV0910_P2_CORREL_ABS 0xf22100ff + +/*P2_CORRELEXP*/ +#define RSTV0910_P2_CORRELEXP 0xf222 +#define FSTV0910_P2_CORREL_ABSEXP 0xf22200f0 +#define FSTV0910_P2_CORREL_EXP 0xf222000f + +/*P2_PLHMODCOD*/ +#define RSTV0910_P2_PLHMODCOD 0xf224 +#define FSTV0910_P2_SPECINV_DEMOD 0xf2240080 +#define FSTV0910_P2_PLH_MODCOD 0xf224007c +#define FSTV0910_P2_PLH_TYPE 0xf2240003 + +/*P2_DMDREG*/ +#define RSTV0910_P2_DMDREG 0xf225 +#define FSTV0910_P2_EXTPSK_MODE 0xf2250080 +#define FSTV0910_P2_HIER_SHORTFRAME 0xf2250002 +#define FSTV0910_P2_DECIM_PLFRAMES 0xf2250001 + +/*P2_AGC2O*/ +#define RSTV0910_P2_AGC2O 0xf22c +#define FSTV0910_P2_CSTENV_MODE 0xf22c00c0 +#define FSTV0910_P2_AGC2_LKSQRT 0xf22c0020 +#define FSTV0910_P2_AGC2_LKMODE 0xf22c0010 +#define FSTV0910_P2_AGC2_LKEQUA 0xf22c0008 +#define FSTV0910_P2_AGC2_COEF 0xf22c0007 + +/*P2_AGC2REF*/ +#define RSTV0910_P2_AGC2REF 0xf22d +#define FSTV0910_P2_AGC2_REF 0xf22d00ff + +/*P2_AGC1ADJ*/ +#define RSTV0910_P2_AGC1ADJ 0xf22e +#define FSTV0910_P2_AGC1ADJ_MANUAL 0xf22e0080 +#define FSTV0910_P2_AGC1_ADJUSTED 0xf22e007f + +/*P2_AGC2I1*/ +#define RSTV0910_P2_AGC2I1 0xf236 +#define FSTV0910_P2_AGC2_INTEGRATOR1 0xf23600ff + +/*P2_AGC2I0*/ +#define RSTV0910_P2_AGC2I0 0xf237 +#define FSTV0910_P2_AGC2_INTEGRATOR0 0xf23700ff + +/*P2_CARCFG*/ +#define RSTV0910_P2_CARCFG 0xf238 +#define FSTV0910_P2_CFRUPLOW_AUTO 0xf2380080 +#define FSTV0910_P2_CFRUPLOW_TEST 0xf2380040 +#define FSTV0910_P2_WIDE_FREQDET 0xf2380020 +#define FSTV0910_P2_CARHDR_NODIV8 0xf2380010 +#define FSTV0910_P2_I2C_ROTA 0xf2380008 +#define FSTV0910_P2_ROTAON 0xf2380004 +#define FSTV0910_P2_PH_DET_ALGO 0xf2380003 + +/*P2_ACLC*/ +#define RSTV0910_P2_ACLC 0xf239 +#define FSTV0910_P2_CARS1_ANOSAUTO 0xf2390040 +#define FSTV0910_P2_CAR_ALPHA_MANT 0xf2390030 +#define FSTV0910_P2_CAR_ALPHA_EXP 0xf239000f + +/*P2_BCLC*/ +#define RSTV0910_P2_BCLC 0xf23a +#define FSTV0910_P2_CARS1_BNOSAUTO 0xf23a0040 +#define FSTV0910_P2_CAR_BETA_MANT 0xf23a0030 +#define FSTV0910_P2_CAR_BETA_EXP 0xf23a000f + +/*P2_CARFREQ*/ +#define RSTV0910_P2_CARFREQ 0xf23d +#define FSTV0910_P2_KC_COARSE_EXP 0xf23d00f0 +#define FSTV0910_P2_BETA_FREQ 0xf23d000f + +/*P2_CARHDR*/ +#define RSTV0910_P2_CARHDR 0xf23e +#define FSTV0910_P2_K_FREQ_HDR 0xf23e00ff + +/*P2_LDT*/ +#define RSTV0910_P2_LDT 0xf23f +#define FSTV0910_P2_CARLOCK_THRES 0xf23f01ff + +/*P2_LDT2*/ +#define RSTV0910_P2_LDT2 0xf240 +#define FSTV0910_P2_CARLOCK_THRES2 0xf24001ff + +/*P2_CFRICFG*/ +#define RSTV0910_P2_CFRICFG 0xf241 +#define FSTV0910_P2_CFRINIT_UNVALRNG 0xf2410080 +#define FSTV0910_P2_CFRINIT_LUNVALCPT 0xf2410040 +#define FSTV0910_P2_CFRINIT_ABORTDBL 0xf2410020 +#define FSTV0910_P2_CFRINIT_ABORTPRED 0xf2410010 +#define FSTV0910_P2_CFRINIT_UNVALSKIP 0xf2410008 +#define FSTV0910_P2_CFRINIT_CSTINC 0xf2410004 +#define FSTV0910_P2_CFRIROLL_GARDER 0xf2410002 +#define FSTV0910_P2_NEG_CFRSTEP 0xf2410001 + +/*P2_CFRUP1*/ +#define RSTV0910_P2_CFRUP1 0xf242 +#define FSTV0910_P2_CFR_UP1 0xf24201ff + +/*P2_CFRUP0*/ +#define RSTV0910_P2_CFRUP0 0xf243 +#define FSTV0910_P2_CFR_UP0 0xf24300ff + +/*P2_CFRIBASE1*/ +#define RSTV0910_P2_CFRIBASE1 0xf244 +#define FSTV0910_P2_CFRINIT_BASE1 0xf24400ff + +/*P2_CFRIBASE0*/ +#define RSTV0910_P2_CFRIBASE0 0xf245 +#define FSTV0910_P2_CFRINIT_BASE0 0xf24500ff + +/*P2_CFRLOW1*/ +#define RSTV0910_P2_CFRLOW1 0xf246 +#define FSTV0910_P2_CFR_LOW1 0xf24601ff + +/*P2_CFRLOW0*/ +#define RSTV0910_P2_CFRLOW0 0xf247 +#define FSTV0910_P2_CFR_LOW0 0xf24700ff + +/*P2_CFRINIT1*/ +#define RSTV0910_P2_CFRINIT1 0xf248 +#define FSTV0910_P2_CFR_INIT1 0xf24801ff + +/*P2_CFRINIT0*/ +#define RSTV0910_P2_CFRINIT0 0xf249 +#define FSTV0910_P2_CFR_INIT0 0xf24900ff + +/*P2_CFRINC1*/ +#define RSTV0910_P2_CFRINC1 0xf24a +#define FSTV0910_P2_MANUAL_CFRINC 0xf24a0080 +#define FSTV0910_P2_CFR_INC1 0xf24a003f + +/*P2_CFRINC0*/ +#define RSTV0910_P2_CFRINC0 0xf24b +#define FSTV0910_P2_CFR_INC0 0xf24b00ff + +/*P2_CFR2*/ +#define RSTV0910_P2_CFR2 0xf24c +#define FSTV0910_P2_CAR_FREQ2 0xf24c01ff + +/*P2_CFR1*/ +#define RSTV0910_P2_CFR1 0xf24d +#define FSTV0910_P2_CAR_FREQ1 0xf24d00ff + +/*P2_CFR0*/ +#define RSTV0910_P2_CFR0 0xf24e +#define FSTV0910_P2_CAR_FREQ0 0xf24e00ff + +/*P2_LDI*/ +#define RSTV0910_P2_LDI 0xf24f +#define FSTV0910_P2_LOCK_DET_INTEGR 0xf24f01ff + +/*P2_TMGCFG*/ +#define RSTV0910_P2_TMGCFG 0xf250 +#define FSTV0910_P2_TMGLOCK_BETA 0xf25000c0 +#define FSTV0910_P2_DO_TIMING_CORR 0xf2500010 +#define FSTV0910_P2_MANUAL_SCAN 0xf250000c +#define FSTV0910_P2_TMG_MINFREQ 0xf2500003 + +/*P2_RTC*/ +#define RSTV0910_P2_RTC 0xf251 +#define FSTV0910_P2_TMGALPHA_EXP 0xf25100f0 +#define FSTV0910_P2_TMGBETA_EXP 0xf251000f + +/*P2_RTCS2*/ +#define RSTV0910_P2_RTCS2 0xf252 +#define FSTV0910_P2_TMGALPHAS2_EXP 0xf25200f0 +#define FSTV0910_P2_TMGBETAS2_EXP 0xf252000f + +/*P2_TMGTHRISE*/ +#define RSTV0910_P2_TMGTHRISE 0xf253 +#define FSTV0910_P2_TMGLOCK_THRISE 0xf25300ff + +/*P2_TMGTHFALL*/ +#define RSTV0910_P2_TMGTHFALL 0xf254 +#define FSTV0910_P2_TMGLOCK_THFALL 0xf25400ff + +/*P2_SFRUPRATIO*/ +#define RSTV0910_P2_SFRUPRATIO 0xf255 +#define FSTV0910_P2_SFR_UPRATIO 0xf25500ff + +/*P2_SFRLOWRATIO*/ +#define RSTV0910_P2_SFRLOWRATIO 0xf256 +#define FSTV0910_P2_SFR_LOWRATIO 0xf25600ff + +/*P2_KTTMG*/ +#define RSTV0910_P2_KTTMG 0xf257 +#define FSTV0910_P2_KT_TMG_EXP 0xf25700f0 + +/*P2_KREFTMG*/ +#define RSTV0910_P2_KREFTMG 0xf258 +#define FSTV0910_P2_KREF_TMG 0xf25800ff + +/*P2_SFRSTEP*/ +#define RSTV0910_P2_SFRSTEP 0xf259 +#define FSTV0910_P2_SFR_SCANSTEP 0xf25900f0 +#define FSTV0910_P2_SFR_CENTERSTEP 0xf259000f + +/*P2_TMGCFG2*/ +#define RSTV0910_P2_TMGCFG2 0xf25a +#define FSTV0910_P2_KREFTMG2_DECMODE 0xf25a00c0 +#define FSTV0910_P2_DIS_AUTOSAMP 0xf25a0008 +#define FSTV0910_P2_SCANINIT_QUART 0xf25a0004 +#define FSTV0910_P2_NOTMG_DVBS1DERAT 0xf25a0002 +#define FSTV0910_P2_SFRRATIO_FINE 0xf25a0001 + +/*P2_KREFTMG2*/ +#define RSTV0910_P2_KREFTMG2 0xf25b +#define FSTV0910_P2_KREF_TMG2 0xf25b00ff + +/*P2_TMGCFG3*/ +#define RSTV0910_P2_TMGCFG3 0xf25d +#define FSTV0910_P2_CFRINC_MODE 0xf25d0070 +#define FSTV0910_P2_CONT_TMGCENTER 0xf25d0008 +#define FSTV0910_P2_AUTO_GUP 0xf25d0004 +#define FSTV0910_P2_AUTO_GLOW 0xf25d0002 +#define FSTV0910_P2_SFRVAL_MINMODE 0xf25d0001 + +/*P2_SFRINIT1*/ +#define RSTV0910_P2_SFRINIT1 0xf25e +#define FSTV0910_P2_SFR_INIT1 0xf25e00ff + +/*P2_SFRINIT0*/ +#define RSTV0910_P2_SFRINIT0 0xf25f +#define FSTV0910_P2_SFR_INIT0 0xf25f00ff + +/*P2_SFRUP1*/ +#define RSTV0910_P2_SFRUP1 0xf260 +#define FSTV0910_P2_SYMB_FREQ_UP1 0xf26000ff + +/*P2_SFRUP0*/ +#define RSTV0910_P2_SFRUP0 0xf261 +#define FSTV0910_P2_SYMB_FREQ_UP0 0xf26100ff + +/*P2_SFRLOW1*/ +#define RSTV0910_P2_SFRLOW1 0xf262 +#define FSTV0910_P2_SYMB_FREQ_LOW1 0xf26200ff + +/*P2_SFRLOW0*/ +#define RSTV0910_P2_SFRLOW0 0xf263 +#define FSTV0910_P2_SYMB_FREQ_LOW0 0xf26300ff + +/*P2_SFR3*/ +#define RSTV0910_P2_SFR3 0xf264 +#define FSTV0910_P2_SYMB_FREQ3 0xf26400ff + +/*P2_SFR2*/ +#define RSTV0910_P2_SFR2 0xf265 +#define FSTV0910_P2_SYMB_FREQ2 0xf26500ff + +/*P2_SFR1*/ +#define RSTV0910_P2_SFR1 0xf266 +#define FSTV0910_P2_SYMB_FREQ1 0xf26600ff + +/*P2_SFR0*/ +#define RSTV0910_P2_SFR0 0xf267 +#define FSTV0910_P2_SYMB_FREQ0 0xf26700ff + +/*P2_TMGREG2*/ +#define RSTV0910_P2_TMGREG2 0xf268 +#define FSTV0910_P2_TMGREG2 0xf26800ff + +/*P2_TMGREG1*/ +#define RSTV0910_P2_TMGREG1 0xf269 +#define FSTV0910_P2_TMGREG1 0xf26900ff + +/*P2_TMGREG0*/ +#define RSTV0910_P2_TMGREG0 0xf26a +#define FSTV0910_P2_TMGREG0 0xf26a00ff + +/*P2_TMGLOCK1*/ +#define RSTV0910_P2_TMGLOCK1 0xf26b +#define FSTV0910_P2_TMGLOCK_LEVEL1 0xf26b01ff + +/*P2_TMGLOCK0*/ +#define RSTV0910_P2_TMGLOCK0 0xf26c +#define FSTV0910_P2_TMGLOCK_LEVEL0 0xf26c00ff + +/*P2_TMGOBS*/ +#define RSTV0910_P2_TMGOBS 0xf26d +#define FSTV0910_P2_ROLLOFF_STATUS 0xf26d00c0 +#define FSTV0910_P2_SCAN_SIGN 0xf26d0030 +#define FSTV0910_P2_TMG_SCANNING 0xf26d0008 +#define FSTV0910_P2_CHCENTERING_MODE 0xf26d0004 +#define FSTV0910_P2_TMG_SCANFAIL 0xf26d0002 + +/*P2_EQUALCFG*/ +#define RSTV0910_P2_EQUALCFG 0xf26f +#define FSTV0910_P2_NOTMG_NEGALWAIT 0xf26f0080 +#define FSTV0910_P2_EQUAL_ON 0xf26f0040 +#define FSTV0910_P2_SEL_EQUALCOR 0xf26f0038 +#define FSTV0910_P2_MU_EQUALDFE 0xf26f0007 + +/*P2_EQUAI1*/ +#define RSTV0910_P2_EQUAI1 0xf270 +#define FSTV0910_P2_EQUA_ACCI1 0xf27001ff + +/*P2_EQUAQ1*/ +#define RSTV0910_P2_EQUAQ1 0xf271 +#define FSTV0910_P2_EQUA_ACCQ1 0xf27101ff + +/*P2_EQUAI2*/ +#define RSTV0910_P2_EQUAI2 0xf272 +#define FSTV0910_P2_EQUA_ACCI2 0xf27201ff + +/*P2_EQUAQ2*/ +#define RSTV0910_P2_EQUAQ2 0xf273 +#define FSTV0910_P2_EQUA_ACCQ2 0xf27301ff + +/*P2_EQUAI3*/ +#define RSTV0910_P2_EQUAI3 0xf274 +#define FSTV0910_P2_EQUA_ACCI3 0xf27401ff + +/*P2_EQUAQ3*/ +#define RSTV0910_P2_EQUAQ3 0xf275 +#define FSTV0910_P2_EQUA_ACCQ3 0xf27501ff + +/*P2_EQUAI4*/ +#define RSTV0910_P2_EQUAI4 0xf276 +#define FSTV0910_P2_EQUA_ACCI4 0xf27601ff + +/*P2_EQUAQ4*/ +#define RSTV0910_P2_EQUAQ4 0xf277 +#define FSTV0910_P2_EQUA_ACCQ4 0xf27701ff + +/*P2_EQUAI5*/ +#define RSTV0910_P2_EQUAI5 0xf278 +#define FSTV0910_P2_EQUA_ACCI5 0xf27801ff + +/*P2_EQUAQ5*/ +#define RSTV0910_P2_EQUAQ5 0xf279 +#define FSTV0910_P2_EQUA_ACCQ5 0xf27901ff + +/*P2_EQUAI6*/ +#define RSTV0910_P2_EQUAI6 0xf27a +#define FSTV0910_P2_EQUA_ACCI6 0xf27a01ff + +/*P2_EQUAQ6*/ +#define RSTV0910_P2_EQUAQ6 0xf27b +#define FSTV0910_P2_EQUA_ACCQ6 0xf27b01ff + +/*P2_EQUAI7*/ +#define RSTV0910_P2_EQUAI7 0xf27c +#define FSTV0910_P2_EQUA_ACCI7 0xf27c01ff + +/*P2_EQUAQ7*/ +#define RSTV0910_P2_EQUAQ7 0xf27d +#define FSTV0910_P2_EQUA_ACCQ7 0xf27d01ff + +/*P2_EQUAI8*/ +#define RSTV0910_P2_EQUAI8 0xf27e +#define FSTV0910_P2_EQUA_ACCI8 0xf27e01ff + +/*P2_EQUAQ8*/ +#define RSTV0910_P2_EQUAQ8 0xf27f +#define FSTV0910_P2_EQUA_ACCQ8 0xf27f01ff + +/*P2_NNOSDATAT1*/ +#define RSTV0910_P2_NNOSDATAT1 0xf280 +#define FSTV0910_P2_NOSDATAT_NORMED1 0xf28000ff + +/*P2_NNOSDATAT0*/ +#define RSTV0910_P2_NNOSDATAT0 0xf281 +#define FSTV0910_P2_NOSDATAT_NORMED0 0xf28100ff + +/*P2_NNOSDATA1*/ +#define RSTV0910_P2_NNOSDATA1 0xf282 +#define FSTV0910_P2_NOSDATA_NORMED1 0xf28200ff + +/*P2_NNOSDATA0*/ +#define RSTV0910_P2_NNOSDATA0 0xf283 +#define FSTV0910_P2_NOSDATA_NORMED0 0xf28300ff + +/*P2_NNOSPLHT1*/ +#define RSTV0910_P2_NNOSPLHT1 0xf284 +#define FSTV0910_P2_NOSPLHT_NORMED1 0xf28400ff + +/*P2_NNOSPLHT0*/ +#define RSTV0910_P2_NNOSPLHT0 0xf285 +#define FSTV0910_P2_NOSPLHT_NORMED0 0xf28500ff + +/*P2_NNOSPLH1*/ +#define RSTV0910_P2_NNOSPLH1 0xf286 +#define FSTV0910_P2_NOSPLH_NORMED1 0xf28600ff + +/*P2_NNOSPLH0*/ +#define RSTV0910_P2_NNOSPLH0 0xf287 +#define FSTV0910_P2_NOSPLH_NORMED0 0xf28700ff + +/*P2_NOSDATAT1*/ +#define RSTV0910_P2_NOSDATAT1 0xf288 +#define FSTV0910_P2_NOSDATAT_UNNORMED1 0xf28800ff + +/*P2_NOSDATAT0*/ +#define RSTV0910_P2_NOSDATAT0 0xf289 +#define FSTV0910_P2_NOSDATAT_UNNORMED0 0xf28900ff + +/*P2_NNOSFRAME1*/ +#define RSTV0910_P2_NNOSFRAME1 0xf28a +#define FSTV0910_P2_NOSFRAME_NORMED1 0xf28a00ff + +/*P2_NNOSFRAME0*/ +#define RSTV0910_P2_NNOSFRAME0 0xf28b +#define FSTV0910_P2_NOSFRAME_NORMED0 0xf28b00ff + +/*P2_NNOSRAD1*/ +#define RSTV0910_P2_NNOSRAD1 0xf28c +#define FSTV0910_P2_NOSRADIAL_NORMED1 0xf28c00ff + +/*P2_NNOSRAD0*/ +#define RSTV0910_P2_NNOSRAD0 0xf28d +#define FSTV0910_P2_NOSRADIAL_NORMED0 0xf28d00ff + +/*P2_NOSCFGF1*/ +#define RSTV0910_P2_NOSCFGF1 0xf28e +#define FSTV0910_P2_LOWNOISE_MESURE 0xf28e0080 +#define FSTV0910_P2_NOS_DELFRAME 0xf28e0040 +#define FSTV0910_P2_NOSDATA_MODE 0xf28e0030 +#define FSTV0910_P2_FRAMESEL_TYPESEL 0xf28e000c +#define FSTV0910_P2_FRAMESEL_TYPE 0xf28e0003 + +/*P2_CAR2CFG*/ +#define RSTV0910_P2_CAR2CFG 0xf290 +#define FSTV0910_P2_DESCRAMB_OFF 0xf2900080 +#define FSTV0910_P2_EN_PHNOSRAM 0xf2900020 +#define FSTV0910_P2_STOP_CFR2UPDATE 0xf2900010 +#define FSTV0910_P2_STOP_NCO2UPDATE 0xf2900008 +#define FSTV0910_P2_ROTA2ON 0xf2900004 +#define FSTV0910_P2_PH_DET_ALGO2 0xf2900003 + +/*P2_CFR2CFR1*/ +#define RSTV0910_P2_CFR2CFR1 0xf291 +#define FSTV0910_P2_CFR2_S2CONTROL 0xf29100c0 +#define FSTV0910_P2_EN_S2CAR2CENTER 0xf2910020 +#define FSTV0910_P2_BCHERRCFR2_MODE 0xf2910018 +#define FSTV0910_P2_CFR2TOCFR1_BETA 0xf2910007 + +/*P2_CAR3CFG*/ +#define RSTV0910_P2_CAR3CFG 0xf292 +#define FSTV0910_P2_CARRIER23_MODE 0xf29200c0 +#define FSTV0910_P2_CAR3INTERM_DVBS1 0xf2920020 +#define FSTV0910_P2_ABAMPLIF_MODE 0xf2920018 +#define FSTV0910_P2_CARRIER3_ALPHA3DL 0xf2920007 + +/*P2_CFR22*/ +#define RSTV0910_P2_CFR22 0xf293 +#define FSTV0910_P2_CAR2_FREQ2 0xf29301ff + +/*P2_CFR21*/ +#define RSTV0910_P2_CFR21 0xf294 +#define FSTV0910_P2_CAR2_FREQ1 0xf29400ff + +/*P2_CFR20*/ +#define RSTV0910_P2_CFR20 0xf295 +#define FSTV0910_P2_CAR2_FREQ0 0xf29500ff + +/*P2_ACLC2S2Q*/ +#define RSTV0910_P2_ACLC2S2Q 0xf297 +#define FSTV0910_P2_ENAB_SPSKSYMB 0xf2970080 +#define FSTV0910_P2_CAR2S2_QANOSAUTO 0xf2970040 +#define FSTV0910_P2_CAR2S2_Q_ALPH_M 0xf2970030 +#define FSTV0910_P2_CAR2S2_Q_ALPH_E 0xf297000f + +/*P2_ACLC2S28*/ +#define RSTV0910_P2_ACLC2S28 0xf298 +#define FSTV0910_P2_OLDI3Q_MODE 0xf2980080 +#define FSTV0910_P2_CAR2S2_8ANOSAUTO 0xf2980040 +#define FSTV0910_P2_CAR2S2_8_ALPH_M 0xf2980030 +#define FSTV0910_P2_CAR2S2_8_ALPH_E 0xf298000f + +/*P2_ACLC2S216A*/ +#define RSTV0910_P2_ACLC2S216A 0xf299 +#define FSTV0910_P2_CAR2S2_16ANOSAUTO 0xf2990040 +#define FSTV0910_P2_CAR2S2_16A_ALPH_M 0xf2990030 +#define FSTV0910_P2_CAR2S2_16A_ALPH_E 0xf299000f + +/*P2_ACLC2S232A*/ +#define RSTV0910_P2_ACLC2S232A 0xf29a +#define FSTV0910_P2_CAR2S2_32ANOSUATO 0xf29a0040 +#define FSTV0910_P2_CAR2S2_32A_ALPH_M 0xf29a0030 +#define FSTV0910_P2_CAR2S2_32A_ALPH_E 0xf29a000f + +/*P2_BCLC2S2Q*/ +#define RSTV0910_P2_BCLC2S2Q 0xf29c +#define FSTV0910_P2_DVBS2S2Q_NIP 0xf29c0080 +#define FSTV0910_P2_CAR2S2_QBNOSAUTO 0xf29c0040 +#define FSTV0910_P2_CAR2S2_Q_BETA_M 0xf29c0030 +#define FSTV0910_P2_CAR2S2_Q_BETA_E 0xf29c000f + +/*P2_BCLC2S28*/ +#define RSTV0910_P2_BCLC2S28 0xf29d +#define FSTV0910_P2_DVBS2S28_NIP 0xf29d0080 +#define FSTV0910_P2_CAR2S2_8BNOSAUTO 0xf29d0040 +#define FSTV0910_P2_CAR2S2_8_BETA_M 0xf29d0030 +#define FSTV0910_P2_CAR2S2_8_BETA_E 0xf29d000f + +/*P2_PLROOT2*/ +#define RSTV0910_P2_PLROOT2 0xf2ac +#define FSTV0910_P2_PLHAUTO_DISPLH 0xf2ac0040 +#define FSTV0910_P2_PLHAUTO_FASTMODE 0xf2ac0020 +#define FSTV0910_P2_PLHAUTO_ENABLE 0xf2ac0010 +#define FSTV0910_P2_PLSCRAMB_MODE 0xf2ac000c +#define FSTV0910_P2_PLSCRAMB_ROOT2 0xf2ac0003 + +/*P2_PLROOT1*/ +#define RSTV0910_P2_PLROOT1 0xf2ad +#define FSTV0910_P2_PLSCRAMB_ROOT1 0xf2ad00ff + +/*P2_PLROOT0*/ +#define RSTV0910_P2_PLROOT0 0xf2ae +#define FSTV0910_P2_PLSCRAMB_ROOT0 0xf2ae00ff + +/*P2_MODCODLST7*/ +#define RSTV0910_P2_MODCODLST7 0xf2b7 +#define FSTV0910_P2_MODCOD_NNOSFILTER 0xf2b70080 +#define FSTV0910_P2_MODCODLST_NOSTYPE 0xf2b70040 +#define FSTV0910_P2_DIS_8PSK_9_10 0xf2b70030 +#define FSTV0910_P2_DIS_8P_8_9 0xf2b7000f + +/*P2_MODCODLST8*/ +#define RSTV0910_P2_MODCODLST8 0xf2b8 +#define FSTV0910_P2_DIS_8P_5_6 0xf2b800f0 +#define FSTV0910_P2_DIS_8P_3_4 0xf2b8000f + +/*P2_MODCODLST9*/ +#define RSTV0910_P2_MODCODLST9 0xf2b9 +#define FSTV0910_P2_DIS_8P_2_3 0xf2b900f0 +#define FSTV0910_P2_DIS_8P_3_5 0xf2b9000f + +/*P2_MODCODLSTA*/ +#define RSTV0910_P2_MODCODLSTA 0xf2ba +#define FSTV0910_P2_NOSFILTER_LIMITE 0xf2ba0080 +#define FSTV0910_P2_NOSFILTER_MODE 0xf2ba0040 +#define FSTV0910_P2_DIS_QPSK_9_10 0xf2ba0030 +#define FSTV0910_P2_DIS_QP_8_9 0xf2ba000f + +/*P2_MODCODLSTB*/ +#define RSTV0910_P2_MODCODLSTB 0xf2bb +#define FSTV0910_P2_DIS_QP_5_6 0xf2bb00f0 +#define FSTV0910_P2_DIS_QP_4_5 0xf2bb000f + +/*P2_MODCODLSTC*/ +#define RSTV0910_P2_MODCODLSTC 0xf2bc +#define FSTV0910_P2_DIS_QP_3_4 0xf2bc00f0 +#define FSTV0910_P2_DIS_QP_2_3 0xf2bc000f + +/*P2_MODCODLSTD*/ +#define RSTV0910_P2_MODCODLSTD 0xf2bd +#define FSTV0910_P2_DIS_QPSK_3_5 0xf2bd00f0 +#define FSTV0910_P2_DIS_QPSK_1_2 0xf2bd000f + +/*P2_GAUSSR0*/ +#define RSTV0910_P2_GAUSSR0 0xf2c0 +#define FSTV0910_P2_EN_CCIMODE 0xf2c00080 +#define FSTV0910_P2_R0_GAUSSIEN 0xf2c0007f + +/*P2_CCIR0*/ +#define RSTV0910_P2_CCIR0 0xf2c1 +#define FSTV0910_P2_CCIDETECT_PLHONLY 0xf2c10080 +#define FSTV0910_P2_R0_CCI 0xf2c1007f + +/*P2_CCIQUANT*/ +#define RSTV0910_P2_CCIQUANT 0xf2c2 +#define FSTV0910_P2_CCI_BETA 0xf2c200e0 +#define FSTV0910_P2_CCI_QUANT 0xf2c2001f + +/*P2_CCITHRES*/ +#define RSTV0910_P2_CCITHRES 0xf2c3 +#define FSTV0910_P2_CCI_THRESHOLD 0xf2c300ff + +/*P2_CCIACC*/ +#define RSTV0910_P2_CCIACC 0xf2c4 +#define FSTV0910_P2_CCI_VALUE 0xf2c400ff + +/*P2_DSTATUS4*/ +#define RSTV0910_P2_DSTATUS4 0xf2c5 +#define FSTV0910_P2_RAINFADE_DETECT 0xf2c50080 +#define FSTV0910_P2_NOTHRES2_FAIL 0xf2c50040 +#define FSTV0910_P2_NOTHRES1_FAIL 0xf2c50020 +#define FSTV0910_P2_PILOT_FAILDETECT 0xf2c50010 +#define FSTV0910_P2_HIER_DETECT 0xf2c50008 +#define FSTV0910_P2_DMDPROG_ERROR 0xf2c50004 +#define FSTV0910_P2_CSTENV_DETECT 0xf2c50002 +#define FSTV0910_P2_DETECTION_TRIAX 0xf2c50001 + +/*P2_DMDRESCFG*/ +#define RSTV0910_P2_DMDRESCFG 0xf2c6 +#define FSTV0910_P2_DMDRES_RESET 0xf2c60080 +#define FSTV0910_P2_DMDRES_NOISESQR 0xf2c60010 +#define FSTV0910_P2_DMDRES_STRALL 0xf2c60008 +#define FSTV0910_P2_DMDRES_NEWONLY 0xf2c60004 +#define FSTV0910_P2_DMDRES_NOSTORE 0xf2c60002 +#define FSTV0910_P2_DMDRES_AGC2MEM 0xf2c60001 + +/*P2_DMDRESADR*/ +#define RSTV0910_P2_DMDRESADR 0xf2c7 +#define FSTV0910_P2_SUSP_PREDCANAL 0xf2c70080 +#define FSTV0910_P2_DMDRES_VALIDCFR 0xf2c70040 +#define FSTV0910_P2_DMDRES_MEMFULL 0xf2c70030 +#define FSTV0910_P2_DMDRES_RESNBR 0xf2c7000f + +/*P2_DMDRESDATA7*/ +#define RSTV0910_P2_DMDRESDATA7 0xf2c8 +#define FSTV0910_P2_DMDRES_DATA7 0xf2c800ff + +/*P2_DMDRESDATA6*/ +#define RSTV0910_P2_DMDRESDATA6 0xf2c9 +#define FSTV0910_P2_DMDRES_DATA6 0xf2c900ff + +/*P2_DMDRESDATA5*/ +#define RSTV0910_P2_DMDRESDATA5 0xf2ca +#define FSTV0910_P2_DMDRES_DATA5 0xf2ca00ff + +/*P2_DMDRESDATA4*/ +#define RSTV0910_P2_DMDRESDATA4 0xf2cb +#define FSTV0910_P2_DMDRES_DATA4 0xf2cb00ff + +/*P2_DMDRESDATA3*/ +#define RSTV0910_P2_DMDRESDATA3 0xf2cc +#define FSTV0910_P2_DMDRES_DATA3 0xf2cc00ff + +/*P2_DMDRESDATA2*/ +#define RSTV0910_P2_DMDRESDATA2 0xf2cd +#define FSTV0910_P2_DMDRES_DATA2 0xf2cd00ff + +/*P2_DMDRESDATA1*/ +#define RSTV0910_P2_DMDRESDATA1 0xf2ce +#define FSTV0910_P2_DMDRES_DATA1 0xf2ce00ff + +/*P2_DMDRESDATA0*/ +#define RSTV0910_P2_DMDRESDATA0 0xf2cf +#define FSTV0910_P2_DMDRES_DATA0 0xf2cf00ff + +/*P2_FFEI1*/ +#define RSTV0910_P2_FFEI1 0xf2d0 +#define FSTV0910_P2_FFE_ACCI1 0xf2d001ff + +/*P2_FFEQ1*/ +#define RSTV0910_P2_FFEQ1 0xf2d1 +#define FSTV0910_P2_FFE_ACCQ1 0xf2d101ff + +/*P2_FFEI2*/ +#define RSTV0910_P2_FFEI2 0xf2d2 +#define FSTV0910_P2_FFE_ACCI2 0xf2d201ff + +/*P2_FFEQ2*/ +#define RSTV0910_P2_FFEQ2 0xf2d3 +#define FSTV0910_P2_FFE_ACCQ2 0xf2d301ff + +/*P2_FFEI3*/ +#define RSTV0910_P2_FFEI3 0xf2d4 +#define FSTV0910_P2_FFE_ACCI3 0xf2d401ff + +/*P2_FFEQ3*/ +#define RSTV0910_P2_FFEQ3 0xf2d5 +#define FSTV0910_P2_FFE_ACCQ3 0xf2d501ff + +/*P2_FFEI4*/ +#define RSTV0910_P2_FFEI4 0xf2d6 +#define FSTV0910_P2_FFE_ACCI4 0xf2d601ff + +/*P2_FFEQ4*/ +#define RSTV0910_P2_FFEQ4 0xf2d7 +#define FSTV0910_P2_FFE_ACCQ4 0xf2d701ff + +/*P2_FFECFG*/ +#define RSTV0910_P2_FFECFG 0xf2d8 +#define FSTV0910_P2_EQUALFFE_ON 0xf2d80040 +#define FSTV0910_P2_EQUAL_USEDSYMB 0xf2d80030 +#define FSTV0910_P2_MU_EQUALFFE 0xf2d80007 + +/*P2_TNRCFG2*/ +#define RSTV0910_P2_TNRCFG2 0xf2e1 +#define FSTV0910_P2_TUN_IQSWAP 0xf2e10080 +#define FSTV0910_P2_STB6110_STEP2MHZ 0xf2e10040 +#define FSTV0910_P2_STB6120_DBLI2C 0xf2e10020 +#define FSTV0910_P2_TUNER_WIDEBAND 0xf2e10010 +#define FSTV0910_P2_TUNER_OBSPAGE 0xf2e10008 +#define FSTV0910_P2_DIS_BWCALC 0xf2e10004 +#define FSTV0910_P2_SHORT_WAITSTATES 0xf2e10002 +#define FSTV0910_P2_DIS_2BWAGC1 0xf2e10001 + +/*P2_SMAPCOEF7*/ +#define RSTV0910_P2_SMAPCOEF7 0xf300 +#define FSTV0910_P2_DIS_QSCALE 0xf3000080 +#define FSTV0910_P2_SMAPCOEF_Q_LLR12 0xf300017f + +/*P2_SMAPCOEF6*/ +#define RSTV0910_P2_SMAPCOEF6 0xf301 +#define FSTV0910_P2_DIS_AGC2SCALE 0xf3010080 +#define FSTV0910_P2_DIS_16IQMULT 0xf3010040 +#define FSTV0910_P2_OLD_16APSK47 0xf3010020 +#define FSTV0910_P2_OLD_16APSK12 0xf3010010 +#define FSTV0910_P2_DIS_NEWSCALE 0xf3010008 +#define FSTV0910_P2_ADJ_8PSKLLR1 0xf3010004 +#define FSTV0910_P2_OLD_8PSKLLR1 0xf3010002 +#define FSTV0910_P2_DIS_AB8PSK 0xf3010001 + +/*P2_SMAPCOEF5*/ +#define RSTV0910_P2_SMAPCOEF5 0xf302 +#define FSTV0910_P2_DIS_8SCALE 0xf3020080 +#define FSTV0910_P2_SMAPCOEF_8P_LLR23 0xf302017f + +/*P2_NOSTHRES1*/ +#define RSTV0910_P2_NOSTHRES1 0xf309 +#define FSTV0910_P2_NOS_THRESHOLD1 0xf30900ff + +/*P2_NOSTHRES2*/ +#define RSTV0910_P2_NOSTHRES2 0xf30a +#define FSTV0910_P2_NOS_THRESHOLD2 0xf30a00ff + +/*P2_NOSDIFF1*/ +#define RSTV0910_P2_NOSDIFF1 0xf30b +#define FSTV0910_P2_NOSTHRES1_DIFF 0xf30b00ff + +/*P2_RAINFADE*/ +#define RSTV0910_P2_RAINFADE 0xf30c +#define FSTV0910_P2_NOSTHRES_DATAT 0xf30c0080 +#define FSTV0910_P2_RAINFADE_CNLIMIT 0xf30c0070 +#define FSTV0910_P2_RAINFADE_TIMEOUT 0xf30c0007 + +/*P2_NOSRAMCFG*/ +#define RSTV0910_P2_NOSRAMCFG 0xf30d +#define FSTV0910_P2_NOSRAM_DVBS2DATA 0xf30d0080 +#define FSTV0910_P2_NOSRAM_QUADRAT 0xf30d0040 +#define FSTV0910_P2_NOSRAM_ACTIVATION 0xf30d0030 +#define FSTV0910_P2_NOSRAM_CNRONLY 0xf30d0008 +#define FSTV0910_P2_NOSRAM_LGNCNR1 0xf30d0007 + +/*P2_NOSRAMPOS*/ +#define RSTV0910_P2_NOSRAMPOS 0xf30e +#define FSTV0910_P2_NOSRAM_LGNCNR0 0xf30e00f0 +#define FSTV0910_P2_NOSRAM_VALIDE 0xf30e0004 +#define FSTV0910_P2_NOSRAM_CNRVAL1 0xf30e0003 + +/*P2_NOSRAMVAL*/ +#define RSTV0910_P2_NOSRAMVAL 0xf30f +#define FSTV0910_P2_NOSRAM_CNRVAL0 0xf30f00ff + +/*P2_DMDPLHSTAT*/ +#define RSTV0910_P2_DMDPLHSTAT 0xf320 +#define FSTV0910_P2_PLH_STATISTIC 0xf32000ff + +/*P2_LOCKTIME3*/ +#define RSTV0910_P2_LOCKTIME3 0xf322 +#define FSTV0910_P2_DEMOD_LOCKTIME3 0xf32200ff + +/*P2_LOCKTIME2*/ +#define RSTV0910_P2_LOCKTIME2 0xf323 +#define FSTV0910_P2_DEMOD_LOCKTIME2 0xf32300ff + +/*P2_LOCKTIME1*/ +#define RSTV0910_P2_LOCKTIME1 0xf324 +#define FSTV0910_P2_DEMOD_LOCKTIME1 0xf32400ff + +/*P2_LOCKTIME0*/ +#define RSTV0910_P2_LOCKTIME0 0xf325 +#define FSTV0910_P2_DEMOD_LOCKTIME0 0xf32500ff + +/*P2_VITSCALE*/ +#define RSTV0910_P2_VITSCALE 0xf332 +#define FSTV0910_P2_NVTH_NOSRANGE 0xf3320080 +#define FSTV0910_P2_VERROR_MAXMODE 0xf3320040 +#define FSTV0910_P2_KDIV_MODE 0xf3320030 +#define FSTV0910_P2_NSLOWSN_LOCKED 0xf3320008 +#define FSTV0910_P2_DELOCK_PRFLOSS 0xf3320004 +#define FSTV0910_P2_DIS_RSFLOCK 0xf3320002 + +/*P2_FECM*/ +#define RSTV0910_P2_FECM 0xf333 +#define FSTV0910_P2_DSS_DVB 0xf3330080 +#define FSTV0910_P2_DEMOD_BYPASS 0xf3330040 +#define FSTV0910_P2_CMP_SLOWMODE 0xf3330020 +#define FSTV0910_P2_DSS_SRCH 0xf3330010 +#define FSTV0910_P2_DIFF_MODEVIT 0xf3330004 +#define FSTV0910_P2_SYNCVIT 0xf3330002 +#define FSTV0910_P2_IQINV 0xf3330001 + +/*P2_VTH12*/ +#define RSTV0910_P2_VTH12 0xf334 +#define FSTV0910_P2_VTH12 0xf33400ff + +/*P2_VTH23*/ +#define RSTV0910_P2_VTH23 0xf335 +#define FSTV0910_P2_VTH23 0xf33500ff + +/*P2_VTH34*/ +#define RSTV0910_P2_VTH34 0xf336 +#define FSTV0910_P2_VTH34 0xf33600ff + +/*P2_VTH56*/ +#define RSTV0910_P2_VTH56 0xf337 +#define FSTV0910_P2_VTH56 0xf33700ff + +/*P2_VTH67*/ +#define RSTV0910_P2_VTH67 0xf338 +#define FSTV0910_P2_VTH67 0xf33800ff + +/*P2_VTH78*/ +#define RSTV0910_P2_VTH78 0xf339 +#define FSTV0910_P2_VTH78 0xf33900ff + +/*P2_VITCURPUN*/ +#define RSTV0910_P2_VITCURPUN 0xf33a +#define FSTV0910_P2_CYCLESLIP_VIT 0xf33a0080 +#define FSTV0910_P2_VIT_ROTA180 0xf33a0040 +#define FSTV0910_P2_VIT_ROTA90 0xf33a0020 +#define FSTV0910_P2_VIT_CURPUN 0xf33a001f + +/*P2_VERROR*/ +#define RSTV0910_P2_VERROR 0xf33b +#define FSTV0910_P2_REGERR_VIT 0xf33b00ff + +/*P2_PRVIT*/ +#define RSTV0910_P2_PRVIT 0xf33c +#define FSTV0910_P2_DIS_VTHLOCK 0xf33c0040 +#define FSTV0910_P2_E7_8VIT 0xf33c0020 +#define FSTV0910_P2_E6_7VIT 0xf33c0010 +#define FSTV0910_P2_E5_6VIT 0xf33c0008 +#define FSTV0910_P2_E3_4VIT 0xf33c0004 +#define FSTV0910_P2_E2_3VIT 0xf33c0002 +#define FSTV0910_P2_E1_2VIT 0xf33c0001 + +/*P2_VAVSRVIT*/ +#define RSTV0910_P2_VAVSRVIT 0xf33d +#define FSTV0910_P2_AMVIT 0xf33d0080 +#define FSTV0910_P2_FROZENVIT 0xf33d0040 +#define FSTV0910_P2_SNVIT 0xf33d0030 +#define FSTV0910_P2_TOVVIT 0xf33d000c +#define FSTV0910_P2_HYPVIT 0xf33d0003 + +/*P2_VSTATUSVIT*/ +#define RSTV0910_P2_VSTATUSVIT 0xf33e +#define FSTV0910_P2_VITERBI_ON 0xf33e0080 +#define FSTV0910_P2_END_LOOPVIT 0xf33e0040 +#define FSTV0910_P2_VITERBI_DEPRF 0xf33e0020 +#define FSTV0910_P2_PRFVIT 0xf33e0010 +#define FSTV0910_P2_LOCKEDVIT 0xf33e0008 +#define FSTV0910_P2_VITERBI_DELOCK 0xf33e0004 +#define FSTV0910_P2_VIT_DEMODSEL 0xf33e0002 +#define FSTV0910_P2_VITERBI_COMPOUT 0xf33e0001 + +/*P2_VTHINUSE*/ +#define RSTV0910_P2_VTHINUSE 0xf33f +#define FSTV0910_P2_VIT_INUSE 0xf33f00ff + +/*P2_KDIV12*/ +#define RSTV0910_P2_KDIV12 0xf340 +#define FSTV0910_P2_KDIV12_MANUAL 0xf3400080 +#define FSTV0910_P2_K_DIVIDER_12 0xf340007f + +/*P2_KDIV23*/ +#define RSTV0910_P2_KDIV23 0xf341 +#define FSTV0910_P2_KDIV23_MANUAL 0xf3410080 +#define FSTV0910_P2_K_DIVIDER_23 0xf341007f + +/*P2_KDIV34*/ +#define RSTV0910_P2_KDIV34 0xf342 +#define FSTV0910_P2_KDIV34_MANUAL 0xf3420080 +#define FSTV0910_P2_K_DIVIDER_34 0xf342007f + +/*P2_KDIV56*/ +#define RSTV0910_P2_KDIV56 0xf343 +#define FSTV0910_P2_KDIV56_MANUAL 0xf3430080 +#define FSTV0910_P2_K_DIVIDER_56 0xf343007f + +/*P2_KDIV67*/ +#define RSTV0910_P2_KDIV67 0xf344 +#define FSTV0910_P2_KDIV67_MANUAL 0xf3440080 +#define FSTV0910_P2_K_DIVIDER_67 0xf344007f + +/*P2_KDIV78*/ +#define RSTV0910_P2_KDIV78 0xf345 +#define FSTV0910_P2_KDIV78_MANUAL 0xf3450080 +#define FSTV0910_P2_K_DIVIDER_78 0xf345007f + +/*P2_PDELCTRL0*/ +#define RSTV0910_P2_PDELCTRL0 0xf34f +#define FSTV0910_P2_ISIOBS_MODE 0xf34f0030 +#define FSTV0910_P2_PDELDIS_BITWISE 0xf34f0004 + +/*P2_PDELCTRL1*/ +#define RSTV0910_P2_PDELCTRL1 0xf350 +#define FSTV0910_P2_INV_MISMASK 0xf3500080 +#define FSTV0910_P2_FORCE_ACCEPTED 0xf3500040 +#define FSTV0910_P2_FILTER_EN 0xf3500020 +#define FSTV0910_P2_FORCE_PKTDELINUSE 0xf3500010 +#define FSTV0910_P2_HYSTEN 0xf3500008 +#define FSTV0910_P2_HYSTSWRST 0xf3500004 +#define FSTV0910_P2_EN_MIS00 0xf3500002 +#define FSTV0910_P2_ALGOSWRST 0xf3500001 + +/*P2_PDELCTRL2*/ +#define RSTV0910_P2_PDELCTRL2 0xf351 +#define FSTV0910_P2_FORCE_CONTINUOUS 0xf3510080 +#define FSTV0910_P2_RESET_UPKO_COUNT 0xf3510040 +#define FSTV0910_P2_USER_PKTDELIN_NB 0xf3510020 +#define FSTV0910_P2_DATA_UNBBSCRAMBLED 0xf3510008 +#define FSTV0910_P2_FORCE_LONGPKT 0xf3510004 +#define FSTV0910_P2_FRAME_MODE 0xf3510002 + +/*P2_HYSTTHRESH*/ +#define RSTV0910_P2_HYSTTHRESH 0xf354 +#define FSTV0910_P2_DELIN_LOCKTHRES 0xf35400f0 +#define FSTV0910_P2_DELIN_UNLOCKTHRES 0xf354000f + +/*P2_ISIENTRY*/ +#define RSTV0910_P2_ISIENTRY 0xf35e +#define FSTV0910_P2_ISI_ENTRY 0xf35e00ff + +/*P2_ISIBITENA*/ +#define RSTV0910_P2_ISIBITENA 0xf35f +#define FSTV0910_P2_ISI_BIT_EN 0xf35f00ff + +/*P2_MATSTR1*/ +#define RSTV0910_P2_MATSTR1 0xf360 +#define FSTV0910_P2_MATYPE_CURRENT1 0xf36000ff + +/*P2_MATSTR0*/ +#define RSTV0910_P2_MATSTR0 0xf361 +#define FSTV0910_P2_MATYPE_CURRENT0 0xf36100ff + +/*P2_UPLSTR1*/ +#define RSTV0910_P2_UPLSTR1 0xf362 +#define FSTV0910_P2_UPL_CURRENT1 0xf36200ff + +/*P2_UPLSTR0*/ +#define RSTV0910_P2_UPLSTR0 0xf363 +#define FSTV0910_P2_UPL_CURRENT0 0xf36300ff + +/*P2_DFLSTR1*/ +#define RSTV0910_P2_DFLSTR1 0xf364 +#define FSTV0910_P2_DFL_CURRENT1 0xf36400ff + +/*P2_DFLSTR0*/ +#define RSTV0910_P2_DFLSTR0 0xf365 +#define FSTV0910_P2_DFL_CURRENT0 0xf36500ff + +/*P2_SYNCSTR*/ +#define RSTV0910_P2_SYNCSTR 0xf366 +#define FSTV0910_P2_SYNC_CURRENT 0xf36600ff + +/*P2_SYNCDSTR1*/ +#define RSTV0910_P2_SYNCDSTR1 0xf367 +#define FSTV0910_P2_SYNCD_CURRENT1 0xf36700ff + +/*P2_SYNCDSTR0*/ +#define RSTV0910_P2_SYNCDSTR0 0xf368 +#define FSTV0910_P2_SYNCD_CURRENT0 0xf36800ff + +/*P2_PDELSTATUS1*/ +#define RSTV0910_P2_PDELSTATUS1 0xf369 +#define FSTV0910_P2_PKTDELIN_DELOCK 0xf3690080 +#define FSTV0910_P2_SYNCDUPDFL_BADDFL 0xf3690040 +#define FSTV0910_P2_CONTINUOUS_STREAM 0xf3690020 +#define FSTV0910_P2_UNACCEPTED_STREAM 0xf3690010 +#define FSTV0910_P2_BCH_ERROR_FLAG 0xf3690008 +#define FSTV0910_P2_BBHCRCKO 0xf3690004 +#define FSTV0910_P2_PKTDELIN_LOCK 0xf3690002 +#define FSTV0910_P2_FIRST_LOCK 0xf3690001 + +/*P2_PDELSTATUS2*/ +#define RSTV0910_P2_PDELSTATUS2 0xf36a +#define FSTV0910_P2_PKTDEL_DEMODSEL 0xf36a0080 +#define FSTV0910_P2_FRAME_MODCOD 0xf36a007c +#define FSTV0910_P2_FRAME_TYPE 0xf36a0003 + +/*P2_BBFCRCKO1*/ +#define RSTV0910_P2_BBFCRCKO1 0xf36b +#define FSTV0910_P2_BBHCRC_KOCNT1 0xf36b00ff + +/*P2_BBFCRCKO0*/ +#define RSTV0910_P2_BBFCRCKO0 0xf36c +#define FSTV0910_P2_BBHCRC_KOCNT0 0xf36c00ff + +/*P2_UPCRCKO1*/ +#define RSTV0910_P2_UPCRCKO1 0xf36d +#define FSTV0910_P2_PKTCRC_KOCNT1 0xf36d00ff + +/*P2_UPCRCKO0*/ +#define RSTV0910_P2_UPCRCKO0 0xf36e +#define FSTV0910_P2_PKTCRC_KOCNT0 0xf36e00ff + +/*P2_PDELCTRL3*/ +#define RSTV0910_P2_PDELCTRL3 0xf36f +#define FSTV0910_P2_PKTDEL_CONTFAIL 0xf36f0080 +#define FSTV0910_P2_PKTDEL_ENLONGPKT 0xf36f0040 +#define FSTV0910_P2_NOFIFO_BCHERR 0xf36f0020 +#define FSTV0910_P2_PKTDELIN_DELACMERR 0xf36f0010 +#define FSTV0910_P2_SATURATE_BBPKTKO 0xf36f0004 +#define FSTV0910_P2_PKTDEL_BCHERRCONT 0xf36f0002 +#define FSTV0910_P2_ETHERNET_DISFCS 0xf36f0001 + +/*P2_TSSTATEM*/ +#define RSTV0910_P2_TSSTATEM 0xf370 +#define FSTV0910_P2_TSDIL_ON 0xf3700080 +#define FSTV0910_P2_TSSKIPRS_ON 0xf3700040 +#define FSTV0910_P2_TSRS_ON 0xf3700020 +#define FSTV0910_P2_TSDESCRAMB_ON 0xf3700010 +#define FSTV0910_P2_TSFRAME_MODE 0xf3700008 +#define FSTV0910_P2_TS_DISABLE 0xf3700004 +#define FSTV0910_P2_TSACM_MODE 0xf3700002 +#define FSTV0910_P2_TSOUT_NOSYNC 0xf3700001 + +/*P2_TSCFGH*/ +#define RSTV0910_P2_TSCFGH 0xf372 +#define FSTV0910_P2_TSFIFO_DVBCI 0xf3720080 +#define FSTV0910_P2_TSFIFO_SERIAL 0xf3720040 +#define FSTV0910_P2_TSFIFO_TEIUPDATE 0xf3720020 +#define FSTV0910_P2_TSFIFO_DUTY50 0xf3720010 +#define FSTV0910_P2_TSFIFO_HSGNLOUT 0xf3720008 +#define FSTV0910_P2_TSFIFO_ERRMODE 0xf3720006 +#define FSTV0910_P2_RST_HWARE 0xf3720001 + +/*P2_TSCFGM*/ +#define RSTV0910_P2_TSCFGM 0xf373 +#define FSTV0910_P2_TSFIFO_MANSPEED 0xf37300c0 +#define FSTV0910_P2_TSFIFO_PERMDATA 0xf3730020 +#define FSTV0910_P2_TSFIFO_NONEWSGNL 0xf3730010 +#define FSTV0910_P2_NPD_SPECDVBS2 0xf3730004 +#define FSTV0910_P2_TSFIFO_DPUNACTIVE 0xf3730002 +#define FSTV0910_P2_TSFIFO_INVDATA 0xf3730001 + +/*P2_TSCFGL*/ +#define RSTV0910_P2_TSCFGL 0xf374 +#define FSTV0910_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 +#define FSTV0910_P2_BCHERROR_MODE 0xf3740030 +#define FSTV0910_P2_TSFIFO_NSGNL2DATA 0xf3740008 +#define FSTV0910_P2_TSFIFO_EMBINDVB 0xf3740004 +#define FSTV0910_P2_TSFIFO_BITSPEED 0xf3740003 + +/*P2_TSINSDELH*/ +#define RSTV0910_P2_TSINSDELH 0xf376 +#define FSTV0910_P2_TSDEL_SYNCBYTE 0xf3760080 +#define FSTV0910_P2_TSDEL_XXHEADER 0xf3760040 +#define FSTV0910_P2_TSDEL_BBHEADER 0xf3760020 +#define FSTV0910_P2_TSDEL_DATAFIELD 0xf3760010 +#define FSTV0910_P2_TSINSDEL_ISCR 0xf3760008 +#define FSTV0910_P2_TSINSDEL_NPD 0xf3760004 +#define FSTV0910_P2_TSINSDEL_RSPARITY 0xf3760002 +#define FSTV0910_P2_TSINSDEL_CRC8 0xf3760001 + +/*P2_TSDIVN*/ +#define RSTV0910_P2_TSDIVN 0xf379 +#define FSTV0910_P2_TSFIFO_SPEEDMODE 0xf37900c0 +#define FSTV0910_P2_BYTE_OVERSAMPLING 0xf3790038 +#define FSTV0910_P2_TSFIFO_RISEOK 0xf3790007 + +/*P2_TSCFG4*/ +#define RSTV0910_P2_TSCFG4 0xf37a +#define FSTV0910_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0 +#define FSTV0910_P2_TSFIFO_HIERSEL 0xf37a0020 +#define FSTV0910_P2_TSFIFO_SPECTOKEN 0xf37a0010 +#define FSTV0910_P2_TSFIFO_MAXMODE 0xf37a0008 +#define FSTV0910_P2_TSFIFO_FRFORCEPKT 0xf37a0004 +#define FSTV0910_P2_EXT_FECSPYIN 0xf37a0002 +#define FSTV0910_P2_TSFIFO_DELSPEEDUP 0xf37a0001 + +/*P2_TSSPEED*/ +#define RSTV0910_P2_TSSPEED 0xf380 +#define FSTV0910_P2_TSFIFO_OUTSPEED 0xf38000ff + +/*P2_TSSTATUS*/ +#define RSTV0910_P2_TSSTATUS 0xf381 +#define FSTV0910_P2_TSFIFO_LINEOK 0xf3810080 +#define FSTV0910_P2_TSFIFO_ERROR 0xf3810040 +#define FSTV0910_P2_TSFIFO_DATA7 0xf3810020 +#define FSTV0910_P2_TSFIFO_NOSYNC 0xf3810010 +#define FSTV0910_P2_ISCR_INITIALIZED 0xf3810008 +#define FSTV0910_P2_TSREGUL_ERROR 0xf3810004 +#define FSTV0910_P2_SOFFIFO_UNREGUL 0xf3810002 +#define FSTV0910_P2_DIL_READY 0xf3810001 + +/*P2_TSSTATUS2*/ +#define RSTV0910_P2_TSSTATUS2 0xf382 +#define FSTV0910_P2_TSFIFO_DEMODSEL 0xf3820080 +#define FSTV0910_P2_TSFIFOSPEED_STORE 0xf3820040 +#define FSTV0910_P2_DILXX_RESET 0xf3820020 +#define FSTV0910_P2_TSSPEED_IMPOSSIBLE 0xf3820010 +#define FSTV0910_P2_TSFIFO_LINENOK 0xf3820008 +#define FSTV0910_P2_TSFIFO_MUXSTREAM 0xf3820004 +#define FSTV0910_P2_SCRAMBDETECT 0xf3820002 +#define FSTV0910_P2_ULDTV67_FALSELOCK 0xf3820001 + +/*P2_TSBITRATE1*/ +#define RSTV0910_P2_TSBITRATE1 0xf383 +#define FSTV0910_P2_TSFIFO_BITRATE1 0xf38300ff + +/*P2_TSBITRATE0*/ +#define RSTV0910_P2_TSBITRATE0 0xf384 +#define FSTV0910_P2_TSFIFO_BITRATE0 0xf38400ff + +/*P2_ERRCTRL1*/ +#define RSTV0910_P2_ERRCTRL1 0xf398 +#define FSTV0910_P2_ERR_SOURCE1 0xf39800f0 +#define FSTV0910_P2_NUM_EVENT1 0xf3980007 + +/*P2_ERRCNT12*/ +#define RSTV0910_P2_ERRCNT12 0xf399 +#define FSTV0910_P2_ERRCNT1_OLDVALUE 0xf3990080 +#define FSTV0910_P2_ERR_CNT12 0xf399007f + +/*P2_ERRCNT11*/ +#define RSTV0910_P2_ERRCNT11 0xf39a +#define FSTV0910_P2_ERR_CNT11 0xf39a00ff + +/*P2_ERRCNT10*/ +#define RSTV0910_P2_ERRCNT10 0xf39b +#define FSTV0910_P2_ERR_CNT10 0xf39b00ff + +/*P2_ERRCTRL2*/ +#define RSTV0910_P2_ERRCTRL2 0xf39c +#define FSTV0910_P2_ERR_SOURCE2 0xf39c00f0 +#define FSTV0910_P2_NUM_EVENT2 0xf39c0007 + +/*P2_ERRCNT22*/ +#define RSTV0910_P2_ERRCNT22 0xf39d +#define FSTV0910_P2_ERRCNT2_OLDVALUE 0xf39d0080 +#define FSTV0910_P2_ERR_CNT22 0xf39d007f + +/*P2_ERRCNT21*/ +#define RSTV0910_P2_ERRCNT21 0xf39e +#define FSTV0910_P2_ERR_CNT21 0xf39e00ff + +/*P2_ERRCNT20*/ +#define RSTV0910_P2_ERRCNT20 0xf39f +#define FSTV0910_P2_ERR_CNT20 0xf39f00ff + +/*P2_FECSPY*/ +#define RSTV0910_P2_FECSPY 0xf3a0 +#define FSTV0910_P2_SPY_ENABLE 0xf3a00080 +#define FSTV0910_P2_NO_SYNCBYTE 0xf3a00040 +#define FSTV0910_P2_SERIAL_MODE 0xf3a00020 +#define FSTV0910_P2_UNUSUAL_PACKET 0xf3a00010 +#define FSTV0910_P2_BERMETER_DATAMODE 0xf3a0000c +#define FSTV0910_P2_BERMETER_LMODE 0xf3a00002 +#define FSTV0910_P2_BERMETER_RESET 0xf3a00001 + +/*P2_FSPYCFG*/ +#define RSTV0910_P2_FSPYCFG 0xf3a1 +#define FSTV0910_P2_FECSPY_INPUT 0xf3a100c0 +#define FSTV0910_P2_RST_ON_ERROR 0xf3a10020 +#define FSTV0910_P2_ONE_SHOT 0xf3a10010 +#define FSTV0910_P2_I2C_MODE 0xf3a1000c +#define FSTV0910_P2_SPY_HYSTERESIS 0xf3a10003 + +/*P2_FSPYDATA*/ +#define RSTV0910_P2_FSPYDATA 0xf3a2 +#define FSTV0910_P2_SPY_STUFFING 0xf3a20080 +#define FSTV0910_P2_NOERROR_PKTJITTER 0xf3a20040 +#define FSTV0910_P2_SPY_CNULLPKT 0xf3a20020 +#define FSTV0910_P2_SPY_OUTDATA_MODE 0xf3a2001f + +/*P2_FSPYOUT*/ +#define RSTV0910_P2_FSPYOUT 0xf3a3 +#define FSTV0910_P2_FSPY_DIRECT 0xf3a30080 +#define FSTV0910_P2_SPY_OUTDATA_BUS 0xf3a30038 +#define FSTV0910_P2_STUFF_MODE 0xf3a30007 + +/*P2_FSTATUS*/ +#define RSTV0910_P2_FSTATUS 0xf3a4 +#define FSTV0910_P2_SPY_ENDSIM 0xf3a40080 +#define FSTV0910_P2_VALID_SIM 0xf3a40040 +#define FSTV0910_P2_FOUND_SIGNAL 0xf3a40020 +#define FSTV0910_P2_DSS_SYNCBYTE 0xf3a40010 +#define FSTV0910_P2_RESULT_STATE 0xf3a4000f + +/*P2_FBERCPT4*/ +#define RSTV0910_P2_FBERCPT4 0xf3a8 +#define FSTV0910_P2_FBERMETER_CPT4 0xf3a800ff + +/*P2_FBERCPT3*/ +#define RSTV0910_P2_FBERCPT3 0xf3a9 +#define FSTV0910_P2_FBERMETER_CPT3 0xf3a900ff + +/*P2_FBERCPT2*/ +#define RSTV0910_P2_FBERCPT2 0xf3aa +#define FSTV0910_P2_FBERMETER_CPT2 0xf3aa00ff + +/*P2_FBERCPT1*/ +#define RSTV0910_P2_FBERCPT1 0xf3ab +#define FSTV0910_P2_FBERMETER_CPT1 0xf3ab00ff + +/*P2_FBERCPT0*/ +#define RSTV0910_P2_FBERCPT0 0xf3ac +#define FSTV0910_P2_FBERMETER_CPT0 0xf3ac00ff + +/*P2_FBERERR2*/ +#define RSTV0910_P2_FBERERR2 0xf3ad +#define FSTV0910_P2_FBERMETER_ERR2 0xf3ad00ff + +/*P2_FBERERR1*/ +#define RSTV0910_P2_FBERERR1 0xf3ae +#define FSTV0910_P2_FBERMETER_ERR1 0xf3ae00ff + +/*P2_FBERERR0*/ +#define RSTV0910_P2_FBERERR0 0xf3af +#define FSTV0910_P2_FBERMETER_ERR0 0xf3af00ff + +/*P2_FSPYBER*/ +#define RSTV0910_P2_FSPYBER 0xf3b2 +#define FSTV0910_P2_FSPYOBS_XORREAD 0xf3b20040 +#define FSTV0910_P2_FSPYBER_OBSMODE 0xf3b20020 +#define FSTV0910_P2_FSPYBER_SYNCBYTE 0xf3b20010 +#define FSTV0910_P2_FSPYBER_UNSYNC 0xf3b20008 +#define FSTV0910_P2_FSPYBER_CTIME 0xf3b20007 + +/*P2_SFERROR*/ +#define RSTV0910_P2_SFERROR 0xf3c1 +#define FSTV0910_P2_SFEC_REGERR_VIT 0xf3c100ff + +/*P2_SFECSTATUS*/ +#define RSTV0910_P2_SFECSTATUS 0xf3c3 +#define FSTV0910_P2_SFEC_ON 0xf3c30080 +#define FSTV0910_P2_SFEC_OFF 0xf3c30040 +#define FSTV0910_P2_LOCKEDSFEC 0xf3c30008 +#define FSTV0910_P2_SFEC_DELOCK 0xf3c30004 +#define FSTV0910_P2_SFEC_DEMODSEL 0xf3c30002 +#define FSTV0910_P2_SFEC_OVFON 0xf3c30001 + +/*P2_SFKDIV12*/ +#define RSTV0910_P2_SFKDIV12 0xf3c4 +#define FSTV0910_P2_SFECKDIV12_MAN 0xf3c40080 +#define FSTV0910_P2_SFEC_K_DIVIDER_12 0xf3c4007f + +/*P2_SFKDIV23*/ +#define RSTV0910_P2_SFKDIV23 0xf3c5 +#define FSTV0910_P2_SFECKDIV23_MAN 0xf3c50080 +#define FSTV0910_P2_SFEC_K_DIVIDER_23 0xf3c5007f + +/*P2_SFKDIV34*/ +#define RSTV0910_P2_SFKDIV34 0xf3c6 +#define FSTV0910_P2_SFECKDIV34_MAN 0xf3c60080 +#define FSTV0910_P2_SFEC_K_DIVIDER_34 0xf3c6007f + +/*P2_SFKDIV56*/ +#define RSTV0910_P2_SFKDIV56 0xf3c7 +#define FSTV0910_P2_SFECKDIV56_MAN 0xf3c70080 +#define FSTV0910_P2_SFEC_K_DIVIDER_56 0xf3c7007f + +/*P2_SFKDIV67*/ +#define RSTV0910_P2_SFKDIV67 0xf3c8 +#define FSTV0910_P2_SFECKDIV67_MAN 0xf3c80080 +#define FSTV0910_P2_SFEC_K_DIVIDER_67 0xf3c8007f + +/*P2_SFKDIV78*/ +#define RSTV0910_P2_SFKDIV78 0xf3c9 +#define FSTV0910_P2_SFECKDIV78_MAN 0xf3c90080 +#define FSTV0910_P2_SFEC_K_DIVIDER_78 0xf3c9007f + +/*P2_SFSTATUS*/ +#define RSTV0910_P2_SFSTATUS 0xf3cc +#define FSTV0910_P2_SFEC_LINEOK 0xf3cc0080 +#define FSTV0910_P2_SFEC_ERROR 0xf3cc0040 +#define FSTV0910_P2_SFEC_DATA7 0xf3cc0020 +#define FSTV0910_P2_SFEC_PKTDNBRFAIL 0xf3cc0010 +#define FSTV0910_P2_TSSFEC_DEMODSEL 0xf3cc0008 +#define FSTV0910_P2_SFEC_NOSYNC 0xf3cc0004 +#define FSTV0910_P2_SFEC_UNREGULA 0xf3cc0002 +#define FSTV0910_P2_SFEC_READY 0xf3cc0001 + +/*P2_SFDLYSET2*/ +#define RSTV0910_P2_SFDLYSET2 0xf3d0 +#define FSTV0910_P2_SFEC_OFFSET 0xf3d000c0 +#define FSTV0910_P2_RST_SFEC 0xf3d00008 +#define FSTV0910_P2_DILDLINE_ERROR 0xf3d00004 +#define FSTV0910_P2_SFEC_DISABLE 0xf3d00002 +#define FSTV0910_P2_SFEC_UNREGUL 0xf3d00001 + +/*P2_SFERRCTRL*/ +#define RSTV0910_P2_SFERRCTRL 0xf3d8 +#define FSTV0910_P2_SFEC_ERR_SOURCE 0xf3d800f0 +#define FSTV0910_P2_SFEC_NUM_EVENT 0xf3d80007 + +/*P2_SFERRCNT2*/ +#define RSTV0910_P2_SFERRCNT2 0xf3d9 +#define FSTV0910_P2_SFERRC_OLDVALUE 0xf3d90080 +#define FSTV0910_P2_SFEC_ERR_CNT2 0xf3d9007f + +/*P2_SFERRCNT1*/ +#define RSTV0910_P2_SFERRCNT1 0xf3da +#define FSTV0910_P2_SFEC_ERR_CNT1 0xf3da00ff + +/*P2_SFERRCNT0*/ +#define RSTV0910_P2_SFERRCNT0 0xf3db +#define FSTV0910_P2_SFEC_ERR_CNT0 0xf3db00ff + +/*P1_IQCONST*/ +#define RSTV0910_P1_IQCONST 0xf400 +#define FSTV0910_P1_CONSTEL_SELECT 0xf4000060 +#define FSTV0910_P1_IQSYMB_SEL 0xf400001f + +/*P1_NOSCFG*/ +#define RSTV0910_P1_NOSCFG 0xf401 +#define FSTV0910_P1_DIS_ACMRATIO 0xf4010080 +#define FSTV0910_P1_NOSIN_EGALSEL 0xf4010040 +#define FSTV0910_P1_DUMMYPL_NOSDATA 0xf4010020 +#define FSTV0910_P1_NOSPLH_BETA 0xf4010018 +#define FSTV0910_P1_NOSDATA_BETA 0xf4010007 + +/*P1_ISYMB*/ +#define RSTV0910_P1_ISYMB 0xf402 +#define FSTV0910_P1_I_SYMBOL 0xf40201ff + +/*P1_QSYMB*/ +#define RSTV0910_P1_QSYMB 0xf403 +#define FSTV0910_P1_Q_SYMBOL 0xf40301ff + +/*P1_AGC1CFG*/ +#define RSTV0910_P1_AGC1CFG 0xf404 +#define FSTV0910_P1_DC_FROZEN 0xf4040080 +#define FSTV0910_P1_DC_CORRECT 0xf4040040 +#define FSTV0910_P1_AMM_FROZEN 0xf4040020 +#define FSTV0910_P1_AMM_CORRECT 0xf4040010 +#define FSTV0910_P1_QUAD_FROZEN 0xf4040008 +#define FSTV0910_P1_QUAD_CORRECT 0xf4040004 +#define FSTV0910_P1_DCCOMP_SLOW 0xf4040002 +#define FSTV0910_P1_IQMISM_SLOW 0xf4040001 + +/*P1_AGC1CN*/ +#define RSTV0910_P1_AGC1CN 0xf406 +#define FSTV0910_P1_AGC1_LOCKED 0xf4060080 +#define FSTV0910_P1_AGC1_OVERFLOW 0xf4060040 +#define FSTV0910_P1_AGC1_NOSLOWLK 0xf4060020 +#define FSTV0910_P1_AGC1_MINPOWER 0xf4060010 +#define FSTV0910_P1_AGCOUT_FAST 0xf4060008 +#define FSTV0910_P1_AGCIQ_BETA 0xf4060007 + +/*P1_AGC1REF*/ +#define RSTV0910_P1_AGC1REF 0xf407 +#define FSTV0910_P1_AGCIQ_REF 0xf40700ff + +/*P1_IDCCOMP*/ +#define RSTV0910_P1_IDCCOMP 0xf408 +#define FSTV0910_P1_IAVERAGE_ADJ 0xf40801ff + +/*P1_QDCCOMP*/ +#define RSTV0910_P1_QDCCOMP 0xf409 +#define FSTV0910_P1_QAVERAGE_ADJ 0xf40901ff + +/*P1_POWERI*/ +#define RSTV0910_P1_POWERI 0xf40a +#define FSTV0910_P1_POWER_I 0xf40a00ff + +/*P1_POWERQ*/ +#define RSTV0910_P1_POWERQ 0xf40b +#define FSTV0910_P1_POWER_Q 0xf40b00ff + +/*P1_AGC1AMM*/ +#define RSTV0910_P1_AGC1AMM 0xf40c +#define FSTV0910_P1_AMM_VALUE 0xf40c00ff + +/*P1_AGC1QUAD*/ +#define RSTV0910_P1_AGC1QUAD 0xf40d +#define FSTV0910_P1_QUAD_VALUE 0xf40d01ff + +/*P1_AGCIQIN1*/ +#define RSTV0910_P1_AGCIQIN1 0xf40e +#define FSTV0910_P1_AGCIQ_VALUE1 0xf40e00ff + +/*P1_AGCIQIN0*/ +#define RSTV0910_P1_AGCIQIN0 0xf40f +#define FSTV0910_P1_AGCIQ_VALUE0 0xf40f00ff + +/*P1_DEMOD*/ +#define RSTV0910_P1_DEMOD 0xf410 +#define FSTV0910_P1_MANUALS2_ROLLOFF 0xf4100080 +#define FSTV0910_P1_SPECINV_CONTROL 0xf4100030 +#define FSTV0910_P1_MANUALSX_ROLLOFF 0xf4100004 +#define FSTV0910_P1_ROLLOFF_CONTROL 0xf4100003 + +/*P1_DMDMODCOD*/ +#define RSTV0910_P1_DMDMODCOD 0xf411 +#define FSTV0910_P1_MANUAL_MODCOD 0xf4110080 +#define FSTV0910_P1_DEMOD_MODCOD 0xf411007c +#define FSTV0910_P1_DEMOD_TYPE 0xf4110003 + +/*P1_DSTATUS*/ +#define RSTV0910_P1_DSTATUS 0xf412 +#define FSTV0910_P1_CAR_LOCK 0xf4120080 +#define FSTV0910_P1_TMGLOCK_QUALITY 0xf4120060 +#define FSTV0910_P1_SDVBS1_ENABLE 0xf4120010 +#define FSTV0910_P1_LOCK_DEFINITIF 0xf4120008 +#define FSTV0910_P1_TIMING_IS_LOCKED 0xf4120004 +#define FSTV0910_P1_DEMOD_SYSCFG 0xf4120002 +#define FSTV0910_P1_OVADC_DETECT 0xf4120001 + +/*P1_DSTATUS2*/ +#define RSTV0910_P1_DSTATUS2 0xf413 +#define FSTV0910_P1_DEMOD_DELOCK 0xf4130080 +#define FSTV0910_P1_DEMOD_TIMEOUT 0xf4130040 +#define FSTV0910_P1_MODCODRQ_SYNCTAG 0xf4130020 +#define FSTV0910_P1_POLYPH_SATEVENT 0xf4130010 +#define FSTV0910_P1_AGC1_NOSIGNALACK 0xf4130008 +#define FSTV0910_P1_AGC2_OVERFLOW 0xf4130004 +#define FSTV0910_P1_CFR_OVERFLOW 0xf4130002 +#define FSTV0910_P1_GAMMA_OVERUNDER 0xf4130001 + +/*P1_DMDCFGMD*/ +#define RSTV0910_P1_DMDCFGMD 0xf414 +#define FSTV0910_P1_DVBS2_ENABLE 0xf4140080 +#define FSTV0910_P1_DVBS1_ENABLE 0xf4140040 +#define FSTV0910_P1_SCAN_ENABLE 0xf4140010 +#define FSTV0910_P1_CFR_AUTOSCAN 0xf4140008 +#define FSTV0910_P1_NOFORCE_RELOCK 0xf4140004 +#define FSTV0910_P1_TUN_RNG 0xf4140003 + +/*P1_DMDCFG2*/ +#define RSTV0910_P1_DMDCFG2 0xf415 +#define FSTV0910_P1_AGC1_WAITLOCK 0xf4150080 +#define FSTV0910_P1_S1S2_SEQUENTIAL 0xf4150040 +#define FSTV0910_P1_BLINDPEA_MODE 0xf4150020 +#define FSTV0910_P1_INFINITE_RELOCK 0xf4150010 +#define FSTV0910_P1_BWOFFSET_COLDWARM 0xf4150008 +#define FSTV0910_P1_TMGLOCK_NSCANSTOP 0xf4150004 +#define FSTV0910_P1_COARSE_LK3MODE 0xf4150002 +#define FSTV0910_P1_COARSE_LK2MODE 0xf4150001 + +/*P1_DMDISTATE*/ +#define RSTV0910_P1_DMDISTATE 0xf416 +#define FSTV0910_P1_I2C_NORESETDMODE 0xf4160080 +#define FSTV0910_P1_FORCE_ETAPED 0xf4160040 +#define FSTV0910_P1_SDMDRST_DIRCLK 0xf4160020 +#define FSTV0910_P1_I2C_DEMOD_MODE 0xf416001f + +/*P1_DMDT0M*/ +#define RSTV0910_P1_DMDT0M 0xf417 +#define FSTV0910_P1_DMDT0_MIN 0xf41700ff + +/*P1_DMDSTATE*/ +#define RSTV0910_P1_DMDSTATE 0xf41b +#define FSTV0910_P1_DEMOD_LOCKED 0xf41b0080 +#define FSTV0910_P1_HEADER_MODE 0xf41b0060 +#define FSTV0910_P1_DEMOD_MODE 0xf41b001f + +/*P1_DMDFLYW*/ +#define RSTV0910_P1_DMDFLYW 0xf41c +#define FSTV0910_P1_I2C_IRQVAL 0xf41c00f0 +#define FSTV0910_P1_FLYWHEEL_CPT 0xf41c000f + +/*P1_DSTATUS3*/ +#define RSTV0910_P1_DSTATUS3 0xf41d +#define FSTV0910_P1_CFR_ZIGZAG 0xf41d0080 +#define FSTV0910_P1_DEMOD_CFGMODE 0xf41d0060 +#define FSTV0910_P1_GAMMA_LOWBAUDRATE 0xf41d0010 +#define FSTV0910_P1_RELOCK_MODE 0xf41d0008 +#define FSTV0910_P1_DEMOD_FAIL 0xf41d0004 +#define FSTV0910_P1_ETAPE1A_DVBXMEM 0xf41d0003 + +/*P1_DMDCFG3*/ +#define RSTV0910_P1_DMDCFG3 0xf41e +#define FSTV0910_P1_DVBS1_TMGWAIT 0xf41e0080 +#define FSTV0910_P1_NO_BWCENTERING 0xf41e0040 +#define FSTV0910_P1_INV_SEQSRCH 0xf41e0020 +#define FSTV0910_P1_DIS_SFRUPLOW_TRK 0xf41e0010 +#define FSTV0910_P1_NOSTOP_FIFOFULL 0xf41e0008 +#define FSTV0910_P1_LOCKTIME_MODE 0xf41e0007 + +/*P1_DMDCFG4*/ +#define RSTV0910_P1_DMDCFG4 0xf41f +#define FSTV0910_P1_DIS_VITLOCK 0xf41f0080 +#define FSTV0910_P1_S1S2TOUT_FAST 0xf41f0040 +#define FSTV0910_P1_DEMOD_FASTLOCK 0xf41f0020 +#define FSTV0910_P1_S1HIER_ENABLE 0xf41f0010 +#define FSTV0910_P1_TUNER_NRELAUNCH 0xf41f0008 +#define FSTV0910_P1_DIS_CLKENABLE 0xf41f0004 +#define FSTV0910_P1_DIS_HDRDIVLOCK 0xf41f0002 +#define FSTV0910_P1_NO_TNRWBINIT 0xf41f0001 + +/*P1_CORRELMANT*/ +#define RSTV0910_P1_CORRELMANT 0xf420 +#define FSTV0910_P1_CORREL_MANT 0xf42000ff + +/*P1_CORRELABS*/ +#define RSTV0910_P1_CORRELABS 0xf421 +#define FSTV0910_P1_CORREL_ABS 0xf42100ff + +/*P1_CORRELEXP*/ +#define RSTV0910_P1_CORRELEXP 0xf422 +#define FSTV0910_P1_CORREL_ABSEXP 0xf42200f0 +#define FSTV0910_P1_CORREL_EXP 0xf422000f + +/*P1_PLHMODCOD*/ +#define RSTV0910_P1_PLHMODCOD 0xf424 +#define FSTV0910_P1_SPECINV_DEMOD 0xf4240080 +#define FSTV0910_P1_PLH_MODCOD 0xf424007c +#define FSTV0910_P1_PLH_TYPE 0xf4240003 + +/*P1_DMDREG*/ +#define RSTV0910_P1_DMDREG 0xf425 +#define FSTV0910_P1_EXTPSK_MODE 0xf4250080 +#define FSTV0910_P1_HIER_SHORTFRAME 0xf4250002 +#define FSTV0910_P1_DECIM_PLFRAMES 0xf4250001 + +/*P1_AGC2O*/ +#define RSTV0910_P1_AGC2O 0xf42c +#define FSTV0910_P1_CSTENV_MODE 0xf42c00c0 +#define FSTV0910_P1_AGC2_LKSQRT 0xf42c0020 +#define FSTV0910_P1_AGC2_LKMODE 0xf42c0010 +#define FSTV0910_P1_AGC2_LKEQUA 0xf42c0008 +#define FSTV0910_P1_AGC2_COEF 0xf42c0007 + +/*P1_AGC2REF*/ +#define RSTV0910_P1_AGC2REF 0xf42d +#define FSTV0910_P1_AGC2_REF 0xf42d00ff + +/*P1_AGC1ADJ*/ +#define RSTV0910_P1_AGC1ADJ 0xf42e +#define FSTV0910_P1_AGC1ADJ_MANUAL 0xf42e0080 +#define FSTV0910_P1_AGC1_ADJUSTED 0xf42e007f + +/*P1_AGC2I1*/ +#define RSTV0910_P1_AGC2I1 0xf436 +#define FSTV0910_P1_AGC2_INTEGRATOR1 0xf43600ff + +/*P1_AGC2I0*/ +#define RSTV0910_P1_AGC2I0 0xf437 +#define FSTV0910_P1_AGC2_INTEGRATOR0 0xf43700ff + +/*P1_CARCFG*/ +#define RSTV0910_P1_CARCFG 0xf438 +#define FSTV0910_P1_CFRUPLOW_AUTO 0xf4380080 +#define FSTV0910_P1_CFRUPLOW_TEST 0xf4380040 +#define FSTV0910_P1_WIDE_FREQDET 0xf4380020 +#define FSTV0910_P1_CARHDR_NODIV8 0xf4380010 +#define FSTV0910_P1_I2C_ROTA 0xf4380008 +#define FSTV0910_P1_ROTAON 0xf4380004 +#define FSTV0910_P1_PH_DET_ALGO 0xf4380003 + +/*P1_ACLC*/ +#define RSTV0910_P1_ACLC 0xf439 +#define FSTV0910_P1_CARS1_ANOSAUTO 0xf4390040 +#define FSTV0910_P1_CAR_ALPHA_MANT 0xf4390030 +#define FSTV0910_P1_CAR_ALPHA_EXP 0xf439000f + +/*P1_BCLC*/ +#define RSTV0910_P1_BCLC 0xf43a +#define FSTV0910_P1_CARS1_BNOSAUTO 0xf43a0040 +#define FSTV0910_P1_CAR_BETA_MANT 0xf43a0030 +#define FSTV0910_P1_CAR_BETA_EXP 0xf43a000f + +/*P1_CARFREQ*/ +#define RSTV0910_P1_CARFREQ 0xf43d +#define FSTV0910_P1_KC_COARSE_EXP 0xf43d00f0 +#define FSTV0910_P1_BETA_FREQ 0xf43d000f + +/*P1_CARHDR*/ +#define RSTV0910_P1_CARHDR 0xf43e +#define FSTV0910_P1_K_FREQ_HDR 0xf43e00ff + +/*P1_LDT*/ +#define RSTV0910_P1_LDT 0xf43f +#define FSTV0910_P1_CARLOCK_THRES 0xf43f01ff + +/*P1_LDT2*/ +#define RSTV0910_P1_LDT2 0xf440 +#define FSTV0910_P1_CARLOCK_THRES2 0xf44001ff + +/*P1_CFRICFG*/ +#define RSTV0910_P1_CFRICFG 0xf441 +#define FSTV0910_P1_CFRINIT_UNVALRNG 0xf4410080 +#define FSTV0910_P1_CFRINIT_LUNVALCPT 0xf4410040 +#define FSTV0910_P1_CFRINIT_ABORTDBL 0xf4410020 +#define FSTV0910_P1_CFRINIT_ABORTPRED 0xf4410010 +#define FSTV0910_P1_CFRINIT_UNVALSKIP 0xf4410008 +#define FSTV0910_P1_CFRINIT_CSTINC 0xf4410004 +#define FSTV0910_P1_CFRIROLL_GARDER 0xf4410002 +#define FSTV0910_P1_NEG_CFRSTEP 0xf4410001 + +/*P1_CFRUP1*/ +#define RSTV0910_P1_CFRUP1 0xf442 +#define FSTV0910_P1_CFR_UP1 0xf44201ff + +/*P1_CFRUP0*/ +#define RSTV0910_P1_CFRUP0 0xf443 +#define FSTV0910_P1_CFR_UP0 0xf44300ff + +/*P1_CFRIBASE1*/ +#define RSTV0910_P1_CFRIBASE1 0xf444 +#define FSTV0910_P1_CFRINIT_BASE1 0xf44400ff + +/*P1_CFRIBASE0*/ +#define RSTV0910_P1_CFRIBASE0 0xf445 +#define FSTV0910_P1_CFRINIT_BASE0 0xf44500ff + +/*P1_CFRLOW1*/ +#define RSTV0910_P1_CFRLOW1 0xf446 +#define FSTV0910_P1_CFR_LOW1 0xf44601ff + +/*P1_CFRLOW0*/ +#define RSTV0910_P1_CFRLOW0 0xf447 +#define FSTV0910_P1_CFR_LOW0 0xf44700ff + +/*P1_CFRINIT1*/ +#define RSTV0910_P1_CFRINIT1 0xf448 +#define FSTV0910_P1_CFR_INIT1 0xf44801ff + +/*P1_CFRINIT0*/ +#define RSTV0910_P1_CFRINIT0 0xf449 +#define FSTV0910_P1_CFR_INIT0 0xf44900ff + +/*P1_CFRINC1*/ +#define RSTV0910_P1_CFRINC1 0xf44a +#define FSTV0910_P1_MANUAL_CFRINC 0xf44a0080 +#define FSTV0910_P1_CFR_INC1 0xf44a003f + +/*P1_CFRINC0*/ +#define RSTV0910_P1_CFRINC0 0xf44b +#define FSTV0910_P1_CFR_INC0 0xf44b00ff + +/*P1_CFR2*/ +#define RSTV0910_P1_CFR2 0xf44c +#define FSTV0910_P1_CAR_FREQ2 0xf44c01ff + +/*P1_CFR1*/ +#define RSTV0910_P1_CFR1 0xf44d +#define FSTV0910_P1_CAR_FREQ1 0xf44d00ff + +/*P1_CFR0*/ +#define RSTV0910_P1_CFR0 0xf44e +#define FSTV0910_P1_CAR_FREQ0 0xf44e00ff + +/*P1_LDI*/ +#define RSTV0910_P1_LDI 0xf44f +#define FSTV0910_P1_LOCK_DET_INTEGR 0xf44f01ff + +/*P1_TMGCFG*/ +#define RSTV0910_P1_TMGCFG 0xf450 +#define FSTV0910_P1_TMGLOCK_BETA 0xf45000c0 +#define FSTV0910_P1_DO_TIMING_CORR 0xf4500010 +#define FSTV0910_P1_MANUAL_SCAN 0xf450000c +#define FSTV0910_P1_TMG_MINFREQ 0xf4500003 + +/*P1_RTC*/ +#define RSTV0910_P1_RTC 0xf451 +#define FSTV0910_P1_TMGALPHA_EXP 0xf45100f0 +#define FSTV0910_P1_TMGBETA_EXP 0xf451000f + +/*P1_RTCS2*/ +#define RSTV0910_P1_RTCS2 0xf452 +#define FSTV0910_P1_TMGALPHAS2_EXP 0xf45200f0 +#define FSTV0910_P1_TMGBETAS2_EXP 0xf452000f + +/*P1_TMGTHRISE*/ +#define RSTV0910_P1_TMGTHRISE 0xf453 +#define FSTV0910_P1_TMGLOCK_THRISE 0xf45300ff + +/*P1_TMGTHFALL*/ +#define RSTV0910_P1_TMGTHFALL 0xf454 +#define FSTV0910_P1_TMGLOCK_THFALL 0xf45400ff + +/*P1_SFRUPRATIO*/ +#define RSTV0910_P1_SFRUPRATIO 0xf455 +#define FSTV0910_P1_SFR_UPRATIO 0xf45500ff + +/*P1_SFRLOWRATIO*/ +#define RSTV0910_P1_SFRLOWRATIO 0xf456 +#define FSTV0910_P1_SFR_LOWRATIO 0xf45600ff + +/*P1_KTTMG*/ +#define RSTV0910_P1_KTTMG 0xf457 +#define FSTV0910_P1_KT_TMG_EXP 0xf45700f0 + +/*P1_KREFTMG*/ +#define RSTV0910_P1_KREFTMG 0xf458 +#define FSTV0910_P1_KREF_TMG 0xf45800ff + +/*P1_SFRSTEP*/ +#define RSTV0910_P1_SFRSTEP 0xf459 +#define FSTV0910_P1_SFR_SCANSTEP 0xf45900f0 +#define FSTV0910_P1_SFR_CENTERSTEP 0xf459000f + +/*P1_TMGCFG2*/ +#define RSTV0910_P1_TMGCFG2 0xf45a +#define FSTV0910_P1_KREFTMG2_DECMODE 0xf45a00c0 +#define FSTV0910_P1_DIS_AUTOSAMP 0xf45a0008 +#define FSTV0910_P1_SCANINIT_QUART 0xf45a0004 +#define FSTV0910_P1_NOTMG_DVBS1DERAT 0xf45a0002 +#define FSTV0910_P1_SFRRATIO_FINE 0xf45a0001 + +/*P1_KREFTMG2*/ +#define RSTV0910_P1_KREFTMG2 0xf45b +#define FSTV0910_P1_KREF_TMG2 0xf45b00ff + +/*P1_TMGCFG3*/ +#define RSTV0910_P1_TMGCFG3 0xf45d +#define FSTV0910_P1_CFRINC_MODE 0xf45d0070 +#define FSTV0910_P1_CONT_TMGCENTER 0xf45d0008 +#define FSTV0910_P1_AUTO_GUP 0xf45d0004 +#define FSTV0910_P1_AUTO_GLOW 0xf45d0002 +#define FSTV0910_P1_SFRVAL_MINMODE 0xf45d0001 + +/*P1_SFRINIT1*/ +#define RSTV0910_P1_SFRINIT1 0xf45e +#define FSTV0910_P1_SFR_INIT1 0xf45e00ff + +/*P1_SFRINIT0*/ +#define RSTV0910_P1_SFRINIT0 0xf45f +#define FSTV0910_P1_SFR_INIT0 0xf45f00ff + +/*P1_SFRUP1*/ +#define RSTV0910_P1_SFRUP1 0xf460 +#define FSTV0910_P1_SYMB_FREQ_UP1 0xf46000ff + +/*P1_SFRUP0*/ +#define RSTV0910_P1_SFRUP0 0xf461 +#define FSTV0910_P1_SYMB_FREQ_UP0 0xf46100ff + +/*P1_SFRLOW1*/ +#define RSTV0910_P1_SFRLOW1 0xf462 +#define FSTV0910_P1_SYMB_FREQ_LOW1 0xf46200ff + +/*P1_SFRLOW0*/ +#define RSTV0910_P1_SFRLOW0 0xf463 +#define FSTV0910_P1_SYMB_FREQ_LOW0 0xf46300ff + +/*P1_SFR3*/ +#define RSTV0910_P1_SFR3 0xf464 +#define FSTV0910_P1_SYMB_FREQ3 0xf46400ff + +/*P1_SFR2*/ +#define RSTV0910_P1_SFR2 0xf465 +#define FSTV0910_P1_SYMB_FREQ2 0xf46500ff + +/*P1_SFR1*/ +#define RSTV0910_P1_SFR1 0xf466 +#define FSTV0910_P1_SYMB_FREQ1 0xf46600ff + +/*P1_SFR0*/ +#define RSTV0910_P1_SFR0 0xf467 +#define FSTV0910_P1_SYMB_FREQ0 0xf46700ff + +/*P1_TMGREG2*/ +#define RSTV0910_P1_TMGREG2 0xf468 +#define FSTV0910_P1_TMGREG2 0xf46800ff + +/*P1_TMGREG1*/ +#define RSTV0910_P1_TMGREG1 0xf469 +#define FSTV0910_P1_TMGREG1 0xf46900ff + +/*P1_TMGREG0*/ +#define RSTV0910_P1_TMGREG0 0xf46a +#define FSTV0910_P1_TMGREG0 0xf46a00ff + +/*P1_TMGLOCK1*/ +#define RSTV0910_P1_TMGLOCK1 0xf46b +#define FSTV0910_P1_TMGLOCK_LEVEL1 0xf46b01ff + +/*P1_TMGLOCK0*/ +#define RSTV0910_P1_TMGLOCK0 0xf46c +#define FSTV0910_P1_TMGLOCK_LEVEL0 0xf46c00ff + +/*P1_TMGOBS*/ +#define RSTV0910_P1_TMGOBS 0xf46d +#define FSTV0910_P1_ROLLOFF_STATUS 0xf46d00c0 +#define FSTV0910_P1_SCAN_SIGN 0xf46d0030 +#define FSTV0910_P1_TMG_SCANNING 0xf46d0008 +#define FSTV0910_P1_CHCENTERING_MODE 0xf46d0004 +#define FSTV0910_P1_TMG_SCANFAIL 0xf46d0002 + +/*P1_EQUALCFG*/ +#define RSTV0910_P1_EQUALCFG 0xf46f +#define FSTV0910_P1_NOTMG_NEGALWAIT 0xf46f0080 +#define FSTV0910_P1_EQUAL_ON 0xf46f0040 +#define FSTV0910_P1_SEL_EQUALCOR 0xf46f0038 +#define FSTV0910_P1_MU_EQUALDFE 0xf46f0007 + +/*P1_EQUAI1*/ +#define RSTV0910_P1_EQUAI1 0xf470 +#define FSTV0910_P1_EQUA_ACCI1 0xf47001ff + +/*P1_EQUAQ1*/ +#define RSTV0910_P1_EQUAQ1 0xf471 +#define FSTV0910_P1_EQUA_ACCQ1 0xf47101ff + +/*P1_EQUAI2*/ +#define RSTV0910_P1_EQUAI2 0xf472 +#define FSTV0910_P1_EQUA_ACCI2 0xf47201ff + +/*P1_EQUAQ2*/ +#define RSTV0910_P1_EQUAQ2 0xf473 +#define FSTV0910_P1_EQUA_ACCQ2 0xf47301ff + +/*P1_EQUAI3*/ +#define RSTV0910_P1_EQUAI3 0xf474 +#define FSTV0910_P1_EQUA_ACCI3 0xf47401ff + +/*P1_EQUAQ3*/ +#define RSTV0910_P1_EQUAQ3 0xf475 +#define FSTV0910_P1_EQUA_ACCQ3 0xf47501ff + +/*P1_EQUAI4*/ +#define RSTV0910_P1_EQUAI4 0xf476 +#define FSTV0910_P1_EQUA_ACCI4 0xf47601ff + +/*P1_EQUAQ4*/ +#define RSTV0910_P1_EQUAQ4 0xf477 +#define FSTV0910_P1_EQUA_ACCQ4 0xf47701ff + +/*P1_EQUAI5*/ +#define RSTV0910_P1_EQUAI5 0xf478 +#define FSTV0910_P1_EQUA_ACCI5 0xf47801ff + +/*P1_EQUAQ5*/ +#define RSTV0910_P1_EQUAQ5 0xf479 +#define FSTV0910_P1_EQUA_ACCQ5 0xf47901ff + +/*P1_EQUAI6*/ +#define RSTV0910_P1_EQUAI6 0xf47a +#define FSTV0910_P1_EQUA_ACCI6 0xf47a01ff + +/*P1_EQUAQ6*/ +#define RSTV0910_P1_EQUAQ6 0xf47b +#define FSTV0910_P1_EQUA_ACCQ6 0xf47b01ff + +/*P1_EQUAI7*/ +#define RSTV0910_P1_EQUAI7 0xf47c +#define FSTV0910_P1_EQUA_ACCI7 0xf47c01ff + +/*P1_EQUAQ7*/ +#define RSTV0910_P1_EQUAQ7 0xf47d +#define FSTV0910_P1_EQUA_ACCQ7 0xf47d01ff + +/*P1_EQUAI8*/ +#define RSTV0910_P1_EQUAI8 0xf47e +#define FSTV0910_P1_EQUA_ACCI8 0xf47e01ff + +/*P1_EQUAQ8*/ +#define RSTV0910_P1_EQUAQ8 0xf47f +#define FSTV0910_P1_EQUA_ACCQ8 0xf47f01ff + +/*P1_NNOSDATAT1*/ +#define RSTV0910_P1_NNOSDATAT1 0xf480 +#define FSTV0910_P1_NOSDATAT_NORMED1 0xf48000ff + +/*P1_NNOSDATAT0*/ +#define RSTV0910_P1_NNOSDATAT0 0xf481 +#define FSTV0910_P1_NOSDATAT_NORMED0 0xf48100ff + +/*P1_NNOSDATA1*/ +#define RSTV0910_P1_NNOSDATA1 0xf482 +#define FSTV0910_P1_NOSDATA_NORMED1 0xf48200ff + +/*P1_NNOSDATA0*/ +#define RSTV0910_P1_NNOSDATA0 0xf483 +#define FSTV0910_P1_NOSDATA_NORMED0 0xf48300ff + +/*P1_NNOSPLHT1*/ +#define RSTV0910_P1_NNOSPLHT1 0xf484 +#define FSTV0910_P1_NOSPLHT_NORMED1 0xf48400ff + +/*P1_NNOSPLHT0*/ +#define RSTV0910_P1_NNOSPLHT0 0xf485 +#define FSTV0910_P1_NOSPLHT_NORMED0 0xf48500ff + +/*P1_NNOSPLH1*/ +#define RSTV0910_P1_NNOSPLH1 0xf486 +#define FSTV0910_P1_NOSPLH_NORMED1 0xf48600ff + +/*P1_NNOSPLH0*/ +#define RSTV0910_P1_NNOSPLH0 0xf487 +#define FSTV0910_P1_NOSPLH_NORMED0 0xf48700ff + +/*P1_NOSDATAT1*/ +#define RSTV0910_P1_NOSDATAT1 0xf488 +#define FSTV0910_P1_NOSDATAT_UNNORMED1 0xf48800ff + +/*P1_NOSDATAT0*/ +#define RSTV0910_P1_NOSDATAT0 0xf489 +#define FSTV0910_P1_NOSDATAT_UNNORMED0 0xf48900ff + +/*P1_NNOSFRAME1*/ +#define RSTV0910_P1_NNOSFRAME1 0xf48a +#define FSTV0910_P1_NOSFRAME_NORMED1 0xf48a00ff + +/*P1_NNOSFRAME0*/ +#define RSTV0910_P1_NNOSFRAME0 0xf48b +#define FSTV0910_P1_NOSFRAME_NORMED0 0xf48b00ff + +/*P1_NNOSRAD1*/ +#define RSTV0910_P1_NNOSRAD1 0xf48c +#define FSTV0910_P1_NOSRADIAL_NORMED1 0xf48c00ff + +/*P1_NNOSRAD0*/ +#define RSTV0910_P1_NNOSRAD0 0xf48d +#define FSTV0910_P1_NOSRADIAL_NORMED0 0xf48d00ff + +/*P1_NOSCFGF1*/ +#define RSTV0910_P1_NOSCFGF1 0xf48e +#define FSTV0910_P1_LOWNOISE_MESURE 0xf48e0080 +#define FSTV0910_P1_NOS_DELFRAME 0xf48e0040 +#define FSTV0910_P1_NOSDATA_MODE 0xf48e0030 +#define FSTV0910_P1_FRAMESEL_TYPESEL 0xf48e000c +#define FSTV0910_P1_FRAMESEL_TYPE 0xf48e0003 + +/*P1_CAR2CFG*/ +#define RSTV0910_P1_CAR2CFG 0xf490 +#define FSTV0910_P1_DESCRAMB_OFF 0xf4900080 +#define FSTV0910_P1_EN_PHNOSRAM 0xf4900020 +#define FSTV0910_P1_STOP_CFR2UPDATE 0xf4900010 +#define FSTV0910_P1_STOP_NCO2UPDATE 0xf4900008 +#define FSTV0910_P1_ROTA2ON 0xf4900004 +#define FSTV0910_P1_PH_DET_ALGO2 0xf4900003 + +/*P1_CFR2CFR1*/ +#define RSTV0910_P1_CFR2CFR1 0xf491 +#define FSTV0910_P1_CFR2_S2CONTROL 0xf49100c0 +#define FSTV0910_P1_EN_S2CAR2CENTER 0xf4910020 +#define FSTV0910_P1_BCHERRCFR2_MODE 0xf4910018 +#define FSTV0910_P1_CFR2TOCFR1_BETA 0xf4910007 + +/*P1_CAR3CFG*/ +#define RSTV0910_P1_CAR3CFG 0xf492 +#define FSTV0910_P1_CARRIER23_MODE 0xf49200c0 +#define FSTV0910_P1_CAR3INTERM_DVBS1 0xf4920020 +#define FSTV0910_P1_ABAMPLIF_MODE 0xf4920018 +#define FSTV0910_P1_CARRIER3_ALPHA3DL 0xf4920007 + +/*P1_CFR22*/ +#define RSTV0910_P1_CFR22 0xf493 +#define FSTV0910_P1_CAR2_FREQ2 0xf49301ff + +/*P1_CFR21*/ +#define RSTV0910_P1_CFR21 0xf494 +#define FSTV0910_P1_CAR2_FREQ1 0xf49400ff + +/*P1_CFR20*/ +#define RSTV0910_P1_CFR20 0xf495 +#define FSTV0910_P1_CAR2_FREQ0 0xf49500ff + +/*P1_ACLC2S2Q*/ +#define RSTV0910_P1_ACLC2S2Q 0xf497 +#define FSTV0910_P1_ENAB_SPSKSYMB 0xf4970080 +#define FSTV0910_P1_CAR2S2_QANOSAUTO 0xf4970040 +#define FSTV0910_P1_CAR2S2_Q_ALPH_M 0xf4970030 +#define FSTV0910_P1_CAR2S2_Q_ALPH_E 0xf497000f + +/*P1_ACLC2S28*/ +#define RSTV0910_P1_ACLC2S28 0xf498 +#define FSTV0910_P1_OLDI3Q_MODE 0xf4980080 +#define FSTV0910_P1_CAR2S2_8ANOSAUTO 0xf4980040 +#define FSTV0910_P1_CAR2S2_8_ALPH_M 0xf4980030 +#define FSTV0910_P1_CAR2S2_8_ALPH_E 0xf498000f + +/*P1_ACLC2S216A*/ +#define RSTV0910_P1_ACLC2S216A 0xf499 +#define FSTV0910_P1_CAR2S2_16ANOSAUTO 0xf4990040 +#define FSTV0910_P1_CAR2S2_16A_ALPH_M 0xf4990030 +#define FSTV0910_P1_CAR2S2_16A_ALPH_E 0xf499000f + +/*P1_ACLC2S232A*/ +#define RSTV0910_P1_ACLC2S232A 0xf49a +#define FSTV0910_P1_CAR2S2_32ANOSUATO 0xf49a0040 +#define FSTV0910_P1_CAR2S2_32A_ALPH_M 0xf49a0030 +#define FSTV0910_P1_CAR2S2_32A_ALPH_E 0xf49a000f + +/*P1_BCLC2S2Q*/ +#define RSTV0910_P1_BCLC2S2Q 0xf49c +#define FSTV0910_P1_DVBS2S2Q_NIP 0xf49c0080 +#define FSTV0910_P1_CAR2S2_QBNOSAUTO 0xf49c0040 +#define FSTV0910_P1_CAR2S2_Q_BETA_M 0xf49c0030 +#define FSTV0910_P1_CAR2S2_Q_BETA_E 0xf49c000f + +/*P1_BCLC2S28*/ +#define RSTV0910_P1_BCLC2S28 0xf49d +#define FSTV0910_P1_DVBS2S28_NIP 0xf49d0080 +#define FSTV0910_P1_CAR2S2_8BNOSAUTO 0xf49d0040 +#define FSTV0910_P1_CAR2S2_8_BETA_M 0xf49d0030 +#define FSTV0910_P1_CAR2S2_8_BETA_E 0xf49d000f + +/*P1_PLROOT2*/ +#define RSTV0910_P1_PLROOT2 0xf4ac +#define FSTV0910_P1_PLHAUTO_DISPLH 0xf4ac0040 +#define FSTV0910_P1_PLHAUTO_FASTMODE 0xf4ac0020 +#define FSTV0910_P1_PLHAUTO_ENABLE 0xf4ac0010 +#define FSTV0910_P1_PLSCRAMB_MODE 0xf4ac000c +#define FSTV0910_P1_PLSCRAMB_ROOT2 0xf4ac0003 + +/*P1_PLROOT1*/ +#define RSTV0910_P1_PLROOT1 0xf4ad +#define FSTV0910_P1_PLSCRAMB_ROOT1 0xf4ad00ff + +/*P1_PLROOT0*/ +#define RSTV0910_P1_PLROOT0 0xf4ae +#define FSTV0910_P1_PLSCRAMB_ROOT0 0xf4ae00ff + +/*P1_MODCODLST7*/ +#define RSTV0910_P1_MODCODLST7 0xf4b7 +#define FSTV0910_P1_MODCOD_NNOSFILTER 0xf4b70080 +#define FSTV0910_P1_MODCODLST_NOSTYPE 0xf4b70040 +#define FSTV0910_P1_DIS_8PSK_9_10 0xf4b70030 +#define FSTV0910_P1_DIS_8P_8_9 0xf4b7000f + +/*P1_MODCODLST8*/ +#define RSTV0910_P1_MODCODLST8 0xf4b8 +#define FSTV0910_P1_DIS_8P_5_6 0xf4b800f0 +#define FSTV0910_P1_DIS_8P_3_4 0xf4b8000f + +/*P1_MODCODLST9*/ +#define RSTV0910_P1_MODCODLST9 0xf4b9 +#define FSTV0910_P1_DIS_8P_2_3 0xf4b900f0 +#define FSTV0910_P1_DIS_8P_3_5 0xf4b9000f + +/*P1_MODCODLSTA*/ +#define RSTV0910_P1_MODCODLSTA 0xf4ba +#define FSTV0910_P1_NOSFILTER_LIMITE 0xf4ba0080 +#define FSTV0910_P1_NOSFILTER_MODE 0xf4ba0040 +#define FSTV0910_P1_DIS_QPSK_9_10 0xf4ba0030 +#define FSTV0910_P1_DIS_QP_8_9 0xf4ba000f + +/*P1_MODCODLSTB*/ +#define RSTV0910_P1_MODCODLSTB 0xf4bb +#define FSTV0910_P1_DIS_QP_5_6 0xf4bb00f0 +#define FSTV0910_P1_DIS_QP_4_5 0xf4bb000f + +/*P1_MODCODLSTC*/ +#define RSTV0910_P1_MODCODLSTC 0xf4bc +#define FSTV0910_P1_DIS_QP_3_4 0xf4bc00f0 +#define FSTV0910_P1_DIS_QP_2_3 0xf4bc000f + +/*P1_MODCODLSTD*/ +#define RSTV0910_P1_MODCODLSTD 0xf4bd +#define FSTV0910_P1_DIS_QPSK_3_5 0xf4bd00f0 +#define FSTV0910_P1_DIS_QPSK_1_2 0xf4bd000f + +/*P1_GAUSSR0*/ +#define RSTV0910_P1_GAUSSR0 0xf4c0 +#define FSTV0910_P1_EN_CCIMODE 0xf4c00080 +#define FSTV0910_P1_R0_GAUSSIEN 0xf4c0007f + +/*P1_CCIR0*/ +#define RSTV0910_P1_CCIR0 0xf4c1 +#define FSTV0910_P1_CCIDETECT_PLHONLY 0xf4c10080 +#define FSTV0910_P1_R0_CCI 0xf4c1007f + +/*P1_CCIQUANT*/ +#define RSTV0910_P1_CCIQUANT 0xf4c2 +#define FSTV0910_P1_CCI_BETA 0xf4c200e0 +#define FSTV0910_P1_CCI_QUANT 0xf4c2001f + +/*P1_CCITHRES*/ +#define RSTV0910_P1_CCITHRES 0xf4c3 +#define FSTV0910_P1_CCI_THRESHOLD 0xf4c300ff + +/*P1_CCIACC*/ +#define RSTV0910_P1_CCIACC 0xf4c4 +#define FSTV0910_P1_CCI_VALUE 0xf4c400ff + +/*P1_DSTATUS4*/ +#define RSTV0910_P1_DSTATUS4 0xf4c5 +#define FSTV0910_P1_RAINFADE_DETECT 0xf4c50080 +#define FSTV0910_P1_NOTHRES2_FAIL 0xf4c50040 +#define FSTV0910_P1_NOTHRES1_FAIL 0xf4c50020 +#define FSTV0910_P1_PILOT_FAILDETECT 0xf4c50010 +#define FSTV0910_P1_HIER_DETECT 0xf4c50008 +#define FSTV0910_P1_DMDPROG_ERROR 0xf4c50004 +#define FSTV0910_P1_CSTENV_DETECT 0xf4c50002 +#define FSTV0910_P1_DETECTION_TRIAX 0xf4c50001 + +/*P1_DMDRESCFG*/ +#define RSTV0910_P1_DMDRESCFG 0xf4c6 +#define FSTV0910_P1_DMDRES_RESET 0xf4c60080 +#define FSTV0910_P1_DMDRES_NOISESQR 0xf4c60010 +#define FSTV0910_P1_DMDRES_STRALL 0xf4c60008 +#define FSTV0910_P1_DMDRES_NEWONLY 0xf4c60004 +#define FSTV0910_P1_DMDRES_NOSTORE 0xf4c60002 +#define FSTV0910_P1_DMDRES_AGC2MEM 0xf4c60001 + +/*P1_DMDRESADR*/ +#define RSTV0910_P1_DMDRESADR 0xf4c7 +#define FSTV0910_P1_SUSP_PREDCANAL 0xf4c70080 +#define FSTV0910_P1_DMDRES_VALIDCFR 0xf4c70040 +#define FSTV0910_P1_DMDRES_MEMFULL 0xf4c70030 +#define FSTV0910_P1_DMDRES_RESNBR 0xf4c7000f + +/*P1_DMDRESDATA7*/ +#define RSTV0910_P1_DMDRESDATA7 0xf4c8 +#define FSTV0910_P1_DMDRES_DATA7 0xf4c800ff + +/*P1_DMDRESDATA6*/ +#define RSTV0910_P1_DMDRESDATA6 0xf4c9 +#define FSTV0910_P1_DMDRES_DATA6 0xf4c900ff + +/*P1_DMDRESDATA5*/ +#define RSTV0910_P1_DMDRESDATA5 0xf4ca +#define FSTV0910_P1_DMDRES_DATA5 0xf4ca00ff + +/*P1_DMDRESDATA4*/ +#define RSTV0910_P1_DMDRESDATA4 0xf4cb +#define FSTV0910_P1_DMDRES_DATA4 0xf4cb00ff + +/*P1_DMDRESDATA3*/ +#define RSTV0910_P1_DMDRESDATA3 0xf4cc +#define FSTV0910_P1_DMDRES_DATA3 0xf4cc00ff + +/*P1_DMDRESDATA2*/ +#define RSTV0910_P1_DMDRESDATA2 0xf4cd +#define FSTV0910_P1_DMDRES_DATA2 0xf4cd00ff + +/*P1_DMDRESDATA1*/ +#define RSTV0910_P1_DMDRESDATA1 0xf4ce +#define FSTV0910_P1_DMDRES_DATA1 0xf4ce00ff + +/*P1_DMDRESDATA0*/ +#define RSTV0910_P1_DMDRESDATA0 0xf4cf +#define FSTV0910_P1_DMDRES_DATA0 0xf4cf00ff + +/*P1_FFEI1*/ +#define RSTV0910_P1_FFEI1 0xf4d0 +#define FSTV0910_P1_FFE_ACCI1 0xf4d001ff + +/*P1_FFEQ1*/ +#define RSTV0910_P1_FFEQ1 0xf4d1 +#define FSTV0910_P1_FFE_ACCQ1 0xf4d101ff + +/*P1_FFEI2*/ +#define RSTV0910_P1_FFEI2 0xf4d2 +#define FSTV0910_P1_FFE_ACCI2 0xf4d201ff + +/*P1_FFEQ2*/ +#define RSTV0910_P1_FFEQ2 0xf4d3 +#define FSTV0910_P1_FFE_ACCQ2 0xf4d301ff + +/*P1_FFEI3*/ +#define RSTV0910_P1_FFEI3 0xf4d4 +#define FSTV0910_P1_FFE_ACCI3 0xf4d401ff + +/*P1_FFEQ3*/ +#define RSTV0910_P1_FFEQ3 0xf4d5 +#define FSTV0910_P1_FFE_ACCQ3 0xf4d501ff + +/*P1_FFEI4*/ +#define RSTV0910_P1_FFEI4 0xf4d6 +#define FSTV0910_P1_FFE_ACCI4 0xf4d601ff + +/*P1_FFEQ4*/ +#define RSTV0910_P1_FFEQ4 0xf4d7 +#define FSTV0910_P1_FFE_ACCQ4 0xf4d701ff + +/*P1_FFECFG*/ +#define RSTV0910_P1_FFECFG 0xf4d8 +#define FSTV0910_P1_EQUALFFE_ON 0xf4d80040 +#define FSTV0910_P1_EQUAL_USEDSYMB 0xf4d80030 +#define FSTV0910_P1_MU_EQUALFFE 0xf4d80007 + +/*P1_TNRCFG2*/ +#define RSTV0910_P1_TNRCFG2 0xf4e1 +#define FSTV0910_P1_TUN_IQSWAP 0xf4e10080 +#define FSTV0910_P1_STB6110_STEP2MHZ 0xf4e10040 +#define FSTV0910_P1_STB6120_DBLI2C 0xf4e10020 +#define FSTV0910_P1_TUNER_WIDEBAND 0xf4e10010 +#define FSTV0910_P1_TUNER_OBSPAGE 0xf4e10008 +#define FSTV0910_P1_DIS_BWCALC 0xf4e10004 +#define FSTV0910_P1_SHORT_WAITSTATES 0xf4e10002 +#define FSTV0910_P1_DIS_2BWAGC1 0xf4e10001 + +/*P1_SMAPCOEF7*/ +#define RSTV0910_P1_SMAPCOEF7 0xf500 +#define FSTV0910_P1_DIS_QSCALE 0xf5000080 +#define FSTV0910_P1_SMAPCOEF_Q_LLR12 0xf500017f + +/*P1_SMAPCOEF6*/ +#define RSTV0910_P1_SMAPCOEF6 0xf501 +#define FSTV0910_P1_DIS_AGC2SCALE 0xf5010080 +#define FSTV0910_P1_DIS_16IQMULT 0xf5010040 +#define FSTV0910_P1_OLD_16APSK47 0xf5010020 +#define FSTV0910_P1_OLD_16APSK12 0xf5010010 +#define FSTV0910_P1_DIS_NEWSCALE 0xf5010008 +#define FSTV0910_P1_ADJ_8PSKLLR1 0xf5010004 +#define FSTV0910_P1_OLD_8PSKLLR1 0xf5010002 +#define FSTV0910_P1_DIS_AB8PSK 0xf5010001 + +/*P1_SMAPCOEF5*/ +#define RSTV0910_P1_SMAPCOEF5 0xf502 +#define FSTV0910_P1_DIS_8SCALE 0xf5020080 +#define FSTV0910_P1_SMAPCOEF_8P_LLR23 0xf502017f + +/*P1_NOSTHRES1*/ +#define RSTV0910_P1_NOSTHRES1 0xf509 +#define FSTV0910_P1_NOS_THRESHOLD1 0xf50900ff + +/*P1_NOSTHRES2*/ +#define RSTV0910_P1_NOSTHRES2 0xf50a +#define FSTV0910_P1_NOS_THRESHOLD2 0xf50a00ff + +/*P1_NOSDIFF1*/ +#define RSTV0910_P1_NOSDIFF1 0xf50b +#define FSTV0910_P1_NOSTHRES1_DIFF 0xf50b00ff + +/*P1_RAINFADE*/ +#define RSTV0910_P1_RAINFADE 0xf50c +#define FSTV0910_P1_NOSTHRES_DATAT 0xf50c0080 +#define FSTV0910_P1_RAINFADE_CNLIMIT 0xf50c0070 +#define FSTV0910_P1_RAINFADE_TIMEOUT 0xf50c0007 + +/*P1_NOSRAMCFG*/ +#define RSTV0910_P1_NOSRAMCFG 0xf50d +#define FSTV0910_P1_NOSRAM_DVBS2DATA 0xf50d0080 +#define FSTV0910_P1_NOSRAM_QUADRAT 0xf50d0040 +#define FSTV0910_P1_NOSRAM_ACTIVATION 0xf50d0030 +#define FSTV0910_P1_NOSRAM_CNRONLY 0xf50d0008 +#define FSTV0910_P1_NOSRAM_LGNCNR1 0xf50d0007 + +/*P1_NOSRAMPOS*/ +#define RSTV0910_P1_NOSRAMPOS 0xf50e +#define FSTV0910_P1_NOSRAM_LGNCNR0 0xf50e00f0 +#define FSTV0910_P1_NOSRAM_VALIDE 0xf50e0004 +#define FSTV0910_P1_NOSRAM_CNRVAL1 0xf50e0003 + +/*P1_NOSRAMVAL*/ +#define RSTV0910_P1_NOSRAMVAL 0xf50f +#define FSTV0910_P1_NOSRAM_CNRVAL0 0xf50f00ff + +/*P1_DMDPLHSTAT*/ +#define RSTV0910_P1_DMDPLHSTAT 0xf520 +#define FSTV0910_P1_PLH_STATISTIC 0xf52000ff + +/*P1_LOCKTIME3*/ +#define RSTV0910_P1_LOCKTIME3 0xf522 +#define FSTV0910_P1_DEMOD_LOCKTIME3 0xf52200ff + +/*P1_LOCKTIME2*/ +#define RSTV0910_P1_LOCKTIME2 0xf523 +#define FSTV0910_P1_DEMOD_LOCKTIME2 0xf52300ff + +/*P1_LOCKTIME1*/ +#define RSTV0910_P1_LOCKTIME1 0xf524 +#define FSTV0910_P1_DEMOD_LOCKTIME1 0xf52400ff + +/*P1_LOCKTIME0*/ +#define RSTV0910_P1_LOCKTIME0 0xf525 +#define FSTV0910_P1_DEMOD_LOCKTIME0 0xf52500ff + +/*P1_VITSCALE*/ +#define RSTV0910_P1_VITSCALE 0xf532 +#define FSTV0910_P1_NVTH_NOSRANGE 0xf5320080 +#define FSTV0910_P1_VERROR_MAXMODE 0xf5320040 +#define FSTV0910_P1_KDIV_MODE 0xf5320030 +#define FSTV0910_P1_NSLOWSN_LOCKED 0xf5320008 +#define FSTV0910_P1_DELOCK_PRFLOSS 0xf5320004 +#define FSTV0910_P1_DIS_RSFLOCK 0xf5320002 + +/*P1_FECM*/ +#define RSTV0910_P1_FECM 0xf533 +#define FSTV0910_P1_DSS_DVB 0xf5330080 +#define FSTV0910_P1_DEMOD_BYPASS 0xf5330040 +#define FSTV0910_P1_CMP_SLOWMODE 0xf5330020 +#define FSTV0910_P1_DSS_SRCH 0xf5330010 +#define FSTV0910_P1_DIFF_MODEVIT 0xf5330004 +#define FSTV0910_P1_SYNCVIT 0xf5330002 +#define FSTV0910_P1_IQINV 0xf5330001 + +/*P1_VTH12*/ +#define RSTV0910_P1_VTH12 0xf534 +#define FSTV0910_P1_VTH12 0xf53400ff + +/*P1_VTH23*/ +#define RSTV0910_P1_VTH23 0xf535 +#define FSTV0910_P1_VTH23 0xf53500ff + +/*P1_VTH34*/ +#define RSTV0910_P1_VTH34 0xf536 +#define FSTV0910_P1_VTH34 0xf53600ff + +/*P1_VTH56*/ +#define RSTV0910_P1_VTH56 0xf537 +#define FSTV0910_P1_VTH56 0xf53700ff + +/*P1_VTH67*/ +#define RSTV0910_P1_VTH67 0xf538 +#define FSTV0910_P1_VTH67 0xf53800ff + +/*P1_VTH78*/ +#define RSTV0910_P1_VTH78 0xf539 +#define FSTV0910_P1_VTH78 0xf53900ff + +/*P1_VITCURPUN*/ +#define RSTV0910_P1_VITCURPUN 0xf53a +#define FSTV0910_P1_CYCLESLIP_VIT 0xf53a0080 +#define FSTV0910_P1_VIT_ROTA180 0xf53a0040 +#define FSTV0910_P1_VIT_ROTA90 0xf53a0020 +#define FSTV0910_P1_VIT_CURPUN 0xf53a001f + +/*P1_VERROR*/ +#define RSTV0910_P1_VERROR 0xf53b +#define FSTV0910_P1_REGERR_VIT 0xf53b00ff + +/*P1_PRVIT*/ +#define RSTV0910_P1_PRVIT 0xf53c +#define FSTV0910_P1_DIS_VTHLOCK 0xf53c0040 +#define FSTV0910_P1_E7_8VIT 0xf53c0020 +#define FSTV0910_P1_E6_7VIT 0xf53c0010 +#define FSTV0910_P1_E5_6VIT 0xf53c0008 +#define FSTV0910_P1_E3_4VIT 0xf53c0004 +#define FSTV0910_P1_E2_3VIT 0xf53c0002 +#define FSTV0910_P1_E1_2VIT 0xf53c0001 + +/*P1_VAVSRVIT*/ +#define RSTV0910_P1_VAVSRVIT 0xf53d +#define FSTV0910_P1_AMVIT 0xf53d0080 +#define FSTV0910_P1_FROZENVIT 0xf53d0040 +#define FSTV0910_P1_SNVIT 0xf53d0030 +#define FSTV0910_P1_TOVVIT 0xf53d000c +#define FSTV0910_P1_HYPVIT 0xf53d0003 + +/*P1_VSTATUSVIT*/ +#define RSTV0910_P1_VSTATUSVIT 0xf53e +#define FSTV0910_P1_VITERBI_ON 0xf53e0080 +#define FSTV0910_P1_END_LOOPVIT 0xf53e0040 +#define FSTV0910_P1_VITERBI_DEPRF 0xf53e0020 +#define FSTV0910_P1_PRFVIT 0xf53e0010 +#define FSTV0910_P1_LOCKEDVIT 0xf53e0008 +#define FSTV0910_P1_VITERBI_DELOCK 0xf53e0004 +#define FSTV0910_P1_VIT_DEMODSEL 0xf53e0002 +#define FSTV0910_P1_VITERBI_COMPOUT 0xf53e0001 + +/*P1_VTHINUSE*/ +#define RSTV0910_P1_VTHINUSE 0xf53f +#define FSTV0910_P1_VIT_INUSE 0xf53f00ff + +/*P1_KDIV12*/ +#define RSTV0910_P1_KDIV12 0xf540 +#define FSTV0910_P1_KDIV12_MANUAL 0xf5400080 +#define FSTV0910_P1_K_DIVIDER_12 0xf540007f + +/*P1_KDIV23*/ +#define RSTV0910_P1_KDIV23 0xf541 +#define FSTV0910_P1_KDIV23_MANUAL 0xf5410080 +#define FSTV0910_P1_K_DIVIDER_23 0xf541007f + +/*P1_KDIV34*/ +#define RSTV0910_P1_KDIV34 0xf542 +#define FSTV0910_P1_KDIV34_MANUAL 0xf5420080 +#define FSTV0910_P1_K_DIVIDER_34 0xf542007f + +/*P1_KDIV56*/ +#define RSTV0910_P1_KDIV56 0xf543 +#define FSTV0910_P1_KDIV56_MANUAL 0xf5430080 +#define FSTV0910_P1_K_DIVIDER_56 0xf543007f + +/*P1_KDIV67*/ +#define RSTV0910_P1_KDIV67 0xf544 +#define FSTV0910_P1_KDIV67_MANUAL 0xf5440080 +#define FSTV0910_P1_K_DIVIDER_67 0xf544007f + +/*P1_KDIV78*/ +#define RSTV0910_P1_KDIV78 0xf545 +#define FSTV0910_P1_KDIV78_MANUAL 0xf5450080 +#define FSTV0910_P1_K_DIVIDER_78 0xf545007f + +/*P1_PDELCTRL0*/ +#define RSTV0910_P1_PDELCTRL0 0xf54f +#define FSTV0910_P1_ISIOBS_MODE 0xf54f0030 +#define FSTV0910_P1_PDELDIS_BITWISE 0xf54f0004 + +/*P1_PDELCTRL1*/ +#define RSTV0910_P1_PDELCTRL1 0xf550 +#define FSTV0910_P1_INV_MISMASK 0xf5500080 +#define FSTV0910_P1_FORCE_ACCEPTED 0xf5500040 +#define FSTV0910_P1_FILTER_EN 0xf5500020 +#define FSTV0910_P1_FORCE_PKTDELINUSE 0xf5500010 +#define FSTV0910_P1_HYSTEN 0xf5500008 +#define FSTV0910_P1_HYSTSWRST 0xf5500004 +#define FSTV0910_P1_EN_MIS00 0xf5500002 +#define FSTV0910_P1_ALGOSWRST 0xf5500001 + +/*P1_PDELCTRL2*/ +#define RSTV0910_P1_PDELCTRL2 0xf551 +#define FSTV0910_P1_FORCE_CONTINUOUS 0xf5510080 +#define FSTV0910_P1_RESET_UPKO_COUNT 0xf5510040 +#define FSTV0910_P1_USER_PKTDELIN_NB 0xf5510020 +#define FSTV0910_P1_DATA_UNBBSCRAMBLED 0xf5510008 +#define FSTV0910_P1_FORCE_LONGPKT 0xf5510004 +#define FSTV0910_P1_FRAME_MODE 0xf5510002 + +/*P1_HYSTTHRESH*/ +#define RSTV0910_P1_HYSTTHRESH 0xf554 +#define FSTV0910_P1_DELIN_LOCKTHRES 0xf55400f0 +#define FSTV0910_P1_DELIN_UNLOCKTHRES 0xf554000f + +/*P1_ISIENTRY*/ +#define RSTV0910_P1_ISIENTRY 0xf55e +#define FSTV0910_P1_ISI_ENTRY 0xf55e00ff + +/*P1_ISIBITENA*/ +#define RSTV0910_P1_ISIBITENA 0xf55f +#define FSTV0910_P1_ISI_BIT_EN 0xf55f00ff + +/*P1_MATSTR1*/ +#define RSTV0910_P1_MATSTR1 0xf560 +#define FSTV0910_P1_MATYPE_CURRENT1 0xf56000ff + +/*P1_MATSTR0*/ +#define RSTV0910_P1_MATSTR0 0xf561 +#define FSTV0910_P1_MATYPE_CURRENT0 0xf56100ff + +/*P1_UPLSTR1*/ +#define RSTV0910_P1_UPLSTR1 0xf562 +#define FSTV0910_P1_UPL_CURRENT1 0xf56200ff + +/*P1_UPLSTR0*/ +#define RSTV0910_P1_UPLSTR0 0xf563 +#define FSTV0910_P1_UPL_CURRENT0 0xf56300ff + +/*P1_DFLSTR1*/ +#define RSTV0910_P1_DFLSTR1 0xf564 +#define FSTV0910_P1_DFL_CURRENT1 0xf56400ff + +/*P1_DFLSTR0*/ +#define RSTV0910_P1_DFLSTR0 0xf565 +#define FSTV0910_P1_DFL_CURRENT0 0xf56500ff + +/*P1_SYNCSTR*/ +#define RSTV0910_P1_SYNCSTR 0xf566 +#define FSTV0910_P1_SYNC_CURRENT 0xf56600ff + +/*P1_SYNCDSTR1*/ +#define RSTV0910_P1_SYNCDSTR1 0xf567 +#define FSTV0910_P1_SYNCD_CURRENT1 0xf56700ff + +/*P1_SYNCDSTR0*/ +#define RSTV0910_P1_SYNCDSTR0 0xf568 +#define FSTV0910_P1_SYNCD_CURRENT0 0xf56800ff + +/*P1_PDELSTATUS1*/ +#define RSTV0910_P1_PDELSTATUS1 0xf569 +#define FSTV0910_P1_PKTDELIN_DELOCK 0xf5690080 +#define FSTV0910_P1_SYNCDUPDFL_BADDFL 0xf5690040 +#define FSTV0910_P1_CONTINUOUS_STREAM 0xf5690020 +#define FSTV0910_P1_UNACCEPTED_STREAM 0xf5690010 +#define FSTV0910_P1_BCH_ERROR_FLAG 0xf5690008 +#define FSTV0910_P1_BBHCRCKO 0xf5690004 +#define FSTV0910_P1_PKTDELIN_LOCK 0xf5690002 +#define FSTV0910_P1_FIRST_LOCK 0xf5690001 + +/*P1_PDELSTATUS2*/ +#define RSTV0910_P1_PDELSTATUS2 0xf56a +#define FSTV0910_P1_PKTDEL_DEMODSEL 0xf56a0080 +#define FSTV0910_P1_FRAME_MODCOD 0xf56a007c +#define FSTV0910_P1_FRAME_TYPE 0xf56a0003 + +/*P1_BBFCRCKO1*/ +#define RSTV0910_P1_BBFCRCKO1 0xf56b +#define FSTV0910_P1_BBHCRC_KOCNT1 0xf56b00ff + +/*P1_BBFCRCKO0*/ +#define RSTV0910_P1_BBFCRCKO0 0xf56c +#define FSTV0910_P1_BBHCRC_KOCNT0 0xf56c00ff + +/*P1_UPCRCKO1*/ +#define RSTV0910_P1_UPCRCKO1 0xf56d +#define FSTV0910_P1_PKTCRC_KOCNT1 0xf56d00ff + +/*P1_UPCRCKO0*/ +#define RSTV0910_P1_UPCRCKO0 0xf56e +#define FSTV0910_P1_PKTCRC_KOCNT0 0xf56e00ff + +/*P1_PDELCTRL3*/ +#define RSTV0910_P1_PDELCTRL3 0xf56f +#define FSTV0910_P1_PKTDEL_CONTFAIL 0xf56f0080 +#define FSTV0910_P1_PKTDEL_ENLONGPKT 0xf56f0040 +#define FSTV0910_P1_NOFIFO_BCHERR 0xf56f0020 +#define FSTV0910_P1_PKTDELIN_DELACMERR 0xf56f0010 +#define FSTV0910_P1_SATURATE_BBPKTKO 0xf56f0004 +#define FSTV0910_P1_PKTDEL_BCHERRCONT 0xf56f0002 +#define FSTV0910_P1_ETHERNET_DISFCS 0xf56f0001 + +/*P1_TSSTATEM*/ +#define RSTV0910_P1_TSSTATEM 0xf570 +#define FSTV0910_P1_TSDIL_ON 0xf5700080 +#define FSTV0910_P1_TSSKIPRS_ON 0xf5700040 +#define FSTV0910_P1_TSRS_ON 0xf5700020 +#define FSTV0910_P1_TSDESCRAMB_ON 0xf5700010 +#define FSTV0910_P1_TSFRAME_MODE 0xf5700008 +#define FSTV0910_P1_TS_DISABLE 0xf5700004 +#define FSTV0910_P1_TSACM_MODE 0xf5700002 +#define FSTV0910_P1_TSOUT_NOSYNC 0xf5700001 + +/*P1_TSCFGH*/ +#define RSTV0910_P1_TSCFGH 0xf572 +#define FSTV0910_P1_TSFIFO_DVBCI 0xf5720080 +#define FSTV0910_P1_TSFIFO_SERIAL 0xf5720040 +#define FSTV0910_P1_TSFIFO_TEIUPDATE 0xf5720020 +#define FSTV0910_P1_TSFIFO_DUTY50 0xf5720010 +#define FSTV0910_P1_TSFIFO_HSGNLOUT 0xf5720008 +#define FSTV0910_P1_TSFIFO_ERRMODE 0xf5720006 +#define FSTV0910_P1_RST_HWARE 0xf5720001 + +/*P1_TSCFGM*/ +#define RSTV0910_P1_TSCFGM 0xf573 +#define FSTV0910_P1_TSFIFO_MANSPEED 0xf57300c0 +#define FSTV0910_P1_TSFIFO_PERMDATA 0xf5730020 +#define FSTV0910_P1_TSFIFO_NONEWSGNL 0xf5730010 +#define FSTV0910_P1_NPD_SPECDVBS2 0xf5730004 +#define FSTV0910_P1_TSFIFO_DPUNACTIVE 0xf5730002 +#define FSTV0910_P1_TSFIFO_INVDATA 0xf5730001 + +/*P1_TSCFGL*/ +#define RSTV0910_P1_TSCFGL 0xf574 +#define FSTV0910_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 +#define FSTV0910_P1_BCHERROR_MODE 0xf5740030 +#define FSTV0910_P1_TSFIFO_NSGNL2DATA 0xf5740008 +#define FSTV0910_P1_TSFIFO_EMBINDVB 0xf5740004 +#define FSTV0910_P1_TSFIFO_BITSPEED 0xf5740003 + +/*P1_TSINSDELH*/ +#define RSTV0910_P1_TSINSDELH 0xf576 +#define FSTV0910_P1_TSDEL_SYNCBYTE 0xf5760080 +#define FSTV0910_P1_TSDEL_XXHEADER 0xf5760040 +#define FSTV0910_P1_TSDEL_BBHEADER 0xf5760020 +#define FSTV0910_P1_TSDEL_DATAFIELD 0xf5760010 +#define FSTV0910_P1_TSINSDEL_ISCR 0xf5760008 +#define FSTV0910_P1_TSINSDEL_NPD 0xf5760004 +#define FSTV0910_P1_TSINSDEL_RSPARITY 0xf5760002 +#define FSTV0910_P1_TSINSDEL_CRC8 0xf5760001 + +/*P1_TSDIVN*/ +#define RSTV0910_P1_TSDIVN 0xf579 +#define FSTV0910_P1_TSFIFO_SPEEDMODE 0xf57900c0 +#define FSTV0910_P1_BYTE_OVERSAMPLING 0xf5790038 +#define FSTV0910_P1_TSFIFO_RISEOK 0xf5790007 + +/*P1_TSCFG4*/ +#define RSTV0910_P1_TSCFG4 0xf57a +#define FSTV0910_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0 +#define FSTV0910_P1_TSFIFO_HIERSEL 0xf57a0020 +#define FSTV0910_P1_TSFIFO_SPECTOKEN 0xf57a0010 +#define FSTV0910_P1_TSFIFO_MAXMODE 0xf57a0008 +#define FSTV0910_P1_TSFIFO_FRFORCEPKT 0xf57a0004 +#define FSTV0910_P1_EXT_FECSPYIN 0xf57a0002 +#define FSTV0910_P1_TSFIFO_DELSPEEDUP 0xf57a0001 + +/*P1_TSSPEED*/ +#define RSTV0910_P1_TSSPEED 0xf580 +#define FSTV0910_P1_TSFIFO_OUTSPEED 0xf58000ff + +/*P1_TSSTATUS*/ +#define RSTV0910_P1_TSSTATUS 0xf581 +#define FSTV0910_P1_TSFIFO_LINEOK 0xf5810080 +#define FSTV0910_P1_TSFIFO_ERROR 0xf5810040 +#define FSTV0910_P1_TSFIFO_DATA7 0xf5810020 +#define FSTV0910_P1_TSFIFO_NOSYNC 0xf5810010 +#define FSTV0910_P1_ISCR_INITIALIZED 0xf5810008 +#define FSTV0910_P1_TSREGUL_ERROR 0xf5810004 +#define FSTV0910_P1_SOFFIFO_UNREGUL 0xf5810002 +#define FSTV0910_P1_DIL_READY 0xf5810001 + +/*P1_TSSTATUS2*/ +#define RSTV0910_P1_TSSTATUS2 0xf582 +#define FSTV0910_P1_TSFIFO_DEMODSEL 0xf5820080 +#define FSTV0910_P1_TSFIFOSPEED_STORE 0xf5820040 +#define FSTV0910_P1_DILXX_RESET 0xf5820020 +#define FSTV0910_P1_TSSPEED_IMPOSSIBLE 0xf5820010 +#define FSTV0910_P1_TSFIFO_LINENOK 0xf5820008 +#define FSTV0910_P1_TSFIFO_MUXSTREAM 0xf5820004 +#define FSTV0910_P1_SCRAMBDETECT 0xf5820002 +#define FSTV0910_P1_ULDTV67_FALSELOCK 0xf5820001 + +/*P1_TSBITRATE1*/ +#define RSTV0910_P1_TSBITRATE1 0xf583 +#define FSTV0910_P1_TSFIFO_BITRATE1 0xf58300ff + +/*P1_TSBITRATE0*/ +#define RSTV0910_P1_TSBITRATE0 0xf584 +#define FSTV0910_P1_TSFIFO_BITRATE0 0xf58400ff + +/*P1_ERRCTRL1*/ +#define RSTV0910_P1_ERRCTRL1 0xf598 +#define FSTV0910_P1_ERR_SOURCE1 0xf59800f0 +#define FSTV0910_P1_NUM_EVENT1 0xf5980007 + +/*P1_ERRCNT12*/ +#define RSTV0910_P1_ERRCNT12 0xf599 +#define FSTV0910_P1_ERRCNT1_OLDVALUE 0xf5990080 +#define FSTV0910_P1_ERR_CNT12 0xf599007f + +/*P1_ERRCNT11*/ +#define RSTV0910_P1_ERRCNT11 0xf59a +#define FSTV0910_P1_ERR_CNT11 0xf59a00ff + +/*P1_ERRCNT10*/ +#define RSTV0910_P1_ERRCNT10 0xf59b +#define FSTV0910_P1_ERR_CNT10 0xf59b00ff + +/*P1_ERRCTRL2*/ +#define RSTV0910_P1_ERRCTRL2 0xf59c +#define FSTV0910_P1_ERR_SOURCE2 0xf59c00f0 +#define FSTV0910_P1_NUM_EVENT2 0xf59c0007 + +/*P1_ERRCNT22*/ +#define RSTV0910_P1_ERRCNT22 0xf59d +#define FSTV0910_P1_ERRCNT2_OLDVALUE 0xf59d0080 +#define FSTV0910_P1_ERR_CNT22 0xf59d007f + +/*P1_ERRCNT21*/ +#define RSTV0910_P1_ERRCNT21 0xf59e +#define FSTV0910_P1_ERR_CNT21 0xf59e00ff + +/*P1_ERRCNT20*/ +#define RSTV0910_P1_ERRCNT20 0xf59f +#define FSTV0910_P1_ERR_CNT20 0xf59f00ff + +/*P1_FECSPY*/ +#define RSTV0910_P1_FECSPY 0xf5a0 +#define FSTV0910_P1_SPY_ENABLE 0xf5a00080 +#define FSTV0910_P1_NO_SYNCBYTE 0xf5a00040 +#define FSTV0910_P1_SERIAL_MODE 0xf5a00020 +#define FSTV0910_P1_UNUSUAL_PACKET 0xf5a00010 +#define FSTV0910_P1_BERMETER_DATAMODE 0xf5a0000c +#define FSTV0910_P1_BERMETER_LMODE 0xf5a00002 +#define FSTV0910_P1_BERMETER_RESET 0xf5a00001 + +/*P1_FSPYCFG*/ +#define RSTV0910_P1_FSPYCFG 0xf5a1 +#define FSTV0910_P1_FECSPY_INPUT 0xf5a100c0 +#define FSTV0910_P1_RST_ON_ERROR 0xf5a10020 +#define FSTV0910_P1_ONE_SHOT 0xf5a10010 +#define FSTV0910_P1_I2C_MODE 0xf5a1000c +#define FSTV0910_P1_SPY_HYSTERESIS 0xf5a10003 + +/*P1_FSPYDATA*/ +#define RSTV0910_P1_FSPYDATA 0xf5a2 +#define FSTV0910_P1_SPY_STUFFING 0xf5a20080 +#define FSTV0910_P1_NOERROR_PKTJITTER 0xf5a20040 +#define FSTV0910_P1_SPY_CNULLPKT 0xf5a20020 +#define FSTV0910_P1_SPY_OUTDATA_MODE 0xf5a2001f + +/*P1_FSPYOUT*/ +#define RSTV0910_P1_FSPYOUT 0xf5a3 +#define FSTV0910_P1_FSPY_DIRECT 0xf5a30080 +#define FSTV0910_P1_SPY_OUTDATA_BUS 0xf5a30038 +#define FSTV0910_P1_STUFF_MODE 0xf5a30007 + +/*P1_FSTATUS*/ +#define RSTV0910_P1_FSTATUS 0xf5a4 +#define FSTV0910_P1_SPY_ENDSIM 0xf5a40080 +#define FSTV0910_P1_VALID_SIM 0xf5a40040 +#define FSTV0910_P1_FOUND_SIGNAL 0xf5a40020 +#define FSTV0910_P1_DSS_SYNCBYTE 0xf5a40010 +#define FSTV0910_P1_RESULT_STATE 0xf5a4000f + +/*P1_FBERCPT4*/ +#define RSTV0910_P1_FBERCPT4 0xf5a8 +#define FSTV0910_P1_FBERMETER_CPT4 0xf5a800ff + +/*P1_FBERCPT3*/ +#define RSTV0910_P1_FBERCPT3 0xf5a9 +#define FSTV0910_P1_FBERMETER_CPT3 0xf5a900ff + +/*P1_FBERCPT2*/ +#define RSTV0910_P1_FBERCPT2 0xf5aa +#define FSTV0910_P1_FBERMETER_CPT2 0xf5aa00ff + +/*P1_FBERCPT1*/ +#define RSTV0910_P1_FBERCPT1 0xf5ab +#define FSTV0910_P1_FBERMETER_CPT1 0xf5ab00ff + +/*P1_FBERCPT0*/ +#define RSTV0910_P1_FBERCPT0 0xf5ac +#define FSTV0910_P1_FBERMETER_CPT0 0xf5ac00ff + +/*P1_FBERERR2*/ +#define RSTV0910_P1_FBERERR2 0xf5ad +#define FSTV0910_P1_FBERMETER_ERR2 0xf5ad00ff + +/*P1_FBERERR1*/ +#define RSTV0910_P1_FBERERR1 0xf5ae +#define FSTV0910_P1_FBERMETER_ERR1 0xf5ae00ff + +/*P1_FBERERR0*/ +#define RSTV0910_P1_FBERERR0 0xf5af +#define FSTV0910_P1_FBERMETER_ERR0 0xf5af00ff + +/*P1_FSPYBER*/ +#define RSTV0910_P1_FSPYBER 0xf5b2 +#define FSTV0910_P1_FSPYOBS_XORREAD 0xf5b20040 +#define FSTV0910_P1_FSPYBER_OBSMODE 0xf5b20020 +#define FSTV0910_P1_FSPYBER_SYNCBYTE 0xf5b20010 +#define FSTV0910_P1_FSPYBER_UNSYNC 0xf5b20008 +#define FSTV0910_P1_FSPYBER_CTIME 0xf5b20007 + +/*P1_SFERROR*/ +#define RSTV0910_P1_SFERROR 0xf5c1 +#define FSTV0910_P1_SFEC_REGERR_VIT 0xf5c100ff + +/*P1_SFECSTATUS*/ +#define RSTV0910_P1_SFECSTATUS 0xf5c3 +#define FSTV0910_P1_SFEC_ON 0xf5c30080 +#define FSTV0910_P1_SFEC_OFF 0xf5c30040 +#define FSTV0910_P1_LOCKEDSFEC 0xf5c30008 +#define FSTV0910_P1_SFEC_DELOCK 0xf5c30004 +#define FSTV0910_P1_SFEC_DEMODSEL 0xf5c30002 +#define FSTV0910_P1_SFEC_OVFON 0xf5c30001 + +/*P1_SFKDIV12*/ +#define RSTV0910_P1_SFKDIV12 0xf5c4 +#define FSTV0910_P1_SFECKDIV12_MAN 0xf5c40080 +#define FSTV0910_P1_SFEC_K_DIVIDER_12 0xf5c4007f + +/*P1_SFKDIV23*/ +#define RSTV0910_P1_SFKDIV23 0xf5c5 +#define FSTV0910_P1_SFECKDIV23_MAN 0xf5c50080 +#define FSTV0910_P1_SFEC_K_DIVIDER_23 0xf5c5007f + +/*P1_SFKDIV34*/ +#define RSTV0910_P1_SFKDIV34 0xf5c6 +#define FSTV0910_P1_SFECKDIV34_MAN 0xf5c60080 +#define FSTV0910_P1_SFEC_K_DIVIDER_34 0xf5c6007f + +/*P1_SFKDIV56*/ +#define RSTV0910_P1_SFKDIV56 0xf5c7 +#define FSTV0910_P1_SFECKDIV56_MAN 0xf5c70080 +#define FSTV0910_P1_SFEC_K_DIVIDER_56 0xf5c7007f + +/*P1_SFKDIV67*/ +#define RSTV0910_P1_SFKDIV67 0xf5c8 +#define FSTV0910_P1_SFECKDIV67_MAN 0xf5c80080 +#define FSTV0910_P1_SFEC_K_DIVIDER_67 0xf5c8007f + +/*P1_SFKDIV78*/ +#define RSTV0910_P1_SFKDIV78 0xf5c9 +#define FSTV0910_P1_SFECKDIV78_MAN 0xf5c90080 +#define FSTV0910_P1_SFEC_K_DIVIDER_78 0xf5c9007f + +/*P1_SFSTATUS*/ +#define RSTV0910_P1_SFSTATUS 0xf5cc +#define FSTV0910_P1_SFEC_LINEOK 0xf5cc0080 +#define FSTV0910_P1_SFEC_ERROR 0xf5cc0040 +#define FSTV0910_P1_SFEC_DATA7 0xf5cc0020 +#define FSTV0910_P1_SFEC_PKTDNBRFAIL 0xf5cc0010 +#define FSTV0910_P1_TSSFEC_DEMODSEL 0xf5cc0008 +#define FSTV0910_P1_SFEC_NOSYNC 0xf5cc0004 +#define FSTV0910_P1_SFEC_UNREGULA 0xf5cc0002 +#define FSTV0910_P1_SFEC_READY 0xf5cc0001 + +/*P1_SFDLYSET2*/ +#define RSTV0910_P1_SFDLYSET2 0xf5d0 +#define FSTV0910_P1_SFEC_OFFSET 0xf5d000c0 +#define FSTV0910_P1_RST_SFEC 0xf5d00008 +#define FSTV0910_P1_DILDLINE_ERROR 0xf5d00004 +#define FSTV0910_P1_SFEC_DISABLE 0xf5d00002 +#define FSTV0910_P1_SFEC_UNREGUL 0xf5d00001 + +/*P1_SFERRCTRL*/ +#define RSTV0910_P1_SFERRCTRL 0xf5d8 +#define FSTV0910_P1_SFEC_ERR_SOURCE 0xf5d800f0 +#define FSTV0910_P1_SFEC_NUM_EVENT 0xf5d80007 + +/*P1_SFERRCNT2*/ +#define RSTV0910_P1_SFERRCNT2 0xf5d9 +#define FSTV0910_P1_SFERRC_OLDVALUE 0xf5d90080 +#define FSTV0910_P1_SFEC_ERR_CNT2 0xf5d9007f + +/*P1_SFERRCNT1*/ +#define RSTV0910_P1_SFERRCNT1 0xf5da +#define FSTV0910_P1_SFEC_ERR_CNT1 0xf5da00ff + +/*P1_SFERRCNT0*/ +#define RSTV0910_P1_SFERRCNT0 0xf5db +#define FSTV0910_P1_SFEC_ERR_CNT0 0xf5db00ff + +/*TSGENERAL*/ +#define RSTV0910_TSGENERAL 0xf630 +#define FSTV0910_EN_LGNERROR 0xf6300080 +#define FSTV0910_TSFIFO_DISTS2PAR 0xf6300040 +#define FSTV0910_MUXSTREAM_COMPMOSE 0xf6300030 +#define FSTV0910_MUXSTREAM_OUTMODE 0xf6300008 +#define FSTV0910_TSFIFO_PERMPARAL 0xf6300006 +#define FSTV0910_RST_REEDSOLO 0xf6300001 + +/*P1_DISIRQCFG*/ +#define RSTV0910_P1_DISIRQCFG 0xf700 +#define FSTV0910_P1_ENRXEND 0xf7000040 +#define FSTV0910_P1_ENRXFIFO8B 0xf7000020 +#define FSTV0910_P1_ENTRFINISH 0xf7000010 +#define FSTV0910_P1_ENTIMEOUT 0xf7000008 +#define FSTV0910_P1_ENTXEND 0xf7000004 +#define FSTV0910_P1_ENTXFIFO64B 0xf7000002 +#define FSTV0910_P1_ENGAPBURST 0xf7000001 + +/*P1_DISIRQSTAT*/ +#define RSTV0910_P1_DISIRQSTAT 0xf701 +#define FSTV0910_P1_IRQRXEND 0xf7010040 +#define FSTV0910_P1_IRQRXFIFO8B 0xf7010020 +#define FSTV0910_P1_IRQTRFINISH 0xf7010010 +#define FSTV0910_P1_IRQTIMEOUT 0xf7010008 +#define FSTV0910_P1_IRQTXEND 0xf7010004 +#define FSTV0910_P1_IRQTXFIFO64B 0xf7010002 +#define FSTV0910_P1_IRQGAPBURST 0xf7010001 + +/*P1_DISTXCFG*/ +#define RSTV0910_P1_DISTXCFG 0xf702 +#define FSTV0910_P1_DISTX_RESET 0xf7020080 +#define FSTV0910_P1_TIM_OFF 0xf7020040 +#define FSTV0910_P1_TIM_CMD 0xf7020030 +#define FSTV0910_P1_ENVELOP 0xf7020008 +#define FSTV0910_P1_DIS_PRECHARGE 0xf7020004 +#define FSTV0910_P1_DISEQC_MODE 0xf7020003 + +/*P1_DISTXSTATUS*/ +#define RSTV0910_P1_DISTXSTATUS 0xf703 +#define FSTV0910_P1_TX_FIFO_FULL 0xf7030040 +#define FSTV0910_P1_TX_IDLE 0xf7030020 +#define FSTV0910_P1_GAP_BURST 0xf7030010 +#define FSTV0910_P1_TX_FIFO64B 0xf7030008 +#define FSTV0910_P1_TX_END 0xf7030004 +#define FSTV0910_P1_TR_TIMEOUT 0xf7030002 +#define FSTV0910_P1_TR_FINISH 0xf7030001 + +/*P1_DISTXBYTES*/ +#define RSTV0910_P1_DISTXBYTES 0xf704 +#define FSTV0910_P1_TXFIFO_BYTES 0xf70400ff + +/*P1_DISTXFIFO*/ +#define RSTV0910_P1_DISTXFIFO 0xf705 +#define FSTV0910_P1_DISEQC_TX_FIFO 0xf70500ff + +/*P1_DISTXF22*/ +#define RSTV0910_P1_DISTXF22 0xf706 +#define FSTV0910_P1_F22TX 0xf70600ff + +/*P1_DISTIMEOCFG*/ +#define RSTV0910_P1_DISTIMEOCFG 0xf708 +#define FSTV0910_P1_RXCHOICE 0xf7080006 +#define FSTV0910_P1_TIMEOUT_OFF 0xf7080001 + +/*P1_DISTIMEOUT*/ +#define RSTV0910_P1_DISTIMEOUT 0xf709 +#define FSTV0910_P1_TIMEOUT_COUNT 0xf70900ff + +/*P1_DISRXCFG*/ +#define RSTV0910_P1_DISRXCFG 0xf70a +#define FSTV0910_P1_DISRX_RESET 0xf70a0080 +#define FSTV0910_P1_EXTENVELOP 0xf70a0040 +#define FSTV0910_P1_PINSELECT 0xf70a0038 +#define FSTV0910_P1_IGNORE_SHORT22K 0xf70a0004 +#define FSTV0910_P1_SIGNED_RXIN 0xf70a0002 +#define FSTV0910_P1_DISRX_ON 0xf70a0001 + +/*P1_DISRXSTAT1*/ +#define RSTV0910_P1_DISRXSTAT1 0xf70b +#define FSTV0910_P1_RXEND 0xf70b0080 +#define FSTV0910_P1_RXACTIVE 0xf70b0040 +#define FSTV0910_P1_RXDETECT 0xf70b0020 +#define FSTV0910_P1_CONTTONE 0xf70b0010 +#define FSTV0910_P1_8BFIFOREADY 0xf70b0008 +#define FSTV0910_P1_FIFOEMPTY 0xf70b0004 + +/*P1_DISRXSTAT0*/ +#define RSTV0910_P1_DISRXSTAT0 0xf70c +#define FSTV0910_P1_RXFAIL 0xf70c0080 +#define FSTV0910_P1_FIFOPFAIL 0xf70c0040 +#define FSTV0910_P1_RXNONBYTE 0xf70c0020 +#define FSTV0910_P1_FIFOOVF 0xf70c0010 +#define FSTV0910_P1_SHORT22K 0xf70c0008 +#define FSTV0910_P1_RXMSGLOST 0xf70c0004 + +/*P1_DISRXBYTES*/ +#define RSTV0910_P1_DISRXBYTES 0xf70d +#define FSTV0910_P1_RXFIFO_BYTES 0xf70d001f + +/*P1_DISRXPARITY1*/ +#define RSTV0910_P1_DISRXPARITY1 0xf70e +#define FSTV0910_P1_DISRX_PARITY1 0xf70e00ff + +/*P1_DISRXPARITY0*/ +#define RSTV0910_P1_DISRXPARITY0 0xf70f +#define FSTV0910_P1_DISRX_PARITY0 0xf70f00ff + +/*P1_DISRXFIFO*/ +#define RSTV0910_P1_DISRXFIFO 0xf710 +#define FSTV0910_P1_DISEQC_RX_FIFO 0xf71000ff + +/*P1_DISRXDC1*/ +#define RSTV0910_P1_DISRXDC1 0xf711 +#define FSTV0910_P1_DC_VALUE1 0xf7110103 + +/*P1_DISRXDC0*/ +#define RSTV0910_P1_DISRXDC0 0xf712 +#define FSTV0910_P1_DC_VALUE0 0xf71200ff + +/*P1_DISRXF221*/ +#define RSTV0910_P1_DISRXF221 0xf714 +#define FSTV0910_P1_F22RX1 0xf714000f + +/*P1_DISRXF220*/ +#define RSTV0910_P1_DISRXF220 0xf715 +#define FSTV0910_P1_F22RX0 0xf71500ff + +/*P1_DISRXF100*/ +#define RSTV0910_P1_DISRXF100 0xf716 +#define FSTV0910_P1_F100RX 0xf71600ff + +/*P1_DISRXSHORT22K*/ +#define RSTV0910_P1_DISRXSHORT22K 0xf71c +#define FSTV0910_P1_SHORT22K_LENGTH 0xf71c001f + +/*P1_ACRPRESC*/ +#define RSTV0910_P1_ACRPRESC 0xf71e +#define FSTV0910_P1_ACR_CODFRDY 0xf71e0008 +#define FSTV0910_P1_ACR_PRESC 0xf71e0007 + +/*P1_ACRDIV*/ +#define RSTV0910_P1_ACRDIV 0xf71f +#define FSTV0910_P1_ACR_DIV 0xf71f00ff + +/*P2_DISIRQCFG*/ +#define RSTV0910_P2_DISIRQCFG 0xf740 +#define FSTV0910_P2_ENRXEND 0xf7400040 +#define FSTV0910_P2_ENRXFIFO8B 0xf7400020 +#define FSTV0910_P2_ENTRFINISH 0xf7400010 +#define FSTV0910_P2_ENTIMEOUT 0xf7400008 +#define FSTV0910_P2_ENTXEND 0xf7400004 +#define FSTV0910_P2_ENTXFIFO64B 0xf7400002 +#define FSTV0910_P2_ENGAPBURST 0xf7400001 + +/*P2_DISIRQSTAT*/ +#define RSTV0910_P2_DISIRQSTAT 0xf741 +#define FSTV0910_P2_IRQRXEND 0xf7410040 +#define FSTV0910_P2_IRQRXFIFO8B 0xf7410020 +#define FSTV0910_P2_IRQTRFINISH 0xf7410010 +#define FSTV0910_P2_IRQTIMEOUT 0xf7410008 +#define FSTV0910_P2_IRQTXEND 0xf7410004 +#define FSTV0910_P2_IRQTXFIFO64B 0xf7410002 +#define FSTV0910_P2_IRQGAPBURST 0xf7410001 + +/*P2_DISTXCFG*/ +#define RSTV0910_P2_DISTXCFG 0xf742 +#define FSTV0910_P2_DISTX_RESET 0xf7420080 +#define FSTV0910_P2_TIM_OFF 0xf7420040 +#define FSTV0910_P2_TIM_CMD 0xf7420030 +#define FSTV0910_P2_ENVELOP 0xf7420008 +#define FSTV0910_P2_DIS_PRECHARGE 0xf7420004 +#define FSTV0910_P2_DISEQC_MODE 0xf7420003 + +/*P2_DISTXSTATUS*/ +#define RSTV0910_P2_DISTXSTATUS 0xf743 +#define FSTV0910_P2_TX_FIFO_FULL 0xf7430040 +#define FSTV0910_P2_TX_IDLE 0xf7430020 +#define FSTV0910_P2_GAP_BURST 0xf7430010 +#define FSTV0910_P2_TX_FIFO64B 0xf7430008 +#define FSTV0910_P2_TX_END 0xf7430004 +#define FSTV0910_P2_TR_TIMEOUT 0xf7430002 +#define FSTV0910_P2_TR_FINISH 0xf7430001 + +/*P2_DISTXBYTES*/ +#define RSTV0910_P2_DISTXBYTES 0xf744 +#define FSTV0910_P2_TXFIFO_BYTES 0xf74400ff + +/*P2_DISTXFIFO*/ +#define RSTV0910_P2_DISTXFIFO 0xf745 +#define FSTV0910_P2_DISEQC_TX_FIFO 0xf74500ff + +/*P2_DISTXF22*/ +#define RSTV0910_P2_DISTXF22 0xf746 +#define FSTV0910_P2_F22TX 0xf74600ff + +/*P2_DISTIMEOCFG*/ +#define RSTV0910_P2_DISTIMEOCFG 0xf748 +#define FSTV0910_P2_RXCHOICE 0xf7480006 +#define FSTV0910_P2_TIMEOUT_OFF 0xf7480001 + +/*P2_DISTIMEOUT*/ +#define RSTV0910_P2_DISTIMEOUT 0xf749 +#define FSTV0910_P2_TIMEOUT_COUNT 0xf74900ff + +/*P2_DISRXCFG*/ +#define RSTV0910_P2_DISRXCFG 0xf74a +#define FSTV0910_P2_DISRX_RESET 0xf74a0080 +#define FSTV0910_P2_EXTENVELOP 0xf74a0040 +#define FSTV0910_P2_PINSELECT 0xf74a0038 +#define FSTV0910_P2_IGNORE_SHORT22K 0xf74a0004 +#define FSTV0910_P2_SIGNED_RXIN 0xf74a0002 +#define FSTV0910_P2_DISRX_ON 0xf74a0001 + +/*P2_DISRXSTAT1*/ +#define RSTV0910_P2_DISRXSTAT1 0xf74b +#define FSTV0910_P2_RXEND 0xf74b0080 +#define FSTV0910_P2_RXACTIVE 0xf74b0040 +#define FSTV0910_P2_RXDETECT 0xf74b0020 +#define FSTV0910_P2_CONTTONE 0xf74b0010 +#define FSTV0910_P2_8BFIFOREADY 0xf74b0008 +#define FSTV0910_P2_FIFOEMPTY 0xf74b0004 + +/*P2_DISRXSTAT0*/ +#define RSTV0910_P2_DISRXSTAT0 0xf74c +#define FSTV0910_P2_RXFAIL 0xf74c0080 +#define FSTV0910_P2_FIFOPFAIL 0xf74c0040 +#define FSTV0910_P2_RXNONBYTE 0xf74c0020 +#define FSTV0910_P2_FIFOOVF 0xf74c0010 +#define FSTV0910_P2_SHORT22K 0xf74c0008 +#define FSTV0910_P2_RXMSGLOST 0xf74c0004 + +/*P2_DISRXBYTES*/ +#define RSTV0910_P2_DISRXBYTES 0xf74d +#define FSTV0910_P2_RXFIFO_BYTES 0xf74d001f + +/*P2_DISRXPARITY1*/ +#define RSTV0910_P2_DISRXPARITY1 0xf74e +#define FSTV0910_P2_DISRX_PARITY1 0xf74e00ff + +/*P2_DISRXPARITY0*/ +#define RSTV0910_P2_DISRXPARITY0 0xf74f +#define FSTV0910_P2_DISRX_PARITY0 0xf74f00ff + +/*P2_DISRXFIFO*/ +#define RSTV0910_P2_DISRXFIFO 0xf750 +#define FSTV0910_P2_DISEQC_RX_FIFO 0xf75000ff + +/*P2_DISRXDC1*/ +#define RSTV0910_P2_DISRXDC1 0xf751 +#define FSTV0910_P2_DC_VALUE1 0xf7510103 + +/*P2_DISRXDC0*/ +#define RSTV0910_P2_DISRXDC0 0xf752 +#define FSTV0910_P2_DC_VALUE0 0xf75200ff + +/*P2_DISRXF221*/ +#define RSTV0910_P2_DISRXF221 0xf754 +#define FSTV0910_P2_F22RX1 0xf754000f + +/*P2_DISRXF220*/ +#define RSTV0910_P2_DISRXF220 0xf755 +#define FSTV0910_P2_F22RX0 0xf75500ff + +/*P2_DISRXF100*/ +#define RSTV0910_P2_DISRXF100 0xf756 +#define FSTV0910_P2_F100RX 0xf75600ff + +/*P2_DISRXSHORT22K*/ +#define RSTV0910_P2_DISRXSHORT22K 0xf75c +#define FSTV0910_P2_SHORT22K_LENGTH 0xf75c001f + +/*P2_ACRPRESC*/ +#define RSTV0910_P2_ACRPRESC 0xf75e +#define FSTV0910_P2_ACR_CODFRDY 0xf75e0008 +#define FSTV0910_P2_ACR_PRESC 0xf75e0007 + +/*P2_ACRDIV*/ +#define RSTV0910_P2_ACRDIV 0xf75f +#define FSTV0910_P2_ACR_DIV 0xf75f00ff + +/*P1_NBITER_NF4*/ +#define RSTV0910_P1_NBITER_NF4 0xfa03 +#define FSTV0910_P1_NBITER_NF_QPSK_1_2 0xfa0300ff + +/*P1_NBITER_NF5*/ +#define RSTV0910_P1_NBITER_NF5 0xfa04 +#define FSTV0910_P1_NBITER_NF_QPSK_3_5 0xfa0400ff + +/*P1_NBITER_NF6*/ +#define RSTV0910_P1_NBITER_NF6 0xfa05 +#define FSTV0910_P1_NBITER_NF_QPSK_2_3 0xfa0500ff + +/*P1_NBITER_NF7*/ +#define RSTV0910_P1_NBITER_NF7 0xfa06 +#define FSTV0910_P1_NBITER_NF_QPSK_3_4 0xfa0600ff + +/*P1_NBITER_NF8*/ +#define RSTV0910_P1_NBITER_NF8 0xfa07 +#define FSTV0910_P1_NBITER_NF_QPSK_4_5 0xfa0700ff + +/*P1_NBITER_NF9*/ +#define RSTV0910_P1_NBITER_NF9 0xfa08 +#define FSTV0910_P1_NBITER_NF_QPSK_5_6 0xfa0800ff + +/*P1_NBITER_NF10*/ +#define RSTV0910_P1_NBITER_NF10 0xfa09 +#define FSTV0910_P1_NBITER_NF_QPSK_8_9 0xfa0900ff + +/*P1_NBITER_NF11*/ +#define RSTV0910_P1_NBITER_NF11 0xfa0a +#define FSTV0910_P1_NBITER_NF_QPSK_9_10 0xfa0a00ff + +/*P1_NBITER_NF12*/ +#define RSTV0910_P1_NBITER_NF12 0xfa0b +#define FSTV0910_P1_NBITER_NF_8PSK_3_5 0xfa0b00ff + +/*P1_NBITER_NF13*/ +#define RSTV0910_P1_NBITER_NF13 0xfa0c +#define FSTV0910_P1_NBITER_NF_8PSK_2_3 0xfa0c00ff + +/*P1_NBITER_NF14*/ +#define RSTV0910_P1_NBITER_NF14 0xfa0d +#define FSTV0910_P1_NBITER_NF_8PSK_3_4 0xfa0d00ff + +/*P1_NBITER_NF15*/ +#define RSTV0910_P1_NBITER_NF15 0xfa0e +#define FSTV0910_P1_NBITER_NF_8PSK_5_6 0xfa0e00ff + +/*P1_NBITER_NF16*/ +#define RSTV0910_P1_NBITER_NF16 0xfa0f +#define FSTV0910_P1_NBITER_NF_8PSK_8_9 0xfa0f00ff + +/*P1_NBITER_NF17*/ +#define RSTV0910_P1_NBITER_NF17 0xfa10 +#define FSTV0910_P1_NBITER_NF_8PSK_9_10 0xfa1000ff + +/*GAINLLR_NF4*/ +#define RSTV0910_GAINLLR_NF4 0xfa43 +#define FSTV0910_GAINLLR_NF_QPSK_1_2 0xfa43007f + +/*GAINLLR_NF5*/ +#define RSTV0910_GAINLLR_NF5 0xfa44 +#define FSTV0910_GAINLLR_NF_QPSK_3_5 0xfa44007f + +/*GAINLLR_NF6*/ +#define RSTV0910_GAINLLR_NF6 0xfa45 +#define FSTV0910_GAINLLR_NF_QPSK_2_3 0xfa45007f + +/*GAINLLR_NF7*/ +#define RSTV0910_GAINLLR_NF7 0xfa46 +#define FSTV0910_GAINLLR_NF_QPSK_3_4 0xfa46007f + +/*GAINLLR_NF8*/ +#define RSTV0910_GAINLLR_NF8 0xfa47 +#define FSTV0910_GAINLLR_NF_QPSK_4_5 0xfa47007f + +/*GAINLLR_NF9*/ +#define RSTV0910_GAINLLR_NF9 0xfa48 +#define FSTV0910_GAINLLR_NF_QPSK_5_6 0xfa48007f + +/*GAINLLR_NF10*/ +#define RSTV0910_GAINLLR_NF10 0xfa49 +#define FSTV0910_GAINLLR_NF_QPSK_8_9 0xfa49007f + +/*GAINLLR_NF11*/ +#define RSTV0910_GAINLLR_NF11 0xfa4a +#define FSTV0910_GAINLLR_NF_QPSK_9_10 0xfa4a007f + +/*GAINLLR_NF12*/ +#define RSTV0910_GAINLLR_NF12 0xfa4b +#define FSTV0910_GAINLLR_NF_8PSK_3_5 0xfa4b007f + +/*GAINLLR_NF13*/ +#define RSTV0910_GAINLLR_NF13 0xfa4c +#define FSTV0910_GAINLLR_NF_8PSK_2_3 0xfa4c007f + +/*GAINLLR_NF14*/ +#define RSTV0910_GAINLLR_NF14 0xfa4d +#define FSTV0910_GAINLLR_NF_8PSK_3_4 0xfa4d007f + +/*GAINLLR_NF15*/ +#define RSTV0910_GAINLLR_NF15 0xfa4e +#define FSTV0910_GAINLLR_NF_8PSK_5_6 0xfa4e007f + +/*GAINLLR_NF16*/ +#define RSTV0910_GAINLLR_NF16 0xfa4f +#define FSTV0910_GAINLLR_NF_8PSK_8_9 0xfa4f007f + +/*GAINLLR_NF17*/ +#define RSTV0910_GAINLLR_NF17 0xfa50 +#define FSTV0910_GAINLLR_NF_8PSK_9_10 0xfa50007f + +/*CFGEXT*/ +#define RSTV0910_CFGEXT 0xfa80 +#define FSTV0910_BYPFIFOBCH 0xfa800080 +#define FSTV0910_BYPBCH 0xfa800040 +#define FSTV0910_BYPLDPC 0xfa800020 +#define FSTV0910_BYPFIFOBCHF 0xfa800010 +#define FSTV0910_INVLLRSIGN 0xfa800008 +#define FSTV0910_SHORTMULT 0xfa800004 +#define FSTV0910_ENSTOPDEC 0xfa800002 + +/*GENCFG*/ +#define RSTV0910_GENCFG 0xfa86 +#define FSTV0910_LEG_ITER 0xfa860040 +#define FSTV0910_NOSHFRD1 0xfa860020 +#define FSTV0910_BROADCAST 0xfa860010 +#define FSTV0910_NOSHFRD2 0xfa860008 +#define FSTV0910_BCHERRFLAG 0xfa860004 +#define FSTV0910_CROSSINPUT 0xfa860002 +#define FSTV0910_DDEMOD 0xfa860001 + +/*LDPCERR1*/ +#define RSTV0910_LDPCERR1 0xfa96 +#define FSTV0910_LDPC_ERRORS1 0xfa9600ff + +/*LDPCERR0*/ +#define RSTV0910_LDPCERR0 0xfa97 +#define FSTV0910_LDPC_ERRORS0 0xfa9700ff + +/*BCHERR*/ +#define RSTV0910_BCHERR 0xfa98 +#define FSTV0910_ERRORFLAG 0xfa980010 +#define FSTV0910_BCH_ERRORS_COUNTER 0xfa98000f + +/*P1_MAXEXTRAITER*/ +#define RSTV0910_P1_MAXEXTRAITER 0xfab1 +#define FSTV0910_P1_MAX_EXTRA_ITER 0xfab100ff + +/*P2_MAXEXTRAITER*/ +#define RSTV0910_P2_MAXEXTRAITER 0xfab6 +#define FSTV0910_P2_MAX_EXTRA_ITER 0xfab600ff + +/*P1_STATUSITER*/ +#define RSTV0910_P1_STATUSITER 0xfabc +#define FSTV0910_P1_STATUS_ITER 0xfabc00ff + +/*P1_STATUSMAXITER*/ +#define RSTV0910_P1_STATUSMAXITER 0xfabd +#define FSTV0910_P1_STATUS_MAX_ITER 0xfabd00ff + +/*P2_STATUSITER*/ +#define RSTV0910_P2_STATUSITER 0xfabe +#define FSTV0910_P2_STATUS_ITER 0xfabe00ff + +/*P2_STATUSMAXITER*/ +#define RSTV0910_P2_STATUSMAXITER 0xfabf +#define FSTV0910_P2_STATUS_MAX_ITER 0xfabf00ff + +/*P2_NBITER_NF4*/ +#define RSTV0910_P2_NBITER_NF4 0xfac3 +#define FSTV0910_P2_NBITER_NF_QPSK_1_2 0xfac300ff + +/*P2_NBITER_NF5*/ +#define RSTV0910_P2_NBITER_NF5 0xfac4 +#define FSTV0910_P2_NBITER_NF_QPSK_3_5 0xfac400ff + +/*P2_NBITER_NF6*/ +#define RSTV0910_P2_NBITER_NF6 0xfac5 +#define FSTV0910_P2_NBITER_NF_QPSK_2_3 0xfac500ff + +/*P2_NBITER_NF7*/ +#define RSTV0910_P2_NBITER_NF7 0xfac6 +#define FSTV0910_P2_NBITER_NF_QPSK_3_4 0xfac600ff + +/*P2_NBITER_NF8*/ +#define RSTV0910_P2_NBITER_NF8 0xfac7 +#define FSTV0910_P2_NBITER_NF_QPSK_4_5 0xfac700ff + +/*P2_NBITER_NF9*/ +#define RSTV0910_P2_NBITER_NF9 0xfac8 +#define FSTV0910_P2_NBITER_NF_QPSK_5_6 0xfac800ff + +/*P2_NBITER_NF10*/ +#define RSTV0910_P2_NBITER_NF10 0xfac9 +#define FSTV0910_P2_NBITER_NF_QPSK_8_9 0xfac900ff + +/*P2_NBITER_NF11*/ +#define RSTV0910_P2_NBITER_NF11 0xfaca +#define FSTV0910_P2_NBITER_NF_QPSK_9_10 0xfaca00ff + +/*P2_NBITER_NF12*/ +#define RSTV0910_P2_NBITER_NF12 0xfacb +#define FSTV0910_P2_NBITER_NF_8PSK_3_5 0xfacb00ff + +/*P2_NBITER_NF13*/ +#define RSTV0910_P2_NBITER_NF13 0xfacc +#define FSTV0910_P2_NBITER_NF_8PSK_2_3 0xfacc00ff + +/*P2_NBITER_NF14*/ +#define RSTV0910_P2_NBITER_NF14 0xfacd +#define FSTV0910_P2_NBITER_NF_8PSK_3_4 0xfacd00ff + +/*P2_NBITER_NF15*/ +#define RSTV0910_P2_NBITER_NF15 0xface +#define FSTV0910_P2_NBITER_NF_8PSK_5_6 0xface00ff + +/*P2_NBITER_NF16*/ +#define RSTV0910_P2_NBITER_NF16 0xfacf +#define FSTV0910_P2_NBITER_NF_8PSK_8_9 0xfacf00ff + +/*P2_NBITER_NF17*/ +#define RSTV0910_P2_NBITER_NF17 0xfad0 +#define FSTV0910_P2_NBITER_NF_8PSK_9_10 0xfad000ff + +/*TSTRES0*/ +#define RSTV0910_TSTRES0 0xff11 +#define FSTV0910_FRESFEC 0xff110080 +#define FSTV0910_FRESTS 0xff110040 +#define FSTV0910_FRESVIT1 0xff110020 +#define FSTV0910_FRESVIT2 0xff110010 +#define FSTV0910_FRESSYM1 0xff110008 +#define FSTV0910_FRESSYM2 0xff110004 +#define FSTV0910_FRESMAS 0xff110002 +#define FSTV0910_FRESINT 0xff110001 + +/*P2_TCTL4*/ +#define RSTV0910_P2_TCTL4 0xff28 +#define FSTV0910_P2_CFR2TOCFR1_DVBS1 0xff2800c0 +#define FSTV0910_P2_TSTINV_PHERR 0xff280020 +#define FSTV0910_P2_EN_PLHCALC 0xff280010 +#define FSTV0910_P2_TETA3L_RSTTETA3D 0xff280008 +#define FSTV0910_P2_DIS_FORCEBETA2 0xff280004 +#define FSTV0910_P2_CAR3_NOTRACEBACK 0xff280002 +#define FSTV0910_P2_CAR3_NOFORWARD 0xff280001 + +/*P1_TCTL4*/ +#define RSTV0910_P1_TCTL4 0xff48 +#define FSTV0910_P1_CFR2TOCFR1_DVBS1 0xff4800c0 +#define FSTV0910_P1_TSTINV_PHERR 0xff480020 +#define FSTV0910_P1_EN_PLHCALC 0xff480010 +#define FSTV0910_P1_TETA3L_RSTTETA3D 0xff480008 +#define FSTV0910_P1_DIS_FORCEBETA2 0xff480004 +#define FSTV0910_P1_CAR3_NOTRACEBACK 0xff480002 +#define FSTV0910_P1_CAR3_NOFORWARD 0xff480001 + +#define STV0910_NBREGS 735 +#define STV0910_NBFIELDS 1776