mirror of
https://github.com/DigitalDevices/dddvb.git
synced 2023-10-10 13:37:43 +02:00
add frequency and center frequency setting for SDR modulator
This commit is contained in:
parent
4070713556
commit
8931ae4d9e
@ -1,7 +1,7 @@
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/*
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/*
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* ddbridge.c: Digital Devices PCIe bridge driver
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* ddbridge.c: Digital Devices PCIe bridge driver
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*
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*
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* Copyright (C) 2010-2015 Digital Devices GmbH
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* Copyright (C) 2010-2017 Digital Devices GmbH
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* Marcus Metzler <mocm@metzlerbros.de>
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* Marcus Metzler <mocm@metzlerbros.de>
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* Ralph Metzler <rjkm@metzlerbros.de>
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* Ralph Metzler <rjkm@metzlerbros.de>
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*
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*
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@ -1481,14 +1481,84 @@ void ddbridge_mod_rate_handler(unsigned long data)
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PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement);
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PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement);
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}
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}
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static int mod_set_ari(struct ddb_mod *mod, u32 rate)
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static int mod3_set_base_frequency(struct ddb *dev, u32 frequency)
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{
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u64 tmp;
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if (frequency % 1000)
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return -EINVAL;
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if ((frequency < 114000000) || (frequency > 874000000))
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return -EINVAL;
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dev->mod_base.frequency = frequency;
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tmp = frequency;
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tmp <<= 33;
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tmp = div64_s64(tmp, 4915200000);
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printk("set base frequency = %u regs = 0x%08llx\n", frequency, tmp);
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ddbwritel(dev, (u32) tmp, RFDAC_FCW);
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return 0;
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}
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static void mod3_set_cfcw(struct ddb_mod *mod, u32 f)
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{
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struct ddb *dev = mod->port->dev;
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s32 freq = f;
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s32 dcf = dev->mod_base.frequency;
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s64 tmp, srdac = 245760000;
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u32 cfcw;
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tmp = ((s64) (freq - dcf)) << 32;
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tmp = div64_s64(tmp, srdac);
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cfcw = (u32) tmp;
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printk("f=%u cfcw = %08x nr = %u\n", f, cfcw, mod->port->nr);
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ddbwritel(dev, cfcw, SDR_CHANNEL_CFCW(mod->port->nr));
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}
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static int mod3_set_frequency(struct ddb_mod *mod, u32 frequency)
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{
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struct ddb *dev = mod->port->dev;
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#if 0
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if (frequency % 1000)
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return -EINVAL;
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if ((frequency < 114000000) || (frequency > 874000000))
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return -EINVAL;
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if (frequency > dev->mod_base.frequency)
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if (frequency - dev->mod_base.frequency > 100000000)
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return -EINVAL;
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else
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if (dev->mod_base.frequency - frequency > 100000000)
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return -EINVAL;
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#endif
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mod3_set_cfcw(mod, frequency);
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return 0;
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}
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static int mod3_set_ari(struct ddb_mod *mod, u32 rate)
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{
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{
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ddbwritel(mod->port->dev, rate, SDR_CHANNEL_ARICW(mod->port->nr));
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ddbwritel(mod->port->dev, rate, SDR_CHANNEL_ARICW(mod->port->nr));
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return 0;
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return 0;
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}
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}
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static int mod3_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
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{
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switch(tvp->cmd) {
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case MODULATOR_OUTPUT_ARI:
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return mod3_set_ari(mod, tvp->u.data);
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case MODULATOR_FREQUENCY:
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return mod3_set_frequency(mod, tvp->u.data);
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case MODULATOR_BASE_FREQUENCY:
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return mod3_set_base_frequency(mod->port->dev, tvp->u.data);
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}
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return -EINVAL;
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}
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static int mod_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
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static int mod_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
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{
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{
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if (mod->port->dev->link[0].info->version == 3)
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return mod3_prop_proc(mod, tvp);
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switch(tvp->cmd) {
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switch(tvp->cmd) {
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case MODULATOR_SYMBOL_RATE:
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case MODULATOR_SYMBOL_RATE:
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return mod_set_symbolrate(mod, tvp->u.data);
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return mod_set_symbolrate(mod, tvp->u.data);
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@ -1505,8 +1575,6 @@ static int mod_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
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case MODULATOR_INPUT_BITRATE:
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case MODULATOR_INPUT_BITRATE:
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return mod_set_ibitrate(mod, tvp->u.data);
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return mod_set_ibitrate(mod, tvp->u.data);
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case MODULATOR_OUTPUT_ARI:
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return mod_set_ari(mod, tvp->u.data);
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}
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}
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return 0;
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return 0;
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}
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}
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@ -1518,7 +1586,9 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
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struct ddb *dev = output->port->dev;
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struct ddb *dev = output->port->dev;
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struct ddb_mod *mod = &dev->mod[output->nr];
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struct ddb_mod *mod = &dev->mod[output->nr];
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int ret = 0;
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int ret = 0;
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if (dev->link[0].info->version == 3 && cmd != FE_SET_PROPERTY)
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return -EINVAL;
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switch (cmd) {
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switch (cmd) {
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case FE_SET_PROPERTY:
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case FE_SET_PROPERTY:
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{
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{
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@ -1666,8 +1736,6 @@ static void mod_set_sdr_table(struct ddb_mod *mod, u32 *tab, u32 len)
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ddbwritel(dev, tab[i], SDR_CHANNEL_SETFIR(mod->port->nr));
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ddbwritel(dev, tab[i], SDR_CHANNEL_SETFIR(mod->port->nr));
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}
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}
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static int rfdac_init(struct ddb *dev)
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static int rfdac_init(struct ddb *dev)
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{
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{
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int i;
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int i;
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@ -1716,22 +1784,6 @@ static int rfdac_init(struct ddb *dev)
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return 0;
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return 0;
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}
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}
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static void mod_set_cfcw(struct ddb_mod *mod, int i)
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{
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struct ddb *dev = mod->port->dev;
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s32 freq = 182250000 + 7000000 * i;
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s32 dcf = 188000000;
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s64 tmp, srdac = 245760000;
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u32 cfcw;
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tmp = ((s64) (freq - dcf)) << 32;
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tmp = div64_s64(tmp, srdac);
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cfcw = (u32) tmp;
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printk("cfcw = %08x nr = %u\n", cfcw, mod->port->nr);
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ddbwritel(dev, cfcw, SDR_CHANNEL_CFCW(mod->port->nr));
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}
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static int mod_init_3(struct ddb *dev, u32 Frequency)
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static int mod_init_3(struct ddb *dev, u32 Frequency)
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{
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{
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int streams = dev->link[0].info->port_num;
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int streams = dev->link[0].info->port_num;
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@ -1758,13 +1810,14 @@ static int mod_init_3(struct ddb *dev, u32 Frequency)
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ddbwritel(dev, 0x1800, 0x244);
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ddbwritel(dev, 0x1800, 0x244);
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ddbwritel(dev, 0x01, 0x240);
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ddbwritel(dev, 0x01, 0x240);
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//msleep(500);
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//msleep(500);
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mod3_set_base_frequency(dev, 188000000);
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for (i = 0; i < streams; i++) {
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for (i = 0; i < streams; i++) {
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struct ddb_mod *mod = &dev->mod[i];
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struct ddb_mod *mod = &dev->mod[i];
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ddbwritel(dev, 0x00, SDR_CHANNEL_CONTROL(i));
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ddbwritel(dev, 0x00, SDR_CHANNEL_CONTROL(i));
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ddbwritel(dev, 0x06, SDR_CHANNEL_CONFIG(i));
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ddbwritel(dev, 0x06, SDR_CHANNEL_CONFIG(i));
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ddbwritel(dev, 0x70800000, SDR_CHANNEL_ARICW(i));
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ddbwritel(dev, 0x70800000, SDR_CHANNEL_ARICW(i));
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mod_set_cfcw(mod, i);
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mod3_set_frequency(mod, 182250000 + 7000000 * i);
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ddbwritel(dev, 0x00011f80, SDR_CHANNEL_RGAIN(i));
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ddbwritel(dev, 0x00011f80, SDR_CHANNEL_RGAIN(i));
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ddbwritel(dev, 0x00001000, SDR_CHANNEL_FM1GAIN(i));
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ddbwritel(dev, 0x00001000, SDR_CHANNEL_FM1GAIN(i));
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@ -25,6 +25,7 @@ struct dvb_mod_channel_params {
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#define MODULATOR_FREQUENCY 3
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#define MODULATOR_FREQUENCY 3
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#define MODULATOR_MODULATION 4
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#define MODULATOR_MODULATION 4
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#define MODULATOR_SYMBOL_RATE 5 /* Hz */
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#define MODULATOR_SYMBOL_RATE 5 /* Hz */
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#define MODULATOR_BASE_FREQUENCY 6
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#define MODULATOR_ATTENUATOR 32
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#define MODULATOR_ATTENUATOR 32
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#define MODULATOR_INPUT_BITRATE 33 /* Hz */
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#define MODULATOR_INPUT_BITRATE 33 /* Hz */
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#define MODULATOR_PCR_MODE 34 /* 1=pcr correction enabled */
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#define MODULATOR_PCR_MODE 34 /* 1=pcr correction enabled */
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