mirror of
https://github.com/DigitalDevices/dddvb.git
synced 2023-10-10 13:37:43 +02:00
first support for V2 modulator cards
This commit is contained in:
Ralph Metzler
parent
5c7b55490a
commit
8c82d0166c
@ -92,6 +92,32 @@ static struct ddb_regset octopus_mod_odma_buf = {
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.size = 0x100,
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};
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static struct ddb_regset octopus_mod_channel = {
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.base = 0x400,
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.num = 0x0a,
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.size = 0x40,
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};
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/****************************************************************************/
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static struct ddb_regset octopus_mod_2_odma = {
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.base = 0x400,
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.num = 0x18,
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.size = 0x10,
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};
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static struct ddb_regset octopus_mod_2_odma_buf = {
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.base = 0x8000,
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.num = 0x18,
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.size = 0x100,
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};
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static struct ddb_regset octopus_mod_2_channel = {
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.base = 0x800,
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.num = 0x18,
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.size = 0x40,
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};
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/****************************************************************************/
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static struct ddb_regset octopus_input = {
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@ -249,15 +275,10 @@ static struct ddb_regmap octopro_hdin_map = {
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.output = &octopro_output,
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};
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static struct ddb_regset octopus_mod_channel = {
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.base = 0x400,
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.num = 0x0c,
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.size = 0x40,
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};
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static struct ddb_regmap octopus_mod_map = {
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.irq_version = 1,
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.irq_base_odma = 8,
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.irq_base_rate = 18,
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.output = &octopus_output,
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.odma = &octopus_mod_odma,
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.odma_buf = &octopus_mod_odma_buf,
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@ -265,6 +286,17 @@ static struct ddb_regmap octopus_mod_map = {
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};
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static struct ddb_regmap octopus_mod_2_map = {
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.irq_version = 2,
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.irq_base_odma = 64,
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.irq_base_rate = 32,
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.output = &octopus_output,
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.odma = &octopus_mod_2_odma,
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.odma_buf = &octopus_mod_2_odma_buf,
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.channel = &octopus_mod_2_channel,
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};
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/****************************************************************************/
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static struct ddb_info ddb_s2_48 = {
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@ -3395,9 +3427,9 @@ static void ddb_ports_init(struct ddb *dev)
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break;
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case DDB_MOD:
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ddb_output_init(port, i);
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dev->handler[0][i + 18] =
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dev->handler[0][i + rm->irq_base_rate] =
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ddbridge_mod_rate_handler;
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dev->handler_data[0][i + 18] =
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dev->handler_data[0][i + rm->irq_base_rate] =
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(unsigned long) &dev->output[i];
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break;
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default:
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@ -4845,7 +4877,7 @@ static void ddb_device_attrs_del(struct ddb *dev)
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device_remove_file(dev->ddb_dev, &ddb_attrs_snr[i]);
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device_remove_file(dev->ddb_dev, &ddb_attrs_ctemp[i]);
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}
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for (i = 0; ddb_attrs[i].attr.name; i++)
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for (i = 0; ddb_attrs[i].attr.name != NULL; i++)
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device_remove_file(dev->ddb_dev, &ddb_attrs[i]);
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}
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@ -4853,19 +4885,19 @@ static int ddb_device_attrs_add(struct ddb *dev)
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{
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int i;
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for (i = 0; ddb_attrs[i].attr.name; i++)
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for (i = 0; ddb_attrs[i].attr.name != NULL; i++)
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if (device_create_file(dev->ddb_dev, &ddb_attrs[i]))
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goto fail;
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for (i = 0; i < dev->link[0].info->temp_num; i++)
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if (device_create_file(dev->ddb_dev, &ddb_attrs_temp[i]))
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goto fail;
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for (i = 0; i < dev->link[0].info->port_num; i++)
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for (i = 0; (i < dev->link[0].info->port_num) && (i < 10); i++)
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if (device_create_file(dev->ddb_dev, &ddb_attrs_mod[i]))
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goto fail;
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for (i = 0; i < dev->link[0].info->fan_num; i++)
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if (device_create_file(dev->ddb_dev, &ddb_attrs_fan[i]))
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goto fail;
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for (i = 0; i < dev->i2c_num && i < 4; i++) {
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for (i = 0; (i < dev->i2c_num) && (i < 4); i++) {
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if (device_create_file(dev->ddb_dev, &ddb_attrs_snr[i]))
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goto fail;
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if (device_create_file(dev->ddb_dev, &ddb_attrs_ctemp[i]))
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@ -28,6 +28,10 @@
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#include <linux/dvb/mod.h>
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/****************************************************************************/
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/****************************************************************************/
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/****************************************************************************/
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inline s64 ConvertPCR(s64 a)
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{
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s32 ext;
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@ -72,6 +76,81 @@ inline s64 RoundPCRDown(s64 a)
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return a & ~(HW_LSB_MASK - 1);
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}
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// Calculating KF, LF from Symbolrate
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//
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// Symbolrate is usually calculated as (M/N) * 10.24 MS/s
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//
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// Common Values for M,N
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// J.83 Annex A,
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// Euro Docsis 6.952 MS/s : M = 869, N = 1280
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// 6.900 MS/s : M = 345, N = 512
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// 6.875 MS/s : M = 1375, N = 2048
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// 6.111 MS/s : M = 6111, N = 10240
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// J.83 Annex B **
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// QAM64 5.056941 : M = 401, N = 812
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// QAM256 5.360537 : M = 78, N = 149
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// J.83 Annex C **
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// 5.309734 : M = 1889, N = 3643
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//
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// For the present hardware
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// KF' = 256 * M
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// LF' = 225 * N
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// or
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// KF' = Symbolrate in Hz
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// LF' = 9000000
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//
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// KF = KF' / gcd(KF',LF')
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// LF = LF' / gcd(KF',LF')
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// Note: LF must not be a power of 2.
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// Maximum value for KF,LF = 13421727 ( 0x7FFFFFF )
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// ** using these M,N values will result in a small err (<5ppm)
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// calculating KF,LF directly gives the exact normative result
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// but with rather large KF,LF values
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static inline u32 gcd(u32 u,u32 v)
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{
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int s = 0;
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while (((u|v)&1) == 0) {
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s += 1;
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u >>= 1;
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v >>= 1;
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}
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while ((u&1) == 0)
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u >>= 1;
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do {
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while ( (v&1) == 0 ) v >>= 1;
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if( u > v ) {
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u32 t = v;
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v = u;
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u = t;
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}
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v = v - u;
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} while(v != 0);
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return u << s;
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}
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/****************************************************************************/
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/****************************************************************************/
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/****************************************************************************/
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static int mod_SendChannelCommand(struct ddb *dev, u32 Channel, u32 Command)
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{
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u32 ControlReg = ddbreadl(dev, CHANNEL_CONTROL(Channel));
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ControlReg = (ControlReg & ~CHANNEL_CONTROL_CMD_MASK)|Command;
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ddbwritel(dev, ControlReg, CHANNEL_CONTROL(Channel));
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while(1) {
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ControlReg = ddbreadl(dev, CHANNEL_CONTROL(Channel));
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if (ControlReg == 0xFFFFFFFF)
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return -EIO;
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if((ControlReg & CHANNEL_CONTROL_CMD_STATUS) == 0)
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break;
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}
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if (ControlReg & CHANNEL_CONTROL_ERROR_CMD)
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return -EINVAL;
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return 0;
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}
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static int mod_busy(struct ddb *dev, int chan)
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{
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u32 creg;
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@ -89,10 +168,12 @@ static int mod_busy(struct ddb *dev, int chan)
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void ddbridge_mod_output_stop(struct ddb_output *output)
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{
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struct ddb *dev = output->port->dev;
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struct mod_state *mod = &dev->mod[output->nr];
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struct ddb_mod *mod = &dev->mod[output->nr];
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mod->State = CM_IDLE;
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mod->Control = 0;
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if (dev->link[0].info->version == 2)
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mod_SendChannelCommand(dev, output->nr, CHANNEL_CONTROL_CMD_FREE);
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ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
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#if 0
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udelay(10);
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@ -108,7 +189,7 @@ static void mod_set_incs(struct ddb_output *output)
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{
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s64 pcr;
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struct ddb *dev = output->port->dev;
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struct mod_state *mod = &dev->mod[output->nr];
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struct ddb_mod *mod = &dev->mod[output->nr];
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pcr = ConvertPCR(mod->PCRIncrement);
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ddbwritel(dev, pcr & 0xffffffff,
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@ -137,7 +218,9 @@ static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 };
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void ddbridge_mod_output_start(struct ddb_output *output)
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{
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struct ddb *dev = output->port->dev;
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struct mod_state *mod = &dev->mod[output->nr];
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u32 Channel = output->nr;
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struct ddb_mod *mod = &dev->mod[output->nr];
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u32 Symbolrate = 6900000;
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/*PCRIncrement = RoundPCR(PCRIncrement);*/
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/*PCRDecrement = RoundPCR(PCRDecrement);*/
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@ -164,18 +247,55 @@ void ddbridge_mod_output_start(struct ddb_output *output)
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udelay(10);
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ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
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/* QAM: 600 601 602 903 604 = 16 32 64 128 256 */
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/* ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); */
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ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr));
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pr_info("CHANNEL_BASE = %08x\n", CHANNEL_BASE);
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pr_info("CHANNEL_CONTROL = %08x\n", CHANNEL_CONTROL(Channel));
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if (dev->link[0].info->version == 2) {
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u32 Output = ((dev->mod_base.frequency - 114000000)/8000000 + Channel) % 96;
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u32 KF = Symbolrate;
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u32 LF = 9000000UL;
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u32 d = gcd(KF,LF);
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u32 checkLF;
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mod->modulation = QAM_256 - 1;
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ddbwritel(dev, mod->modulation, CHANNEL_SETTINGS(Channel));
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ddbwritel(dev, Output, CHANNEL_SETTINGS2(Channel));
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KF = KF / d;
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LF = LF / d;
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while( (KF > KFLF_MAX) || (LF > KFLF_MAX) ) {
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KF >>= 1;
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LF >>= 1;
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}
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checkLF = LF;
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while ((checkLF & 1) == 0)
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checkLF >>= 1;
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if (checkLF <= 1)
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return -EINVAL;
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pr_info("KF=%u LF=%u Output=%u mod=%u\n", KF, LF, Output, mod->modulation);
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ddbwritel(dev, KF, CHANNEL_KF(Channel));
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ddbwritel(dev, LF, CHANNEL_LF(Channel));
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if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_SETUP))
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return -EINVAL;
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mod->Control = CHANNEL_CONTROL_ENABLE_DVB;
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} else {
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/* QAM: 600 601 602 903 604 = 16 32 64 128 256 */
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/* ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); */
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ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr));
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mod->Control = (CHANNEL_CONTROL_ENABLE_IQ | CHANNEL_CONTROL_ENABLE_DVB);
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}
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mod_set_rateinc(dev, output->nr);
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mod_set_incs(output);
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mod->Control = (CHANNEL_CONTROL_ENABLE_IQ |
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CHANNEL_CONTROL_ENABLE_DVB |
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CHANNEL_CONTROL_ENABLE_SOURCE);
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mod->Control |= CHANNEL_CONTROL_ENABLE_SOURCE;
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ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
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if (dev->link[0].info->version == 2)
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if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_UNMUTE))
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return -EINVAL;
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pr_info("mod_output_start %d.%d\n", dev->nr, output->nr);
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}
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@ -183,6 +303,195 @@ void ddbridge_mod_output_start(struct ddb_output *output)
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/****************************************************************************/
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/****************************************************************************/
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static int mod_write_max2871(struct ddb *dev, u32 val)
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{
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ddbwritel(dev, val, MAX2871_OUTDATA);
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ddbwritel(dev, MAX2871_CONTROL_CE | MAX2871_CONTROL_WRITE, MAX2871_CONTROL);
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while(1) {
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u32 ControlReg = ddbreadl(dev, MAX2871_CONTROL);
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if (ControlReg == 0xFFFFFFFF)
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return -EIO;
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if ((ControlReg & MAX2871_CONTROL_WRITE) == 0)
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break;
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}
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return 0;
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}
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static int mod_setup_max2871(struct ddb *dev)
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{
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int status = 0;
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int i;
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ddbwritel(dev, MAX2871_CONTROL_CE, MAX2871_CONTROL);
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for (i = 0; i < 2; i++) {
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status = mod_write_max2871(dev, 0x00440005);
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if (status)
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break;
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status = mod_write_max2871(dev, 0x6199003C);
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if (status)
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break;
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status = mod_write_max2871(dev, 0x000000CB);
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if (status)
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break;
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status = mod_write_max2871(dev, 0x510061C2);
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if (status)
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break;
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status = mod_write_max2871(dev, 0x600080A1);
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if (status)
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break;
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status = mod_write_max2871(dev, 0x00730040);
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if (status)
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break;
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msleep(30);
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} while(0);
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if (status == 0) {
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u32 ControlReg = ddbreadl(dev, MAX2871_CONTROL);
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if ((ControlReg & MAX2871_CONTROL_LOCK) == 0)
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status = -EIO;
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}
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return status;
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}
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static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels)
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{
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int status = 0;
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u32 Capacity;
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u32 tmp = ddbreadl(dev, FSM_STATUS);
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if ((tmp & FSM_STATUS_READY) == 0) {
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status = mod_setup_max2871(dev);
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if (status)
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return status;
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ddbwritel(dev, FSM_CMD_RESET, FSM_CONTROL);
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msleep(10);
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tmp = ddbreadl(dev, FSM_STATUS);
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if ((tmp & FSM_STATUS_READY) == 0)
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return -1;
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}
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Capacity = ddbreadl(dev, FSM_CAPACITY);
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if (((tmp & FSM_STATUS_QAMREADY) != 0) &&
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((Capacity & FSM_CAPACITY_INUSE) != 0))
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return -EBUSY;
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ddbwritel(dev, FSM_CMD_SETUP, FSM_CONTROL);
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msleep(10);
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tmp = ddbreadl(dev, FSM_STATUS);
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if ((tmp & FSM_STATUS_QAMREADY) == 0)
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return -1;
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if (MaxUsedChannels == 0)
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MaxUsedChannels = (Capacity & FSM_CAPACITY_CUR) >> 16;
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pr_info("max used chan = %u\n", MaxUsedChannels);
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if (MaxUsedChannels <= 1 )
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ddbwritel(dev, FSM_GAIN_N1, FSM_GAIN);
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else if (MaxUsedChannels <= 2)
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ddbwritel(dev, FSM_GAIN_N2, FSM_GAIN);
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else if (MaxUsedChannels <= 4)
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ddbwritel(dev, FSM_GAIN_N4, FSM_GAIN);
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else if (MaxUsedChannels <= 8)
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ddbwritel(dev, FSM_GAIN_N8, FSM_GAIN);
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else if (MaxUsedChannels <= 16)
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ddbwritel(dev, FSM_GAIN_N16, FSM_GAIN);
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else if (MaxUsedChannels <= 24)
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ddbwritel(dev, FSM_GAIN_N24, FSM_GAIN);
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else
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ddbwritel(dev, FSM_GAIN_N96, FSM_GAIN);
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ddbwritel(dev, FSM_CONTROL_ENABLE, FSM_CONTROL);
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return status;
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}
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static int mod_set_vga(struct ddb *dev, u32 Gain)
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{
|
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if( Gain > 255 )
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return -EINVAL;
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ddbwritel(dev, Gain, RF_VGA);
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return 0;
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}
|
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static int mod_get_vga(struct ddb *dev, u32 *pGain)
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{
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*pGain = ddbreadl(dev, RF_VGA);
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return 0;
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}
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static void mod_TemperatureMonitorSetFan(struct ddb *dev)
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{
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u32 tqam, pwm;
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if ((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) {
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pr_info("Over temperature condition\n");
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dev->mod_base.OverTemperatureError = 1;
|
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}
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tqam = (ddbreadl(dev, TEMPMON2_QAMCORE) >> 8) & 0xFF;
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if (tqam & 0x80)
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tqam = 0;
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pwm = (ddbreadl(dev, TEMPMON_FANCONTROL) >> 8) & 0x0F;
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if (pwm > 10)
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pwm = 10;
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|
||||
if (tqam >= dev->mod_base.temp_tab[pwm]) {
|
||||
while( pwm < 10 && tqam >= dev->mod_base.temp_tab[pwm + 1])
|
||||
pwm += 1;
|
||||
} else {
|
||||
while( pwm > 1 && tqam < dev->mod_base.temp_tab[pwm - 2])
|
||||
pwm -= 1;
|
||||
}
|
||||
ddbwritel(dev, (pwm << 8), TEMPMON_FANCONTROL);
|
||||
}
|
||||
|
||||
|
||||
static void mod_temp_handler(unsigned long data)
|
||||
{
|
||||
struct ddb *dev = (struct ddb *) data;
|
||||
|
||||
pr_info("mod_temp_handler\n");
|
||||
|
||||
spin_lock(&dev->mod_base.temp_lock);
|
||||
mod_TemperatureMonitorSetFan(dev);
|
||||
spin_unlock(&dev->mod_base.temp_lock);
|
||||
}
|
||||
|
||||
static int mod_TemperatureMonitorInit(struct ddb *dev, int FirstTime) {
|
||||
int status = 0;
|
||||
|
||||
spin_lock_irq(&dev->mod_base.temp_lock);
|
||||
if (FirstTime) {
|
||||
static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80};
|
||||
|
||||
memcpy(dev->mod_base.temp_tab, TemperatureTable, sizeof(TemperatureTable));
|
||||
}
|
||||
dev->handler[0][8] = mod_temp_handler;
|
||||
dev->handler_data[0][8] = (unsigned long) dev;
|
||||
ddbwritel(dev, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN |
|
||||
TEMPMON_CONTROL_INTENABLE),
|
||||
TEMPMON_CONTROL);
|
||||
ddbwritel(dev, (3 << 8), TEMPMON_FANCONTROL);
|
||||
|
||||
dev->mod_base.OverTemperatureError =
|
||||
((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0);
|
||||
if (dev->mod_base.OverTemperatureError) {
|
||||
pr_info("Over temperature condition\n");
|
||||
status = -1;
|
||||
}
|
||||
mod_TemperatureMonitorSetFan(dev);
|
||||
spin_unlock_irq(&dev->mod_base.temp_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
|
||||
static void mod_write_dac_register(struct ddb *dev, u8 Index, u8 Value)
|
||||
{
|
||||
u32 RegValue = 0;
|
||||
@ -804,7 +1113,7 @@ static int set_base_frequency(struct ddb *dev, u32 freq)
|
||||
return mod_set_down(dev, down, 8, Ext);
|
||||
}
|
||||
|
||||
static int mod_init(struct ddb *dev, u32 Frequency)
|
||||
static int mod_init_1(struct ddb *dev, u32 Frequency)
|
||||
{
|
||||
int stat = 0;
|
||||
u8 *buffer;
|
||||
@ -906,7 +1215,7 @@ void ddbridge_mod_rate_handler(unsigned long data)
|
||||
struct ddb_output *output = (struct ddb_output *) data;
|
||||
struct ddb_dma *dma = output->dma;
|
||||
struct ddb *dev = output->port->dev;
|
||||
struct mod_state *mod = &dev->mod[output->nr];
|
||||
struct ddb_mod *mod = &dev->mod[output->nr];
|
||||
|
||||
u32 chan = output->nr;
|
||||
u32 OutPacketCount;
|
||||
@ -1081,7 +1390,7 @@ void ddbridge_mod_rate_handler(unsigned long data)
|
||||
PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement);
|
||||
}
|
||||
|
||||
int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
static int mod_ioctl_1(struct file *file, unsigned int cmd, void *parg)
|
||||
{
|
||||
struct dvb_device *dvbdev = file->private_data;
|
||||
struct ddb_output *output = dvbdev->priv;
|
||||
@ -1146,7 +1455,117 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
|
||||
static int mod_ioctl_2(struct file *file, unsigned int cmd, void *parg)
|
||||
{
|
||||
struct dvb_device *dvbdev = file->private_data;
|
||||
struct ddb_output *output = dvbdev->priv;
|
||||
struct ddb *dev = output->port->dev;
|
||||
|
||||
/* unsigned long arg = (unsigned long) parg; */
|
||||
int ret = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case DVB_MOD_SET:
|
||||
{
|
||||
struct dvb_mod_params *mp = parg;
|
||||
|
||||
pr_info("set base freq\n");
|
||||
dev->mod_base.frequency = mp->base_frequency;
|
||||
pr_info("set attenuator\n");
|
||||
mod_set_attenuator(dev, mp->attenuator);
|
||||
break;
|
||||
}
|
||||
case DVB_MOD_CHANNEL_SET:
|
||||
{
|
||||
struct dvb_mod_channel_params *cp = parg;
|
||||
int res;
|
||||
u32 ri;
|
||||
|
||||
pr_info("set modulation\n");
|
||||
res = mod_set_modulation(dev, output->nr, cp->modulation);
|
||||
if (res)
|
||||
return res;
|
||||
|
||||
if (cp->input_bitrate > dev->mod[output->nr].obitrate)
|
||||
return -EINVAL;
|
||||
dev->mod[output->nr].ibitrate = cp->input_bitrate;
|
||||
dev->mod[output->nr].pcr_correction = cp->pcr_correction;
|
||||
|
||||
pr_info("ibitrate %llu\n", dev->mod[output->nr].ibitrate);
|
||||
pr_info("obitrate %llu\n", dev->mod[output->nr].obitrate);
|
||||
if (cp->input_bitrate != 0) {
|
||||
u64 d = dev->mod[output->nr].obitrate -
|
||||
dev->mod[output->nr].ibitrate;
|
||||
|
||||
d = div64_u64(d, dev->mod[output->nr].obitrate >> 24);
|
||||
if (d > 0xfffffe)
|
||||
ri = 0xfffffe;
|
||||
else
|
||||
ri = d;
|
||||
} else
|
||||
ri = 0;
|
||||
dev->mod[output->nr].rate_inc = ri;
|
||||
pr_info("ibr=%llu, obr=%llu, ri=0x%06x\n",
|
||||
dev->mod[output->nr].ibitrate >> 32,
|
||||
dev->mod[output->nr].obitrate >> 32,
|
||||
ri);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static int mod_init_2(struct ddb *dev, u32 Frequency)
|
||||
{
|
||||
int status;
|
||||
printk("mod_init_2\n");
|
||||
|
||||
dev->mod_base.frequency = Frequency;
|
||||
mod_TemperatureMonitorInit(dev, 1);
|
||||
status = mod_fsm_setup(dev, 0, 0);
|
||||
pr_info("fsm_setup = %d\n", status);
|
||||
|
||||
#if 0
|
||||
if (pdx->NumOutputStreams <= 8)
|
||||
mod_set_vga(dev, RF_VGA_GAIN_N8);
|
||||
else if (pdx->NumOutputStreams <= 16)
|
||||
mod_set_vga(dev, RF_VGA_GAIN_N16);
|
||||
else
|
||||
#endif
|
||||
mod_set_vga(dev, RF_VGA_GAIN_N24);
|
||||
|
||||
mod_set_attenuator(dev, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
{
|
||||
struct dvb_device *dvbdev = file->private_data;
|
||||
struct ddb_output *output = dvbdev->priv;
|
||||
struct ddb *dev = output->port->dev;
|
||||
|
||||
if (dev->link[0].info->version <= 0)
|
||||
return mod_ioctl_1(file, cmd, parg);
|
||||
if (dev->link[0].info->version == 2)
|
||||
return mod_ioctl_2(file, cmd, parg);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int ddbridge_mod_init(struct ddb *dev)
|
||||
{
|
||||
return mod_init(dev, 722000000);
|
||||
spin_lock_init(&dev->mod_base.temp_lock);
|
||||
if (dev->link[0].info->version <= 1)
|
||||
return mod_init_1(dev, 722000000);
|
||||
if (dev->link[0].info->version == 2)
|
||||
return mod_init_2(dev, 114000000);
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -23,12 +23,11 @@
|
||||
|
||||
/* Register Definitions */
|
||||
|
||||
#define CUR_REGISTERMAP_VERSION 0x10003
|
||||
#define CUR_REGISTERMAP_VERSION_CI 0x10000
|
||||
#define CUR_REGISTERMAP_VERSION_MOD 0x10000
|
||||
#define CUR_REGISTERMAP_VERSION_V1 0x00010001
|
||||
#define CUR_REGISTERMAP_VERSION_V2 0x00020000
|
||||
|
||||
#define HARDWARE_VERSION 0x00
|
||||
#define REGISTERMAP_VERSION 0x04
|
||||
#define HARDWARE_VERSION 0x00000000
|
||||
#define REGISTERMAP_VERSION 0x00000004
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* SPI Controller */
|
||||
@ -76,6 +75,8 @@
|
||||
|
||||
#define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20)
|
||||
#define INTERRUPT_ACK (INTERRUPT_BASE + 0x20)
|
||||
#define INTERRUPT_ACK1 (INTERRUPT_BASE + 0x24)
|
||||
#define INTERRUPT_ACK2 (INTERRUPT_BASE + 0x28)
|
||||
|
||||
#define INTMASK_CLOCKGEN (0x00000001)
|
||||
#define INTMASK_TEMPMON (0x00000002)
|
||||
@ -148,11 +149,37 @@
|
||||
/* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */
|
||||
#define TEMPMON_BASE (0xA0)
|
||||
#define TEMPMON_CONTROL (TEMPMON_BASE + 0x00)
|
||||
|
||||
#define TEMPMON_CONTROL_SCAN (0x00000001)
|
||||
#define TEMPMON_CONTROL_AUTOSCAN (0x00000002)
|
||||
#define TEMPMON_CONTROL_INTENABLE (0x00000004)
|
||||
#define TEMPMON_CONTROL_OVERTEMP (0x00008000)
|
||||
|
||||
|
||||
/* SHORT Temperature in °C x 256 */
|
||||
#define TEMPMON_CORE (TEMPMON_BASE + 0x04)
|
||||
#define TEMPMON_SENSOR0 (TEMPMON_BASE + 0x04)
|
||||
#define TEMPMON_SENSOR1 (TEMPMON_BASE + 0x08)
|
||||
#define TEMPMON_SENSOR2 (TEMPMON_BASE + 0x0C)
|
||||
|
||||
#define TEMPMON_FANCONTROL (TEMPMON_BASE + 0x10)
|
||||
#define TEMPMON_FANPWM (0x00000F00) // PWM speed in 10% steps
|
||||
#define TEMPMON_FANTACHO (0x000000FF) // Rotations in 100/min steps
|
||||
|
||||
// V1 Temperature Monitor
|
||||
// Temperature Monitor TEMPMON_CONTROL & 0x8000 == 0 : ( 2x LM75A @ 0x90,0x92 )
|
||||
// Temperature Monitor TEMPMON_CONTROL & 0x8000 == 1 : ( 1x LM75A @ 0x90, 1x ADM1032 @ 0x9A )
|
||||
|
||||
#define TEMPMON1_CORE (TEMPMON_SENSOR0) // SHORT Temperature in °C x 256 (ADM1032 ext)
|
||||
#define TEMPMON1_SENSOR1 (TEMPMON_BASE + 0x08) // SHORT Temperature in °C x 256 (LM75A 0x90)
|
||||
#define TEMPMON1_SENSOR2 (TEMPMON_BASE + 0x0C) // SHORT Temperature in °C x 256 (LM75A 0x92 or ADM1032 Int)
|
||||
|
||||
// V2 Temperature Monitor 2 ADM1032
|
||||
|
||||
#define TEMPMON2_BOARD (TEMPMON_SENSOR0) // SHORT Temperature in °C x 256 (ADM1032 int)
|
||||
#define TEMPMON2_FPGACORE (TEMPMON_SENSOR1) // SHORT Temperature in °C x 256 (ADM1032 ext)
|
||||
#define TEMPMON2_QAMCORE (TEMPMON_SENSOR2) // SHORT Temperature in °C x 256 (ADM1032 ext)
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* I2C Master Controller */
|
||||
|
||||
@ -271,6 +298,8 @@
|
||||
#define CI_BLOCKIO_SEND_BUFFER(i) \
|
||||
(CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE + CI_BLOCKIO_BUFFER_SIZE)
|
||||
|
||||
// V1
|
||||
|
||||
#define VCO1_BASE (0xC0)
|
||||
#define VCO1_CONTROL (VCO1_BASE + 0x00)
|
||||
#define VCO1_DATA (VCO1_BASE + 0x04) /* 24 Bit */
|
||||
@ -301,6 +330,53 @@
|
||||
/* Muxout from VCO (usually = Lock) */
|
||||
#define VCO3_CONTROL_MUXOUT (0x00000004)
|
||||
|
||||
// V2
|
||||
|
||||
#define MAX2871_BASE (0xC0)
|
||||
#define MAX2871_CONTROL (MAX2871_BASE + 0x00)
|
||||
#define MAX2871_OUTDATA (MAX2871_BASE + 0x04) // 32 Bit
|
||||
#define MAX2871_INDATA (MAX2871_BASE + 0x08) // 32 Bit
|
||||
#define MAX2871_CONTROL_WRITE (0x00000001) // 1 = Trigger write, resets when done
|
||||
#define MAX2871_CONTROL_CE (0x00000002) // 0 = Put VCO into power down
|
||||
#define MAX2871_CONTROL_MUXOUT (0x00000004) // Muxout from VCO
|
||||
#define MAX2871_CONTROL_LOCK (0x00000008) // Lock from VCO
|
||||
|
||||
#define FSM_BASE (0x200)
|
||||
#define FSM_CONTROL (FSM_BASE + 0x00)
|
||||
|
||||
#define FSM_CONTROL_ENABLE (0x00000100)
|
||||
|
||||
#define FSM_CMD_MASK (0x00000087)
|
||||
#define FSM_CMD_STATUS (0x00000080)
|
||||
#define FSM_CMD_RESET (0x00000080)
|
||||
#define FSM_CMD_POWERDOWN (0x00000081)
|
||||
#define FSM_CMD_SETUP (0x00000082)
|
||||
|
||||
#define FSM_STATUS (FSM_BASE + 0x00)
|
||||
#define FSM_STATUS_READY (0x00010000)
|
||||
#define FSM_STATUS_QAMREADY (0x00020000)
|
||||
|
||||
|
||||
#define FSM_CAPACITY (FSM_BASE + 0x04)
|
||||
#define FSM_CAPACITY_MAX (0x3F000000)
|
||||
#define FSM_CAPACITY_CUR (0x003F0000)
|
||||
#define FSM_CAPACITY_INUSE (0x0000003F)
|
||||
|
||||
#define FSM_GAIN (FSM_BASE + 0x10)
|
||||
#define FSM_GAINMASK (0x000000FF)
|
||||
|
||||
#define FSM_GAIN_N1 (0x000000FE)
|
||||
#define FSM_GAIN_N2 (0x000000A1)
|
||||
#define FSM_GAIN_N4 (0x00000066)
|
||||
#define FSM_GAIN_N8 (0x00000048)
|
||||
#define FSM_GAIN_N16 (0x0000002D)
|
||||
#define FSM_GAIN_N24 (0x00000029)
|
||||
#define FSM_GAIN_N96 (0x00000011)
|
||||
|
||||
|
||||
// Attenuator/VGA
|
||||
|
||||
#define RF_ATTENUATOR (0xD8)
|
||||
#define RF_ATTENUATOR (0xD8)
|
||||
/* 0x00 = 0 dB
|
||||
0x01 = 1 dB
|
||||
@ -308,6 +384,20 @@
|
||||
0x1F = 31 dB
|
||||
*/
|
||||
|
||||
#define RF_VGA (0xDC)
|
||||
/* Only V2 */
|
||||
/* 8 bit range 0 - 31.75 dB Gain */
|
||||
|
||||
/* VGA Gain for same output level as V1 Modulator */
|
||||
#define RF_VGA_GAIN_N8 (85)
|
||||
#define RF_VGA_GAIN_N16 (117)
|
||||
#define RF_VGA_GAIN_N24 (122)
|
||||
|
||||
#define RF_VGA_GAIN_MAX (200)
|
||||
|
||||
|
||||
/* V1 only */
|
||||
|
||||
#define RF_POWER (0xE0)
|
||||
#define RF_POWER_BASE (0xE0)
|
||||
#define RF_POWER_CONTROL (RF_POWER_BASE + 0x00)
|
||||
@ -351,7 +441,7 @@
|
||||
#define IQOUTPUT_CONTROL_BYPASS_EQUALIZER (0x00000010)
|
||||
|
||||
|
||||
/* Modulator Base */
|
||||
/* Modulator Base V1 */
|
||||
|
||||
#define MODULATOR_BASE (0x200)
|
||||
#define MODULATOR_CONTROL (MODULATOR_BASE)
|
||||
@ -369,9 +459,11 @@
|
||||
|
||||
/* Modulator Channels */
|
||||
|
||||
#define CHANNEL_BASE (0x400)
|
||||
#define CHANNEL_BASE dev->link[0].info->regmap->channel->base
|
||||
|
||||
#define CHANNEL_CONTROL(i) (CHANNEL_BASE + (i) * 64 + 0x00)
|
||||
#define CHANNEL_SETTINGS(i) (CHANNEL_BASE + (i) * 64 + 0x04)
|
||||
#define CHANNEL_SETTINGS2(i) (CHANNEL_BASE + (i) * 64 + 0x08)
|
||||
#define CHANNEL_RATE_INCR(i) (CHANNEL_BASE + (i) * 64 + 0x0C)
|
||||
#define CHANNEL_PCR_ADJUST_OUTL(i) (CHANNEL_BASE + (i) * 64 + 0x10)
|
||||
#define CHANNEL_PCR_ADJUST_OUTH(i) (CHANNEL_BASE + (i) * 64 + 0x14)
|
||||
@ -381,6 +473,8 @@
|
||||
#define CHANNEL_PCR_ADJUST_ACCUH(i) (CHANNEL_BASE + (i) * 64 + 0x24)
|
||||
#define CHANNEL_PKT_COUNT_OUT(i) (CHANNEL_BASE + (i) * 64 + 0x28)
|
||||
#define CHANNEL_PKT_COUNT_IN(i) (CHANNEL_BASE + (i) * 64 + 0x2C)
|
||||
#define CHANNEL_KF(i) (CHANNEL_BASE + (i) * 64 + 0x30)
|
||||
#define CHANNEL_LF(i) (CHANNEL_BASE + (i) * 64 + 0x34)
|
||||
|
||||
#define CHANNEL_CONTROL_RESET (0x00000001)
|
||||
#define CHANNEL_CONTROL_ENABLE_DVB (0x00000002)
|
||||
@ -389,8 +483,17 @@
|
||||
#define CHANNEL_CONTROL_ENABLE_PCRADJUST (0x00000010)
|
||||
#define CHANNEL_CONTROL_FREEZE_STATUS (0x00000100)
|
||||
|
||||
#define CHANNEL_CONTROL_CMD_MASK (0x0000F000)
|
||||
#define CHANNEL_CONTROL_CMD_STATUS (0x00008000)
|
||||
#define CHANNEL_CONTROL_CMD_FREE (0x00008000)
|
||||
#define CHANNEL_CONTROL_CMD_SETUP (0x00009000)
|
||||
#define CHANNEL_CONTROL_CMD_MUTE (0x0000A000)
|
||||
#define CHANNEL_CONTROL_CMD_UNMUTE (0x0000B000)
|
||||
|
||||
#define CHANNEL_CONTROL_RESET_ERROR (0x00010000)
|
||||
#define CHANNEL_CONTROL_BUSY (0x01000000)
|
||||
#define CHANNEL_CONTROL_ACTIVE (0x00400000)
|
||||
#define CHANNEL_CONTROL_BUSY (0x00800000)
|
||||
#define CHANNEL_CONTROL_ERROR_CMD (0x10000000)
|
||||
#define CHANNEL_CONTROL_ERROR_SYNC (0x20000000)
|
||||
#define CHANNEL_CONTROL_ERROR_UNDERRUN (0x40000000)
|
||||
#define CHANNEL_CONTROL_ERROR_FATAL (0x80000000)
|
||||
@ -402,6 +505,14 @@
|
||||
#define CHANNEL_SETTINGS_QAM128 (0x00000003)
|
||||
#define CHANNEL_SETTINGS_QAM256 (0x00000004)
|
||||
|
||||
#define CHANNEL_SETTINGS2_OUTPUT_MASK (0x0000007F)
|
||||
|
||||
#define KFLF_MAX (0x07FFFFFFUL)
|
||||
#define KF_INIT(Symbolrate) (Symbolrate)
|
||||
#define LF_INIT(Symbolrate) (9000000UL)
|
||||
#define MIN_SYMBOLRATE (1000000)
|
||||
#define MAX_SYMBOLRATE (7100000)
|
||||
|
||||
|
||||
/* OCTONET */
|
||||
|
||||
|
||||
@ -468,6 +468,33 @@ static struct ddb_info ddb_mod = {
|
||||
.temp_num = 1,
|
||||
};
|
||||
|
||||
static struct ddb_info ddb_mod_fsm_24 = {
|
||||
.type = DDB_MOD,
|
||||
.version = 2,
|
||||
.name = "Digital Devices DVB-C modulator FSM-24",
|
||||
.regmap = &octopus_mod_2_map,
|
||||
.port_num = 24,
|
||||
.temp_num = 1,
|
||||
};
|
||||
|
||||
static struct ddb_info ddb_mod_fsm_16 = {
|
||||
.type = DDB_MOD,
|
||||
.version = 2,
|
||||
.name = "Digital Devices DVB-C modulator FSM-16",
|
||||
.regmap = &octopus_mod_2_map,
|
||||
.port_num = 16,
|
||||
.temp_num = 1,
|
||||
};
|
||||
|
||||
static struct ddb_info ddb_mod_fsm_8 = {
|
||||
.type = DDB_MOD,
|
||||
.name = "Digital Devices DVB-C modulator FSM-8",
|
||||
.version = 2,
|
||||
.regmap = &octopus_mod_2_map,
|
||||
.port_num = 8,
|
||||
.temp_num = 1,
|
||||
};
|
||||
|
||||
static struct ddb_info ddb_octopro_hdin = {
|
||||
.type = DDB_OCTOPRO_HDIN,
|
||||
.name = "Digital Devices OctopusNet Pro HDIN",
|
||||
@ -523,6 +550,9 @@ static const struct pci_device_id ddb_id_tbl[] __devinitconst = {
|
||||
DDB_ID(DDVID, 0x0013, DDVID, 0x0043, ddb_ci_s2_pro),
|
||||
DDB_ID(DDVID, 0x0201, DDVID, 0x0001, ddb_mod),
|
||||
DDB_ID(DDVID, 0x0201, DDVID, 0x0002, ddb_mod),
|
||||
DDB_ID(DDVID, 0x0210, DDVID, 0x0001, ddb_mod_fsm_24),
|
||||
DDB_ID(DDVID, 0x0210, DDVID, 0x0002, ddb_mod_fsm_16),
|
||||
DDB_ID(DDVID, 0x0210, DDVID, 0x0003, ddb_mod_fsm_8),
|
||||
/* testing on OctopusNet Pro */
|
||||
DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_octopro_hdin),
|
||||
DDB_ID(DDVID, 0x0321, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
|
||||
|
||||
@ -112,6 +112,7 @@ struct ddb_regmap {
|
||||
u32 irq_base_idma;
|
||||
u32 irq_base_odma;
|
||||
u32 irq_base_gtl;
|
||||
u32 irq_base_rate;
|
||||
|
||||
struct ddb_regset *i2c;
|
||||
struct ddb_regset *i2c_buf;
|
||||
@ -144,7 +145,7 @@ struct ddb_ids {
|
||||
};
|
||||
|
||||
struct ddb_info {
|
||||
int type;
|
||||
u32 type;
|
||||
#define DDB_NONE 0
|
||||
#define DDB_OCTOPUS 1
|
||||
#define DDB_OCTOPUS_CI 2
|
||||
@ -154,6 +155,7 @@ struct ddb_info {
|
||||
#define DDB_OCTOPUS_MAX_CT 6
|
||||
#define DDB_OCTOPRO 7
|
||||
#define DDB_OCTOPRO_HDIN 8
|
||||
u32 version;
|
||||
char *name;
|
||||
u32 i2c_mask;
|
||||
u8 port_num;
|
||||
@ -167,8 +169,9 @@ struct ddb_info {
|
||||
u8 mdio_num;
|
||||
u8 con_clock; /* use a continuous clock */
|
||||
u8 ts_quirks;
|
||||
#define TS_QUIRK_SERIAL 1
|
||||
#define TS_QUIRK_REVERSED 2
|
||||
#define TS_QUIRK_SERIAL 1
|
||||
#define TS_QUIRK_REVERSED 2
|
||||
#define TS_QUIRK_NO_OUTPUT 4
|
||||
struct ddb_regmap *regmap;
|
||||
};
|
||||
|
||||
@ -335,10 +338,21 @@ struct mod_base {
|
||||
u32 frequency;
|
||||
u32 flat_start;
|
||||
u32 flat_end;
|
||||
|
||||
spinlock_t temp_lock;
|
||||
int OverTemperatureError;
|
||||
u8 temp_tab[11];
|
||||
};
|
||||
|
||||
struct mod_state {
|
||||
struct ddb_mod {
|
||||
struct ddb_port *port;
|
||||
u32 nr;
|
||||
u32 regs;
|
||||
|
||||
u32 frequency;
|
||||
u32 modulation;
|
||||
u32 symbolrate;
|
||||
|
||||
u64 obitrate;
|
||||
u64 ibitrate;
|
||||
u32 pcr_correction;
|
||||
@ -456,7 +470,7 @@ struct ddb {
|
||||
u8 tsbuf[TS_CAPTURE_LEN];
|
||||
|
||||
struct mod_base mod_base;
|
||||
struct mod_state mod[10];
|
||||
struct ddb_mod mod[24];
|
||||
};
|
||||
|
||||
static inline void ddbwriteb(struct ddb *dev, u32 val, u32 adr)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user