diff --git a/CHANGELOG b/CHANGELOG index 2d18827..95a20cd 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,6 @@ +0.9.24 2016.08.03 +- suport new V2 modulator cards + 0.9.19c 2015.07.20 - MAX S8: do not turn on diseqc and tuners on init diff --git a/apps/cit.c b/apps/cit.c index ca3f7e4..2a3f6e7 100644 --- a/apps/cit.c +++ b/apps/cit.c @@ -9,6 +9,9 @@ #include #include #include +#include + +uint32_t adapter = 0, device = 0, snum = 256, rnum = 256; uint8_t fill[188]={0x47, 0x1f, 0xff, 0x10, 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, @@ -68,24 +71,34 @@ void proc_buf(uint8_t *buf, uint32_t *d) } else { if (memcmp(ts+8, buf+8, 180)) printf("error\n"); - if (!(c&0xffff)) - printf("R %08x\n", c); + if (!(c&0xffff)) { + printf("R %08x\r", c); + fflush(0); + } } (*d)++; } void *get_ts(void *a) { - uint8_t buf[188*1024]; + uint8_t *buf; int len, off; - - int fdi=open("/dev/dvb/adapter2/ci0", O_RDONLY); + int fdi; + char fname[80]; uint32_t d=0; + buf = malloc(188*rnum); + if (!buf) + return NULL; + sprintf(fname, "/dev/dvb/adapter%u/ci%u", adapter, device); + fdi = open(fname, O_RDONLY); + while (1) { - len=read(fdi, buf, 188*1024); + memset(buf, 0, 188*rnum); + len=read(fdi, buf, 188*rnum); if (len<0) continue; + //printf("read %u\n", len); if (buf[0]!=0x47) { read(fdi, buf, 1); continue; @@ -96,20 +109,23 @@ void *get_ts(void *a) } } -#define SNUM 233 -//671 -void send(void) + +int send(void) { - uint8_t buf[188*SNUM], *cts; + uint8_t *buf, *cts; int i; uint32_t c=0; int fdo; - - fdo=open("/dev/dvb/adapter2/ci0", O_WRONLY); - + char fname[80]; + + buf = malloc(188*snum); + if (!buf) + return -1; + sprintf(fname, "/dev/dvb/adapter%u/ci%u", adapter, device); + fdo=open(fname, O_WRONLY); while (1) { - for (i=0; i>24); @@ -122,15 +138,54 @@ void send(void) //usleep(100000+0xffff&rand()); //usleep(1000); } - write(fdo, buf, 188*SNUM); + write(fdo, buf, 188*snum); } } -int main() +int main(int argc, char **argv) { pthread_t th; - + + while (1) { + int option_index = 0; + int c; + static struct option long_options[] = { + {"adapter", required_argument, 0, 'a'}, + {"device", required_argument, 0, 'd'}, + {"snum", required_argument, 0, 's'}, + {"rnum", required_argument, 0, 'r'}, + {"help", no_argument , 0, 'h'}, + {0, 0, 0, 0} + }; + c = getopt_long(argc, argv, + "a:d:h", + long_options, &option_index); + if (c==-1) + break; + + switch (c) { + case 'd': + device = strtoul(optarg, NULL, 10); + break; + case 'a': + adapter = strtoul(optarg, NULL, 10); + break; + case 's': + snum = strtoul(optarg, NULL, 10); + break; + case 'r': + rnum = strtoul(optarg, NULL, 10); + break; + case 'h': + default: + break; + + } + } + if (optind < argc) { + printf("Warning: unused arguments\n"); + } memset(ts+8, 180, 0x5a); pthread_create(&th, NULL, get_ts, NULL); usleep(10000); diff --git a/apps/octonet/ddtest.c b/apps/octonet/ddtest.c index a53a923..3941029 100644 --- a/apps/octonet/ddtest.c +++ b/apps/octonet/ddtest.c @@ -145,7 +145,6 @@ int ReadFlash(int ddb, int argc, char *argv[], uint32_t Flags) } - int FlashDetect(int dev) { uint8_t Cmd = 0x9F; @@ -765,7 +764,6 @@ uint32_t GetFPGA_ID(uint8_t * Buffer) } - int FlashProg(int dev,int argc, char* argv[],uint32_t Flags) { uint8_t * Buffer = NULL; @@ -1652,6 +1650,60 @@ int lic_erase(int dev, int argc, char* argv[], uint32_t Flags) return err; } +static int read_sfpd(int dev, uint8_t adr, uint8_t *val) +{ + uint8_t cmd[5] = { 0x5a, 0, 0, adr, 00 }; + int r; + + r = FlashIO(dev, cmd, 5, val, 1); + if (r < 0) + return r; + return 0; +} + +static int read_sst_id(int dev, uint8_t *id) +{ + uint8_t cmd[2] = { 0x88, 0 }; + uint8_t buf[9]; + int r; + + r = FlashIO(dev, cmd, 2, buf, 9); + if (r < 0) + return r; + memcpy(id, buf + 1, 8); + return 0; +} + +int read_id(int dev, int argc, char* argv[], uint32_t Flags) +{ + int Flash = FlashDetect(dev); + uint8_t Cmd;; + uint8_t Id[8]; + uint32_t len, i, adr; + + + switch(Flash) { + case SPANSION_S25FL116K: + case SPANSION_S25FL132K: + case SPANSION_S25FL164K: + for (i = 0; i < 8; i++) + read_sfpd(dev, 0xf8 + i, &Id[i]); + len = 8; + break; + case SSTI_SST25VF064C: + read_sst_id(dev, Id); + len = 8; + break; + default: + printf("Unsupported Flash\n"); + break; + } + printf("ID: "); + for (i = 0; i < 8; i++) + printf("%02x ", Id[i]); + printf("\n"); + +} struct SCommand CommandTable[] = { @@ -1661,7 +1713,7 @@ struct SCommand CommandTable[] = { "register", GetSetRegister, 1, "Get/Set Register : reg |<[0x]regnum> [[0x]value(32)]" }, { "flashread", ReadFlash, 1, "Read Flash : flashread " }, - { "flashio", FlashIO, 1, "Flash IO : flashio .. " }, + { "flashio", FlashIOC, 1, "Flash IO : flashio .. " }, { "flashprog", FlashProg, 1, "Flash Programming : flashprog [
]" }, { "flashprog", FlashProg, 1, "Flash Programming : flashprog -SubVendorID " }, { "flashprog", FlashProg, 1, "Flash Programming : flashprog -Jump
" }, @@ -1676,6 +1728,7 @@ struct SCommand CommandTable[] = { "licimport", lic_import, 1, "License Import : licimport" }, { "licexport", lic_export, 1, "License Export : licexport" }, { "licerase", lic_erase, 1, "License Erase : licerase" }, + { "read_id", read_id, 1, "Read Unique ID : read_id" }, { NULL,NULL,0 } }; diff --git a/ddbridge/ddbridge-core.c b/ddbridge/ddbridge-core.c index 7d3a14a..8530957 100644 --- a/ddbridge/ddbridge-core.c +++ b/ddbridge/ddbridge-core.c @@ -1,7 +1,7 @@ /* * ddbridge-core.c: Digital Devices bridge core functions * - * Copyright (C) 2010-2015 Digital Devices GmbH + * Copyright (C) 2010-2016 Digital Devices GmbH * Marcus Metzler * Ralph Metzler * @@ -28,7 +28,7 @@ DEFINE_MUTEX(redirect_lock); static int ci_bitrate = 72000; module_param(ci_bitrate, int, 0444); -MODULE_PARM_DESC(ci_bitrate, " Bitrate for output to CI."); +MODULE_PARM_DESC(ci_bitrate, " Bitrate in KHz for output to CI."); static int ts_loop = -1; module_param(ts_loop, int, 0444); @@ -50,6 +50,22 @@ static int old_quattro; module_param(old_quattro, int, 0444); MODULE_PARM_DESC(old_quattro, "old quattro LNB input order "); +static int xo2_speed = 2; +module_param(xo2_speed, int, 0444); +MODULE_PARM_DESC(xo2_speed, "default transfer speed for xo2 based duoflex, 0=55,1=75,2=90,3=104 MBit/s, default=2, use attribute to change for individual cards"); + +#ifdef __arm__ +static int alt_dma = 1; +#else +static int alt_dma; +#endif +module_param(alt_dma, int, 0444); +MODULE_PARM_DESC(alt_dma, "use alternative DMA buffer handling"); + +static int no_init; +module_param(no_init, int, 0444); +MODULE_PARM_DESC(no_init, "do not initialize most devices"); + #define DDB_MAX_ADAPTER 64 static struct ddb *ddbs[DDB_MAX_ADAPTER]; @@ -60,20 +76,269 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); #include "ddbridge-ns.c" -static void ddb_set_dma_table(struct ddb *dev, struct ddb_dma *dma) +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static struct ddb_regset octopus_mod_odma = { + .base = 0x300, + .num = 0x0a, + .size = 0x10, +}; + +static struct ddb_regset octopus_mod_odma_buf = { + .base = 0x2000, + .num = 0x0a, + .size = 0x100, +}; + +static struct ddb_regset octopus_mod_channel = { + .base = 0x400, + .num = 0x0a, + .size = 0x40, +}; + +/****************************************************************************/ + +static struct ddb_regset octopus_mod_2_odma = { + .base = 0x400, + .num = 0x18, + .size = 0x10, +}; + +static struct ddb_regset octopus_mod_2_odma_buf = { + .base = 0x8000, + .num = 0x18, + .size = 0x100, +}; + +static struct ddb_regset octopus_mod_2_channel = { + .base = 0x800, + .num = 0x18, + .size = 0x40, +}; + +/****************************************************************************/ + +static struct ddb_regset octopus_input = { + .base = 0x200, + .num = 0x08, + .size = 0x10, +}; + +static struct ddb_regset octopus_output = { + .base = 0x280, + .num = 0x08, + .size = 0x10, +}; + +static struct ddb_regset octopus_idma = { + .base = 0x300, + .num = 0x08, + .size = 0x10, +}; + +static struct ddb_regset octopus_idma_buf = { + .base = 0x2000, + .num = 0x08, + .size = 0x100, +}; + +static struct ddb_regset octopus_odma = { + .base = 0x380, + .num = 0x04, + .size = 0x10, +}; + +static struct ddb_regset octopus_odma_buf = { + .base = 0x2800, + .num = 0x04, + .size = 0x100, +}; + +static struct ddb_regset octopus_i2c = { + .base = 0x80, + .num = 0x04, + .size = 0x20, +}; + +static struct ddb_regset octopus_i2c_buf = { + .base = 0x1000, + .num = 0x04, + .size = 0x200, +}; + +/****************************************************************************/ + +static struct ddb_regset octopro_input = { + .base = 0x400, + .num = 0x14, + .size = 0x10, +}; + +static struct ddb_regset octopro_output = { + .base = 0x600, + .num = 0x0a, + .size = 0x10, +}; + +static struct ddb_regset octopro_idma = { + .base = 0x800, + .num = 0x40, + .size = 0x10, +}; + +static struct ddb_regset octopro_idma_buf = { + .base = 0x4000, + .num = 0x40, + .size = 0x100, +}; + +static struct ddb_regset octopro_odma = { + .base = 0xc00, + .num = 0x20, + .size = 0x10, +}; + +static struct ddb_regset octopro_odma_buf = { + .base = 0x8000, + .num = 0x20, + .size = 0x100, +}; + +static struct ddb_regset octopro_i2c = { + .base = 0x200, + .num = 0x0a, + .size = 0x20, +}; + +static struct ddb_regset octopro_i2c_buf = { + .base = 0x2000, + .num = 0x0a, + .size = 0x200, +}; + +static struct ddb_regset octopro_gtl = { + .base = 0xe00, + .num = 0x03, + .size = 0x40, +}; + +/****************************************************************************/ +/****************************************************************************/ + + +static struct ddb_regmap octopus_map = { + .irq_version = 1, + .irq_base_i2c = 0, + .irq_base_idma = 8, + .irq_base_odma = 16, + .i2c = &octopus_i2c, + .i2c_buf = &octopus_i2c_buf, + .idma = &octopus_idma, + .idma_buf = &octopus_idma_buf, + .odma = &octopus_odma, + .odma_buf = &octopus_odma_buf, + .input = &octopus_input, + .output = &octopus_output, +}; + +static struct ddb_regmap octopro_map = { + .irq_version = 2, + .irq_base_i2c = 32, + .irq_base_idma = 64, + .irq_base_odma = 128, + .irq_base_gtl = 8, + .i2c = &octopro_i2c, + .i2c_buf = &octopro_i2c_buf, + .idma = &octopro_idma, + .idma_buf = &octopro_idma_buf, + .odma = &octopro_odma, + .odma_buf = &octopro_odma_buf, + .input = &octopro_input, + .output = &octopro_output, + .gtl = &octopro_gtl, +}; + +static struct ddb_regmap octopro_hdin_map = { + .irq_version = 2, + .irq_base_i2c = 32, + .irq_base_idma = 64, + .irq_base_odma = 128, + .i2c = &octopro_i2c, + .i2c_buf = &octopro_i2c_buf, + .idma = &octopro_idma, + .idma_buf = &octopro_idma_buf, + .odma = &octopro_odma, + .odma_buf = &octopro_odma_buf, + .input = &octopro_input, + .output = &octopro_output, +}; + +static struct ddb_regmap octopus_mod_map = { + .irq_version = 1, + .irq_base_odma = 8, + .irq_base_rate = 18, + .output = &octopus_output, + .odma = &octopus_mod_odma, + .odma_buf = &octopus_mod_odma_buf, + .channel = &octopus_mod_channel, +}; + + +static struct ddb_regmap octopus_mod_2_map = { + .irq_version = 2, + .irq_base_odma = 64, + .irq_base_rate = 32, + .output = &octopus_output, + .odma = &octopus_mod_2_odma, + .odma_buf = &octopus_mod_2_odma_buf, + .channel = &octopus_mod_2_channel, +}; + + +/****************************************************************************/ + +static struct ddb_info ddb_s2_48 = { + .type = DDB_OCTOPUS_MAX, + .name = "Digital Devices MAX S8 4/8", + .regmap = &octopus_map, + .port_num = 4, + .i2c_mask = 0x01, + .board_control = 1, +}; + +static struct ddb_info ddb_ct_8 = { + .type = DDB_OCTOPUS_MAX_CT, + .name = "Digital Devices MAX CT8", + .regmap = &octopus_map, + .port_num = 4, + .i2c_mask = 0x0f, + .board_control = 0x0ff, + .board_control_2 = 0xf00, + .ts_quirks = TS_QUIRK_SERIAL, +}; + + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static void ddb_set_dma_table(struct ddb_io *io) { - u32 i, base; + struct ddb *dev = io->port->dev; + struct ddb_dma *dma = io->dma; + u32 i; u64 mem; if (!dma) return; - base = DMA_BASE_ADDRESS_TABLE + dma->nr * 0x100; for (i = 0; i < dma->num; i++) { mem = dma->pbuf[i]; - ddbwritel(dev, mem & 0xffffffff, base + i * 8); - ddbwritel(dev, mem >> 32, base + i * 8 + 4); + ddbwritel(dev, mem & 0xffffffff, dma->bufregs + i * 8); + ddbwritel(dev, mem >> 32, dma->bufregs + i * 8 + 4); } - dma->bufreg = (dma->div << 16) | + dma->bufval = (dma->div << 16) | ((dma->num & 0x1f) << 11) | ((dma->size >> 7) & 0x7ff); } @@ -81,11 +346,15 @@ static void ddb_set_dma_table(struct ddb *dev, struct ddb_dma *dma) static void ddb_set_dma_tables(struct ddb *dev) { u32 i; - - for (i = 0; i < dev->link[0].info->port_num * 2; i++) - ddb_set_dma_table(dev, dev->input[i].dma); - for (i = 0; i < dev->link[0].info->port_num; i++) - ddb_set_dma_table(dev, dev->output[i].dma); + + for (i = 0; i < DDB_MAX_PORT; i++) { + if (dev->port[i].input[0]) + ddb_set_dma_table(dev->port[i].input[0]); + if (dev->port[i].input[1]) + ddb_set_dma_table(dev->port[i].input[1]); + if (dev->port[i].output) + ddb_set_dma_table(dev->port[i].output); + } } @@ -100,8 +369,8 @@ static void ddb_redirect_dma(struct ddb *dev, u32 i, base; u64 mem; - sdma->bufreg = ddma->bufreg; - base = DMA_BASE_ADDRESS_TABLE + sdma->nr * 0x100; + sdma->bufval = ddma->bufval; + base = sdma->bufregs; for (i = 0; i < ddma->num; i++) { mem = ddma->pbuf[i]; ddbwritel(dev, mem & 0xffffffff, base + i * 8); @@ -135,7 +404,7 @@ static int ddb_unredirect(struct ddb_port *port) oredi->dma, iredo->dma); } port->input[0]->redo = 0; - ddb_set_dma_table(port->dev, port->input[0]->dma); + ddb_set_dma_table(port->input[0]); } oredi->redi = iredi; port->input[0]->redi = 0; @@ -143,7 +412,7 @@ static int ddb_unredirect(struct ddb_port *port) oredi->redo = 0; port->output->redi = 0; - ddb_set_dma_table(oredi->port->dev, oredi->dma); + ddb_set_dma_table(oredi); done: mutex_unlock(&redirect_lock); return 0; @@ -151,9 +420,9 @@ done: static int ddb_redirect(u32 i, u32 p) { - struct ddb *idev = ddbs[(i >> 4) & 0x1f]; + struct ddb *idev = ddbs[(i >> 4) & 0x3f]; struct ddb_input *input, *input2; - struct ddb *pdev = ddbs[(p >> 4) & 0x1f]; + struct ddb *pdev = ddbs[(p >> 4) & 0x3f]; struct ddb_port *port; if (!idev->has_dma || !pdev->has_dma) @@ -199,7 +468,6 @@ static int ddb_redirect(u32 i, u32 p) /****************************************************************************/ /****************************************************************************/ -#ifdef DDB_ALT_DMA static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir) { int i; @@ -208,54 +476,16 @@ static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir) return; for (i = 0; i < dma->num; i++) { if (dma->vbuf[i]) { - dma_unmap_single(&pdev->dev, dma->pbuf[i], - dma->size, - dir ? DMA_TO_DEVICE : - DMA_FROM_DEVICE); - kfree(dma->vbuf[i]); - dma->vbuf[i] = NULL; - } - } -} - -static int dma_alloc(struct pci_dev *pdev, struct ddb_dma *dma, int dir) -{ - int i; - - if (!dma) - return 0; - for (i = 0; i < dma->num; i++) { - dma->vbuf[i] = kmalloc(dma->size, __GFP_REPEAT); - if (!dma->vbuf[i]) - return -ENOMEM; - dma->pbuf[i] = dma_map_single(&pdev->dev, dma->vbuf[i], - dma->size, - dir ? DMA_TO_DEVICE : - DMA_FROM_DEVICE); - if (dma_mapping_error(&pdev->dev, dma->pbuf[i])) { - kfree(dma->vbuf[i]); - return -ENOMEM; - } - } - return 0; -} -#else - -static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir) -{ - int i; - - if (!dma) - return; - for (i = 0; i < dma->num; i++) { - if (dma->vbuf[i]) { -#if 0 - pci_free_consistent(pdev, dma->size, - dma->vbuf[i], dma->pbuf[i]); -#else - dma_free_coherent(&pdev->dev, dma->size, - dma->vbuf[i], dma->pbuf[i]); -#endif + if (alt_dma) { + dma_unmap_single(&pdev->dev, dma->pbuf[i], + dma->size, + dir ? DMA_TO_DEVICE : + DMA_FROM_DEVICE); + kfree(dma->vbuf[i]); + } else + dma_free_coherent(&pdev->dev, dma->size, + dma->vbuf[i], + dma->pbuf[i]); dma->vbuf[i] = 0; } } @@ -268,26 +498,38 @@ static int dma_alloc(struct pci_dev *pdev, struct ddb_dma *dma, int dir) if (!dma) return 0; for (i = 0; i < dma->num; i++) { -#if 0 - dma->vbuf[i] = pci_alloc_consistent(pdev, dma->size, - &dma->pbuf[i]); -#else - dma->vbuf[i] = dma_alloc_coherent(&pdev->dev, dma->size, - &dma->pbuf[i], GFP_KERNEL); -#endif - if (!dma->vbuf[i]) - return -ENOMEM; + if (alt_dma) { + dma->vbuf[i] = kmalloc(dma->size, __GFP_REPEAT); + if (!dma->vbuf[i]) + return -ENOMEM; + dma->pbuf[i] = dma_map_single(&pdev->dev, + dma->vbuf[i], + dma->size, + dir ? DMA_TO_DEVICE : + DMA_FROM_DEVICE); + if (dma_mapping_error(&pdev->dev, dma->pbuf[i])) { + kfree(dma->vbuf[i]); + dma->vbuf[i] = 0; + return -ENOMEM; + } + } else { + dma->vbuf[i] = dma_alloc_coherent(&pdev->dev, + dma->size, + &dma->pbuf[i], + GFP_KERNEL); + if (!dma->vbuf[i]) + return -ENOMEM; + } } return 0; } -#endif static int ddb_buffers_alloc(struct ddb *dev) { int i; struct ddb_port *port; - for (i = 0; i < dev->link[0].info->port_num; i++) { + for (i = 0; i < dev->port_num; i++) { port = &dev->port[i]; switch (port->class) { case DDB_PORT_TUNER: @@ -325,7 +567,7 @@ static void ddb_buffers_free(struct ddb *dev) int i; struct ddb_port *port; - for (i = 0; i < dev->link[0].info->port_num; i++) { + for (i = 0; i < dev->port_num; i++) { port = &dev->port[i]; if (port->input[0] && port->input[0]->dma) @@ -337,47 +579,104 @@ static void ddb_buffers_free(struct ddb *dev) } } +static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags) +{ + struct ddb *dev = output->port->dev; + u32 bitrate = output->port->obr, max_bitrate = 72000; + u32 gap = 4, nco = 0; + + *con = 0x1C; + if (output->port->gap != 0xffffffff) { + flags |= 1; + gap = output->port->gap; + } + if (dev->link[0].info->type == DDB_OCTOPUS_CI && output->port->nr > 1) { + *con = 0x10c; + if (dev->link[0].ids.regmapid >= 0x10003 && !(flags & 1)) { + if (!(flags & 2)) { + /* NCO */ + max_bitrate = 0; + gap = 0; + if (bitrate != 72000) { + if (bitrate >= 96000) + *con |= 0x800; + else { + *con |= 0x1000; + nco = (bitrate * 8192 + 71999) / 72000; + } + } + } else { + /* Divider and gap */ + *con |= 0x1810; + if (bitrate <= 64000) { + max_bitrate = 64000; + nco = 8; + } else if( bitrate <= 72000) { + max_bitrate = 72000; + nco = 7; + } else { + max_bitrate = 96000; + nco = 5; + } + } + } else { + if (bitrate > 72000) { + *con |= 0x810; /* 96 MBit/s and gap */ + max_bitrate = 96000; + } + } + } + if (max_bitrate > 0) { + if (bitrate > max_bitrate) + bitrate = max_bitrate; + if (bitrate < 31000) + bitrate = 31000; + gap = ((max_bitrate - bitrate) * 94) / bitrate; + if (gap < 2) + *con &= ~0x10; /* Disable gap */ + else + gap -= 2; + if (gap > 127) + gap = 127; + } + *con2 = (nco << 16) | gap; + return; +} + static void ddb_output_start(struct ddb_output *output) { struct ddb *dev = output->port->dev; - u32 con2; - - con2 = ((output->port->obr << 13) + 71999) / 72000; - con2 = (con2 << 16) | output->port->gap; + u32 con = 0x11c, con2 = 0; if (output->dma) { spin_lock_irq(&output->dma->lock); output->dma->cbuf = 0; output->dma->coff = 0; output->dma->stat = 0; - ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma->nr)); + ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma)); } if (output->port->class == DDB_PORT_MOD) ddbridge_mod_output_start(output); else { - ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); - ddbwritel(dev, 2, TS_OUTPUT_CONTROL(output->nr)); - ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); - ddbwritel(dev, 0x3c, TS_OUTPUT_CONTROL(output->nr)); - ddbwritel(dev, con2, TS_OUTPUT_CONTROL2(output->nr)); + if (output->port->input[0]->port->class == DDB_PORT_LOOP) + con = (1UL << 13) | 0x14; + else + calc_con(output, &con, &con2, 0); + ddbwritel(dev, 0, TS_CONTROL(output)); + ddbwritel(dev, 2, TS_CONTROL(output)); + ddbwritel(dev, 0, TS_CONTROL(output)); + ddbwritel(dev, con, TS_CONTROL(output)); + ddbwritel(dev, con2, TS_CONTROL2(output)); } if (output->dma) { - ddbwritel(dev, output->dma->bufreg, - DMA_BUFFER_SIZE(output->dma->nr)); - ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma->nr)); + ddbwritel(dev, output->dma->bufval, + DMA_BUFFER_SIZE(output->dma)); + ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma)); ddbwritel(dev, 1, DMA_BASE_READ); - ddbwritel(dev, 3, DMA_BUFFER_CONTROL(output->dma->nr)); - } - if (output->port->class != DDB_PORT_MOD) { - if (output->port->input[0]->port->class == DDB_PORT_LOOP) - /*ddbwritel(dev, 0x15, TS_OUTPUT_CONTROL(output->nr)); - ddbwritel(dev, 0x45, - TS_OUTPUT_CONTROL(output->nr));*/ - ddbwritel(dev, (1 << 13) | 0x15, - TS_OUTPUT_CONTROL(output->nr)); - else - ddbwritel(dev, 0x11d, TS_OUTPUT_CONTROL(output->nr)); + ddbwritel(dev, 3, DMA_BUFFER_CONTROL(output->dma)); } + if (output->port->class != DDB_PORT_MOD) + ddbwritel(dev, con | 1, TS_CONTROL(output)); if (output->dma) { output->dma->running = 1; spin_unlock_irq(&output->dma->lock); @@ -393,9 +692,9 @@ static void ddb_output_stop(struct ddb_output *output) if (output->port->class == DDB_PORT_MOD) ddbridge_mod_output_stop(output); else - ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); + ddbwritel(dev, 0, TS_CONTROL(output)); if (output->dma) { - ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma->nr)); + ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma)); output->dma->running = 0; spin_unlock_irq(&output->dma->lock); } @@ -408,9 +707,9 @@ static void ddb_input_stop(struct ddb_input *input) if (input->dma) spin_lock_irq(&input->dma->lock); - ddbwritel(dev, 0, tag | TS_INPUT_CONTROL(input->nr)); + ddbwritel(dev, 0, tag | TS_CONTROL(input)); if (input->dma) { - ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); + ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma)); input->dma->running = 0; spin_unlock_irq(&input->dma->lock); } @@ -421,38 +720,33 @@ static void ddb_input_stop(struct ddb_input *input) static void ddb_input_start(struct ddb_input *input) { struct ddb *dev = input->port->dev; - /* u32 tsbase = TS_INPUT_BASE + input->nr * 0x10; */ - u32 tag = DDB_LINK_TAG(input->port->lnr); if (input->dma) { spin_lock_irq(&input->dma->lock); input->dma->cbuf = 0; input->dma->coff = 0; input->dma->stat = 0; - ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); + ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma)); } - ddbwritel(dev, 0, tag | TS_INPUT_CONTROL2(input->nr)); - ddbwritel(dev, 0, tag | TS_INPUT_CONTROL(input->nr)); - ddbwritel(dev, 2, tag | TS_INPUT_CONTROL(input->nr)); - ddbwritel(dev, 0, tag | TS_INPUT_CONTROL(input->nr)); + ddbwritel(dev, 0, TS_CONTROL(input)); + ddbwritel(dev, 2, TS_CONTROL(input)); + ddbwritel(dev, 0, TS_CONTROL(input)); if (input->dma) { - ddbwritel(dev, input->dma->bufreg, - DMA_BUFFER_SIZE(input->dma->nr)); - ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); + ddbwritel(dev, input->dma->bufval, + DMA_BUFFER_SIZE(input->dma)); + ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma)); ddbwritel(dev, 1, DMA_BASE_WRITE); - ddbwritel(dev, 3, DMA_BUFFER_CONTROL(input->dma->nr)); + ddbwritel(dev, 3, DMA_BUFFER_CONTROL(input->dma)); } if (dev->link[0].info->type == DDB_OCTONET) - ddbwritel(dev, 0x01, tag | TS_INPUT_CONTROL(input->nr)); + ddbwritel(dev, 0x01, TS_CONTROL(input)); else - ddbwritel(dev, 0x09, tag | TS_INPUT_CONTROL(input->nr)); + ddbwritel(dev, 0x09, TS_CONTROL(input)); if (input->dma) { input->dma->running = 1; spin_unlock_irq(&input->dma->lock); } - /*printk("input_start %u.%u.%u\n", - dev->nr, input->port->lnr, input->nr); */ } @@ -581,12 +875,11 @@ static ssize_t ddb_output_write(struct ddb_output *output, output->dma->coff, buf, len)) return -EIO; -#ifdef DDB_ALT_DMA - dma_sync_single_for_device(dev->dev, - output->dma->pbuf[ - output->dma->cbuf], - output->dma->size, DMA_TO_DEVICE); -#endif + if (alt_dma) + dma_sync_single_for_device(dev->dev, + output->dma->pbuf[ + output->dma->cbuf], + output->dma->size, DMA_TO_DEVICE); left -= len; buf += len; output->dma->coff += len; @@ -598,7 +891,7 @@ static ssize_t ddb_output_write(struct ddb_output *output, ddbwritel(dev, (output->dma->cbuf << 11) | (output->dma->coff >> 7), - DMA_BUFFER_ACK(output->dma->nr)); + DMA_BUFFER_ACK(output->dma)); } return count - left; } @@ -608,7 +901,7 @@ static u32 ddb_input_free_bytes(struct ddb_input *input) { struct ddb *dev = input->port->dev; u32 idx, off, stat = input->dma->stat; - u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma->nr)); + u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma)); idx = (stat >> 11) & 0x1f; off = (stat & 0x7ff) << 7; @@ -682,14 +975,14 @@ static u32 ddb_input_avail(struct ddb_input *input) { struct ddb *dev = input->port->dev; u32 idx, off, stat = input->dma->stat; - u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma->nr)); + u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma)); idx = (stat >> 11) & 0x1f; off = (stat & 0x7ff) << 7; if (ctrl & 4) { pr_err("IA %d %d %08x\n", idx, off, ctrl); - ddbwritel(dev, stat, DMA_BUFFER_ACK(input->dma->nr)); + ddbwritel(dev, stat, DMA_BUFFER_ACK(input->dma)); return 0; } if (input->dma->cbuf != idx) @@ -714,11 +1007,10 @@ static size_t ddb_input_read(struct ddb_input *input, free = input->dma->size - input->dma->coff; if (free > left) free = left; -#ifdef DDB_ALT_DMA - dma_sync_single_for_cpu(dev->dev, - input->dma->pbuf[input->dma->cbuf], - input->dma->size, DMA_FROM_DEVICE); -#endif + if (alt_dma) + dma_sync_single_for_cpu(dev->dev, + input->dma->pbuf[input->dma->cbuf], + input->dma->size, DMA_FROM_DEVICE); ret = copy_to_user(buf, input->dma->vbuf[input->dma->cbuf] + input->dma->coff, free); if (ret) @@ -730,9 +1022,10 @@ static size_t ddb_input_read(struct ddb_input *input, input->dma->num; } left -= free; + buf += free; ddbwritel(dev, (input->dma->cbuf << 11) | (input->dma->coff >> 7), - DMA_BUFFER_ACK(input->dma->nr)); + DMA_BUFFER_ACK(input->dma)); } return count; } @@ -938,20 +1231,6 @@ static struct dvb_device dvbdev_mod = { .fops = &mod_fops, }; - -#if 0 -static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) -{ - int i; - - for (i = 0; i < dev->link[0].info->port_num * 2; i++) { - if (dev->input[i].fe == fe) - return &dev->input[i]; - } - return NULL; -} -#endif - static int locked_gate_ctrl(struct dvb_frontend *fe, int enable) { struct ddb_input *input = fe->sec_priv; @@ -2117,7 +2396,7 @@ static int init_xo2(struct ddb_port *port) i2c_write_reg(i2c, 0x10, 0x08, 0x07); /* speed: 0=55,1=75,2=90,3=104 MBit/s */ - i2c_write_reg(i2c, 0x10, 0x09, 2); + i2c_write_reg(i2c, 0x10, 0x09, xo2_speed); if (dev->link[port->lnr].info->con_clock) { pr_info("Setting continuous clock for XO2\n"); @@ -2237,6 +2516,15 @@ static void ddb_port_probe(struct ddb_port *port) port->class = DDB_PORT_MOD; return; } + + if (dev->link[l].info->type == DDB_OCTOPRO_HDIN) { + if( port->nr == 0 ) { + dev->link[l].info->type = DDB_OCTOPUS; + port->name = "HDIN"; + port->class = DDB_PORT_LOOP; + } + return; + } if (dev->link[l].info->type == DDB_OCTOPUS_MAX) { port->name = "DUAL DVB-S2 MAX"; @@ -2800,7 +3088,7 @@ static void input_write_output(struct ddb_input *input, struct ddb_output *output) { ddbwritel(output->port->dev, - input->dma->stat, DMA_BUFFER_ACK(output->dma->nr)); + input->dma->stat, DMA_BUFFER_ACK(output->dma)); output->dma->cbuf = (input->dma->stat >> 11) & 0x1f; output->dma->coff = (input->dma->stat & 0x7ff) << 7; } @@ -2809,7 +3097,7 @@ static void output_ack_input(struct ddb_output *output, struct ddb_input *input) { ddbwritel(input->port->dev, - output->dma->stat, DMA_BUFFER_ACK(input->dma->nr)); + output->dma->stat, DMA_BUFFER_ACK(input->dma)); } static void input_write_dvb(struct ddb_input *input, @@ -2833,9 +3121,13 @@ static void input_write_dvb(struct ddb_input *input, /*pr_err("Overflow dma %d\n", dma->nr);*/ ack = 1; } -#ifdef DDB_ALT_DMA - dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf], - dma2->size, DMA_FROM_DEVICE); + if (alt_dma) + dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf], + dma2->size, DMA_FROM_DEVICE); +#if 0 + pr_info("%02x %02x %02x %02x \n", + dma2->vbuf[dma->cbuf][0], dma2->vbuf[dma->cbuf][1], + dma2->vbuf[dma->cbuf][2], dma2->vbuf[dma->cbuf][3]); #endif dvb_dmx_swfilter_packets(&dvb->demux, dma2->vbuf[dma->cbuf], @@ -2843,9 +3135,9 @@ static void input_write_dvb(struct ddb_input *input, dma->cbuf = (dma->cbuf + 1) % dma2->num; if (ack) ddbwritel(dev, (dma->cbuf << 11), - DMA_BUFFER_ACK(dma->nr)); - dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); - dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); + DMA_BUFFER_ACK(dma)); + dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma)); + dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma)); } } @@ -2868,8 +3160,8 @@ static void input_tasklet(unsigned long data) spin_unlock_irqrestore(&dma->lock, flags); return; } - dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); - dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); + dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma)); + dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma)); #if 0 if (4 & dma->ctrl) @@ -2916,8 +3208,8 @@ static void output_handler(unsigned long data) spin_unlock(&dma->lock); return; } - dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); - dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); + dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma)); + dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma)); if (output->redi) output_ack_input(output, output->redi); wake_up(&dma->wq); @@ -2929,17 +3221,32 @@ static void output_handler(unsigned long data) /****************************************************************************/ -static void ddb_dma_init(struct ddb_dma *dma, int nr, void *io, int out) +static struct ddb_regmap *io_regmap(struct ddb_io *io, int link) { -#ifndef DDB_USE_WORK - unsigned long priv = (unsigned long) io; -#endif + struct ddb_info *info; + if (link) + info = io->port->dev->link[io->port->lnr].info; + else + info = io->port->dev->link[0].info; + if (!info) + return NULL; + return info->regmap; +} + +static void ddb_dma_init(struct ddb_io *io, int nr, int out) +{ + struct ddb_dma *dma; + struct ddb_regmap *rm = io_regmap(io, 0); + + dma = out ? &io->port->dev->odma[nr] : &io->port->dev->idma[nr]; + io->dma = dma; dma->io = io; - dma->nr = nr; spin_lock_init(&dma->lock); init_waitqueue_head(&dma->wq); if (out) { + dma->regs = rm->odma->base + rm->odma->size * nr; + dma->bufregs = rm->odma_buf->base + rm->odma_buf->size * nr; dma->num = OUTPUT_DMA_BUFS; dma->size = OUTPUT_DMA_SIZE; dma->div = OUTPUT_DMA_IRQ_DIV; @@ -2947,63 +3254,68 @@ static void ddb_dma_init(struct ddb_dma *dma, int nr, void *io, int out) #ifdef DDB_USE_WORK INIT_WORK(&dma->work, input_work); #else - tasklet_init(&dma->tasklet, input_tasklet, priv); + tasklet_init(&dma->tasklet, input_tasklet, (unsigned long) io); #endif + dma->regs = rm->idma->base + rm->idma->size * nr; + dma->bufregs = rm->idma_buf->base + rm->idma_buf->size * nr; dma->num = INPUT_DMA_BUFS; dma->size = INPUT_DMA_SIZE; dma->div = INPUT_DMA_IRQ_DIV; } + ddbwritel(io->port->dev, 0, DMA_BUFFER_ACK(dma)); + pr_info("init link %u, io %u, dma %u, dmaregs %08x bufregs %08x\n", + io->port->lnr, io->nr, nr, dma->regs, dma->bufregs); } -static void ddb_input_init(struct ddb_port *port, int nr, int pnr, - int dma_nr, int anr) +static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr) { struct ddb *dev = port->dev; struct ddb_input *input = &dev->input[anr]; + struct ddb_regmap *rm; - if (dev->has_dma) { - dev->handler[dma_nr + 8] = input_handler; - dev->handler_data[dma_nr + 8] = (unsigned long) input; - } port->input[pnr] = input; input->nr = nr; input->port = port; + rm = io_regmap(input, 1); + input->regs = DDB_LINK_TAG(port->lnr) | + (rm->input->base + rm->input->size * nr); + pr_info("init link %u, input %u, regs %08x\n", port->lnr, nr, input->regs); if (dev->has_dma) { - input->dma = &dev->dma[dma_nr]; - ddb_dma_init(input->dma, dma_nr, (void *) input, 0); + struct ddb_regmap *rm0 = io_regmap(input, 0); + u32 base = rm0->irq_base_idma; + u32 dma_nr = nr; + + if (port->lnr) + dma_nr += 32 + (port->lnr - 1) * 8; + + pr_info("init link %u, input %u, handler %u\n", port->lnr, nr, dma_nr + base); + dev->handler[0][dma_nr + base] = input_handler; + dev->handler_data[0][dma_nr + base] = (unsigned long) input; + ddb_dma_init(input, dma_nr, 0); } - ddbwritel(dev, 0, TS_INPUT_CONTROL(nr)); - ddbwritel(dev, 2, TS_INPUT_CONTROL(nr)); - ddbwritel(dev, 0, TS_INPUT_CONTROL(nr)); - if (input->dma) - ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); } -static void ddb_output_init(struct ddb_port *port, int nr, int dma_nr) +static void ddb_output_init(struct ddb_port *port, int nr) { struct ddb *dev = port->dev; struct ddb_output *output = &dev->output[nr]; + struct ddb_regmap *rm; - if (dev->has_dma) { - dev->handler[dma_nr + 8] = output_handler; - dev->handler_data[dma_nr + 8] = (unsigned long) output; - } port->output = output; output->nr = nr; output->port = port; + rm = io_regmap(output, 1); + output->regs = DDB_LINK_TAG(port->lnr) | + (rm->output->base + rm->output->size * nr); + pr_info("init link %u, output %u, regs %08x\n", port->lnr, nr, output->regs); if (dev->has_dma) { - output->dma = &dev->dma[dma_nr]; - ddb_dma_init(output->dma, dma_nr, (void *) output, 1); + struct ddb_regmap *rm0 = io_regmap(output, 0); + u32 base = rm0->irq_base_odma; + + dev->handler[0][nr + base] = output_handler; + dev->handler_data[0][nr + base] = (unsigned long) output; + ddb_dma_init(output, nr, 1); } - if (output->port->class == DDB_PORT_MOD) { - /*ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));*/ - } else { - ddbwritel(dev, 0, TS_OUTPUT_CONTROL(nr)); - ddbwritel(dev, 2, TS_OUTPUT_CONTROL(nr)); - ddbwritel(dev, 0, TS_OUTPUT_CONTROL(nr)); - } - if (output->dma) - ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma->nr)); } static int ddb_port_match_i2c(struct ddb_port *port) @@ -3021,9 +3333,23 @@ static int ddb_port_match_i2c(struct ddb_port *port) return 0; } +static int ddb_port_match_link_i2c(struct ddb_port *port) +{ + struct ddb *dev = port->dev; + u32 i; + + for (i = 0; i < dev->i2c_num; i++) { + if (dev->i2c[i].link == port->lnr) { + port->i2c = &dev->i2c[i]; + return 1; + } + } + return 0; +} + static void ddb_ports_init(struct ddb *dev) { - u32 i, l, p, li2c; + u32 i, l, p; struct ddb_port *port; struct ddb_info *info; struct ddb_regmap *rm; @@ -3035,24 +3361,18 @@ static void ddb_ports_init(struct ddb *dev) rm = info->regmap; if (!rm) continue; - for (li2c = 0; li2c < dev->i2c_num; li2c++) - if (dev->i2c[li2c].link == l) - break; for (i = 0; i < info->port_num; i++, p++) { port = &dev->port[p]; port->dev = dev; port->nr = i; port->lnr = l; port->pnr = p; - port->gap = 4; + port->gap = 0xffffffff; port->obr = ci_bitrate; mutex_init(&port->i2c_gate_lock); - - if (!ddb_port_match_i2c(port)) { + if (!ddb_port_match_i2c(port)) if (info->type == DDB_OCTOPUS_MAX) - port->i2c = &dev->i2c[li2c]; - } - + ddb_port_match_link_i2c(port); ddb_port_probe(port); port->dvb[0].adap = &dev->adap[2 * p]; @@ -3065,54 +3385,51 @@ static void ddb_ports_init(struct ddb *dev) port->name = "DuoFlex CI_B"; port->i2c = dev->port[p - 1].i2c; } - pr_info("Port %u: Link %u, Link Port %u (TAB %u): %s\n", port->pnr, port->lnr, port->nr, port->nr + 1, port->name); if (port->class == DDB_PORT_CI && port->type == DDB_CI_EXTERNAL_XO2) { - ddb_input_init(port, 2 * i, 0, 2 * i, 2 * i); - ddb_output_init(port, i, i + 8); + ddb_input_init(port, 2 * i, 0, 2 * i); + ddb_output_init(port, i); continue; } if (port->class == DDB_PORT_CI && port->type == DDB_CI_EXTERNAL_XO2_B) { - ddb_input_init(port, 2 * i - 1, 0, - 2 * i - 1, 2 * i - 1); - ddb_output_init(port, i, i + 8); + ddb_input_init(port, 2 * i - 1, 0, 2 * i - 1); + ddb_output_init(port, i); continue; } + if (port->class == DDB_PORT_NONE) + continue; switch (dev->link[l].info->type) { case DDB_OCTOPUS_CI: if (i >= 2) { - ddb_input_init(port, 2 + i, 0, - 2 + i, 2 + i); - ddb_input_init(port, 4 + i, 1, - 4 + i, 4 + i); - ddb_output_init(port, i, i + 8); + ddb_input_init(port, 2 + i, 0, 2 + i); + ddb_input_init(port, 4 + i, 1, 4 + i); + ddb_output_init(port, i); break; } /* fallthrough */ case DDB_OCTONET: case DDB_OCTOPUS: - ddb_input_init(port, 2 * i, 0, 2 * i, 2 * i); - ddb_input_init(port, 2 * i + 1, 1, - 2 * i + 1, 2 * i + 1); - ddb_output_init(port, i, i + 8); + case DDB_OCTOPRO: + ddb_input_init(port, 2 * i, 0, 2 * i); + ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1); + ddb_output_init(port, i); break; case DDB_OCTOPUS_MAX: case DDB_OCTOPUS_MAX_CT: - ddb_input_init(port, 2 * i, 0, 2 * i, 2 * p); - ddb_input_init(port, 2 * i + 1, - 1, 2 * i + 1, 2 * p + 1); + ddb_input_init(port, 2 * i, 0, 2 * p); + ddb_input_init(port, 2 * i + 1, 1, 2 * p + 1); break; case DDB_MOD: - ddb_output_init(port, i, i); - dev->handler[i + 18] = + ddb_output_init(port, i); + dev->handler[0][i + rm->irq_base_rate] = ddbridge_mod_rate_handler; - dev->handler_data[i + 18] = + dev->handler_data[0][i + rm->irq_base_rate] = (unsigned long) &dev->output[i]; break; default: @@ -3153,10 +3470,23 @@ static void ddb_ports_release(struct ddb *dev) /****************************************************************************/ #define IRQ_HANDLE(_nr) \ - do { if ((s & (1UL << _nr)) && dev->handler[_nr]) \ - dev->handler[_nr](dev->handler_data[_nr]); } \ + do { if ((s & (1UL << ((_nr) & 0x1f))) && dev->handler[0][_nr]) \ + dev->handler[0][_nr](dev->handler_data[0][_nr]); } \ while (0) +#define IRQ_HANDLE_BYTE(_n) \ + if (s & (0x000000ff << ((_n) & 0x1f))) { \ + IRQ_HANDLE(0 + _n); \ + IRQ_HANDLE(1 + _n); \ + IRQ_HANDLE(2 + _n); \ + IRQ_HANDLE(3 + _n); \ + IRQ_HANDLE(4 + _n); \ + IRQ_HANDLE(5 + _n); \ + IRQ_HANDLE(6 + _n); \ + IRQ_HANDLE(7 + _n); \ + } + + static void irq_handle_msg(struct ddb *dev, u32 s) { dev->i2c_irq++; @@ -3213,11 +3543,11 @@ static irqreturn_t irq_handler0(int irq, void *dev_id) u32 s = ddbreadl(dev, INTERRUPT_STATUS); do { - if (s == 0xffffffff) + if (s & 0x80000000) return IRQ_NONE; if (!(s & 0xfff00)) return IRQ_NONE; - ddbwritel(dev, s, INTERRUPT_ACK); + ddbwritel(dev, s & 0xfff00, INTERRUPT_ACK); irq_handle_io(dev, s); } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); @@ -3234,7 +3564,7 @@ static irqreturn_t irq_handler1(int irq, void *dev_id) return IRQ_NONE; if (!(s & 0x0000f)) return IRQ_NONE; - ddbwritel(dev, s, INTERRUPT_ACK); + ddbwritel(dev, s & 0x0000f, INTERRUPT_ACK); irq_handle_msg(dev, s); } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); @@ -3267,6 +3597,86 @@ static irqreturn_t irq_handler(int irq, void *dev_id) return ret; } +static irqreturn_t irq_handle_v2_n(struct ddb *dev, u32 n) +{ + u32 reg = INTERRUPT_V2_STATUS + 4 * n; + u32 s = ddbreadl(dev, reg); + u32 off = n * 32; + + if (!s) + return IRQ_NONE; + ddbwritel(dev, s, reg); + + if ((s & 0x000000ff)) { + IRQ_HANDLE( 0 + off); + IRQ_HANDLE( 1 + off); + IRQ_HANDLE( 2 + off); + IRQ_HANDLE( 3 + off); + IRQ_HANDLE( 4 + off); + IRQ_HANDLE( 5 + off); + IRQ_HANDLE( 6 + off); + IRQ_HANDLE( 7 + off); + } + if ((s & 0x0000ff00)) { + IRQ_HANDLE( 8 + off); + IRQ_HANDLE( 9 + off); + IRQ_HANDLE(10 + off); + IRQ_HANDLE(11 + off); + IRQ_HANDLE(12 + off); + IRQ_HANDLE(13 + off); + IRQ_HANDLE(14 + off); + IRQ_HANDLE(15 + off); + } + if ((s & 0x00ff0000)) { + IRQ_HANDLE(16 + off); + IRQ_HANDLE(17 + off); + IRQ_HANDLE(18 + off); + IRQ_HANDLE(19 + off); + IRQ_HANDLE(20 + off); + IRQ_HANDLE(21 + off); + IRQ_HANDLE(22 + off); + IRQ_HANDLE(23 + off); + } + if ((s & 0xff000000)) { + IRQ_HANDLE(24 + off); + IRQ_HANDLE(25 + off); + IRQ_HANDLE(26 + off); + IRQ_HANDLE(27 + off); + IRQ_HANDLE(28 + off); + IRQ_HANDLE(29 + off); + IRQ_HANDLE(30 + off); + IRQ_HANDLE(31 + off); + } + return IRQ_HANDLED; +} + +static irqreturn_t irq_handler_v2(int irq, void *dev_id) +{ + struct ddb *dev = (struct ddb *) dev_id; + u32 s = 0xffff & ddbreadl(dev, INTERRUPT_V2_STATUS); + int ret = IRQ_HANDLED; + + if (!s) + return IRQ_NONE; + do { + if (s & 0x80) + return IRQ_NONE; + ddbwritel(dev, s, INTERRUPT_V2_STATUS); + if (s & 0x00000001) + irq_handle_v2_n(dev, 1); + if (s & 0x00000002) + irq_handle_v2_n(dev, 2); + if (s & 0x00000004) + irq_handle_v2_n(dev, 3); + IRQ_HANDLE(8); + IRQ_HANDLE(9); + IRQ_HANDLE(10); + IRQ_HANDLE(11); + } while ((s = 0xffff & ddbreadl(dev, INTERRUPT_V2_STATUS))); + + return ret; +} + #ifdef DDB_TEST_THREADED static irqreturn_t irq_thread(int irq, void *dev_id) { @@ -3903,7 +4313,7 @@ static ssize_t ports_show(struct device *device, { struct ddb *dev = dev_get_drvdata(device); - return sprintf(buf, "%d\n", dev->link[0].info->port_num); + return sprintf(buf, "%d\n", dev->port_num); } static ssize_t ts_irq_show(struct device *device, @@ -3954,10 +4364,23 @@ static ssize_t temp_show(struct device *device, { struct ddb *dev = dev_get_drvdata(device); struct i2c_adapter *adap; - int temp, temp2, temp3, i; + s32 temp, temp2, temp3; + int i; u8 tmp[2]; if (dev->link[0].info->type == DDB_MOD) { + if (dev->link[0].info->version == 2) { + temp = ddbreadl(dev, TEMPMON2_BOARD); + temp = (temp * 1000) >> 8; + + temp2 = ddbreadl(dev, TEMPMON2_FPGACORE); + temp2 = (temp2 * 1000) >> 8; + + temp3 = ddbreadl(dev, TEMPMON2_QAMCORE); + temp3 = (temp3 * 1000) >> 8; + + return sprintf(buf, "%d %d %d\n", temp, temp2, temp3); + } ddbwritel(dev, 1, TEMPMON_CONTROL); for (i = 0; i < 10; i++) { if (0 == (1 & ddbreadl(dev, TEMPMON_CONTROL))) @@ -4194,6 +4617,30 @@ static ssize_t redirect_store(struct device *device, return count; } +/* A L P I AAAAAALLPPPPPPII */ +/* AAAAAAAA LLLLLLLL PPPPPPII */ +static ssize_t redirect2_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + return 0; +} + +static ssize_t redirect2_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned int i, p; + int res; + + if (sscanf(buf, "%x %x\n", &i, &p) != 2) + return -EINVAL; + res = ddb_redirect(i, p); + if (res < 0) + return res; + pr_info("redirect: %02x, %02x\n", i, p); + return count; +} + static ssize_t gap_show(struct device *device, struct device_attribute *attr, char *buf) { @@ -4219,6 +4666,31 @@ static ssize_t gap_store(struct device *device, struct device_attribute *attr, return count; } +static ssize_t obr_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; + + return sprintf(buf, "%d\n", dev->port[num].obr); + +} + +static ssize_t obr_store(struct device *device, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; + unsigned int val; + + if (sscanf(buf, "%u\n", &val) != 1) + return -EINVAL; + if (val > 96000) + return -EINVAL; + dev->port[num].obr = val; + return count; +} + static ssize_t version_show(struct device *device, struct device_attribute *attr, char *buf) { @@ -4311,6 +4783,10 @@ static struct device_attribute ddb_attrs[] = { __ATTR(gap1, 0664, gap_show, gap_store), __ATTR(gap2, 0664, gap_show, gap_store), __ATTR(gap3, 0664, gap_show, gap_store), + __ATTR(obr0, 0664, obr_show, obr_store), + __ATTR(obr1, 0664, obr_show, obr_store), + __ATTR(obr2, 0664, obr_show, obr_store), + __ATTR(obr3, 0664, obr_show, obr_store), __ATTR(vlan, 0664, vlan_show, vlan_store), __ATTR(fmode0, 0664, fmode_show, fmode_store), __ATTR(fmode1, 0664, fmode_show, fmode_store), @@ -4414,7 +4890,7 @@ static void ddb_device_attrs_del(struct ddb *dev) device_remove_file(dev->ddb_dev, &ddb_attrs_snr[i]); device_remove_file(dev->ddb_dev, &ddb_attrs_ctemp[i]); } - for (i = 0; ddb_attrs[i].attr.name; i++) + for (i = 0; ddb_attrs[i].attr.name != NULL; i++) device_remove_file(dev->ddb_dev, &ddb_attrs[i]); } @@ -4422,19 +4898,19 @@ static int ddb_device_attrs_add(struct ddb *dev) { int i; - for (i = 0; ddb_attrs[i].attr.name; i++) + for (i = 0; ddb_attrs[i].attr.name != NULL; i++) if (device_create_file(dev->ddb_dev, &ddb_attrs[i])) goto fail; for (i = 0; i < dev->link[0].info->temp_num; i++) if (device_create_file(dev->ddb_dev, &ddb_attrs_temp[i])) goto fail; - for (i = 0; i < dev->link[0].info->port_num; i++) + for (i = 0; (i < dev->link[0].info->port_num) && (i < 10); i++) if (device_create_file(dev->ddb_dev, &ddb_attrs_mod[i])) goto fail; for (i = 0; i < dev->link[0].info->fan_num; i++) if (device_create_file(dev->ddb_dev, &ddb_attrs_fan[i])) goto fail; - for (i = 0; i < dev->i2c_num && i < 4; i++) { + for (i = 0; (i < dev->i2c_num) && (i < 4); i++) { if (device_create_file(dev->ddb_dev, &ddb_attrs_snr[i])) goto fail; if (device_create_file(dev->ddb_dev, &ddb_attrs_ctemp[i])) @@ -4487,9 +4963,9 @@ static void ddb_device_destroy(struct ddb *dev) device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); } -#define LINK_IRQ_HANDLE(_nr) \ - do { if ((s & (1UL << _nr)) && dev->handler[_nr + off]) \ - dev->handler[_nr + off](dev->handler_data[_nr + off]); } \ +#define LINK_IRQ_HANDLE(_l, _nr) \ + do { if ((s & (1UL << _nr)) && dev->handler[_l][_nr]) \ + dev->handler[_l][_nr](dev->handler_data[_l][_nr]); } \ while (0) static void gtl_link_handler(unsigned long priv) @@ -4505,18 +4981,19 @@ static void link_tasklet(unsigned long data) { struct ddb_link *link = (struct ddb_link *) data; struct ddb *dev = link->dev; - u32 s, off = 32 * link->nr, tag = DDB_LINK_TAG(link->nr); - + u32 s, tag = DDB_LINK_TAG(link->nr); + u32 l = link->nr; + s = ddbreadl(dev, tag | INTERRUPT_STATUS); pr_info("gtl_irq %08x = %08x\n", tag | INTERRUPT_STATUS, s); if (!s) return; ddbwritel(dev, s, tag | INTERRUPT_ACK); - LINK_IRQ_HANDLE(0); - LINK_IRQ_HANDLE(1); - LINK_IRQ_HANDLE(2); - LINK_IRQ_HANDLE(3); + LINK_IRQ_HANDLE(l, 0); + LINK_IRQ_HANDLE(l, 1); + LINK_IRQ_HANDLE(l, 2); + LINK_IRQ_HANDLE(l, 3); } static void gtl_irq_handler(unsigned long priv) @@ -4524,82 +5001,27 @@ static void gtl_irq_handler(unsigned long priv) struct ddb_link *link = (struct ddb_link *) priv; #if 1 struct ddb *dev = link->dev; - u32 s, off = 32 * link->nr, tag = DDB_LINK_TAG(link->nr); + u32 s, l = link->nr, tag = DDB_LINK_TAG(link->nr); while ((s = ddbreadl(dev, tag | INTERRUPT_STATUS))) { ddbwritel(dev, s, tag | INTERRUPT_ACK); - LINK_IRQ_HANDLE(0); - LINK_IRQ_HANDLE(1); - LINK_IRQ_HANDLE(2); - LINK_IRQ_HANDLE(3); + //pr_info("gtlirq %08x\n", s); + LINK_IRQ_HANDLE(l, 0); + LINK_IRQ_HANDLE(l, 1); + LINK_IRQ_HANDLE(l, 2); + LINK_IRQ_HANDLE(l, 3); } #else tasklet_schedule(&link->tasklet); #endif } -static struct ddb_regset octopus_max_gtl_i2c = { - .base = 0x80, - .num = 0x01, - .size = 0x20, -}; - -static struct ddb_regset octopus_max_gtl_i2c_buf = { - .base = 0x1000, - .num = 0x01, - .size = 0x200, -}; - -static struct ddb_regmap octopus_max_gtl_map = { - .i2c = &octopus_max_gtl_i2c, - .i2c_buf = &octopus_max_gtl_i2c_buf, -}; - -static struct ddb_info octopus_max_gtl = { - .type = DDB_OCTOPUS_MAX, - .name = "Digital Devices Octopus MAX GTL", - .regmap = &octopus_max_gtl_map, - .port_num = 4, - .i2c_mask = 0x01, - .board_control = 1, -}; - - -static struct ddb_regset octopus_maxct_gtl_i2c = { - .base = 0x80, - .num = 0x04, - .size = 0x20, -}; - -static struct ddb_regset octopus_maxct_gtl_i2c_buf = { - .base = 0x1000, - .num = 0x04, - .size = 0x200, -}; - -static struct ddb_regmap octopus_maxct_gtl_map = { - .i2c = &octopus_maxct_gtl_i2c, - .i2c_buf = &octopus_maxct_gtl_i2c_buf, -}; - -static struct ddb_info octopus_ct_gtl = { - .type = DDB_OCTOPUS_MAX_CT, - .name = "Digital Devices Octopus MAX CT GTL", - .regmap = &octopus_maxct_gtl_map, - .port_num = 4, - .i2c_mask = 0x0f, - .board_control = 0xff, - .board_control_2 = 0xf00, - .ts_quirks = TS_QUIRK_SERIAL, -}; - - static int ddb_gtl_init_link(struct ddb *dev, u32 l) { struct ddb_link *link = &dev->link[l]; u32 regs = dev->link[0].info->regmap->gtl->base + (l - 1) * dev->link[0].info->regmap->gtl->size; - u32 id; + u32 id, base = dev->link[0].info->regmap->irq_base_gtl; pr_info("Checking GT link %u: regs = %08x\n", l, regs); @@ -4608,6 +5030,10 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l) link->lnb.fmode = 0xffffffff; mutex_init(&link->flash_mutex); + link->nr = l; + link->dev = dev; + link->regs = regs; + if (!(1 & ddbreadl(dev, regs))) { u32 c; @@ -4622,17 +5048,13 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l) if (c == 5) return -1; } - link->nr = l; - link->dev = dev; - link->regs = regs; - id = ddbreadl(dev, DDB_LINK_TAG(l) | 8); switch (id) { case 0x0007dd01: - link->info = &octopus_max_gtl; + link->info = &ddb_s2_48; break; case 0x0008dd01: - link->info = &octopus_ct_gtl; + link->info = &ddb_ct_8; break; default: pr_info("DDBridge: Detected GT link but found invalid ID %08x. You might have to update (flash) the add-on card first.", @@ -4641,10 +5063,10 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l) } link->ids.devid = id; - ddbwritel(dev, 1, 0x1a0); + ddbwritel(dev, 1, regs + 0x20); - dev->handler_data[11] = (unsigned long) link; - dev->handler[11] = gtl_irq_handler; + dev->handler_data[0][base + l] = (unsigned long) link; + dev->handler[0][base + l] = gtl_irq_handler; pr_info("GTL %s\n", dev->link[l].info->name); pr_info("GTL HW %08x REGMAP %08x\n", @@ -4662,11 +5084,10 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l) static int ddb_gtl_init(struct ddb *dev) { - u32 l; - - dev->handler_data[10] = (unsigned long) dev; - dev->handler[10] = gtl_link_handler; + u32 l, base = dev->link[0].info->regmap->irq_base_gtl; + dev->handler_data[0][base] = (unsigned long) dev; + dev->handler[0][base] = gtl_link_handler; for (l = 1; l < dev->link[0].info->regmap->gtl->num + 1; l++) ddb_gtl_init_link(dev, l); return 0; @@ -4698,15 +5119,18 @@ static int ddb_init_boards(struct ddb *dev) static int ddb_init(struct ddb *dev) { + mutex_init(&dev->link[0].flash_mutex); + if (no_init) { + ddb_device_create(dev); + return 0; + } if (dev->link[0].info->ns_num) { ddbwritel(dev, 1, ETHER_CONTROL); dev->vlan = vlan; ddbwritel(dev, 14 + (dev->vlan ? 4 : 0), ETHER_LENGTH); } - mutex_init(&dev->link[0].lnb.lock); - mutex_init(&dev->link[0].flash_mutex); - + if (dev->link[0].info->regmap->gtl) ddb_gtl_init(dev); @@ -4749,3 +5173,24 @@ fail: pr_err("fail1\n"); return -1; } + +static void ddb_reset_io(struct ddb *dev, u32 reg) +{ + ddbwritel(dev, 0x00, reg); + ddbwritel(dev, 0x02, reg); + ddbwritel(dev, 0x00, reg); +} + +static void ddb_reset_ios(struct ddb *dev) +{ + u32 i; + struct ddb_regmap *rm = dev->link[0].info->regmap; + + if (rm->input) + for (i = 0; i < rm->input->num; i++) + ddb_reset_io(dev, rm->input->base + i * rm->input->size); + if (rm->output) + for (i = 0; i < rm->output->num; i++) + ddb_reset_io(dev, rm->output->base + i * rm->output->size); + usleep_range(5000, 6000); +} diff --git a/ddbridge/ddbridge-i2c.c b/ddbridge/ddbridge-i2c.c index e96f3e1..d3fd477 100644 --- a/ddbridge/ddbridge-i2c.c +++ b/ddbridge/ddbridge-i2c.c @@ -247,7 +247,9 @@ static int ddb_i2c_add(struct ddb *dev, struct ddb_i2c *i2c, adap->class = I2C_CLASS_TV_ANALOG; #endif #endif - strcpy(adap->name, "ddbridge"); + /*strcpy(adap->name, "ddbridge");*/ + snprintf(adap->name, I2C_NAME_SIZE, "ddbridge_%02x.%x.%x", + dev->nr, i2c->link, i); adap->algo = &ddb_i2c_algo; adap->algo_data = (void *)i2c; adap->dev.parent = dev->dev; @@ -257,7 +259,7 @@ static int ddb_i2c_add(struct ddb *dev, struct ddb_i2c *i2c, static int ddb_i2c_init(struct ddb *dev) { int stat = 0; - u32 i, j, num = 0, l; + u32 i, j, num = 0, l, base; struct ddb_i2c *i2c; struct i2c_adapter *adap; struct ddb_regmap *regmap; @@ -268,12 +270,13 @@ static int ddb_i2c_init(struct ddb *dev) regmap = dev->link[l].info->regmap; if (!regmap || !regmap->i2c) continue; + base = regmap->irq_base_i2c; for (i = 0; i < regmap->i2c->num; i++) { if (!(dev->link[l].info->i2c_mask & (1 << i))) continue; i2c = &dev->i2c[num]; - dev->handler_data[i + l * 32] = (unsigned long) i2c; - dev->handler[i + l * 32] = i2c_handler; + dev->handler_data[l][i + base] = (unsigned long) i2c; + dev->handler[l][i + base] = i2c_handler; stat = ddb_i2c_add(dev, i2c, regmap, l, i, num); if (stat) break; diff --git a/ddbridge/ddbridge-mod.c b/ddbridge/ddbridge-mod.c index 5503328..99b37c3 100644 --- a/ddbridge/ddbridge-mod.c +++ b/ddbridge/ddbridge-mod.c @@ -28,6 +28,10 @@ #include +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + inline s64 ConvertPCR(s64 a) { s32 ext; @@ -72,6 +76,81 @@ inline s64 RoundPCRDown(s64 a) return a & ~(HW_LSB_MASK - 1); } +// Calculating KF, LF from Symbolrate +// +// Symbolrate is usually calculated as (M/N) * 10.24 MS/s +// +// Common Values for M,N +// J.83 Annex A, +// Euro Docsis 6.952 MS/s : M = 869, N = 1280 +// 6.900 MS/s : M = 345, N = 512 +// 6.875 MS/s : M = 1375, N = 2048 +// 6.111 MS/s : M = 6111, N = 10240 +// J.83 Annex B ** +// QAM64 5.056941 : M = 401, N = 812 +// QAM256 5.360537 : M = 78, N = 149 +// J.83 Annex C ** +// 5.309734 : M = 1889, N = 3643 +// +// For the present hardware +// KF' = 256 * M +// LF' = 225 * N +// or +// KF' = Symbolrate in Hz +// LF' = 9000000 +// +// KF = KF' / gcd(KF',LF') +// LF = LF' / gcd(KF',LF') +// Note: LF must not be a power of 2. +// Maximum value for KF,LF = 13421727 ( 0x7FFFFFF ) +// ** using these M,N values will result in a small err (<5ppm) +// calculating KF,LF directly gives the exact normative result +// but with rather large KF,LF values + +static inline u32 gcd(u32 u,u32 v) +{ + int s = 0; + while (((u|v)&1) == 0) { + s += 1; + u >>= 1; + v >>= 1; + } + while ((u&1) == 0) + u >>= 1; + do { + while ( (v&1) == 0 ) v >>= 1; + if( u > v ) { + u32 t = v; + v = u; + u = t; + } + v = v - u; + } while(v != 0); + return u << s; +} + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static int mod_SendChannelCommand(struct ddb *dev, u32 Channel, u32 Command) +{ + u32 ControlReg = ddbreadl(dev, CHANNEL_CONTROL(Channel)); + + ControlReg = (ControlReg & ~CHANNEL_CONTROL_CMD_MASK)|Command; + ddbwritel(dev, ControlReg, CHANNEL_CONTROL(Channel)); + while(1) { + ControlReg = ddbreadl(dev, CHANNEL_CONTROL(Channel)); + if (ControlReg == 0xFFFFFFFF) + return -EIO; + if((ControlReg & CHANNEL_CONTROL_CMD_STATUS) == 0) + break; + } + if (ControlReg & CHANNEL_CONTROL_ERROR_CMD) + return -EINVAL; + return 0; +} + static int mod_busy(struct ddb *dev, int chan) { u32 creg; @@ -89,10 +168,12 @@ static int mod_busy(struct ddb *dev, int chan) void ddbridge_mod_output_stop(struct ddb_output *output) { struct ddb *dev = output->port->dev; - struct mod_state *mod = &dev->mod[output->nr]; + struct ddb_mod *mod = &dev->mod[output->nr]; mod->State = CM_IDLE; mod->Control = 0; + if (dev->link[0].info->version == 2) + mod_SendChannelCommand(dev, output->nr, CHANNEL_CONTROL_CMD_FREE); ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); #if 0 udelay(10); @@ -108,7 +189,7 @@ static void mod_set_incs(struct ddb_output *output) { s64 pcr; struct ddb *dev = output->port->dev; - struct mod_state *mod = &dev->mod[output->nr]; + struct ddb_mod *mod = &dev->mod[output->nr]; pcr = ConvertPCR(mod->PCRIncrement); ddbwritel(dev, pcr & 0xffffffff, @@ -137,8 +218,10 @@ static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 }; void ddbridge_mod_output_start(struct ddb_output *output) { struct ddb *dev = output->port->dev; - struct mod_state *mod = &dev->mod[output->nr]; - + u32 Channel = output->nr; + struct ddb_mod *mod = &dev->mod[output->nr]; + u32 Symbolrate = 6900000; + /*PCRIncrement = RoundPCR(PCRIncrement);*/ /*PCRDecrement = RoundPCR(PCRDecrement);*/ @@ -164,18 +247,55 @@ void ddbridge_mod_output_start(struct ddb_output *output) udelay(10); ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); - /* QAM: 600 601 602 903 604 = 16 32 64 128 256 */ - /* ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); */ - ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr)); + pr_info("CHANNEL_BASE = %08x\n", CHANNEL_BASE); + pr_info("CHANNEL_CONTROL = %08x\n", CHANNEL_CONTROL(Channel)); + if (dev->link[0].info->version == 2) { + u32 Output = ((dev->mod_base.frequency - 114000000)/8000000 + Channel) % 96; + u32 KF = Symbolrate; + u32 LF = 9000000UL; + u32 d = gcd(KF,LF); + u32 checkLF; + mod->modulation = QAM_256 - 1; + ddbwritel(dev, mod->modulation, CHANNEL_SETTINGS(Channel)); + ddbwritel(dev, Output, CHANNEL_SETTINGS2(Channel)); + + KF = KF / d; + LF = LF / d; + + while( (KF > KFLF_MAX) || (LF > KFLF_MAX) ) { + KF >>= 1; + LF >>= 1; + } + + checkLF = LF; + while ((checkLF & 1) == 0) + checkLF >>= 1; + if (checkLF <= 1) + return -EINVAL; + + pr_info("KF=%u LF=%u Output=%u mod=%u\n", KF, LF, Output, mod->modulation); + ddbwritel(dev, KF, CHANNEL_KF(Channel)); + ddbwritel(dev, LF, CHANNEL_LF(Channel)); + + if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_SETUP)) + return -EINVAL; + mod->Control = CHANNEL_CONTROL_ENABLE_DVB; + } else { + /* QAM: 600 601 602 903 604 = 16 32 64 128 256 */ + /* ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); */ + ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr)); + mod->Control = (CHANNEL_CONTROL_ENABLE_IQ | CHANNEL_CONTROL_ENABLE_DVB); + } mod_set_rateinc(dev, output->nr); mod_set_incs(output); - mod->Control = (CHANNEL_CONTROL_ENABLE_IQ | - CHANNEL_CONTROL_ENABLE_DVB | - CHANNEL_CONTROL_ENABLE_SOURCE); + mod->Control |= CHANNEL_CONTROL_ENABLE_SOURCE; ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr)); + if (dev->link[0].info->version == 2) + if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_UNMUTE)) + return -EINVAL; pr_info("mod_output_start %d.%d\n", dev->nr, output->nr); } @@ -183,6 +303,195 @@ void ddbridge_mod_output_start(struct ddb_output *output) /****************************************************************************/ /****************************************************************************/ +static int mod_write_max2871(struct ddb *dev, u32 val) +{ + ddbwritel(dev, val, MAX2871_OUTDATA); + ddbwritel(dev, MAX2871_CONTROL_CE | MAX2871_CONTROL_WRITE, MAX2871_CONTROL); + while(1) { + u32 ControlReg = ddbreadl(dev, MAX2871_CONTROL); + if (ControlReg == 0xFFFFFFFF) + return -EIO; + if ((ControlReg & MAX2871_CONTROL_WRITE) == 0) + break; + } + return 0; +} + +static int mod_setup_max2871(struct ddb *dev) +{ + int status = 0; + int i; + + ddbwritel(dev, MAX2871_CONTROL_CE, MAX2871_CONTROL); + for (i = 0; i < 2; i++) { + status = mod_write_max2871(dev, 0x00440005); + if (status) + break; + status = mod_write_max2871(dev, 0x6199003C); + if (status) + break; + status = mod_write_max2871(dev, 0x000000CB); + if (status) + break; + status = mod_write_max2871(dev, 0x510061C2); + if (status) + break; + status = mod_write_max2871(dev, 0x600080A1); + if (status) + break; + status = mod_write_max2871(dev, 0x00730040); + if (status) + break; + msleep(30); + } while(0); + + if (status == 0) { + u32 ControlReg = ddbreadl(dev, MAX2871_CONTROL); + + if ((ControlReg & MAX2871_CONTROL_LOCK) == 0) + status = -EIO; + } + + return status; +} + + +static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels) +{ + int status = 0; + u32 Capacity; + u32 tmp = ddbreadl(dev, FSM_STATUS); + + if ((tmp & FSM_STATUS_READY) == 0) { + status = mod_setup_max2871(dev); + if (status) + return status; + ddbwritel(dev, FSM_CMD_RESET, FSM_CONTROL); + msleep(10); + + tmp = ddbreadl(dev, FSM_STATUS); + if ((tmp & FSM_STATUS_READY) == 0) + return -1; + } + Capacity = ddbreadl(dev, FSM_CAPACITY); + if (((tmp & FSM_STATUS_QAMREADY) != 0) && + ((Capacity & FSM_CAPACITY_INUSE) != 0)) + return -EBUSY; + + ddbwritel(dev, FSM_CMD_SETUP, FSM_CONTROL); + msleep(10); + tmp = ddbreadl(dev, FSM_STATUS); + + if ((tmp & FSM_STATUS_QAMREADY) == 0) + return -1; + + if (MaxUsedChannels == 0) + MaxUsedChannels = (Capacity & FSM_CAPACITY_CUR) >> 16; + + pr_info("max used chan = %u\n", MaxUsedChannels); + if (MaxUsedChannels <= 1 ) + ddbwritel(dev, FSM_GAIN_N1, FSM_GAIN); + else if (MaxUsedChannels <= 2) + ddbwritel(dev, FSM_GAIN_N2, FSM_GAIN); + else if (MaxUsedChannels <= 4) + ddbwritel(dev, FSM_GAIN_N4, FSM_GAIN); + else if (MaxUsedChannels <= 8) + ddbwritel(dev, FSM_GAIN_N8, FSM_GAIN); + else if (MaxUsedChannels <= 16) + ddbwritel(dev, FSM_GAIN_N16, FSM_GAIN); + else if (MaxUsedChannels <= 24) + ddbwritel(dev, FSM_GAIN_N24, FSM_GAIN); + else + ddbwritel(dev, FSM_GAIN_N96, FSM_GAIN); + + ddbwritel(dev, FSM_CONTROL_ENABLE, FSM_CONTROL); + + return status; +} + +static int mod_set_vga(struct ddb *dev, u32 Gain) +{ + if( Gain > 255 ) + return -EINVAL; + ddbwritel(dev, Gain, RF_VGA); + return 0; +} + +static int mod_get_vga(struct ddb *dev, u32 *pGain) +{ + *pGain = ddbreadl(dev, RF_VGA); + return 0; +} + +static void mod_TemperatureMonitorSetFan(struct ddb *dev) +{ + u32 tqam, pwm; + + if ((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) { + pr_info("Over temperature condition\n"); + dev->mod_base.OverTemperatureError = 1; + } + tqam = (ddbreadl(dev, TEMPMON2_QAMCORE) >> 8) & 0xFF; + if (tqam & 0x80) + tqam = 0; + + pwm = (ddbreadl(dev, TEMPMON_FANCONTROL) >> 8) & 0x0F; + if (pwm > 10) + pwm = 10; + + if (tqam >= dev->mod_base.temp_tab[pwm]) { + while( pwm < 10 && tqam >= dev->mod_base.temp_tab[pwm + 1]) + pwm += 1; + } else { + while( pwm > 1 && tqam < dev->mod_base.temp_tab[pwm - 2]) + pwm -= 1; + } + ddbwritel(dev, (pwm << 8), TEMPMON_FANCONTROL); +} + + +static void mod_temp_handler(unsigned long data) +{ + struct ddb *dev = (struct ddb *) data; + + pr_info("mod_temp_handler\n"); + + spin_lock(&dev->mod_base.temp_lock); + mod_TemperatureMonitorSetFan(dev); + spin_unlock(&dev->mod_base.temp_lock); +} + +static int mod_TemperatureMonitorInit(struct ddb *dev, int FirstTime) { + int status = 0; + + spin_lock_irq(&dev->mod_base.temp_lock); + if (FirstTime) { + static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80}; + + memcpy(dev->mod_base.temp_tab, TemperatureTable, sizeof(TemperatureTable)); + } + dev->handler[0][8] = mod_temp_handler; + dev->handler_data[0][8] = (unsigned long) dev; + ddbwritel(dev, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN | + TEMPMON_CONTROL_INTENABLE), + TEMPMON_CONTROL); + ddbwritel(dev, (3 << 8), TEMPMON_FANCONTROL); + + dev->mod_base.OverTemperatureError = + ((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0); + if (dev->mod_base.OverTemperatureError) { + pr_info("Over temperature condition\n"); + status = -1; + } + mod_TemperatureMonitorSetFan(dev); + spin_unlock_irq(&dev->mod_base.temp_lock); + return status; +} + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + static void mod_write_dac_register(struct ddb *dev, u8 Index, u8 Value) { u32 RegValue = 0; @@ -804,7 +1113,7 @@ static int set_base_frequency(struct ddb *dev, u32 freq) return mod_set_down(dev, down, 8, Ext); } -static int mod_init(struct ddb *dev, u32 Frequency) +static int mod_init_1(struct ddb *dev, u32 Frequency) { int stat = 0; u8 *buffer; @@ -906,7 +1215,7 @@ void ddbridge_mod_rate_handler(unsigned long data) struct ddb_output *output = (struct ddb_output *) data; struct ddb_dma *dma = output->dma; struct ddb *dev = output->port->dev; - struct mod_state *mod = &dev->mod[output->nr]; + struct ddb_mod *mod = &dev->mod[output->nr]; u32 chan = output->nr; u32 OutPacketCount; @@ -1081,7 +1390,7 @@ void ddbridge_mod_rate_handler(unsigned long data) PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement); } -int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg) +static int mod_ioctl_1(struct file *file, unsigned int cmd, void *parg) { struct dvb_device *dvbdev = file->private_data; struct ddb_output *output = dvbdev->priv; @@ -1146,7 +1455,114 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg) return ret; } + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static int mod_ioctl_2(struct file *file, unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb *dev = output->port->dev; + + /* unsigned long arg = (unsigned long) parg; */ + int ret = 0; + + switch (cmd) { + case DVB_MOD_SET: + { + struct dvb_mod_params *mp = parg; + + pr_info("set base freq\n"); + dev->mod_base.frequency = mp->base_frequency; + pr_info("set attenuator\n"); + mod_set_attenuator(dev, mp->attenuator); + break; + } + case DVB_MOD_CHANNEL_SET: + { + struct dvb_mod_channel_params *cp = parg; + int res; + u32 ri; + + pr_info("set modulation\n"); + res = mod_set_modulation(dev, output->nr, cp->modulation); + if (res) + return res; + + if (cp->input_bitrate > dev->mod[output->nr].obitrate) + return -EINVAL; + dev->mod[output->nr].ibitrate = cp->input_bitrate; + dev->mod[output->nr].pcr_correction = cp->pcr_correction; + + pr_info("ibitrate %llu\n", dev->mod[output->nr].ibitrate); + pr_info("obitrate %llu\n", dev->mod[output->nr].obitrate); + if (cp->input_bitrate != 0) { + u64 d = dev->mod[output->nr].obitrate - + dev->mod[output->nr].ibitrate; + + d = div64_u64(d, dev->mod[output->nr].obitrate >> 24); + if (d > 0xfffffe) + ri = 0xfffffe; + else + ri = d; + } else + ri = 0; + dev->mod[output->nr].rate_inc = ri; + pr_info("ibr=%llu, obr=%llu, ri=0x%06x\n", + dev->mod[output->nr].ibitrate >> 32, + dev->mod[output->nr].obitrate >> 32, + ri); + break; + } + default: + ret = -EINVAL; + break; + } + return ret; +} + + +static int mod_init_2(struct ddb *dev, u32 Frequency) +{ + int status; + int streams = dev->link[0].info->port_num; + + dev->mod_base.frequency = Frequency; + mod_TemperatureMonitorInit(dev, 1); + status = mod_fsm_setup(dev, 0, 0); + + if (streams <= 8) + mod_set_vga(dev, RF_VGA_GAIN_N8); + else if (streams <= 16) + mod_set_vga(dev, RF_VGA_GAIN_N16); + else + mod_set_vga(dev, RF_VGA_GAIN_N24); + + mod_set_attenuator(dev, 0); + return 0; +} + +int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb *dev = output->port->dev; + + if (dev->link[0].info->version <= 0) + return mod_ioctl_1(file, cmd, parg); + if (dev->link[0].info->version == 2) + return mod_ioctl_2(file, cmd, parg); + return -1; +} + int ddbridge_mod_init(struct ddb *dev) { - return mod_init(dev, 722000000); + spin_lock_init(&dev->mod_base.temp_lock); + if (dev->link[0].info->version <= 1) + return mod_init_1(dev, 722000000); + if (dev->link[0].info->version == 2) + return mod_init_2(dev, 114000000); + return -1; } diff --git a/ddbridge/ddbridge-ns.c b/ddbridge/ddbridge-ns.c index cd6b348..38522ae 100644 --- a/ddbridge/ddbridge-ns.c +++ b/ddbridge/ddbridge-ns.c @@ -201,10 +201,10 @@ static int ns_set_ci(struct dvbnss *nss, u8 ci) pr_info("input %d.%d to ci %d at port %d\n", input->port->lnr, input->nr, ci, ciport); ddbwritel(dev, (input->port->lnr << 21) | (input->nr << 16) | 0x1c, - TS_OUTPUT_CONTROL(ciport)); + TS_CONTROL(dev->port[ciport].output)); usleep_range(1, 5); ddbwritel(dev, (input->port->lnr << 21) | (input->nr << 16) | 0x1d, - TS_OUTPUT_CONTROL(ciport)); + TS_CONTROL(dev->port[ciport].output)); dns->fe = dev->port[ciport].input[0]; return 0; } diff --git a/ddbridge/ddbridge-regs.h b/ddbridge/ddbridge-regs.h index 9e03350..b887381 100644 --- a/ddbridge/ddbridge-regs.h +++ b/ddbridge/ddbridge-regs.h @@ -1,7 +1,7 @@ /* * ddbridge-regs.h: Digital Devices PCIe bridge driver * - * Copyright (C) 2010-2015 Digital Devices GmbH + * Copyright (C) 2010-2016 Digital Devices GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -23,12 +23,11 @@ /* Register Definitions */ -#define CUR_REGISTERMAP_VERSION 0x10003 -#define CUR_REGISTERMAP_VERSION_CI 0x10000 -#define CUR_REGISTERMAP_VERSION_MOD 0x10000 +#define CUR_REGISTERMAP_VERSION_V1 0x00010001 +#define CUR_REGISTERMAP_VERSION_V2 0x00020000 -#define HARDWARE_VERSION 0x00 -#define REGISTERMAP_VERSION 0x04 +#define HARDWARE_VERSION 0x00000000 +#define REGISTERMAP_VERSION 0x00000004 /* ------------------------------------------------------------------------- */ /* SPI Controller */ @@ -76,6 +75,8 @@ #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20) #define INTERRUPT_ACK (INTERRUPT_BASE + 0x20) +#define INTERRUPT_ACK1 (INTERRUPT_BASE + 0x24) +#define INTERRUPT_ACK2 (INTERRUPT_BASE + 0x28) #define INTMASK_CLOCKGEN (0x00000001) #define INTMASK_TEMPMON (0x00000002) @@ -105,6 +106,26 @@ #define INTMASK_TSOUTPUT4 (0x00080000) +#define INTERRUPT_V2_CONTROL (INTERRUPT_BASE + 0x00) +#define INTERRUPT_V2_ENABLE_1 (INTERRUPT_BASE + 0x04) +#define INTERRUPT_V2_ENABLE_2 (INTERRUPT_BASE + 0x08) +#define INTERRUPT_V2_ENABLE_3 (INTERRUPT_BASE + 0x0c) +#define INTERRUPT_V2_ENABLE_4 (INTERRUPT_BASE + 0x10) +#define INTERRUPT_V2_ENABLE_5 (INTERRUPT_BASE + 0x14) +#define INTERRUPT_V2_ENABLE_6 (INTERRUPT_BASE + 0x18) +#define INTERRUPT_V2_ENABLE_7 (INTERRUPT_BASE + 0x1c) + +#define INTERRUPT_V2_STATUS (INTERRUPT_BASE + 0x20) +#define INTERRUPT_V2_STATUS_1 (INTERRUPT_BASE + 0x24) +#define INTERRUPT_V2_STATUS_2 (INTERRUPT_BASE + 0x28) +#define INTERRUPT_V2_STATUS_3 (INTERRUPT_BASE + 0x2c) +#define INTERRUPT_V2_STATUS_4 (INTERRUPT_BASE + 0x30) +#define INTERRUPT_V2_STATUS_5 (INTERRUPT_BASE + 0x34) +#define INTERRUPT_V2_STATUS_6 (INTERRUPT_BASE + 0x38) +#define INTERRUPT_V2_STATUS_7 (INTERRUPT_BASE + 0x3c) + + + /* Modulator registers */ @@ -128,23 +149,46 @@ /* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */ #define TEMPMON_BASE (0xA0) #define TEMPMON_CONTROL (TEMPMON_BASE + 0x00) + +#define TEMPMON_CONTROL_SCAN (0x00000001) +#define TEMPMON_CONTROL_AUTOSCAN (0x00000002) +#define TEMPMON_CONTROL_INTENABLE (0x00000004) +#define TEMPMON_CONTROL_OVERTEMP (0x00008000) + + /* SHORT Temperature in °C x 256 */ #define TEMPMON_CORE (TEMPMON_BASE + 0x04) +#define TEMPMON_SENSOR0 (TEMPMON_BASE + 0x04) #define TEMPMON_SENSOR1 (TEMPMON_BASE + 0x08) #define TEMPMON_SENSOR2 (TEMPMON_BASE + 0x0C) +#define TEMPMON_FANCONTROL (TEMPMON_BASE + 0x10) +#define TEMPMON_FANPWM (0x00000F00) // PWM speed in 10% steps +#define TEMPMON_FANTACHO (0x000000FF) // Rotations in 100/min steps + +// V1 Temperature Monitor +// Temperature Monitor TEMPMON_CONTROL & 0x8000 == 0 : ( 2x LM75A @ 0x90,0x92 ) +// Temperature Monitor TEMPMON_CONTROL & 0x8000 == 1 : ( 1x LM75A @ 0x90, 1x ADM1032 @ 0x9A ) + +#define TEMPMON1_CORE (TEMPMON_SENSOR0) // SHORT Temperature in °C x 256 (ADM1032 ext) +#define TEMPMON1_SENSOR1 (TEMPMON_BASE + 0x08) // SHORT Temperature in °C x 256 (LM75A 0x90) +#define TEMPMON1_SENSOR2 (TEMPMON_BASE + 0x0C) // SHORT Temperature in °C x 256 (LM75A 0x92 or ADM1032 Int) + +// V2 Temperature Monitor 2 ADM1032 + +#define TEMPMON2_BOARD (TEMPMON_SENSOR0) // SHORT Temperature in °C x 256 (ADM1032 int) +#define TEMPMON2_FPGACORE (TEMPMON_SENSOR1) // SHORT Temperature in °C x 256 (ADM1032 ext) +#define TEMPMON2_QAMCORE (TEMPMON_SENSOR2) // SHORT Temperature in °C x 256 (ADM1032 ext) + /* ------------------------------------------------------------------------- */ /* I2C Master Controller */ -#define I2C_BASE (0x80) /* Byte offset */ - #define I2C_COMMAND (0x00) #define I2C_TIMING (0x04) #define I2C_TASKLENGTH (0x08) /* High read, low write */ #define I2C_TASKADDRESS (0x0C) /* High read, low write */ #define I2C_MONITOR (0x1C) - #define I2C_SPEED_666 (0x02010202) #define I2C_SPEED_400 (0x04030404) #define I2C_SPEED_200 (0x09080909) @@ -173,26 +217,17 @@ #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) #define DMA_DIAG_WAITCOUNTER (0x3C) -#define TS_INPUT_BASE (0x200) -#define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 0x10 + 0x00) -#define TS_INPUT_CONTROL2(i) (TS_INPUT_BASE + (i) * 0x10 + 0x04) +#define TS_CONTROL(_io) (_io->regs + 0x00) +#define TS_CONTROL2(_io) (_io->regs + 0x04) -#define TS_OUTPUT_BASE (0x280) -#define TS_OUTPUT_CONTROL(i) (TS_OUTPUT_BASE + (i) * 0x10 + 0x00) -#define TS_OUTPUT_CONTROL2(i) (TS_OUTPUT_BASE + (i) * 0x10 + 0x04) /* ------------------------------------------------------------------------- */ /* DMA Buffer */ -#define DMA_BUFFER_BASE (0x300) - -#define DMA_BUFFER_CONTROL(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x00) -#define DMA_BUFFER_ACK(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x04) -#define DMA_BUFFER_CURRENT(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x08) -#define DMA_BUFFER_SIZE(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x0c) - -#define DMA_BASE_ADDRESS_TABLE (0x2000) -#define DMA_BASE_ADDRESS_TABLE_ENTRIES (512) +#define DMA_BUFFER_CONTROL(_dma) (_dma->regs + 0x00) +#define DMA_BUFFER_ACK(_dma) (_dma->regs + 0x04) +#define DMA_BUFFER_CURRENT(_dma) (_dma->regs + 0x08) +#define DMA_BUFFER_SIZE(_dma) (_dma->regs + 0x0c) /* ------------------------------------------------------------------------- */ @@ -263,6 +298,8 @@ #define CI_BLOCKIO_SEND_BUFFER(i) \ (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE + CI_BLOCKIO_BUFFER_SIZE) +// V1 + #define VCO1_BASE (0xC0) #define VCO1_CONTROL (VCO1_BASE + 0x00) #define VCO1_DATA (VCO1_BASE + 0x04) /* 24 Bit */ @@ -293,6 +330,53 @@ /* Muxout from VCO (usually = Lock) */ #define VCO3_CONTROL_MUXOUT (0x00000004) +// V2 + +#define MAX2871_BASE (0xC0) +#define MAX2871_CONTROL (MAX2871_BASE + 0x00) +#define MAX2871_OUTDATA (MAX2871_BASE + 0x04) // 32 Bit +#define MAX2871_INDATA (MAX2871_BASE + 0x08) // 32 Bit +#define MAX2871_CONTROL_WRITE (0x00000001) // 1 = Trigger write, resets when done +#define MAX2871_CONTROL_CE (0x00000002) // 0 = Put VCO into power down +#define MAX2871_CONTROL_MUXOUT (0x00000004) // Muxout from VCO +#define MAX2871_CONTROL_LOCK (0x00000008) // Lock from VCO + +#define FSM_BASE (0x200) +#define FSM_CONTROL (FSM_BASE + 0x00) + +#define FSM_CONTROL_ENABLE (0x00000100) + +#define FSM_CMD_MASK (0x00000087) +#define FSM_CMD_STATUS (0x00000080) +#define FSM_CMD_RESET (0x00000080) +#define FSM_CMD_POWERDOWN (0x00000081) +#define FSM_CMD_SETUP (0x00000082) + +#define FSM_STATUS (FSM_BASE + 0x00) +#define FSM_STATUS_READY (0x00010000) +#define FSM_STATUS_QAMREADY (0x00020000) + + +#define FSM_CAPACITY (FSM_BASE + 0x04) +#define FSM_CAPACITY_MAX (0x3F000000) +#define FSM_CAPACITY_CUR (0x003F0000) +#define FSM_CAPACITY_INUSE (0x0000003F) + +#define FSM_GAIN (FSM_BASE + 0x10) +#define FSM_GAINMASK (0x000000FF) + +#define FSM_GAIN_N1 (0x000000FE) +#define FSM_GAIN_N2 (0x000000A1) +#define FSM_GAIN_N4 (0x00000066) +#define FSM_GAIN_N8 (0x00000048) +#define FSM_GAIN_N16 (0x0000002D) +#define FSM_GAIN_N24 (0x00000029) +#define FSM_GAIN_N96 (0x00000011) + + +// Attenuator/VGA + +#define RF_ATTENUATOR (0xD8) #define RF_ATTENUATOR (0xD8) /* 0x00 = 0 dB 0x01 = 1 dB @@ -300,6 +384,20 @@ 0x1F = 31 dB */ +#define RF_VGA (0xDC) +/* Only V2 */ +/* 8 bit range 0 - 31.75 dB Gain */ + +/* VGA Gain for same output level as V1 Modulator */ +#define RF_VGA_GAIN_N8 (85) +#define RF_VGA_GAIN_N16 (117) +#define RF_VGA_GAIN_N24 (122) + +#define RF_VGA_GAIN_MAX (200) + + +/* V1 only */ + #define RF_POWER (0xE0) #define RF_POWER_BASE (0xE0) #define RF_POWER_CONTROL (RF_POWER_BASE + 0x00) @@ -343,7 +441,7 @@ #define IQOUTPUT_CONTROL_BYPASS_EQUALIZER (0x00000010) -/* Modulator Base */ +/* Modulator Base V1 */ #define MODULATOR_BASE (0x200) #define MODULATOR_CONTROL (MODULATOR_BASE) @@ -361,9 +459,11 @@ /* Modulator Channels */ -#define CHANNEL_BASE (0x400) +#define CHANNEL_BASE dev->link[0].info->regmap->channel->base + #define CHANNEL_CONTROL(i) (CHANNEL_BASE + (i) * 64 + 0x00) #define CHANNEL_SETTINGS(i) (CHANNEL_BASE + (i) * 64 + 0x04) +#define CHANNEL_SETTINGS2(i) (CHANNEL_BASE + (i) * 64 + 0x08) #define CHANNEL_RATE_INCR(i) (CHANNEL_BASE + (i) * 64 + 0x0C) #define CHANNEL_PCR_ADJUST_OUTL(i) (CHANNEL_BASE + (i) * 64 + 0x10) #define CHANNEL_PCR_ADJUST_OUTH(i) (CHANNEL_BASE + (i) * 64 + 0x14) @@ -373,6 +473,8 @@ #define CHANNEL_PCR_ADJUST_ACCUH(i) (CHANNEL_BASE + (i) * 64 + 0x24) #define CHANNEL_PKT_COUNT_OUT(i) (CHANNEL_BASE + (i) * 64 + 0x28) #define CHANNEL_PKT_COUNT_IN(i) (CHANNEL_BASE + (i) * 64 + 0x2C) +#define CHANNEL_KF(i) (CHANNEL_BASE + (i) * 64 + 0x30) +#define CHANNEL_LF(i) (CHANNEL_BASE + (i) * 64 + 0x34) #define CHANNEL_CONTROL_RESET (0x00000001) #define CHANNEL_CONTROL_ENABLE_DVB (0x00000002) @@ -381,8 +483,17 @@ #define CHANNEL_CONTROL_ENABLE_PCRADJUST (0x00000010) #define CHANNEL_CONTROL_FREEZE_STATUS (0x00000100) +#define CHANNEL_CONTROL_CMD_MASK (0x0000F000) +#define CHANNEL_CONTROL_CMD_STATUS (0x00008000) +#define CHANNEL_CONTROL_CMD_FREE (0x00008000) +#define CHANNEL_CONTROL_CMD_SETUP (0x00009000) +#define CHANNEL_CONTROL_CMD_MUTE (0x0000A000) +#define CHANNEL_CONTROL_CMD_UNMUTE (0x0000B000) + #define CHANNEL_CONTROL_RESET_ERROR (0x00010000) -#define CHANNEL_CONTROL_BUSY (0x01000000) +#define CHANNEL_CONTROL_ACTIVE (0x00400000) +#define CHANNEL_CONTROL_BUSY (0x00800000) +#define CHANNEL_CONTROL_ERROR_CMD (0x10000000) #define CHANNEL_CONTROL_ERROR_SYNC (0x20000000) #define CHANNEL_CONTROL_ERROR_UNDERRUN (0x40000000) #define CHANNEL_CONTROL_ERROR_FATAL (0x80000000) @@ -394,6 +505,14 @@ #define CHANNEL_SETTINGS_QAM128 (0x00000003) #define CHANNEL_SETTINGS_QAM256 (0x00000004) +#define CHANNEL_SETTINGS2_OUTPUT_MASK (0x0000007F) + +#define KFLF_MAX (0x07FFFFFFUL) +#define KF_INIT(Symbolrate) (Symbolrate) +#define LF_INIT(Symbolrate) (9000000UL) +#define MIN_SYMBOLRATE (1000000) +#define MAX_SYMBOLRATE (7100000) + /* OCTONET */ diff --git a/ddbridge/ddbridge.c b/ddbridge/ddbridge.c index c356e71..ce7699f 100644 --- a/ddbridge/ddbridge.c +++ b/ddbridge/ddbridge.c @@ -24,7 +24,6 @@ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html */ -/*#define DDB_ALT_DMA*/ #define DDB_USE_WORK /*#define DDB_TEST_THREADED*/ @@ -58,6 +57,34 @@ static void ddb_unmap(struct ddb *dev) vfree(dev); } +static void __devexit ddb_irq_disable(struct ddb *dev) +{ + if (dev->link[0].info->regmap->irq_version == 2) { + ddbwritel(dev, 0x00000000, INTERRUPT_V2_CONTROL); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_1); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_2); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_3); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_4); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_5); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_6); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_7); + } else { + ddbwritel(dev, 0, INTERRUPT_ENABLE); + ddbwritel(dev, 0, MSI1_ENABLE); + } +} + +static void __devexit ddb_irq_exit(struct ddb *dev) +{ + ddb_irq_disable(dev); + if (dev->msi == 2) + free_irq(dev->pdev->irq + 1, dev); + free_irq(dev->pdev->irq, dev); +#ifdef CONFIG_PCI_MSI + if (dev->msi) + pci_disable_msi(dev->pdev); +#endif +} static void __devexit ddb_remove(struct pci_dev *pdev) { @@ -70,16 +97,7 @@ static void __devexit ddb_remove(struct pci_dev *pdev) if (dev->link[0].info->ns_num) ddbwritel(dev, 0, ETHER_CONTROL); - ddbwritel(dev, 0, INTERRUPT_ENABLE); - - ddbwritel(dev, 0, MSI1_ENABLE); - if (dev->msi == 2) - free_irq(dev->pdev->irq + 1, dev); - free_irq(dev->pdev->irq, dev); -#ifdef CONFIG_PCI_MSI - if (dev->msi) - pci_disable_msi(dev->pdev); -#endif + ddb_irq_exit(dev); ddb_ports_release(dev); ddb_buffers_free(dev); @@ -93,16 +111,146 @@ static void __devexit ddb_remove(struct pci_dev *pdev) #define __devinitdata #endif +static int __devinit ddb_irq_msi(struct ddb *dev, int nr) +{ + int stat; + +#ifdef CONFIG_PCI_MSI + if (msi && pci_msi_enabled()) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) + stat = pci_enable_msi_range(dev->pdev, 1, nr); + if (stat >= 1) { + dev->msi = stat; + pr_info("DDBridge: using %d MSI interrupt(s)\n", + dev->msi); + } else + pr_info("DDBridge: MSI not available.\n"); + +#else + stat = pci_enable_msi_block(dev->pdev, nr); + if (stat == 0) { + dev->msi = nr; + pr_info("DDBridge: using %d MSI interrupts\n", nr); + } else if (stat == 1) { + stat = pci_enable_msi(dev->pdev); + dev->msi = 1; + } + if (stat < 0) + pr_info("DDBridge: MSI not available.\n"); +#endif + } + return stat; +} + +static int __devinit ddb_irq_init2(struct ddb *dev) +{ + int stat; + int irq_flag = IRQF_SHARED; + + pr_info("init type 2 IRQ hardware block\n"); + + ddbwritel(dev, 0x00000000, INTERRUPT_V2_CONTROL); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_1); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_2); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_3); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_4); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_5); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_6); + ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_7); + + ddb_irq_msi(dev, 1); + if (dev->msi) + irq_flag = 0; + + stat = request_irq(dev->pdev->irq, irq_handler_v2, + irq_flag, "ddbridge", (void *) dev); + if (stat < 0) + return stat; + + ddbwritel(dev, 0x0000ff7f, INTERRUPT_V2_CONTROL); + ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_1); + ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_2); + ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_3); + ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_4); + ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_5); + ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_6); + ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_7); + return stat; +} + +static int __devinit ddb_irq_init(struct ddb *dev) +{ + int stat; + int irq_flag = IRQF_SHARED; + + if (dev->link[0].info->regmap->irq_version == 2) + return ddb_irq_init2(dev); + + ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE); + ddbwritel(dev, 0x00000000, MSI1_ENABLE); + ddbwritel(dev, 0x00000000, MSI2_ENABLE); + ddbwritel(dev, 0x00000000, MSI3_ENABLE); + ddbwritel(dev, 0x00000000, MSI4_ENABLE); + ddbwritel(dev, 0x00000000, MSI5_ENABLE); + ddbwritel(dev, 0x00000000, MSI6_ENABLE); + ddbwritel(dev, 0x00000000, MSI7_ENABLE); + + ddb_irq_msi(dev, 2); + + if (dev->msi) + irq_flag = 0; + if (dev->msi == 2) { + stat = request_irq(dev->pdev->irq, irq_handler0, + irq_flag, "ddbridge", (void *) dev); + if (stat < 0) + return stat; + stat = request_irq(dev->pdev->irq + 1, irq_handler1, + irq_flag, "ddbridge", (void *) dev); + if (stat < 0) { + free_irq(dev->pdev->irq, dev); + return stat; + } + } else +#endif + { +#ifdef DDB_TEST_THREADED + stat = request_threaded_irq(dev->pdev->irq, irq_handler, + irq_thread, + irq_flag, + "ddbridge", (void *) dev); +#else + stat = request_irq(dev->pdev->irq, irq_handler, + irq_flag, "ddbridge", (void *) dev); +#endif + if (stat < 0) + return stat; + } + /*ddbwritel(dev, 0xffffffff, INTERRUPT_ACK);*/ + if (dev->msi == 2) { + ddbwritel(dev, 0x0fffff00, INTERRUPT_ENABLE); + ddbwritel(dev, 0x0000000f, MSI1_ENABLE); + } else { + ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE); + ddbwritel(dev, 0x00000000, MSI1_ENABLE); + } + return stat; +} + static int __devinit ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct ddb *dev; int stat = 0; - int irq_flag = IRQF_SHARED; if (pci_enable_device(pdev) < 0) return -ENODEV; + pci_set_master(pdev); + + if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) + if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) + return -ENODEV; + dev = vzalloc(sizeof(struct ddb)); if (dev == NULL) return -ENOMEM; @@ -144,75 +292,8 @@ static int __devinit ddb_probe(struct pci_dev *pdev, dev->link[0].ids.hwid, dev->link[0].ids.regmapid); if (dev->link[0].info->ns_num) { - int i; - ddbwritel(dev, 0, ETHER_CONTROL); - for (i = 0; i < 16; i++) - ddbwritel(dev, 0x00, TS_OUTPUT_CONTROL(i)); - usleep_range(5000, 6000); - } - ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE); - ddbwritel(dev, 0x00000000, MSI1_ENABLE); - ddbwritel(dev, 0x00000000, MSI2_ENABLE); - ddbwritel(dev, 0x00000000, MSI3_ENABLE); - ddbwritel(dev, 0x00000000, MSI4_ENABLE); - ddbwritel(dev, 0x00000000, MSI5_ENABLE); - ddbwritel(dev, 0x00000000, MSI6_ENABLE); - ddbwritel(dev, 0x00000000, MSI7_ENABLE); - -#ifdef CONFIG_PCI_MSI - if (msi && pci_msi_enabled()) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) - stat = pci_enable_msi_range(dev->pdev, 1, 2); - if (stat >= 1) { - dev->msi = stat; - pr_info("DDBridge: using %d MSI interrupt(s)\n", - dev->msi); - irq_flag = 0; - } else - pr_info("DDBridge: MSI not available.\n"); - -#else - stat = pci_enable_msi_block(dev->pdev, 2); - if (stat == 0) { - dev->msi = 1; - pr_info("DDBridge: using 2 MSI interrupts\n"); - } - if (stat == 1) - stat = pci_enable_msi(dev->pdev); - if (stat < 0) { - pr_info("DDBridge: MSI not available.\n"); - } else { - irq_flag = 0; - dev->msi++; - } -#endif - } - if (dev->msi == 2) { - stat = request_irq(dev->pdev->irq, irq_handler0, - irq_flag, "ddbridge", (void *) dev); - if (stat < 0) - goto fail0; - stat = request_irq(dev->pdev->irq + 1, irq_handler1, - irq_flag, "ddbridge", (void *) dev); - if (stat < 0) { - free_irq(dev->pdev->irq, dev); - goto fail0; - } - } else -#endif - { -#ifdef DDB_TEST_THREADED - stat = request_threaded_irq(dev->pdev->irq, irq_handler, - irq_thread, - irq_flag, - "ddbridge", (void *) dev); -#else - stat = request_irq(dev->pdev->irq, irq_handler, - irq_flag, "ddbridge", (void *) dev); -#endif - if (stat < 0) - goto fail0; + ddb_reset_ios(dev); } ddbwritel(dev, 0, DMA_BASE_READ); if (dev->link[0].info->type != DDB_MOD) @@ -223,22 +304,14 @@ static int __devinit ddb_probe(struct pci_dev *pdev, dev->link[0].info->port_num = 4; } - /*ddbwritel(dev, 0xffffffff, INTERRUPT_ACK);*/ - if (dev->msi == 2) { - ddbwritel(dev, 0x0fffff00, INTERRUPT_ENABLE); - ddbwritel(dev, 0x0000000f, MSI1_ENABLE); - } else { - ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE); - ddbwritel(dev, 0x00000000, MSI1_ENABLE); - } + stat = ddb_irq_init(dev); + if (stat < 0) + goto fail0; + if (ddb_init(dev) == 0) return 0; - ddbwritel(dev, 0, INTERRUPT_ENABLE); - ddbwritel(dev, 0, MSI1_ENABLE); - free_irq(dev->pdev->irq, dev); - if (dev->msi == 2) - free_irq(dev->pdev->irq + 1, dev); + ddb_irq_disable(dev); fail0: pr_err("fail0\n"); if (dev->msi) @@ -256,37 +329,6 @@ fail: /****************************************************************************/ /****************************************************************************/ -static struct ddb_regset octopus_i2c = { - .base = 0x80, - .num = 0x04, - .size = 0x20, -}; - -static struct ddb_regset octopus_i2c_buf = { - .base = 0x1000, - .num = 0x04, - .size = 0x200, -}; - -/****************************************************************************/ - - -static struct ddb_regmap octopus_map = { - .i2c = &octopus_i2c, - .i2c_buf = &octopus_i2c_buf, -}; - -static struct ddb_regmap octopus_net_map = { - .i2c = &octopus_i2c, - .i2c_buf = &octopus_i2c_buf, -}; - -static struct ddb_regmap octopus_mod_map = { -}; - - -/****************************************************************************/ - static struct ddb_info ddb_none = { .type = DDB_NONE, .name = "unknown Digital Devices PCIe card, install newer driver", @@ -418,26 +460,6 @@ static struct ddb_info ddb_dvbct = { /****************************************************************************/ -static struct ddb_info ddb_s2_48 = { - .type = DDB_OCTOPUS_MAX, - .name = "Digital Devices MAX S8 4/8", - .regmap = &octopus_map, - .port_num = 4, - .i2c_mask = 0x01, - .board_control = 1, -}; - -static struct ddb_info ddb_ct_8 = { - .type = DDB_OCTOPUS_MAX_CT, - .name = "Digital Devices MAX CT8", - .regmap = &octopus_map, - .port_num = 4, - .i2c_mask = 0x0f, - .board_control = 0x0ff, - .board_control_2 = 0xf00, - .ts_quirks = TS_QUIRK_SERIAL, -}; - static struct ddb_info ddb_mod = { .type = DDB_MOD, .name = "Digital Devices DVB-C modulator", @@ -446,13 +468,48 @@ static struct ddb_info ddb_mod = { .temp_num = 1, }; -static struct ddb_info ddb_octopus_net = { - .type = DDB_OCTONET, - .name = "Digital Devices OctopusNet network DVB adapter", - .regmap = &octopus_net_map, +static struct ddb_info ddb_mod_fsm_24 = { + .type = DDB_MOD, + .version = 2, + .name = "Digital Devices DVB-C modulator FSM-24", + .regmap = &octopus_mod_2_map, + .port_num = 24, + .temp_num = 1, +}; + +static struct ddb_info ddb_mod_fsm_16 = { + .type = DDB_MOD, + .version = 2, + .name = "Digital Devices DVB-C modulator FSM-16", + .regmap = &octopus_mod_2_map, + .port_num = 16, + .temp_num = 1, +}; + +static struct ddb_info ddb_mod_fsm_8 = { + .type = DDB_MOD, + .name = "Digital Devices DVB-C modulator FSM-8", + .version = 2, + .regmap = &octopus_mod_2_map, + .port_num = 8, + .temp_num = 1, +}; + +static struct ddb_info ddb_octopro_hdin = { + .type = DDB_OCTOPRO_HDIN, + .name = "Digital Devices OctopusNet Pro HDIN", + .regmap = &octopro_hdin_map, + .port_num = 10, + .i2c_mask = 0x3ff, + .mdio_num = 1, +}; + +static struct ddb_info ddb_octopro = { + .type = DDB_OCTOPRO, + .name = "Digital Devices OctopusNet Pro", + .regmap = &octopro_map, .port_num = 10, .i2c_mask = 0x3ff, - .ns_num = 12, .mdio_num = 1, }; @@ -493,7 +550,16 @@ static const struct pci_device_id ddb_id_tbl[] __devinitconst = { DDB_ID(DDVID, 0x0013, DDVID, 0x0043, ddb_ci_s2_pro), DDB_ID(DDVID, 0x0201, DDVID, 0x0001, ddb_mod), DDB_ID(DDVID, 0x0201, DDVID, 0x0002, ddb_mod), - DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_octopus_net), + DDB_ID(DDVID, 0x0210, DDVID, 0x0001, ddb_mod_fsm_24), + DDB_ID(DDVID, 0x0210, DDVID, 0x0002, ddb_mod_fsm_16), + DDB_ID(DDVID, 0x0210, DDVID, 0x0003, ddb_mod_fsm_8), + /* testing on OctopusNet Pro */ + DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_octopro_hdin), + DDB_ID(DDVID, 0x0321, PCI_ANY_ID, PCI_ANY_ID, ddb_none), + DDB_ID(DDVID, 0x0322, PCI_ANY_ID, PCI_ANY_ID, ddb_octopro), + DDB_ID(DDVID, 0x0323, PCI_ANY_ID, PCI_ANY_ID, ddb_none), + DDB_ID(DDVID, 0x0328, PCI_ANY_ID, PCI_ANY_ID, ddb_none), + DDB_ID(DDVID, 0x0329, PCI_ANY_ID, PCI_ANY_ID, ddb_octopro_hdin), /* in case sub-ids got deleted in flash */ DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), DDB_ID(DDVID, 0x0005, PCI_ANY_ID, PCI_ANY_ID, ddb_none), @@ -521,7 +587,7 @@ static __init int module_init_ddbridge(void) pr_info("Digital Devices PCIE bridge driver " DDBRIDGE_VERSION - ", Copyright (C) 2010-15 Digital Devices GmbH\n"); + ", Copyright (C) 2010-16 Digital Devices GmbH\n"); if (ddb_class_create() < 0) return -1; ddb_wq = create_workqueue("ddbridge"); diff --git a/ddbridge/ddbridge.h b/ddbridge/ddbridge.h index 25bbc71..cb70974 100644 --- a/ddbridge/ddbridge.h +++ b/ddbridge/ddbridge.h @@ -91,10 +91,10 @@ #include "lnbh25.h" #include "mxl5xx.h" -#define DDB_MAX_I2C 16 -#define DDB_MAX_PORT 16 -#define DDB_MAX_INPUT 44 -#define DDB_MAX_OUTPUT 10 +#define DDB_MAX_I2C 32 +#define DDB_MAX_PORT 32 +#define DDB_MAX_INPUT 64 +#define DDB_MAX_OUTPUT 32 #define DDB_MAX_LINK 4 #define DDB_LINK_SHIFT 28 @@ -106,25 +106,30 @@ struct ddb_regset { u32 size; }; -struct ddb_ports { - u32 base; - u32 num; - u32 size; -}; - struct ddb_regmap { - struct ddb_ports *bc; + u32 irq_version; + u32 irq_base_i2c; + u32 irq_base_idma; + u32 irq_base_odma; + u32 irq_base_gtl; + u32 irq_base_rate; + struct ddb_regset *i2c; struct ddb_regset *i2c_buf; - struct ddb_regset *dma; - struct ddb_regset *dma_buf; + struct ddb_regset *idma; + struct ddb_regset *idma_buf; + struct ddb_regset *odma; + struct ddb_regset *odma_buf; + struct ddb_regset *input; struct ddb_regset *output; + struct ddb_regset *channel; - struct ddb_regset *ci; - struct ddb_regset *pid_filter; - struct ddb_regset *ns; + //struct ddb_regset *ci; + //struct ddb_regset *pid_filter; + //struct ddb_regset *ns; struct ddb_regset *gtl; + //struct ddb_regset *mdio; }; struct ddb_ids { @@ -140,7 +145,7 @@ struct ddb_ids { }; struct ddb_info { - int type; + u32 type; #define DDB_NONE 0 #define DDB_OCTOPUS 1 #define DDB_OCTOPUS_CI 2 @@ -148,6 +153,9 @@ struct ddb_info { #define DDB_OCTONET 4 #define DDB_OCTOPUS_MAX 5 #define DDB_OCTOPUS_MAX_CT 6 +#define DDB_OCTOPRO 7 +#define DDB_OCTOPRO_HDIN 8 + u32 version; char *name; u32 i2c_mask; u8 port_num; @@ -161,8 +169,9 @@ struct ddb_info { u8 mdio_num; u8 con_clock; /* use a continuous clock */ u8 ts_quirks; -#define TS_QUIRK_SERIAL 1 -#define TS_QUIRK_REVERSED 2 +#define TS_QUIRK_SERIAL 1 +#define TS_QUIRK_REVERSED 2 +#define TS_QUIRK_NO_OUTPUT 4 struct ddb_regmap *regmap; }; @@ -171,6 +180,15 @@ struct ddb_info { #define DMA_MAX_BUFS 32 /* hardware table limit */ +#ifdef SMALL_DMA_BUFS +#define INPUT_DMA_BUFS 32 +#define INPUT_DMA_SIZE (32*47*21) +#define INPUT_DMA_IRQ_DIV 1 + +#define OUTPUT_DMA_BUFS 32 +#define OUTPUT_DMA_SIZE (32*47*21) +#define OUTPUT_DMA_IRQ_DIV 1 +#else #define INPUT_DMA_BUFS 8 #define INPUT_DMA_SIZE (128*47*21) #define INPUT_DMA_IRQ_DIV 1 @@ -178,19 +196,22 @@ struct ddb_info { #define OUTPUT_DMA_BUFS 8 #define OUTPUT_DMA_SIZE (128*47*21) #define OUTPUT_DMA_IRQ_DIV 1 +#endif struct ddb; struct ddb_port; struct ddb_dma { void *io; - u32 nr; + u32 regs; + u32 bufregs; + dma_addr_t pbuf[DMA_MAX_BUFS]; u8 *vbuf[DMA_MAX_BUFS]; u32 num; u32 size; u32 div; - u32 bufreg; + u32 bufval; #ifdef DDB_USE_WORK struct work_struct work; @@ -242,6 +263,7 @@ struct ddb_ci { struct ddb_io { struct ddb_port *port; u32 nr; + u32 regs; struct ddb_dma *dma; struct ddb_io *redo; struct ddb_io *redi; @@ -316,10 +338,21 @@ struct mod_base { u32 frequency; u32 flat_start; u32 flat_end; + + spinlock_t temp_lock; + int OverTemperatureError; + u8 temp_tab[11]; }; -struct mod_state { +struct ddb_mod { + struct ddb_port *port; + u32 nr; + u32 regs; + + u32 frequency; u32 modulation; + u32 symbolrate; + u64 obitrate; u64 ibitrate; u32 pcr_correction; @@ -413,10 +446,11 @@ struct ddb { struct ddb_input input[DDB_MAX_INPUT]; struct ddb_output output[DDB_MAX_OUTPUT]; struct dvb_adapter adap[DDB_MAX_INPUT]; - struct ddb_dma dma[DDB_MAX_INPUT + DDB_MAX_OUTPUT]; + struct ddb_dma idma[DDB_MAX_INPUT]; + struct ddb_dma odma[DDB_MAX_OUTPUT]; - void (*handler[128])(unsigned long); - unsigned long handler_data[128]; + void (*handler[4][256])(unsigned long); + unsigned long handler_data[4][256]; struct device *ddb_dev; u32 ddb_dev_users; @@ -436,7 +470,7 @@ struct ddb { u8 tsbuf[TS_CAPTURE_LEN]; struct mod_base mod_base; - struct mod_state mod[10]; + struct ddb_mod mod[24]; }; static inline void ddbwriteb(struct ddb *dev, u32 val, u32 adr) @@ -486,6 +520,7 @@ static inline void gtlw(struct ddb_link *link) } #endif +#if 0 static u32 ddblreadl(struct ddb_link *link, u32 adr) { if (unlikely(link->nr)) { @@ -519,6 +554,7 @@ static void ddblwritel(struct ddb_link *link, u32 val, u32 adr) } writel(val, (char *) (link->dev->regs + (adr))); } +#endif static u32 ddbreadl(struct ddb *dev, u32 adr) { @@ -714,6 +750,6 @@ void ddbridge_mod_rate_handler(unsigned long data); int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len); -#define DDBRIDGE_VERSION "0.9.23" +#define DDBRIDGE_VERSION "0.9.24" #endif diff --git a/ddbridge/octonet.c b/ddbridge/octonet.c index a8687b3..35dfb33 100644 --- a/ddbridge/octonet.c +++ b/ddbridge/octonet.c @@ -1,7 +1,7 @@ /* * octonet.c: Digital Devices network tuner driver * - * Copyright (C) 2012-15 Digital Devices GmbH + * Copyright (C) 2012-16 Digital Devices GmbH * Marcus Metzler * Ralph Metzler * @@ -25,7 +25,11 @@ #include "ddbridge.h" #include "ddbridge-regs.h" +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0)) #include +#else +#include +#endif static int adapter_alloc = 3; module_param(adapter_alloc, int, 0444); @@ -34,21 +38,13 @@ MODULE_PARM_DESC(adapter_alloc, #include "ddbridge-core.c" -static struct ddb_regset octopus_i2c = { - .base = 0x80, - .num = 0x04, - .size = 0x20, -}; - -static struct ddb_regset octopus_i2c_buf = { - .base = 0x1000, - .num = 0x04, - .size = 0x200, -}; - static struct ddb_regmap octopus_net_map = { + .irq_version = 1, + .irq_base_i2c = 0, .i2c = &octopus_i2c, .i2c_buf = &octopus_i2c_buf, + .input = &octopus_input, + .output = &octopus_output, }; static struct ddb_regset octopus_gtl = { @@ -58,8 +54,13 @@ static struct ddb_regset octopus_gtl = { }; static struct ddb_regmap octopus_net_gtl = { + .irq_version = 1, + .irq_base_i2c = 0, + .irq_base_gtl = 10, .i2c = &octopus_i2c, .i2c_buf = &octopus_i2c_buf, + .input = &octopus_input, + .output = &octopus_output, .gtl = &octopus_gtl, }; @@ -134,7 +135,6 @@ static int __init octonet_probe(struct platform_device *pdev) struct ddb *dev; struct resource *regs; int irq; - int i; dev = vzalloc(sizeof(struct ddb)); if (!dev) @@ -185,9 +185,7 @@ static int __init octonet_probe(struct platform_device *pdev) ddbwritel(dev, 0, ETHER_CONTROL); ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE); ddbwritel(dev, 0xffffffff, INTERRUPT_STATUS); - for (i = 0; i < 16; i++) - ddbwritel(dev, 0x00, TS_OUTPUT_CONTROL(i)); - usleep_range(5000, 6000); + ddb_reset_ios(dev); irq = platform_get_irq(dev->pfdev, 0); if (irq < 0) @@ -236,7 +234,7 @@ static __init int init_octonet(void) int res; pr_info("Digital Devices OctopusNet driver " DDBRIDGE_VERSION - ", Copyright (C) 2010-15 Digital Devices GmbH\n"); + ", Copyright (C) 2010-16 Digital Devices GmbH\n"); res = ddb_class_create(); if (res) return res; diff --git a/docs/ci b/docs/ci index 8bfca4e..dc5a839 100644 --- a/docs/ci +++ b/docs/ci @@ -1,3 +1,5 @@ +- General Information + The caX device associated with a CI device behaves just like any other caX interface. You usually use it through a library like libdvben50221 which is part of the dvb-apps package available at linuxtv.org. @@ -26,6 +28,24 @@ use the new interface. See docs/redirect for more info. +- Clock Speed + +The normal clock speed for the TS output is 72 MHz wich is the standard +speed used for CI. + +Packets are sent with an adjustable gap between the packets. +The gap size is (gap value * 2) + 4 or 0 if the gap is disabled. +So, the standard gap value of 4 leads to a gap of 12 bytes which means +that the effective data rate is (72*188)/200 = 67.68 MBits/s. + +Depending on the hardware, the clock speed can be changed with the +ci_bitrate module parameter: + +- Octopus CI, Octopus CI S2 Pro : supported + +- old CI single flex modules: supported + +- new dual CI flex module: not yet supported, use the standard 72000 kHz - +Valid ranges for are from ... to 96000 KHz. diff --git a/dvb-core/dvb_frontend.c b/dvb-core/dvb_frontend.c index 4a59c87..6454678 100644 --- a/dvb-core/dvb_frontend.c +++ b/dvb-core/dvb_frontend.c @@ -955,6 +955,7 @@ static int dvb_frontend_clear_cache(struct dvb_frontend *fe) } c->stream_id = NO_STREAM_ID_FILTER; + c->pls = NO_SCRAMBLING_CODE; switch (c->delivery_system) { case SYS_DVBS: @@ -1031,6 +1032,7 @@ static struct dtv_cmds_h dtv_cmds[DTV_MAX_COMMAND + 1] = { _DTV_CMD(DTV_DVBT2_PLP_ID_LEGACY, 1, 0), _DTV_CMD(DTV_LNA, 1, 0), _DTV_CMD(DTV_INPUT, 1, 0), + _DTV_CMD(DTV_PLS, 1, 0), /* Get */ _DTV_CMD(DTV_DISEQC_SLAVE_REPLY, 0, 1), @@ -1462,6 +1464,10 @@ static int dtv_property_process_get(struct dvb_frontend *fe, tvp->u.buffer.len = 4; break; + case DTV_PLS: + tvp->u.data = c->pls; + break; + /* Fill quality measures */ case DTV_STAT_SIGNAL_STRENGTH: tvp->u.st = c->strength; @@ -1901,6 +1907,10 @@ static int dtv_property_process_set(struct dvb_frontend *fe, r = fe->ops.set_input(fe, c->input); break; + case DTV_PLS: + c->pls = tvp->u.data; + break; + default: return -EINVAL; } diff --git a/dvb-core/dvb_frontend.h b/dvb-core/dvb_frontend.h index 2fd7752..a8df38f 100644 --- a/dvb-core/dvb_frontend.h +++ b/dvb-core/dvb_frontend.h @@ -397,6 +397,7 @@ struct dtv_frontend_properties { u32 lna; s32 input; + u32 pls; /* statistics data */ struct dtv_fe_stats strength; diff --git a/frontends/cxd2843.c b/frontends/cxd2843.c index 7ec11ee..10e8a3b 100644 --- a/frontends/cxd2843.c +++ b/frontends/cxd2843.c @@ -35,8 +35,11 @@ #include #include "dvb_frontend.h" +#include "dvb_math.h" #include "cxd2843.h" +#define Log10x100(x) ((s32)(((((u64) intlog2(x) * 0x1e1a5e2e) >> 47 ) + 1) >> 1)) + #define USE_ALGO 1 enum demod_type { CXD2843, CXD2837, CXD2838 }; @@ -329,7 +332,7 @@ static inline u32 MulDiv32(u32 a, u32 b, u32 c) static int read_tps(struct cxd_state *state, u8 *tps) { if (state->last_status != 0x1f) - return 0; + return -1; freeze_regst(state); readregst_unlocked(state, 0x10, 0x2f, tps, 7); @@ -337,6 +340,63 @@ static int read_tps(struct cxd_state *state, u8 *tps) return 0; } +/* Read DVBT2 OFDM Info */ +/* OFDMInfo[0] [5] OFDM_MIXED */ +/* OFDMInfo[0] [4] OFDM_MISO */ +/* OFDMInfo[0] [2:0] OFDM_FFTSIZE[2:0] */ +/* OFDMInfo[1] [6:4] OFDM_GI[2:0] */ +/* OFDMInfo[1] [2:0] OFDM_PP[2:0] */ +/* OFDMInfo[2] [4] OFDM_BWT_EXT */ +/* OFDMInfo[2] [3:0] OFDM_PAPR[3:0] */ +/* OFDMInfo[3] [3:0] OFDM_NDSYM[11:8] */ +/* OFDMInfo[4] [7:0] OFDM_NDSYM[7:0] */ + +static int read_t2_ofdm_info(struct cxd_state *state, u8 *ofdm) +{ + if (state->last_status != 0x1f) + return -1; + + freeze_regst(state); + readregst_unlocked(state, 0x20, 0x5c, ofdm, 5); + unfreeze_regst(state); + return 0; +} + +/* Read DVBT2 QAM, + Data PLP + 0 [7:0] L1POST_PLP_ID[7:0] + 1 [2:0] L1POST_PLP_TYPE[2:0] + 2 [4:0] L1POST_PLP_PAYLOAD_TYPE[4:0] + 3 [0] L1POST_FF_FLAG + 4 [2:0] L1POST_FIRST_RF_IDX[2:0] + 5 [7:0] L1POST_FIRST_FRAME_IDX[7:0] + 6 [7:0] L1POST_PLP_GROUP_ID[7:0] + 7 [2:0] L1POST_PLP_COD[2:0] + 8 [2:0] L1POST_PLP_MOD[2:0] + 9 [0] L1POST_PLP_ROTATION + 10 [1:0] L1POST_PLP_FEC_TYPE[1:0] + 11 [1:0] L1POST_PLP_NUM_BLOCKS_MAX[9:8] + 12 [7:0] L1POST_PLP_NUM_BLOCKS_MAX[7:0] + 13 [7:0] L1POST_FRAME_INTERVAL[7:0] + 14 [7:0] L1POST_TIME_IL_LENGTH[7:0] + 15 [0] L1POST_TIME_IL_TYPE + 16 [0] L1POST_IN_BAND_FLAG + 17 [7:0] L1POST_RESERVED_1[15:8] + 18 [7:0] L1POST_RESERVED_1[7:0] + 19-37 same for common PLP +*/ + +static int read_t2_tlp_info(struct cxd_state *state, u8 off, u8 count, u8 *tlp) +{ + if (state->last_status != 0x1f) + return -1; + + freeze_regst(state); + readregst_unlocked(state, 0x22, 0x54 + off, tlp, count); + unfreeze_regst(state); + return 0; +} + static void Active_to_Sleep(struct cxd_state *state) { if (state->state <= Sleep) @@ -1174,7 +1234,7 @@ static int set_parameters(struct dvb_frontend *fe) fe->ops.tuner_ops.set_params(fe); state->bandwidth = fe->dtv_property_cache.bandwidth_hz; state->bw = (fe->dtv_property_cache.bandwidth_hz + 999999) / 1000000; - if (fe->dtv_property_cache.stream_id == 0xffffffff) { + if (fe->dtv_property_cache.stream_id == NO_STREAM_ID_FILTER) { state->DataSliceID = 0xffffffff; state->plp = 0xffffffff; } else { @@ -1273,18 +1333,20 @@ static int read_snr(struct dvb_frontend *fe, u16 *snr); static int get_stats(struct dvb_frontend *fe) { - struct cxd_state *state = fe->demodulator_priv; struct dtv_frontend_properties *p = &fe->dtv_property_cache; u16 val; + s64 str; if (fe->ops.tuner_ops.get_rf_strength) fe->ops.tuner_ops.get_rf_strength(fe, &val); else val = 0; + str = 1000 * (s64) (s16) val; + str -= 108750; p->strength.len = 1; p->strength.stat[0].scale = FE_SCALE_DECIBEL; - p->strength.stat[0].uvalue = 1000 * (s64) (s16) val; + p->strength.stat[0].uvalue = str; read_snr(fe, &val); p->cnr.len = 1; @@ -1313,6 +1375,12 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status) if (rdata & 0x20) *status |= 0x1f; } + if (*status == 0x1f && state->FirstTimeLock) { + readregst(state, 0x40, 0x19, &rdata, 1); + rdata &= 0x07; + state->BERScaleMax = ( rdata < 2 ) ? 18 : 19; + state->FirstTimeLock = 0; + } break; case ActiveT: readregst(state, 0x10, 0x10, &rdata, 1); @@ -1323,6 +1391,16 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status) if (rdata & 0x20) *status |= 0x1f; } + if (*status == 0x1f && state->FirstTimeLock) { + u8 tps[7]; + + read_tps(state, tps); + state->BERScaleMax = + (((tps[0] >> 6) & 0x03) < 2 ) ? 17 : 18; + if ((tps[0] & 7) < 2) + state->BERScaleMax--; + state->FirstTimeLock = 0; + } break; case ActiveT2: readregst(state, 0x20, 0x10, &rdata, 1); @@ -1369,6 +1447,12 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status) if (rdata & 0x01) *status |= 0x18; } + if (*status == 0x1f && state->FirstTimeLock) { + /* readregst(state, 0x40, 0x19, &rdata, 1); */ + /* rdata &= 0x07; */ + /* state->BERScaleMax = ( rdata < 2 ) ? 18 : 19; */ + state->FirstTimeLock = 0; + } break; default: break; @@ -1407,8 +1491,44 @@ static int get_ber_t(struct cxd_state *state, u32 *n, u32 *d) static int get_ber_t2(struct cxd_state *state, u32 *n, u32 *d) { + u8 BERRegs[4]; + u8 Scale; + u8 FECType; + u8 CodeRate; + static const u32 nBCHBitsLookup[2][8] = { + /* R1_2 R3_5 R2_3 R3_4 R4_5 R5_6 R1_3 R2_5 */ + {7200, 9720, 10800, 11880, 12600, 13320, 5400, 6480}, /* 16K FEC */ + {32400, 38880, 43200, 48600, 51840, 54000, 21600, 25920} /* 64k FEC */ + }; + *n = 0; *d = 1; + freeze_regst(state); + readregst(state, 0x24, 0x40, BERRegs, 4); + readregst(state, 0x22, 0x5e, &FECType, 1); + readregst(state, 0x22, 0x5b, &CodeRate, 1); + + FECType &= 0x03; + CodeRate &= 0x07; + unfreeze_regst(state); + if (FECType > 1) + return 0; + + + readregst(state, 0x20, 0x72, &Scale, 1); + Scale &= 0x0F; + if (BERRegs[0] & 0x01) { + state->LastBERNominator = (((u32) BERRegs[1] & 0x3F) << 16) | + (((u32) BERRegs[2]) << 8) | BERRegs[3]; + state->LastBERDenominator = nBCHBitsLookup[FECType][CodeRate] << Scale; + if (state->LastBERNominator < 256 && + Scale < state->BERScaleMax) { + writebitst(state, 0x20, 0x72, Scale + 1, 0x0F); + } else if (state->LastBERNominator > 512 && Scale > 8) + writebitst(state, 0x20, 0x72, Scale - 1, 0x0F); + } + *n = state->LastBERNominator; + *d = state->LastBERDenominator; return 0; } @@ -1458,7 +1578,7 @@ static int read_ber(struct dvb_frontend *fe, u32 *ber) { struct cxd_state *state = fe->demodulator_priv; struct dtv_frontend_properties *p = &fe->dtv_property_cache; - u32 n, d; + u32 n = 0, d = 1; int s = 0; *ber = 0; @@ -1504,57 +1624,63 @@ static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) return 0; } -static s32 Log10x100(u32 x) -{ - static u32 LookupTable[100] = { - 101157945, 103514217, 105925373, 108392691, 110917482, - 113501082, 116144861, 118850223, 121618600, 124451461, - 127350308, 130316678, 133352143, 136458314, 139636836, - 142889396, 146217717, 149623566, 153108746, 156675107, - 160324539, 164058977, 167880402, 171790839, 175792361, - 179887092, 184077200, 188364909, 192752491, 197242274, - 201836636, 206538016, 211348904, 216271852, 221309471, - 226464431, 231739465, 237137371, 242661010, 248313311, - 254097271, 260015956, 266072506, 272270131, 278612117, - 285101827, 291742701, 298538262, 305492111, 312607937, - 319889511, 327340695, 334965439, 342767787, 350751874, - 358921935, 367282300, 375837404, 384591782, 393550075, - 402717034, 412097519, 421696503, 431519077, 441570447, - 451855944, 462381021, 473151259, 484172368, 495450191, - 506990708, 518800039, 530884444, 543250331, 555904257, - 568852931, 582103218, 595662144, 609536897, 623734835, - 638263486, 653130553, 668343918, 683911647, 699841996, - 716143410, 732824533, 749894209, 767361489, 785235635, - 803526122, 822242650, 841395142, 860993752, 881048873, - 901571138, 922571427, 944060876, 966050879, 988553095, - }; - s32 y; - int i; - - if (x == 0) - return 0; - y = 800; - if (x >= 1000000000) { - x /= 10; - y += 100; - } - - while (x < 100000000) { - x *= 10; - y -= 100; - } - i = 0; - while (i < 100 && x > LookupTable[i]) - i += 1; - y += i; - return y; -} - #if 0 ++NTSTATUS CCXD2843ER::GetT2PLPIds(DD_T2_PLPIDS* pT2_PLPIDS) + { + NTSTATUS status = STATUS_SUCCESS; +- *pReturned = 0; ++ + if( m_DemodState != ActiveT2 ) return STATUS_NOT_IMPLEMENTED; +- if( m_LastLockStatus < TSLock || m_LastLockStatus == Unlock ) return status; ++ if( m_LastLockStatus < TSLock ) return status; + + do + { ++ BYTE tmp; ++ + CHK_ERROR(FreezeRegsT()); + ++ CHK_ERROR(ReadRegT(0x20,0x5C,&tmp)); // OFDM Info ++ ++ if( tmp & 0x20 ) pT2_PLPIDS->Flags |= DD_T2_PLPIDS_FEF; ++ if( m_T2Profile == T2P_Lite ) pT2_PLPIDS->Flags |= DD_T2_PLPIDS_LITE; ++ ++ CHK_ERROR(ReadRegT(0x22,0x54,&tmp)); ++ pT2_PLPIDS->PLPID = tmp; ++ ++ CHK_ERROR(ReadRegT(0x22,0x54 + 19 + 13,&tmp)); // Interval ++ if( tmp > 0 ) ++ { ++ CHK_ERROR(ReadRegT(0x22,0x54 + 19,&tmp)); ++ pT2_PLPIDS->CommonPLPID = tmp; ++ } ++ + BYTE nPids = 0; + CHK_ERROR(ReadRegT(0x22,0x7F,&nPids)); + +- pValues[0] = nPids; +- if( nPids >= nValues ) nPids = BYTE(nValues-1); ++ pT2_PLPIDS->NumPLPS = nPids; ++ CHK_ERROR(ReadRegT(0x22,0x80,&pT2_PLPIDS->PLPList[0], nPids > 128 ? 128 : nPids)); + +- CHK_ERROR(ReadRegT(0x22,0x80,&pValues[1], nPids > 128 ? 128 : nPids)); +- + if( nPids > 128 ) + { +- CHK_ERROR(ReadRegT(0x23,0x10,&pValues[129], nPids - 128)); ++ CHK_ERROR(ReadRegT(0x23,0x10,&pT2_PLPIDS->PLPList[128], nPids - 128)); + } + +- *pReturned = nPids + 1; ++ + } + while(0); + UnFreezeRegsT(); + static void GetPLPIds(struct cxd_state *state, u32 nValues, u8 *Values, u32 *Returned) { - u8 nPids = 0; + u8 nPids = 0, tmp; *Returned = 0; if (state->state != ActiveT2) @@ -1780,6 +1906,110 @@ static int get_algo(struct dvb_frontend *fe) return DVBFE_ALGO_HW; } +static int get_fe_t2(struct cxd_state *state) +{ + struct dvb_frontend *fe = &state->frontend; + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + u8 ofdm[5], modcod[2]; + + freeze_regst(state); + readregst_unlocked(state, 0x20, 0x5c, ofdm, 5); + readregst_unlocked(state, 0x22, 0x5b, modcod, 2); + unfreeze_regst(state); + + switch (modcod[0] & 0x07) { + case 0: + p->fec_inner = FEC_1_2; + break; + case 1: + p->fec_inner = FEC_3_5; + break; + case 2: + p->fec_inner = FEC_2_3; + break; + case 3: + p->fec_inner = FEC_3_4; + break; + case 4: + p->fec_inner = FEC_4_5; + break; + case 5: + p->fec_inner = FEC_5_6; + break; + case 6: + p->fec_inner = FEC_1_3; + break; + case 7: + p->fec_inner = FEC_2_5; + break; + } + + switch (modcod[1] & 0x07) { + case 0: + p->modulation = QPSK; + break; + case 1: + p->modulation = QAM_16; + break; + case 2: + p->modulation = QAM_64; + break; + case 3: + p->modulation = QAM_256; + break; + } + + switch (ofdm[0] & 0x07) { + case 0: + p->transmission_mode = TRANSMISSION_MODE_2K; + break; + case 1: + p->transmission_mode = TRANSMISSION_MODE_8K; + break; + case 2: + p->transmission_mode = TRANSMISSION_MODE_4K; + break; + case 3: + p->transmission_mode = TRANSMISSION_MODE_1K; + break; + case 4: + p->transmission_mode = TRANSMISSION_MODE_16K; + break; + case 5: + p->transmission_mode = TRANSMISSION_MODE_32K; + break; + case 6: + p->transmission_mode = TRANSMISSION_MODE_64K; + break; + } + + switch ((ofdm[1] >> 4) & 0x07) { + case 0: + p->guard_interval = GUARD_INTERVAL_1_32; + break; + case 1: + p->guard_interval = GUARD_INTERVAL_1_16; + break; + case 2: + p->guard_interval = GUARD_INTERVAL_1_8; + break; + case 3: + p->guard_interval = GUARD_INTERVAL_1_4; + break; + case 4: + p->guard_interval = GUARD_INTERVAL_1_128; + break; + case 5: + p->guard_interval = GUARD_INTERVAL_19_128; + break; + case 6: + p->guard_interval = GUARD_INTERVAL_19_256; + break; + } + + return 0; +} + static int get_fe_t(struct cxd_state *state) { struct dvb_frontend *fe = &state->frontend; @@ -1907,6 +2137,7 @@ static int get_frontend(struct dvb_frontend *fe) get_fe_t(state); break; case ActiveT2: + get_fe_t2(state); break; case ActiveC: get_fe_c(state); diff --git a/frontends/drxk_hard.c b/frontends/drxk_hard.c index 85fc35e..a87307b 100644 --- a/frontends/drxk_hard.c +++ b/frontends/drxk_hard.c @@ -4866,10 +4866,6 @@ static int drxk_set_parameters (struct dvb_frontend *fe, struct dvb_frontend_parameters *p) #endif { -#ifndef USE_API3 - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - u32 delsys = p->delivery_system, old_delsys; -#endif struct drxk_state *state = fe->demodulator_priv; u32 IF; @@ -4896,7 +4892,7 @@ static int drxk_set_parameters (struct dvb_frontend *fe, return 0; } -static int drxk_c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +static int drxk_c_get_frontend(struct dvb_frontend *fe) { //struct drxk_state *state = fe->demodulator_priv; //printk("%s\n", __FUNCTION__); @@ -4990,7 +4986,7 @@ static int drxk_t_sleep(struct dvb_frontend* fe) return 0; } -static int drxk_t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +static int drxk_t_get_frontend(struct dvb_frontend *fe) { //struct drxk_state *state = fe->demodulator_priv; //printk("%s\n", __FUNCTION__); diff --git a/frontends/mxl5xx.c b/frontends/mxl5xx.c index 7148c64..452e82a 100644 --- a/frontends/mxl5xx.c +++ b/frontends/mxl5xx.c @@ -193,7 +193,8 @@ static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val) if (stat) pr_err("i2c read error 1\n"); if (!stat) - stat = i2cread(state, (u8 *) val, MXL_HYDRA_REG_SIZE_IN_BYTES); + stat = i2cread(state, (u8 *) val, + MXL_HYDRA_REG_SIZE_IN_BYTES); le32_to_cpus(val); if (stat) pr_err("i2c read error 2\n"); @@ -218,7 +219,8 @@ static int send_command(struct mxl *state, u32 size, u8 *buf) mutex_unlock(&state->base->i2c_lock); usleep_range(1000, 2000); mutex_lock(&state->base->i2c_lock); - read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val); + read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, + &val); } if (!count) { pr_info("mxl5xx: send_command busy\n"); @@ -247,7 +249,8 @@ static int write_register(struct mxl *state, u32 reg, u32 val) return stat; } -static int write_register_block(struct mxl *state, u32 reg, u32 size, u8 *data) +static int write_register_block(struct mxl *state, u32 reg, + u32 size, u8 *data) { int stat; u8 *buf = state->base->buf; @@ -308,7 +311,8 @@ static int read_register(struct mxl *state, u32 reg, u32 *val) if (stat) pr_err("i2c read error 1\n"); if (!stat) - stat = i2cread(state, (u8 *) val, MXL_HYDRA_REG_SIZE_IN_BYTES); + stat = i2cread(state, (u8 *) val, + MXL_HYDRA_REG_SIZE_IN_BYTES); mutex_unlock(&state->base->i2c_lock); le32_to_cpus(val); if (stat) @@ -443,8 +447,10 @@ static int CfgDemodAbortTune(struct mxl *state) u8 cmdBuff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; abortTuneCmd.demodId = state->demod; - BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE, cmdSize, &abortTuneCmd, cmdBuff); - return send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]); + BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE, + cmdSize, &abortTuneCmd, cmdBuff); + return send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, + &cmdBuff[0]); } static int reset_fec_counter(struct mxl *state) @@ -456,7 +462,8 @@ static int reset_fec_counter(struct mxl *state) BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_RESET_FEC_COUNTER_CMD, MXL_CMD_WRITE, cmdSize, &demodIndex, cmdBuff); - return send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]); + return send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, + &cmdBuff[0]); } static int send_master_cmd(struct dvb_frontend *fe, @@ -517,14 +524,16 @@ static int set_parameters(struct dvb_frontend *fe) demodChanCfg.fecCodeRate = MXL_HYDRA_FEC_AUTO; mutex_lock(&state->base->tune_lock); - if (time_after(jiffies + msecs_to_jiffies(200), state->base->next_tune)) + if (time_after(jiffies + msecs_to_jiffies(200), + state->base->next_tune)) while (time_before(jiffies, state->base->next_tune)) msleep(10); state->base->next_tune = jiffies + msecs_to_jiffies(100); state->tuner_in_use = state->tuner; BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_SET_PARAM_CMD, MXL_CMD_WRITE, cmdSize, &demodChanCfg, cmdBuff); - stat = send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]); + stat = send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, + &cmdBuff[0]); mutex_unlock(&state->base->tune_lock); return stat; } @@ -634,7 +643,7 @@ static int read_ber(struct dvb_frontend *fe, u32 *ber) { struct mxl *state = fe->demodulator_priv; struct dtv_frontend_properties *p = &fe->dtv_property_cache; - u32 reg[8], reg2[4]; + u32 reg[8], reg2[4], n = 0, d = 0; int stat; *ber = 0; @@ -645,11 +654,12 @@ static int read_ber(struct dvb_frontend *fe, u32 *ber) HYDRA_DMD_STATUS_OFFSET(state->demod)), (7 * sizeof(u32)), (u8 *) ®[0]); - stat = read_register_block(state, - (HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET + - HYDRA_DMD_STATUS_OFFSET(state->demod)), - (4 * sizeof(u32)), - (u8 *) ®2[0]); + stat = read_register_block( + state, + (HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET + + HYDRA_DMD_STATUS_OFFSET(state->demod)), + (4 * sizeof(u32)), + (u8 *) ®2[0]); HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); mutex_unlock(&state->base->status_lock); @@ -670,9 +680,9 @@ static int read_ber(struct dvb_frontend *fe, u32 *ber) default: break; } - pr_info("mxl5xx: ber %08x %08x %08x %08x %08x %08x %08x\n", + pr_debug("mxl5xx: ber %08x %08x %08x %08x %08x %08x %08x\n", reg[0], reg[1], reg[2], reg[3], reg[4], reg[5], reg[6]); - pr_info("mxl5xx: ber2 %08x %08x %08x %08x\n", + pr_debug("mxl5xx: ber2 %08x %08x %08x %08x\n", reg[0], reg[1], reg[2], reg[3]); //pre_bit_error, pre_bit_count //post_bit_error, post_bit_count; @@ -755,7 +765,7 @@ static int get_frontend(struct dvb_frontend *fe) HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); mutex_unlock(&state->base->status_lock); - pr_info("mxl5xx: freq=%u delsys=%u srate=%u\n", + pr_debug("mxl5xx: freq=%u delsys=%u srate=%u\n", freq * 1000, regData[DMD_STANDARD_ADDR], regData[DMD_SYMBOL_RATE_ADDR]); p->symbol_rate = regData[DMD_SYMBOL_RATE_ADDR]; @@ -769,7 +779,8 @@ static int get_frontend(struct dvb_frontend *fe) case SYS_DSS: break; case SYS_DVBS2: - switch ((MXL_HYDRA_PILOTS_E ) regData[DMD_DVBS2_PILOT_ON_OFF_ADDR]) { + switch ((MXL_HYDRA_PILOTS_E ) + regData[DMD_DVBS2_PILOT_ON_OFF_ADDR]) { case MXL_HYDRA_PILOTS_OFF: p->pilot = PILOT_OFF; break; @@ -780,7 +791,8 @@ static int get_frontend(struct dvb_frontend *fe) break; } case SYS_DVBS: - switch ((MXL_HYDRA_MODULATION_E) regData[DMD_MODULATION_SCHEME_ADDR]) { + switch ((MXL_HYDRA_MODULATION_E) + regData[DMD_MODULATION_SCHEME_ADDR]) { case MXL_HYDRA_MOD_QPSK: p->modulation = QPSK; break; @@ -790,7 +802,8 @@ static int get_frontend(struct dvb_frontend *fe) default: break; } - switch ((MXL_HYDRA_ROLLOFF_E) regData[DMD_SPECTRUM_ROLL_OFF_ADDR]) { + switch ((MXL_HYDRA_ROLLOFF_E) + regData[DMD_SPECTRUM_ROLL_OFF_ADDR]) { case MXL_HYDRA_ROLLOFF_0_20: p->rolloff = ROLLOFF_20; break; @@ -903,12 +916,14 @@ static int write_fw_segment(struct mxl *state, u32 origSize = 0; u8 *wBufPtr = NULL; u32 blockSize = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - - (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4; + (MXL_HYDRA_I2C_HDR_SIZE + + MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4; u8 wMsgBuffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)]; do { - size = origSize = (((u32)(dataCount + blockSize)) > totalSize) ? + size = origSize = + (((u32)(dataCount + blockSize)) > totalSize) ? (totalSize - dataCount) : blockSize; if (origSize & 3) @@ -929,8 +944,8 @@ static int write_fw_segment(struct mxl *state, return status; } -static int do_firmware_download(struct mxl *state, u8 *mbinBufferPtr, u32 mbinBufferSize) - +static int do_firmware_download(struct mxl *state, u8 *mbinBufferPtr, + u32 mbinBufferSize) { int status; u32 index = 0; @@ -955,26 +970,31 @@ static int do_firmware_download(struct mxl *state, u8 *mbinBufferPtr, u32 mbinBu __func__, segmentPtr->header.id); return -EINVAL; } - segLength = get_big_endian(24, &(segmentPtr->header.len24[0])); - segAddress = get_big_endian(32, &(segmentPtr->header.address[0])); + segLength = get_big_endian(24, + &(segmentPtr->header.len24[0])); + segAddress = get_big_endian(32, + &(segmentPtr->header.address[0])); if (state->base->type == MXL_HYDRA_DEVICE_568) { if ((((segAddress & 0x90760000) == 0x90760000) || ((segAddress & 0x90740000) == 0x90740000)) && (xcpuFwFlag == MXL_FALSE)) { - SET_REG_FIELD_DATA(PRCM_PRCM_CPU_SOFT_RST_N, 1); + SET_REG_FIELD_DATA(PRCM_PRCM_CPU_SOFT_RST_N, + 1); msleep(200); write_register(state, 0x90720000, 0); msleep(10); xcpuFwFlag = MXL_TRUE; } status = write_fw_segment(state, segAddress, - segLength, (u8 *) segmentPtr->data); + segLength, + (u8 *) segmentPtr->data); } else { if (((segAddress & 0x90760000) != 0x90760000) && ((segAddress & 0x90740000) != 0x90740000)) status = write_fw_segment(state, segAddress, - segLength, (u8 *) segmentPtr->data); + segLength, + (u8 *) segmentPtr->data); } if (status) return status; @@ -1037,14 +1057,17 @@ static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len) if (status) return status; - /* Disable clock to Baseband, Wideband, SerDes, Alias ext & Transport modules */ - status = write_register(state, HYDRA_MODULES_CLK_2_REG, HYDRA_DISABLE_CLK_2); + /* Disable clock to Baseband, Wideband, SerDes, + Alias ext & Transport modules */ + status = write_register(state, HYDRA_MODULES_CLK_2_REG, + HYDRA_DISABLE_CLK_2); if (status) return status; /* Clear Software & Host interrupt status - (Clear on read) */ status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®Data); if (status) return status; + status = do_firmware_download(state, mbin, mbin_len); if (status) return status; @@ -1081,13 +1104,15 @@ static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len) pr_info("mxl5xx: Hydra FW alive. Hail!\n"); - /* sometimes register values are wrong shortly after first heart beats */ + /* sometimes register values are wrong shortly + after first heart beats */ msleep(50); devSkuCfg.skuType = state->base->sku_type; BUILD_HYDRA_CMD(MXL_HYDRA_DEV_CFG_SKU_CMD, MXL_CMD_WRITE, cmdSize, &devSkuCfg, cmdBuff); - status = send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]); + status = send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, + &cmdBuff[0]); return status; } @@ -1117,19 +1142,32 @@ static int cfg_ts_pad_mux(struct mxl *state, MXL_BOOL_E enableSerialTS) case MXL_HYDRA_DEVICE_541S: case MXL_HYDRA_DEVICE_561S: case MXL_HYDRA_DEVICE_581S: - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_14_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_15_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_16_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_17_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_18_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_19_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_20_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_21_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_22_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_23_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_24_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_25_PINMUX_SEL, padMuxValue); - status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_26_PINMUX_SEL, padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_14_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_15_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_16_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_17_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_18_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_19_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_20_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_21_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_22_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_23_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_24_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_25_PINMUX_SEL, + padMuxValue); + status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_26_PINMUX_SEL, + padMuxValue); break; case MXL_HYDRA_DEVICE_544: @@ -1313,7 +1351,7 @@ static int enable_tuner(struct mxl *state, u32 tuner, u32 enable) if (!count) return -1; read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); - pr_info("mxl5xx: tuner %u ready = %u\n", tuner , (val >> tuner) & 1); + /*pr_info("mxl5xx: tuner %u ready = %u\n", tuner , (val >> tuner) & 1);*/ #endif return 0; @@ -1348,8 +1386,10 @@ static int config_ts(struct mxl *state, MXL_HYDRA_DEMOD_ID_E demodId, {XPT_TS_CLK_PHASE4}, {XPT_TS_CLK_PHASE5}, {XPT_TS_CLK_PHASE6}, {XPT_TS_CLK_PHASE7} }; MXL_REG_FIELD_T xpt_lsb_first[MXL_HYDRA_DEMOD_MAX] = { - {XPT_LSB_FIRST0}, {XPT_LSB_FIRST1}, {XPT_LSB_FIRST2}, {XPT_LSB_FIRST3}, - {XPT_LSB_FIRST4}, {XPT_LSB_FIRST5}, {XPT_LSB_FIRST6}, {XPT_LSB_FIRST7} }; + {XPT_LSB_FIRST0}, {XPT_LSB_FIRST1}, + {XPT_LSB_FIRST2}, {XPT_LSB_FIRST3}, + {XPT_LSB_FIRST4}, {XPT_LSB_FIRST5}, + {XPT_LSB_FIRST6}, {XPT_LSB_FIRST7} }; MXL_REG_FIELD_T xpt_sync_byte[MXL_HYDRA_DEMOD_MAX] = { {XPT_SYNC_FULL_BYTE0}, {XPT_SYNC_FULL_BYTE1}, {XPT_SYNC_FULL_BYTE2}, {XPT_SYNC_FULL_BYTE3}, @@ -1384,16 +1424,17 @@ static int config_ts(struct mxl *state, MXL_HYDRA_DEMOD_ID_E demodId, MXL_REG_FIELD_T mxl561_xpt_ts_sync[MXL_HYDRA_DEMOD_ID_6] = { {PAD_MUX_DIGIO_25_PINMUX_SEL}, {PAD_MUX_DIGIO_20_PINMUX_SEL}, {PAD_MUX_DIGIO_17_PINMUX_SEL}, {PAD_MUX_DIGIO_11_PINMUX_SEL}, - {PAD_MUX_DIGIO_08_PINMUX_SEL}, {PAD_MUX_DIGIO_03_PINMUX_SEL} }; + {PAD_MUX_DIGIO_08_PINMUX_SEL}, {PAD_MUX_DIGIO_03_PINMUX_SEL}}; MXL_REG_FIELD_T mxl561_xpt_ts_valid[MXL_HYDRA_DEMOD_ID_6] = { {PAD_MUX_DIGIO_26_PINMUX_SEL}, {PAD_MUX_DIGIO_19_PINMUX_SEL}, {PAD_MUX_DIGIO_18_PINMUX_SEL}, {PAD_MUX_DIGIO_10_PINMUX_SEL}, - {PAD_MUX_DIGIO_09_PINMUX_SEL}, {PAD_MUX_DIGIO_02_PINMUX_SEL} }; + {PAD_MUX_DIGIO_09_PINMUX_SEL}, {PAD_MUX_DIGIO_02_PINMUX_SEL}}; demodId = state->base->ts_map[demodId]; if (MXL_ENABLE == mpegOutParamPtr->enable) { - if (mpegOutParamPtr->mpegMode == MXL_HYDRA_MPEG_MODE_PARALLEL) { + if (mpegOutParamPtr->mpegMode == + MXL_HYDRA_MPEG_MODE_PARALLEL) { #if 0 for (i = MXL_HYDRA_DEMOD_ID_0; i < MXL_HYDRA_DEMOD_MAX; i++) { mxlStatus |= MxLWare_Hydra_UpdateByMnemonic(devId, @@ -1527,11 +1568,12 @@ static int config_ts(struct mxl *state, MXL_HYDRA_DEMOD_ID_E demodId, } if (mpegOutParamPtr->mpegMode != MXL_HYDRA_MPEG_MODE_PARALLEL) { - status |= update_by_mnemonic(state, - xpt_enable_output[demodId].regAddr, - xpt_enable_output[demodId].lsbPos, - xpt_enable_output[demodId].numOfBits, - mpegOutParamPtr->enable); + status |= + update_by_mnemonic(state, + xpt_enable_output[demodId].regAddr, + xpt_enable_output[demodId].lsbPos, + xpt_enable_output[demodId].numOfBits, + mpegOutParamPtr->enable); } return status; } @@ -1569,7 +1611,8 @@ static int config_dis(struct mxl *state, u32 id) BUILD_HYDRA_CMD(MXL_HYDRA_DISEQC_CFG_MSG_CMD, MXL_CMD_WRITE, cmdSize, &diseqcMsg, cmdBuff); - return send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]); + return send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, + &cmdBuff[0]); } static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg) diff --git a/frontends/stv090x.c b/frontends/stv090x.c index 60efb8b..0b0e1ed 100644 --- a/frontends/stv090x.c +++ b/frontends/stv090x.c @@ -36,6 +36,8 @@ #include "stv090x.h" #include "stv090x_priv.h" +/* Max transfer size done by I2C transfer functions */ +#define MAX_XFER_SIZE 64 #define ERRCTRL1_DVBS1 0x76 #define ERRCTRL1_DVBS2 0x67 @@ -728,8 +730,16 @@ static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 { const struct stv090x_config *config = state->config; int ret; - u8 buf[2 + count]; - struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count }; + u8 buf[MAX_XFER_SIZE]; + struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, + .buf = buf, .len = 2 + count }; + + if (2 + count > sizeof(buf)) { + printk(KERN_WARNING + "%s: i2c wr reg=%04x: len=%d is too big!\n", + KBUILD_MODNAME, reg, count); + return -EINVAL; + } buf[0] = reg >> 8; buf[1] = reg & 0xff; @@ -2144,7 +2154,7 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) u32 reg; s32 car_step, steps, cur_step, dir, freq, timeout_lock; - int lock = 0; + int lock; if (state->srate >= 10000000) timeout_lock = timeout_dmd / 3; @@ -2152,100 +2162,97 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) timeout_lock = timeout_dmd / 2; lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */ - if (!lock) { - if (state->srate >= 10000000) { - if (stv090x_chk_tmg(state)) { - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) - goto err; - lock = stv090x_get_dmdlock(state, timeout_dmd); - } else { - lock = 0; - } - } else { - if (state->srate <= 4000000) - car_step = 1000; - else if (state->srate <= 7000000) - car_step = 2000; - else if (state->srate <= 10000000) - car_step = 3000; - else - car_step = 5000; + if (lock) + return lock; - steps = (state->search_range / 1000) / car_step; - steps /= 2; - steps = 2 * (steps + 1); - if (steps < 0) - steps = 2; - else if (steps > 12) - steps = 12; - - cur_step = 1; - dir = 1; - - if (!lock) { - freq = state->frequency; - state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate; - while ((cur_step <= steps) && (!lock)) { - if (dir > 0) - freq += cur_step * car_step; - else - freq -= cur_step * car_step; - - /* Setup tuner */ - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_set_frequency) { - if (state->config->tuner_set_frequency(fe, freq) < 0) - goto err_gateoff; - } - - if (state->config->tuner_set_bandwidth) { - if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) - goto err_gateoff; - } - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - msleep(50); - - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_get_status) { - if (state->config->tuner_get_status(fe, ®) < 0) - goto err_gateoff; - } - - if (reg) - dprintk(FE_DEBUG, 1, "Tuner phase locked"); - else - dprintk(FE_DEBUG, 1, "Tuner unlocked"); - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); - if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) - goto err; - lock = stv090x_get_dmdlock(state, (timeout_dmd / 3)); - - dir *= -1; - cur_step++; - } - } + if (state->srate >= 10000000) { + if (stv090x_chk_tmg(state)) { + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) + goto err; + return stv090x_get_dmdlock(state, timeout_dmd); } + return 0; } + if (state->srate <= 4000000) + car_step = 1000; + else if (state->srate <= 7000000) + car_step = 2000; + else if (state->srate <= 10000000) + car_step = 3000; + else + car_step = 5000; + + steps = (state->search_range / 1000) / car_step; + steps /= 2; + steps = 2 * (steps + 1); + if (steps < 0) + steps = 2; + else if (steps > 12) + steps = 12; + + cur_step = 1; + dir = 1; + + freq = state->frequency; + state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate; + while ((cur_step <= steps) && (!lock)) { + if (dir > 0) + freq += cur_step * car_step; + else + freq -= cur_step * car_step; + + /* Setup tuner */ + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_set_frequency) { + if (state->config->tuner_set_frequency(fe, freq) < 0) + goto err_gateoff; + } + + if (state->config->tuner_set_bandwidth) { + if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) + goto err_gateoff; + } + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + msleep(50); + + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_get_status) { + if (state->config->tuner_get_status(fe, ®) < 0) + goto err_gateoff; + } + + if (reg) + dprintk(FE_DEBUG, 1, "Tuner phase locked"); + else + dprintk(FE_DEBUG, 1, "Tuner unlocked"); + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); + if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) + goto err; + lock = stv090x_get_dmdlock(state, (timeout_dmd / 3)); + + dir *= -1; + cur_step++; + } return lock; err_gateoff: @@ -2661,14 +2668,9 @@ static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *st return STV090x_RANGEOK; else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000)) return STV090x_RANGEOK; - else - return STV090x_OUTOFRANGE; /* Out of Range */ - } else { + } else if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) return STV090x_RANGEOK; - else - return STV090x_OUTOFRANGE; - } return STV090x_OUTOFRANGE; @@ -2787,6 +2789,12 @@ static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_mod aclc = car_loop[i].crl_pilots_off_30; } } else { /* 16APSK and 32APSK */ + /* + * This should never happen in practice, except if + * something is really wrong at the car_loop table. + */ + if (i >= 11) + i = 10; if (state->srate <= 3000000) aclc = car_loop_apsk_low[i].crl_pilots_on_2; else if (state->srate <= 7000000) @@ -3435,6 +3443,48 @@ err: return -1; } +static int stv090x_set_pls(struct stv090x_state *state, u8 pls_mode, u32 pls_code) +{ + dprintk(FE_DEBUG, 1, "Set PLS code %d (mode %d)", pls_code, pls_mode); + if (STV090x_WRITE_DEMOD(state, PLROOT2, (pls_mode << 2) | (pls_code >> 16)) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, PLROOT1, (pls_code >> 8) & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, PLROOT0, pls_code & 0xff) < 0) + goto err; + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_set_mis(struct stv090x_state *state, u32 mis) +{ + u32 reg; + + if (mis == NO_STREAM_ID_FILTER) { + dprintk(FE_DEBUG, 1, "Disable MIS filtering"); + reg = STV090x_READ_DEMOD(state, PDELCTRL1); + STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00); + if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) + goto err; + } else { + dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis); + reg = STV090x_READ_DEMOD(state, PDELCTRL1); + STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01); + if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0) + goto err; + } + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + #ifndef USE_API3 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe) #else @@ -3443,14 +3493,27 @@ static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_fron { struct stv090x_state *state = fe->demodulator_priv; struct dtv_frontend_properties *props = &fe->dtv_property_cache; - + u32 pls = 1; + #ifndef USE_API3 if (props->frequency == 0) #else return DVBFE_ALGO_SEARCH_INVALID; #endif - state->delsys = props->delivery_system; + switch (props->delivery_system) { + case SYS_DSS: + state->delsys = STV090x_DSS; + break; + case SYS_DVBS: + state->delsys = STV090x_DVBS1; + break; + case SYS_DVBS2: + state->delsys = STV090x_DVBS2; + break; + default: + return DVBFE_ALGO_SEARCH_INVALID; + } #ifndef USE_API3 state->frequency = props->frequency; state->srate = props->symbol_rate; @@ -3469,6 +3532,16 @@ static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_fron state->search_range = 5000000; } + /* Backwards compatibility to "crazy" API. + PRBS X root cannot be 0, so this should always work. */ + if ((props->stream_id != NO_STREAM_ID_FILTER) && + (props->stream_id & 0xffffff00)) + pls = props->stream_id >> 8; + if (props->pls != NO_SCRAMBLING_CODE) + pls = props->pls | 0x40000; /* props->pls is always gold code */ + stv090x_set_pls(state, (pls >> 18) & 3, pls & 0x3ffff); + stv090x_set_mis(state, props->stream_id); + if (stv090x_algo(state) == STV090x_RANGEOK) { dprintk(FE_DEBUG, 1, "Search success!"); return DVBFE_ALGO_SEARCH_SUCCESS; @@ -3585,7 +3658,6 @@ static int stv090x_read_ber(struct dvb_frontend *fe, u32 *ber) { struct stv090x_state *state = fe->demodulator_priv; struct dtv_frontend_properties *p = &fe->dtv_property_cache; - u32 reg, h, m, l; enum fe_status status; @@ -3605,6 +3677,14 @@ static int stv090x_read_ber(struct dvb_frontend *fe, u32 *ber) *ber = ((h << 16) | (m << 8) | l); } +#if 0 + p->pre_bit_error.len = 1; + p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_error.stat[0].uvalue = n; + p->pre_bit_count.len = 1; + p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_count.stat[0].uvalue = d; +#endif return 0; } @@ -3723,6 +3803,9 @@ static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength) p->strength.stat[0].uvalue = 1000 * (s64) (s32) str; #ifdef DBVALS *strength = str; + p->strength.len = 1; + p->strength.stat[0].scale = FE_SCALE_DECIBEL; + p->strength.stat[0].uvalue = 10 * (s64) str; #else *strength = (str + 100) * 0xFFFF / 100; #endif @@ -3813,7 +3896,6 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr) default: break; } - #ifdef DBVALS *cnr = cnr_db; #endif @@ -3823,7 +3905,7 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr) return 0; } -static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) +static int stv090x_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) { struct stv090x_state *state = fe->demodulator_priv; u32 reg; @@ -3921,7 +4003,8 @@ err: return -1; } -static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) +static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, + enum fe_sec_mini_cmd burst) { struct stv090x_state *state = fe->demodulator_priv; u32 reg, idle = 0, fifo_full = 1; @@ -4032,12 +4115,12 @@ static int stv090x_sleep(struct dvb_frontend *fe) reg = stv090x_read_reg(state, STV090x_TSTTNR1); STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0); if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) - goto err; + goto err_unlock; /* power off DiSEqC 1 */ reg = stv090x_read_reg(state, STV090x_TSTTNR2); STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0); if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) - goto err; + goto err_unlock; /* check whether path 2 is already sleeping, that is when ADC2 is off */ @@ -4056,7 +4139,7 @@ static int stv090x_sleep(struct dvb_frontend *fe) if (full_standby) STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) - goto err; + goto err_unlock; reg = stv090x_read_reg(state, STV090x_STOPCLK2); /* sampling 1 clock */ STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1); @@ -4067,7 +4150,7 @@ static int stv090x_sleep(struct dvb_frontend *fe) if (full_standby) STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) - goto err; + goto err_unlock; break; case STV090x_DEMODULATOR_1: @@ -4075,12 +4158,12 @@ static int stv090x_sleep(struct dvb_frontend *fe) reg = stv090x_read_reg(state, STV090x_TSTTNR3); STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0); if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) - goto err; + goto err_unlock; /* power off DiSEqC 2 */ reg = stv090x_read_reg(state, STV090x_TSTTNR4); STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0); if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) - goto err; + goto err_unlock; /* check whether path 1 is already sleeping, that is when ADC1 is off */ @@ -4099,7 +4182,7 @@ static int stv090x_sleep(struct dvb_frontend *fe) if (full_standby) STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) - goto err; + goto err_unlock; reg = stv090x_read_reg(state, STV090x_STOPCLK2); /* sampling 2 clock */ STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1); @@ -4110,7 +4193,7 @@ static int stv090x_sleep(struct dvb_frontend *fe) if (full_standby) STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) - goto err; + goto err_unlock; break; default: @@ -4123,7 +4206,7 @@ static int stv090x_sleep(struct dvb_frontend *fe) reg = stv090x_read_reg(state, STV090x_SYNTCTRL); STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01); if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) - goto err; + goto err_unlock; } mutex_unlock(&state->internal->demod_lock); @@ -4131,8 +4214,10 @@ static int stv090x_sleep(struct dvb_frontend *fe) err_gateoff: stv090x_i2c_gate_ctrl(state, 0); -err: + goto err; +err_unlock: mutex_unlock(&state->internal->demod_lock); +err: dprintk(FE_ERROR, 1, "I/O error"); return -1; } @@ -4393,7 +4478,7 @@ err: return -1; } -static int stv090x_set_tspath(struct stv090x_state *state) +static int stv0900_set_tspath(struct stv090x_state *state) { u32 reg; @@ -4643,8 +4728,6 @@ static int stv090x_set_tspath(struct stv090x_state *state) } - printk("TSCFGH resets\n"); - reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) @@ -4667,6 +4750,121 @@ err: return -1; } +static int stv0903_set_tspath(struct stv090x_state *state) +{ + u32 reg; + + if (state->internal->dev_ver >= 0x20) { + switch (state->config->ts1_mode) { + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); + break; + + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + default: + stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c); + break; + } + } else { + switch (state->config->ts1_mode) { + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); + break; + + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + default: + stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); + break; + } + } + + switch (state->config->ts1_mode) { + case STV090x_TSMODE_PARALLEL_PUNCTURED: + reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + break; + + case STV090x_TSMODE_DVBCI: + reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + break; + + case STV090x_TSMODE_SERIAL_PUNCTURED: + reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + break; + + case STV090x_TSMODE_SERIAL_CONTINUOUS: + reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + break; + + default: + break; + } + + if (state->config->ts1_clk > 0) { + u32 speed; + + switch (state->config->ts1_mode) { + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + default: + speed = state->internal->mclk / + (state->config->ts1_clk / 4); + if (speed < 0x08) + speed = 0x08; + if (speed > 0xFF) + speed = 0xFF; + break; + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + speed = state->internal->mclk / + (state->config->ts1_clk / 32); + if (speed < 0x20) + speed = 0x20; + if (speed > 0xFF) + speed = 0xFF; + break; + } + reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); + STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); + if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) + goto err; + } + + reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); + STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + static int stv090x_init(struct dvb_frontend *fe) { struct stv090x_state *state = fe->demodulator_priv; @@ -4730,8 +4928,13 @@ static int stv090x_init(struct dvb_frontend *fe) goto err; #if 0 - if (stv090x_set_tspath(state) < 0) - goto err; + if (state->device == STV0900) { + if (stv0900_set_tspath(state) < 0) + goto err; + } else { + if (stv0903_set_tspath(state) < 0) + goto err; + } #endif return 0; @@ -4772,23 +4975,26 @@ static int stv090x_setup(struct dvb_frontend *fe) /* Stop Demod */ if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0) goto err; - if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0) - goto err; + if (state->device == STV0900) + if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0) + goto err; msleep(5); /* Set No Tuner Mode */ if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0) goto err; - if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0) - goto err; + if (state->device == STV0900) + if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0) + goto err; /* I2C repeater OFF */ STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level); if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0) goto err; - if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) - goto err; + if (state->device == STV0900) + if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) + goto err; if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */ goto err; @@ -4848,8 +5054,13 @@ static int stv090x_setup(struct dvb_frontend *fe) if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0) goto err; - if (stv090x_set_tspath(state) < 0) - goto err; + if (state->device == STV0900) { + if (stv0900_set_tspath(state) < 0) + goto err; + } else { + if (stv0903_set_tspath(state) < 0) + goto err; + } return 0; err: @@ -4857,8 +5068,8 @@ err: return -1; } -int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, u8 value, - u8 xor_value) +static int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, + u8 value, u8 xor_value) { struct stv090x_state *state = fe->demodulator_priv; u8 reg = 0; @@ -4869,7 +5080,69 @@ int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, u8 value, return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg); } -EXPORT_SYMBOL(stv090x_set_gpio); + +static int stv090x_get_frontend(struct dvb_frontend *fe) +{ + struct stv090x_state *state = fe->demodulator_priv; + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + u8 tmp; + u32 reg = 0; + + if (state->rec_mode == 2) { + u32 mc; + enum fe_modulation modcod2mod[0x20] = { + QPSK, QPSK, QPSK, QPSK, + QPSK, QPSK, QPSK, QPSK, + QPSK, QPSK, QPSK, QPSK, + PSK_8, PSK_8, PSK_8, PSK_8, + PSK_8, PSK_8, APSK_16, APSK_16, + APSK_16, APSK_16, APSK_16, APSK_16, + APSK_32, APSK_32, APSK_32, APSK_32, + APSK_32, + }; + enum fe_code_rate modcod2fec[0x20] = { + FEC_NONE, FEC_1_4, FEC_1_3, FEC_2_5, + FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4, + FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10, + FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6, + FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4, + FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10, + FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9, + FEC_9_10 + }; + mc = state->modcod; + p->pilot = (state->pilots & 0x01) ? PILOT_ON : PILOT_OFF; + p->modulation = modcod2mod[mc]; + p->fec_inner = modcod2fec[mc]; + } else if (state->rec_mode == 1) { + reg = STV090x_READ_DEMOD(state, VITCURPUN); + switch( reg & 0x1F ) { + case 0x0d: + p->fec_inner = FEC_1_2; + break; + case 0x12: + p->fec_inner = FEC_2_3; + break; + case 0x15: + p->fec_inner = FEC_3_4; + break; + case 0x18: + p->fec_inner = FEC_5_6; + break; + case 0x1a: + p->fec_inner = FEC_7_8; + break; + default: + p->fec_inner = FEC_NONE; + break; + } + p->rolloff = ROLLOFF_35; + } else { + + } + + return 0; +} static int get_frontend(struct dvb_frontend *fe) { @@ -4960,7 +5233,7 @@ static struct dvb_frontend_ops stv090x_ops = { .sleep = stv090x_sleep, .get_frontend_algo = stv090x_frontend_algo, - .get_frontend = get_frontend, + .get_frontend = stv090x_get_frontend, .diseqc_send_master_cmd = stv090x_send_diseqc_msg, .diseqc_send_burst = stv090x_send_diseqc_burst, @@ -4976,7 +5249,7 @@ static struct dvb_frontend_ops stv090x_ops = { }; -struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, +struct dvb_frontend *stv090x_attach(struct stv090x_config *config, struct i2c_adapter *i2c, enum stv090x_demodulator demod) { @@ -5030,10 +5303,15 @@ struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, } } + if (state->internal->dev_ver >= 0x30) + state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM; + /* workaround for stuck DiSEqC output */ if (config->diseqc_envelope_mode) stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A); + config->set_gpio = stv090x_set_gpio; + dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x", state->device == STV0900 ? "STV0900" : "STV0903", demod, diff --git a/frontends/stv090x.h b/frontends/stv090x.h index 29cdc2b..e529b85 100644 --- a/frontends/stv090x.h +++ b/frontends/stv090x.h @@ -101,18 +101,18 @@ struct stv090x_config { int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk); int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status); void (*tuner_i2c_lock) (struct dvb_frontend *fe, int lock); + + /* dir = 0 -> output, dir = 1 -> input/open-drain */ + int (*set_gpio)(struct dvb_frontend *fe, u8 gpio, u8 dir, u8 value, + u8 xor_value); }; #if defined(CONFIG_DVB_STV090x) || (defined(CONFIG_DVB_STV090x_MODULE) && defined(MODULE)) -extern struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, +extern struct dvb_frontend *stv090x_attach(struct stv090x_config *config, struct i2c_adapter *i2c, enum stv090x_demodulator demod); -/* dir = 0 -> output, dir = 1 -> input/open-drain */ -extern int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, - u8 dir, u8 value, u8 xor_value); - #else static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, @@ -123,12 +123,6 @@ static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *c return NULL; } -static inline int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, - u8 opd, u8 value, u8 xor_value) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return -ENODEV; -} #endif /* CONFIG_DVB_STV090x */ #endif /* __STV090x_H */ diff --git a/frontends/stv0910.c b/frontends/stv0910.c index a7052dc..fc725c8 100644 --- a/frontends/stv0910.c +++ b/frontends/stv0910.c @@ -1,7 +1,7 @@ /* * Driver for the ST STV0910 DVB-S/S2 demodulator. * - * Copyright (C) 2014-2015 Ralph Metzler + * Copyright (C) 2014-2016 Ralph Metzler * Marcus Metzler * developed for Digital Devices GmbH * @@ -38,6 +38,7 @@ #include "stv0910_regs.h" +#define EXT_CLOCK 30000000 #define TUNING_DELAY 200 #define BER_SRC_S 0x20 #define BER_SRC_S2 0x20 @@ -123,9 +124,17 @@ struct stv { u32 Pilots; enum FE_STV0910_RollOff FERollOff; + int isStandardBroadcast; + int isVCM; + + u32 CurScramblingCode; + u32 ScramblingCode; + u32 LastBERNumerator; u32 LastBERDenominator; u8 BERScale; + + u8 VTH[6]; }; struct SInitTable { @@ -193,6 +202,19 @@ static int read_regs(struct stv *state, u16 reg, u8 *val, int len) reg, val, len); } +static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val) +{ + int status; + u8 tmp; + + mutex_lock(&state->base->reg_lock); + status = read_reg(state, reg, &tmp); + if (!status) + status = write_reg(state, reg, (tmp & ~mask) | (val & mask)); + mutex_unlock(&state->base->reg_lock); + return status; +} + struct SLookup S1_SN_Lookup[] = { { 0, 9242 }, /*C/N= 0dB*/ { 05, 9105 }, /*C/N=0.5dB*/ @@ -452,24 +474,45 @@ static int GetCurSymbolRate(struct stv *state, u32 *pSymbolRate) static int GetSignalParameters(struct stv *state) { + u8 tmp; + if (!state->Started) return -1; - + if (state->ReceiveMode == Mode_DVBS2) { - u8 tmp; - u8 rolloff; - read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); state->ModCod = (enum FE_STV0910_ModCod) ((tmp & 0x7c) >> 2); state->Pilots = (tmp & 0x01) != 0; state->FECType = (enum DVBS2_FECType) ((tmp & 0x02) >> 1); +#if 0 read_reg(state, RSTV0910_P2_TMGOBS + state->regoff, &rolloff); rolloff = rolloff >> 6; state->FERollOff = (enum FE_STV0910_RollOff) rolloff; - +#endif } else if (state->ReceiveMode == Mode_DVBS) { - /* todo */ + read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); + state->PunctureRate = FEC_NONE; + switch (tmp & 0x1F) { + case 0x0d: + state->PunctureRate = FEC_1_2; + break; + case 0x12: + state->PunctureRate = FEC_2_3; + break; + case 0x15: + state->PunctureRate = FEC_3_4; + break; + case 0x18: + state->PunctureRate = FEC_5_6; + break; + case 0x1A: + state->PunctureRate = FEC_7_8; + break; + } + state->isVCM = 0; + state->isStandardBroadcast = 1; + state->FERollOff = FE_SAT_35; } return 0; } @@ -485,18 +528,20 @@ static int TrackingOptimization(struct stv *state) switch (state->ReceiveMode) { case Mode_DVBS: - tmp |= 0x40; break; + tmp |= 0x40; + break; case Mode_DVBS2: - tmp |= 0x80; break; + tmp |= 0x80; + break; default: - tmp |= 0xC0; break; + tmp |= 0xC0; + break; } write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); if (state->ReceiveMode == Mode_DVBS2) { - /* force to PRE BCH Rate */ - write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, - BER_SRC_S2 | state->BERScale); + /*Disable Reed-Solomon */ + write_shared_reg(state, RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x03); if (state->FECType == DVBS2_64K) { u8 aclc = get_optim_cloop(state, state->ModCod, @@ -523,29 +568,6 @@ static int TrackingOptimization(struct stv *state) } } } - if (state->ReceiveMode == Mode_DVBS) { - u8 tmp; - - read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); - state->PunctureRate = FEC_NONE; - switch (tmp & 0x1F) { - case 0x0d: - state->PunctureRate = FEC_1_2; - break; - case 0x12: - state->PunctureRate = FEC_2_3; - break; - case 0x15: - state->PunctureRate = FEC_3_4; - break; - case 0x18: - state->PunctureRate = FEC_5_6; - break; - case 0x1A: - state->PunctureRate = FEC_7_8; - break; - } - } return 0; } @@ -558,7 +580,7 @@ static s32 TableLookup(struct SLookup *Table, int i; s32 RegDiff; - // Assumes Table[0].RegValue > Table[imax].RegValue + /* Assumes Table[0].RegValue > Table[imax].RegValue */ if( RegValue >= Table[0].RegValue ) Value = Table[0].Value; else if( RegValue <= Table[imax].RegValue ) @@ -686,11 +708,12 @@ static u32 DVBS2_nBCH(enum DVBS2_ModCod ModCod, enum DVBS2_FECType FECType) return 64800; } -static int GetBitErrorRateS2(struct stv *state, u32 *BERNumerator, +static int GetBitErrorRateS2(struct stv *state, + u32 *BERNumerator, u32 *BERDenominator) { u8 Regs[3]; - + int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff, Regs, 3); @@ -828,12 +851,118 @@ static int Stop(struct stv *state) } +static int init_search_param(struct stv *state) +{ + u8 tmp; + + read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp); + tmp |= 0x20; // Filter_en (no effect if SIS=non-MIS + write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); + + read_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, &tmp); + tmp &= ~0x02; // frame mode = 0 + write_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, tmp); + + write_reg(state, RSTV0910_P2_UPLCCST0 + state->regoff, 0xe0); + write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0x00); + + read_reg(state, RSTV0910_P2_TSSTATEM + state->regoff, &tmp); + tmp &= ~0x01; // nosync = 0, in case next signal is standard TS + write_reg(state, RSTV0910_P2_TSSTATEM + state->regoff, tmp); + + read_reg(state, RSTV0910_P2_TSCFGL + state->regoff, &tmp); + tmp &= ~0x04; // embindvb = 0 + write_reg(state, RSTV0910_P2_TSCFGL + state->regoff, tmp); + + read_reg(state, RSTV0910_P2_TSINSDELH + state->regoff, &tmp); + tmp &= ~0x80; // syncbyte = 0 + write_reg(state, RSTV0910_P2_TSINSDELH + state->regoff, tmp); + + read_reg(state, RSTV0910_P2_TSINSDELM + state->regoff, &tmp); + tmp &= ~0x08; // token = 0 + write_reg(state, RSTV0910_P2_TSINSDELM + state->regoff, tmp); + + read_reg(state, RSTV0910_P2_TSDLYSET2 + state->regoff, &tmp); + tmp &= ~0x30; // hysteresis threshold = 0 + write_reg(state, RSTV0910_P2_TSDLYSET2 + state->regoff, tmp); + + read_reg(state, RSTV0910_P2_PDELCTRL0 + state->regoff, &tmp); + tmp = (tmp & ~0x30) | 0x10; // isi obs mode = 1, observe min ISI + write_reg(state, RSTV0910_P2_PDELCTRL0 + state->regoff, tmp); + + return 0; +} + +static int EnablePunctureRate(struct stv *state, enum fe_code_rate rate) +{ + switch(rate) { + case FEC_1_2: + return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x01); + case FEC_2_3: + return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x02); + case FEC_3_4: + return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x04); + case FEC_5_6: + return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x08); + case FEC_7_8: + return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x20); + case FEC_NONE: + default: + return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2f); + } +} + +static int set_vth_default(struct stv *state) +{ + state->VTH[0] = 0xd7; + state->VTH[1] = 0x85; + state->VTH[2] = 0x58; + state->VTH[3] = 0x3a; + state->VTH[4] = 0x34; + state->VTH[5] = 0x28; + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->VTH[0]); + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->VTH[1]); + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->VTH[2]); + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->VTH[3]); + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->VTH[4]); + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->VTH[5]); + return 0; +} + +static int set_vth(struct stv *state) +{ + static struct SLookup VTHLookupTable[] = { + {250, 8780}, /*C/N=1.5dB*/ + {100, 7405}, /*C/N=4.5dB*/ + {40, 6330}, /*C/N=6.5dB*/ + {12, 5224}, /*C/N=8.5dB*/ + {5, 4236} /*C/N=10.5dB*/ + }; + int i; + u8 tmp[2]; + int status = read_regs(state, RSTV0910_P2_NNOSDATAT1 + state->regoff, tmp, 2); + u16 RegValue = (tmp[0] << 8) | tmp[1]; + s32 vth = TableLookup(VTHLookupTable, ARRAY_SIZE(VTHLookupTable), RegValue); + + for (i = 0; i < 6; i += 1) + if (state->VTH[i] > vth) + state->VTH[i] = vth; + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->VTH[0]); + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->VTH[1]); + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->VTH[2]); + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->VTH[3]); + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->VTH[4]); + write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->VTH[5]); + return status; +} + static int Start(struct stv *state, struct dtv_frontend_properties *p) { s32 Freq; u8 regDMDCFGMD; u16 symb; - + u32 ScramblingCode = 1; + if (p->symbol_rate < 100000 || p->symbol_rate > 70000000) return -EINVAL; @@ -844,6 +973,34 @@ static int Start(struct stv *state, struct dtv_frontend_properties *p) if (state->Started) write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); + init_search_param(state); + + if (p->stream_id != NO_STREAM_ID_FILTER) { + /* Backwards compatibility to "crazy" API. + PRBS X root cannot be 0, so this should always work. + */ + if (p->stream_id & 0xffffff00) + ScramblingCode = p->stream_id >> 8; + write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, p->stream_id & 0xff); + write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff); + //pr_info("ID=%08x\n", p->stream_id & 0xff); + } + + /* props->pls is always gold code ! */ + if (p->pls != NO_SCRAMBLING_CODE) + ScramblingCode = p->pls | 0x40000; + + if (ScramblingCode != state->CurScramblingCode) { + write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, + ScramblingCode & 0xff); + write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, + (ScramblingCode >> 8) & 0xff); + write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, + (ScramblingCode >> 16) & 0x07); + state->CurScramblingCode = ScramblingCode; + //pr_info("PLS=%08x\n", ScramblingCode); + } + if (p->symbol_rate <= 1000000) { /*SR <=1Msps*/ state->DemodTimeout = 3000; state->FecTimeout = 2000; @@ -852,7 +1009,7 @@ static int Start(struct stv *state, struct dtv_frontend_properties *p) state->FecTimeout = 1300; } else if (p->symbol_rate <= 5000000) { /*2Msps< SR <=5Msps*/ state->DemodTimeout = 1000; - state->FecTimeout = 650; + state->FecTimeout = 650; } else if (p->symbol_rate <= 10000000) { /*5Msps< SR <=10Msps*/ state->DemodTimeout = 700; state->FecTimeout = 350; @@ -879,25 +1036,43 @@ static int Start(struct stv *state, struct dtv_frontend_properties *p) read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®DMDCFGMD); write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, regDMDCFGMD |= 0xC0); - + write_shared_reg(state, RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00); + /* Disable DSS */ write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); + EnablePunctureRate(state, FEC_NONE); + /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA*/ write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); - /* Reset demod */ + write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79); + + write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29); + write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09); + write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84); + write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84); + + /* Reset CAR3, bug DVBS2->DVBS1 lock*/ + /* Note: The bit is only pulsed -> no lock on shared register needed */ + write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08); + write_reg(state, RSTV0910_TSTRES0, 0); + + set_vth_default(state); + + /* Reset demod */ write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); - Freq = (state->SearchRange / 2000) + 600; if (p->symbol_rate <= 5000000) - Freq -= (600 + 80); + Freq = (state->SearchRange / 2000) + 80; + else + Freq = (state->SearchRange / 2000) + 1600; Freq = (Freq << 16) / (state->base->mclk / 1000); write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff, @@ -955,19 +1130,29 @@ static int probe(struct stv *state) /* Configure the I2C repeater to off */ write_reg(state, RSTV0910_P2_I2CRPT, 0x24); /* Set the I2C to oversampling ratio */ - write_reg(state, RSTV0910_I2CCFG, 0x88); + write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */ write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */ - write_reg(state, RSTV0910_PADCFG, 0x05); /* RF AGC Pads Dev = 05 */ + write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */ write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */ write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */ write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */ write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */ - + write_reg(state, RSTV0910_P1_CAR3CFG, 0x02); + write_reg(state, RSTV0910_P2_CAR3CFG, 0x02); + write_reg(state, RSTV0910_P1_DMDCFG4, 0x04); + write_reg(state, RSTV0910_P2_DMDCFG4, 0x04); + write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */ write_reg(state, RSTV0910_TSTRES0, 0x00); + write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00); + write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00); + + write_reg(state, RSTV0910_P1_TMGCFG2, 0x80); + write_reg(state, RSTV0910_P2_TMGCFG2, 0x80); + set_mclock(state, 135000000); /* TS output */ @@ -1054,12 +1239,31 @@ static int set_parameters(struct dvb_frontend *fe) return stat; } +static int get_frequency_offset(struct stv *state, s32 *off) +{ + u8 cfr0, cfr1, cfr2; + s32 derot; + + read_reg(state, RSTV0910_P2_CFR2 + state->regoff, &cfr2); + read_reg(state, RSTV0910_P2_CFR1 + state->regoff, &cfr1); + read_reg(state, RSTV0910_P2_CFR0 + state->regoff, &cfr0); + + derot = ((u32) cfr2 << 16) | ((u32)cfr1 << 8) | cfr0; + if (derot & (1<<23)) + derot |= 0xFF000000; + *off = - (s32) (((s64) derot * (s64) state->base->mclk) >> 24); + //pr_info("foff = %d\n", *off); + return 0; +} + + static int get_frontend(struct dvb_frontend *fe) { struct stv *state = fe->demodulator_priv; struct dtv_frontend_properties *p = &fe->dtv_property_cache; u8 tmp; + if (state->ReceiveMode == Mode_DVBS2) { u32 mc; enum fe_modulation modcod2mod[0x20] = { @@ -1118,6 +1322,28 @@ static int get_frontend(struct dvb_frontend *fe) } +static int ManageMatypeInfo(struct stv *state) +{ + if (!state->Started) + return -1; + if (state->ReceiveMode == Mode_DVBS2 ) { + u8 BBHeader[2]; + + read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff, + BBHeader, 2); + state->FERollOff = + (enum FE_STV0910_RollOff) (BBHeader[0] & 0x03); + state->isVCM = (BBHeader[0] & 0x10) == 0; + state->isStandardBroadcast = (BBHeader[0] & 0xFC) == 0xF0; + } else if (state->ReceiveMode == Mode_DVBS) { + state->isVCM = 0; + state->isStandardBroadcast = 1; + state->FERollOff = FE_SAT_35; + } + return 0; +} + + static int read_snr(struct dvb_frontend *fe, u16 *snr); static int read_signal_strength(struct dvb_frontend *fe, u16 *strength); static int read_ber(struct dvb_frontend *fe, u32 *ber); @@ -1125,13 +1351,15 @@ static int read_ber(struct dvb_frontend *fe, u32 *ber); static int read_status(struct dvb_frontend *fe, fe_status_t *status) { struct stv *state = fe->demodulator_priv; - struct dtv_frontend_properties *p = &fe->dtv_property_cache; u8 DmdState = 0; u8 DStatus = 0; enum ReceiveMode CurReceiveMode = Mode_None; u32 FECLock = 0; u16 val; u32 ber; + s32 foff; + + get_frequency_offset(state, &foff); read_signal_strength(fe, &val); @@ -1140,24 +1368,42 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status) read_ber(fe, &ber); read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &DmdState); - if (DmdState & 0x40) { - read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &DStatus); + read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, + &DStatus); if (DStatus & 0x08) CurReceiveMode = (DmdState & 0x20) ? Mode_DVBS : Mode_DVBS2; } if (CurReceiveMode == Mode_None) { + set_vth(state); + //if( Time >= m_DemodTimeout ) *pLockStatus = NEVER_LOCK; *status = 0; return 0; } - *status |= 0x0f; if (state->ReceiveMode == Mode_None) { state->ReceiveMode = CurReceiveMode; state->DemodLockTime = jiffies; state->FirstTimeLock = 1; + GetSignalParameters(state); + TrackingOptimization(state); + +#if 0 + if( CurReceiveMode == Mode_DVBS2 && m_bPilots + && ( m_ModCod == FE_8PSK_23 || m_ModCod == FE_8PSK_35) ) + { + LONG C_N; + CHK_ERROR(GetSignalToNoise(&C_N)); + if( C_N < 80 ) + { + CHK_ERROR(WriteReg(RSTV0910_P2_CARHDR + m_DemodOffset , 0x04)); + CHK_ERROR(WriteReg(RSTV0910_P2_BCLC2S28 + m_DemodOffset , 0x31)); + } + } +#endif + write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, state->tscfgh); usleep_range(3000, 4000); @@ -1183,6 +1429,7 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status) } if (!FECLock) + //if( Time >= m_DemodLockTime + m_FecTimeout ) *pLockStatus = NEVER_LOCK; return 0; *status |= 0x10; @@ -1191,10 +1438,23 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status) u8 tmp; state->FirstTimeLock = 0; - GetSignalParameters(state); - if (state->ReceiveMode == Mode_DVBS2) { - /* FSTV0910_P2_MANUALSX_ROLLOFF, + ManageMatypeInfo(state); + +#if 0 + ULONG Bitrate; + CSTV0910::GetBitrate(&Bitrate); + BYTE newTSSPEED = (Bitrate > 67000000) ? 0x30 : 0x40; + if (newTSSPEED != m_TSSPEED) + { + KdPrintEx((MSG_INFO "_%d " __FUNCTION__ " TSSPEED = %02X\n", m_Instance, newTSSPEED)); + CHK_ERROR(WriteReg(RSTV0910_P2_TSSPEED + m_DemodOffset, newTSSPEED)); + m_TSSPEED = newTSSPEED; + } + +#endif + if (state->ReceiveMode == Mode_DVBS2) { + /* FSTV0910_P2_MANUALSX_ROLLOFF, FSTV0910_P2_MANUALS2_ROLLOFF = 0 */ state->DEMOD &= ~0x84; write_reg(state, RSTV0910_P2_DEMOD + state->regoff, @@ -1203,11 +1463,13 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status) &tmp); /*reset DVBS2 packet delinator error counter */ tmp |= 0x40; - write_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, + write_reg(state, RSTV0910_P2_PDELCTRL2 + + state->regoff, tmp); /*reset DVBS2 packet delinator error counter */ tmp &= ~0x40; - write_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, + write_reg(state, RSTV0910_P2_PDELCTRL2 + + state->regoff, tmp); state->BERScale = 2; @@ -1230,8 +1492,25 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status) infinit error count mode )*/ write_reg(state, RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); - TrackingOptimization(state); + set_vth_default(state); + if (state->ReceiveMode == Mode_DVBS) + EnablePunctureRate(state, state->PunctureRate); } + +#if 0 + if( m_isVCM ) + { + // Use highest signaled ModCod for quality + BYTE tmp; + CHK_ERROR(ReadReg(RSTV0910_P2_DMDMODCOD + + m_DemodOffset,&tmp)); + FE_STV0910_ModCod ModCod = + FE_STV0910_ModCod((tmp & 0x7c) >> 2); + + if( ModCod > m_ModCod ) + m_ModCod = ModCod; + } +#endif return 0; } @@ -1439,24 +1718,21 @@ static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) { struct stv *state = fe->demodulator_priv; struct dtv_frontend_properties *p = &fe->dtv_property_cache; - u8 Agc1, Agc0; u8 Reg[2]; s32 bbgain; s32 Power = 0; int i; read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, Reg, 2); - //KdPrintEx((MSG_INFO "_%d " __FUNCTION__ " AGCIQIN1 = %02x%02x\n",m_Instance,Reg[0],Reg[1])); - *strength = (((u32) Reg[0]) << 8) | Reg[1]; for (i = 0; i < 5; i += 1) { read_regs(state, RSTV0910_P2_POWERI + state->regoff, Reg, 2); - Power += (u32) Reg[0] * (u32) Reg[0] + (u32) Reg[1] * (u32) Reg[1]; + Power += (u32) Reg[0] * (u32) Reg[0] + + (u32) Reg[1] * (u32) Reg[1]; msleep(3); } Power /= 5; - bbgain = (465 - Log10x100(Power)) * 10; if (fe->ops.tuner_ops.get_rf_strength) @@ -1464,7 +1740,6 @@ static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) else *strength = 0; - printk("pwr = %d bb = %d str = %u\n", Power, bbgain, *strength); if (bbgain < (s32) *strength) *strength -= bbgain; else @@ -1473,7 +1748,8 @@ static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) p->strength.len = 1; p->strength.stat[0].scale = FE_SCALE_DECIBEL; p->strength.stat[0].uvalue = 10 * (s64) (s16) *strength - 108750; - + + /* *strength is in hundredth dBuv, uvalue is in thousandth dBm */ return 0; } @@ -1550,6 +1826,7 @@ struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c, state->SearchRange = 16000000; state->DEMOD = 0x10; /* Inversion : Auto with reset to 0 */ state->ReceiveMode = Mode_None; + state->CurScramblingCode = NO_SCRAMBLING_CODE; base = match_base(i2c, cfg->adr); if (base) { @@ -1586,5 +1863,5 @@ fail: EXPORT_SYMBOL_GPL(stv0910_attach); MODULE_DESCRIPTION("STV0910 driver"); -MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); +MODULE_AUTHOR("Ralph und Marcus Metzler, Manfred Voelkel"); MODULE_LICENSE("GPL"); diff --git a/frontends/stv0910_regs.h b/frontends/stv0910_regs.h index 305f5da..e921937 100644 --- a/frontends/stv0910_regs.h +++ b/frontends/stv0910_regs.h @@ -2,7 +2,7 @@ // Author Manfred Völkel, August 2013 // (c) 2013 Digital Devices GmbH Germany. All rights reserved -// $Id: DD_STV0910Register.h 504 2013-09-02 23:02:14Z manfred $ +// $Id: DD_STV0910Register.h 627 2015-11-23 11:51:14Z manfred $ /* ======================================================================= -- Registers Declaration (Internal ST, All Applications ) @@ -51,7 +51,6 @@ /*OUTCFG*/ #define RSTV0910_OUTCFG 0xf11c -#define FSTV0910_INV_DATA6 0xf11c0080 #define FSTV0910_TS2_OUTSER_HZ 0xf11c0020 #define FSTV0910_TS1_OUTSER_HZ 0xf11c0010 #define FSTV0910_TS2_OUTPAR_HZ 0xf11c0008 @@ -93,9 +92,7 @@ #define FSTV0910_SDEMOD_LOCK_1 0xf1230040 #define FSTV0910_SDEMOD_IRQ_1 0xf1230020 #define FSTV0910_SBCH_ERRFLAG 0xf1230010 -#define FSTV0910_SECW2_IRQ 0xf1230008 #define FSTV0910_SDISEQC2_IRQ 0xf1230004 -#define FSTV0910_SECW1_IRQ 0xf1230002 #define FSTV0910_SDISEQC1_IRQ 0xf1230001 /*IRQMASK3*/ @@ -133,18 +130,12 @@ #define FSTV0910_MDEMOD_LOCK_1 0xf1270040 #define FSTV0910_MDEMOD_IRQ_1 0xf1270020 #define FSTV0910_MBCH_ERRFLAG 0xf1270010 -#define FSTV0910_MECW2_IRQ 0xf1270008 #define FSTV0910_MDISEQC2_IRQ 0xf1270004 -#define FSTV0910_MECW1_IRQ 0xf1270002 #define FSTV0910_MDISEQC1_IRQ 0xf1270001 /*I2CCFG*/ #define RSTV0910_I2CCFG 0xf129 -#define FSTV0910_I2C2_FASTMODE 0xf1290080 -#define FSTV0910_STATUS_WR2 0xf1290040 -#define FSTV0910_I2C2ADDR_INC 0xf1290030 #define FSTV0910_I2C_FASTMODE 0xf1290008 -#define FSTV0910_STATUS_WR 0xf1290004 #define FSTV0910_I2CADDR_INC 0xf1290003 /*P1_I2CRPT*/ @@ -460,7 +451,6 @@ /*PLLSTAT*/ #define RSTV0910_PLLSTAT 0xf1b8 -#define FSTV0910_PLL_BIST_END 0xf1b80004 #define FSTV0910_PLLLOCK 0xf1b80001 /*STOPCLK1*/ @@ -484,29 +474,18 @@ /*TSTTNR0*/ #define RSTV0910_TSTTNR0 0xf1df #define FSTV0910_FSK_PON 0xf1df0004 -#define FSTV0910_FSK_OPENLOOP 0xf1df0002 /*TSTTNR1*/ #define RSTV0910_TSTTNR1 0xf1e0 -#define FSTV0910_BYPASS_ADC1 0xf1e00080 -#define FSTV0910_INVADC1_CKOUT 0xf1e00040 -#define FSTV0910_SELIQSRC1 0xf1e00030 -#define FSTV0910_DEMOD2_SELADC 0xf1e00008 -#define FSTV0910_DEMOD1_SELADC 0xf1e00004 #define FSTV0910_ADC1_PON 0xf1e00002 /*TSTTNR2*/ #define RSTV0910_TSTTNR2 0xf1e1 -#define FSTV0910_I2C_DISEQC_BYPASS 0xf1e10080 -#define FSTV0910_I2C_DISEQC_ENCH 0xf1e10040 #define FSTV0910_I2C_DISEQC_PON 0xf1e10020 #define FSTV0910_DISEQC_CLKDIV 0xf1e1000f /*TSTTNR3*/ #define RSTV0910_TSTTNR3 0xf1e2 -#define FSTV0910_BYPASS_ADC2 0xf1e20080 -#define FSTV0910_INVADC2_CKOUT 0xf1e20040 -#define FSTV0910_SELIQSRC2 0xf1e20030 #define FSTV0910_ADC2_PON 0xf1e20002 /*P2_IQCONST*/ @@ -516,8 +495,6 @@ /*P2_NOSCFG*/ #define RSTV0910_P2_NOSCFG 0xf201 -#define FSTV0910_P2_DIS_ACMRATIO 0xf2010080 -#define FSTV0910_P2_NOSIN_EGALSEL 0xf2010040 #define FSTV0910_P2_DUMMYPL_NOSDATA 0xf2010020 #define FSTV0910_P2_NOSPLH_BETA 0xf2010018 #define FSTV0910_P2_NOSDATA_BETA 0xf2010007 @@ -538,14 +515,10 @@ #define FSTV0910_P2_AMM_CORRECT 0xf2040010 #define FSTV0910_P2_QUAD_FROZEN 0xf2040008 #define FSTV0910_P2_QUAD_CORRECT 0xf2040004 -#define FSTV0910_P2_DCCOMP_SLOW 0xf2040002 -#define FSTV0910_P2_IQMISM_SLOW 0xf2040001 /*P2_AGC1CN*/ #define RSTV0910_P2_AGC1CN 0xf206 #define FSTV0910_P2_AGC1_LOCKED 0xf2060080 -#define FSTV0910_P2_AGC1_OVERFLOW 0xf2060040 -#define FSTV0910_P2_AGC1_NOSLOWLK 0xf2060020 #define FSTV0910_P2_AGC1_MINPOWER 0xf2060010 #define FSTV0910_P2_AGCOUT_FAST 0xf2060008 #define FSTV0910_P2_AGCIQ_BETA 0xf2060007 @@ -603,16 +576,12 @@ #define RSTV0910_P2_DSTATUS 0xf212 #define FSTV0910_P2_CAR_LOCK 0xf2120080 #define FSTV0910_P2_TMGLOCK_QUALITY 0xf2120060 -#define FSTV0910_P2_SDVBS1_ENABLE 0xf2120010 #define FSTV0910_P2_LOCK_DEFINITIF 0xf2120008 -#define FSTV0910_P2_TIMING_IS_LOCKED 0xf2120004 -#define FSTV0910_P2_DEMOD_SYSCFG 0xf2120002 #define FSTV0910_P2_OVADC_DETECT 0xf2120001 /*P2_DSTATUS2*/ #define RSTV0910_P2_DSTATUS2 0xf213 #define FSTV0910_P2_DEMOD_DELOCK 0xf2130080 -#define FSTV0910_P2_DEMOD_TIMEOUT 0xf2130040 #define FSTV0910_P2_MODCODRQ_SYNCTAG 0xf2130020 #define FSTV0910_P2_POLYPH_SATEVENT 0xf2130010 #define FSTV0910_P2_AGC1_NOSIGNALACK 0xf2130008 @@ -626,25 +595,16 @@ #define FSTV0910_P2_DVBS1_ENABLE 0xf2140040 #define FSTV0910_P2_SCAN_ENABLE 0xf2140010 #define FSTV0910_P2_CFR_AUTOSCAN 0xf2140008 -#define FSTV0910_P2_NOFORCE_RELOCK 0xf2140004 #define FSTV0910_P2_TUN_RNG 0xf2140003 /*P2_DMDCFG2*/ #define RSTV0910_P2_DMDCFG2 0xf215 -#define FSTV0910_P2_AGC1_WAITLOCK 0xf2150080 #define FSTV0910_P2_S1S2_SEQUENTIAL 0xf2150040 -#define FSTV0910_P2_BLINDPEA_MODE 0xf2150020 #define FSTV0910_P2_INFINITE_RELOCK 0xf2150010 -#define FSTV0910_P2_BWOFFSET_COLDWARM 0xf2150008 -#define FSTV0910_P2_TMGLOCK_NSCANSTOP 0xf2150004 -#define FSTV0910_P2_COARSE_LK3MODE 0xf2150002 -#define FSTV0910_P2_COARSE_LK2MODE 0xf2150001 /*P2_DMDISTATE*/ #define RSTV0910_P2_DMDISTATE 0xf216 #define FSTV0910_P2_I2C_NORESETDMODE 0xf2160080 -#define FSTV0910_P2_FORCE_ETAPED 0xf2160040 -#define FSTV0910_P2_SDMDRST_DIRCLK 0xf2160020 #define FSTV0910_P2_I2C_DEMOD_MODE 0xf216001f /*P2_DMDT0M*/ @@ -653,9 +613,7 @@ /*P2_DMDSTATE*/ #define RSTV0910_P2_DMDSTATE 0xf21b -#define FSTV0910_P2_DEMOD_LOCKED 0xf21b0080 #define FSTV0910_P2_HEADER_MODE 0xf21b0060 -#define FSTV0910_P2_DEMOD_MODE 0xf21b001f /*P2_DMDFLYW*/ #define RSTV0910_P2_DMDFLYW 0xf21c @@ -667,29 +625,15 @@ #define FSTV0910_P2_CFR_ZIGZAG 0xf21d0080 #define FSTV0910_P2_DEMOD_CFGMODE 0xf21d0060 #define FSTV0910_P2_GAMMA_LOWBAUDRATE 0xf21d0010 -#define FSTV0910_P2_RELOCK_MODE 0xf21d0008 -#define FSTV0910_P2_DEMOD_FAIL 0xf21d0004 -#define FSTV0910_P2_ETAPE1A_DVBXMEM 0xf21d0003 /*P2_DMDCFG3*/ #define RSTV0910_P2_DMDCFG3 0xf21e -#define FSTV0910_P2_DVBS1_TMGWAIT 0xf21e0080 -#define FSTV0910_P2_NO_BWCENTERING 0xf21e0040 -#define FSTV0910_P2_INV_SEQSRCH 0xf21e0020 -#define FSTV0910_P2_DIS_SFRUPLOW_TRK 0xf21e0010 #define FSTV0910_P2_NOSTOP_FIFOFULL 0xf21e0008 -#define FSTV0910_P2_LOCKTIME_MODE 0xf21e0007 /*P2_DMDCFG4*/ #define RSTV0910_P2_DMDCFG4 0xf21f #define FSTV0910_P2_DIS_VITLOCK 0xf21f0080 -#define FSTV0910_P2_S1S2TOUT_FAST 0xf21f0040 -#define FSTV0910_P2_DEMOD_FASTLOCK 0xf21f0020 -#define FSTV0910_P2_S1HIER_ENABLE 0xf21f0010 -#define FSTV0910_P2_TUNER_NRELAUNCH 0xf21f0008 #define FSTV0910_P2_DIS_CLKENABLE 0xf21f0004 -#define FSTV0910_P2_DIS_HDRDIVLOCK 0xf21f0002 -#define FSTV0910_P2_NO_TNRWBINIT 0xf21f0001 /*P2_CORRELMANT*/ #define RSTV0910_P2_CORRELMANT 0xf220 @@ -712,16 +656,45 @@ /*P2_DMDREG*/ #define RSTV0910_P2_DMDREG 0xf225 -#define FSTV0910_P2_EXTPSK_MODE 0xf2250080 -#define FSTV0910_P2_HIER_SHORTFRAME 0xf2250002 #define FSTV0910_P2_DECIM_PLFRAMES 0xf2250001 +/*P2_AGCNADJ*/ +#define RSTV0910_P2_AGCNADJ 0xf226 +#define FSTV0910_P2_RADJOFF_AGC2 0xf2260080 +#define FSTV0910_P2_RADJOFF_AGC1 0xf2260040 +#define FSTV0910_P2_AGC_NADJ 0xf226013f + +/*P2_AGCKS*/ +#define RSTV0910_P2_AGCKS 0xf227 +#define FSTV0910_P2_RSADJ_MANUALCFG 0xf2270080 +#define FSTV0910_P2_RSADJ_CCMMODE 0xf2270040 +#define FSTV0910_P2_RADJ_SPSK 0xf227013f + +/*P2_AGCKQ*/ +#define RSTV0910_P2_AGCKQ 0xf228 +#define FSTV0910_P2_RADJON_DVBS1 0xf2280040 +#define FSTV0910_P2_RADJ_QPSK 0xf228013f + +/*P2_AGCK8*/ +#define RSTV0910_P2_AGCK8 0xf229 +#define FSTV0910_P2_RADJ_8PSK 0xf229013f + +/*P2_AGCK16*/ +#define RSTV0910_P2_AGCK16 0xf22a +#define FSTV0910_P2_R2ADJOFF_16APSK 0xf22a0040 +#define FSTV0910_P2_R1ADJOFF_16APSK 0xf22a0020 +#define FSTV0910_P2_RADJ_16APSK 0xf22a011f + +/*P2_AGCK32*/ +#define RSTV0910_P2_AGCK32 0xf22b +#define FSTV0910_P2_R3ADJOFF_32APSK 0xf22b0080 +#define FSTV0910_P2_R2ADJOFF_32APSK 0xf22b0040 +#define FSTV0910_P2_R1ADJOFF_32APSK 0xf22b0020 +#define FSTV0910_P2_RADJ_32APSK 0xf22b011f + /*P2_AGC2O*/ #define RSTV0910_P2_AGC2O 0xf22c #define FSTV0910_P2_CSTENV_MODE 0xf22c00c0 -#define FSTV0910_P2_AGC2_LKSQRT 0xf22c0020 -#define FSTV0910_P2_AGC2_LKMODE 0xf22c0010 -#define FSTV0910_P2_AGC2_LKEQUA 0xf22c0008 #define FSTV0910_P2_AGC2_COEF 0xf22c0007 /*P2_AGC2REF*/ @@ -730,9 +703,36 @@ /*P2_AGC1ADJ*/ #define RSTV0910_P2_AGC1ADJ 0xf22e -#define FSTV0910_P2_AGC1ADJ_MANUAL 0xf22e0080 #define FSTV0910_P2_AGC1_ADJUSTED 0xf22e007f +/*P2_AGCRSADJ*/ +#define RSTV0910_P2_AGCRSADJ 0xf22f +#define FSTV0910_P2_RS_ADJUSTED 0xf22f007f + +/*P2_AGCRQADJ*/ +#define RSTV0910_P2_AGCRQADJ 0xf230 +#define FSTV0910_P2_RQ_ADJUSTED 0xf230007f + +/*P2_AGCR8ADJ*/ +#define RSTV0910_P2_AGCR8ADJ 0xf231 +#define FSTV0910_P2_R8_ADJUSTED 0xf231007f + +/*P2_AGCR1ADJ*/ +#define RSTV0910_P2_AGCR1ADJ 0xf232 +#define FSTV0910_P2_R1_ADJUSTED 0xf232007f + +/*P2_AGCR2ADJ*/ +#define RSTV0910_P2_AGCR2ADJ 0xf233 +#define FSTV0910_P2_R2_ADJUSTED 0xf233007f + +/*P2_AGCR3ADJ*/ +#define RSTV0910_P2_AGCR3ADJ 0xf234 +#define FSTV0910_P2_R3_ADJUSTED 0xf234007f + +/*P2_AGCREFADJ*/ +#define RSTV0910_P2_AGCREFADJ 0xf235 +#define FSTV0910_P2_AGC2REF_ADJUSTED 0xf235007f + /*P2_AGC2I1*/ #define RSTV0910_P2_AGC2I1 0xf236 #define FSTV0910_P2_AGC2_INTEGRATOR1 0xf23600ff @@ -743,26 +743,29 @@ /*P2_CARCFG*/ #define RSTV0910_P2_CARCFG 0xf238 -#define FSTV0910_P2_CFRUPLOW_AUTO 0xf2380080 -#define FSTV0910_P2_CFRUPLOW_TEST 0xf2380040 -#define FSTV0910_P2_WIDE_FREQDET 0xf2380020 -#define FSTV0910_P2_CARHDR_NODIV8 0xf2380010 -#define FSTV0910_P2_I2C_ROTA 0xf2380008 #define FSTV0910_P2_ROTAON 0xf2380004 #define FSTV0910_P2_PH_DET_ALGO 0xf2380003 /*P2_ACLC*/ #define RSTV0910_P2_ACLC 0xf239 -#define FSTV0910_P2_CARS1_ANOSAUTO 0xf2390040 #define FSTV0910_P2_CAR_ALPHA_MANT 0xf2390030 #define FSTV0910_P2_CAR_ALPHA_EXP 0xf239000f /*P2_BCLC*/ #define RSTV0910_P2_BCLC 0xf23a -#define FSTV0910_P2_CARS1_BNOSAUTO 0xf23a0040 #define FSTV0910_P2_CAR_BETA_MANT 0xf23a0030 #define FSTV0910_P2_CAR_BETA_EXP 0xf23a000f +/*P2_ACLCS2*/ +#define RSTV0910_P2_ACLCS2 0xf23b +#define FSTV0910_P2_CARS2_APLHA_MANTISSE 0xf23b0030 +#define FSTV0910_P2_CARS2_ALPHA_EXP 0xf23b000f + +/*P2_BCLCS2*/ +#define RSTV0910_P2_BCLCS2 0xf23c +#define FSTV0910_P2_CARS2_BETA_MANTISSE 0xf23c0030 +#define FSTV0910_P2_CARS2_BETA_EXP 0xf23c000f + /*P2_CARFREQ*/ #define RSTV0910_P2_CARFREQ 0xf23d #define FSTV0910_P2_KC_COARSE_EXP 0xf23d00f0 @@ -782,13 +785,6 @@ /*P2_CFRICFG*/ #define RSTV0910_P2_CFRICFG 0xf241 -#define FSTV0910_P2_CFRINIT_UNVALRNG 0xf2410080 -#define FSTV0910_P2_CFRINIT_LUNVALCPT 0xf2410040 -#define FSTV0910_P2_CFRINIT_ABORTDBL 0xf2410020 -#define FSTV0910_P2_CFRINIT_ABORTPRED 0xf2410010 -#define FSTV0910_P2_CFRINIT_UNVALSKIP 0xf2410008 -#define FSTV0910_P2_CFRINIT_CSTINC 0xf2410004 -#define FSTV0910_P2_CFRIROLL_GARDER 0xf2410002 #define FSTV0910_P2_NEG_CFRSTEP 0xf2410001 /*P2_CFRUP1*/ @@ -852,7 +848,6 @@ #define RSTV0910_P2_TMGCFG 0xf250 #define FSTV0910_P2_TMGLOCK_BETA 0xf25000c0 #define FSTV0910_P2_DO_TIMING_CORR 0xf2500010 -#define FSTV0910_P2_MANUAL_SCAN 0xf250000c #define FSTV0910_P2_TMG_MINFREQ 0xf2500003 /*P2_RTC*/ @@ -896,10 +891,7 @@ /*P2_TMGCFG2*/ #define RSTV0910_P2_TMGCFG2 0xf25a -#define FSTV0910_P2_KREFTMG2_DECMODE 0xf25a00c0 #define FSTV0910_P2_DIS_AUTOSAMP 0xf25a0008 -#define FSTV0910_P2_SCANINIT_QUART 0xf25a0004 -#define FSTV0910_P2_NOTMG_DVBS1DERAT 0xf25a0002 #define FSTV0910_P2_SFRRATIO_FINE 0xf25a0001 /*P2_KREFTMG2*/ @@ -908,11 +900,9 @@ /*P2_TMGCFG3*/ #define RSTV0910_P2_TMGCFG3 0xf25d -#define FSTV0910_P2_CFRINC_MODE 0xf25d0070 #define FSTV0910_P2_CONT_TMGCENTER 0xf25d0008 #define FSTV0910_P2_AUTO_GUP 0xf25d0004 #define FSTV0910_P2_AUTO_GLOW 0xf25d0002 -#define FSTV0910_P2_SFRVAL_MINMODE 0xf25d0001 /*P2_SFRINIT1*/ #define RSTV0910_P2_SFRINIT1 0xf25e @@ -977,16 +967,10 @@ /*P2_TMGOBS*/ #define RSTV0910_P2_TMGOBS 0xf26d #define FSTV0910_P2_ROLLOFF_STATUS 0xf26d00c0 -#define FSTV0910_P2_SCAN_SIGN 0xf26d0030 -#define FSTV0910_P2_TMG_SCANNING 0xf26d0008 -#define FSTV0910_P2_CHCENTERING_MODE 0xf26d0004 -#define FSTV0910_P2_TMG_SCANFAIL 0xf26d0002 /*P2_EQUALCFG*/ #define RSTV0910_P2_EQUALCFG 0xf26f -#define FSTV0910_P2_NOTMG_NEGALWAIT 0xf26f0080 #define FSTV0910_P2_EQUAL_ON 0xf26f0040 -#define FSTV0910_P2_SEL_EQUALCOR 0xf26f0038 #define FSTV0910_P2_MU_EQUALDFE 0xf26f0007 /*P2_EQUAI1*/ @@ -1117,20 +1101,20 @@ #define FSTV0910_P2_FRAMESEL_TYPESEL 0xf28e000c #define FSTV0910_P2_FRAMESEL_TYPE 0xf28e0003 +/*P2_NOSCFGF2*/ +#define RSTV0910_P2_NOSCFGF2 0xf28f +#define FSTV0910_P2_DIS_NOSPILOTS 0xf28f0080 +#define FSTV0910_P2_FRAMESEL_MODCODSEL 0xf28f0060 +#define FSTV0910_P2_FRAMESEL_MODCOD 0xf28f001f + /*P2_CAR2CFG*/ #define RSTV0910_P2_CAR2CFG 0xf290 -#define FSTV0910_P2_DESCRAMB_OFF 0xf2900080 -#define FSTV0910_P2_EN_PHNOSRAM 0xf2900020 -#define FSTV0910_P2_STOP_CFR2UPDATE 0xf2900010 -#define FSTV0910_P2_STOP_NCO2UPDATE 0xf2900008 #define FSTV0910_P2_ROTA2ON 0xf2900004 #define FSTV0910_P2_PH_DET_ALGO2 0xf2900003 /*P2_CFR2CFR1*/ #define RSTV0910_P2_CFR2CFR1 0xf291 -#define FSTV0910_P2_CFR2_S2CONTROL 0xf29100c0 #define FSTV0910_P2_EN_S2CAR2CENTER 0xf2910020 -#define FSTV0910_P2_BCHERRCFR2_MODE 0xf2910018 #define FSTV0910_P2_CFR2TOCFR1_BETA 0xf2910007 /*P2_CAR3CFG*/ @@ -1155,48 +1139,48 @@ /*P2_ACLC2S2Q*/ #define RSTV0910_P2_ACLC2S2Q 0xf297 #define FSTV0910_P2_ENAB_SPSKSYMB 0xf2970080 -#define FSTV0910_P2_CAR2S2_QANOSAUTO 0xf2970040 #define FSTV0910_P2_CAR2S2_Q_ALPH_M 0xf2970030 #define FSTV0910_P2_CAR2S2_Q_ALPH_E 0xf297000f /*P2_ACLC2S28*/ #define RSTV0910_P2_ACLC2S28 0xf298 -#define FSTV0910_P2_OLDI3Q_MODE 0xf2980080 -#define FSTV0910_P2_CAR2S2_8ANOSAUTO 0xf2980040 #define FSTV0910_P2_CAR2S2_8_ALPH_M 0xf2980030 #define FSTV0910_P2_CAR2S2_8_ALPH_E 0xf298000f /*P2_ACLC2S216A*/ #define RSTV0910_P2_ACLC2S216A 0xf299 -#define FSTV0910_P2_CAR2S2_16ANOSAUTO 0xf2990040 #define FSTV0910_P2_CAR2S2_16A_ALPH_M 0xf2990030 #define FSTV0910_P2_CAR2S2_16A_ALPH_E 0xf299000f /*P2_ACLC2S232A*/ #define RSTV0910_P2_ACLC2S232A 0xf29a -#define FSTV0910_P2_CAR2S2_32ANOSUATO 0xf29a0040 #define FSTV0910_P2_CAR2S2_32A_ALPH_M 0xf29a0030 #define FSTV0910_P2_CAR2S2_32A_ALPH_E 0xf29a000f /*P2_BCLC2S2Q*/ #define RSTV0910_P2_BCLC2S2Q 0xf29c -#define FSTV0910_P2_DVBS2S2Q_NIP 0xf29c0080 -#define FSTV0910_P2_CAR2S2_QBNOSAUTO 0xf29c0040 #define FSTV0910_P2_CAR2S2_Q_BETA_M 0xf29c0030 #define FSTV0910_P2_CAR2S2_Q_BETA_E 0xf29c000f /*P2_BCLC2S28*/ #define RSTV0910_P2_BCLC2S28 0xf29d -#define FSTV0910_P2_DVBS2S28_NIP 0xf29d0080 -#define FSTV0910_P2_CAR2S2_8BNOSAUTO 0xf29d0040 #define FSTV0910_P2_CAR2S2_8_BETA_M 0xf29d0030 #define FSTV0910_P2_CAR2S2_8_BETA_E 0xf29d000f +/*P2_BCLC2S216A*/ +#define RSTV0910_P2_BCLC2S216A 0xf29e +#define FSTV0910_P2_DVBS2S216A_NIP 0xf29e0080 +#define FSTV0910_P2_CAR2S2_16A_BETA_M 0xf29e0030 +#define FSTV0910_P2_CAR2S2_16A_BETA_E 0xf29e000f + +/*P2_BCLC2S232A*/ +#define RSTV0910_P2_BCLC2S232A 0xf29f +#define FSTV0910_P2_DVBS2S232A_NIP 0xf29f0080 +#define FSTV0910_P2_CAR2S2_32A_BETA_M 0xf29f0030 +#define FSTV0910_P2_CAR2S2_32A_BETA_E 0xf29f000f + /*P2_PLROOT2*/ #define RSTV0910_P2_PLROOT2 0xf2ac -#define FSTV0910_P2_PLHAUTO_DISPLH 0xf2ac0040 -#define FSTV0910_P2_PLHAUTO_FASTMODE 0xf2ac0020 -#define FSTV0910_P2_PLHAUTO_ENABLE 0xf2ac0010 #define FSTV0910_P2_PLSCRAMB_MODE 0xf2ac000c #define FSTV0910_P2_PLSCRAMB_ROOT2 0xf2ac0003 @@ -1208,45 +1192,93 @@ #define RSTV0910_P2_PLROOT0 0xf2ae #define FSTV0910_P2_PLSCRAMB_ROOT0 0xf2ae00ff +/*P2_MODCODLST0*/ +#define RSTV0910_P2_MODCODLST0 0xf2b0 +#define FSTV0910_P2_NACCES_MODCODCH 0xf2b00001 + +/*P2_MODCODLST1*/ +#define RSTV0910_P2_MODCODLST1 0xf2b1 +#define FSTV0910_P2_SYMBRATE_FILTER 0xf2b10008 +#define FSTV0910_P2_NRESET_MODCODLST 0xf2b10004 +#define FSTV0910_P2_DIS_32PSK_9_10 0xf2b10003 + +/*P2_MODCODLST2*/ +#define RSTV0910_P2_MODCODLST2 0xf2b2 +#define FSTV0910_P2_DIS_32PSK_8_9 0xf2b200f0 +#define FSTV0910_P2_DIS_32PSK_5_6 0xf2b2000f + +/*P2_MODCODLST3*/ +#define RSTV0910_P2_MODCODLST3 0xf2b3 +#define FSTV0910_P2_DIS_32PSK_4_5 0xf2b300f0 +#define FSTV0910_P2_DIS_32PSK_3_4 0xf2b3000f + +/*P2_MODCODLST4*/ +#define RSTV0910_P2_MODCODLST4 0xf2b4 +#define FSTV0910_P2_DUMMYPL_PILOT 0xf2b40080 +#define FSTV0910_P2_DUMMYPL_NOPILOT 0xf2b40040 +#define FSTV0910_P2_DIS_16PSK_9_10 0xf2b40030 +#define FSTV0910_P2_DIS_16PSK_8_9 0xf2b4000f + +/*P2_MODCODLST5*/ +#define RSTV0910_P2_MODCODLST5 0xf2b5 +#define FSTV0910_P2_DIS_16PSK_5_6 0xf2b500f0 +#define FSTV0910_P2_DIS_16PSK_4_5 0xf2b5000f + +/*P2_MODCODLST6*/ +#define RSTV0910_P2_MODCODLST6 0xf2b6 +#define FSTV0910_P2_DIS_16PSK_3_4 0xf2b600f0 +#define FSTV0910_P2_DIS_16PSK_2_3 0xf2b6000f + /*P2_MODCODLST7*/ #define RSTV0910_P2_MODCODLST7 0xf2b7 #define FSTV0910_P2_MODCOD_NNOSFILTER 0xf2b70080 -#define FSTV0910_P2_MODCODLST_NOSTYPE 0xf2b70040 #define FSTV0910_P2_DIS_8PSK_9_10 0xf2b70030 -#define FSTV0910_P2_DIS_8P_8_9 0xf2b7000f +#define FSTV0910_P2_DIS_8PSK_8_9 0xf2b7000f /*P2_MODCODLST8*/ #define RSTV0910_P2_MODCODLST8 0xf2b8 -#define FSTV0910_P2_DIS_8P_5_6 0xf2b800f0 -#define FSTV0910_P2_DIS_8P_3_4 0xf2b8000f +#define FSTV0910_P2_DIS_8PSK_5_6 0xf2b800f0 +#define FSTV0910_P2_DIS_8PSK_3_4 0xf2b8000f /*P2_MODCODLST9*/ #define RSTV0910_P2_MODCODLST9 0xf2b9 -#define FSTV0910_P2_DIS_8P_2_3 0xf2b900f0 -#define FSTV0910_P2_DIS_8P_3_5 0xf2b9000f +#define FSTV0910_P2_DIS_8PSK_2_3 0xf2b900f0 +#define FSTV0910_P2_DIS_8PSK_3_5 0xf2b9000f /*P2_MODCODLSTA*/ #define RSTV0910_P2_MODCODLSTA 0xf2ba #define FSTV0910_P2_NOSFILTER_LIMITE 0xf2ba0080 -#define FSTV0910_P2_NOSFILTER_MODE 0xf2ba0040 #define FSTV0910_P2_DIS_QPSK_9_10 0xf2ba0030 -#define FSTV0910_P2_DIS_QP_8_9 0xf2ba000f +#define FSTV0910_P2_DIS_QPSK_8_9 0xf2ba000f /*P2_MODCODLSTB*/ #define RSTV0910_P2_MODCODLSTB 0xf2bb -#define FSTV0910_P2_DIS_QP_5_6 0xf2bb00f0 -#define FSTV0910_P2_DIS_QP_4_5 0xf2bb000f +#define FSTV0910_P2_DIS_QPSK_5_6 0xf2bb00f0 +#define FSTV0910_P2_DIS_QPSK_4_5 0xf2bb000f /*P2_MODCODLSTC*/ #define RSTV0910_P2_MODCODLSTC 0xf2bc -#define FSTV0910_P2_DIS_QP_3_4 0xf2bc00f0 -#define FSTV0910_P2_DIS_QP_2_3 0xf2bc000f +#define FSTV0910_P2_DIS_QPSK_3_4 0xf2bc00f0 +#define FSTV0910_P2_DIS_QPSK_2_3 0xf2bc000f /*P2_MODCODLSTD*/ #define RSTV0910_P2_MODCODLSTD 0xf2bd #define FSTV0910_P2_DIS_QPSK_3_5 0xf2bd00f0 #define FSTV0910_P2_DIS_QPSK_1_2 0xf2bd000f +/*P2_MODCODLSTE*/ +#define RSTV0910_P2_MODCODLSTE 0xf2be +#define FSTV0910_P2_DIS_QPSK_2_5 0xf2be00f0 +#define FSTV0910_P2_DIS_QPSK_1_3 0xf2be000f + +/*P2_MODCODLSTF*/ +#define RSTV0910_P2_MODCODLSTF 0xf2bf +#define FSTV0910_P2_DIS_QPSK_1_4 0xf2bf00f0 +#define FSTV0910_P2_DEMOD_INVMODLST 0xf2bf0008 +#define FSTV0910_P2_DEMODOUT_ENABLE 0xf2bf0004 +#define FSTV0910_P2_DDEMOD_NSET 0xf2bf0002 +#define FSTV0910_P2_MODCOD_NSTOCK 0xf2bf0001 + /*P2_GAUSSR0*/ #define RSTV0910_P2_GAUSSR0 0xf2c0 #define FSTV0910_P2_EN_CCIMODE 0xf2c00080 @@ -1275,8 +1307,6 @@ #define FSTV0910_P2_RAINFADE_DETECT 0xf2c50080 #define FSTV0910_P2_NOTHRES2_FAIL 0xf2c50040 #define FSTV0910_P2_NOTHRES1_FAIL 0xf2c50020 -#define FSTV0910_P2_PILOT_FAILDETECT 0xf2c50010 -#define FSTV0910_P2_HIER_DETECT 0xf2c50008 #define FSTV0910_P2_DMDPROG_ERROR 0xf2c50004 #define FSTV0910_P2_CSTENV_DETECT 0xf2c50002 #define FSTV0910_P2_DETECTION_TRIAX 0xf2c50001 @@ -1284,15 +1314,12 @@ /*P2_DMDRESCFG*/ #define RSTV0910_P2_DMDRESCFG 0xf2c6 #define FSTV0910_P2_DMDRES_RESET 0xf2c60080 -#define FSTV0910_P2_DMDRES_NOISESQR 0xf2c60010 #define FSTV0910_P2_DMDRES_STRALL 0xf2c60008 #define FSTV0910_P2_DMDRES_NEWONLY 0xf2c60004 #define FSTV0910_P2_DMDRES_NOSTORE 0xf2c60002 -#define FSTV0910_P2_DMDRES_AGC2MEM 0xf2c60001 /*P2_DMDRESADR*/ #define RSTV0910_P2_DMDRESADR 0xf2c7 -#define FSTV0910_P2_SUSP_PREDCANAL 0xf2c70080 #define FSTV0910_P2_DMDRES_VALIDCFR 0xf2c70040 #define FSTV0910_P2_DMDRES_MEMFULL 0xf2c70030 #define FSTV0910_P2_DMDRES_RESNBR 0xf2c7000f @@ -1370,13 +1397,6 @@ /*P2_TNRCFG2*/ #define RSTV0910_P2_TNRCFG2 0xf2e1 #define FSTV0910_P2_TUN_IQSWAP 0xf2e10080 -#define FSTV0910_P2_STB6110_STEP2MHZ 0xf2e10040 -#define FSTV0910_P2_STB6120_DBLI2C 0xf2e10020 -#define FSTV0910_P2_TUNER_WIDEBAND 0xf2e10010 -#define FSTV0910_P2_TUNER_OBSPAGE 0xf2e10008 -#define FSTV0910_P2_DIS_BWCALC 0xf2e10004 -#define FSTV0910_P2_SHORT_WAITSTATES 0xf2e10002 -#define FSTV0910_P2_DIS_2BWAGC1 0xf2e10001 /*P2_SMAPCOEF7*/ #define RSTV0910_P2_SMAPCOEF7 0xf300 @@ -1386,10 +1406,6 @@ /*P2_SMAPCOEF6*/ #define RSTV0910_P2_SMAPCOEF6 0xf301 #define FSTV0910_P2_DIS_AGC2SCALE 0xf3010080 -#define FSTV0910_P2_DIS_16IQMULT 0xf3010040 -#define FSTV0910_P2_OLD_16APSK47 0xf3010020 -#define FSTV0910_P2_OLD_16APSK12 0xf3010010 -#define FSTV0910_P2_DIS_NEWSCALE 0xf3010008 #define FSTV0910_P2_ADJ_8PSKLLR1 0xf3010004 #define FSTV0910_P2_OLD_8PSKLLR1 0xf3010002 #define FSTV0910_P2_DIS_AB8PSK 0xf3010001 @@ -1399,6 +1415,29 @@ #define FSTV0910_P2_DIS_8SCALE 0xf3020080 #define FSTV0910_P2_SMAPCOEF_8P_LLR23 0xf302017f +/*P2_SMAPCOEF4*/ +#define RSTV0910_P2_SMAPCOEF4 0xf303 +#define FSTV0910_P2_SMAPCOEF_16APSK_LLR12 0xf303017f + +/*P2_SMAPCOEF3*/ +#define RSTV0910_P2_SMAPCOEF3 0xf304 +#define FSTV0910_P2_SMAPCOEF_16APSK_LLR34 0xf304017f + +/*P2_SMAPCOEF2*/ +#define RSTV0910_P2_SMAPCOEF2 0xf305 +#define FSTV0910_P2_SMAPCOEF_32APSK_R2R3 0xf30501f0 +#define FSTV0910_P2_SMAPCOEF_32APSK_LLR2 0xf305010f + +/*P2_SMAPCOEF1*/ +#define RSTV0910_P2_SMAPCOEF1 0xf306 +#define FSTV0910_P2_DIS_16SCALE 0xf3060080 +#define FSTV0910_P2_SMAPCOEF_32_LLR34 0xf306017f + +/*P2_SMAPCOEF0*/ +#define RSTV0910_P2_SMAPCOEF0 0xf307 +#define FSTV0910_P2_DIS_32SCALE 0xf3070080 +#define FSTV0910_P2_SMAPCOEF_32_LLR15 0xf307017f + /*P2_NOSTHRES1*/ #define RSTV0910_P2_NOSTHRES1 0xf309 #define FSTV0910_P2_NOS_THRESHOLD1 0xf30900ff @@ -1419,8 +1458,6 @@ /*P2_NOSRAMCFG*/ #define RSTV0910_P2_NOSRAMCFG 0xf30d -#define FSTV0910_P2_NOSRAM_DVBS2DATA 0xf30d0080 -#define FSTV0910_P2_NOSRAM_QUADRAT 0xf30d0040 #define FSTV0910_P2_NOSRAM_ACTIVATION 0xf30d0030 #define FSTV0910_P2_NOSRAM_CNRONLY 0xf30d0008 #define FSTV0910_P2_NOSRAM_LGNCNR1 0xf30d0007 @@ -1459,18 +1496,13 @@ #define RSTV0910_P2_VITSCALE 0xf332 #define FSTV0910_P2_NVTH_NOSRANGE 0xf3320080 #define FSTV0910_P2_VERROR_MAXMODE 0xf3320040 -#define FSTV0910_P2_KDIV_MODE 0xf3320030 #define FSTV0910_P2_NSLOWSN_LOCKED 0xf3320008 -#define FSTV0910_P2_DELOCK_PRFLOSS 0xf3320004 #define FSTV0910_P2_DIS_RSFLOCK 0xf3320002 /*P2_FECM*/ #define RSTV0910_P2_FECM 0xf333 #define FSTV0910_P2_DSS_DVB 0xf3330080 -#define FSTV0910_P2_DEMOD_BYPASS 0xf3330040 -#define FSTV0910_P2_CMP_SLOWMODE 0xf3330020 #define FSTV0910_P2_DSS_SRCH 0xf3330010 -#define FSTV0910_P2_DIFF_MODEVIT 0xf3330004 #define FSTV0910_P2_SYNCVIT 0xf3330002 #define FSTV0910_P2_IQINV 0xf3330001 @@ -1500,9 +1532,6 @@ /*P2_VITCURPUN*/ #define RSTV0910_P2_VITCURPUN 0xf33a -#define FSTV0910_P2_CYCLESLIP_VIT 0xf33a0080 -#define FSTV0910_P2_VIT_ROTA180 0xf33a0040 -#define FSTV0910_P2_VIT_ROTA90 0xf33a0020 #define FSTV0910_P2_VIT_CURPUN 0xf33a001f /*P2_VERROR*/ @@ -1529,14 +1558,8 @@ /*P2_VSTATUSVIT*/ #define RSTV0910_P2_VSTATUSVIT 0xf33e -#define FSTV0910_P2_VITERBI_ON 0xf33e0080 -#define FSTV0910_P2_END_LOOPVIT 0xf33e0040 -#define FSTV0910_P2_VITERBI_DEPRF 0xf33e0020 #define FSTV0910_P2_PRFVIT 0xf33e0010 #define FSTV0910_P2_LOCKEDVIT 0xf33e0008 -#define FSTV0910_P2_VITERBI_DELOCK 0xf33e0004 -#define FSTV0910_P2_VIT_DEMODSEL 0xf33e0002 -#define FSTV0910_P2_VITERBI_COMPOUT 0xf33e0001 /*P2_VTHINUSE*/ #define RSTV0910_P2_VTHINUSE 0xf33f @@ -1544,45 +1567,44 @@ /*P2_KDIV12*/ #define RSTV0910_P2_KDIV12 0xf340 -#define FSTV0910_P2_KDIV12_MANUAL 0xf3400080 #define FSTV0910_P2_K_DIVIDER_12 0xf340007f /*P2_KDIV23*/ #define RSTV0910_P2_KDIV23 0xf341 -#define FSTV0910_P2_KDIV23_MANUAL 0xf3410080 #define FSTV0910_P2_K_DIVIDER_23 0xf341007f /*P2_KDIV34*/ #define RSTV0910_P2_KDIV34 0xf342 -#define FSTV0910_P2_KDIV34_MANUAL 0xf3420080 #define FSTV0910_P2_K_DIVIDER_34 0xf342007f /*P2_KDIV56*/ #define RSTV0910_P2_KDIV56 0xf343 -#define FSTV0910_P2_KDIV56_MANUAL 0xf3430080 #define FSTV0910_P2_K_DIVIDER_56 0xf343007f /*P2_KDIV67*/ #define RSTV0910_P2_KDIV67 0xf344 -#define FSTV0910_P2_KDIV67_MANUAL 0xf3440080 #define FSTV0910_P2_K_DIVIDER_67 0xf344007f /*P2_KDIV78*/ #define RSTV0910_P2_KDIV78 0xf345 -#define FSTV0910_P2_KDIV78_MANUAL 0xf3450080 #define FSTV0910_P2_K_DIVIDER_78 0xf345007f +/*P2_TSPIDFLT1*/ +#define RSTV0910_P2_TSPIDFLT1 0xf346 +#define FSTV0910_P2_PIDFLT_ADDR 0xf34600ff + +/*P2_TSPIDFLT0*/ +#define RSTV0910_P2_TSPIDFLT0 0xf347 +#define FSTV0910_P2_PIDFLT_DATA 0xf34700ff + /*P2_PDELCTRL0*/ #define RSTV0910_P2_PDELCTRL0 0xf34f #define FSTV0910_P2_ISIOBS_MODE 0xf34f0030 -#define FSTV0910_P2_PDELDIS_BITWISE 0xf34f0004 /*P2_PDELCTRL1*/ #define RSTV0910_P2_PDELCTRL1 0xf350 #define FSTV0910_P2_INV_MISMASK 0xf3500080 -#define FSTV0910_P2_FORCE_ACCEPTED 0xf3500040 #define FSTV0910_P2_FILTER_EN 0xf3500020 -#define FSTV0910_P2_FORCE_PKTDELINUSE 0xf3500010 #define FSTV0910_P2_HYSTEN 0xf3500008 #define FSTV0910_P2_HYSTSWRST 0xf3500004 #define FSTV0910_P2_EN_MIS00 0xf3500002 @@ -1593,8 +1615,6 @@ #define FSTV0910_P2_FORCE_CONTINUOUS 0xf3510080 #define FSTV0910_P2_RESET_UPKO_COUNT 0xf3510040 #define FSTV0910_P2_USER_PKTDELIN_NB 0xf3510020 -#define FSTV0910_P2_DATA_UNBBSCRAMBLED 0xf3510008 -#define FSTV0910_P2_FORCE_LONGPKT 0xf3510004 #define FSTV0910_P2_FRAME_MODE 0xf3510002 /*P2_HYSTTHRESH*/ @@ -1602,6 +1622,11 @@ #define FSTV0910_P2_DELIN_LOCKTHRES 0xf35400f0 #define FSTV0910_P2_DELIN_UNLOCKTHRES 0xf354000f +/*P2_UPLCCST0*/ +#define RSTV0910_P2_UPLCCST0 0xf358 +#define FSTV0910_P2_UPL_CST0 0xf35800f8 +#define FSTV0910_P2_UPL_MODE 0xf3580007 + /*P2_ISIENTRY*/ #define RSTV0910_P2_ISIENTRY 0xf35e #define FSTV0910_P2_ISI_ENTRY 0xf35e00ff @@ -1650,16 +1675,13 @@ #define RSTV0910_P2_PDELSTATUS1 0xf369 #define FSTV0910_P2_PKTDELIN_DELOCK 0xf3690080 #define FSTV0910_P2_SYNCDUPDFL_BADDFL 0xf3690040 -#define FSTV0910_P2_CONTINUOUS_STREAM 0xf3690020 #define FSTV0910_P2_UNACCEPTED_STREAM 0xf3690010 #define FSTV0910_P2_BCH_ERROR_FLAG 0xf3690008 -#define FSTV0910_P2_BBHCRCKO 0xf3690004 #define FSTV0910_P2_PKTDELIN_LOCK 0xf3690002 #define FSTV0910_P2_FIRST_LOCK 0xf3690001 /*P2_PDELSTATUS2*/ #define RSTV0910_P2_PDELSTATUS2 0xf36a -#define FSTV0910_P2_PKTDEL_DEMODSEL 0xf36a0080 #define FSTV0910_P2_FRAME_MODCOD 0xf36a007c #define FSTV0910_P2_FRAME_TYPE 0xf36a0003 @@ -1681,18 +1703,12 @@ /*P2_PDELCTRL3*/ #define RSTV0910_P2_PDELCTRL3 0xf36f -#define FSTV0910_P2_PKTDEL_CONTFAIL 0xf36f0080 -#define FSTV0910_P2_PKTDEL_ENLONGPKT 0xf36f0040 #define FSTV0910_P2_NOFIFO_BCHERR 0xf36f0020 #define FSTV0910_P2_PKTDELIN_DELACMERR 0xf36f0010 -#define FSTV0910_P2_SATURATE_BBPKTKO 0xf36f0004 -#define FSTV0910_P2_PKTDEL_BCHERRCONT 0xf36f0002 -#define FSTV0910_P2_ETHERNET_DISFCS 0xf36f0001 /*P2_TSSTATEM*/ #define RSTV0910_P2_TSSTATEM 0xf370 #define FSTV0910_P2_TSDIL_ON 0xf3700080 -#define FSTV0910_P2_TSSKIPRS_ON 0xf3700040 #define FSTV0910_P2_TSRS_ON 0xf3700020 #define FSTV0910_P2_TSDESCRAMB_ON 0xf3700010 #define FSTV0910_P2_TSFRAME_MODE 0xf3700008 @@ -1700,6 +1716,15 @@ #define FSTV0910_P2_TSACM_MODE 0xf3700002 #define FSTV0910_P2_TSOUT_NOSYNC 0xf3700001 +/*P2_TSSTATEL*/ +#define RSTV0910_P2_TSSTATEL 0xf371 +#define FSTV0910_P2_TSNOSYNCBYTE 0xf3710080 +#define FSTV0910_P2_TSPARITY_ON 0xf3710040 +#define FSTV0910_P2_TSISSYI_ON 0xf3710008 +#define FSTV0910_P2_TSNPD_ON 0xf3710004 +#define FSTV0910_P2_TSCRC8_ON 0xf3710002 +#define FSTV0910_P2_TSDSS_PACKET 0xf3710001 + /*P2_TSCFGH*/ #define RSTV0910_P2_TSCFGH 0xf372 #define FSTV0910_P2_TSFIFO_DVBCI 0xf3720080 @@ -1715,8 +1740,6 @@ #define FSTV0910_P2_TSFIFO_MANSPEED 0xf37300c0 #define FSTV0910_P2_TSFIFO_PERMDATA 0xf3730020 #define FSTV0910_P2_TSFIFO_NONEWSGNL 0xf3730010 -#define FSTV0910_P2_NPD_SPECDVBS2 0xf3730004 -#define FSTV0910_P2_TSFIFO_DPUNACTIVE 0xf3730002 #define FSTV0910_P2_TSFIFO_INVDATA 0xf3730001 /*P2_TSCFGL*/ @@ -1727,32 +1750,45 @@ #define FSTV0910_P2_TSFIFO_EMBINDVB 0xf3740004 #define FSTV0910_P2_TSFIFO_BITSPEED 0xf3740003 +/*P2_TSSYNC*/ +#define RSTV0910_P2_TSSYNC 0xf375 +#define FSTV0910_P2_TSFIFO_SYNCMODE 0xf3750018 + /*P2_TSINSDELH*/ #define RSTV0910_P2_TSINSDELH 0xf376 #define FSTV0910_P2_TSDEL_SYNCBYTE 0xf3760080 #define FSTV0910_P2_TSDEL_XXHEADER 0xf3760040 -#define FSTV0910_P2_TSDEL_BBHEADER 0xf3760020 #define FSTV0910_P2_TSDEL_DATAFIELD 0xf3760010 -#define FSTV0910_P2_TSINSDEL_ISCR 0xf3760008 -#define FSTV0910_P2_TSINSDEL_NPD 0xf3760004 #define FSTV0910_P2_TSINSDEL_RSPARITY 0xf3760002 #define FSTV0910_P2_TSINSDEL_CRC8 0xf3760001 +/*P2_TSINSDELM*/ +#define RSTV0910_P2_TSINSDELM 0xf377 +#define FSTV0910_P2_TSINS_EMODCOD 0xf3770010 +#define FSTV0910_P2_TSINS_TOKEN 0xf3770008 +#define FSTV0910_P2_TSINS_XXXERR 0xf3770004 +#define FSTV0910_P2_TSINS_MATYPE 0xf3770002 +#define FSTV0910_P2_TSINS_UPL 0xf3770001 + +/*P2_TSINSDELL*/ +#define RSTV0910_P2_TSINSDELL 0xf378 +#define FSTV0910_P2_TSINS_DFL 0xf3780080 +#define FSTV0910_P2_TSINS_SYNCD 0xf3780040 +#define FSTV0910_P2_TSINS_BLOCLEN 0xf3780020 +#define FSTV0910_P2_TSINS_SIGPCOUNT 0xf3780010 +#define FSTV0910_P2_TSINS_FIFO 0xf3780008 +#define FSTV0910_P2_TSINS_REALPACK 0xf3780004 +#define FSTV0910_P2_TSINS_TSCONFIG 0xf3780002 +#define FSTV0910_P2_TSINS_LATENCY 0xf3780001 + /*P2_TSDIVN*/ #define RSTV0910_P2_TSDIVN 0xf379 #define FSTV0910_P2_TSFIFO_SPEEDMODE 0xf37900c0 -#define FSTV0910_P2_BYTE_OVERSAMPLING 0xf3790038 #define FSTV0910_P2_TSFIFO_RISEOK 0xf3790007 /*P2_TSCFG4*/ #define RSTV0910_P2_TSCFG4 0xf37a #define FSTV0910_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0 -#define FSTV0910_P2_TSFIFO_HIERSEL 0xf37a0020 -#define FSTV0910_P2_TSFIFO_SPECTOKEN 0xf37a0010 -#define FSTV0910_P2_TSFIFO_MAXMODE 0xf37a0008 -#define FSTV0910_P2_TSFIFO_FRFORCEPKT 0xf37a0004 -#define FSTV0910_P2_EXT_FECSPYIN 0xf37a0002 -#define FSTV0910_P2_TSFIFO_DELSPEEDUP 0xf37a0001 /*P2_TSSPEED*/ #define RSTV0910_P2_TSSPEED 0xf380 @@ -1762,11 +1798,8 @@ #define RSTV0910_P2_TSSTATUS 0xf381 #define FSTV0910_P2_TSFIFO_LINEOK 0xf3810080 #define FSTV0910_P2_TSFIFO_ERROR 0xf3810040 -#define FSTV0910_P2_TSFIFO_DATA7 0xf3810020 #define FSTV0910_P2_TSFIFO_NOSYNC 0xf3810010 -#define FSTV0910_P2_ISCR_INITIALIZED 0xf3810008 #define FSTV0910_P2_TSREGUL_ERROR 0xf3810004 -#define FSTV0910_P2_SOFFIFO_UNREGUL 0xf3810002 #define FSTV0910_P2_DIL_READY 0xf3810001 /*P2_TSSTATUS2*/ @@ -1774,11 +1807,7 @@ #define FSTV0910_P2_TSFIFO_DEMODSEL 0xf3820080 #define FSTV0910_P2_TSFIFOSPEED_STORE 0xf3820040 #define FSTV0910_P2_DILXX_RESET 0xf3820020 -#define FSTV0910_P2_TSSPEED_IMPOSSIBLE 0xf3820010 -#define FSTV0910_P2_TSFIFO_LINENOK 0xf3820008 -#define FSTV0910_P2_TSFIFO_MUXSTREAM 0xf3820004 #define FSTV0910_P2_SCRAMBDETECT 0xf3820002 -#define FSTV0910_P2_ULDTV67_FALSELOCK 0xf3820001 /*P2_TSBITRATE1*/ #define RSTV0910_P2_TSBITRATE1 0xf383 @@ -1788,6 +1817,59 @@ #define RSTV0910_P2_TSBITRATE0 0xf384 #define FSTV0910_P2_TSFIFO_BITRATE0 0xf38400ff +/*P2_TSPACKLEN1*/ +#define RSTV0910_P2_TSPACKLEN1 0xf385 +#define FSTV0910_P2_TSFIFO_PACKCPT 0xf38500e0 + +/*P2_TSDLY2*/ +#define RSTV0910_P2_TSDLY2 0xf389 +#define FSTV0910_P2_SOFFIFO_LATENCY2 0xf389000f + +/*P2_TSDLY1*/ +#define RSTV0910_P2_TSDLY1 0xf38a +#define FSTV0910_P2_SOFFIFO_LATENCY1 0xf38a00ff + +/*P2_TSDLY0*/ +#define RSTV0910_P2_TSDLY0 0xf38b +#define FSTV0910_P2_SOFFIFO_LATENCY0 0xf38b00ff + +/*P2_TSNPDAV*/ +#define RSTV0910_P2_TSNPDAV 0xf38c +#define FSTV0910_P2_TSNPD_AVERAGE 0xf38c00ff + +/*P2_TSBUFSTAT2*/ +#define RSTV0910_P2_TSBUFSTAT2 0xf38d +#define FSTV0910_P2_TSISCR_3BYTES 0xf38d0080 +#define FSTV0910_P2_TSISCR_NEWDATA 0xf38d0040 +#define FSTV0910_P2_TSISCR_BUFSTAT2 0xf38d003f + +/*P2_TSBUFSTAT1*/ +#define RSTV0910_P2_TSBUFSTAT1 0xf38e +#define FSTV0910_P2_TSISCR_BUFSTAT1 0xf38e00ff + +/*P2_TSBUFSTAT0*/ +#define RSTV0910_P2_TSBUFSTAT0 0xf38f +#define FSTV0910_P2_TSISCR_BUFSTAT0 0xf38f00ff + +/*P2_TSDEBUGL*/ +#define RSTV0910_P2_TSDEBUGL 0xf391 +#define FSTV0910_P2_TSFIFO_ERROR_EVNT 0xf3910004 +#define FSTV0910_P2_TSFIFO_OVERFLOWM 0xf3910001 + +/*P2_TSDLYSET2*/ +#define RSTV0910_P2_TSDLYSET2 0xf392 +#define FSTV0910_P2_SOFFIFO_OFFSET 0xf39200c0 +#define FSTV0910_P2_HYSTERESIS_THRESHOLD 0xf3920030 +#define FSTV0910_P2_SOFFIFO_SYMBOFFS2 0xf392000f + +/*P2_TSDLYSET1*/ +#define RSTV0910_P2_TSDLYSET1 0xf393 +#define FSTV0910_P2_SOFFIFO_SYMBOFFS1 0xf39300ff + +/*P2_TSDLYSET0*/ +#define RSTV0910_P2_TSDLYSET0 0xf394 +#define FSTV0910_P2_SOFFIFO_SYMBOFFS0 0xf39400ff + /*P2_ERRCTRL1*/ #define RSTV0910_P2_ERRCTRL1 0xf398 #define FSTV0910_P2_ERR_SOURCE1 0xf39800f0 @@ -1845,14 +1927,12 @@ /*P2_FSPYDATA*/ #define RSTV0910_P2_FSPYDATA 0xf3a2 #define FSTV0910_P2_SPY_STUFFING 0xf3a20080 -#define FSTV0910_P2_NOERROR_PKTJITTER 0xf3a20040 #define FSTV0910_P2_SPY_CNULLPKT 0xf3a20020 #define FSTV0910_P2_SPY_OUTDATA_MODE 0xf3a2001f /*P2_FSPYOUT*/ #define RSTV0910_P2_FSPYOUT 0xf3a3 #define FSTV0910_P2_FSPY_DIRECT 0xf3a30080 -#define FSTV0910_P2_SPY_OUTDATA_BUS 0xf3a30038 #define FSTV0910_P2_STUFF_MODE 0xf3a30007 /*P2_FSTATUS*/ @@ -1897,8 +1977,6 @@ /*P2_FSPYBER*/ #define RSTV0910_P2_FSPYBER 0xf3b2 -#define FSTV0910_P2_FSPYOBS_XORREAD 0xf3b20040 -#define FSTV0910_P2_FSPYBER_OBSMODE 0xf3b20020 #define FSTV0910_P2_FSPYBER_SYNCBYTE 0xf3b20010 #define FSTV0910_P2_FSPYBER_UNSYNC 0xf3b20008 #define FSTV0910_P2_FSPYBER_CTIME 0xf3b20007 @@ -1919,32 +1997,26 @@ /*P2_SFKDIV12*/ #define RSTV0910_P2_SFKDIV12 0xf3c4 #define FSTV0910_P2_SFECKDIV12_MAN 0xf3c40080 -#define FSTV0910_P2_SFEC_K_DIVIDER_12 0xf3c4007f /*P2_SFKDIV23*/ #define RSTV0910_P2_SFKDIV23 0xf3c5 #define FSTV0910_P2_SFECKDIV23_MAN 0xf3c50080 -#define FSTV0910_P2_SFEC_K_DIVIDER_23 0xf3c5007f /*P2_SFKDIV34*/ #define RSTV0910_P2_SFKDIV34 0xf3c6 #define FSTV0910_P2_SFECKDIV34_MAN 0xf3c60080 -#define FSTV0910_P2_SFEC_K_DIVIDER_34 0xf3c6007f /*P2_SFKDIV56*/ #define RSTV0910_P2_SFKDIV56 0xf3c7 #define FSTV0910_P2_SFECKDIV56_MAN 0xf3c70080 -#define FSTV0910_P2_SFEC_K_DIVIDER_56 0xf3c7007f /*P2_SFKDIV67*/ #define RSTV0910_P2_SFKDIV67 0xf3c8 #define FSTV0910_P2_SFECKDIV67_MAN 0xf3c80080 -#define FSTV0910_P2_SFEC_K_DIVIDER_67 0xf3c8007f /*P2_SFKDIV78*/ #define RSTV0910_P2_SFKDIV78 0xf3c9 #define FSTV0910_P2_SFECKDIV78_MAN 0xf3c90080 -#define FSTV0910_P2_SFEC_K_DIVIDER_78 0xf3c9007f /*P2_SFSTATUS*/ #define RSTV0910_P2_SFSTATUS 0xf3cc @@ -1959,11 +2031,7 @@ /*P2_SFDLYSET2*/ #define RSTV0910_P2_SFDLYSET2 0xf3d0 -#define FSTV0910_P2_SFEC_OFFSET 0xf3d000c0 -#define FSTV0910_P2_RST_SFEC 0xf3d00008 -#define FSTV0910_P2_DILDLINE_ERROR 0xf3d00004 #define FSTV0910_P2_SFEC_DISABLE 0xf3d00002 -#define FSTV0910_P2_SFEC_UNREGUL 0xf3d00001 /*P2_SFERRCTRL*/ #define RSTV0910_P2_SFERRCTRL 0xf3d8 @@ -1990,8 +2058,6 @@ /*P1_NOSCFG*/ #define RSTV0910_P1_NOSCFG 0xf401 -#define FSTV0910_P1_DIS_ACMRATIO 0xf4010080 -#define FSTV0910_P1_NOSIN_EGALSEL 0xf4010040 #define FSTV0910_P1_DUMMYPL_NOSDATA 0xf4010020 #define FSTV0910_P1_NOSPLH_BETA 0xf4010018 #define FSTV0910_P1_NOSDATA_BETA 0xf4010007 @@ -2012,14 +2078,10 @@ #define FSTV0910_P1_AMM_CORRECT 0xf4040010 #define FSTV0910_P1_QUAD_FROZEN 0xf4040008 #define FSTV0910_P1_QUAD_CORRECT 0xf4040004 -#define FSTV0910_P1_DCCOMP_SLOW 0xf4040002 -#define FSTV0910_P1_IQMISM_SLOW 0xf4040001 /*P1_AGC1CN*/ #define RSTV0910_P1_AGC1CN 0xf406 #define FSTV0910_P1_AGC1_LOCKED 0xf4060080 -#define FSTV0910_P1_AGC1_OVERFLOW 0xf4060040 -#define FSTV0910_P1_AGC1_NOSLOWLK 0xf4060020 #define FSTV0910_P1_AGC1_MINPOWER 0xf4060010 #define FSTV0910_P1_AGCOUT_FAST 0xf4060008 #define FSTV0910_P1_AGCIQ_BETA 0xf4060007 @@ -2077,16 +2139,12 @@ #define RSTV0910_P1_DSTATUS 0xf412 #define FSTV0910_P1_CAR_LOCK 0xf4120080 #define FSTV0910_P1_TMGLOCK_QUALITY 0xf4120060 -#define FSTV0910_P1_SDVBS1_ENABLE 0xf4120010 #define FSTV0910_P1_LOCK_DEFINITIF 0xf4120008 -#define FSTV0910_P1_TIMING_IS_LOCKED 0xf4120004 -#define FSTV0910_P1_DEMOD_SYSCFG 0xf4120002 #define FSTV0910_P1_OVADC_DETECT 0xf4120001 /*P1_DSTATUS2*/ #define RSTV0910_P1_DSTATUS2 0xf413 #define FSTV0910_P1_DEMOD_DELOCK 0xf4130080 -#define FSTV0910_P1_DEMOD_TIMEOUT 0xf4130040 #define FSTV0910_P1_MODCODRQ_SYNCTAG 0xf4130020 #define FSTV0910_P1_POLYPH_SATEVENT 0xf4130010 #define FSTV0910_P1_AGC1_NOSIGNALACK 0xf4130008 @@ -2100,25 +2158,16 @@ #define FSTV0910_P1_DVBS1_ENABLE 0xf4140040 #define FSTV0910_P1_SCAN_ENABLE 0xf4140010 #define FSTV0910_P1_CFR_AUTOSCAN 0xf4140008 -#define FSTV0910_P1_NOFORCE_RELOCK 0xf4140004 #define FSTV0910_P1_TUN_RNG 0xf4140003 /*P1_DMDCFG2*/ #define RSTV0910_P1_DMDCFG2 0xf415 -#define FSTV0910_P1_AGC1_WAITLOCK 0xf4150080 #define FSTV0910_P1_S1S2_SEQUENTIAL 0xf4150040 -#define FSTV0910_P1_BLINDPEA_MODE 0xf4150020 #define FSTV0910_P1_INFINITE_RELOCK 0xf4150010 -#define FSTV0910_P1_BWOFFSET_COLDWARM 0xf4150008 -#define FSTV0910_P1_TMGLOCK_NSCANSTOP 0xf4150004 -#define FSTV0910_P1_COARSE_LK3MODE 0xf4150002 -#define FSTV0910_P1_COARSE_LK2MODE 0xf4150001 /*P1_DMDISTATE*/ #define RSTV0910_P1_DMDISTATE 0xf416 #define FSTV0910_P1_I2C_NORESETDMODE 0xf4160080 -#define FSTV0910_P1_FORCE_ETAPED 0xf4160040 -#define FSTV0910_P1_SDMDRST_DIRCLK 0xf4160020 #define FSTV0910_P1_I2C_DEMOD_MODE 0xf416001f /*P1_DMDT0M*/ @@ -2127,9 +2176,7 @@ /*P1_DMDSTATE*/ #define RSTV0910_P1_DMDSTATE 0xf41b -#define FSTV0910_P1_DEMOD_LOCKED 0xf41b0080 #define FSTV0910_P1_HEADER_MODE 0xf41b0060 -#define FSTV0910_P1_DEMOD_MODE 0xf41b001f /*P1_DMDFLYW*/ #define RSTV0910_P1_DMDFLYW 0xf41c @@ -2141,29 +2188,15 @@ #define FSTV0910_P1_CFR_ZIGZAG 0xf41d0080 #define FSTV0910_P1_DEMOD_CFGMODE 0xf41d0060 #define FSTV0910_P1_GAMMA_LOWBAUDRATE 0xf41d0010 -#define FSTV0910_P1_RELOCK_MODE 0xf41d0008 -#define FSTV0910_P1_DEMOD_FAIL 0xf41d0004 -#define FSTV0910_P1_ETAPE1A_DVBXMEM 0xf41d0003 /*P1_DMDCFG3*/ #define RSTV0910_P1_DMDCFG3 0xf41e -#define FSTV0910_P1_DVBS1_TMGWAIT 0xf41e0080 -#define FSTV0910_P1_NO_BWCENTERING 0xf41e0040 -#define FSTV0910_P1_INV_SEQSRCH 0xf41e0020 -#define FSTV0910_P1_DIS_SFRUPLOW_TRK 0xf41e0010 #define FSTV0910_P1_NOSTOP_FIFOFULL 0xf41e0008 -#define FSTV0910_P1_LOCKTIME_MODE 0xf41e0007 /*P1_DMDCFG4*/ #define RSTV0910_P1_DMDCFG4 0xf41f #define FSTV0910_P1_DIS_VITLOCK 0xf41f0080 -#define FSTV0910_P1_S1S2TOUT_FAST 0xf41f0040 -#define FSTV0910_P1_DEMOD_FASTLOCK 0xf41f0020 -#define FSTV0910_P1_S1HIER_ENABLE 0xf41f0010 -#define FSTV0910_P1_TUNER_NRELAUNCH 0xf41f0008 #define FSTV0910_P1_DIS_CLKENABLE 0xf41f0004 -#define FSTV0910_P1_DIS_HDRDIVLOCK 0xf41f0002 -#define FSTV0910_P1_NO_TNRWBINIT 0xf41f0001 /*P1_CORRELMANT*/ #define RSTV0910_P1_CORRELMANT 0xf420 @@ -2186,16 +2219,45 @@ /*P1_DMDREG*/ #define RSTV0910_P1_DMDREG 0xf425 -#define FSTV0910_P1_EXTPSK_MODE 0xf4250080 -#define FSTV0910_P1_HIER_SHORTFRAME 0xf4250002 #define FSTV0910_P1_DECIM_PLFRAMES 0xf4250001 +/*P1_AGCNADJ*/ +#define RSTV0910_P1_AGCNADJ 0xf426 +#define FSTV0910_P1_RADJOFF_AGC2 0xf4260080 +#define FSTV0910_P1_RADJOFF_AGC1 0xf4260040 +#define FSTV0910_P1_AGC_NADJ 0xf426013f + +/*P1_AGCKS*/ +#define RSTV0910_P1_AGCKS 0xf427 +#define FSTV0910_P1_RSADJ_MANUALCFG 0xf4270080 +#define FSTV0910_P1_RSADJ_CCMMODE 0xf4270040 +#define FSTV0910_P1_RADJ_SPSK 0xf427013f + +/*P1_AGCKQ*/ +#define RSTV0910_P1_AGCKQ 0xf428 +#define FSTV0910_P1_RADJON_DVBS1 0xf4280040 +#define FSTV0910_P1_RADJ_QPSK 0xf428013f + +/*P1_AGCK8*/ +#define RSTV0910_P1_AGCK8 0xf429 +#define FSTV0910_P1_RADJ_8PSK 0xf429013f + +/*P1_AGCK16*/ +#define RSTV0910_P1_AGCK16 0xf42a +#define FSTV0910_P1_R2ADJOFF_16APSK 0xf42a0040 +#define FSTV0910_P1_R1ADJOFF_16APSK 0xf42a0020 +#define FSTV0910_P1_RADJ_16APSK 0xf42a011f + +/*P1_AGCK32*/ +#define RSTV0910_P1_AGCK32 0xf42b +#define FSTV0910_P1_R3ADJOFF_32APSK 0xf42b0080 +#define FSTV0910_P1_R2ADJOFF_32APSK 0xf42b0040 +#define FSTV0910_P1_R1ADJOFF_32APSK 0xf42b0020 +#define FSTV0910_P1_RADJ_32APSK 0xf42b011f + /*P1_AGC2O*/ #define RSTV0910_P1_AGC2O 0xf42c #define FSTV0910_P1_CSTENV_MODE 0xf42c00c0 -#define FSTV0910_P1_AGC2_LKSQRT 0xf42c0020 -#define FSTV0910_P1_AGC2_LKMODE 0xf42c0010 -#define FSTV0910_P1_AGC2_LKEQUA 0xf42c0008 #define FSTV0910_P1_AGC2_COEF 0xf42c0007 /*P1_AGC2REF*/ @@ -2204,9 +2266,36 @@ /*P1_AGC1ADJ*/ #define RSTV0910_P1_AGC1ADJ 0xf42e -#define FSTV0910_P1_AGC1ADJ_MANUAL 0xf42e0080 #define FSTV0910_P1_AGC1_ADJUSTED 0xf42e007f +/*P1_AGCRSADJ*/ +#define RSTV0910_P1_AGCRSADJ 0xf42f +#define FSTV0910_P1_RS_ADJUSTED 0xf42f007f + +/*P1_AGCRQADJ*/ +#define RSTV0910_P1_AGCRQADJ 0xf430 +#define FSTV0910_P1_RQ_ADJUSTED 0xf430007f + +/*P1_AGCR8ADJ*/ +#define RSTV0910_P1_AGCR8ADJ 0xf431 +#define FSTV0910_P1_R8_ADJUSTED 0xf431007f + +/*P1_AGCR1ADJ*/ +#define RSTV0910_P1_AGCR1ADJ 0xf432 +#define FSTV0910_P1_R1_ADJUSTED 0xf432007f + +/*P1_AGCR2ADJ*/ +#define RSTV0910_P1_AGCR2ADJ 0xf433 +#define FSTV0910_P1_R2_ADJUSTED 0xf433007f + +/*P1_AGCR3ADJ*/ +#define RSTV0910_P1_AGCR3ADJ 0xf434 +#define FSTV0910_P1_R3_ADJUSTED 0xf434007f + +/*P1_AGCREFADJ*/ +#define RSTV0910_P1_AGCREFADJ 0xf435 +#define FSTV0910_P1_AGC2REF_ADJUSTED 0xf435007f + /*P1_AGC2I1*/ #define RSTV0910_P1_AGC2I1 0xf436 #define FSTV0910_P1_AGC2_INTEGRATOR1 0xf43600ff @@ -2217,26 +2306,29 @@ /*P1_CARCFG*/ #define RSTV0910_P1_CARCFG 0xf438 -#define FSTV0910_P1_CFRUPLOW_AUTO 0xf4380080 -#define FSTV0910_P1_CFRUPLOW_TEST 0xf4380040 -#define FSTV0910_P1_WIDE_FREQDET 0xf4380020 -#define FSTV0910_P1_CARHDR_NODIV8 0xf4380010 -#define FSTV0910_P1_I2C_ROTA 0xf4380008 #define FSTV0910_P1_ROTAON 0xf4380004 #define FSTV0910_P1_PH_DET_ALGO 0xf4380003 /*P1_ACLC*/ #define RSTV0910_P1_ACLC 0xf439 -#define FSTV0910_P1_CARS1_ANOSAUTO 0xf4390040 #define FSTV0910_P1_CAR_ALPHA_MANT 0xf4390030 #define FSTV0910_P1_CAR_ALPHA_EXP 0xf439000f /*P1_BCLC*/ #define RSTV0910_P1_BCLC 0xf43a -#define FSTV0910_P1_CARS1_BNOSAUTO 0xf43a0040 #define FSTV0910_P1_CAR_BETA_MANT 0xf43a0030 #define FSTV0910_P1_CAR_BETA_EXP 0xf43a000f +/*P1_ACLCS2*/ +#define RSTV0910_P1_ACLCS2 0xf43b +#define FSTV0910_P1_CARS2_APLHA_MANTISSE 0xf43b0030 +#define FSTV0910_P1_CARS2_ALPHA_EXP 0xf43b000f + +/*P1_BCLCS2*/ +#define RSTV0910_P1_BCLCS2 0xf43c +#define FSTV0910_P1_CARS2_BETA_MANTISSE 0xf43c0030 +#define FSTV0910_P1_CARS2_BETA_EXP 0xf43c000f + /*P1_CARFREQ*/ #define RSTV0910_P1_CARFREQ 0xf43d #define FSTV0910_P1_KC_COARSE_EXP 0xf43d00f0 @@ -2256,13 +2348,6 @@ /*P1_CFRICFG*/ #define RSTV0910_P1_CFRICFG 0xf441 -#define FSTV0910_P1_CFRINIT_UNVALRNG 0xf4410080 -#define FSTV0910_P1_CFRINIT_LUNVALCPT 0xf4410040 -#define FSTV0910_P1_CFRINIT_ABORTDBL 0xf4410020 -#define FSTV0910_P1_CFRINIT_ABORTPRED 0xf4410010 -#define FSTV0910_P1_CFRINIT_UNVALSKIP 0xf4410008 -#define FSTV0910_P1_CFRINIT_CSTINC 0xf4410004 -#define FSTV0910_P1_CFRIROLL_GARDER 0xf4410002 #define FSTV0910_P1_NEG_CFRSTEP 0xf4410001 /*P1_CFRUP1*/ @@ -2326,7 +2411,6 @@ #define RSTV0910_P1_TMGCFG 0xf450 #define FSTV0910_P1_TMGLOCK_BETA 0xf45000c0 #define FSTV0910_P1_DO_TIMING_CORR 0xf4500010 -#define FSTV0910_P1_MANUAL_SCAN 0xf450000c #define FSTV0910_P1_TMG_MINFREQ 0xf4500003 /*P1_RTC*/ @@ -2370,10 +2454,7 @@ /*P1_TMGCFG2*/ #define RSTV0910_P1_TMGCFG2 0xf45a -#define FSTV0910_P1_KREFTMG2_DECMODE 0xf45a00c0 #define FSTV0910_P1_DIS_AUTOSAMP 0xf45a0008 -#define FSTV0910_P1_SCANINIT_QUART 0xf45a0004 -#define FSTV0910_P1_NOTMG_DVBS1DERAT 0xf45a0002 #define FSTV0910_P1_SFRRATIO_FINE 0xf45a0001 /*P1_KREFTMG2*/ @@ -2382,11 +2463,9 @@ /*P1_TMGCFG3*/ #define RSTV0910_P1_TMGCFG3 0xf45d -#define FSTV0910_P1_CFRINC_MODE 0xf45d0070 #define FSTV0910_P1_CONT_TMGCENTER 0xf45d0008 #define FSTV0910_P1_AUTO_GUP 0xf45d0004 #define FSTV0910_P1_AUTO_GLOW 0xf45d0002 -#define FSTV0910_P1_SFRVAL_MINMODE 0xf45d0001 /*P1_SFRINIT1*/ #define RSTV0910_P1_SFRINIT1 0xf45e @@ -2451,16 +2530,10 @@ /*P1_TMGOBS*/ #define RSTV0910_P1_TMGOBS 0xf46d #define FSTV0910_P1_ROLLOFF_STATUS 0xf46d00c0 -#define FSTV0910_P1_SCAN_SIGN 0xf46d0030 -#define FSTV0910_P1_TMG_SCANNING 0xf46d0008 -#define FSTV0910_P1_CHCENTERING_MODE 0xf46d0004 -#define FSTV0910_P1_TMG_SCANFAIL 0xf46d0002 /*P1_EQUALCFG*/ #define RSTV0910_P1_EQUALCFG 0xf46f -#define FSTV0910_P1_NOTMG_NEGALWAIT 0xf46f0080 #define FSTV0910_P1_EQUAL_ON 0xf46f0040 -#define FSTV0910_P1_SEL_EQUALCOR 0xf46f0038 #define FSTV0910_P1_MU_EQUALDFE 0xf46f0007 /*P1_EQUAI1*/ @@ -2591,20 +2664,20 @@ #define FSTV0910_P1_FRAMESEL_TYPESEL 0xf48e000c #define FSTV0910_P1_FRAMESEL_TYPE 0xf48e0003 +/*P1_NOSCFGF2*/ +#define RSTV0910_P1_NOSCFGF2 0xf48f +#define FSTV0910_P1_DIS_NOSPILOTS 0xf48f0080 +#define FSTV0910_P1_FRAMESEL_MODCODSEL 0xf48f0060 +#define FSTV0910_P1_FRAMESEL_MODCOD 0xf48f001f + /*P1_CAR2CFG*/ #define RSTV0910_P1_CAR2CFG 0xf490 -#define FSTV0910_P1_DESCRAMB_OFF 0xf4900080 -#define FSTV0910_P1_EN_PHNOSRAM 0xf4900020 -#define FSTV0910_P1_STOP_CFR2UPDATE 0xf4900010 -#define FSTV0910_P1_STOP_NCO2UPDATE 0xf4900008 #define FSTV0910_P1_ROTA2ON 0xf4900004 #define FSTV0910_P1_PH_DET_ALGO2 0xf4900003 /*P1_CFR2CFR1*/ #define RSTV0910_P1_CFR2CFR1 0xf491 -#define FSTV0910_P1_CFR2_S2CONTROL 0xf49100c0 #define FSTV0910_P1_EN_S2CAR2CENTER 0xf4910020 -#define FSTV0910_P1_BCHERRCFR2_MODE 0xf4910018 #define FSTV0910_P1_CFR2TOCFR1_BETA 0xf4910007 /*P1_CAR3CFG*/ @@ -2629,48 +2702,48 @@ /*P1_ACLC2S2Q*/ #define RSTV0910_P1_ACLC2S2Q 0xf497 #define FSTV0910_P1_ENAB_SPSKSYMB 0xf4970080 -#define FSTV0910_P1_CAR2S2_QANOSAUTO 0xf4970040 #define FSTV0910_P1_CAR2S2_Q_ALPH_M 0xf4970030 #define FSTV0910_P1_CAR2S2_Q_ALPH_E 0xf497000f /*P1_ACLC2S28*/ #define RSTV0910_P1_ACLC2S28 0xf498 -#define FSTV0910_P1_OLDI3Q_MODE 0xf4980080 -#define FSTV0910_P1_CAR2S2_8ANOSAUTO 0xf4980040 #define FSTV0910_P1_CAR2S2_8_ALPH_M 0xf4980030 #define FSTV0910_P1_CAR2S2_8_ALPH_E 0xf498000f /*P1_ACLC2S216A*/ #define RSTV0910_P1_ACLC2S216A 0xf499 -#define FSTV0910_P1_CAR2S2_16ANOSAUTO 0xf4990040 #define FSTV0910_P1_CAR2S2_16A_ALPH_M 0xf4990030 #define FSTV0910_P1_CAR2S2_16A_ALPH_E 0xf499000f /*P1_ACLC2S232A*/ #define RSTV0910_P1_ACLC2S232A 0xf49a -#define FSTV0910_P1_CAR2S2_32ANOSUATO 0xf49a0040 #define FSTV0910_P1_CAR2S2_32A_ALPH_M 0xf49a0030 #define FSTV0910_P1_CAR2S2_32A_ALPH_E 0xf49a000f /*P1_BCLC2S2Q*/ #define RSTV0910_P1_BCLC2S2Q 0xf49c -#define FSTV0910_P1_DVBS2S2Q_NIP 0xf49c0080 -#define FSTV0910_P1_CAR2S2_QBNOSAUTO 0xf49c0040 #define FSTV0910_P1_CAR2S2_Q_BETA_M 0xf49c0030 #define FSTV0910_P1_CAR2S2_Q_BETA_E 0xf49c000f /*P1_BCLC2S28*/ #define RSTV0910_P1_BCLC2S28 0xf49d -#define FSTV0910_P1_DVBS2S28_NIP 0xf49d0080 -#define FSTV0910_P1_CAR2S2_8BNOSAUTO 0xf49d0040 #define FSTV0910_P1_CAR2S2_8_BETA_M 0xf49d0030 #define FSTV0910_P1_CAR2S2_8_BETA_E 0xf49d000f +/*P1_BCLC2S216A*/ +#define RSTV0910_P1_BCLC2S216A 0xf49e +#define FSTV0910_P1_DVBS2S216A_NIP 0xf49e0080 +#define FSTV0910_P1_CAR2S2_16A_BETA_M 0xf49e0030 +#define FSTV0910_P1_CAR2S2_16A_BETA_E 0xf49e000f + +/*P1_BCLC2S232A*/ +#define RSTV0910_P1_BCLC2S232A 0xf49f +#define FSTV0910_P1_DVBS2S232A_NIP 0xf49f0080 +#define FSTV0910_P1_CAR2S2_32A_BETA_M 0xf49f0030 +#define FSTV0910_P1_CAR2S2_32A_BETA_E 0xf49f000f + /*P1_PLROOT2*/ #define RSTV0910_P1_PLROOT2 0xf4ac -#define FSTV0910_P1_PLHAUTO_DISPLH 0xf4ac0040 -#define FSTV0910_P1_PLHAUTO_FASTMODE 0xf4ac0020 -#define FSTV0910_P1_PLHAUTO_ENABLE 0xf4ac0010 #define FSTV0910_P1_PLSCRAMB_MODE 0xf4ac000c #define FSTV0910_P1_PLSCRAMB_ROOT2 0xf4ac0003 @@ -2682,45 +2755,93 @@ #define RSTV0910_P1_PLROOT0 0xf4ae #define FSTV0910_P1_PLSCRAMB_ROOT0 0xf4ae00ff +/*P1_MODCODLST0*/ +#define RSTV0910_P1_MODCODLST0 0xf4b0 +#define FSTV0910_P1_NACCES_MODCODCH 0xf4b00001 + +/*P1_MODCODLST1*/ +#define RSTV0910_P1_MODCODLST1 0xf4b1 +#define FSTV0910_P1_SYMBRATE_FILTER 0xf4b10008 +#define FSTV0910_P1_NRESET_MODCODLST 0xf4b10004 +#define FSTV0910_P1_DIS_32PSK_9_10 0xf4b10003 + +/*P1_MODCODLST2*/ +#define RSTV0910_P1_MODCODLST2 0xf4b2 +#define FSTV0910_P1_DIS_32PSK_8_9 0xf4b200f0 +#define FSTV0910_P1_DIS_32PSK_5_6 0xf4b2000f + +/*P1_MODCODLST3*/ +#define RSTV0910_P1_MODCODLST3 0xf4b3 +#define FSTV0910_P1_DIS_32PSK_4_5 0xf4b300f0 +#define FSTV0910_P1_DIS_32PSK_3_4 0xf4b3000f + +/*P1_MODCODLST4*/ +#define RSTV0910_P1_MODCODLST4 0xf4b4 +#define FSTV0910_P1_DUMMYPL_PILOT 0xf4b40080 +#define FSTV0910_P1_DUMMYPL_NOPILOT 0xf4b40040 +#define FSTV0910_P1_DIS_16PSK_9_10 0xf4b40030 +#define FSTV0910_P1_DIS_16PSK_8_9 0xf4b4000f + +/*P1_MODCODLST5*/ +#define RSTV0910_P1_MODCODLST5 0xf4b5 +#define FSTV0910_P1_DIS_16PSK_5_6 0xf4b500f0 +#define FSTV0910_P1_DIS_16PSK_4_5 0xf4b5000f + +/*P1_MODCODLST6*/ +#define RSTV0910_P1_MODCODLST6 0xf4b6 +#define FSTV0910_P1_DIS_16PSK_3_4 0xf4b600f0 +#define FSTV0910_P1_DIS_16PSK_2_3 0xf4b6000f + /*P1_MODCODLST7*/ #define RSTV0910_P1_MODCODLST7 0xf4b7 #define FSTV0910_P1_MODCOD_NNOSFILTER 0xf4b70080 -#define FSTV0910_P1_MODCODLST_NOSTYPE 0xf4b70040 #define FSTV0910_P1_DIS_8PSK_9_10 0xf4b70030 -#define FSTV0910_P1_DIS_8P_8_9 0xf4b7000f +#define FSTV0910_P1_DIS_8PSK_8_9 0xf4b7000f /*P1_MODCODLST8*/ #define RSTV0910_P1_MODCODLST8 0xf4b8 -#define FSTV0910_P1_DIS_8P_5_6 0xf4b800f0 -#define FSTV0910_P1_DIS_8P_3_4 0xf4b8000f +#define FSTV0910_P1_DIS_8PSK_5_6 0xf4b800f0 +#define FSTV0910_P1_DIS_8PSK_3_4 0xf4b8000f /*P1_MODCODLST9*/ #define RSTV0910_P1_MODCODLST9 0xf4b9 -#define FSTV0910_P1_DIS_8P_2_3 0xf4b900f0 -#define FSTV0910_P1_DIS_8P_3_5 0xf4b9000f +#define FSTV0910_P1_DIS_8PSK_2_3 0xf4b900f0 +#define FSTV0910_P1_DIS_8PSK_3_5 0xf4b9000f /*P1_MODCODLSTA*/ #define RSTV0910_P1_MODCODLSTA 0xf4ba #define FSTV0910_P1_NOSFILTER_LIMITE 0xf4ba0080 -#define FSTV0910_P1_NOSFILTER_MODE 0xf4ba0040 #define FSTV0910_P1_DIS_QPSK_9_10 0xf4ba0030 -#define FSTV0910_P1_DIS_QP_8_9 0xf4ba000f +#define FSTV0910_P1_DIS_QPSK_8_9 0xf4ba000f /*P1_MODCODLSTB*/ #define RSTV0910_P1_MODCODLSTB 0xf4bb -#define FSTV0910_P1_DIS_QP_5_6 0xf4bb00f0 -#define FSTV0910_P1_DIS_QP_4_5 0xf4bb000f +#define FSTV0910_P1_DIS_QPSK_5_6 0xf4bb00f0 +#define FSTV0910_P1_DIS_QPSK_4_5 0xf4bb000f /*P1_MODCODLSTC*/ #define RSTV0910_P1_MODCODLSTC 0xf4bc -#define FSTV0910_P1_DIS_QP_3_4 0xf4bc00f0 -#define FSTV0910_P1_DIS_QP_2_3 0xf4bc000f +#define FSTV0910_P1_DIS_QPSK_3_4 0xf4bc00f0 +#define FSTV0910_P1_DIS_QPSK_2_3 0xf4bc000f /*P1_MODCODLSTD*/ #define RSTV0910_P1_MODCODLSTD 0xf4bd #define FSTV0910_P1_DIS_QPSK_3_5 0xf4bd00f0 #define FSTV0910_P1_DIS_QPSK_1_2 0xf4bd000f +/*P1_MODCODLSTE*/ +#define RSTV0910_P1_MODCODLSTE 0xf4be +#define FSTV0910_P1_DIS_QPSK_2_5 0xf4be00f0 +#define FSTV0910_P1_DIS_QPSK_1_3 0xf4be000f + +/*P1_MODCODLSTF*/ +#define RSTV0910_P1_MODCODLSTF 0xf4bf +#define FSTV0910_P1_DIS_QPSK_1_4 0xf4bf00f0 +#define FSTV0910_P1_DEMOD_INVMODLST 0xf4bf0008 +#define FSTV0910_P1_DEMODOUT_ENABLE 0xf4bf0004 +#define FSTV0910_P1_DDEMOD_NSET 0xf4bf0002 +#define FSTV0910_P1_MODCOD_NSTOCK 0xf4bf0001 + /*P1_GAUSSR0*/ #define RSTV0910_P1_GAUSSR0 0xf4c0 #define FSTV0910_P1_EN_CCIMODE 0xf4c00080 @@ -2749,8 +2870,6 @@ #define FSTV0910_P1_RAINFADE_DETECT 0xf4c50080 #define FSTV0910_P1_NOTHRES2_FAIL 0xf4c50040 #define FSTV0910_P1_NOTHRES1_FAIL 0xf4c50020 -#define FSTV0910_P1_PILOT_FAILDETECT 0xf4c50010 -#define FSTV0910_P1_HIER_DETECT 0xf4c50008 #define FSTV0910_P1_DMDPROG_ERROR 0xf4c50004 #define FSTV0910_P1_CSTENV_DETECT 0xf4c50002 #define FSTV0910_P1_DETECTION_TRIAX 0xf4c50001 @@ -2758,15 +2877,12 @@ /*P1_DMDRESCFG*/ #define RSTV0910_P1_DMDRESCFG 0xf4c6 #define FSTV0910_P1_DMDRES_RESET 0xf4c60080 -#define FSTV0910_P1_DMDRES_NOISESQR 0xf4c60010 #define FSTV0910_P1_DMDRES_STRALL 0xf4c60008 #define FSTV0910_P1_DMDRES_NEWONLY 0xf4c60004 #define FSTV0910_P1_DMDRES_NOSTORE 0xf4c60002 -#define FSTV0910_P1_DMDRES_AGC2MEM 0xf4c60001 /*P1_DMDRESADR*/ #define RSTV0910_P1_DMDRESADR 0xf4c7 -#define FSTV0910_P1_SUSP_PREDCANAL 0xf4c70080 #define FSTV0910_P1_DMDRES_VALIDCFR 0xf4c70040 #define FSTV0910_P1_DMDRES_MEMFULL 0xf4c70030 #define FSTV0910_P1_DMDRES_RESNBR 0xf4c7000f @@ -2844,13 +2960,6 @@ /*P1_TNRCFG2*/ #define RSTV0910_P1_TNRCFG2 0xf4e1 #define FSTV0910_P1_TUN_IQSWAP 0xf4e10080 -#define FSTV0910_P1_STB6110_STEP2MHZ 0xf4e10040 -#define FSTV0910_P1_STB6120_DBLI2C 0xf4e10020 -#define FSTV0910_P1_TUNER_WIDEBAND 0xf4e10010 -#define FSTV0910_P1_TUNER_OBSPAGE 0xf4e10008 -#define FSTV0910_P1_DIS_BWCALC 0xf4e10004 -#define FSTV0910_P1_SHORT_WAITSTATES 0xf4e10002 -#define FSTV0910_P1_DIS_2BWAGC1 0xf4e10001 /*P1_SMAPCOEF7*/ #define RSTV0910_P1_SMAPCOEF7 0xf500 @@ -2860,10 +2969,6 @@ /*P1_SMAPCOEF6*/ #define RSTV0910_P1_SMAPCOEF6 0xf501 #define FSTV0910_P1_DIS_AGC2SCALE 0xf5010080 -#define FSTV0910_P1_DIS_16IQMULT 0xf5010040 -#define FSTV0910_P1_OLD_16APSK47 0xf5010020 -#define FSTV0910_P1_OLD_16APSK12 0xf5010010 -#define FSTV0910_P1_DIS_NEWSCALE 0xf5010008 #define FSTV0910_P1_ADJ_8PSKLLR1 0xf5010004 #define FSTV0910_P1_OLD_8PSKLLR1 0xf5010002 #define FSTV0910_P1_DIS_AB8PSK 0xf5010001 @@ -2873,6 +2978,29 @@ #define FSTV0910_P1_DIS_8SCALE 0xf5020080 #define FSTV0910_P1_SMAPCOEF_8P_LLR23 0xf502017f +/*P1_SMAPCOEF4*/ +#define RSTV0910_P1_SMAPCOEF4 0xf503 +#define FSTV0910_P1_SMAPCOEF_16APSK_LLR12 0xf503017f + +/*P1_SMAPCOEF3*/ +#define RSTV0910_P1_SMAPCOEF3 0xf504 +#define FSTV0910_P1_SMAPCOEF_16APSK_LLR34 0xf504017f + +/*P1_SMAPCOEF2*/ +#define RSTV0910_P1_SMAPCOEF2 0xf505 +#define FSTV0910_P1_SMAPCOEF_32APSK_R2R3 0xf50501f0 +#define FSTV0910_P1_SMAPCOEF_32APSK_LLR2 0xf505010f + +/*P1_SMAPCOEF1*/ +#define RSTV0910_P1_SMAPCOEF1 0xf506 +#define FSTV0910_P1_DIS_16SCALE 0xf5060080 +#define FSTV0910_P1_SMAPCOEF_32_LLR34 0xf506017f + +/*P1_SMAPCOEF0*/ +#define RSTV0910_P1_SMAPCOEF0 0xf507 +#define FSTV0910_P1_DIS_32SCALE 0xf5070080 +#define FSTV0910_P1_SMAPCOEF_32_LLR15 0xf507017f + /*P1_NOSTHRES1*/ #define RSTV0910_P1_NOSTHRES1 0xf509 #define FSTV0910_P1_NOS_THRESHOLD1 0xf50900ff @@ -2893,8 +3021,6 @@ /*P1_NOSRAMCFG*/ #define RSTV0910_P1_NOSRAMCFG 0xf50d -#define FSTV0910_P1_NOSRAM_DVBS2DATA 0xf50d0080 -#define FSTV0910_P1_NOSRAM_QUADRAT 0xf50d0040 #define FSTV0910_P1_NOSRAM_ACTIVATION 0xf50d0030 #define FSTV0910_P1_NOSRAM_CNRONLY 0xf50d0008 #define FSTV0910_P1_NOSRAM_LGNCNR1 0xf50d0007 @@ -2933,18 +3059,13 @@ #define RSTV0910_P1_VITSCALE 0xf532 #define FSTV0910_P1_NVTH_NOSRANGE 0xf5320080 #define FSTV0910_P1_VERROR_MAXMODE 0xf5320040 -#define FSTV0910_P1_KDIV_MODE 0xf5320030 #define FSTV0910_P1_NSLOWSN_LOCKED 0xf5320008 -#define FSTV0910_P1_DELOCK_PRFLOSS 0xf5320004 #define FSTV0910_P1_DIS_RSFLOCK 0xf5320002 /*P1_FECM*/ #define RSTV0910_P1_FECM 0xf533 #define FSTV0910_P1_DSS_DVB 0xf5330080 -#define FSTV0910_P1_DEMOD_BYPASS 0xf5330040 -#define FSTV0910_P1_CMP_SLOWMODE 0xf5330020 #define FSTV0910_P1_DSS_SRCH 0xf5330010 -#define FSTV0910_P1_DIFF_MODEVIT 0xf5330004 #define FSTV0910_P1_SYNCVIT 0xf5330002 #define FSTV0910_P1_IQINV 0xf5330001 @@ -2974,9 +3095,6 @@ /*P1_VITCURPUN*/ #define RSTV0910_P1_VITCURPUN 0xf53a -#define FSTV0910_P1_CYCLESLIP_VIT 0xf53a0080 -#define FSTV0910_P1_VIT_ROTA180 0xf53a0040 -#define FSTV0910_P1_VIT_ROTA90 0xf53a0020 #define FSTV0910_P1_VIT_CURPUN 0xf53a001f /*P1_VERROR*/ @@ -3003,14 +3121,8 @@ /*P1_VSTATUSVIT*/ #define RSTV0910_P1_VSTATUSVIT 0xf53e -#define FSTV0910_P1_VITERBI_ON 0xf53e0080 -#define FSTV0910_P1_END_LOOPVIT 0xf53e0040 -#define FSTV0910_P1_VITERBI_DEPRF 0xf53e0020 #define FSTV0910_P1_PRFVIT 0xf53e0010 #define FSTV0910_P1_LOCKEDVIT 0xf53e0008 -#define FSTV0910_P1_VITERBI_DELOCK 0xf53e0004 -#define FSTV0910_P1_VIT_DEMODSEL 0xf53e0002 -#define FSTV0910_P1_VITERBI_COMPOUT 0xf53e0001 /*P1_VTHINUSE*/ #define RSTV0910_P1_VTHINUSE 0xf53f @@ -3018,45 +3130,44 @@ /*P1_KDIV12*/ #define RSTV0910_P1_KDIV12 0xf540 -#define FSTV0910_P1_KDIV12_MANUAL 0xf5400080 #define FSTV0910_P1_K_DIVIDER_12 0xf540007f /*P1_KDIV23*/ #define RSTV0910_P1_KDIV23 0xf541 -#define FSTV0910_P1_KDIV23_MANUAL 0xf5410080 #define FSTV0910_P1_K_DIVIDER_23 0xf541007f /*P1_KDIV34*/ #define RSTV0910_P1_KDIV34 0xf542 -#define FSTV0910_P1_KDIV34_MANUAL 0xf5420080 #define FSTV0910_P1_K_DIVIDER_34 0xf542007f /*P1_KDIV56*/ #define RSTV0910_P1_KDIV56 0xf543 -#define FSTV0910_P1_KDIV56_MANUAL 0xf5430080 #define FSTV0910_P1_K_DIVIDER_56 0xf543007f /*P1_KDIV67*/ #define RSTV0910_P1_KDIV67 0xf544 -#define FSTV0910_P1_KDIV67_MANUAL 0xf5440080 #define FSTV0910_P1_K_DIVIDER_67 0xf544007f /*P1_KDIV78*/ #define RSTV0910_P1_KDIV78 0xf545 -#define FSTV0910_P1_KDIV78_MANUAL 0xf5450080 #define FSTV0910_P1_K_DIVIDER_78 0xf545007f +/*P1_TSPIDFLT1*/ +#define RSTV0910_P1_TSPIDFLT1 0xf546 +#define FSTV0910_P1_PIDFLT_ADDR 0xf54600ff + +/*P1_TSPIDFLT0*/ +#define RSTV0910_P1_TSPIDFLT0 0xf547 +#define FSTV0910_P1_PIDFLT_DATA 0xf54700ff + /*P1_PDELCTRL0*/ #define RSTV0910_P1_PDELCTRL0 0xf54f #define FSTV0910_P1_ISIOBS_MODE 0xf54f0030 -#define FSTV0910_P1_PDELDIS_BITWISE 0xf54f0004 /*P1_PDELCTRL1*/ #define RSTV0910_P1_PDELCTRL1 0xf550 #define FSTV0910_P1_INV_MISMASK 0xf5500080 -#define FSTV0910_P1_FORCE_ACCEPTED 0xf5500040 #define FSTV0910_P1_FILTER_EN 0xf5500020 -#define FSTV0910_P1_FORCE_PKTDELINUSE 0xf5500010 #define FSTV0910_P1_HYSTEN 0xf5500008 #define FSTV0910_P1_HYSTSWRST 0xf5500004 #define FSTV0910_P1_EN_MIS00 0xf5500002 @@ -3067,8 +3178,6 @@ #define FSTV0910_P1_FORCE_CONTINUOUS 0xf5510080 #define FSTV0910_P1_RESET_UPKO_COUNT 0xf5510040 #define FSTV0910_P1_USER_PKTDELIN_NB 0xf5510020 -#define FSTV0910_P1_DATA_UNBBSCRAMBLED 0xf5510008 -#define FSTV0910_P1_FORCE_LONGPKT 0xf5510004 #define FSTV0910_P1_FRAME_MODE 0xf5510002 /*P1_HYSTTHRESH*/ @@ -3076,6 +3185,11 @@ #define FSTV0910_P1_DELIN_LOCKTHRES 0xf55400f0 #define FSTV0910_P1_DELIN_UNLOCKTHRES 0xf554000f +/*P1_UPLCCST0*/ +#define RSTV0910_P1_UPLCCST0 0xf558 +#define FSTV0910_P1_UPL_CST0 0xf55800f8 +#define FSTV0910_P1_UPL_MODE 0xf5580007 + /*P1_ISIENTRY*/ #define RSTV0910_P1_ISIENTRY 0xf55e #define FSTV0910_P1_ISI_ENTRY 0xf55e00ff @@ -3124,16 +3238,13 @@ #define RSTV0910_P1_PDELSTATUS1 0xf569 #define FSTV0910_P1_PKTDELIN_DELOCK 0xf5690080 #define FSTV0910_P1_SYNCDUPDFL_BADDFL 0xf5690040 -#define FSTV0910_P1_CONTINUOUS_STREAM 0xf5690020 #define FSTV0910_P1_UNACCEPTED_STREAM 0xf5690010 #define FSTV0910_P1_BCH_ERROR_FLAG 0xf5690008 -#define FSTV0910_P1_BBHCRCKO 0xf5690004 #define FSTV0910_P1_PKTDELIN_LOCK 0xf5690002 #define FSTV0910_P1_FIRST_LOCK 0xf5690001 /*P1_PDELSTATUS2*/ #define RSTV0910_P1_PDELSTATUS2 0xf56a -#define FSTV0910_P1_PKTDEL_DEMODSEL 0xf56a0080 #define FSTV0910_P1_FRAME_MODCOD 0xf56a007c #define FSTV0910_P1_FRAME_TYPE 0xf56a0003 @@ -3155,18 +3266,12 @@ /*P1_PDELCTRL3*/ #define RSTV0910_P1_PDELCTRL3 0xf56f -#define FSTV0910_P1_PKTDEL_CONTFAIL 0xf56f0080 -#define FSTV0910_P1_PKTDEL_ENLONGPKT 0xf56f0040 #define FSTV0910_P1_NOFIFO_BCHERR 0xf56f0020 #define FSTV0910_P1_PKTDELIN_DELACMERR 0xf56f0010 -#define FSTV0910_P1_SATURATE_BBPKTKO 0xf56f0004 -#define FSTV0910_P1_PKTDEL_BCHERRCONT 0xf56f0002 -#define FSTV0910_P1_ETHERNET_DISFCS 0xf56f0001 /*P1_TSSTATEM*/ #define RSTV0910_P1_TSSTATEM 0xf570 #define FSTV0910_P1_TSDIL_ON 0xf5700080 -#define FSTV0910_P1_TSSKIPRS_ON 0xf5700040 #define FSTV0910_P1_TSRS_ON 0xf5700020 #define FSTV0910_P1_TSDESCRAMB_ON 0xf5700010 #define FSTV0910_P1_TSFRAME_MODE 0xf5700008 @@ -3174,6 +3279,15 @@ #define FSTV0910_P1_TSACM_MODE 0xf5700002 #define FSTV0910_P1_TSOUT_NOSYNC 0xf5700001 +/*P1_TSSTATEL*/ +#define RSTV0910_P1_TSSTATEL 0xf571 +#define FSTV0910_P1_TSNOSYNCBYTE 0xf5710080 +#define FSTV0910_P1_TSPARITY_ON 0xf5710040 +#define FSTV0910_P1_TSISSYI_ON 0xf5710008 +#define FSTV0910_P1_TSNPD_ON 0xf5710004 +#define FSTV0910_P1_TSCRC8_ON 0xf5710002 +#define FSTV0910_P1_TSDSS_PACKET 0xf5710001 + /*P1_TSCFGH*/ #define RSTV0910_P1_TSCFGH 0xf572 #define FSTV0910_P1_TSFIFO_DVBCI 0xf5720080 @@ -3189,8 +3303,6 @@ #define FSTV0910_P1_TSFIFO_MANSPEED 0xf57300c0 #define FSTV0910_P1_TSFIFO_PERMDATA 0xf5730020 #define FSTV0910_P1_TSFIFO_NONEWSGNL 0xf5730010 -#define FSTV0910_P1_NPD_SPECDVBS2 0xf5730004 -#define FSTV0910_P1_TSFIFO_DPUNACTIVE 0xf5730002 #define FSTV0910_P1_TSFIFO_INVDATA 0xf5730001 /*P1_TSCFGL*/ @@ -3201,32 +3313,45 @@ #define FSTV0910_P1_TSFIFO_EMBINDVB 0xf5740004 #define FSTV0910_P1_TSFIFO_BITSPEED 0xf5740003 +/*P1_TSSYNC*/ +#define RSTV0910_P1_TSSYNC 0xf575 +#define FSTV0910_P1_TSFIFO_SYNCMODE 0xf5750018 + /*P1_TSINSDELH*/ #define RSTV0910_P1_TSINSDELH 0xf576 #define FSTV0910_P1_TSDEL_SYNCBYTE 0xf5760080 #define FSTV0910_P1_TSDEL_XXHEADER 0xf5760040 -#define FSTV0910_P1_TSDEL_BBHEADER 0xf5760020 #define FSTV0910_P1_TSDEL_DATAFIELD 0xf5760010 -#define FSTV0910_P1_TSINSDEL_ISCR 0xf5760008 -#define FSTV0910_P1_TSINSDEL_NPD 0xf5760004 #define FSTV0910_P1_TSINSDEL_RSPARITY 0xf5760002 #define FSTV0910_P1_TSINSDEL_CRC8 0xf5760001 +/*P1_TSINSDELM*/ +#define RSTV0910_P1_TSINSDELM 0xf577 +#define FSTV0910_P1_TSINS_EMODCOD 0xf5770010 +#define FSTV0910_P1_TSINS_TOKEN 0xf5770008 +#define FSTV0910_P1_TSINS_XXXERR 0xf5770004 +#define FSTV0910_P1_TSINS_MATYPE 0xf5770002 +#define FSTV0910_P1_TSINS_UPL 0xf5770001 + +/*P1_TSINSDELL*/ +#define RSTV0910_P1_TSINSDELL 0xf578 +#define FSTV0910_P1_TSINS_DFL 0xf5780080 +#define FSTV0910_P1_TSINS_SYNCD 0xf5780040 +#define FSTV0910_P1_TSINS_BLOCLEN 0xf5780020 +#define FSTV0910_P1_TSINS_SIGPCOUNT 0xf5780010 +#define FSTV0910_P1_TSINS_FIFO 0xf5780008 +#define FSTV0910_P1_TSINS_REALPACK 0xf5780004 +#define FSTV0910_P1_TSINS_TSCONFIG 0xf5780002 +#define FSTV0910_P1_TSINS_LATENCY 0xf5780001 + /*P1_TSDIVN*/ #define RSTV0910_P1_TSDIVN 0xf579 #define FSTV0910_P1_TSFIFO_SPEEDMODE 0xf57900c0 -#define FSTV0910_P1_BYTE_OVERSAMPLING 0xf5790038 #define FSTV0910_P1_TSFIFO_RISEOK 0xf5790007 /*P1_TSCFG4*/ #define RSTV0910_P1_TSCFG4 0xf57a #define FSTV0910_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0 -#define FSTV0910_P1_TSFIFO_HIERSEL 0xf57a0020 -#define FSTV0910_P1_TSFIFO_SPECTOKEN 0xf57a0010 -#define FSTV0910_P1_TSFIFO_MAXMODE 0xf57a0008 -#define FSTV0910_P1_TSFIFO_FRFORCEPKT 0xf57a0004 -#define FSTV0910_P1_EXT_FECSPYIN 0xf57a0002 -#define FSTV0910_P1_TSFIFO_DELSPEEDUP 0xf57a0001 /*P1_TSSPEED*/ #define RSTV0910_P1_TSSPEED 0xf580 @@ -3236,11 +3361,8 @@ #define RSTV0910_P1_TSSTATUS 0xf581 #define FSTV0910_P1_TSFIFO_LINEOK 0xf5810080 #define FSTV0910_P1_TSFIFO_ERROR 0xf5810040 -#define FSTV0910_P1_TSFIFO_DATA7 0xf5810020 #define FSTV0910_P1_TSFIFO_NOSYNC 0xf5810010 -#define FSTV0910_P1_ISCR_INITIALIZED 0xf5810008 #define FSTV0910_P1_TSREGUL_ERROR 0xf5810004 -#define FSTV0910_P1_SOFFIFO_UNREGUL 0xf5810002 #define FSTV0910_P1_DIL_READY 0xf5810001 /*P1_TSSTATUS2*/ @@ -3248,11 +3370,7 @@ #define FSTV0910_P1_TSFIFO_DEMODSEL 0xf5820080 #define FSTV0910_P1_TSFIFOSPEED_STORE 0xf5820040 #define FSTV0910_P1_DILXX_RESET 0xf5820020 -#define FSTV0910_P1_TSSPEED_IMPOSSIBLE 0xf5820010 -#define FSTV0910_P1_TSFIFO_LINENOK 0xf5820008 -#define FSTV0910_P1_TSFIFO_MUXSTREAM 0xf5820004 #define FSTV0910_P1_SCRAMBDETECT 0xf5820002 -#define FSTV0910_P1_ULDTV67_FALSELOCK 0xf5820001 /*P1_TSBITRATE1*/ #define RSTV0910_P1_TSBITRATE1 0xf583 @@ -3262,6 +3380,59 @@ #define RSTV0910_P1_TSBITRATE0 0xf584 #define FSTV0910_P1_TSFIFO_BITRATE0 0xf58400ff +/*P1_TSPACKLEN1*/ +#define RSTV0910_P1_TSPACKLEN1 0xf585 +#define FSTV0910_P1_TSFIFO_PACKCPT 0xf58500e0 + +/*P1_TSDLY2*/ +#define RSTV0910_P1_TSDLY2 0xf589 +#define FSTV0910_P1_SOFFIFO_LATENCY2 0xf589000f + +/*P1_TSDLY1*/ +#define RSTV0910_P1_TSDLY1 0xf58a +#define FSTV0910_P1_SOFFIFO_LATENCY1 0xf58a00ff + +/*P1_TSDLY0*/ +#define RSTV0910_P1_TSDLY0 0xf58b +#define FSTV0910_P1_SOFFIFO_LATENCY0 0xf58b00ff + +/*P1_TSNPDAV*/ +#define RSTV0910_P1_TSNPDAV 0xf58c +#define FSTV0910_P1_TSNPD_AVERAGE 0xf58c00ff + +/*P1_TSBUFSTAT2*/ +#define RSTV0910_P1_TSBUFSTAT2 0xf58d +#define FSTV0910_P1_TSISCR_3BYTES 0xf58d0080 +#define FSTV0910_P1_TSISCR_NEWDATA 0xf58d0040 +#define FSTV0910_P1_TSISCR_BUFSTAT2 0xf58d003f + +/*P1_TSBUFSTAT1*/ +#define RSTV0910_P1_TSBUFSTAT1 0xf58e +#define FSTV0910_P1_TSISCR_BUFSTAT1 0xf58e00ff + +/*P1_TSBUFSTAT0*/ +#define RSTV0910_P1_TSBUFSTAT0 0xf58f +#define FSTV0910_P1_TSISCR_BUFSTAT0 0xf58f00ff + +/*P1_TSDEBUGL*/ +#define RSTV0910_P1_TSDEBUGL 0xf591 +#define FSTV0910_P1_TSFIFO_ERROR_EVNT 0xf5910004 +#define FSTV0910_P1_TSFIFO_OVERFLOWM 0xf5910001 + +/*P1_TSDLYSET2*/ +#define RSTV0910_P1_TSDLYSET2 0xf592 +#define FSTV0910_P1_SOFFIFO_OFFSET 0xf59200c0 +#define FSTV0910_P1_HYSTERESIS_THRESHOLD 0xf5920030 +#define FSTV0910_P1_SOFFIFO_SYMBOFFS2 0xf592000f + +/*P1_TSDLYSET1*/ +#define RSTV0910_P1_TSDLYSET1 0xf593 +#define FSTV0910_P1_SOFFIFO_SYMBOFFS1 0xf59300ff + +/*P1_TSDLYSET0*/ +#define RSTV0910_P1_TSDLYSET0 0xf594 +#define FSTV0910_P1_SOFFIFO_SYMBOFFS0 0xf59400ff + /*P1_ERRCTRL1*/ #define RSTV0910_P1_ERRCTRL1 0xf598 #define FSTV0910_P1_ERR_SOURCE1 0xf59800f0 @@ -3319,14 +3490,12 @@ /*P1_FSPYDATA*/ #define RSTV0910_P1_FSPYDATA 0xf5a2 #define FSTV0910_P1_SPY_STUFFING 0xf5a20080 -#define FSTV0910_P1_NOERROR_PKTJITTER 0xf5a20040 #define FSTV0910_P1_SPY_CNULLPKT 0xf5a20020 #define FSTV0910_P1_SPY_OUTDATA_MODE 0xf5a2001f /*P1_FSPYOUT*/ #define RSTV0910_P1_FSPYOUT 0xf5a3 #define FSTV0910_P1_FSPY_DIRECT 0xf5a30080 -#define FSTV0910_P1_SPY_OUTDATA_BUS 0xf5a30038 #define FSTV0910_P1_STUFF_MODE 0xf5a30007 /*P1_FSTATUS*/ @@ -3371,8 +3540,6 @@ /*P1_FSPYBER*/ #define RSTV0910_P1_FSPYBER 0xf5b2 -#define FSTV0910_P1_FSPYOBS_XORREAD 0xf5b20040 -#define FSTV0910_P1_FSPYBER_OBSMODE 0xf5b20020 #define FSTV0910_P1_FSPYBER_SYNCBYTE 0xf5b20010 #define FSTV0910_P1_FSPYBER_UNSYNC 0xf5b20008 #define FSTV0910_P1_FSPYBER_CTIME 0xf5b20007 @@ -3393,32 +3560,26 @@ /*P1_SFKDIV12*/ #define RSTV0910_P1_SFKDIV12 0xf5c4 #define FSTV0910_P1_SFECKDIV12_MAN 0xf5c40080 -#define FSTV0910_P1_SFEC_K_DIVIDER_12 0xf5c4007f /*P1_SFKDIV23*/ #define RSTV0910_P1_SFKDIV23 0xf5c5 #define FSTV0910_P1_SFECKDIV23_MAN 0xf5c50080 -#define FSTV0910_P1_SFEC_K_DIVIDER_23 0xf5c5007f /*P1_SFKDIV34*/ #define RSTV0910_P1_SFKDIV34 0xf5c6 #define FSTV0910_P1_SFECKDIV34_MAN 0xf5c60080 -#define FSTV0910_P1_SFEC_K_DIVIDER_34 0xf5c6007f /*P1_SFKDIV56*/ #define RSTV0910_P1_SFKDIV56 0xf5c7 #define FSTV0910_P1_SFECKDIV56_MAN 0xf5c70080 -#define FSTV0910_P1_SFEC_K_DIVIDER_56 0xf5c7007f /*P1_SFKDIV67*/ #define RSTV0910_P1_SFKDIV67 0xf5c8 #define FSTV0910_P1_SFECKDIV67_MAN 0xf5c80080 -#define FSTV0910_P1_SFEC_K_DIVIDER_67 0xf5c8007f /*P1_SFKDIV78*/ #define RSTV0910_P1_SFKDIV78 0xf5c9 #define FSTV0910_P1_SFECKDIV78_MAN 0xf5c90080 -#define FSTV0910_P1_SFEC_K_DIVIDER_78 0xf5c9007f /*P1_SFSTATUS*/ #define RSTV0910_P1_SFSTATUS 0xf5cc @@ -3433,11 +3594,7 @@ /*P1_SFDLYSET2*/ #define RSTV0910_P1_SFDLYSET2 0xf5d0 -#define FSTV0910_P1_SFEC_OFFSET 0xf5d000c0 -#define FSTV0910_P1_RST_SFEC 0xf5d00008 -#define FSTV0910_P1_DILDLINE_ERROR 0xf5d00004 #define FSTV0910_P1_SFEC_DISABLE 0xf5d00002 -#define FSTV0910_P1_SFEC_UNREGUL 0xf5d00001 /*P1_SFERRCTRL*/ #define RSTV0910_P1_SFERRCTRL 0xf5d8 @@ -3457,14 +3614,79 @@ #define RSTV0910_P1_SFERRCNT0 0xf5db #define FSTV0910_P1_SFEC_ERR_CNT0 0xf5db00ff +/*RCCFG2*/ +#define RSTV0910_RCCFG2 0xf600 +#define FSTV0910_TSRCFIFO_DVBCI 0xf6000080 +#define FSTV0910_TSRCFIFO_SERIAL 0xf6000040 +#define FSTV0910_TSRCFIFO_DISABLE 0xf6000020 +#define FSTV0910_TSFIFO_2TORC 0xf6000010 +#define FSTV0910_TSRCFIFO_HSGNLOUT 0xf6000008 +#define FSTV0910_TSRCFIFO_ERRMODE 0xf6000006 + +/*RCCFG1*/ +#define RSTV0910_RCCFG1 0xf601 +#define FSTV0910_TSRCFIFO_MANSPEED 0xf60100c0 +#define FSTV0910_TSRCFIFO_PERMDATA 0xf6010020 +#define FSTV0910_TSRCFIFO_NONEWSGNL 0xf6010010 +#define FSTV0910_TSRCFIFO_INVDATA 0xf6010001 + +/*RCCFG0*/ +#define RSTV0910_RCCFG0 0xf602 +#define FSTV0910_TSRCFIFO_BCLKDEL1CK 0xf60200c0 +#define FSTV0910_TSRCFIFO_DUTY50 0xf6020010 +#define FSTV0910_TSRCFIFO_NSGNL2DATA 0xf6020008 +#define FSTV0910_TSRCFIFO_NPDSGNL 0xf6020004 + +/*RCINSDEL2*/ +#define RSTV0910_RCINSDEL2 0xf603 +#define FSTV0910_TSRCDEL_SYNCBYTE 0xf6030080 +#define FSTV0910_TSRCDEL_XXHEADER 0xf6030040 +#define FSTV0910_TSRCDEL_BBHEADER 0xf6030020 +#define FSTV0910_TSRCDEL_DATAFIELD 0xf6030010 +#define FSTV0910_TSRCINSDEL_ISCR 0xf6030008 +#define FSTV0910_TSRCINSDEL_NPD 0xf6030004 +#define FSTV0910_TSRCINSDEL_RSPARITY 0xf6030002 +#define FSTV0910_TSRCINSDEL_CRC8 0xf6030001 + +/*RCINSDEL1*/ +#define RSTV0910_RCINSDEL1 0xf604 +#define FSTV0910_TSRCINS_BBPADDING 0xf6040080 +#define FSTV0910_TSRCINS_BCHFEC 0xf6040040 +#define FSTV0910_TSRCINS_EMODCOD 0xf6040010 +#define FSTV0910_TSRCINS_TOKEN 0xf6040008 +#define FSTV0910_TSRCINS_XXXERR 0xf6040004 +#define FSTV0910_TSRCINS_MATYPE 0xf6040002 +#define FSTV0910_TSRCINS_UPL 0xf6040001 + +/*RCINSDEL0*/ +#define RSTV0910_RCINSDEL0 0xf605 +#define FSTV0910_TSRCINS_DFL 0xf6050080 +#define FSTV0910_TSRCINS_SYNCD 0xf6050040 +#define FSTV0910_TSRCINS_BLOCLEN 0xf6050020 +#define FSTV0910_TSRCINS_SIGPCOUNT 0xf6050010 +#define FSTV0910_TSRCINS_FIFO 0xf6050008 +#define FSTV0910_TSRCINS_REALPACK 0xf6050004 +#define FSTV0910_TSRCINS_TSCONFIG 0xf6050002 +#define FSTV0910_TSRCINS_LATENCY 0xf6050001 + +/*RCSTATUS*/ +#define RSTV0910_RCSTATUS 0xf606 +#define FSTV0910_TSRCFIFO_LINEOK 0xf6060080 +#define FSTV0910_TSRCFIFO_ERROR 0xf6060040 +#define FSTV0910_TSRCREGUL_ERROR 0xf6060010 +#define FSTV0910_TSRCFIFO_DEMODSEL 0xf6060008 +#define FSTV0910_TSRCFIFOSPEED_STORE 0xf6060004 +#define FSTV0910_TSRCSPEED_IMPOSSIBLE 0xf6060001 + +/*RCSPEED*/ +#define RSTV0910_RCSPEED 0xf607 +#define FSTV0910_TSRCFIFO_OUTSPEED 0xf60700ff + /*TSGENERAL*/ #define RSTV0910_TSGENERAL 0xf630 -#define FSTV0910_EN_LGNERROR 0xf6300080 #define FSTV0910_TSFIFO_DISTS2PAR 0xf6300040 -#define FSTV0910_MUXSTREAM_COMPMOSE 0xf6300030 #define FSTV0910_MUXSTREAM_OUTMODE 0xf6300008 #define FSTV0910_TSFIFO_PERMPARAL 0xf6300006 -#define FSTV0910_RST_REEDSOLO 0xf6300001 /*P1_DISIRQCFG*/ #define RSTV0910_P1_DISIRQCFG 0xf700 @@ -3595,7 +3817,6 @@ /*P1_ACRPRESC*/ #define RSTV0910_P1_ACRPRESC 0xf71e -#define FSTV0910_P1_ACR_CODFRDY 0xf71e0008 #define FSTV0910_P1_ACR_PRESC 0xf71e0007 /*P1_ACRDIV*/ @@ -3731,13 +3952,24 @@ /*P2_ACRPRESC*/ #define RSTV0910_P2_ACRPRESC 0xf75e -#define FSTV0910_P2_ACR_CODFRDY 0xf75e0008 #define FSTV0910_P2_ACR_PRESC 0xf75e0007 /*P2_ACRDIV*/ #define RSTV0910_P2_ACRDIV 0xf75f #define FSTV0910_P2_ACR_DIV 0xf75f00ff +/*P1_NBITER_NF1*/ +#define RSTV0910_P1_NBITER_NF1 0xfa00 +#define FSTV0910_P1_NBITER_NF_QPSK_1_4 0xfa0000ff + +/*P1_NBITER_NF2*/ +#define RSTV0910_P1_NBITER_NF2 0xfa01 +#define FSTV0910_P1_NBITER_NF_QPSK_1_3 0xfa0100ff + +/*P1_NBITER_NF3*/ +#define RSTV0910_P1_NBITER_NF3 0xfa02 +#define FSTV0910_P1_NBITER_NF_QPSK_2_5 0xfa0200ff + /*P1_NBITER_NF4*/ #define RSTV0910_P1_NBITER_NF4 0xfa03 #define FSTV0910_P1_NBITER_NF_QPSK_1_2 0xfa0300ff @@ -3794,6 +4026,231 @@ #define RSTV0910_P1_NBITER_NF17 0xfa10 #define FSTV0910_P1_NBITER_NF_8PSK_9_10 0xfa1000ff +/*P1_NBITER_NF18*/ +#define RSTV0910_P1_NBITER_NF18 0xfa11 +#define FSTV0910_P1_NBITER_NF_16APSK_2_3 0xfa1100ff + +/*P1_NBITER_NF19*/ +#define RSTV0910_P1_NBITER_NF19 0xfa12 +#define FSTV0910_P1_NBITER_NF_16APSK_3_4 0xfa1200ff + +/*P1_NBITER_NF20*/ +#define RSTV0910_P1_NBITER_NF20 0xfa13 +#define FSTV0910_P1_NBITER_NF_16APSK_4_5 0xfa1300ff + +/*P1_NBITER_NF21*/ +#define RSTV0910_P1_NBITER_NF21 0xfa14 +#define FSTV0910_P1_NBITER_NF_16APSK_5_6 0xfa1400ff + +/*P1_NBITER_NF22*/ +#define RSTV0910_P1_NBITER_NF22 0xfa15 +#define FSTV0910_P1_NBITER_NF_16APSK_8_9 0xfa1500ff + +/*P1_NBITER_NF23*/ +#define RSTV0910_P1_NBITER_NF23 0xfa16 +#define FSTV0910_P1_NBITER_NF_16APSK_9_10 0xfa1600ff + +/*P1_NBITER_NF24*/ +#define RSTV0910_P1_NBITER_NF24 0xfa17 +#define FSTV0910_P1_NBITER_NF_32APSK_3_4 0xfa1700ff + +/*P1_NBITER_NF25*/ +#define RSTV0910_P1_NBITER_NF25 0xfa18 +#define FSTV0910_P1_NBITER_NF_32APSK_4_5 0xfa1800ff + +/*P1_NBITER_NF26*/ +#define RSTV0910_P1_NBITER_NF26 0xfa19 +#define FSTV0910_P1_NBITER_NF_32APSK_5_6 0xfa1900ff + +/*P1_NBITER_NF27*/ +#define RSTV0910_P1_NBITER_NF27 0xfa1a +#define FSTV0910_P1_NBITER_NF_32APSK_8_9 0xfa1a00ff + +/*P1_NBITER_NF28*/ +#define RSTV0910_P1_NBITER_NF28 0xfa1b +#define FSTV0910_P1_NBITER_NF_32APSK_9_10 0xfa1b00ff + +/*P1_NBITER_SF1*/ +#define RSTV0910_P1_NBITER_SF1 0xfa1c +#define FSTV0910_P1_NBITER_SF_QPSK_1_4 0xfa1c00ff + +/*P1_NBITER_SF2*/ +#define RSTV0910_P1_NBITER_SF2 0xfa1d +#define FSTV0910_P1_NBITER_SF_QPSK_1_3 0xfa1d00ff + +/*P1_NBITER_SF3*/ +#define RSTV0910_P1_NBITER_SF3 0xfa1e +#define FSTV0910_P1_NBITER_SF_QPSK_2_5 0xfa1e00ff + +/*P1_NBITER_SF4*/ +#define RSTV0910_P1_NBITER_SF4 0xfa1f +#define FSTV0910_P1_NBITER_SF_QPSK_1_2 0xfa1f00ff + +/*P1_NBITER_SF5*/ +#define RSTV0910_P1_NBITER_SF5 0xfa20 +#define FSTV0910_P1_NBITER_SF_QPSK_3_5 0xfa2000ff + +/*P1_NBITER_SF6*/ +#define RSTV0910_P1_NBITER_SF6 0xfa21 +#define FSTV0910_P1_NBITER_SF_QPSK_2_3 0xfa2100ff + +/*P1_NBITER_SF7*/ +#define RSTV0910_P1_NBITER_SF7 0xfa22 +#define FSTV0910_P1_NBITER_SF_QPSK_3_4 0xfa2200ff + +/*P1_NBITER_SF8*/ +#define RSTV0910_P1_NBITER_SF8 0xfa23 +#define FSTV0910_P1_NBITER_SF_QPSK_4_5 0xfa2300ff + +/*P1_NBITER_SF9*/ +#define RSTV0910_P1_NBITER_SF9 0xfa24 +#define FSTV0910_P1_NBITER_SF_QPSK_5_6 0xfa2400ff + +/*P1_NBITER_SF10*/ +#define RSTV0910_P1_NBITER_SF10 0xfa25 +#define FSTV0910_P1_NBITER_SF_QPSK_8_9 0xfa2500ff + +/*P1_NBITER_SF12*/ +#define RSTV0910_P1_NBITER_SF12 0xfa26 +#define FSTV0910_P1_NBITER_SF_8PSK_3_5 0xfa2600ff + +/*P1_NBITER_SF13*/ +#define RSTV0910_P1_NBITER_SF13 0xfa27 +#define FSTV0910_P1_NBITER_SF_8PSK_2_3 0xfa2700ff + +/*P1_NBITER_SF14*/ +#define RSTV0910_P1_NBITER_SF14 0xfa28 +#define FSTV0910_P1_NBITER_SF_8PSK_3_4 0xfa2800ff + +/*P1_NBITER_SF15*/ +#define RSTV0910_P1_NBITER_SF15 0xfa29 +#define FSTV0910_P1_NBITER_SF_8PSK_5_6 0xfa2900ff + +/*P1_NBITER_SF16*/ +#define RSTV0910_P1_NBITER_SF16 0xfa2a +#define FSTV0910_P1_NBITER_SF_8PSK_8_9 0xfa2a00ff + +/*P1_NBITER_SF18*/ +#define RSTV0910_P1_NBITER_SF18 0xfa2b +#define FSTV0910_P1_NBITER_SF_16APSK_2_3 0xfa2b00ff + +/*P1_NBITER_SF19*/ +#define RSTV0910_P1_NBITER_SF19 0xfa2c +#define FSTV0910_P1_NBITER_SF_16APSK_3_4 0xfa2c00ff + +/*P1_NBITER_SF20*/ +#define RSTV0910_P1_NBITER_SF20 0xfa2d +#define FSTV0910_P1_NBITER_SF_16APSK_4_5 0xfa2d00ff + +/*P1_NBITER_SF21*/ +#define RSTV0910_P1_NBITER_SF21 0xfa2e +#define FSTV0910_P1_NBITER_SF_16APSK_5_6 0xfa2e00ff + +/*P1_NBITER_SF22*/ +#define RSTV0910_P1_NBITER_SF22 0xfa2f +#define FSTV0910_P1_NBITER_SF_16APSK_8_9 0xfa2f00ff + +/*P1_NBITER_SF24*/ +#define RSTV0910_P1_NBITER_SF24 0xfa30 +#define FSTV0910_P1_NBITER_SF_32APSK_3_4 0xfa3000ff + +/*P1_NBITER_SF25*/ +#define RSTV0910_P1_NBITER_SF25 0xfa31 +#define FSTV0910_P1_NBITER_SF_32APSK_4_5 0xfa3100ff + +/*P1_NBITER_SF26*/ +#define RSTV0910_P1_NBITER_SF26 0xfa32 +#define FSTV0910_P1_NBITER_SF_32APSK_5_6 0xfa3200ff + +/*P1_NBITER_SF27*/ +#define RSTV0910_P1_NBITER_SF27 0xfa33 +#define FSTV0910_P1_NBITER_SF_32APSK_8_9 0xfa3300ff + +/*SELSATUR6*/ +#define RSTV0910_SELSATUR6 0xfa34 +#define FSTV0910_SSAT_SF27 0xfa340008 +#define FSTV0910_SSAT_SF26 0xfa340004 +#define FSTV0910_SSAT_SF25 0xfa340002 +#define FSTV0910_SSAT_SF24 0xfa340001 + +/*SELSATUR5*/ +#define RSTV0910_SELSATUR5 0xfa35 +#define FSTV0910_SSAT_SF22 0xfa350080 +#define FSTV0910_SSAT_SF21 0xfa350040 +#define FSTV0910_SSAT_SF20 0xfa350020 +#define FSTV0910_SSAT_SF19 0xfa350010 +#define FSTV0910_SSAT_SF18 0xfa350008 +#define FSTV0910_SSAT_SF16 0xfa350004 +#define FSTV0910_SSAT_SF15 0xfa350002 +#define FSTV0910_SSAT_SF14 0xfa350001 + +/*SELSATUR4*/ +#define RSTV0910_SELSATUR4 0xfa36 +#define FSTV0910_SSAT_SF13 0xfa360080 +#define FSTV0910_SSAT_SF12 0xfa360040 +#define FSTV0910_SSAT_SF10 0xfa360020 +#define FSTV0910_SSAT_SF9 0xfa360010 +#define FSTV0910_SSAT_SF8 0xfa360008 +#define FSTV0910_SSAT_SF7 0xfa360004 +#define FSTV0910_SSAT_SF6 0xfa360002 +#define FSTV0910_SSAT_SF5 0xfa360001 + +/*SELSATUR3*/ +#define RSTV0910_SELSATUR3 0xfa37 +#define FSTV0910_SSAT_SF4 0xfa370080 +#define FSTV0910_SSAT_SF3 0xfa370040 +#define FSTV0910_SSAT_SF2 0xfa370020 +#define FSTV0910_SSAT_SF1 0xfa370010 +#define FSTV0910_SSAT_NF28 0xfa370008 +#define FSTV0910_SSAT_NF27 0xfa370004 +#define FSTV0910_SSAT_NF26 0xfa370002 +#define FSTV0910_SSAT_NF25 0xfa370001 + +/*SELSATUR2*/ +#define RSTV0910_SELSATUR2 0xfa38 +#define FSTV0910_SSAT_NF24 0xfa380080 +#define FSTV0910_SSAT_NF23 0xfa380040 +#define FSTV0910_SSAT_NF22 0xfa380020 +#define FSTV0910_SSAT_NF21 0xfa380010 +#define FSTV0910_SSAT_NF20 0xfa380008 +#define FSTV0910_SSAT_NF19 0xfa380004 +#define FSTV0910_SSAT_NF18 0xfa380002 +#define FSTV0910_SSAT_NF17 0xfa380001 + +/*SELSATUR1*/ +#define RSTV0910_SELSATUR1 0xfa39 +#define FSTV0910_SSAT_NF16 0xfa390080 +#define FSTV0910_SSAT_NF15 0xfa390040 +#define FSTV0910_SSAT_NF14 0xfa390020 +#define FSTV0910_SSAT_NF13 0xfa390010 +#define FSTV0910_SSAT_NF12 0xfa390008 +#define FSTV0910_SSAT_NF11 0xfa390004 +#define FSTV0910_SSAT_NF10 0xfa390002 +#define FSTV0910_SSAT_NF9 0xfa390001 + +/*SELSATUR0*/ +#define RSTV0910_SELSATUR0 0xfa3a +#define FSTV0910_SSAT_NF8 0xfa3a0080 +#define FSTV0910_SSAT_NF7 0xfa3a0040 +#define FSTV0910_SSAT_NF6 0xfa3a0020 +#define FSTV0910_SSAT_NF5 0xfa3a0010 +#define FSTV0910_SSAT_NF4 0xfa3a0008 +#define FSTV0910_SSAT_NF3 0xfa3a0004 +#define FSTV0910_SSAT_NF2 0xfa3a0002 +#define FSTV0910_SSAT_NF1 0xfa3a0001 + +/*GAINLLR_NF1*/ +#define RSTV0910_GAINLLR_NF1 0xfa40 +#define FSTV0910_GAINLLR_NF_QPSK_1_4 0xfa40007f + +/*GAINLLR_NF2*/ +#define RSTV0910_GAINLLR_NF2 0xfa41 +#define FSTV0910_GAINLLR_NF_QPSK_1_3 0xfa41007f + +/*GAINLLR_NF3*/ +#define RSTV0910_GAINLLR_NF3 0xfa42 +#define FSTV0910_GAINLLR_NF_QPSK_2_5 0xfa42007f + /*GAINLLR_NF4*/ #define RSTV0910_GAINLLR_NF4 0xfa43 #define FSTV0910_GAINLLR_NF_QPSK_1_2 0xfa43007f @@ -3850,23 +4307,155 @@ #define RSTV0910_GAINLLR_NF17 0xfa50 #define FSTV0910_GAINLLR_NF_8PSK_9_10 0xfa50007f +/*GAINLLR_NF18*/ +#define RSTV0910_GAINLLR_NF18 0xfa51 +#define FSTV0910_GAINLLR_NF_16APSK_2_3 0xfa51007f + +/*GAINLLR_NF19*/ +#define RSTV0910_GAINLLR_NF19 0xfa52 +#define FSTV0910_GAINLLR_NF_16APSK_3_4 0xfa52007f + +/*GAINLLR_NF20*/ +#define RSTV0910_GAINLLR_NF20 0xfa53 +#define FSTV0910_GAINLLR_NF_16APSK_4_5 0xfa53007f + +/*GAINLLR_NF21*/ +#define RSTV0910_GAINLLR_NF21 0xfa54 +#define FSTV0910_GAINLLR_NF_16APSK_5_6 0xfa54007f + +/*GAINLLR_NF22*/ +#define RSTV0910_GAINLLR_NF22 0xfa55 +#define FSTV0910_GAINLLR_NF_16APSK_8_9 0xfa55007f + +/*GAINLLR_NF23*/ +#define RSTV0910_GAINLLR_NF23 0xfa56 +#define FSTV0910_GAINLLR_NF_16APSK_9_10 0xfa56007f + +/*GAINLLR_NF24*/ +#define RSTV0910_GAINLLR_NF24 0xfa57 +#define FSTV0910_GAINLLR_NF_32APSK_3_4 0xfa57007f + +/*GAINLLR_NF25*/ +#define RSTV0910_GAINLLR_NF25 0xfa58 +#define FSTV0910_GAINLLR_NF_32APSK_4_5 0xfa58007f + +/*GAINLLR_NF26*/ +#define RSTV0910_GAINLLR_NF26 0xfa59 +#define FSTV0910_GAINLLR_NF_32APSK_5_6 0xfa59007f + +/*GAINLLR_NF27*/ +#define RSTV0910_GAINLLR_NF27 0xfa5a +#define FSTV0910_GAINLLR_NF_32APSK_8_9 0xfa5a007f + +/*GAINLLR_NF28*/ +#define RSTV0910_GAINLLR_NF28 0xfa5b +#define FSTV0910_GAINLLR_NF_32APSK_9_10 0xfa5b007f + +/*GAINLLR_SF1*/ +#define RSTV0910_GAINLLR_SF1 0xfa5c +#define FSTV0910_GAINLLR_SF_QPSK_1_4 0xfa5c007f + +/*GAINLLR_SF2*/ +#define RSTV0910_GAINLLR_SF2 0xfa5d +#define FSTV0910_GAINLLR_SF_QPSK_1_3 0xfa5d007f + +/*GAINLLR_SF3*/ +#define RSTV0910_GAINLLR_SF3 0xfa5e +#define FSTV0910_GAINLLR_SF_QPSK_2_5 0xfa5e007f + +/*GAINLLR_SF4*/ +#define RSTV0910_GAINLLR_SF4 0xfa5f +#define FSTV0910_GAINLLR_SF_QPSK_1_2 0xfa5f007f + +/*GAINLLR_SF5*/ +#define RSTV0910_GAINLLR_SF5 0xfa60 +#define FSTV0910_GAINLLR_SF_QPSK_3_5 0xfa60007f + +/*GAINLLR_SF6*/ +#define RSTV0910_GAINLLR_SF6 0xfa61 +#define FSTV0910_GAINLLR_SF_QPSK_2_3 0xfa61007f + +/*GAINLLR_SF7*/ +#define RSTV0910_GAINLLR_SF7 0xfa62 +#define FSTV0910_GAINLLR_SF_QPSK_3_4 0xfa62007f + +/*GAINLLR_SF8*/ +#define RSTV0910_GAINLLR_SF8 0xfa63 +#define FSTV0910_GAINLLR_SF_QPSK_4_5 0xfa63007f + +/*GAINLLR_SF9*/ +#define RSTV0910_GAINLLR_SF9 0xfa64 +#define FSTV0910_GAINLLR_SF_QPSK_5_6 0xfa64007f + +/*GAINLLR_SF10*/ +#define RSTV0910_GAINLLR_SF10 0xfa65 +#define FSTV0910_GAINLLR_SF_QPSK_8_9 0xfa65007f + +/*GAINLLR_SF12*/ +#define RSTV0910_GAINLLR_SF12 0xfa66 +#define FSTV0910_GAINLLR_SF_8PSK_3_5 0xfa66007f + +/*GAINLLR_SF13*/ +#define RSTV0910_GAINLLR_SF13 0xfa67 +#define FSTV0910_GAINLLR_SF_8PSK_2_3 0xfa67007f + +/*GAINLLR_SF14*/ +#define RSTV0910_GAINLLR_SF14 0xfa68 +#define FSTV0910_GAINLLR_SF_8PSK_3_4 0xfa68007f + +/*GAINLLR_SF15*/ +#define RSTV0910_GAINLLR_SF15 0xfa69 +#define FSTV0910_GAINLLR_SF_8PSK_5_6 0xfa69007f + +/*GAINLLR_SF16*/ +#define RSTV0910_GAINLLR_SF16 0xfa6a +#define FSTV0910_GAINLLR_SF_8PSK_8_9 0xfa6a007f + +/*GAINLLR_SF18*/ +#define RSTV0910_GAINLLR_SF18 0xfa6b +#define FSTV0910_GAINLLR_SF_16APSK_2_3 0xfa6b007f + +/*GAINLLR_SF19*/ +#define RSTV0910_GAINLLR_SF19 0xfa6c +#define FSTV0910_GAINLLR_SF_16APSK_3_4 0xfa6c007f + +/*GAINLLR_SF20*/ +#define RSTV0910_GAINLLR_SF20 0xfa6d +#define FSTV0910_GAINLLR_SF_16APSK_4_5 0xfa6d007f + +/*GAINLLR_SF21*/ +#define RSTV0910_GAINLLR_SF21 0xfa6e +#define FSTV0910_GAINLLR_SF_16APSK_5_6 0xfa6e007f + +/*GAINLLR_SF22*/ +#define RSTV0910_GAINLLR_SF22 0xfa6f +#define FSTV0910_GAINLLR_SF_16APSK_8_9 0xfa6f007f + +/*GAINLLR_SF24*/ +#define RSTV0910_GAINLLR_SF24 0xfa70 +#define FSTV0910_GAINLLR_SF_32APSK_3_4 0xfa70007f + +/*GAINLLR_SF25*/ +#define RSTV0910_GAINLLR_SF25 0xfa71 +#define FSTV0910_GAINLLR_SF_32APSK_4_5 0xfa71007f + +/*GAINLLR_SF26*/ +#define RSTV0910_GAINLLR_SF26 0xfa72 +#define FSTV0910_GAINLLR_SF_32APSK_5_6 0xfa72007f + +/*GAINLLR_SF27*/ +#define RSTV0910_GAINLLR_SF27 0xfa73 +#define FSTV0910_GAINLLR_SF_32APSK_8_9 0xfa73007f + /*CFGEXT*/ #define RSTV0910_CFGEXT 0xfa80 -#define FSTV0910_BYPFIFOBCH 0xfa800080 #define FSTV0910_BYPBCH 0xfa800040 #define FSTV0910_BYPLDPC 0xfa800020 -#define FSTV0910_BYPFIFOBCHF 0xfa800010 -#define FSTV0910_INVLLRSIGN 0xfa800008 #define FSTV0910_SHORTMULT 0xfa800004 -#define FSTV0910_ENSTOPDEC 0xfa800002 /*GENCFG*/ #define RSTV0910_GENCFG 0xfa86 -#define FSTV0910_LEG_ITER 0xfa860040 -#define FSTV0910_NOSHFRD1 0xfa860020 #define FSTV0910_BROADCAST 0xfa860010 -#define FSTV0910_NOSHFRD2 0xfa860008 -#define FSTV0910_BCHERRFLAG 0xfa860004 #define FSTV0910_CROSSINPUT 0xfa860002 #define FSTV0910_DDEMOD 0xfa860001 @@ -3907,6 +4496,18 @@ #define RSTV0910_P2_STATUSMAXITER 0xfabf #define FSTV0910_P2_STATUS_MAX_ITER 0xfabf00ff +/*P2_NBITER_NF1*/ +#define RSTV0910_P2_NBITER_NF1 0xfac0 +#define FSTV0910_P2_NBITER_NF_QPSK_1_4 0xfac000ff + +/*P2_NBITER_NF2*/ +#define RSTV0910_P2_NBITER_NF2 0xfac1 +#define FSTV0910_P2_NBITER_NF_QPSK_1_3 0xfac100ff + +/*P2_NBITER_NF3*/ +#define RSTV0910_P2_NBITER_NF3 0xfac2 +#define FSTV0910_P2_NBITER_NF_QPSK_2_5 0xfac200ff + /*P2_NBITER_NF4*/ #define RSTV0910_P2_NBITER_NF4 0xfac3 #define FSTV0910_P2_NBITER_NF_QPSK_1_2 0xfac300ff @@ -3963,36 +4564,197 @@ #define RSTV0910_P2_NBITER_NF17 0xfad0 #define FSTV0910_P2_NBITER_NF_8PSK_9_10 0xfad000ff +/*P2_NBITER_NF18*/ +#define RSTV0910_P2_NBITER_NF18 0xfad1 +#define FSTV0910_P2_NBITER_NF_16APSK_2_3 0xfad100ff + +/*P2_NBITER_NF19*/ +#define RSTV0910_P2_NBITER_NF19 0xfad2 +#define FSTV0910_P2_NBITER_NF_16APSK_3_4 0xfad200ff + +/*P2_NBITER_NF20*/ +#define RSTV0910_P2_NBITER_NF20 0xfad3 +#define FSTV0910_P2_NBITER_NF_16APSK_4_5 0xfad300ff + +/*P2_NBITER_NF21*/ +#define RSTV0910_P2_NBITER_NF21 0xfad4 +#define FSTV0910_P2_NBITER_NF_16APSK_5_6 0xfad400ff + +/*P2_NBITER_NF22*/ +#define RSTV0910_P2_NBITER_NF22 0xfad5 +#define FSTV0910_P2_NBITER_NF_16APSK_8_9 0xfad500ff + +/*P2_NBITER_NF23*/ +#define RSTV0910_P2_NBITER_NF23 0xfad6 +#define FSTV0910_P2_NBITER_NF_16APSK_9_10 0xfad600ff + +/*P2_NBITER_NF24*/ +#define RSTV0910_P2_NBITER_NF24 0xfad7 +#define FSTV0910_P2_NBITER_NF_32APSK_3_4 0xfad700ff + +/*P2_NBITER_NF25*/ +#define RSTV0910_P2_NBITER_NF25 0xfad8 +#define FSTV0910_P2_NBITER_NF_32APSK_4_5 0xfad800ff + +/*P2_NBITER_NF26*/ +#define RSTV0910_P2_NBITER_NF26 0xfad9 +#define FSTV0910_P2_NBITER_NF_32APSK_5_6 0xfad900ff + +/*P2_NBITER_NF27*/ +#define RSTV0910_P2_NBITER_NF27 0xfada +#define FSTV0910_P2_NBITER_NF_32APSK_8_9 0xfada00ff + +/*P2_NBITER_NF28*/ +#define RSTV0910_P2_NBITER_NF28 0xfadb +#define FSTV0910_P2_NBITER_NF_32APSK_9_10 0xfadb00ff + +/*P2_NBITER_SF1*/ +#define RSTV0910_P2_NBITER_SF1 0xfadc +#define FSTV0910_P2_NBITER_SF_QPSK_1_4 0xfadc00ff + +/*P2_NBITER_SF2*/ +#define RSTV0910_P2_NBITER_SF2 0xfadd +#define FSTV0910_P2_NBITER_SF_QPSK_1_3 0xfadd00ff + +/*P2_NBITER_SF3*/ +#define RSTV0910_P2_NBITER_SF3 0xfade +#define FSTV0910_P2_NBITER_SF_QPSK_2_5 0xfade00ff + +/*P2_NBITER_SF4*/ +#define RSTV0910_P2_NBITER_SF4 0xfadf +#define FSTV0910_P2_NBITER_SF_QPSK_1_2 0xfadf00ff + +/*P2_NBITER_SF5*/ +#define RSTV0910_P2_NBITER_SF5 0xfae0 +#define FSTV0910_P2_NBITER_SF_QPSK_3_5 0xfae000ff + +/*P2_NBITER_SF6*/ +#define RSTV0910_P2_NBITER_SF6 0xfae1 +#define FSTV0910_P2_NBITER_SF_QPSK_2_3 0xfae100ff + +/*P2_NBITER_SF7*/ +#define RSTV0910_P2_NBITER_SF7 0xfae2 +#define FSTV0910_P2_NBITER_SF_QPSK_3_4 0xfae200ff + +/*P2_NBITER_SF8*/ +#define RSTV0910_P2_NBITER_SF8 0xfae3 +#define FSTV0910_P2_NBITER_SF_QPSK_4_5 0xfae300ff + +/*P2_NBITER_SF9*/ +#define RSTV0910_P2_NBITER_SF9 0xfae4 +#define FSTV0910_P2_NBITER_SF_QPSK_5_6 0xfae400ff + +/*P2_NBITER_SF10*/ +#define RSTV0910_P2_NBITER_SF10 0xfae5 +#define FSTV0910_P2_NBITER_SF_QPSK_8_9 0xfae500ff + +/*P2_NBITER_SF12*/ +#define RSTV0910_P2_NBITER_SF12 0xfae6 +#define FSTV0910_P2_NBITER_SF_8PSK_3_5 0xfae600ff + +/*P2_NBITER_SF13*/ +#define RSTV0910_P2_NBITER_SF13 0xfae7 +#define FSTV0910_P2_NBITER_SF_8PSK_2_3 0xfae700ff + +/*P2_NBITER_SF14*/ +#define RSTV0910_P2_NBITER_SF14 0xfae8 +#define FSTV0910_P2_NBITER_SF_8PSK_3_4 0xfae800ff + +/*P2_NBITER_SF15*/ +#define RSTV0910_P2_NBITER_SF15 0xfae9 +#define FSTV0910_P2_NBITER_SF_8PSK_5_6 0xfae900ff + +/*P2_NBITER_SF16*/ +#define RSTV0910_P2_NBITER_SF16 0xfaea +#define FSTV0910_P2_NBITER_SF_8PSK_8_9 0xfaea00ff + +/*P2_NBITER_SF18*/ +#define RSTV0910_P2_NBITER_SF18 0xfaeb +#define FSTV0910_P2_NBITER_SF_16APSK_2_3 0xfaeb00ff + +/*P2_NBITER_SF19*/ +#define RSTV0910_P2_NBITER_SF19 0xfaec +#define FSTV0910_P2_NBITER_SF_16APSK_3_4 0xfaec00ff + +/*P2_NBITER_SF20*/ +#define RSTV0910_P2_NBITER_SF20 0xfaed +#define FSTV0910_P2_NBITER_SF_16APSK_4_5 0xfaed00ff + +/*P2_NBITER_SF21*/ +#define RSTV0910_P2_NBITER_SF21 0xfaee +#define FSTV0910_P2_NBITER_SF_16APSK_5_6 0xfaee00ff + +/*P2_NBITER_SF22*/ +#define RSTV0910_P2_NBITER_SF22 0xfaef +#define FSTV0910_P2_NBITER_SF_16APSK_8_9 0xfaef00ff + +/*P2_NBITER_SF24*/ +#define RSTV0910_P2_NBITER_SF24 0xfaf0 +#define FSTV0910_P2_NBITER_SF_32APSK_3_4 0xfaf000ff + +/*P2_NBITER_SF25*/ +#define RSTV0910_P2_NBITER_SF25 0xfaf1 +#define FSTV0910_P2_NBITER_SF_32APSK_4_5 0xfaf100ff + +/*P2_NBITER_SF26*/ +#define RSTV0910_P2_NBITER_SF26 0xfaf2 +#define FSTV0910_P2_NBITER_SF_32APSK_5_6 0xfaf200ff + +/*P2_NBITER_SF27*/ +#define RSTV0910_P2_NBITER_SF27 0xfaf3 +#define FSTV0910_P2_NBITER_SF_32APSK_8_9 0xfaf300ff + /*TSTRES0*/ #define RSTV0910_TSTRES0 0xff11 #define FSTV0910_FRESFEC 0xff110080 -#define FSTV0910_FRESTS 0xff110040 -#define FSTV0910_FRESVIT1 0xff110020 -#define FSTV0910_FRESVIT2 0xff110010 #define FSTV0910_FRESSYM1 0xff110008 #define FSTV0910_FRESSYM2 0xff110004 -#define FSTV0910_FRESMAS 0xff110002 -#define FSTV0910_FRESINT 0xff110001 + +/*TSTOUT*/ +#define RSTV0910_TSTOUT 0xff12 +#define FSTV0910_TS 0xff12003e +#define FSTV0910_TEST_OUT 0xff120001 + +/*TSTIN*/ +#define RSTV0910_TSTIN 0xff13 +#define FSTV0910_TEST_IN 0xff130080 + +/*P2_TSTDMD*/ +#define RSTV0910_P2_TSTDMD 0xff20 +#define FSTV0910_P2_CFRINIT_INVZIGZAG 0xff200008 + +/*P2_TCTL1*/ +#define RSTV0910_P2_TCTL1 0xff24 +#define FSTV0910_P2_TST_IQSYMBSEL 0xff24001f /*P2_TCTL4*/ #define RSTV0910_P2_TCTL4 0xff28 #define FSTV0910_P2_CFR2TOCFR1_DVBS1 0xff2800c0 -#define FSTV0910_P2_TSTINV_PHERR 0xff280020 -#define FSTV0910_P2_EN_PLHCALC 0xff280010 -#define FSTV0910_P2_TETA3L_RSTTETA3D 0xff280008 -#define FSTV0910_P2_DIS_FORCEBETA2 0xff280004 -#define FSTV0910_P2_CAR3_NOTRACEBACK 0xff280002 -#define FSTV0910_P2_CAR3_NOFORWARD 0xff280001 + +/*P2_TPKTDELIN*/ +#define RSTV0910_P2_TPKTDELIN 0xff37 +#define FSTV0910_P2_CFG_RSPARITYON 0xff370080 + +/*P1_TSTDMD*/ +#define RSTV0910_P1_TSTDMD 0xff40 +#define FSTV0910_P1_CFRINIT_INVZIGZAG 0xff400008 + +/*P1_TCTL1*/ +#define RSTV0910_P1_TCTL1 0xff44 +#define FSTV0910_P1_TST_IQSYMBSEL 0xff44001f /*P1_TCTL4*/ #define RSTV0910_P1_TCTL4 0xff48 #define FSTV0910_P1_CFR2TOCFR1_DVBS1 0xff4800c0 -#define FSTV0910_P1_TSTINV_PHERR 0xff480020 -#define FSTV0910_P1_EN_PLHCALC 0xff480010 -#define FSTV0910_P1_TETA3L_RSTTETA3D 0xff480008 -#define FSTV0910_P1_DIS_FORCEBETA2 0xff480004 -#define FSTV0910_P1_CAR3_NOTRACEBACK 0xff480002 -#define FSTV0910_P1_CAR3_NOFORWARD 0xff480001 -#define STV0910_NBREGS 735 -#define STV0910_NBFIELDS 1776 +/*P1_TPKTDELIN*/ +#define RSTV0910_P1_TPKTDELIN 0xff57 +#define FSTV0910_P1_CFG_RSPARITYON 0xff570080 + +/*TSTTSRS*/ +#define RSTV0910_TSTTSRS 0xff6d +#define FSTV0910_TSTRS_DISRS2 0xff6d0002 +#define FSTV0910_TSTRS_DISRS1 0xff6d0001 + +#define STV0910_NBREGS 975 +#define STV0910_NBFIELDS 1818 diff --git a/frontends/stv6111.c b/frontends/stv6111.c index 89628df..79a42df 100644 --- a/frontends/stv6111.c +++ b/frontends/stv6111.c @@ -105,20 +105,20 @@ static int read_regs(struct stv *state, u8 reg, u8 *val, int len) return i2c_read(state->i2c, state->adr, ®, 1, val, len); } +#if 0 static void dump_regs(struct stv *state) { u8 d[11], *c = &state->reg[0]; read_regs(state, 0, d, 11); -#if 0 pr_info("stv6111_regs = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], d[8], d[9], d[10]); pr_info("reg[] = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7], c[8], c[9], c[10]); -#endif } +#endif static int wait_for_call_done(struct stv *state, u8 mask) { @@ -184,7 +184,9 @@ static int attach_init(struct stv *state) { if (write_regs(state, 0, 11)) return -1; +#if 0 dump_regs(state); +#endif return 0; } @@ -299,7 +301,9 @@ static int set_lof(struct stv *state, u32 LocalFrequency, u32 CutOffFrequency) state->Frequency = Frequency; +#if 0 dump_regs(state); +#endif return 0; } @@ -330,39 +334,6 @@ static int get_frequency(struct dvb_frontend *fe, u32 *frequency) return 0; } -static u32 AGC_Gain[] = { - 000, /* 0.0 */ - 000, /* 0.1 */ - 1000, /* 0.2 */ - 2000, /* 0.3 */ - 3000, /* 0.4 */ - 4000, /* 0.5 */ - 5000, /* 0.6 */ - 6000, /* 0.7 */ - 7000, /* 0.8 */ - 14000, /* 0.9 */ - 20000, /* 1.0 */ - 27000, /* 1.1 */ - 32000, /* 1.2 */ - 37000, /* 1.3 */ - 42000, /* 1.4 */ - 47000, /* 1.5 */ - 50000, /* 1.6 */ - 53000, /* 1.7 */ - 56000, /* 1.8 */ - 58000, /* 1.9 */ - 60000, /* 2.0 */ - 62000, /* 2.1 */ - 63000, /* 2.2 */ - 64000, /* 2.3 */ - 64500, /* 2.4 */ - 65000, /* 2.5 */ - 65500, /* 2.6 */ - 66000, /* 2.7 */ - 66500, /* 2.8 */ - 67000, /* 2.9 */ -}; - struct SLookup { s16 Value; u16 RegValue; @@ -618,7 +589,6 @@ static struct SLookup Gain_Channel_AGC_IIP3_LookUp[] = { { 1325 , 0xFF00 }, }; -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) static s32 TableLookup(struct SLookup *Table, int TableSize, u16 RegValue) { diff --git a/include/linux/dvb/frontend.h b/include/linux/dvb/frontend.h index ca3976f..3ef96dd 100644 --- a/include/linux/dvb/frontend.h +++ b/include/linux/dvb/frontend.h @@ -197,6 +197,7 @@ typedef enum fe_transmit_mode { TRANSMISSION_MODE_32K, TRANSMISSION_MODE_C1, TRANSMISSION_MODE_C3780, + TRANSMISSION_MODE_64K, } fe_transmit_mode_t; #if defined(__DVB_CORE__) || !defined (__KERNEL__) @@ -378,8 +379,9 @@ struct dvb_frontend_event { #define DTV_STAT_TOTAL_BLOCK_COUNT 69 #define DTV_INPUT 70 +#define DTV_PLS 71 -#define DTV_MAX_COMMAND DTV_INPUT +#define DTV_MAX_COMMAND DTV_PLS typedef enum fe_pilot { PILOT_ON, @@ -454,6 +456,7 @@ enum atscmh_rs_code_mode { }; #define NO_STREAM_ID_FILTER (~0U) +#define NO_SCRAMBLING_CODE (~0U) #define LNA_AUTO (~0U) struct dtv_cmds_h { diff --git a/include/linux/dvb/ns.h b/include/linux/dvb/ns.h index 4cfd9f0..9991375 100644 --- a/include/linux/dvb/ns.h +++ b/include/linux/dvb/ns.h @@ -50,6 +50,11 @@ struct dvb_nsd_ts { __u16 section_id; }; +struct dvb_ns_cap { + __u8 streams_max; + __u8 reserved[127]; +}; + #define NS_SET_NET _IOW('o', 192, struct dvb_ns_params) #define NS_START _IO('o', 193) #define NS_STOP _IO('o', 194) @@ -66,4 +71,6 @@ struct dvb_nsd_ts { #define NS_INSERT_PACKETS _IOW('o', 203, __u8) #define NS_SET_CI _IOW('o', 204, __u8) +#define NS_GET_CAP _IOR('o', 204, struct dvb_ns_cap)) + #endif /*_UAPI_DVBNS_H_*/ diff --git a/include/linux/dvb/osd.h b/include/linux/dvb/osd.h index 880e684..6a295fa 100644 --- a/include/linux/dvb/osd.h +++ b/include/linux/dvb/osd.h @@ -26,6 +26,10 @@ #include +#ifndef __user +#define __user +#endif + typedef enum { // All functions return -2 on "not open" OSD_Close=1, // () diff --git a/include/linux/dvb/video.h b/include/linux/dvb/video.h index d3d14a5..471c1e9 100644 --- a/include/linux/dvb/video.h +++ b/include/linux/dvb/video.h @@ -30,6 +30,10 @@ #include #endif +#ifndef __user +#define __user +#endif + typedef enum { VIDEO_FORMAT_4_3, /* Select 4:3 format */ VIDEO_FORMAT_16_9, /* Select 16:9 format. */