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cleanup and complete MCI defines accroding to upstream firmware

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This commit is contained in:
rjkm
2025-08-22 14:33:22 +02:00
parent bd51e92e29
commit cd1d1b7830
4 changed files with 26 additions and 58 deletions
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4
apps/ddinfo.c
View File

@@ -63,7 +63,7 @@ int temp_info(int dev, uint32_t link)
{
struct ddb_mci_msg msg = {
.link = link,
.cmd.command = SX8_CMD_GETBIST,
.cmd.command = MCI_CMD_GETBIST,
};
int ret;
int i;
@@ -404,7 +404,7 @@ int mci_license(int dev)
{
struct ddb_mci_msg msg = {
.link = 0,
.cmd.command = CMD_GET_SERIALNUMBER,
.cmd.command = MCI_CMD_GET_SERIALNUMBER,
};
int ret;

4
apps/ddlicense.c
View File

@@ -48,7 +48,7 @@ static int mci_get_license(int dev, uint8_t *ID, uint8_t *LK, uint8_t *SN)
{
struct ddb_mci_msg msg = {
.link = 0,
.cmd.command = CMD_GET_SERIALNUMBER,
.cmd.command = MCI_CMD_GET_SERIALNUMBER,
};
int ret;
@@ -71,7 +71,7 @@ static int mci_set_license(int dev, uint8_t *ID, uint8_t *LK)
{
struct ddb_mci_msg msg = {
.link = 0,
.cmd.command = CMD_IMPORT_LICENSE,
.cmd.command = MCI_CMD_IMPORT_LICENSE,
};
int ret;

2
apps/modconfig.c
View File

@@ -456,7 +456,7 @@ void streams_cb(void *priv, char *par, char *val)
int mci_lic(int dev)
{
struct ddb_mci_msg msg = {
.cmd.command = CMD_EXPORT_LICENSE,
.cmd.command = MCI_CMD_EXPORT_LICENSE,
.cmd.get_bb_header.select = 0,
};
struct mci_result *res = &msg.res;

74
ddbridge/ddbridge-mci.h
View File

@@ -24,21 +24,6 @@
#ifndef _DDBRIDGE_MCI_H_
#define _DDBRIDGE_MCI_H_
#define SX8_TSINPUT (0x280)
#define MIC_CONTROL (0x500)
#define MIC_PROGMEM_OLD (0x4000)
#define MIC_PROGMEM_OLD_SIZE (0x4000)
#define MIC_PROGMEM (0x8000)
#define MIC_PROGMEM_SIZE (0x8000)
#define MIC_DATAMEM (0x8000)
#define MIC_DATAMEM_SIZE (0x2000)
#define MIC_INTERFACE_IN (0x0600)
#define MIC_INTERFACE_OUT (0x0680)
#define MIC_INTERFACE_VER (0x06F0)
#define MCI_COMMAND_SIZE (0x80)
#define MCI_RESULT_SIZE (0x80)
@@ -88,19 +73,9 @@
/********************************************************/
#define MCI_DEMOD_STOPPED (0)
#define MCI_DEMOD_WAIT_SIGNAL (2)
#define MCI_DEMOD_TIMEOUT (14)
#define MCI_DEMOD_LOCKED (15)
#define SX8_DEMOD_IQ_MODE (1)
#define SX8_DEMOD_WAIT_MATYPE (3)
#define MX_DEMOD_WAIT_TS (6)
#define MX_DEMOD_C2SCAN (16)
#define MCI_STATUS_OK (0x00)
#define MCI_STATUS_UNSUPPORTED (0x80)
#define MCI_STATUS_POWERED_DOWN (0xF0)
#define MCI_STATUS_DISABLED (0xF9)
#define MCI_STATUS_BUSY (0xFA)
#define MCI_STATUS_HARDWARE_ERROR (0xFB)
@@ -109,6 +84,8 @@
#define MCI_STATUS_NOT_READY (0xFE)
#define MCI_STATUS_ERROR (0xFF)
// Receiver defines
#define MCI_CMD_STOP (0x01)
#define MCI_CMD_GETSTATUS (0x02)
#define MCI_CMD_GETSIGNALINFO (0x03)
@@ -121,6 +98,7 @@
#define MCI_CMD_SEARCH_DVBS (0x10)
#define MCI_CMD_SEARCH_ISDBS (0x11)
#define MCI_CMD_SEARCH_ISDBS3 (0x12)
#define MCI_CMD_SEARCH_DVBC (0x20)
#define MCI_CMD_SEARCH_DVBT (0x21)
@@ -136,21 +114,6 @@
#define MCI_CMD_GET_IQSYMBOL (0x30)
#define MCI_BANDWIDTH_UNKNOWN (0)
#define MCI_BANDWIDTH_1_7MHZ (1)
#define MCI_BANDWIDTH_5MHZ (5)
#define MCI_BANDWIDTH_6MHZ (6)
#define MCI_BANDWIDTH_7MHZ (7)
#define MCI_BANDWIDTH_8MHZ (8)
#define SX8_CMD_GETBIST (0x0F)
#define SX8_CMD_INPUT_ENABLE (0x40)
#define SX8_CMD_INPUT_DISABLE (0x41)
#define SX8_CMD_START_IQ (0x42)
#define SX8_CMD_STOP_IQ (0x43)
#define SX8_CMD_ENABLE_IQOUTPUT (0x44)
#define SX8_CMD_DISABLE_IQOUTPUT (0x45)
#define MX_CMD_GET_L1INFO (0x50)
#define MX_CMD_GET_IDS (0x51)
#define MX_CMD_GET_DVBT_TPS (0x52)
@@ -178,6 +141,14 @@
#define MX_L1INFO_SEL_SETID (MX_T2_FLAGS_SETPLP_ID)
#define MX_L1INFO_MAGIC (0x3254)
#define MCI_BANDWIDTH_UNKNOWN (0)
#define MCI_BANDWIDTH_1_7MHZ (1)
#define MCI_BANDWIDTH_5MHZ (5)
#define MCI_BANDWIDTH_6MHZ (6)
#define MCI_BANDWIDTH_7MHZ (7)
#define MCI_BANDWIDTH_8MHZ (8)
#define MCI_BANDWIDTH_10MHZ (10)
#define MCI_BANDWIDTH_EXTENSION (0x80) // currently used only for J83B in Japan
#define MX_MODE_DVBSX (2)
@@ -223,9 +194,6 @@
#define MX_SIGNALINFO_FLAG_CHANGE (0x01)
#define MX_SIGNALINFO_FLAG_EWS (0x02)
#define MX_SIGNALINFO_FLAG_CHANGE (0x01)
#define MX_SIGNALINFO_FLAG_EWS (0x02)
#define MX_DISABLE_INPUTS (0)
#define MX_ENABLE_TER_INPUT (1)
#define MX_ENABLE_SAT_INPUT (2)
@@ -259,14 +227,13 @@
#define MX_DEMOD_WAIT_TS (6)
#define MX_DEMOD_C2SCAN (16)
#define MCI_SUCCESS(status) ((status & MCI_STATUS_UNSUPPORTED) == 0)
/********************************************************/
// Modulator defines
#define MOD_SETUP_CHANNELS (0x60)
#define MOD_SETUP_OUTPUT (0x61)
#define MOD_SETUP_STREAM (0x62)
#define MOD_SET_STREAM_CHANNEL (0x63)
//#define MOD_SET_STREAM_CHANNEL (0x63)
#define MOD_CLOCK_CORRECTION (0x64)
#define MOD_SETUP_FLAG_FIRST (0x01)
#define MOD_SETUP_FLAG_LAST (0x02)
@@ -352,11 +319,12 @@
#define MOD_QAM_ISDBC_64 (0x08)
#define MOD_QAM_ISDBC_256 (0x09)
#define CMD_GET_SERIALNUMBER (0xF0)
#define CMD_EXPORT_LICENSE (0xF0)
#define CMD_IMPORT_LICENSE (0xF1)
#define CMD_POWER_DOWN (0xF2)
#define CMD_POWER_UP (0xF3)
// Sub Commands for MOD_CLOCK_CORRECTION
// Only available on SDR Modulator (ATV,IQ,IQ2)
#define MOD_CLOCK_COR_RESET (0)
#define MOD_CLOCK_COR_SET (1)
#define MOD_CLOCK_COR_LEGACY_SET (120)
#define MOD_CLOCK_COR_LEGACY_QUERY (121)
struct mod_setup_channels {
u8 flags;