basic support for SDR card

ddbridge/ddbridge-core.c

@@ -299,6 +299,16 @@ static struct ddb_regmap octopus_mod_2_map = {
 	.channel = &octopus_mod_2_channel,
 };
 
+static struct ddb_regmap octopus_sdr_map = {
+	.irq_version = 2,
+	.irq_base_odma = 64,
+	.irq_base_rate = 32,
+	.output = &octopus_output,
+	.odma = &octopus_mod_2_odma,
+	.odma_buf = &octopus_mod_2_odma_buf,
+	.channel = &octopus_mod_2_channel,
+};
+
 
 /****************************************************************************/
 
@@ -4459,7 +4469,7 @@ static ssize_t temp_show(struct device *device,
 	u8 tmp[2];
 	
 	if (dev->link[0].info->type == DDB_MOD) {
-		if (dev->link[0].info->version == 2) {
+		if (dev->link[0].info->version >= 2) {
 			temp = 0xffff & ddbreadl(dev, TEMPMON2_BOARD);
 			temp = (temp * 1000) >> 8;
 

ddbridge/ddbridge-mod.c

@@ -171,10 +171,10 @@ void ddbridge_mod_output_stop(struct ddb_output *output)
 	struct ddb_mod *mod = &dev->mod[output->nr];
 
 	mod->State = CM_IDLE;
-	mod->Control = 0;
+	mod->Control &= 0xfffffff0;
 	if (dev->link[0].info->version == 2)
 		mod_SendChannelCommand(dev, output->nr, CHANNEL_CONTROL_CMD_FREE);
-	ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
+	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 #if 0
 	udelay(10);
 	ddbwritel(dev, CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr));
@@ -308,6 +308,7 @@ int ddbridge_mod_output_start(struct ddb_output *output)
 	u32 Channel = output->nr;
 	struct ddb_mod *mod = &dev->mod[output->nr];
 	u32 Symbolrate = mod->symbolrate;
+	u32 ctrl;
 	
 	mod_calc_rateinc(mod);
 	/*PCRIncrement = RoundPCR(PCRIncrement);*/
@@ -329,11 +330,15 @@ int ddbridge_mod_output_start(struct ddb_output *output)
 	mod->State = CM_STARTUP;
 	mod->StateCounter = CM_STARTUP_DELAY;
 	
-	ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
+	if (dev->link[0].info->version == 3)
+		mod->Control = 0xfffffff0 & ddbreadl(dev, CHANNEL_CONTROL(output->nr));
+	else
+		mod->Control = 0;
+	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 	udelay(10);
-	ddbwritel(dev, CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr));
+	ddbwritel(dev, mod->Control | CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr));
 	udelay(10);
-	ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
+	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 
 	pr_info("DDBridge: CHANNEL_BASE = %08x\n", CHANNEL_BASE);
 	pr_info("DDBridge: CHANNEL_CONTROL = %08x\n", CHANNEL_CONTROL(Channel));
@@ -368,23 +373,25 @@ int ddbridge_mod_output_start(struct ddb_output *output)
 		
 		if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_SETUP))
 			return -EINVAL;
-		mod->Control = CHANNEL_CONTROL_ENABLE_DVB;
+		mod->Control |= CHANNEL_CONTROL_ENABLE_DVB;
 	} else {
 		/* QAM: 600 601 602 903 604 = 16 32 64 128 256 */
 		/* ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); */
 		ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr));
-		mod->Control = (CHANNEL_CONTROL_ENABLE_IQ | CHANNEL_CONTROL_ENABLE_DVB);
+		mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ | CHANNEL_CONTROL_ENABLE_DVB);
+	}
+	if (dev->link[0].info->version < 3) {
+		mod_set_rateinc(dev, output->nr);
+		mod_set_incs(output);
 	}
-	mod_set_rateinc(dev, output->nr);
-	mod_set_incs(output);
-
 	mod->Control |= CHANNEL_CONTROL_ENABLE_SOURCE;
 
 	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 	if (dev->link[0].info->version == 2)
 		if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_UNMUTE))
 			return -EINVAL;
-	pr_info("DDBridge: mod_output_start %d.%d\n", dev->nr, output->nr);
+	pr_info("DDBridge: mod_output_start %d.%d ctrl=%08x\n",
+		dev->nr, output->nr, mod->Control);
 	return 0;
 }
 
@@ -1607,11 +1614,21 @@ static int mod_init_2(struct ddb *dev, u32 Frequency)
 	return 0;
 }
 
+static int mod_init_3(struct ddb *dev, u32 Frequency)
+{
+	int status, i;
+
+	printk("%s\n", __func__);
+	return 0;
+}
+
 int ddbridge_mod_init(struct ddb *dev)
 {
 	if (dev->link[0].info->version <= 1)
 		return mod_init_1(dev, 722000000);
 	if (dev->link[0].info->version == 2)
 		return mod_init_2(dev, 114000000);
+	if (dev->link[0].info->version == 3)
+		return mod_init_3(dev, 114000000);
 	return -1;
 }

ddbridge/ddbridge.c

@@ -498,6 +498,16 @@ static struct ddb_info ddb_mod_fsm_8 = {
 	.tempmon_irq = 8,
 };
 
+static struct ddb_info ddb_sdr = {
+	.type     = DDB_MOD,
+	.name     = "Digital Devices SDR",
+	.version  = 3,
+	.regmap   = &octopus_sdr_map,
+	.port_num = 10,
+	.temp_num = 1,
+	.tempmon_irq = 8,
+};
+
 static struct ddb_info ddb_octopro_hdin = {
 	.type     = DDB_OCTOPRO_HDIN,
 	.name     = "Digital Devices OctopusNet Pro HDIN",
@@ -560,6 +570,7 @@ static const struct pci_device_id ddb_id_tbl[] __devinitconst = {
 	DDB_ID(DDVID, 0x0210, DDVID, 0x0001, ddb_mod_fsm_24),
 	DDB_ID(DDVID, 0x0210, DDVID, 0x0002, ddb_mod_fsm_16),
 	DDB_ID(DDVID, 0x0210, DDVID, 0x0003, ddb_mod_fsm_8),
+	DDB_ID(DDVID, 0x0220, DDVID, 0x0001, ddb_sdr),
 	/* testing on OctopusNet Pro */
 	DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_octopro_hdin),
 	DDB_ID(DDVID, 0x0321, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
@@ -574,9 +585,18 @@ static const struct pci_device_id ddb_id_tbl[] __devinitconst = {
 	DDB_ID(DDVID, 0x0007, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
 	DDB_ID(DDVID, 0x0008, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
 	DDB_ID(DDVID, 0x0011, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
+	DDB_ID(DDVID, 0x0012, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
 	DDB_ID(DDVID, 0x0013, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
 	DDB_ID(DDVID, 0x0201, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
+	DDB_ID(DDVID, 0x0203, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
+	DDB_ID(DDVID, 0x0210, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
+	DDB_ID(DDVID, 0x0220, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
 	DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
+	DDB_ID(DDVID, 0x0321, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
+	DDB_ID(DDVID, 0x0322, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
+	DDB_ID(DDVID, 0x0323, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
+	DDB_ID(DDVID, 0x0328, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
+	DDB_ID(DDVID, 0x0329, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
 	{0}
 };
 MODULE_DEVICE_TABLE(pci, ddb_id_tbl);