From f44a9dfcbd8a16717b598dad08135213dc3dfd3b Mon Sep 17 00:00:00 2001
From: Ralph Metzler <rjkm@metzlerbros.de>
Date: Sun, 16 Apr 2017 21:20:52 +0200
Subject: [PATCH] coding style fixes

---
 ddbridge/ddbridge-core.c | 224 +++++++++++++-----------
 ddbridge/ddbridge-i2c.c  |   2 +-
 ddbridge/ddbridge-mod.c  | 359 +++++++++++++++++----------------------
 ddbridge/ddbridge-ns.c   |   3 -
 ddbridge/ddbridge-regs.h |  56 +++---
 ddbridge/ddbridge.c      |  16 +-
 ddbridge/ddbridge.h      |   9 +-
 7 files changed, 318 insertions(+), 351 deletions(-)

diff --git a/ddbridge/ddbridge-core.c b/ddbridge/ddbridge-core.c
index b8a7d06..153928e 100644
--- a/ddbridge/ddbridge-core.c
+++ b/ddbridge/ddbridge-core.c
@@ -419,7 +419,7 @@ static void ddb_set_dma_table(struct ddb_io *io)
 static void ddb_set_dma_tables(struct ddb *dev)
 {
 	u32 i;
-	
+
 	for (i = 0; i < DDB_MAX_PORT; i++) {
 		if (dev->port[i].input[0])
 			ddb_set_dma_table(dev->port[i].input[0]);
@@ -427,7 +427,7 @@ static void ddb_set_dma_tables(struct ddb *dev)
 			ddb_set_dma_table(dev->port[i].input[1]);
 		if (dev->port[i].output)
 			ddb_set_dma_table(dev->port[i].output);
-        }
+	}
 }
 
 
@@ -653,35 +653,35 @@ static void ddb_buffers_free(struct ddb *dev)
 }
 
 /*
-* Control:
-* 
-* Bit 0 - Enable TS
-*     1 - Reset
-*     2 - clock enable
-*     3 - clock phase
-*     4 - gap enable
-*     5 - send null packets on underrun
-*     6 - enable clock gating
-*     7 - set error bit on inserted null packets
-*     8-10 - fine adjust clock delay
-*     11- HS (high speed), if NCO mode=0: 0=72MHz 1=96Mhz
-*     12- enable NCO mode
-* 
-* Control 2:
-* 
-* Bit 0-6  : gap_size, Gap = (gap_size * 2) + 4
-*     16-31: HS = 0: Speed = 72 * Value / 8192 MBit/s
-*            HS = 1: Speed = 72 * 8 / (Value + 1) MBit/s (only bit 19-16 used)
-* 
-*/
+ * Control:
+ *
+ * Bit 0 - Enable TS
+ *     1 - Reset
+ *     2 - clock enable
+ *     3 - clock phase
+ *     4 - gap enable
+ *     5 - send null packets on underrun
+ *     6 - enable clock gating
+ *     7 - set error bit on inserted null packets
+ *     8-10 - fine adjust clock delay
+ *     11- HS (high speed), if NCO mode=0: 0=72MHz 1=96Mhz
+ *     12- enable NCO mode
+ *
+ * Control 2:
+ *
+ * Bit 0-6  : gap_size, Gap = (gap_size * 2) + 4
+ *     16-31: HS = 0: Speed = 72 * Value / 8192 MBit/s
+ *            HS = 1: Speed = 72 * 8 / (Value + 1) MBit/s (only bit 19-16 used)
+ *
+ */
 
 static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
 {
 	struct ddb *dev = output->port->dev;
 	u32 bitrate = output->port->obr, max_bitrate = 72000;
 	u32 gap = 4, nco = 0;
-	
-	*con = 0x1C; 
+
+	*con = 0x1C;
 	if (output->port->gap != 0xffffffff) {
 		flags |= 1;
 		gap = output->port->gap;
@@ -698,7 +698,8 @@ static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
 						*con |= 0x800;
 					else {
 						*con |= 0x1000;
-						nco = (bitrate * 8192 + 71999) / 72000;
+						nco = (bitrate *
+						       8192 + 71999) / 72000;
 					}
 				}
 			} else {
@@ -707,7 +708,7 @@ static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
 				if (bitrate <= 64000) {
 					max_bitrate = 64000;
 					nco = 8;
-				} else if( bitrate <= 72000) {
+				} else if (bitrate <= 72000) {
 					max_bitrate = 72000;
 					nco = 7;
 				} else {
@@ -736,7 +737,6 @@ static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
 			gap = 127;
 	}
 	*con2 = (nco << 16) | gap;
-	 return;
 }
 
 static void ddb_output_start(struct ddb_output *output)
@@ -744,7 +744,7 @@ static void ddb_output_start(struct ddb_output *output)
 	struct ddb *dev = output->port->dev;
 	u32 con = 0x11c, con2 = 0;
 
-	printk("Channel Base = %08x\n", output->regs);
+	pr_info("Channel Base = %08x\n", output->regs);
 	if (output->dma) {
 		spin_lock_irq(&output->dma->lock);
 		output->dma->cbuf = 0;
@@ -811,7 +811,8 @@ static void ddb_input_stop(struct ddb_input *input)
 		spin_unlock_irq(&input->dma->lock);
 	}
 	/*printk("input_stop %u.%u.%u\n",
-	  dev->nr, input->port->lnr, input->nr);*/
+	 *  dev->nr, input->port->lnr, input->nr);
+	 */
 }
 
 static void ddb_input_start(struct ddb_input *input)
@@ -976,7 +977,8 @@ static ssize_t ddb_output_write(struct ddb_output *output,
 			dma_sync_single_for_device(dev->dev,
 						   output->dma->pbuf[
 							   output->dma->cbuf],
-						   output->dma->size, DMA_TO_DEVICE);
+						   output->dma->size,
+						   DMA_TO_DEVICE);
 		left -= len;
 		buf += len;
 		output->dma->coff += len;
@@ -1106,8 +1108,10 @@ static size_t ddb_input_read(struct ddb_input *input,
 			free = left;
 		if (alt_dma)
 			dma_sync_single_for_cpu(dev->dev,
-						input->dma->pbuf[input->dma->cbuf],
-						input->dma->size, DMA_FROM_DEVICE);
+						input->dma->pbuf[
+							input->dma->cbuf],
+						input->dma->size,
+						DMA_FROM_DEVICE);
 		ret = copy_to_user(buf, input->dma->vbuf[input->dma->cbuf] +
 				   input->dma->coff, free);
 		if (ret)
@@ -1656,7 +1660,8 @@ static int lnb_command(struct ddb *dev, u32 link, u32 lnb, u32 cmd)
 		msleep(20);
 	}
 	if (c == 10)
-		pr_info("DDBridge: lnb_command lnb = %08x  cmd = %08x\n", lnb, cmd);
+		pr_info("DDBridge: lnb_command lnb = %08x  cmd = %08x\n",
+			lnb, cmd);
 	return 0;
 }
 
@@ -1698,13 +1703,15 @@ static int lnb_send_diseqc(struct ddb *dev, u32 link, u32 input,
 	return 0;
 }
 
-static int lnb_set_sat(struct ddb *dev, u32 link, u32 input, u32 sat, u32 band, u32 hor)
+static int lnb_set_sat(struct ddb *dev, u32 link,
+		       u32 input, u32 sat, u32 band, u32 hor)
 {
 	struct dvb_diseqc_master_cmd cmd = {
 		.msg = {0xe0, 0x10, 0x38, 0xf0, 0x00, 0x00},
 		.msg_len = 4
 	};
-	cmd.msg[3] = 0xf0 | ( ((sat << 2) & 0x0c) | (band ? 1 : 0) | (hor ? 2 : 0));
+	cmd.msg[3] = 0xf0 | (((sat << 2) & 0x0c) |
+			     (band ? 1 : 0) | (hor ? 2 : 0));
 	return lnb_send_diseqc(dev, link, input, &cmd);
 }
 
@@ -2529,7 +2536,8 @@ static int init_xo2_ci(struct ddb_port *port)
 			port->nr, data[0]);
 		return -1;
 	}
-	pr_info("DDBridge: Port %d: DuoFlex CI %u.%u\n", port->nr, data[0], data[1]);
+	pr_info("DDBridge: Port %d: DuoFlex CI %u.%u\n",
+		port->nr, data[0], data[1]);
 
 	i2c_read_reg(i2c, 0x10, 0x08, &val);
 	if (val != 0) {
@@ -2615,15 +2623,15 @@ static void ddb_port_probe(struct ddb_port *port)
 		port->class = DDB_PORT_MOD;
 		return;
 	}
-	
+
 	if (dev->link[l].info->type == DDB_OCTOPRO_HDIN) {
-		if( port->nr == 0 ) {
+		if (port->nr == 0) {
 			dev->link[l].info->type = DDB_OCTOPUS;
 			port->name = "HDIN";
 			port->class = DDB_PORT_LOOP;
 		}
 		return;
-	}   
+	}
 
 	if (dev->link[l].info->type == DDB_OCTOPUS_MAX) {
 		port->name = "DUAL DVB-S2 MAX";
@@ -2657,7 +2665,7 @@ static void ddb_port_probe(struct ddb_port *port)
 			ddbwritel(dev, I2C_SPEED_400,
 				  port->i2c->regs + I2C_TIMING);
 		} else {
-			pr_info(KERN_INFO "DDBridge: Port %d: Uninitialized DuoFlex\n",
+			pr_info("DDBridge: Port %d: Uninitialized DuoFlex\n",
 			       port->nr);
 			return;
 		}
@@ -3214,7 +3222,8 @@ static void input_write_dvb(struct ddb_input *input,
 
 	dma = dma2 = input->dma;
 	/* if there also is an output connected, do not ACK.
-	   input_write_output will ACK. */
+	 * input_write_output will ACK.
+	 */
 	if (input->redo) {
 		dma2 = input->redo->dma;
 		ack = 0;
@@ -3229,7 +3238,7 @@ static void input_write_dvb(struct ddb_input *input,
 			dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf],
 						dma2->size, DMA_FROM_DEVICE);
 #if 0
-		pr_info("DDBridge: %02x %02x %02x %02x \n",
+		pr_info("DDBridge: %02x %02x %02x %02x\n",
 			dma2->vbuf[dma->cbuf][0], dma2->vbuf[dma->cbuf][1],
 			dma2->vbuf[dma->cbuf][2], dma2->vbuf[dma->cbuf][3]);
 #endif
@@ -3286,8 +3295,9 @@ static void input_handler(unsigned long data)
 
 
 	/* If there is no input connected, input_tasklet() will
-	   just copy pointers and ACK. So, there is no need to go
-	   through the tasklet scheduler. */
+	 * just copy pointers and ACK. So, there is no need to go
+	 * through the tasklet scheduler.
+	 */
 #ifdef DDB_USE_WORK
 	if (input->redi)
 		queue_work(ddb_wq, &dma->work);
@@ -3342,7 +3352,7 @@ static void ddb_dma_init(struct ddb_io *io, int nr, int out)
 {
 	struct ddb_dma *dma;
 	struct ddb_regmap *rm = io_regmap(io, 0);
-	
+
 	dma = out ? &io->port->dev->odma[nr] : &io->port->dev->idma[nr];
 	io->dma = dma;
 	dma->io = io;
@@ -3390,7 +3400,8 @@ static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
 	rm = io_regmap(input, 1);
 	input->regs = DDB_LINK_TAG(port->lnr) |
 		(rm->input->base + rm->input->size * nr);
-	pr_debug("DDBridge: init link %u, input %u, regs %08x\n", port->lnr, nr, input->regs); 
+	pr_debug("DDBridge: init link %u, input %u, regs %08x\n",
+		 port->lnr, nr, input->regs);
 	if (dev->has_dma) {
 		struct ddb_regmap *rm0 = io_regmap(input, 0);
 		u32 base = rm0->irq_base_idma;
@@ -3398,9 +3409,9 @@ static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
 
 		if (port->lnr)
 			dma_nr += 32 + (port->lnr - 1) * 8;
-		
+
 		pr_debug("DDBridge: init link %u, input %u, handler %u\n",
-			 port->lnr, nr, dma_nr + base); 
+			 port->lnr, nr, dma_nr + base);
 		dev->handler[0][dma_nr + base] = input_handler;
 		dev->handler_data[0][dma_nr + base] = (unsigned long) input;
 		ddb_dma_init(input, dma_nr, 0);
@@ -3420,7 +3431,7 @@ static void ddb_output_init(struct ddb_port *port, int nr)
 	output->regs = DDB_LINK_TAG(port->lnr) |
 		(rm->output->base + rm->output->size * nr);
 	pr_debug("DDBridge: init link %u, output %u, regs %08x\n",
-		 port->lnr, nr, output->regs); 
+		 port->lnr, nr, output->regs);
 	if (dev->has_dma) {
 		struct ddb_regmap *rm0 = io_regmap(output, 0);
 		u32 base = rm0->irq_base_odma;
@@ -3587,18 +3598,18 @@ static void ddb_ports_release(struct ddb *dev)
 		dev->handler[0][_nr](dev->handler_data[0][_nr]); } \
 	while (0)
 
-#define IRQ_HANDLE_BYTE(_n) \
-	if (s & (0x000000ff << ((_n) & 0x1f))) {	\
-		IRQ_HANDLE(0 + _n); \
-		IRQ_HANDLE(1 + _n); \
-		IRQ_HANDLE(2 + _n); \
-		IRQ_HANDLE(3 + _n); \
-		IRQ_HANDLE(4 + _n); \
-		IRQ_HANDLE(5 + _n); \
-		IRQ_HANDLE(6 + _n); \
-		IRQ_HANDLE(7 + _n); \
+#define IRQ_HANDLE_BYTE(_n) { \
+	if (s & (0x000000ff << ((_n) & 0x1f))) { \
+		IRQ_HANDLE(0 + (_n)); \
+		IRQ_HANDLE(1 + (_n)); \
+		IRQ_HANDLE(2 + (_n)); \
+		IRQ_HANDLE(3 + (_n)); \
+		IRQ_HANDLE(4 + (_n)); \
+		IRQ_HANDLE(5 + (_n)); \
+		IRQ_HANDLE(6 + (_n)); \
+		IRQ_HANDLE(7 + (_n)); \
+	} \
 	}
-	
 
 static void irq_handle_msg(struct ddb *dev, u32 s)
 {
@@ -3719,20 +3730,20 @@ static irqreturn_t irq_handle_v2_n(struct ddb *dev, u32 n)
 	if (!s)
 		return IRQ_NONE;
 	ddbwritel(dev, s, reg);
-	
+
 	if ((s & 0x000000ff)) {
-		IRQ_HANDLE( 0 + off);
-		IRQ_HANDLE( 1 + off);
-		IRQ_HANDLE( 2 + off);
-		IRQ_HANDLE( 3 + off);
-		IRQ_HANDLE( 4 + off);
-		IRQ_HANDLE( 5 + off);
-		IRQ_HANDLE( 6 + off);
-		IRQ_HANDLE( 7 + off);
+		IRQ_HANDLE(0 + off);
+		IRQ_HANDLE(1 + off);
+		IRQ_HANDLE(2 + off);
+		IRQ_HANDLE(3 + off);
+		IRQ_HANDLE(4 + off);
+		IRQ_HANDLE(5 + off);
+		IRQ_HANDLE(6 + off);
+		IRQ_HANDLE(7 + off);
 	}
 	if ((s & 0x0000ff00)) {
-		IRQ_HANDLE( 8 + off);
-		IRQ_HANDLE( 9 + off);
+		IRQ_HANDLE(8 + off);
+		IRQ_HANDLE(9 + off);
 		IRQ_HANDLE(10 + off);
 		IRQ_HANDLE(11 + off);
 		IRQ_HANDLE(12 + off);
@@ -3862,7 +3873,7 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
 			return -EINVAL;
 		ctrl = (input->port->lnr << 16) | ((input->nr & 7) << 8) |
 			((ts->filter_mask & 3) << 2);
-		/*pr_info("DDBridge: GET_TS %u.%u\n", input->port->lnr, input->nr);*/
+
 		if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) {
 			pr_info("DDBridge: ts capture busy\n");
 			return -EBUSY;
@@ -4463,7 +4474,7 @@ static ssize_t fan_store(struct device *device, struct device_attribute *d,
 			 const char *buf, size_t count)
 {
 	struct ddb *dev = dev_get_drvdata(device);
-	unsigned val;
+	u32 val;
 
 	if (sscanf(buf, "%u\n", &val) != 1)
 		return -EINVAL;
@@ -4493,7 +4504,7 @@ static ssize_t temp_show(struct device *device,
 	s32 temp, temp2, temp3;
 	int i;
 	u8 tmp[2];
-	
+
 	if (link->info->type == DDB_MOD) {
 		if (link->info->version >= 2) {
 			temp = 0xffff & ddbreadl(dev, TEMPMON2_BOARD);
@@ -4504,7 +4515,7 @@ static ssize_t temp_show(struct device *device,
 
 			temp3 = 0xffff & ddbreadl(dev, TEMPMON2_QAMCORE);
 			temp3 = (temp3 * 1000) >> 8;
-			
+
 			return sprintf(buf, "%d %d %d\n", temp, temp2, temp3);
 		}
 		ddbwritel(dev, 1, TEMPMON_CONTROL);
@@ -4639,7 +4650,7 @@ static ssize_t led_store(struct device *device,
 {
 	struct ddb *dev = dev_get_drvdata(device);
 	int num = attr->attr.name[3] - 0x30;
-	unsigned val;
+	u32 val;
 
 	if (sscanf(buf, "%u\n", &val) != 1)
 		return -EINVAL;
@@ -4799,7 +4810,7 @@ static ssize_t obr_show(struct device *device,
 {
 	struct ddb *dev = dev_get_drvdata(device);
 	int num = attr->attr.name[3] - 0x30;
-	
+
 	return sprintf(buf, "%d\n", dev->port[num].obr);
 
 }
@@ -4810,7 +4821,7 @@ static ssize_t obr_store(struct device *device, struct device_attribute *attr,
 	struct ddb *dev = dev_get_drvdata(device);
 	int num = attr->attr.name[3] - 0x30;
 	unsigned int val;
-	
+
 	if (sscanf(buf, "%u\n", &val) != 1)
 		return -EINVAL;
 	if (val > 96000)
@@ -5016,7 +5027,8 @@ static void ddb_device_attrs_del(struct ddb *dev)
 	for (i = 0; i < 4; i++)
 		if (dev->link[i].info &&
 		    dev->link[i].info->tempmon_irq)
-			device_remove_file(dev->ddb_dev, &ddb_attrs_fanspeed[i]);
+			device_remove_file(dev->ddb_dev,
+					   &ddb_attrs_fanspeed[i]);
 	for (i = 0; i < dev->link[0].info->temp_num; i++)
 		device_remove_file(dev->ddb_dev, &ddb_attrs_temp[i]);
 	for (i = 0; i < dev->link[0].info->port_num; i++)
@@ -5128,7 +5140,7 @@ static void link_tasklet(unsigned long data)
 	struct ddb *dev = link->dev;
 	u32 s, tag = DDB_LINK_TAG(link->nr);
 	u32 l = link->nr;
-	
+
 	s = ddbreadl(dev, tag | INTERRUPT_STATUS);
 	pr_info("DDBridge: gtl_irq %08x = %08x\n", tag | INTERRUPT_STATUS, s);
 
@@ -5257,7 +5269,7 @@ static int ddb_gtl_init(struct ddb *dev)
 	u32 l, base = dev->link[0].info->regmap->irq_base_gtl;
 
 	dev->handler_data[0][base] = (unsigned long) dev;
-	dev->handler[0][base] = gtl_link_handler; 
+	dev->handler[0][base] = gtl_link_handler;
 	for (l = 1; l < dev->link[0].info->regmap->gtl->num + 1; l++)
 		ddb_gtl_init_link(dev, l);
 	return 0;
@@ -5270,8 +5282,9 @@ static int ddb_gtl_init(struct ddb *dev)
 static void tempmon_setfan(struct ddb_link *link)
 {
 	u32 temp, temp2, pwm;
-	
-	if ((ddblreadl(link, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) {
+
+	if ((ddblreadl(link, TEMPMON_CONTROL) &
+	     TEMPMON_CONTROL_OVERTEMP) != 0) {
 		pr_info("DDBridge: Over temperature condition\n");
 		link->OverTemperatureError = 1;
 	}
@@ -5283,16 +5296,16 @@ static void tempmon_setfan(struct ddb_link *link)
 		temp2 = 0;
 	if (temp2 > temp)
 		temp = temp2;
-	
+
 	pwm = (ddblreadl(link, TEMPMON_FANCONTROL) >> 8) & 0x0F;
 	if (pwm > 10)
-		pwm = 10;   
-	
+		pwm = 10;
+
 	if (temp >= link->temp_tab[pwm]) {
-		while( pwm < 10 && temp >= link->temp_tab[pwm + 1])
+		while (pwm < 10 && temp >= link->temp_tab[pwm + 1])
 			pwm += 1;
 	} else {
-		while( pwm > 1 && temp < link->temp_tab[pwm - 2])
+		while (pwm > 1 && temp < link->temp_tab[pwm - 2])
 			pwm -= 1;
 	}
 	ddblwritel(link, (pwm << 8), TEMPMON_FANCONTROL);
@@ -5302,7 +5315,7 @@ static void tempmon_setfan(struct ddb_link *link)
 static void temp_handler(unsigned long data)
 {
 	struct ddb_link *link = (struct ddb_link *) data;
-	
+
 	spin_lock(&link->temp_lock);
 	tempmon_setfan(link);
 	spin_unlock(&link->temp_lock);
@@ -5313,12 +5326,14 @@ static int tempmon_init(struct ddb_link *link, int FirstTime)
 	struct ddb *dev = link->dev;
 	int status = 0;
 	u32 l = link->nr;
-	
+
 	spin_lock_irq(&link->temp_lock);
 	if (FirstTime) {
-		static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80};
-		
-		memcpy(link->temp_tab, TemperatureTable, sizeof(TemperatureTable));
+		static u8 TemperatureTable[11] = {
+			30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80};
+
+		memcpy(link->temp_tab, TemperatureTable,
+		       sizeof(TemperatureTable));
 	}
 	dev->handler[l][link->info->tempmon_irq] = temp_handler;
 	dev->handler_data[l][link->info->tempmon_irq] = (unsigned long) link;
@@ -5326,9 +5341,10 @@ static int tempmon_init(struct ddb_link *link, int FirstTime)
 			  TEMPMON_CONTROL_INTENABLE),
 		   TEMPMON_CONTROL);
 	ddblwritel(link, (3 << 8), TEMPMON_FANCONTROL);
-	
+
 	link->OverTemperatureError =
-		((ddblreadl(link, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0);
+		((ddblreadl(link, TEMPMON_CONTROL) &
+		  TEMPMON_CONTROL_OVERTEMP) != 0);
 	if (link->OverTemperatureError)	{
 		pr_info("DDBridge: Over temperature condition\n");
 		status = -1;
@@ -5341,7 +5357,7 @@ static int tempmon_init(struct ddb_link *link, int FirstTime)
 static int ddb_init_tempmon(struct ddb_link *link)
 {
 	struct ddb_info *info = link->info;
-	
+
 	if (!info->tempmon_irq)
 		return 0;
 	if (info->type == DDB_OCTOPUS_MAX ||
@@ -5371,7 +5387,7 @@ static int ddb_init_boards(struct ddb *dev)
 			l,
 			dev->link[l].ids.vendor, dev->link[l].ids.device,
 			dev->link[l].ids.subvendor, dev->link[l].ids.subdevice);
-		
+
 		if (info->board_control) {
 			ddbwritel(dev, 0, DDB_LINK_TAG(l) | BOARD_CONTROL);
 			msleep(100);
@@ -5393,7 +5409,7 @@ static int ddb_init(struct ddb *dev)
 	mutex_init(&dev->link[0].flash_mutex);
 	if (no_init) {
 		ddb_device_create(dev);
-		return 0;	
+		return 0;
 	}
 	if (dev->link[0].info->ns_num) {
 		ddbwritel(dev, 1, ETHER_CONTROL);
@@ -5401,7 +5417,7 @@ static int ddb_init(struct ddb *dev)
 		ddbwritel(dev, 14 + (dev->vlan ? 4 : 0), ETHER_LENGTH);
 	}
 	mutex_init(&dev->link[0].lnb.lock);
-	
+
 	if (dev->link[0].info->regmap->gtl)
 		ddb_gtl_init(dev);
 
@@ -5452,12 +5468,14 @@ static void ddb_reset_ios(struct ddb *dev)
 {
 	u32 i;
 	struct ddb_regmap *rm = dev->link[0].info->regmap;
-	
+
 	if (rm->input)
 		for (i = 0; i < rm->input->num; i++)
-			ddb_reset_io(dev, rm->input->base + i * rm->input->size);
+			ddb_reset_io(dev,
+				     rm->input->base + i * rm->input->size);
 	if (rm->output)
 		for (i = 0; i < rm->output->num; i++)
-			ddb_reset_io(dev, rm->output->base + i * rm->output->size);
+			ddb_reset_io(dev,
+				     rm->output->base + i * rm->output->size);
 	usleep_range(5000, 6000);
 }
diff --git a/ddbridge/ddbridge-i2c.c b/ddbridge/ddbridge-i2c.c
index 6fc63d5..8691eb9 100644
--- a/ddbridge/ddbridge-i2c.c
+++ b/ddbridge/ddbridge-i2c.c
@@ -169,7 +169,7 @@ static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
 			ddbcpyfrom(dev, msg[0].buf,
 				   i2c->rbuf, msg[0].len);
 			return num;
-		} 
+		}
 		ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len);
 		ddbwritel(dev, msg[0].len, i2c->regs + I2C_TASKLENGTH);
 		if (ddb_i2c_cmd(i2c, addr, 2))
diff --git a/ddbridge/ddbridge-mod.c b/ddbridge/ddbridge-mod.c
index 7783d3a..549e210 100644
--- a/ddbridge/ddbridge-mod.c
+++ b/ddbridge/ddbridge-mod.c
@@ -76,57 +76,62 @@ inline s64 RoundPCRDown(s64 a)
 	return a & ~(HW_LSB_MASK - 1);
 }
 
-// Calculating KF, LF from Symbolrate
-//
-//  Symbolrate is usually calculated as (M/N) * 10.24 MS/s
-//  
-//   Common Values for M,N 
-//     J.83 Annex A,
-//     Euro Docsis  6.952 MS/s : M =   869, N =  1280
-//                  6.900 MS/s : M =   345, N =   512
-//                  6.875 MS/s : M =  1375, N =  2048
-//                  6.111 MS/s : M =  6111, N = 10240
-//     J.83 Annex B **
-//      QAM64       5.056941   : M =   401, N =   812
-//      QAM256      5.360537   : M =    78, N =   149
-//     J.83 Annex C **
-//                  5.309734   : M =  1889, N =  3643
-//
-//    For the present hardware 
-//      KF' = 256 * M 
-//      LF' = 225 * N 
-//       or
-//      KF' = Symbolrate in Hz
-//      LF' = 9000000
-//
-//      KF  = KF' / gcd(KF',LF')
-//      LF  = LF' / gcd(KF',LF')
-// Note: LF must not be a power of 2.
-//       Maximum value for KF,LF = 13421727 ( 0x7FFFFFF )
-//    ** using these M,N values will result in a small err (<5ppm)
-//       calculating KF,LF directly gives the exact normative result
-//       but with rather large KF,LF values
+/* Calculating KF, LF from Symbolrate
+ *
+ *  Symbolrate is usually calculated as (M/N) * 10.24 MS/s
+ *
+ *   Common Values for M,N
+ *     J.83 Annex A,
+ *     Euro Docsis  6.952 MS/s : M =   869, N =  1280
+ *                  6.900 MS/s : M =   345, N =   512
+ *                  6.875 MS/s : M =  1375, N =  2048
+ *                  6.111 MS/s : M =  6111, N = 10240
+ *     J.83 Annex B **
+ *      QAM64       5.056941   : M =   401, N =   812
+ *      QAM256      5.360537   : M =    78, N =   149
+ *     J.83 Annex C **
+ *                  5.309734   : M =  1889, N =  3643
+ *
+ *    For the present hardware
+ *      KF' = 256 * M
+ *      LF' = 225 * N
+ *       or
+ *      KF' = Symbolrate in Hz
+ *      LF' = 9000000
+ *
+ *      KF  = KF' / gcd(KF',LF')
+ *      LF  = LF' / gcd(KF',LF')
+ * Note: LF must not be a power of 2.
+ *       Maximum value for KF,LF = 13421727 ( 0x7FFFFFF )
+ *    ** using these M,N values will result in a small err (<5ppm)
+ *       calculating KF,LF directly gives the exact normative result
+ *       but with rather large KF,LF values
+ */
 
-static inline u32 gcd(u32 u,u32 v)
+static inline u32 gcd(u32 u, u32 v)
 {
-    int s = 0;
-    while (((u|v)&1) == 0) {
-	    s += 1;
-	    u >>= 1;
-	    v >>= 1;
-    }
-    while ((u&1) == 0)
-	    u >>= 1;
-    do {
-	    while ( (v&1) == 0 ) v >>= 1;
-	    if( u > v ) {
-		    u32 t = v;
-		    v = u;
-		    u = t;
-	    }
-	    v = v - u;
-    } while(v != 0);
-    return u << s;
+	int s = 0;
+
+	while (((u | v) & 1) == 0) {
+		s += 1;
+		u >>= 1;
+		v >>= 1;
+	}
+	while ((u & 1) == 0)
+		u >>= 1;
+	do {
+		while ((v & 1) == 0)
+			v >>= 1;
+		if (u > v) {
+			u32 t = v;
+
+			v = u;
+			u = t;
+		}
+		v = v - u;
+	} while (v != 0);
+
+	return (u << s);
 }
 
 /****************************************************************************/
@@ -136,14 +141,14 @@ static inline u32 gcd(u32 u,u32 v)
 static int mod_SendChannelCommand(struct ddb *dev, u32 Channel, u32 Command)
 {
 	u32 ControlReg = ddbreadl(dev, CHANNEL_CONTROL(Channel));
-	
+
 	ControlReg = (ControlReg & ~CHANNEL_CONTROL_CMD_MASK)|Command;
 	ddbwritel(dev, ControlReg, CHANNEL_CONTROL(Channel));
-	while(1) {
+	while (1) {
 		ControlReg = ddbreadl(dev, CHANNEL_CONTROL(Channel));
 		if (ControlReg == 0xFFFFFFFF)
 			return -EIO;
-		if((ControlReg & CHANNEL_CONTROL_CMD_STATUS) == 0)
+		if ((ControlReg & CHANNEL_CONTROL_CMD_STATUS) == 0)
 			break;
 	}
 	if (ControlReg & CHANNEL_CONTROL_ERROR_CMD)
@@ -173,7 +178,8 @@ void ddbridge_mod_output_stop(struct ddb_output *output)
 	mod->State = CM_IDLE;
 	mod->Control &= 0xfffffff0;
 	if (dev->link[0].info->version == 2)
-		mod_SendChannelCommand(dev, output->nr, CHANNEL_CONTROL_CMD_FREE);
+		mod_SendChannelCommand(dev, output->nr,
+				       CHANNEL_CONTROL_CMD_FREE);
 	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 #if 0
 	udelay(10);
@@ -216,13 +222,13 @@ static void mod_set_rateinc(struct ddb *dev, u32 chan)
 static void mod_calc_rateinc(struct ddb_mod *mod)
 {
 	u32 ri;
-	
+
 	pr_info("DDBridge: ibitrate %llu\n", mod->ibitrate);
 	pr_info("DDBridge: obitrate %llu\n", mod->obitrate);
-	
+
 	if (mod->ibitrate != 0) {
 		u64 d = mod->obitrate - mod->ibitrate;
-		
+
 		d = div64_u64(d, mod->obitrate >> 24);
 		if (d > 0xfffffe)
 			ri = 0xfffffe;
@@ -237,7 +243,7 @@ static void mod_calc_rateinc(struct ddb_mod *mod)
 
 static int mod_calc_obitrate(struct ddb_mod *mod)
 {
-	u64 ofac; 
+	u64 ofac;
 
 	ofac = (((u64) mod->symbolrate) << 32) * 188;
 	ofac = div_u64(ofac, 204);
@@ -263,15 +269,17 @@ static int mod_set_symbolrate(struct ddb_mod *mod, u32 srate)
 
 static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 };
 
-static int mod_set_modulation(struct ddb_mod *mod, enum fe_modulation modulation)
+static int mod_set_modulation(struct ddb_mod *mod,
+			      enum fe_modulation modulation)
 {
 	struct ddb *dev = mod->port->dev;
 
 	if (modulation > QAM_256 || modulation < QAM_16)
 		return -EINVAL;
 	mod->modulation = modulation;
-	if (dev->link[0].info->version < 2) 
-		ddbwritel(dev, qamtab[modulation], CHANNEL_SETTINGS(mod->port->nr));
+	if (dev->link[0].info->version < 2)
+		ddbwritel(dev, qamtab[modulation],
+			  CHANNEL_SETTINGS(mod->port->nr));
 	mod_calc_obitrate(mod);
 	return 0;
 }
@@ -279,7 +287,7 @@ static int mod_set_modulation(struct ddb_mod *mod, enum fe_modulation modulation
 static int mod_set_frequency(struct ddb_mod *mod, u32 frequency)
 {
 	u32 freq = frequency / 1000000;
-	
+
 	if (frequency % 1000000)
 		return -EINVAL;
 	if ((freq - 114) % 8)
@@ -324,58 +332,62 @@ int ddbridge_mod_output_start(struct ddb_output *output)
 
 	mod->State = CM_STARTUP;
 	mod->StateCounter = CM_STARTUP_DELAY;
-	
+
 	if (dev->link[0].info->version == 3)
-		mod->Control = 0xfffffff0 & ddbreadl(dev, CHANNEL_CONTROL(output->nr));
+		mod->Control = 0xfffffff0 &
+			ddbreadl(dev, CHANNEL_CONTROL(output->nr));
 	else
 		mod->Control = 0;
 	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 	udelay(10);
-	ddbwritel(dev, mod->Control | CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr));
+	ddbwritel(dev, mod->Control | CHANNEL_CONTROL_RESET,
+		  CHANNEL_CONTROL(output->nr));
 	udelay(10);
 	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 
-	//pr_info("DDBridge: CHANNEL_BASE = %08x\n", CHANNEL_BASE);
-	///pr_info("DDBridge: CHANNEL_CONTROL = %08x\n", CHANNEL_CONTROL(Channel));
 	if (dev->link[0].info->version == 2) {
-		//u32 Output = ((dev->mod_base.frequency - 114000000)/8000000 + Channel) % 96;
 		u32 Output = (mod->frequency - 114000000) / 8000000;
 		u32 KF = Symbolrate;
 		u32 LF = 9000000UL;
-		u32 d = gcd(KF,LF);
+		u32 d = gcd(KF, LF);
 		u32 checkLF;
 
 		ddbwritel(dev, mod->modulation - 1, CHANNEL_SETTINGS(Channel));
 		ddbwritel(dev, Output, CHANNEL_SETTINGS2(Channel));
-		
+
 		KF = KF / d;
 		LF = LF / d;
-		
-		while( (KF > KFLF_MAX) || (LF > KFLF_MAX) ) {
+
+		while ((KF > KFLF_MAX) || (LF > KFLF_MAX)) {
 			KF >>= 1;
 			LF >>= 1;
 		}
-		
+
 		checkLF = LF;
 		while ((checkLF & 1) == 0)
 			checkLF >>= 1;
 		if (checkLF <= 1)
 			return -EINVAL;
 
-		pr_info("DDBridge: KF=%u LF=%u Output=%u mod=%u\n", KF, LF, Output, mod->modulation);
+		pr_info("DDBridge: KF=%u LF=%u Output=%u mod=%u\n",
+			KF, LF, Output, mod->modulation);
 		ddbwritel(dev, KF, CHANNEL_KF(Channel));
 		ddbwritel(dev, LF, CHANNEL_LF(Channel));
-		
-		if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_SETUP))
+
+		if (mod_SendChannelCommand(dev, Channel,
+					   CHANNEL_CONTROL_CMD_SETUP))
 			return -EINVAL;
 		mod->Control |= CHANNEL_CONTROL_ENABLE_DVB;
-	} else 	if (dev->link[0].info->version == 1) {
+	} else if (dev->link[0].info->version == 1) {
 		/* QAM: 600 601 602 903 604 = 16 32 64 128 256 */
 		/* ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); */
-		ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr));
-		mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ | CHANNEL_CONTROL_ENABLE_DVB);
+		ddbwritel(dev, qamtab[mod->modulation],
+			  CHANNEL_SETTINGS(output->nr));
+		mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ |
+				 CHANNEL_CONTROL_ENABLE_DVB);
 	} else if (dev->link[0].info->version == 3) {
-		mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ | CHANNEL_CONTROL_ENABLE_DVB);
+		mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ |
+				 CHANNEL_CONTROL_ENABLE_DVB);
 	}
 	if (dev->link[0].info->version < 3) {
 		mod_set_rateinc(dev, output->nr);
@@ -385,7 +397,8 @@ int ddbridge_mod_output_start(struct ddb_output *output)
 
 	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 	if (dev->link[0].info->version == 2)
-		if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_UNMUTE))
+		if (mod_SendChannelCommand(dev, Channel,
+					   CHANNEL_CONTROL_CMD_UNMUTE))
 			return -EINVAL;
 	pr_info("DDBridge: mod_output_start %d.%d ctrl=%08x\n",
 		dev->nr, output->nr, mod->Control);
@@ -399,9 +412,11 @@ int ddbridge_mod_output_start(struct ddb_output *output)
 static int mod_write_max2871(struct ddb *dev, u32 val)
 {
 	ddbwritel(dev, val, MAX2871_OUTDATA);
-	ddbwritel(dev, MAX2871_CONTROL_CE | MAX2871_CONTROL_WRITE, MAX2871_CONTROL);
-	while(1) {
+	ddbwritel(dev, MAX2871_CONTROL_CE | MAX2871_CONTROL_WRITE,
+		  MAX2871_CONTROL);
+	while (1) {
 		u32 ControlReg = ddbreadl(dev, MAX2871_CONTROL);
+
 		if (ControlReg == 0xFFFFFFFF)
 			return -EIO;
 		if ((ControlReg & MAX2871_CONTROL_WRITE) == 0)
@@ -423,14 +438,14 @@ static int mod_setup_max2871(struct ddb *dev, u32 *reg)
 	int status = 0;
 	int i, j;
 	u32 val;
-	
+
 	ddbwritel(dev, MAX2871_CONTROL_CE, MAX2871_CONTROL);
 	msleep(30);
 	for (i = 0; i < 2; i++) {
 		for (j = 5; j >= 0; j--) {
 			val = reg[j];
-			
-			if (j ==4)
+
+			if (j == 4)
 				val &= 0xFFFFFEDF;
 			status = mod_write_max2871(dev, reg[j]);
 			if (status)
@@ -452,19 +467,20 @@ static int mod_setup_max2871(struct ddb *dev, u32 *reg)
 	return status;
 }
 
-static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels)
+static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan,
+			 u32 MaxUsedChannels)
 {
 	int status = 0;
 	u32 Capacity;
 	u32 tmp = ddbreadl(dev, FSM_STATUS);
-	
+
 	if ((tmp & FSM_STATUS_READY) == 0) {
 		status = mod_setup_max2871(dev, max2871_fsm);
 		if (status)
 			return status;
 		ddbwritel(dev, FSM_CMD_RESET, FSM_CONTROL);
-		msleep(10);
-		
+		msleep(20);
+
 		tmp = ddbreadl(dev, FSM_STATUS);
 		if ((tmp & FSM_STATUS_READY) == 0)
 			return -1;
@@ -473,23 +489,23 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels
 	if (((tmp & FSM_STATUS_QAMREADY) != 0) &&
 	    ((Capacity & FSM_CAPACITY_INUSE) != 0))
 		return -EBUSY;
-	
+
 	ddbwritel(dev, FSM_CMD_SETUP, FSM_CONTROL);
-	msleep(10);
+	msleep(20);
 	tmp = ddbreadl(dev, FSM_STATUS);
-	
+
 	if ((tmp & FSM_STATUS_QAMREADY) == 0)
 		return -1;
-	
+
 	if (MaxUsedChannels == 0)
 		MaxUsedChannels = (Capacity & FSM_CAPACITY_CUR) >> 16;
 
 	pr_info("DDBridge: max used chan = %u\n", MaxUsedChannels);
-	if (MaxUsedChannels <= 1 )
+	if (MaxUsedChannels <= 1)
 		ddbwritel(dev, FSM_GAIN_N1, FSM_GAIN);
 	else if (MaxUsedChannels <= 2)
 		ddbwritel(dev, FSM_GAIN_N2, FSM_GAIN);
-	else if (MaxUsedChannels <= 4) 
+	else if (MaxUsedChannels <= 4)
 		ddbwritel(dev, FSM_GAIN_N4, FSM_GAIN);
 	else if (MaxUsedChannels <= 8)
 		ddbwritel(dev, FSM_GAIN_N8, FSM_GAIN);
@@ -507,84 +523,12 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels
 
 static int mod_set_vga(struct ddb *dev, u32 Gain)
 {
-	if( Gain > 255 )
+	if (Gain > 255)
 		return -EINVAL;
 	ddbwritel(dev, Gain, RF_VGA);
 	return 0;
 }
 
-#if 0
-static int mod_get_vga(struct ddb *dev, u32 *pGain)
-{
-	*pGain = ddbreadl(dev, RF_VGA);
-	return 0;
-}
-
-static void TemperatureMonitorSetFan(struct ddb *dev)
-{
-	u32 tqam, pwm;
-	
-	if ((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) {
-		pr_info("DDBridge: Over temperature condition\n");
-		dev->OverTemperatureError = 1;
-	}
-	tqam  = (ddbreadl(dev, TEMPMON2_QAMCORE) >> 8) & 0xFF;
-	if (tqam & 0x80)
-		tqam = 0;
-	
-	pwm = (ddbreadl(dev, TEMPMON_FANCONTROL) >> 8) & 0x0F;
-	if (pwm > 10)
-		pwm = 10;   
-	
-	if (tqam >= dev->temp_tab[pwm]) {
-		while( pwm < 10 && tqam >= dev->temp_tab[pwm + 1])
-			pwm += 1;
-	} else {
-		while( pwm > 1 && tqam < dev->temp_tab[pwm - 2])
-			pwm -= 1;
-	}
-	ddbwritel(dev, (pwm << 8), TEMPMON_FANCONTROL);
-}
-
-
-static void temp_handler(unsigned long data)
-{
-	struct ddb *dev = (struct ddb *) data;
-
-	pr_info("DDBridge: temp_handler\n");
-
-	spin_lock(&dev->temp_lock);
-	TemperatureMonitorSetFan(dev);
-	spin_unlock(&dev->temp_lock);
-}
-
-static int TemperatureMonitorInit(struct ddb *dev, int FirstTime) {
-	int status = 0;
-	
-	spin_lock_irq(&dev->temp_lock);
-	if (FirstTime) {
-		static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80};
-		
-		memcpy(dev->temp_tab, TemperatureTable, sizeof(TemperatureTable));
-	}
-	dev->handler[0][8] = temp_handler;
-	dev->handler_data[0][8] = (unsigned long) dev;
-	ddbwritel(dev, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN |
-			TEMPMON_CONTROL_INTENABLE),
-		  TEMPMON_CONTROL);
-	ddbwritel(dev, (3 << 8), TEMPMON_FANCONTROL);
-	
-	dev->OverTemperatureError =
-		((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0);
-	if (dev->OverTemperatureError)	{
-		pr_info("DDBridge: Over temperature condition\n");
-		status = -1;
-	}
-	TemperatureMonitorSetFan(dev);
-	spin_unlock_irq(&dev->temp_lock);
-	return status;
-}
-#endif
 /****************************************************************************/
 /****************************************************************************/
 /****************************************************************************/
@@ -749,7 +693,8 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
 		     ((u32)(Data[1] & 0xE0) >> 6)) + 1;
 		fDCO = fOut * (u64)(HSDiv * N);
 		m_fXtal = fDCO << 28;
-		pr_info("DDBridge: fxtal %016llx  rfreq %016llx\n", m_fXtal, RFreq);
+		pr_info("DDBridge: fxtal %016llx  rfreq %016llx\n",
+			m_fXtal, RFreq);
 
 		m_fXtal += RFreq >> 1;
 		m_fXtal = div64_u64(m_fXtal, RFreq);
@@ -950,9 +895,9 @@ static int mod_init_dac_input(struct ddb *dev)
 	Seek = 1;
 	for (Sample = 0; Sample < 32; Sample += 1) {
 		/* printk(" %2d: %d %2d %2d\n",
-		   Sample, SeekTable[Sample], SetTable[Sample],
-		   HldTable[Sample]);
-		*/
+		 * Sample, SeekTable[Sample], SetTable[Sample],
+		 * HldTable[Sample]);
+		 */
 
 		if (Sample1 == 0xFF && SeekTable[Sample] == 1 && Seek == 0)
 			Sample1 = Sample;
@@ -1244,7 +1189,8 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)
 	FrequencyCH10 = flash->DataSet[0].FlatStart + 4;
 	DownFrequency = Frequency + 9 * 8 + FrequencyCH10 +
 		UP1Frequency + UP2Frequency;
-	pr_info("DDBridge: CH10 = %d, Down = %d\n", FrequencyCH10, DownFrequency);
+	pr_info("DDBridge: CH10 = %d, Down = %d\n",
+			FrequencyCH10, DownFrequency);
 
 	if ((FrequencyCH10 + 9 * 8) > (flash->DataSet[0].FlatEnd - 4)) {
 		pr_err("DDBridge: Frequency out of range %d\n", FrequencyCH10);
@@ -1296,10 +1242,10 @@ fail:
 #define FACTOR         (1ULL << 22)
 
 /*
-  double Increment =  FACTOR*PACKET_CLOCKS/double(m_OutputBitrate);
-  double Decrement =  FACTOR*PACKET_CLOCKS/double(m_InputBitrate);
-  27000000 * 1504 * 2^22 / (6900000 * 188 / 204) = 26785190066.1
-*/
+ * double Increment =  FACTOR*PACKET_CLOCKS/double(m_OutputBitrate);
+ * double Decrement =  FACTOR*PACKET_CLOCKS/double(m_InputBitrate);
+ * 27000000 * 1504 * 2^22 / (6900000 * 188 / 204) = 26785190066.1
+ */
 
 void ddbridge_mod_rate_handler(unsigned long data)
 {
@@ -1484,7 +1430,7 @@ void ddbridge_mod_rate_handler(unsigned long data)
 static int mod3_set_base_frequency(struct ddb *dev, u32 frequency)
 {
 	u64 tmp;
-	
+
 	if (frequency % 1000)
 		return -EINVAL;
 	if ((frequency < 114000000) || (frequency > 874000000))
@@ -1493,7 +1439,7 @@ static int mod3_set_base_frequency(struct ddb *dev, u32 frequency)
 	tmp = frequency;
 	tmp <<= 33;
 	tmp = div64_s64(tmp, 4915200000);
-	printk("set base frequency = %u  regs = 0x%08llx\n", frequency, tmp);
+	pr_info("set base frequency = %u  regs = 0x%08llx\n", frequency, tmp);
 	ddbwritel(dev, (u32) tmp, RFDAC_FCW);
 	return 0;
 }
@@ -1505,18 +1451,18 @@ static void mod3_set_cfcw(struct ddb_mod *mod, u32 f)
 	s32 dcf = dev->mod_base.frequency;
 	s64 tmp, srdac = 245760000;
 	u32 cfcw;
-	
+
 	tmp = ((s64) (freq - dcf)) << 32;
 	tmp = div64_s64(tmp, srdac);
 	cfcw = (u32) tmp;
-	printk("f=%u cfcw = %08x nr = %u\n", f, cfcw, mod->port->nr);
+	pr_info("f=%u cfcw = %08x nr = %u\n", f, cfcw, mod->port->nr);
 	ddbwritel(dev, cfcw, SDR_CHANNEL_CFCW(mod->port->nr));
 }
 
 static int mod3_set_frequency(struct ddb_mod *mod, u32 frequency)
 {
 	struct ddb *dev = mod->port->dev;
-	
+
 #if 0
 	if (frequency % 1000)
 		return -EINVAL;
@@ -1542,7 +1488,7 @@ static int mod3_set_ari(struct ddb_mod *mod, u32 rate)
 
 static int mod3_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
 {
-	switch(tvp->cmd) {
+	switch (tvp->cmd) {
 	case MODULATOR_OUTPUT_ARI:
 		return mod3_set_ari(mod, tvp->u.data);
 
@@ -1559,7 +1505,7 @@ static int mod_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
 {
 	if (mod->port->dev->link[0].info->version == 3)
 		return mod3_prop_proc(mod, tvp);
-	switch(tvp->cmd) {
+	switch (tvp->cmd) {
 	case MODULATOR_SYMBOL_RATE:
 		return mod_set_symbolrate(mod, tvp->u.data);
 
@@ -1586,20 +1532,22 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
 	struct ddb *dev = output->port->dev;
 	struct ddb_mod *mod = &dev->mod[output->nr];
 	int ret = 0;
-	
+
 	if (dev->link[0].info->version == 3 && cmd != FE_SET_PROPERTY)
 		return -EINVAL;
 	switch (cmd) {
 	case FE_SET_PROPERTY:
 	{
-		struct dtv_properties *tvps = (struct dtv_properties __user *) parg;
+		struct dtv_properties *tvps =
+			(struct dtv_properties __user *) parg;
 		struct dtv_property *tvp = NULL;
 		int i;
-		
+
 		if ((tvps->num == 0) || (tvps->num > DTV_IOCTL_MAX_MSGS))
 			return -EINVAL;
-		
-		tvp = kmalloc(tvps->num * sizeof(struct dtv_property), GFP_KERNEL);
+
+		tvp = kmalloc(tvps->num * sizeof(struct dtv_property),
+			      GFP_KERNEL);
 		if (!tvp) {
 			ret = -ENOMEM;
 			goto out;
@@ -1610,11 +1558,12 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
 			goto out;
 		}
 		for (i = 0; i < tvps->num; i++) {
-			if ((ret = mod_prop_proc(mod, tvp + i)) < 0)
+			ret = mod_prop_proc(mod, tvp + i);
+			if (ret < 0)
 				goto out;
 			(tvp + i)->result = ret;
 		}
-	out:
+out:
 		kfree(tvp);
 		return ret;
 	}
@@ -1677,7 +1626,7 @@ static int mod_init_2(struct ddb *dev, u32 Frequency)
 		pr_err("FSM setup failed!\n");
 		return -1;
 	}
-	
+
 	for (i = 0; i < streams; i++) {
 		struct ddb_mod *mod = &dev->mod[i];
 
@@ -1692,7 +1641,7 @@ static int mod_init_2(struct ddb *dev, u32 Frequency)
 		mod_set_vga(dev, RF_VGA_GAIN_N16);
 	else
 		mod_set_vga(dev, RF_VGA_GAIN_N24);
-	
+
 	mod_set_attenuator(dev, 0);
 	return 0;
 }
@@ -1732,7 +1681,7 @@ static void mod_set_sdr_table(struct ddb_mod *mod, u32 *tab, u32 len)
 	struct ddb *dev = mod->port->dev;
 	u32 i;
 
-	for (i = 0; i < len; i++) 
+	for (i = 0; i < len; i++)
 		ddbwritel(dev, tab[i], SDR_CHANNEL_SETFIR(mod->port->nr));
 }
 
@@ -1740,45 +1689,45 @@ static int rfdac_init(struct ddb *dev)
 {
 	int i;
 	u32 tmp;
-	
+
 	ddbwritel(dev, RFDAC_CMD_POWERDOWN, RFDAC_CONTROL);
 	for (i = 0; i < 10; i++) {
-		msleep(10);
+		msleep(20);
 		tmp = ddbreadl(dev, RFDAC_CONTROL);
 		if ((tmp & RFDAC_CMD_STATUS) == 0x00)
 			break;
 	}
 	if (tmp & 0x80)
 		return -1;
-	printk("sync %d:%08x\n", i, tmp);
+	pr_info("sync %d:%08x\n", i, tmp);
 	ddbwritel(dev, RFDAC_CMD_RESET, RFDAC_CONTROL);
 	for (i = 0; i < 10; i++) {
-		msleep(10);
+		msleep(20);
 		tmp = ddbreadl(dev, RFDAC_CONTROL);
 		if ((tmp & RFDAC_CMD_STATUS) == 0x00)
 			break;
 	}
 	if (tmp & 0x80)
 		return -1;
-	printk("sync %d:%08x\n", i, tmp);
+	pr_info("sync %d:%08x\n", i, tmp);
 	ddbwritel(dev, RFDAC_CMD_SETUP, RFDAC_CONTROL);
 	for (i = 0; i < 10; i++) {
-		msleep(10);
+		msleep(20);
 		tmp = ddbreadl(dev, RFDAC_CONTROL);
 		if ((tmp & RFDAC_CMD_STATUS) == 0x00)
 			break;
 	}
 	if (tmp & 0x80)
 		return -1;
-	printk("sync %d:%08x\n", i, tmp);
- 	ddbwritel(dev, 0x01, JESD204B_BASE);
+	pr_info("sync %d:%08x\n", i, tmp);
+	ddbwritel(dev, 0x01, JESD204B_BASE);
 	for (i = 0; i < 400; i++) {
-		msleep(10);
+		msleep(20);
 		tmp = ddbreadl(dev, JESD204B_BASE);
 		if ((tmp & 0xc0000000) == 0xc0000000)
 			break;
 	}
-	printk("sync %d:%08x\n", i, tmp);
+	pr_info("sync %d:%08x\n", i, tmp);
 	if ((tmp & 0xc0000000) != 0xc0000000)
 		return -1;
 	return 0;
@@ -1801,8 +1750,8 @@ static int mod_init_3(struct ddb *dev, u32 Frequency)
 
 	for (i = 0; i < streams; i++) {
 		struct ddb_mod *mod = &dev->mod[i];
+
 		mod->port = &dev->port[i];
-		
 		mod_set_sdr_table(mod, vsb13500, 64);
 		mod_set_sdr_table(mod, stage2, 16);
 	}
diff --git a/ddbridge/ddbridge-ns.c b/ddbridge/ddbridge-ns.c
index e5e69cf..9e3fcd6 100644
--- a/ddbridge/ddbridge-ns.c
+++ b/ddbridge/ddbridge-ns.c
@@ -87,7 +87,6 @@ static int ns_alloc(struct dvbnss *nss)
 		dev->ns[i].fe = input;
 		nss->priv = &dev->ns[i];
 		ret = 0;
-		/*pr_info("DDBridge: %s i=%d fe=%d\n", __func__, i, input->nr); */
 		break;
 	}
 	ddbwritel(dev, 0x03, RTP_MASTER_CONTROL);
@@ -446,8 +445,6 @@ static int ns_start(struct dvbnss *nss)
 	if (dns->fe != input)
 		ddb_dvb_ns_input_start(dns->fe);
 	ddb_dvb_ns_input_start(input);
-	/* printk("ns start ns %u, fe %u link %u\n",
-	   dns->nr, dns->fe->nr, dns->fe->port->lnr); */
 	ddbwritel(dev, reg | (dns->fe->nr << 8) | (dns->fe->port->lnr << 16),
 		  STREAM_CONTROL(dns->nr));
 	return 0;
diff --git a/ddbridge/ddbridge-regs.h b/ddbridge/ddbridge-regs.h
index 28d33c1..b62a5b2 100644
--- a/ddbridge/ddbridge-regs.h
+++ b/ddbridge/ddbridge-regs.h
@@ -58,9 +58,9 @@
 /* ------------------------------------------------------------------------- */
 
 /* Interrupt controller
-   How many MSI's are available depends on HW (Min 2 max 8)
-   How many are usable also depends on Host platform
-*/
+ * How many MSI's are available depends on HW (Min 2 max 8)
+ * How many are usable also depends on Host platform
+ */
 
 #define INTERRUPT_BASE   (0x40)
 
@@ -167,13 +167,15 @@
 #define TEMPMON_FANPWM      (0x00000F00)            // PWM speed in 10% steps
 #define TEMPMON_FANTACHO    (0x000000FF)            // Rotations in 100/min steps
 
-// V1 Temperature Monitor
-// Temperature Monitor TEMPMON_CONTROL & 0x8000 == 0 : ( 2x LM75A @ 0x90,0x92 )
-// Temperature Monitor TEMPMON_CONTROL & 0x8000 == 1 : ( 1x LM75A @ 0x90, 1x ADM1032 @ 0x9A )
+/* V1 Temperature Monitor
+ * Temperature Monitor TEMPMON_CONTROL & 0x8000 == 0 : ( 2x LM75A @ 0x90,0x92 )
+ * Temperature Monitor TEMPMON_CONTROL & 0x8000 == 1 :
+ * ( 1x LM75A @ 0x90, 1x ADM1032 @ 0x9A )
+ */
 
-#define TEMPMON1_CORE       (TEMPMON_SENSOR0)    // SHORT Temperature in °C x 256 (ADM1032 ext)
-#define TEMPMON1_SENSOR1    (TEMPMON_BASE + 0x08)    // SHORT Temperature in °C x 256 (LM75A 0x90)
-#define TEMPMON1_SENSOR2    (TEMPMON_BASE + 0x0C)    // SHORT Temperature in °C x 256 (LM75A 0x92 or ADM1032 Int)
+#define TEMPMON1_CORE       (TEMPMON_SENSOR0)    // u16 Temperature in °C x 256 (ADM1032 ext)
+#define TEMPMON1_SENSOR1    (TEMPMON_BASE + 0x08) // SHORT Temperature in °C x 256 (LM75A 0x90)
+#define TEMPMON1_SENSOR2    (TEMPMON_BASE + 0x0C) // SHORT Temperature in °C x 256 (LM75A 0x92 or ADM1032 Int)
 
 // V2 Temperature Monitor 2 ADM1032
 
@@ -332,16 +334,16 @@
 /* Muxout from VCO (usually = Lock) */
 #define VCO3_CONTROL_MUXOUT (0x00000004)
 
-// V2
+/* V2 */
 
 #define MAX2871_BASE            (0xC0)
 #define MAX2871_CONTROL         (MAX2871_BASE + 0x00)
-#define MAX2871_OUTDATA         (MAX2871_BASE + 0x04)  // 32 Bit
-#define MAX2871_INDATA          (MAX2871_BASE + 0x08)  // 32 Bit
+#define MAX2871_OUTDATA         (MAX2871_BASE + 0x04)
+#define MAX2871_INDATA          (MAX2871_BASE + 0x08)
 #define MAX2871_CONTROL_WRITE   (0x00000001)   // 1 = Trigger write, resets when done
 #define MAX2871_CONTROL_CE      (0x00000002)   // 0 = Put VCO into power down
-#define MAX2871_CONTROL_MUXOUT  (0x00000004)   // Muxout from VCO 
-#define MAX2871_CONTROL_LOCK    (0x00000008)   // Lock from VCO 
+#define MAX2871_CONTROL_MUXOUT  (0x00000004)   // Muxout from VCO
+#define MAX2871_CONTROL_LOCK    (0x00000008)   // Lock from VCO
 
 #define FSM_BASE                (0x200)
 #define FSM_CONTROL             (FSM_BASE + 0x00)
@@ -360,9 +362,9 @@
 
 
 #define FSM_CAPACITY            (FSM_BASE + 0x04)
-#define FSM_CAPACITY_MAX        (0x3F000000)  
-#define FSM_CAPACITY_CUR        (0x003F0000)  
-#define FSM_CAPACITY_INUSE      (0x0000003F)  
+#define FSM_CAPACITY_MAX        (0x3F000000)
+#define FSM_CAPACITY_CUR        (0x003F0000)
+#define FSM_CAPACITY_INUSE      (0x0000003F)
 
 #define FSM_GAIN                (FSM_BASE + 0x10)
 #define FSM_GAINMASK            (0x000000FF)
@@ -381,15 +383,15 @@
 #define RF_ATTENUATOR   (0xD8)
 #define RF_ATTENUATOR   (0xD8)
 /*  0x00 =  0 dB
-    0x01 =  1 dB
-      ...
-    0x1F = 31 dB
-*/
+ *  0x01 =  1 dB
+ *    ...
+ *  0x1F = 31 dB
+ */
 
 #define RF_VGA  (0xDC)
 /* Only V2 */
 /* 8 bit range 0 - 31.75 dB Gain  */
-	
+
 /* VGA Gain for same output level as V1 Modulator */
 #define RF_VGA_GAIN_N8          (85)
 #define RF_VGA_GAIN_N16         (117)
@@ -411,9 +413,9 @@
 #define RF_POWER_CONTROL_VALID     (0x00000500)
 
 
-/* --------------------------------------------------------------------------
-   Output control
-*/
+/*
+ *  Output control
+ */
 
 #define IQOUTPUT_BASE           (0x240)
 #define IQOUTPUT_CONTROL        (IQOUTPUT_BASE + 0x00)
@@ -581,7 +583,7 @@
 
 // Additional Status Bits
 
-#define DMA_PCIE_LANES_MASK       ( 0x00070000 )
+#define DMA_PCIE_LANES_MASK       (0x00070000)
 
 
 // --------------------------------------------------------------------------
@@ -619,7 +621,7 @@
 #define SDR_FIR_SELECT_MASK         (0x00C00000)
 #define SDR_VSB_LENGTH_MASK         (0x01000000)
 
-#define SDR_SET_FIR(select,tap,coeff,vsblen)	\
+#define SDR_SET_FIR(select, tap, coeff, vsblen)	\
 	((((select)<<22)&SDR_FIR_SELECT_MASK)|			\
 	 (((tap)<<16)&SDR_FIR_TAP_MASK)|				\
 	 ((coeff)&SDR_FIR_COEFF_MASK)|					\
diff --git a/ddbridge/ddbridge.c b/ddbridge/ddbridge.c
index 5c2b2a7..a4b19d1 100644
--- a/ddbridge/ddbridge.c
+++ b/ddbridge/ddbridge.c
@@ -129,7 +129,7 @@ static int __devinit ddb_irq_msi(struct ddb *dev, int nr)
 				dev->msi);
 		} else
 			pr_info("DDBridge: MSI not available.\n");
-		
+
 #else
 		stat = pci_enable_msi_block(dev->pdev, nr);
 		if (stat == 0) {
@@ -139,7 +139,7 @@ static int __devinit ddb_irq_msi(struct ddb *dev, int nr)
 			stat = pci_enable_msi(dev->pdev);
 			dev->msi = 1;
 		}
-		if (stat < 0) 
+		if (stat < 0)
 			pr_info("DDBridge: MSI not available.\n");
 #endif
 	}
@@ -170,7 +170,7 @@ static int __devinit ddb_irq_init2(struct ddb *dev)
 			   irq_flag, "ddbridge", (void *) dev);
 	if (stat < 0)
 		return stat;
-	
+
 	ddbwritel(dev, 0x0000ff7f, INTERRUPT_V2_CONTROL);
 	ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_1);
 	ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_2);
@@ -181,15 +181,15 @@ static int __devinit ddb_irq_init2(struct ddb *dev)
 	ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_7);
 	return stat;
 }
-	
+
 static int __devinit ddb_irq_init(struct ddb *dev)
 {
 	int stat;
 	int irq_flag = IRQF_SHARED;
-	
+
 	if (dev->link[0].info->regmap->irq_version == 2)
 		return ddb_irq_init2(dev);
-	
+
 	ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE);
 	ddbwritel(dev, 0x00000000, MSI1_ENABLE);
 	ddbwritel(dev, 0x00000000, MSI2_ENABLE);
@@ -254,7 +254,7 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
 	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
 		if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
 			return -ENODEV;
-	
+
 	dev = vzalloc(sizeof(struct ddb));
 	if (dev == NULL)
 		return -ENOMEM;
@@ -315,7 +315,7 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
 	stat = ddb_irq_init(dev);
 	if (stat < 0)
 		goto fail0;
-	
+
 	if (ddb_init(dev) == 0)
 		return 0;
 
diff --git a/ddbridge/ddbridge.h b/ddbridge/ddbridge.h
index add55b3..44ee9ba 100644
--- a/ddbridge/ddbridge.h
+++ b/ddbridge/ddbridge.h
@@ -122,7 +122,7 @@ struct ddb_regmap {
 
 	struct ddb_regset *input;
 	struct ddb_regset *output;
-	
+
 	struct ddb_regset *channel;
 	//struct ddb_regset *ci;
 	//struct ddb_regset *pid_filter;
@@ -191,7 +191,8 @@ struct ddb_info {
 };
 
 /* DMA_SIZE MUST be smaller than 256k and
-   MUST be divisible by 188 and 128 !!! */
+ * MUST be divisible by 188 and 128 !!!
+ */
 
 #define DMA_MAX_BUFS 32      /* hardware table limit */
 
@@ -364,11 +365,11 @@ struct ddb_mod {
 	struct ddb_port       *port;
 	//u32                    nr;
 	//u32                    regs;
-	
+
 	u32                    frequency;
 	u32                    modulation;
 	u32                    symbolrate;
-	
+
 	u64                    obitrate;
 	u64                    ibitrate;
 	u32                    pcr_correction;