4341 lines
177 KiB
C
4341 lines
177 KiB
C
#define AUD_COMM_EXEC_STOP 0x0
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#define AUD_COMM_EXEC__A 0x1000000
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#define FEC_COMM_EXEC_ACTIVE 0x1
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#define FEC_COMM_EXEC_ACTIVE 0x1
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#define FEC_COMM_EXEC_STOP 0x0
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#define FEC_COMM_EXEC__A 0x1C00000
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#define FEC_COMM_EXEC__A 0x1C00000
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#define FEC_COMM_EXEC__A 0x1C00000
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#define FEC_DI_COMM_EXEC_STOP 0x0
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#define FEC_DI_COMM_EXEC__A 0x1C20000
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#define FEC_DI_INPUT_CTL__A 0x1C20016
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#define FEC_OC_AVR_PARM_A__A 0x1C40026
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#define FEC_OC_AVR_PARM_B__A 0x1C40027
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#define FEC_OC_COMM_MB_CTL_ON 0x1
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#define FEC_OC_COMM_MB__A 0x1C40002
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#define FEC_OC_DTO_BURST_LEN__A 0x1C40018
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#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1
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#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4
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#define FEC_OC_DTO_MODE__A 0x1C40014
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#define FEC_OC_DTO_PERIOD__A 0x1C40015
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#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1
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#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2
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#define FEC_OC_FCT_MODE__A 0x1C4001A
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#define FEC_OC_FCT_MODE__PRE 0x0
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#define FEC_OC_IPR_INVERT_MCLK__M 0x800
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#define FEC_OC_IPR_INVERT_MD0__B 0
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#define FEC_OC_IPR_INVERT_MD0__M 0x1
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#define FEC_OC_IPR_INVERT_MD0__PRE 0x0
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#define FEC_OC_IPR_INVERT_MD0__W 1
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#define FEC_OC_IPR_INVERT_MD1__B 1
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#define FEC_OC_IPR_INVERT_MD1__M 0x2
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#define FEC_OC_IPR_INVERT_MD1__PRE 0x0
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#define FEC_OC_IPR_INVERT_MD1__W 1
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#define FEC_OC_IPR_INVERT_MD2__B 2
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#define FEC_OC_IPR_INVERT_MD2__M 0x4
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#define FEC_OC_IPR_INVERT_MD2__PRE 0x0
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#define FEC_OC_IPR_INVERT_MD2__W 1
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#define FEC_OC_IPR_INVERT_MD3__B 3
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#define FEC_OC_IPR_INVERT_MD3__M 0x8
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#define FEC_OC_IPR_INVERT_MD3__PRE 0x0
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#define FEC_OC_IPR_INVERT_MD3__W 1
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#define FEC_OC_IPR_INVERT_MD4__B 4
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#define FEC_OC_IPR_INVERT_MD4__M 0x10
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#define FEC_OC_IPR_INVERT_MD4__PRE 0x0
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#define FEC_OC_IPR_INVERT_MD4__W 1
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#define FEC_OC_IPR_INVERT_MD5__B 5
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#define FEC_OC_IPR_INVERT_MD5__M 0x20
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#define FEC_OC_IPR_INVERT_MD5__PRE 0x0
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#define FEC_OC_IPR_INVERT_MD5__W 1
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#define FEC_OC_IPR_INVERT_MD6__B 6
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#define FEC_OC_IPR_INVERT_MD6__M 0x40
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#define FEC_OC_IPR_INVERT_MD6__PRE 0x0
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#define FEC_OC_IPR_INVERT_MD6__W 1
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#define FEC_OC_IPR_INVERT_MD7__B 7
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#define FEC_OC_IPR_INVERT_MD7__M 0x80
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#define FEC_OC_IPR_INVERT_MD7__PRE 0x0
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#define FEC_OC_IPR_INVERT_MD7__W 1
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#define FEC_OC_IPR_INVERT_MERR__M 0x100
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#define FEC_OC_IPR_INVERT_MSTRT__M 0x200
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#define FEC_OC_IPR_INVERT_MVAL__M 0x400
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#define FEC_OC_IPR_INVERT__A 0x1C40049
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#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4
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#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10
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#define FEC_OC_IPR_MODE_SERIAL__M 0x1
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#define FEC_OC_IPR_MODE__A 0x1C40048
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#define FEC_OC_IPR_MODE__A 0x1C40048
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#define FEC_OC_MODE_PARITY__M 0x1
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#define FEC_OC_MODE__A 0x1C40011
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#define FEC_OC_OCR_INVERT__A 0x1C40052
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#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030
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#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033
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#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032
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#define FEC_OC_RCN_GAIN__A 0x1C4002E
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#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046
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#define FEC_OC_SNC_HWM__A 0x1C40042
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#define FEC_OC_SNC_LWM__A 0x1C40041
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#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10
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#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10
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#define FEC_OC_SNC_MODE__A 0x1C40040
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#define FEC_OC_SNC_MODE__A 0x1C40040
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#define FEC_OC_SNC_UNLOCK__A 0x1C40043
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#define FEC_OC_TMD_COUNT__A 0x1C4001F
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#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020
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#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023
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#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021
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#define FEC_OC_TMD_MODE__A 0x1C4001E
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#define FEC_RS_COMM_EXEC_STOP 0x0
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#define FEC_RS_COMM_EXEC__A 0x1C30000
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#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012
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#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012
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#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013
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#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013
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#define IQM_AF_AGC_IF__A 0x1870028
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#define IQM_AF_AGC_RF__A 0x1870029
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#define IQM_AF_AMUX_SIGNAL2ADC 0x1
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#define IQM_AF_AMUX_SIGNAL2ADC 0x1
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#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0
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#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0
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#define IQM_AF_AMUX__A 0x187002D
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#define IQM_AF_AMUX__A 0x187002D
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#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2
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#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0
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#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2
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#define IQM_AF_CLKNEG__A 0x1870012
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#define IQM_AF_CLP_LEN__A 0x1870023
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#define IQM_AF_CLP_LEN__A 0x1870023
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#define IQM_AF_CLP_TH__A 0x1870024
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#define IQM_AF_CLP_TH__A 0x1870024
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#define IQM_AF_COMM_EXEC_ACTIVE 0x1
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#define IQM_AF_COMM_EXEC__A 0x1870000
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#define IQM_AF_INC_BYPASS__A 0x1870036
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#define IQM_AF_INC_LCT__A 0x1870034
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#define IQM_AF_PDREF__A 0x187002B
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#define IQM_AF_PDREF__M 0x1F
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#define IQM_AF_PHASE0__A 0x187001C
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#define IQM_AF_PHASE0__M 0x7F
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#define IQM_AF_PHASE0__PRE 0x0
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#define IQM_AF_PHASE0__W 7
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#define IQM_AF_PHASE1__A 0x187001D
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#define IQM_AF_PHASE1__M 0x7F
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#define IQM_AF_PHASE1__PRE 0x0
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#define IQM_AF_PHASE1__W 7
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#define IQM_AF_PHASE2__A 0x187001E
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#define IQM_AF_PHASE2__M 0x7F
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#define IQM_AF_PHASE2__PRE 0x0
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#define IQM_AF_PHASE2__W 7
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#define IQM_AF_SNS_LEN__A 0x1870026
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#define IQM_AF_SNS_LEN__A 0x1870026
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#define IQM_AF_START_LOCK__A 0x187001B
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#define IQM_AF_START_LOCK__A 0x187001B
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#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2
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#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4
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#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8
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#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10
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#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10
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#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20
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#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20
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#define IQM_AF_STDBY__A 0x187002C
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#define IQM_AF_STDBY__A 0x187002C
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#define IQM_AF_STDBY__A 0x187002C
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#define IQM_AF_UPD_SEL__A 0x187002F
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#define IQM_AF_UPD_SEL__A 0x187002F
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#define IQM_CF_ADJ_SEL__A 0x1860013
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#define IQM_CF_BYPASSDET__A 0x1860067
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#define IQM_CF_BYPASSDET__A 0x1860067
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#define IQM_CF_CLP_VAL__A 0x1860060
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#define IQM_CF_COMM_INT_MSK__A 0x1860006
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#define IQM_CF_DATATH__A 0x1860061
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#define IQM_CF_DATATH__A 0x1860061
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#define IQM_CF_DET_LCT__A 0x1860064
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#define IQM_CF_DET_LCT__A 0x1860064
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#define IQM_CF_DS_ENA__A 0x1860019
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#define IQM_CF_MIDTAP_IM__B 1
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#define IQM_CF_MIDTAP_RE__B 0
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#define IQM_CF_MIDTAP__A 0x1860011
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#define IQM_CF_OUT_ENA_QAM__B 1
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#define IQM_CF_OUT_ENA__A 0x1860012
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#define IQM_CF_OUT_ENA__A 0x1860012
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#define IQM_CF_PKDTH__A 0x1860062
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#define IQM_CF_PKDTH__A 0x1860062
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#define IQM_CF_POW_MEAS_LEN__A 0x1860017
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#define IQM_CF_POW_MEAS_LEN__A 0x1860017
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#define IQM_CF_SCALE_SH__A 0x1860015
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#define IQM_CF_SCALE_SH__A 0x1860015
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#define IQM_CF_SCALE_SH__PRE 0x0
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#define IQM_CF_SCALE__A 0x1860014
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#define IQM_CF_SYMMETRIC__A 0x1860010
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#define IQM_CF_TAP_IM0_B__B 0
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#define IQM_CF_TAP_IM0_B__M 0x7F
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#define IQM_CF_TAP_IM0_B__PRE 0x2
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#define IQM_CF_TAP_IM0_B__W 7
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#define IQM_CF_TAP_IM0__A 0x1860040
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#define IQM_CF_TAP_IM0__M 0x7F
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#define IQM_CF_TAP_IM0__PRE 0x2
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#define IQM_CF_TAP_IM0__W 7
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#define IQM_CF_TAP_IM10_B__B 0
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#define IQM_CF_TAP_IM10_B__M 0x1FF
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#define IQM_CF_TAP_IM10_B__PRE 0x2
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#define IQM_CF_TAP_IM10_B__W 9
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#define IQM_CF_TAP_IM10__A 0x186004A
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#define IQM_CF_TAP_IM10__M 0x1FF
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#define IQM_CF_TAP_IM10__PRE 0x2
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#define IQM_CF_TAP_IM10__W 9
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#define IQM_CF_TAP_IM11_B__B 0
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#define IQM_CF_TAP_IM11_B__M 0x1FF
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#define IQM_CF_TAP_IM11_B__PRE 0x2
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#define IQM_CF_TAP_IM11_B__W 9
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#define IQM_CF_TAP_IM11__A 0x186004B
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#define IQM_CF_TAP_IM11__M 0x1FF
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#define IQM_CF_TAP_IM11__PRE 0x2
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#define IQM_CF_TAP_IM11__W 9
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#define IQM_CF_TAP_IM12_B__B 0
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#define IQM_CF_TAP_IM12_B__M 0x1FF
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#define IQM_CF_TAP_IM12_B__PRE 0x2
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#define IQM_CF_TAP_IM12_B__W 9
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#define IQM_CF_TAP_IM12__A 0x186004C
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#define IQM_CF_TAP_IM12__M 0x1FF
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#define IQM_CF_TAP_IM12__PRE 0x2
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#define IQM_CF_TAP_IM12__W 9
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#define IQM_CF_TAP_IM13_B__B 0
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#define IQM_CF_TAP_IM13_B__M 0x1FF
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#define IQM_CF_TAP_IM13_B__PRE 0x2
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#define IQM_CF_TAP_IM13_B__W 9
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#define IQM_CF_TAP_IM13__A 0x186004D
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#define IQM_CF_TAP_IM13__M 0x1FF
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#define IQM_CF_TAP_IM13__PRE 0x2
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#define IQM_CF_TAP_IM13__W 9
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#define IQM_CF_TAP_IM14_B__B 0
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#define IQM_CF_TAP_IM14_B__M 0x1FF
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#define IQM_CF_TAP_IM14_B__PRE 0x2
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#define IQM_CF_TAP_IM14_B__W 9
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#define IQM_CF_TAP_IM14__A 0x186004E
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#define IQM_CF_TAP_IM14__M 0x1FF
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#define IQM_CF_TAP_IM14__PRE 0x2
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#define IQM_CF_TAP_IM14__W 9
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#define IQM_CF_TAP_IM15_B__B 0
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#define IQM_CF_TAP_IM15_B__M 0x1FF
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#define IQM_CF_TAP_IM15_B__PRE 0x2
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#define IQM_CF_TAP_IM15_B__W 9
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#define IQM_CF_TAP_IM15__A 0x186004F
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#define IQM_CF_TAP_IM15__M 0x1FF
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#define IQM_CF_TAP_IM15__PRE 0x2
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#define IQM_CF_TAP_IM15__W 9
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#define IQM_CF_TAP_IM16_B__B 0
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#define IQM_CF_TAP_IM16_B__M 0x1FF
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#define IQM_CF_TAP_IM16_B__PRE 0x2
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#define IQM_CF_TAP_IM16_B__W 9
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#define IQM_CF_TAP_IM16__A 0x1860050
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#define IQM_CF_TAP_IM16__M 0x1FF
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#define IQM_CF_TAP_IM16__PRE 0x2
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#define IQM_CF_TAP_IM16__W 9
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#define IQM_CF_TAP_IM17_B__B 0
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#define IQM_CF_TAP_IM17_B__M 0x1FF
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#define IQM_CF_TAP_IM17_B__PRE 0x2
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#define IQM_CF_TAP_IM17_B__W 9
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#define IQM_CF_TAP_IM17__A 0x1860051
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#define IQM_CF_TAP_IM17__M 0x1FF
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#define IQM_CF_TAP_IM17__PRE 0x2
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#define IQM_CF_TAP_IM17__W 9
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#define IQM_CF_TAP_IM18_B__B 0
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#define IQM_CF_TAP_IM18_B__M 0x1FF
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#define IQM_CF_TAP_IM18_B__PRE 0x2
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#define IQM_CF_TAP_IM18_B__W 9
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#define IQM_CF_TAP_IM18__A 0x1860052
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#define IQM_CF_TAP_IM18__M 0x1FF
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#define IQM_CF_TAP_IM18__PRE 0x2
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#define IQM_CF_TAP_IM18__W 9
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#define IQM_CF_TAP_IM19_B__B 0
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#define IQM_CF_TAP_IM19_B__M 0x1FF
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#define IQM_CF_TAP_IM19_B__PRE 0x2
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#define IQM_CF_TAP_IM19_B__W 9
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#define IQM_CF_TAP_IM19__A 0x1860053
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#define IQM_CF_TAP_IM19__M 0x1FF
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#define IQM_CF_TAP_IM19__PRE 0x2
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#define IQM_CF_TAP_IM19__W 9
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#define IQM_CF_TAP_IM1_B__B 0
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#define IQM_CF_TAP_IM1_B__M 0x7F
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#define IQM_CF_TAP_IM1_B__PRE 0x2
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#define IQM_CF_TAP_IM1_B__W 7
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#define IQM_CF_TAP_IM1__A 0x1860041
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#define IQM_CF_TAP_IM1__M 0x7F
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#define IQM_CF_TAP_IM1__PRE 0x2
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#define IQM_CF_TAP_IM1__W 7
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#define IQM_CF_TAP_IM20_B__B 0
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#define IQM_CF_TAP_IM20_B__M 0x1FF
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#define IQM_CF_TAP_IM20_B__PRE 0x2
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#define IQM_CF_TAP_IM20_B__W 9
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#define IQM_CF_TAP_IM20__A 0x1860054
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#define IQM_CF_TAP_IM20__M 0x1FF
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#define IQM_CF_TAP_IM20__PRE 0x2
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#define IQM_CF_TAP_IM20__W 9
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#define IQM_CF_TAP_IM21_B__B 0
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#define IQM_CF_TAP_IM21_B__M 0x7FF
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#define IQM_CF_TAP_IM21_B__PRE 0x2
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#define IQM_CF_TAP_IM21_B__W 11
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#define IQM_CF_TAP_IM21__A 0x1860055
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#define IQM_CF_TAP_IM21__M 0x7FF
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#define IQM_CF_TAP_IM21__PRE 0x2
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#define IQM_CF_TAP_IM21__W 11
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#define IQM_CF_TAP_IM22_B__B 0
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#define IQM_CF_TAP_IM22_B__M 0x7FF
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#define IQM_CF_TAP_IM22_B__PRE 0x2
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#define IQM_CF_TAP_IM22_B__W 11
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#define IQM_CF_TAP_IM22__A 0x1860056
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#define IQM_CF_TAP_IM22__M 0x7FF
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#define IQM_CF_TAP_IM22__PRE 0x2
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#define IQM_CF_TAP_IM22__W 11
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#define IQM_CF_TAP_IM23_B__B 0
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#define IQM_CF_TAP_IM23_B__M 0x7FF
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#define IQM_CF_TAP_IM23_B__PRE 0x2
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#define IQM_CF_TAP_IM23_B__W 11
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#define IQM_CF_TAP_IM23__A 0x1860057
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#define IQM_CF_TAP_IM23__M 0x7FF
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#define IQM_CF_TAP_IM23__PRE 0x2
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#define IQM_CF_TAP_IM23__W 11
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#define IQM_CF_TAP_IM24_B__B 0
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#define IQM_CF_TAP_IM24_B__M 0x7FF
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#define IQM_CF_TAP_IM24_B__PRE 0x2
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#define IQM_CF_TAP_IM24_B__W 11
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#define IQM_CF_TAP_IM24__A 0x1860058
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#define IQM_CF_TAP_IM24__M 0x7FF
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#define IQM_CF_TAP_IM24__PRE 0x2
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#define IQM_CF_TAP_IM24__W 11
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#define IQM_CF_TAP_IM25_B__B 0
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#define IQM_CF_TAP_IM25_B__M 0x7FF
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#define IQM_CF_TAP_IM25_B__PRE 0x2
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#define IQM_CF_TAP_IM25_B__W 11
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#define IQM_CF_TAP_IM25__A 0x1860059
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#define IQM_CF_TAP_IM25__M 0x7FF
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#define IQM_CF_TAP_IM25__PRE 0x2
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#define IQM_CF_TAP_IM25__W 11
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#define IQM_CF_TAP_IM26_B__B 0
|
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#define IQM_CF_TAP_IM26_B__M 0x7FF
|
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#define IQM_CF_TAP_IM26_B__PRE 0x2
|
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#define IQM_CF_TAP_IM26_B__W 11
|
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#define IQM_CF_TAP_IM26__A 0x186005A
|
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#define IQM_CF_TAP_IM26__M 0x7FF
|
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#define IQM_CF_TAP_IM26__PRE 0x2
|
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#define IQM_CF_TAP_IM26__W 11
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#define IQM_CF_TAP_IM27_B__B 0
|
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#define IQM_CF_TAP_IM27_B__M 0x7FF
|
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#define IQM_CF_TAP_IM27_B__PRE 0x2
|
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#define IQM_CF_TAP_IM27_B__W 11
|
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#define IQM_CF_TAP_IM27__A 0x186005B
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#define IQM_CF_TAP_IM27__M 0x7FF
|
|
#define IQM_CF_TAP_IM27__PRE 0x2
|
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#define IQM_CF_TAP_IM27__W 11
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#define IQM_CF_TAP_IM2_B__B 0
|
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#define IQM_CF_TAP_IM2_B__M 0x7F
|
|
#define IQM_CF_TAP_IM2_B__PRE 0x2
|
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#define IQM_CF_TAP_IM2_B__W 7
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#define IQM_CF_TAP_IM2__A 0x1860042
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#define IQM_CF_TAP_IM2__M 0x7F
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#define IQM_CF_TAP_IM2__PRE 0x2
|
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#define IQM_CF_TAP_IM2__W 7
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#define IQM_CF_TAP_IM3_B__B 0
|
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#define IQM_CF_TAP_IM3_B__M 0x7F
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#define IQM_CF_TAP_IM3_B__PRE 0x2
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#define IQM_CF_TAP_IM3_B__W 7
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#define IQM_CF_TAP_IM3__A 0x1860043
|
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#define IQM_CF_TAP_IM3__M 0x7F
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#define IQM_CF_TAP_IM3__PRE 0x2
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#define IQM_CF_TAP_IM3__W 7
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#define IQM_CF_TAP_IM4_B__B 0
|
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#define IQM_CF_TAP_IM4_B__M 0x7F
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#define IQM_CF_TAP_IM4_B__PRE 0x2
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|
#define IQM_CF_TAP_IM4_B__W 7
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#define IQM_CF_TAP_IM4__A 0x1860044
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#define IQM_CF_TAP_IM4__M 0x7F
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#define IQM_CF_TAP_IM4__PRE 0x2
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#define IQM_CF_TAP_IM4__W 7
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#define IQM_CF_TAP_IM5_B__B 0
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#define IQM_CF_TAP_IM5_B__M 0x7F
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#define IQM_CF_TAP_IM5_B__PRE 0x2
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#define IQM_CF_TAP_IM5_B__W 7
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#define IQM_CF_TAP_IM5__A 0x1860045
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#define IQM_CF_TAP_IM5__M 0x7F
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#define IQM_CF_TAP_IM5__PRE 0x2
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#define IQM_CF_TAP_IM5__W 7
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#define IQM_CF_TAP_IM6_B__B 0
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#define IQM_CF_TAP_IM6_B__M 0x7F
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#define IQM_CF_TAP_IM6_B__PRE 0x2
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#define IQM_CF_TAP_IM6_B__W 7
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#define IQM_CF_TAP_IM6__A 0x1860046
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#define IQM_CF_TAP_IM6__M 0x7F
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#define IQM_CF_TAP_IM6__PRE 0x2
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#define IQM_CF_TAP_IM6__W 7
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#define IQM_CF_TAP_IM7_B__B 0
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|
#define IQM_CF_TAP_IM7_B__M 0x1FF
|
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#define IQM_CF_TAP_IM7_B__PRE 0x2
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#define IQM_CF_TAP_IM7_B__W 9
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|
#define IQM_CF_TAP_IM7__A 0x1860047
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#define IQM_CF_TAP_IM7__M 0x1FF
|
|
#define IQM_CF_TAP_IM7__PRE 0x2
|
|
#define IQM_CF_TAP_IM7__W 9
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|
#define IQM_CF_TAP_IM8_B__B 0
|
|
#define IQM_CF_TAP_IM8_B__M 0x1FF
|
|
#define IQM_CF_TAP_IM8_B__PRE 0x2
|
|
#define IQM_CF_TAP_IM8_B__W 9
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|
#define IQM_CF_TAP_IM8__A 0x1860048
|
|
#define IQM_CF_TAP_IM8__M 0x1FF
|
|
#define IQM_CF_TAP_IM8__PRE 0x2
|
|
#define IQM_CF_TAP_IM8__W 9
|
|
#define IQM_CF_TAP_IM9_B__B 0
|
|
#define IQM_CF_TAP_IM9_B__M 0x1FF
|
|
#define IQM_CF_TAP_IM9_B__PRE 0x2
|
|
#define IQM_CF_TAP_IM9_B__W 9
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|
#define IQM_CF_TAP_IM9__A 0x1860049
|
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#define IQM_CF_TAP_IM9__M 0x1FF
|
|
#define IQM_CF_TAP_IM9__PRE 0x2
|
|
#define IQM_CF_TAP_IM9__W 9
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#define IQM_CF_TAP_RE0_B__B 0
|
|
#define IQM_CF_TAP_RE0_B__M 0x7F
|
|
#define IQM_CF_TAP_RE0_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE0_B__W 7
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|
#define IQM_CF_TAP_RE0__A 0x1860020
|
|
#define IQM_CF_TAP_RE0__M 0x7F
|
|
#define IQM_CF_TAP_RE0__PRE 0x2
|
|
#define IQM_CF_TAP_RE0__W 7
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|
#define IQM_CF_TAP_RE10_B__B 0
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|
#define IQM_CF_TAP_RE10_B__M 0x1FF
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|
#define IQM_CF_TAP_RE10_B__PRE 0x2
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|
#define IQM_CF_TAP_RE10_B__W 9
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|
#define IQM_CF_TAP_RE10__A 0x186002A
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#define IQM_CF_TAP_RE10__M 0x1FF
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|
#define IQM_CF_TAP_RE10__PRE 0x2
|
|
#define IQM_CF_TAP_RE10__W 9
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|
#define IQM_CF_TAP_RE11_B__B 0
|
|
#define IQM_CF_TAP_RE11_B__M 0x1FF
|
|
#define IQM_CF_TAP_RE11_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE11_B__W 9
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|
#define IQM_CF_TAP_RE11__A 0x186002B
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|
#define IQM_CF_TAP_RE11__M 0x1FF
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|
#define IQM_CF_TAP_RE11__PRE 0x2
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|
#define IQM_CF_TAP_RE11__W 9
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|
#define IQM_CF_TAP_RE12_B__B 0
|
|
#define IQM_CF_TAP_RE12_B__M 0x1FF
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|
#define IQM_CF_TAP_RE12_B__PRE 0x2
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|
#define IQM_CF_TAP_RE12_B__W 9
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|
#define IQM_CF_TAP_RE12__A 0x186002C
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|
#define IQM_CF_TAP_RE12__M 0x1FF
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|
#define IQM_CF_TAP_RE12__PRE 0x2
|
|
#define IQM_CF_TAP_RE12__W 9
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|
#define IQM_CF_TAP_RE13_B__B 0
|
|
#define IQM_CF_TAP_RE13_B__M 0x1FF
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|
#define IQM_CF_TAP_RE13_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE13_B__W 9
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|
#define IQM_CF_TAP_RE13__A 0x186002D
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|
#define IQM_CF_TAP_RE13__M 0x1FF
|
|
#define IQM_CF_TAP_RE13__PRE 0x2
|
|
#define IQM_CF_TAP_RE13__W 9
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|
#define IQM_CF_TAP_RE14_B__B 0
|
|
#define IQM_CF_TAP_RE14_B__M 0x1FF
|
|
#define IQM_CF_TAP_RE14_B__PRE 0x2
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|
#define IQM_CF_TAP_RE14_B__W 9
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|
#define IQM_CF_TAP_RE14__A 0x186002E
|
|
#define IQM_CF_TAP_RE14__M 0x1FF
|
|
#define IQM_CF_TAP_RE14__PRE 0x2
|
|
#define IQM_CF_TAP_RE14__W 9
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|
#define IQM_CF_TAP_RE15_B__B 0
|
|
#define IQM_CF_TAP_RE15_B__M 0x1FF
|
|
#define IQM_CF_TAP_RE15_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE15_B__W 9
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|
#define IQM_CF_TAP_RE15__A 0x186002F
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|
#define IQM_CF_TAP_RE15__M 0x1FF
|
|
#define IQM_CF_TAP_RE15__PRE 0x2
|
|
#define IQM_CF_TAP_RE15__W 9
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|
#define IQM_CF_TAP_RE16_B__B 0
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|
#define IQM_CF_TAP_RE16_B__M 0x1FF
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|
#define IQM_CF_TAP_RE16_B__PRE 0x2
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|
#define IQM_CF_TAP_RE16_B__W 9
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|
#define IQM_CF_TAP_RE16__A 0x1860030
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|
#define IQM_CF_TAP_RE16__M 0x1FF
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|
#define IQM_CF_TAP_RE16__PRE 0x2
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|
#define IQM_CF_TAP_RE16__W 9
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|
#define IQM_CF_TAP_RE17_B__B 0
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|
#define IQM_CF_TAP_RE17_B__M 0x1FF
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|
#define IQM_CF_TAP_RE17_B__PRE 0x2
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|
#define IQM_CF_TAP_RE17_B__W 9
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|
#define IQM_CF_TAP_RE17__A 0x1860031
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|
#define IQM_CF_TAP_RE17__M 0x1FF
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|
#define IQM_CF_TAP_RE17__PRE 0x2
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|
#define IQM_CF_TAP_RE17__W 9
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|
#define IQM_CF_TAP_RE18_B__B 0
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#define IQM_CF_TAP_RE18_B__M 0x1FF
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|
#define IQM_CF_TAP_RE18_B__PRE 0x2
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|
#define IQM_CF_TAP_RE18_B__W 9
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|
#define IQM_CF_TAP_RE18__A 0x1860032
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|
#define IQM_CF_TAP_RE18__M 0x1FF
|
|
#define IQM_CF_TAP_RE18__PRE 0x2
|
|
#define IQM_CF_TAP_RE18__W 9
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|
#define IQM_CF_TAP_RE19_B__B 0
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|
#define IQM_CF_TAP_RE19_B__M 0x1FF
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|
#define IQM_CF_TAP_RE19_B__PRE 0x2
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|
#define IQM_CF_TAP_RE19_B__W 9
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|
#define IQM_CF_TAP_RE19__A 0x1860033
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|
#define IQM_CF_TAP_RE19__M 0x1FF
|
|
#define IQM_CF_TAP_RE19__PRE 0x2
|
|
#define IQM_CF_TAP_RE19__W 9
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|
#define IQM_CF_TAP_RE1_B__B 0
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|
#define IQM_CF_TAP_RE1_B__M 0x7F
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|
#define IQM_CF_TAP_RE1_B__PRE 0x2
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|
#define IQM_CF_TAP_RE1_B__W 7
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|
#define IQM_CF_TAP_RE1__A 0x1860021
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|
#define IQM_CF_TAP_RE1__M 0x7F
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|
#define IQM_CF_TAP_RE1__PRE 0x2
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|
#define IQM_CF_TAP_RE1__W 7
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|
#define IQM_CF_TAP_RE20_B__B 0
|
|
#define IQM_CF_TAP_RE20_B__M 0x1FF
|
|
#define IQM_CF_TAP_RE20_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE20_B__W 9
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|
#define IQM_CF_TAP_RE20__A 0x1860034
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|
#define IQM_CF_TAP_RE20__M 0x1FF
|
|
#define IQM_CF_TAP_RE20__PRE 0x2
|
|
#define IQM_CF_TAP_RE20__W 9
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|
#define IQM_CF_TAP_RE21_B__B 0
|
|
#define IQM_CF_TAP_RE21_B__M 0x7FF
|
|
#define IQM_CF_TAP_RE21_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE21_B__W 11
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|
#define IQM_CF_TAP_RE21__A 0x1860035
|
|
#define IQM_CF_TAP_RE21__M 0x7FF
|
|
#define IQM_CF_TAP_RE21__PRE 0x2
|
|
#define IQM_CF_TAP_RE21__W 11
|
|
#define IQM_CF_TAP_RE22_B__B 0
|
|
#define IQM_CF_TAP_RE22_B__M 0x7FF
|
|
#define IQM_CF_TAP_RE22_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE22_B__W 11
|
|
#define IQM_CF_TAP_RE22__A 0x1860036
|
|
#define IQM_CF_TAP_RE22__M 0x7FF
|
|
#define IQM_CF_TAP_RE22__PRE 0x2
|
|
#define IQM_CF_TAP_RE22__W 11
|
|
#define IQM_CF_TAP_RE23_B__B 0
|
|
#define IQM_CF_TAP_RE23_B__M 0x7FF
|
|
#define IQM_CF_TAP_RE23_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE23_B__W 11
|
|
#define IQM_CF_TAP_RE23__A 0x1860037
|
|
#define IQM_CF_TAP_RE23__M 0x7FF
|
|
#define IQM_CF_TAP_RE23__PRE 0x2
|
|
#define IQM_CF_TAP_RE23__W 11
|
|
#define IQM_CF_TAP_RE24_B__B 0
|
|
#define IQM_CF_TAP_RE24_B__M 0x7FF
|
|
#define IQM_CF_TAP_RE24_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE24_B__W 11
|
|
#define IQM_CF_TAP_RE24__A 0x1860038
|
|
#define IQM_CF_TAP_RE24__M 0x7FF
|
|
#define IQM_CF_TAP_RE24__PRE 0x2
|
|
#define IQM_CF_TAP_RE24__W 11
|
|
#define IQM_CF_TAP_RE25_B__B 0
|
|
#define IQM_CF_TAP_RE25_B__M 0x7FF
|
|
#define IQM_CF_TAP_RE25_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE25_B__W 11
|
|
#define IQM_CF_TAP_RE25__A 0x1860039
|
|
#define IQM_CF_TAP_RE25__M 0x7FF
|
|
#define IQM_CF_TAP_RE25__PRE 0x2
|
|
#define IQM_CF_TAP_RE25__W 11
|
|
#define IQM_CF_TAP_RE26_B__B 0
|
|
#define IQM_CF_TAP_RE26_B__M 0x7FF
|
|
#define IQM_CF_TAP_RE26_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE26_B__W 11
|
|
#define IQM_CF_TAP_RE26__A 0x186003A
|
|
#define IQM_CF_TAP_RE26__M 0x7FF
|
|
#define IQM_CF_TAP_RE26__PRE 0x2
|
|
#define IQM_CF_TAP_RE26__W 11
|
|
#define IQM_CF_TAP_RE27_B__B 0
|
|
#define IQM_CF_TAP_RE27_B__M 0x7FF
|
|
#define IQM_CF_TAP_RE27_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE27_B__W 11
|
|
#define IQM_CF_TAP_RE27__A 0x186003B
|
|
#define IQM_CF_TAP_RE27__M 0x7FF
|
|
#define IQM_CF_TAP_RE27__PRE 0x2
|
|
#define IQM_CF_TAP_RE27__W 11
|
|
#define IQM_CF_TAP_RE2_B__B 0
|
|
#define IQM_CF_TAP_RE2_B__M 0x7F
|
|
#define IQM_CF_TAP_RE2_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE2_B__W 7
|
|
#define IQM_CF_TAP_RE2__A 0x1860022
|
|
#define IQM_CF_TAP_RE2__M 0x7F
|
|
#define IQM_CF_TAP_RE2__PRE 0x2
|
|
#define IQM_CF_TAP_RE2__W 7
|
|
#define IQM_CF_TAP_RE3_B__B 0
|
|
#define IQM_CF_TAP_RE3_B__M 0x7F
|
|
#define IQM_CF_TAP_RE3_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE3_B__W 7
|
|
#define IQM_CF_TAP_RE3__A 0x1860023
|
|
#define IQM_CF_TAP_RE3__M 0x7F
|
|
#define IQM_CF_TAP_RE3__PRE 0x2
|
|
#define IQM_CF_TAP_RE3__W 7
|
|
#define IQM_CF_TAP_RE4_B__B 0
|
|
#define IQM_CF_TAP_RE4_B__M 0x7F
|
|
#define IQM_CF_TAP_RE4_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE4_B__W 7
|
|
#define IQM_CF_TAP_RE4__A 0x1860024
|
|
#define IQM_CF_TAP_RE4__M 0x7F
|
|
#define IQM_CF_TAP_RE4__PRE 0x2
|
|
#define IQM_CF_TAP_RE4__W 7
|
|
#define IQM_CF_TAP_RE5_B__B 0
|
|
#define IQM_CF_TAP_RE5_B__M 0x7F
|
|
#define IQM_CF_TAP_RE5_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE5_B__W 7
|
|
#define IQM_CF_TAP_RE5__A 0x1860025
|
|
#define IQM_CF_TAP_RE5__M 0x7F
|
|
#define IQM_CF_TAP_RE5__PRE 0x2
|
|
#define IQM_CF_TAP_RE5__W 7
|
|
#define IQM_CF_TAP_RE6_B__B 0
|
|
#define IQM_CF_TAP_RE6_B__M 0x7F
|
|
#define IQM_CF_TAP_RE6_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE6_B__W 7
|
|
#define IQM_CF_TAP_RE6__A 0x1860026
|
|
#define IQM_CF_TAP_RE6__M 0x7F
|
|
#define IQM_CF_TAP_RE6__PRE 0x2
|
|
#define IQM_CF_TAP_RE6__W 7
|
|
#define IQM_CF_TAP_RE7_B__B 0
|
|
#define IQM_CF_TAP_RE7_B__M 0x1FF
|
|
#define IQM_CF_TAP_RE7_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE7_B__W 9
|
|
#define IQM_CF_TAP_RE7__A 0x1860027
|
|
#define IQM_CF_TAP_RE7__M 0x1FF
|
|
#define IQM_CF_TAP_RE7__PRE 0x2
|
|
#define IQM_CF_TAP_RE7__W 9
|
|
#define IQM_CF_TAP_RE8_B__B 0
|
|
#define IQM_CF_TAP_RE8_B__M 0x1FF
|
|
#define IQM_CF_TAP_RE8_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE8_B__W 9
|
|
#define IQM_CF_TAP_RE8__A 0x1860028
|
|
#define IQM_CF_TAP_RE8__M 0x1FF
|
|
#define IQM_CF_TAP_RE8__PRE 0x2
|
|
#define IQM_CF_TAP_RE8__W 9
|
|
#define IQM_CF_TAP_RE9_B__B 0
|
|
#define IQM_CF_TAP_RE9_B__M 0x1FF
|
|
#define IQM_CF_TAP_RE9_B__PRE 0x2
|
|
#define IQM_CF_TAP_RE9_B__W 9
|
|
#define IQM_CF_TAP_RE9__A 0x1860029
|
|
#define IQM_CF_TAP_RE9__M 0x1FF
|
|
#define IQM_CF_TAP_RE9__PRE 0x2
|
|
#define IQM_CF_TAP_RE9__W 9
|
|
#define IQM_CF_WND_LEN__A 0x1860063
|
|
#define IQM_CF_WND_LEN__A 0x1860063
|
|
#define IQM_COMM_EXEC_B_ACTIVE 0x1
|
|
#define IQM_COMM_EXEC_B_ACTIVE 0x1
|
|
#define IQM_COMM_EXEC_B_STOP 0x0
|
|
#define IQM_COMM_EXEC_B_STOP 0x0
|
|
#define IQM_COMM_EXEC_B_STOP 0x0
|
|
#define IQM_COMM_EXEC__A 0x1800000
|
|
#define IQM_COMM_EXEC__A 0x1800000
|
|
#define IQM_COMM_EXEC__A 0x1800000
|
|
#define IQM_COMM_EXEC__A 0x1800000
|
|
#define IQM_FD_RATESEL__A 0x1830010
|
|
#define IQM_FS_ADJ_SEL__A 0x1820014
|
|
#define IQM_FS_RATE_LO__A 0x1820012
|
|
#define IQM_FS_RATE_OFS_LO__A 0x1820010
|
|
#define IQM_RC_ADJ_SEL__A 0x1840014
|
|
#define IQM_RC_RATE_OFS_HI__M 0xFF
|
|
#define IQM_RC_RATE_OFS_LO__A 0x1840010
|
|
#define IQM_RC_RATE_OFS_LO__A 0x1840010
|
|
#define IQM_RC_RATE_OFS_LO__M 0xFFFF
|
|
#define IQM_RC_RATE_OFS_LO__W 16
|
|
#define IQM_RC_STRETCH__A 0x1840016
|
|
#define IQM_RC_STRETCH__A 0x1840016
|
|
#define OFDM_CP_COMM_EXEC_STOP 0x0
|
|
#define OFDM_CP_COMM_EXEC__A 0x2800000
|
|
#define OFDM_EC_SB_PRIOR_HI 0x0
|
|
#define OFDM_EC_SB_PRIOR__A 0x3410013
|
|
#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061
|
|
#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060
|
|
#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E
|
|
#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0
|
|
#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3
|
|
#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1
|
|
#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2
|
|
#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0
|
|
#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054
|
|
#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054
|
|
#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3
|
|
#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3
|
|
#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0
|
|
#define OFDM_EQ_TOP_TD_TPS_CONST__W 2
|
|
#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062
|
|
#define OFDM_LC_COMM_EXEC_STOP 0x0
|
|
#define OFDM_LC_COMM_EXEC_STOP 0x0
|
|
#define OFDM_LC_COMM_EXEC_STOP 0x0
|
|
#define OFDM_LC_COMM_EXEC__A 0x3800000
|
|
#define OFDM_LC_COMM_EXEC__A 0x3800000
|
|
#define OFDM_LC_COMM_EXEC__A 0x3800000
|
|
#define OFDM_SC_COMM_EXEC_STOP 0x0
|
|
#define OFDM_SC_COMM_EXEC_STOP 0x0
|
|
#define OFDM_SC_COMM_EXEC_STOP 0x0
|
|
#define OFDM_SC_COMM_EXEC_STOP 0x0
|
|
#define OFDM_SC_COMM_EXEC__A 0x3C00000
|
|
#define OFDM_SC_COMM_EXEC__A 0x3C00000
|
|
#define OFDM_SC_COMM_EXEC__A 0x3C00000
|
|
#define OFDM_SC_COMM_EXEC__A 0x3C00000
|
|
#define OFDM_SC_COMM_EXEC__A 0x3C00000
|
|
#define OFDM_SC_COMM_STATE__A 0x3C00001
|
|
#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042
|
|
#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5
|
|
#define OFDM_SC_RA_RAM_CMD_NULL 0x0
|
|
#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1
|
|
#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1
|
|
#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4
|
|
#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8
|
|
#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
|
|
#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
|
|
#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7
|
|
#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6
|
|
#define OFDM_SC_RA_RAM_CMD__A 0x3C20043
|
|
#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800
|
|
#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419
|
|
#define OFDM_SC_RA_RAM_ECHO_THRES__W 16
|
|
#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C
|
|
#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6
|
|
#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16
|
|
#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D
|
|
#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C
|
|
#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16
|
|
#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1
|
|
#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1
|
|
#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2
|
|
#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4
|
|
#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8
|
|
#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8
|
|
#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0
|
|
#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16
|
|
#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4
|
|
#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2
|
|
#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8
|
|
#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1
|
|
#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0
|
|
#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3
|
|
#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048
|
|
#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040
|
|
#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040
|
|
#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0
|
|
#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0
|
|
#define OFDM_SC_RA_RAM_PARAM0__W 16
|
|
#define OFDM_SC_RA_RAM_PARAM0__W 16
|
|
#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041
|
|
#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041
|
|
#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0
|
|
#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0
|
|
#define OFDM_SC_RA_RAM_PARAM1__W 16
|
|
#define OFDM_SC_RA_RAM_PARAM1__W 16
|
|
#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0
|
|
#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F
|
|
#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16
|
|
#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8
|
|
#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF
|
|
#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F
|
|
#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16
|
|
#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
|
|
#define QAM_COMM_EXEC_ACTIVE 0x1
|
|
#define QAM_COMM_EXEC_STOP 0x0
|
|
#define QAM_COMM_EXEC_STOP 0x0
|
|
#define QAM_COMM_EXEC__A 0x1400000
|
|
#define QAM_COMM_EXEC__A 0x1400000
|
|
#define QAM_COMM_EXEC__A 0x1400000
|
|
#define QAM_DQ_QUAL_FUN0_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN0_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN0_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN0_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN0_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN0_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN0_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN0_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN0_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN0_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN0__A 0x1440018
|
|
#define QAM_DQ_QUAL_FUN0__A 0x1440018
|
|
#define QAM_DQ_QUAL_FUN0__A 0x1440018
|
|
#define QAM_DQ_QUAL_FUN0__A 0x1440018
|
|
#define QAM_DQ_QUAL_FUN0__A 0x1440018
|
|
#define QAM_DQ_QUAL_FUN0__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN0__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN0__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN0__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN0__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN0__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN0__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN0__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN0__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN0__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN0__W 6
|
|
#define QAM_DQ_QUAL_FUN0__W 6
|
|
#define QAM_DQ_QUAL_FUN0__W 6
|
|
#define QAM_DQ_QUAL_FUN0__W 6
|
|
#define QAM_DQ_QUAL_FUN0__W 6
|
|
#define QAM_DQ_QUAL_FUN1_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN1_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN1_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN1_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN1_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN1_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN1_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN1_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN1_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN1_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN1__A 0x1440019
|
|
#define QAM_DQ_QUAL_FUN1__A 0x1440019
|
|
#define QAM_DQ_QUAL_FUN1__A 0x1440019
|
|
#define QAM_DQ_QUAL_FUN1__A 0x1440019
|
|
#define QAM_DQ_QUAL_FUN1__A 0x1440019
|
|
#define QAM_DQ_QUAL_FUN1__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN1__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN1__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN1__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN1__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN1__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN1__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN1__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN1__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN1__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN1__W 6
|
|
#define QAM_DQ_QUAL_FUN1__W 6
|
|
#define QAM_DQ_QUAL_FUN1__W 6
|
|
#define QAM_DQ_QUAL_FUN1__W 6
|
|
#define QAM_DQ_QUAL_FUN1__W 6
|
|
#define QAM_DQ_QUAL_FUN2_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN2_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN2_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN2_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN2_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN2_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN2_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN2_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN2_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN2_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN2__A 0x144001A
|
|
#define QAM_DQ_QUAL_FUN2__A 0x144001A
|
|
#define QAM_DQ_QUAL_FUN2__A 0x144001A
|
|
#define QAM_DQ_QUAL_FUN2__A 0x144001A
|
|
#define QAM_DQ_QUAL_FUN2__A 0x144001A
|
|
#define QAM_DQ_QUAL_FUN2__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN2__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN2__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN2__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN2__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN2__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN2__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN2__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN2__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN2__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN2__W 6
|
|
#define QAM_DQ_QUAL_FUN2__W 6
|
|
#define QAM_DQ_QUAL_FUN2__W 6
|
|
#define QAM_DQ_QUAL_FUN2__W 6
|
|
#define QAM_DQ_QUAL_FUN2__W 6
|
|
#define QAM_DQ_QUAL_FUN3_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN3_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN3_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN3_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN3_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN3_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN3_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN3_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN3_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN3_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN3__A 0x144001B
|
|
#define QAM_DQ_QUAL_FUN3__A 0x144001B
|
|
#define QAM_DQ_QUAL_FUN3__A 0x144001B
|
|
#define QAM_DQ_QUAL_FUN3__A 0x144001B
|
|
#define QAM_DQ_QUAL_FUN3__A 0x144001B
|
|
#define QAM_DQ_QUAL_FUN3__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN3__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN3__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN3__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN3__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN3__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN3__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN3__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN3__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN3__PRE 0x4
|
|
#define QAM_DQ_QUAL_FUN3__W 6
|
|
#define QAM_DQ_QUAL_FUN3__W 6
|
|
#define QAM_DQ_QUAL_FUN3__W 6
|
|
#define QAM_DQ_QUAL_FUN3__W 6
|
|
#define QAM_DQ_QUAL_FUN3__W 6
|
|
#define QAM_DQ_QUAL_FUN4_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN4_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN4_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN4_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN4_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN4_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN4_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN4_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN4_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN4_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN4__A 0x144001C
|
|
#define QAM_DQ_QUAL_FUN4__A 0x144001C
|
|
#define QAM_DQ_QUAL_FUN4__A 0x144001C
|
|
#define QAM_DQ_QUAL_FUN4__A 0x144001C
|
|
#define QAM_DQ_QUAL_FUN4__A 0x144001C
|
|
#define QAM_DQ_QUAL_FUN4__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN4__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN4__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN4__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN4__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN4__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN4__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN4__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN4__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN4__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN4__W 6
|
|
#define QAM_DQ_QUAL_FUN4__W 6
|
|
#define QAM_DQ_QUAL_FUN4__W 6
|
|
#define QAM_DQ_QUAL_FUN4__W 6
|
|
#define QAM_DQ_QUAL_FUN4__W 6
|
|
#define QAM_DQ_QUAL_FUN5_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN5_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN5_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN5_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN5_BIT__B 0
|
|
#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN5_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN5_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN5_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN5_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN5_BIT__W 6
|
|
#define QAM_DQ_QUAL_FUN5__A 0x144001D
|
|
#define QAM_DQ_QUAL_FUN5__A 0x144001D
|
|
#define QAM_DQ_QUAL_FUN5__A 0x144001D
|
|
#define QAM_DQ_QUAL_FUN5__A 0x144001D
|
|
#define QAM_DQ_QUAL_FUN5__A 0x144001D
|
|
#define QAM_DQ_QUAL_FUN5__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN5__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN5__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN5__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN5__M 0x3F
|
|
#define QAM_DQ_QUAL_FUN5__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN5__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN5__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN5__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN5__PRE 0x6
|
|
#define QAM_DQ_QUAL_FUN5__W 6
|
|
#define QAM_DQ_QUAL_FUN5__W 6
|
|
#define QAM_DQ_QUAL_FUN5__W 6
|
|
#define QAM_DQ_QUAL_FUN5__W 6
|
|
#define QAM_DQ_QUAL_FUN5__W 6
|
|
#define QAM_LC_LPF_FACTORI__A 0x1450029
|
|
#define QAM_LC_LPF_FACTORP__A 0x1450028
|
|
#define QAM_LC_MODE__A 0x1450010
|
|
#define QAM_LC_QUAL_TAB0_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0
|
|
#define QAM_LC_QUAL_TAB0_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB0__A 0x1450018
|
|
#define QAM_LC_QUAL_TAB0__M 0x1F
|
|
#define QAM_LC_QUAL_TAB0__PRE 0x0
|
|
#define QAM_LC_QUAL_TAB0__W 5
|
|
#define QAM_LC_QUAL_TAB10_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA
|
|
#define QAM_LC_QUAL_TAB10_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB10__A 0x1450021
|
|
#define QAM_LC_QUAL_TAB10__M 0x1F
|
|
#define QAM_LC_QUAL_TAB10__PRE 0xA
|
|
#define QAM_LC_QUAL_TAB10__W 5
|
|
#define QAM_LC_QUAL_TAB12_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC
|
|
#define QAM_LC_QUAL_TAB12_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB12__A 0x1450022
|
|
#define QAM_LC_QUAL_TAB12__M 0x1F
|
|
#define QAM_LC_QUAL_TAB12__PRE 0xC
|
|
#define QAM_LC_QUAL_TAB12__W 5
|
|
#define QAM_LC_QUAL_TAB15_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF
|
|
#define QAM_LC_QUAL_TAB15_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB15__A 0x1450023
|
|
#define QAM_LC_QUAL_TAB15__M 0x1F
|
|
#define QAM_LC_QUAL_TAB15__PRE 0xF
|
|
#define QAM_LC_QUAL_TAB15__W 5
|
|
#define QAM_LC_QUAL_TAB16_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10
|
|
#define QAM_LC_QUAL_TAB16_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB16__A 0x1450024
|
|
#define QAM_LC_QUAL_TAB16__M 0x1F
|
|
#define QAM_LC_QUAL_TAB16__PRE 0x10
|
|
#define QAM_LC_QUAL_TAB16__W 5
|
|
#define QAM_LC_QUAL_TAB1_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1
|
|
#define QAM_LC_QUAL_TAB1_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB1__A 0x1450019
|
|
#define QAM_LC_QUAL_TAB1__M 0x1F
|
|
#define QAM_LC_QUAL_TAB1__PRE 0x1
|
|
#define QAM_LC_QUAL_TAB1__W 5
|
|
#define QAM_LC_QUAL_TAB20_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14
|
|
#define QAM_LC_QUAL_TAB20_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB20__A 0x1450025
|
|
#define QAM_LC_QUAL_TAB20__M 0x1F
|
|
#define QAM_LC_QUAL_TAB20__PRE 0x14
|
|
#define QAM_LC_QUAL_TAB20__W 5
|
|
#define QAM_LC_QUAL_TAB25_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19
|
|
#define QAM_LC_QUAL_TAB25_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB25__A 0x1450026
|
|
#define QAM_LC_QUAL_TAB25__M 0x1F
|
|
#define QAM_LC_QUAL_TAB25__PRE 0x19
|
|
#define QAM_LC_QUAL_TAB25__W 5
|
|
#define QAM_LC_QUAL_TAB2_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2
|
|
#define QAM_LC_QUAL_TAB2_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB2__A 0x145001A
|
|
#define QAM_LC_QUAL_TAB2__M 0x1F
|
|
#define QAM_LC_QUAL_TAB2__PRE 0x2
|
|
#define QAM_LC_QUAL_TAB2__W 5
|
|
#define QAM_LC_QUAL_TAB3_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3
|
|
#define QAM_LC_QUAL_TAB3_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB3__A 0x145001B
|
|
#define QAM_LC_QUAL_TAB3__M 0x1F
|
|
#define QAM_LC_QUAL_TAB3__PRE 0x3
|
|
#define QAM_LC_QUAL_TAB3__W 5
|
|
#define QAM_LC_QUAL_TAB4_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4
|
|
#define QAM_LC_QUAL_TAB4_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB4__A 0x145001C
|
|
#define QAM_LC_QUAL_TAB4__M 0x1F
|
|
#define QAM_LC_QUAL_TAB4__PRE 0x4
|
|
#define QAM_LC_QUAL_TAB4__W 5
|
|
#define QAM_LC_QUAL_TAB5_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5
|
|
#define QAM_LC_QUAL_TAB5_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB5__A 0x145001D
|
|
#define QAM_LC_QUAL_TAB5__M 0x1F
|
|
#define QAM_LC_QUAL_TAB5__PRE 0x5
|
|
#define QAM_LC_QUAL_TAB5__W 5
|
|
#define QAM_LC_QUAL_TAB6_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6
|
|
#define QAM_LC_QUAL_TAB6_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB6__A 0x145001E
|
|
#define QAM_LC_QUAL_TAB6__M 0x1F
|
|
#define QAM_LC_QUAL_TAB6__PRE 0x6
|
|
#define QAM_LC_QUAL_TAB6__W 5
|
|
#define QAM_LC_QUAL_TAB8_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8
|
|
#define QAM_LC_QUAL_TAB8_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB8__A 0x145001F
|
|
#define QAM_LC_QUAL_TAB8__M 0x1F
|
|
#define QAM_LC_QUAL_TAB8__PRE 0x8
|
|
#define QAM_LC_QUAL_TAB8__W 5
|
|
#define QAM_LC_QUAL_TAB9_VALUE__B 0
|
|
#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F
|
|
#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9
|
|
#define QAM_LC_QUAL_TAB9_VALUE__W 5
|
|
#define QAM_LC_QUAL_TAB9__A 0x1450020
|
|
#define QAM_LC_QUAL_TAB9__M 0x1F
|
|
#define QAM_LC_QUAL_TAB9__PRE 0x9
|
|
#define QAM_LC_QUAL_TAB9__W 5
|
|
#define QAM_LC_RATE_LIMIT__A 0x145002A
|
|
#define QAM_LC_SYMBOL_FREQ__A 0x145002B
|
|
#define QAM_SL_ERR_POWER__A 0x1430017
|
|
#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0
|
|
#define QAM_SY_SP_INV__A 0x1470017
|
|
#define QAM_SY_SYNC_AWM__A 0x1470013
|
|
#define QAM_SY_SYNC_AWM__A 0x1470013
|
|
#define QAM_SY_SYNC_AWM__A 0x1470013
|
|
#define QAM_SY_SYNC_AWM__A 0x1470013
|
|
#define QAM_SY_SYNC_AWM__A 0x1470013
|
|
#define QAM_SY_SYNC_HWM__A 0x1470014
|
|
#define QAM_SY_SYNC_HWM__A 0x1470014
|
|
#define QAM_SY_SYNC_HWM__A 0x1470014
|
|
#define QAM_SY_SYNC_HWM__A 0x1470014
|
|
#define QAM_SY_SYNC_HWM__A 0x1470014
|
|
#define QAM_SY_SYNC_LWM__A 0x1470012
|
|
#define QAM_SY_SYNC_LWM__A 0x1470012
|
|
#define QAM_SY_SYNC_LWM__A 0x1470012
|
|
#define QAM_SY_SYNC_LWM__A 0x1470012
|
|
#define QAM_SY_SYNC_LWM__A 0x1470012
|
|
#define QAM_SY_TIMEOUT__A 0x1470011
|
|
#define QAM_SY_TIMEOUT__PRE 0x3A98
|
|
#define QAM_TOP_ANNEX_A 0x0
|
|
#define QAM_TOP_ANNEX_C 0x2
|
|
#define SCU_COMM_EXEC_ACTIVE 0x1
|
|
#define SCU_COMM_EXEC_ACTIVE 0x1
|
|
#define SCU_COMM_EXEC_ACTIVE 0x1
|
|
#define SCU_COMM_EXEC_ACTIVE 0x1
|
|
#define SCU_COMM_EXEC_ACTIVE 0x1
|
|
#define SCU_COMM_EXEC_ACTIVE 0x1
|
|
#define SCU_COMM_EXEC_ACTIVE 0x1
|
|
#define SCU_COMM_EXEC_HOLD 0x2
|
|
#define SCU_COMM_EXEC_HOLD 0x2
|
|
#define SCU_COMM_EXEC_HOLD 0x2
|
|
#define SCU_COMM_EXEC_HOLD 0x2
|
|
#define SCU_COMM_EXEC_STOP 0x0
|
|
#define SCU_COMM_EXEC__A 0x800000
|
|
#define SCU_COMM_EXEC__A 0x800000
|
|
#define SCU_COMM_EXEC__A 0x800000
|
|
#define SCU_COMM_EXEC__A 0x800000
|
|
#define SCU_COMM_EXEC__A 0x800000
|
|
#define SCU_COMM_EXEC__A 0x800000
|
|
#define SCU_COMM_EXEC__A 0x800000
|
|
#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8
|
|
#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31
|
|
#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30
|
|
#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34
|
|
#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32
|
|
#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33
|
|
#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F
|
|
#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E
|
|
#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D
|
|
#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2
|
|
#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1
|
|
#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100
|
|
#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200
|
|
#define SCU_RAM_AGC_CONFIG__A 0x831F24
|
|
#define SCU_RAM_AGC_CONFIG__A 0x831F24
|
|
#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA
|
|
#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA
|
|
#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15
|
|
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44
|
|
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44
|
|
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44
|
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#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43
|
|
#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42
|
|
#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40
|
|
#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41
|
|
#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F
|
|
#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F
|
|
#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E
|
|
#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E
|
|
#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D
|
|
#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17
|
|
#define SCU_RAM_AGC_KI_IF__B 8
|
|
#define SCU_RAM_AGC_KI_IF__M 0xF00
|
|
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27
|
|
#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29
|
|
#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A
|
|
#define SCU_RAM_AGC_KI_MAX__A 0x831F2C
|
|
#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28
|
|
#define SCU_RAM_AGC_KI_MIN__A 0x831F2B
|
|
#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4
|
|
#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30
|
|
#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2
|
|
#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC
|
|
#define SCU_RAM_AGC_KI_RED__A 0x831F26
|
|
#define SCU_RAM_AGC_KI_RED__A 0x831F26
|
|
#define SCU_RAM_AGC_KI_RF__B 4
|
|
#define SCU_RAM_AGC_KI_RF__M 0xF0
|
|
#define SCU_RAM_AGC_KI__A 0x831F25
|
|
#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47
|
|
#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45
|
|
#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45
|
|
#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46
|
|
#define SCU_RAM_AGC_RF_MAX__A 0x831F1B
|
|
#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19
|
|
#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A
|
|
#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38
|
|
#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18
|
|
#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B
|
|
#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39
|
|
#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A
|
|
#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37
|
|
#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36
|
|
#define SCU_RAM_AGC_SNS_SUM__A 0x831F35
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9
|
|
#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9
|
|
#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400
|
|
#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400
|
|
#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400
|
|
#define SCU_RAM_COMMAND_STANDARD_QAM 0x200
|
|
#define SCU_RAM_COMMAND_STANDARD_QAM 0x200
|
|
#define SCU_RAM_COMMAND_STANDARD_QAM 0x200
|
|
#define SCU_RAM_COMMAND_STANDARD_QAM 0x200
|
|
#define SCU_RAM_COMMAND__A 0x831FFD
|
|
#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF
|
|
#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB
|
|
#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC
|
|
#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB
|
|
#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05
|
|
#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
|
|
#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
|
|
#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
|
|
#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
|
|
#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
|
|
#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
|
|
#define SCU_RAM_GPIO__A 0x831EC7
|
|
#define SCU_RAM_GPIO__A 0x831EC7
|
|
#define SCU_RAM_GPIO__A 0x831EC7
|
|
#define SCU_RAM_GPIO__A 0x831EC7
|
|
#define SCU_RAM_GPIO__A 0x831EC7
|
|
#define SCU_RAM_GPIO__A 0x831EC7
|
|
#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103
|
|
#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4
|
|
#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40
|
|
#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3
|
|
#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA
|
|
#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109
|
|
#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9
|
|
#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2
|
|
#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0
|
|
#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1
|
|
#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2
|
|
#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3
|
|
#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD
|
|
#define SCU_RAM_PARAM_0_RESULT_OK 0x0
|
|
#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC
|
|
#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF
|
|
#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE
|
|
#define SCU_RAM_PARAM_0__A 0x831FFC
|
|
#define SCU_RAM_PARAM_0__M 0xFFFF
|
|
#define SCU_RAM_PARAM_0__PRE 0x0
|
|
#define SCU_RAM_PARAM_0__W 16
|
|
#define SCU_RAM_PARAM_10__A 0x831FF2
|
|
#define SCU_RAM_PARAM_10__M 0xFFFF
|
|
#define SCU_RAM_PARAM_10__PRE 0x0
|
|
#define SCU_RAM_PARAM_10__W 16
|
|
#define SCU_RAM_PARAM_11__A 0x831FF1
|
|
#define SCU_RAM_PARAM_11__M 0xFFFF
|
|
#define SCU_RAM_PARAM_11__PRE 0x0
|
|
#define SCU_RAM_PARAM_11__W 16
|
|
#define SCU_RAM_PARAM_12__A 0x831FF0
|
|
#define SCU_RAM_PARAM_12__M 0xFFFF
|
|
#define SCU_RAM_PARAM_12__PRE 0x0
|
|
#define SCU_RAM_PARAM_12__W 16
|
|
#define SCU_RAM_PARAM_13__A 0x831FEF
|
|
#define SCU_RAM_PARAM_13__M 0xFFFF
|
|
#define SCU_RAM_PARAM_13__PRE 0x0
|
|
#define SCU_RAM_PARAM_13__W 16
|
|
#define SCU_RAM_PARAM_14__A 0x831FEE
|
|
#define SCU_RAM_PARAM_14__M 0xFFFF
|
|
#define SCU_RAM_PARAM_14__PRE 0x0
|
|
#define SCU_RAM_PARAM_14__W 16
|
|
#define SCU_RAM_PARAM_15__A 0x831FED
|
|
#define SCU_RAM_PARAM_15__M 0xFFFF
|
|
#define SCU_RAM_PARAM_15__PRE 0x0
|
|
#define SCU_RAM_PARAM_15__W 16
|
|
#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000
|
|
#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000
|
|
#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000
|
|
#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0
|
|
#define SCU_RAM_PARAM_1__A 0x831FFB
|
|
#define SCU_RAM_PARAM_1__M 0xFFFF
|
|
#define SCU_RAM_PARAM_1__PRE 0x0
|
|
#define SCU_RAM_PARAM_1__W 16
|
|
#define SCU_RAM_PARAM_2__A 0x831FFA
|
|
#define SCU_RAM_PARAM_2__M 0xFFFF
|
|
#define SCU_RAM_PARAM_2__PRE 0x0
|
|
#define SCU_RAM_PARAM_2__W 16
|
|
#define SCU_RAM_PARAM_3__A 0x831FF9
|
|
#define SCU_RAM_PARAM_3__M 0xFFFF
|
|
#define SCU_RAM_PARAM_3__PRE 0x0
|
|
#define SCU_RAM_PARAM_3__W 16
|
|
#define SCU_RAM_PARAM_4__A 0x831FF8
|
|
#define SCU_RAM_PARAM_4__M 0xFFFF
|
|
#define SCU_RAM_PARAM_4__PRE 0x0
|
|
#define SCU_RAM_PARAM_4__W 16
|
|
#define SCU_RAM_PARAM_5__A 0x831FF7
|
|
#define SCU_RAM_PARAM_5__M 0xFFFF
|
|
#define SCU_RAM_PARAM_5__PRE 0x0
|
|
#define SCU_RAM_PARAM_5__W 16
|
|
#define SCU_RAM_PARAM_6__A 0x831FF6
|
|
#define SCU_RAM_PARAM_6__M 0xFFFF
|
|
#define SCU_RAM_PARAM_6__PRE 0x0
|
|
#define SCU_RAM_PARAM_6__W 16
|
|
#define SCU_RAM_PARAM_7__A 0x831FF5
|
|
#define SCU_RAM_PARAM_7__M 0xFFFF
|
|
#define SCU_RAM_PARAM_7__PRE 0x0
|
|
#define SCU_RAM_PARAM_7__W 16
|
|
#define SCU_RAM_PARAM_8__A 0x831FF4
|
|
#define SCU_RAM_PARAM_8__M 0xFFFF
|
|
#define SCU_RAM_PARAM_8__PRE 0x0
|
|
#define SCU_RAM_PARAM_8__W 16
|
|
#define SCU_RAM_PARAM_9__A 0x831FF3
|
|
#define SCU_RAM_PARAM_9__M 0xFFFF
|
|
#define SCU_RAM_PARAM_9__PRE 0x0
|
|
#define SCU_RAM_PARAM_9__W 16
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9
|
|
#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0
|
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14
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#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14
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#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2
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#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2
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#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2
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#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2
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#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2
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#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF
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#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF
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#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF
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#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF
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#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF
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#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9
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#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9
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#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9
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#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9
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#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9
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#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14
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#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14
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#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14
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#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14
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#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14
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#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96
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#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96
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#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96
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#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96
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#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96
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#define SCU_RAM_QAM_FSM_CTH__A 0x831F92
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#define SCU_RAM_QAM_FSM_CTH__A 0x831F92
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#define SCU_RAM_QAM_FSM_CTH__A 0x831F92
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#define SCU_RAM_QAM_FSM_CTH__A 0x831F92
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#define SCU_RAM_QAM_FSM_CTH__A 0x831F92
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#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95
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#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95
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#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95
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#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95
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#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95
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#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F
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#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F
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#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F
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#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F
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#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF
|
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF
|
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF
|
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF
|
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16
|
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16
|
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A
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#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16
|
|
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16
|
|
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84
|
|
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84
|
|
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84
|
|
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84
|
|
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84
|
|
#define SCU_RAM_QAM_FSM_MTH__A 0x831F91
|
|
#define SCU_RAM_QAM_FSM_MTH__A 0x831F91
|
|
#define SCU_RAM_QAM_FSM_MTH__A 0x831F91
|
|
#define SCU_RAM_QAM_FSM_MTH__A 0x831F91
|
|
#define SCU_RAM_QAM_FSM_MTH__A 0x831F91
|
|
#define SCU_RAM_QAM_FSM_PTH__A 0x831F90
|
|
#define SCU_RAM_QAM_FSM_PTH__A 0x831F90
|
|
#define SCU_RAM_QAM_FSM_PTH__A 0x831F90
|
|
#define SCU_RAM_QAM_FSM_PTH__A 0x831F90
|
|
#define SCU_RAM_QAM_FSM_PTH__A 0x831F90
|
|
#define SCU_RAM_QAM_FSM_QTH__A 0x831F93
|
|
#define SCU_RAM_QAM_FSM_QTH__A 0x831F93
|
|
#define SCU_RAM_QAM_FSM_QTH__A 0x831F93
|
|
#define SCU_RAM_QAM_FSM_QTH__A 0x831F93
|
|
#define SCU_RAM_QAM_FSM_QTH__A 0x831F93
|
|
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85
|
|
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85
|
|
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85
|
|
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85
|
|
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85
|
|
#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94
|
|
#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94
|
|
#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94
|
|
#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94
|
|
#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94
|
|
#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E
|
|
#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E
|
|
#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E
|
|
#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E
|
|
#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E
|
|
#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4
|
|
#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97
|
|
#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97
|
|
#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97
|
|
#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97
|
|
#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97
|
|
#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99
|
|
#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99
|
|
#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99
|
|
#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99
|
|
#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_COARSE__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_FINE__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16
|
|
#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__W 16
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__W 16
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__W 16
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__W 16
|
|
#define SCU_RAM_QAM_LC_CF_COARSE__W 16
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
|
|
#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10
|
|
#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10
|
|
#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10
|
|
#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10
|
|
#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10
|
|
#define SCU_RAM_QAM_LC_CF_FINE__W 16
|
|
#define SCU_RAM_QAM_LC_CF_FINE__W 16
|
|
#define SCU_RAM_QAM_LC_CF_FINE__W 16
|
|
#define SCU_RAM_QAM_LC_CF_FINE__W 16
|
|
#define SCU_RAM_QAM_LC_CF_FINE__W 16
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16
|
|
#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16
|
|
#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D
|
|
#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D
|
|
#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D
|
|
#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D
|
|
#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D
|
|
#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F
|
|
#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F
|
|
#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F
|
|
#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F
|
|
#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F
|
|
#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E
|
|
#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E
|
|
#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E
|
|
#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E
|
|
#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E
|
|
#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A
|
|
#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A
|
|
#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A
|
|
#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A
|
|
#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A
|
|
#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C
|
|
#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C
|
|
#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C
|
|
#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C
|
|
#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C
|
|
#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B
|
|
#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B
|
|
#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B
|
|
#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B
|
|
#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B
|
|
#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3
|
|
#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3
|
|
#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3
|
|
#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3
|
|
#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3
|
|
#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5
|
|
#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5
|
|
#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5
|
|
#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5
|
|
#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5
|
|
#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4
|
|
#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4
|
|
#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4
|
|
#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4
|
|
#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4
|
|
#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0
|
|
#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0
|
|
#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0
|
|
#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0
|
|
#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0
|
|
#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2
|
|
#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2
|
|
#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2
|
|
#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2
|
|
#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2
|
|
#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1
|
|
#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1
|
|
#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1
|
|
#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1
|
|
#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1
|
|
#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000
|
|
#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000
|
|
#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000
|
|
#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC
|
|
#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC
|
|
#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC
|
|
#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC
|
|
#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC
|
|
#define SIO_BL_CHAIN_ADDR__A 0x480018
|
|
#define SIO_BL_CHAIN_LEN__A 0x480019
|
|
#define SIO_BL_COMM_EXEC_ACTIVE 0x1
|
|
#define SIO_BL_COMM_EXEC__A 0x480000
|
|
#define SIO_BL_ENABLE_ON 0x1
|
|
#define SIO_BL_ENABLE_ON 0x1
|
|
#define SIO_BL_ENABLE__A 0x480012
|
|
#define SIO_BL_ENABLE__A 0x480012
|
|
#define SIO_BL_MODE_CHAIN 0x1
|
|
#define SIO_BL_MODE_DIRECT 0x0
|
|
#define SIO_BL_MODE__A 0x480011
|
|
#define SIO_BL_MODE__A 0x480011
|
|
#define SIO_BL_SRC_ADDR__A 0x480016
|
|
#define SIO_BL_SRC_LEN__A 0x480017
|
|
#define SIO_BL_STATUS__A 0x480010
|
|
#define SIO_BL_STATUS__A 0x480010
|
|
#define SIO_BL_TGT_ADDR__A 0x480015
|
|
#define SIO_BL_TGT_HDR__A 0x480014
|
|
#define SIO_CC_PLL_LOCK__A 0x450012
|
|
#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2
|
|
#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2
|
|
#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0
|
|
#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0
|
|
#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1
|
|
#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4
|
|
#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3
|
|
#define SIO_CC_PWD_MODE__A 0x450015
|
|
#define SIO_CC_PWD_MODE__A 0x450015
|
|
#define SIO_CC_PWD_MODE__A 0x450015
|
|
#define SIO_CC_SOFT_RST_OFDM__M 0x1
|
|
#define SIO_CC_SOFT_RST_OSC__M 0x4
|
|
#define SIO_CC_SOFT_RST_SYS__M 0x2
|
|
#define SIO_CC_SOFT_RST__A 0x450016
|
|
#define SIO_CC_UPDATE_KEY 0xFABA
|
|
#define SIO_CC_UPDATE_KEY 0xFABA
|
|
#define SIO_CC_UPDATE_KEY 0xFABA
|
|
#define SIO_CC_UPDATE_KEY 0xFABA
|
|
#define SIO_CC_UPDATE__A 0x450017
|
|
#define SIO_CC_UPDATE__A 0x450017
|
|
#define SIO_CC_UPDATE__A 0x450017
|
|
#define SIO_CC_UPDATE__A 0x450017
|
|
#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8
|
|
#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7
|
|
#define SIO_HI_RA_RAM_CMD_CONFIG 0x3
|
|
#define SIO_HI_RA_RAM_CMD_CONFIG 0x3
|
|
#define SIO_HI_RA_RAM_CMD_RESET 0x2
|
|
#define SIO_HI_RA_RAM_CMD__A 0x420032
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10
|
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#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10
|
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#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10
|
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#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10
|
|
#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1__A 0x420033
|
|
#define SIO_HI_RA_RAM_PAR_1__A 0x420033
|
|
#define SIO_HI_RA_RAM_PAR_1__A 0x420033
|
|
#define SIO_HI_RA_RAM_PAR_1__A 0x420033
|
|
#define SIO_HI_RA_RAM_PAR_1__A 0x420033
|
|
#define SIO_HI_RA_RAM_PAR_1__A 0x420033
|
|
#define SIO_HI_RA_RAM_PAR_1__A 0x420033
|
|
#define SIO_HI_RA_RAM_PAR_1__A 0x420033
|
|
#define SIO_HI_RA_RAM_PAR_1__A 0x420033
|
|
#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_1__W 16
|
|
#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1
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#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7
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#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16
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#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16
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#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16
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#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16
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#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16
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#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16
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#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16
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#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16
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#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16
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#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16
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#define SIO_HI_RA_RAM_PAR_2__A 0x420034
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#define SIO_HI_RA_RAM_PAR_2__A 0x420034
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#define SIO_HI_RA_RAM_PAR_2__A 0x420034
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#define SIO_HI_RA_RAM_PAR_2__A 0x420034
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#define SIO_HI_RA_RAM_PAR_2__A 0x420034
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#define SIO_HI_RA_RAM_PAR_2__A 0x420034
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#define SIO_HI_RA_RAM_PAR_2__A 0x420034
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#define SIO_HI_RA_RAM_PAR_2__A 0x420034
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#define SIO_HI_RA_RAM_PAR_2__A 0x420034
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#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF
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#define SIO_HI_RA_RAM_PAR_2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2__PRE 0x0
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#define SIO_HI_RA_RAM_PAR_2__W 16
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#define SIO_HI_RA_RAM_PAR_2__W 16
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#define SIO_HI_RA_RAM_PAR_2__W 16
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#define SIO_HI_RA_RAM_PAR_2__W 16
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#define SIO_HI_RA_RAM_PAR_2__W 16
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#define SIO_HI_RA_RAM_PAR_2__W 16
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#define SIO_HI_RA_RAM_PAR_2__W 16
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#define SIO_HI_RA_RAM_PAR_2__W 16
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#define SIO_HI_RA_RAM_PAR_2__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1
|
|
#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3__A 0x420035
|
|
#define SIO_HI_RA_RAM_PAR_3__A 0x420035
|
|
#define SIO_HI_RA_RAM_PAR_3__A 0x420035
|
|
#define SIO_HI_RA_RAM_PAR_3__A 0x420035
|
|
#define SIO_HI_RA_RAM_PAR_3__A 0x420035
|
|
#define SIO_HI_RA_RAM_PAR_3__A 0x420035
|
|
#define SIO_HI_RA_RAM_PAR_3__A 0x420035
|
|
#define SIO_HI_RA_RAM_PAR_3__A 0x420035
|
|
#define SIO_HI_RA_RAM_PAR_3__A 0x420035
|
|
#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_3__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8
|
|
#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4__A 0x420036
|
|
#define SIO_HI_RA_RAM_PAR_4__A 0x420036
|
|
#define SIO_HI_RA_RAM_PAR_4__A 0x420036
|
|
#define SIO_HI_RA_RAM_PAR_4__A 0x420036
|
|
#define SIO_HI_RA_RAM_PAR_4__A 0x420036
|
|
#define SIO_HI_RA_RAM_PAR_4__A 0x420036
|
|
#define SIO_HI_RA_RAM_PAR_4__A 0x420036
|
|
#define SIO_HI_RA_RAM_PAR_4__A 0x420036
|
|
#define SIO_HI_RA_RAM_PAR_4__A 0x420036
|
|
#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4__W 16
|
|
#define SIO_HI_RA_RAM_PAR_4__W 16
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#define SIO_HI_RA_RAM_PAR_4__W 16
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#define SIO_HI_RA_RAM_PAR_4__W 16
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16
|
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16
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#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0
|
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#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0
|
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#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0
|
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#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20
|
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#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1
|
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#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1
|
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#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5__A 0x420037
|
|
#define SIO_HI_RA_RAM_PAR_5__A 0x420037
|
|
#define SIO_HI_RA_RAM_PAR_5__A 0x420037
|
|
#define SIO_HI_RA_RAM_PAR_5__A 0x420037
|
|
#define SIO_HI_RA_RAM_PAR_5__A 0x420037
|
|
#define SIO_HI_RA_RAM_PAR_5__A 0x420037
|
|
#define SIO_HI_RA_RAM_PAR_5__A 0x420037
|
|
#define SIO_HI_RA_RAM_PAR_5__A 0x420037
|
|
#define SIO_HI_RA_RAM_PAR_5__A 0x420037
|
|
#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_5__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6__A 0x420038
|
|
#define SIO_HI_RA_RAM_PAR_6__A 0x420038
|
|
#define SIO_HI_RA_RAM_PAR_6__A 0x420038
|
|
#define SIO_HI_RA_RAM_PAR_6__A 0x420038
|
|
#define SIO_HI_RA_RAM_PAR_6__A 0x420038
|
|
#define SIO_HI_RA_RAM_PAR_6__A 0x420038
|
|
#define SIO_HI_RA_RAM_PAR_6__A 0x420038
|
|
#define SIO_HI_RA_RAM_PAR_6__A 0x420038
|
|
#define SIO_HI_RA_RAM_PAR_6__A 0x420038
|
|
#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF
|
|
#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF
|
|
#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF
|
|
#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF
|
|
#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF
|
|
#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF
|
|
#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF
|
|
#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF
|
|
#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF
|
|
#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF
|
|
#define SIO_HI_RA_RAM_PAR_6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6__W 16
|
|
#define SIO_HI_RA_RAM_PAR_6__W 16
|
|
#define SIO_HI_RA_RAM_RES__A 0x420031
|
|
#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0
|
|
#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0
|
|
#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1
|
|
#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1
|
|
#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010
|
|
#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010
|
|
#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0
|
|
#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1
|
|
#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012
|
|
#define SIO_PDR_MCLK_CFG_DRIVE__B 3
|
|
#define SIO_PDR_MCLK_CFG__A 0x7F0028
|
|
#define SIO_PDR_MD0_CFG_DRIVE__B 3
|
|
#define SIO_PDR_MD0_CFG_DRIVE__M 0x38
|
|
#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10
|
|
#define SIO_PDR_MD0_CFG_DRIVE__W 3
|
|
#define SIO_PDR_MD0_CFG_KEEP__B 6
|
|
#define SIO_PDR_MD0_CFG_KEEP__M 0xC0
|
|
#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40
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#define SIO_PDR_MD0_CFG_KEEP__W 2
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#define SIO_PDR_MD0_CFG_MODE__B 0
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#define SIO_PDR_MD0_CFG_MODE__M 0x7
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#define SIO_PDR_MD0_CFG_MODE__PRE 0x0
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#define SIO_PDR_MD0_CFG_MODE__W 3
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#define SIO_PDR_MD0_CFG_UIO__B 8
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#define SIO_PDR_MD0_CFG_UIO__M 0x100
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#define SIO_PDR_MD0_CFG_UIO__PRE 0x0
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#define SIO_PDR_MD0_CFG_UIO__W 1
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#define SIO_PDR_MD0_CFG__A 0x7F002A
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#define SIO_PDR_MD0_CFG__M 0x1FF
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#define SIO_PDR_MD0_CFG__PRE 0x50
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#define SIO_PDR_MD0_CFG__W 9
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#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0
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#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3
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#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0
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#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2
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#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056
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#define SIO_PDR_MD0_GPIO_FNC__M 0x3
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#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0
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#define SIO_PDR_MD0_GPIO_FNC__W 2
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#define SIO_PDR_MD1_CFG_DRIVE__B 3
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#define SIO_PDR_MD1_CFG_DRIVE__M 0x38
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#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10
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#define SIO_PDR_MD1_CFG_DRIVE__W 3
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#define SIO_PDR_MD1_CFG_KEEP__B 6
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#define SIO_PDR_MD1_CFG_KEEP__M 0xC0
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#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40
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#define SIO_PDR_MD1_CFG_KEEP__W 2
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#define SIO_PDR_MD1_CFG_MODE__B 0
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#define SIO_PDR_MD1_CFG_MODE__M 0x7
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#define SIO_PDR_MD1_CFG_MODE__PRE 0x0
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#define SIO_PDR_MD1_CFG_MODE__W 3
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#define SIO_PDR_MD1_CFG_UIO__B 8
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#define SIO_PDR_MD1_CFG_UIO__M 0x100
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#define SIO_PDR_MD1_CFG_UIO__PRE 0x0
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#define SIO_PDR_MD1_CFG_UIO__W 1
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#define SIO_PDR_MD1_CFG__A 0x7F002B
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#define SIO_PDR_MD1_CFG__M 0x1FF
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#define SIO_PDR_MD1_CFG__PRE 0x50
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#define SIO_PDR_MD1_CFG__W 9
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#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0
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#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3
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#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0
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#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2
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#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057
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#define SIO_PDR_MD1_GPIO_FNC__M 0x3
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#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0
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#define SIO_PDR_MD1_GPIO_FNC__W 2
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#define SIO_PDR_MD2_CFG_DRIVE__B 3
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#define SIO_PDR_MD2_CFG_DRIVE__M 0x38
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#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10
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#define SIO_PDR_MD2_CFG_DRIVE__W 3
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#define SIO_PDR_MD2_CFG_KEEP__B 6
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#define SIO_PDR_MD2_CFG_KEEP__M 0xC0
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#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40
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#define SIO_PDR_MD2_CFG_KEEP__W 2
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#define SIO_PDR_MD2_CFG_MODE__B 0
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#define SIO_PDR_MD2_CFG_MODE__M 0x7
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#define SIO_PDR_MD2_CFG_MODE__PRE 0x0
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#define SIO_PDR_MD2_CFG_MODE__W 3
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#define SIO_PDR_MD2_CFG_UIO__B 8
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#define SIO_PDR_MD2_CFG_UIO__M 0x100
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#define SIO_PDR_MD2_CFG_UIO__PRE 0x0
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#define SIO_PDR_MD2_CFG_UIO__W 1
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#define SIO_PDR_MD2_CFG__A 0x7F002C
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#define SIO_PDR_MD2_CFG__M 0x1FF
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#define SIO_PDR_MD2_CFG__PRE 0x50
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#define SIO_PDR_MD2_CFG__W 9
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#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0
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#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3
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#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0
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#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2
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#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058
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#define SIO_PDR_MD2_GPIO_FNC__M 0x3
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#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0
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#define SIO_PDR_MD2_GPIO_FNC__W 2
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#define SIO_PDR_MD3_CFG_DRIVE__B 3
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#define SIO_PDR_MD3_CFG_DRIVE__M 0x38
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#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10
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#define SIO_PDR_MD3_CFG_DRIVE__W 3
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#define SIO_PDR_MD3_CFG_KEEP__B 6
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#define SIO_PDR_MD3_CFG_KEEP__M 0xC0
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#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40
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#define SIO_PDR_MD3_CFG_KEEP__W 2
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#define SIO_PDR_MD3_CFG_MODE__B 0
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#define SIO_PDR_MD3_CFG_MODE__M 0x7
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#define SIO_PDR_MD3_CFG_MODE__PRE 0x0
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#define SIO_PDR_MD3_CFG_MODE__W 3
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#define SIO_PDR_MD3_CFG_UIO__B 8
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#define SIO_PDR_MD3_CFG_UIO__M 0x100
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#define SIO_PDR_MD3_CFG_UIO__PRE 0x0
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#define SIO_PDR_MD3_CFG_UIO__W 1
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#define SIO_PDR_MD3_CFG__A 0x7F002D
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#define SIO_PDR_MD3_CFG__M 0x1FF
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#define SIO_PDR_MD3_CFG__PRE 0x50
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#define SIO_PDR_MD3_CFG__W 9
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#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0
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#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3
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#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0
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#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2
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#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059
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#define SIO_PDR_MD3_GPIO_FNC__M 0x3
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#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0
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#define SIO_PDR_MD3_GPIO_FNC__W 2
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#define SIO_PDR_MD4_CFG_DRIVE__B 3
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#define SIO_PDR_MD4_CFG_DRIVE__M 0x38
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#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10
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#define SIO_PDR_MD4_CFG_DRIVE__W 3
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#define SIO_PDR_MD4_CFG_KEEP__B 6
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#define SIO_PDR_MD4_CFG_KEEP__M 0xC0
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#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40
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#define SIO_PDR_MD4_CFG_KEEP__W 2
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#define SIO_PDR_MD4_CFG_MODE__B 0
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#define SIO_PDR_MD4_CFG_MODE__M 0x7
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#define SIO_PDR_MD4_CFG_MODE__PRE 0x0
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#define SIO_PDR_MD4_CFG_MODE__W 3
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#define SIO_PDR_MD4_CFG_UIO__B 8
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#define SIO_PDR_MD4_CFG_UIO__M 0x100
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#define SIO_PDR_MD4_CFG_UIO__PRE 0x0
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#define SIO_PDR_MD4_CFG_UIO__W 1
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#define SIO_PDR_MD4_CFG__A 0x7F002F
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#define SIO_PDR_MD4_CFG__M 0x1FF
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#define SIO_PDR_MD4_CFG__PRE 0x50
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#define SIO_PDR_MD4_CFG__W 9
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#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0
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#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3
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#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0
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#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2
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#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A
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#define SIO_PDR_MD4_GPIO_FNC__M 0x3
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#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0
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#define SIO_PDR_MD4_GPIO_FNC__W 2
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#define SIO_PDR_MD5_CFG_DRIVE__B 3
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#define SIO_PDR_MD5_CFG_DRIVE__M 0x38
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#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10
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#define SIO_PDR_MD5_CFG_DRIVE__W 3
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#define SIO_PDR_MD5_CFG_KEEP__B 6
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#define SIO_PDR_MD5_CFG_KEEP__M 0xC0
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#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40
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#define SIO_PDR_MD5_CFG_KEEP__W 2
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#define SIO_PDR_MD5_CFG_MODE__B 0
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#define SIO_PDR_MD5_CFG_MODE__M 0x7
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#define SIO_PDR_MD5_CFG_MODE__PRE 0x0
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#define SIO_PDR_MD5_CFG_MODE__W 3
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#define SIO_PDR_MD5_CFG_UIO__B 8
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#define SIO_PDR_MD5_CFG_UIO__M 0x100
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#define SIO_PDR_MD5_CFG_UIO__PRE 0x0
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#define SIO_PDR_MD5_CFG_UIO__W 1
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#define SIO_PDR_MD5_CFG__A 0x7F0030
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#define SIO_PDR_MD5_CFG__M 0x1FF
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#define SIO_PDR_MD5_CFG__PRE 0x50
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#define SIO_PDR_MD5_CFG__W 9
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#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0
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#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3
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#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0
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#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2
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#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B
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#define SIO_PDR_MD5_GPIO_FNC__M 0x3
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#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0
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#define SIO_PDR_MD5_GPIO_FNC__W 2
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#define SIO_PDR_MD6_CFG_DRIVE__B 3
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#define SIO_PDR_MD6_CFG_DRIVE__M 0x38
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#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10
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#define SIO_PDR_MD6_CFG_DRIVE__W 3
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#define SIO_PDR_MD6_CFG_KEEP__B 6
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#define SIO_PDR_MD6_CFG_KEEP__M 0xC0
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#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40
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#define SIO_PDR_MD6_CFG_KEEP__W 2
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#define SIO_PDR_MD6_CFG_MODE__B 0
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#define SIO_PDR_MD6_CFG_MODE__M 0x7
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#define SIO_PDR_MD6_CFG_MODE__PRE 0x0
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#define SIO_PDR_MD6_CFG_MODE__W 3
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#define SIO_PDR_MD6_CFG_UIO__B 8
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#define SIO_PDR_MD6_CFG_UIO__M 0x100
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#define SIO_PDR_MD6_CFG_UIO__PRE 0x0
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#define SIO_PDR_MD6_CFG_UIO__W 1
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#define SIO_PDR_MD6_CFG__A 0x7F0031
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#define SIO_PDR_MD6_CFG__M 0x1FF
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#define SIO_PDR_MD6_CFG__PRE 0x50
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#define SIO_PDR_MD6_CFG__W 9
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#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0
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#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3
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#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0
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#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2
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#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C
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#define SIO_PDR_MD6_GPIO_FNC__M 0x3
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#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0
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#define SIO_PDR_MD6_GPIO_FNC__W 2
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#define SIO_PDR_MD7_CFG_DRIVE__B 3
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#define SIO_PDR_MD7_CFG_DRIVE__M 0x38
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#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10
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#define SIO_PDR_MD7_CFG_DRIVE__W 3
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#define SIO_PDR_MD7_CFG_KEEP__B 6
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#define SIO_PDR_MD7_CFG_KEEP__M 0xC0
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#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40
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#define SIO_PDR_MD7_CFG_KEEP__W 2
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#define SIO_PDR_MD7_CFG_MODE__B 0
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#define SIO_PDR_MD7_CFG_MODE__M 0x7
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#define SIO_PDR_MD7_CFG_MODE__PRE 0x0
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#define SIO_PDR_MD7_CFG_MODE__W 3
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#define SIO_PDR_MD7_CFG_UIO__B 8
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#define SIO_PDR_MD7_CFG_UIO__M 0x100
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#define SIO_PDR_MD7_CFG_UIO__PRE 0x0
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#define SIO_PDR_MD7_CFG_UIO__W 1
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#define SIO_PDR_MD7_CFG__A 0x7F0032
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#define SIO_PDR_MD7_CFG__M 0x1FF
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#define SIO_PDR_MD7_CFG__PRE 0x50
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#define SIO_PDR_MD7_CFG__W 9
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#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0
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#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3
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#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0
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#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2
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#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D
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#define SIO_PDR_MD7_GPIO_FNC__M 0x3
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#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0
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#define SIO_PDR_MD7_GPIO_FNC__W 2
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#define SIO_PDR_MERR_CFG__A 0x7F0026
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#define SIO_PDR_MON_CFG__A 0x7F0010
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#define SIO_PDR_MSTRT_CFG__A 0x7F0025
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#define SIO_PDR_MVAL_CFG__A 0x7F0029
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#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3
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#define SIO_PDR_OHW_CFG__A 0x7F001F
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#define SIO_PDR_SMA_TX_CFG__A 0x7F0038
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#define SIO_PDR_UIO_IN_HI__A 0x7F0015
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#define SIO_PDR_UIO_OUT_LO__A 0x7F0016
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#define SIO_TOP_COMM_KEY_KEY 0xFABA
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#define SIO_TOP_COMM_KEY_KEY 0xFABA
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#define SIO_TOP_COMM_KEY__A 0x41000F
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#define SIO_TOP_COMM_KEY__A 0x41000F
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#define SIO_TOP_COMM_KEY__A 0x41000F
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#define SIO_TOP_COMM_KEY__A 0x41000F
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#define SIO_TOP_JTAGID_LO__A 0x410012
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#define SIO_TOP_JTAGID_LO__A 0x410012
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