mirror of
https://github.com/DigitalDevices/dddvb.git
synced 2023-10-10 13:37:43 +02:00
416 lines
11 KiB
C
416 lines
11 KiB
C
/*
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* ddbridge-mci.c: Digital Devices microcode interface
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*
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* Copyright (C) 2017-2018 Digital Devices GmbH
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* Ralph Metzler <rjkm@metzlerbros.de>
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* Marcus Metzler <mocm@metzlerbros.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 only, as published by the Free Software Foundation.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, point your browser to
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "ddbridge.h"
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#include "ddbridge-io.h"
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#include "ddbridge-mci.h"
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static LIST_HEAD(mci_list);
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static int mci_reset(struct mci *state)
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{
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struct ddb_link *link = state->base->link;
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u32 status = 0;
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u32 timeout = 40;
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ddblwritel(link, MCI_CONTROL_RESET, MCI_CONTROL);
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ddblwritel(link, 0, MCI_CONTROL + 4); /* 1= no internal init */
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msleep(300);
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ddblwritel(link, 0, MCI_CONTROL);
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while(1) {
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status = ddblreadl(link, MCI_CONTROL);
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if ((status & MCI_CONTROL_READY) == MCI_CONTROL_READY)
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break;
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if (--timeout == 0)
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break;
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msleep(50);
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}
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if ((status & MCI_CONTROL_READY) == 0 )
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return -1;
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if (link->ids.device == 0x0009)
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ddblwritel(link, SX8_TSCONFIG_MODE_NORMAL, SX8_TSCONFIG);
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return 0;
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}
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int ddb_mci_config(struct mci *state, u32 config)
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{
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struct ddb_link *link = state->base->link;
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if (link->ids.device != 0x0009)
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return -EINVAL;
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ddblwritel(link, config, SX8_TSCONFIG);
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return 0;
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}
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static int ddb_mci_cmd_raw_unlocked(struct mci *state,
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u32 *cmd, u32 cmd_len,
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u32 *res, u32 res_len)
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{
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struct ddb_link *link = state->base->link;
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u32 i, val;
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unsigned long stat;
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val = ddblreadl(link, MCI_CONTROL);
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if (val & (MCI_CONTROL_RESET | MCI_CONTROL_START_COMMAND))
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return -EIO;
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if (cmd && cmd_len)
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for (i = 0; i < cmd_len; i++)
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ddblwritel(link, cmd[i], MCI_COMMAND + i * 4);
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val |= (MCI_CONTROL_START_COMMAND | MCI_CONTROL_ENABLE_DONE_INTERRUPT);
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ddblwritel(link, val, MCI_CONTROL);
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stat = wait_for_completion_timeout(&state->base->completion, HZ);
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if (stat == 0) {
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printk("MCI timeout\n");
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return -EIO;
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}
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if (res && res_len)
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for (i = 0; i < res_len; i++)
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res[i] = ddblreadl(link, MCI_RESULT + i * 4);
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return 0;
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}
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int ddb_mci_cmd_unlocked(struct mci *state,
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struct mci_command *command,
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struct mci_result *result)
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{
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u32 *cmd = (u32 *) command;
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u32 *res = (u32 *) result;
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return ddb_mci_cmd_raw_unlocked(state, cmd, sizeof(*command)/sizeof(u32),
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res, sizeof(*result)/sizeof(u32));
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}
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int ddb_mci_cmd(struct mci *state,
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struct mci_command *command,
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struct mci_result *result)
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{
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int stat;
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mutex_lock(&state->base->mci_lock);
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stat = ddb_mci_cmd_raw_unlocked(state,
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(u32 *)command, sizeof(*command)/sizeof(u32),
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(u32 *)result, sizeof(*result)/sizeof(u32));
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mutex_unlock(&state->base->mci_lock);
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return stat;
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}
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int ddb_mci_cmd_raw(struct mci *state,
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struct mci_command *command, u32 command_len,
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struct mci_result *result, u32 result_len)
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{
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int stat;
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mutex_lock(&state->base->mci_lock);
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stat = ddb_mci_cmd_raw_unlocked(state,
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(u32 *)command, command_len,
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(u32 *)result, result_len);
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mutex_unlock(&state->base->mci_lock);
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return stat;
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}
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static int ddb_mci_get_iq(struct mci *mci, u32 demod, s16 *i, s16 *q)
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{
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int stat;
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struct mci_command cmd;
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struct mci_result res;
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memset(&cmd, 0, sizeof(cmd));
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memset(&res, 0, sizeof(res));
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cmd.command = MCI_CMD_GET_IQSYMBOL;
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cmd.demod = demod;
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stat = ddb_mci_cmd(mci, &cmd, &res);
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if (!stat) {
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*i = res.iq_symbol.i;
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*q = res.iq_symbol.q;
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}
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return stat;
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}
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int ddb_mci_get_status(struct mci *mci, struct mci_result *res)
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{
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struct mci_command cmd;
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cmd.command = MCI_CMD_GETSTATUS;
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cmd.demod = mci->demod;
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return ddb_mci_cmd_raw(mci, &cmd, 1, res, 1);
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}
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int ddb_mci_get_snr(struct dvb_frontend *fe)
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{
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struct mci *mci = fe->demodulator_priv;
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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p->cnr.len = 1;
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p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
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p->cnr.stat[0].svalue = (s64) mci->
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signal_info.dvbs2_signal_info.signal_to_noise * 10;
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return 0;
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}
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int ddb_mci_get_strength(struct dvb_frontend *fe)
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{
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struct mci *mci = fe->demodulator_priv;
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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s32 str;
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str = mci->signal_info.dvbs2_signal_info.channel_power * 10;
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p->strength.len = 1;
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p->strength.stat[0].scale = FE_SCALE_DECIBEL;
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p->strength.stat[0].svalue = str;
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return 0;
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}
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int ddb_mci_get_info(struct mci *mci)
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{
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int stat;
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struct mci_command cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.command = MCI_CMD_GETSIGNALINFO;
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cmd.demod = mci->demod;
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stat = ddb_mci_cmd(mci, &cmd, &mci->signal_info);
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return stat;
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}
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/****************************************************************************/
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/****************************************************************************/
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void ddb_mci_proc_info(struct mci *mci, struct dtv_frontend_properties *p)
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{
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const enum fe_modulation modcod2mod[0x20] = {
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QPSK, QPSK, QPSK, QPSK,
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QPSK, QPSK, QPSK, QPSK,
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QPSK, QPSK, QPSK, QPSK,
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PSK_8, PSK_8, PSK_8, PSK_8,
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PSK_8, PSK_8, APSK_16, APSK_16,
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APSK_16, APSK_16, APSK_16, APSK_16,
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APSK_32, APSK_32, APSK_32, APSK_32,
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APSK_32,
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};
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const enum fe_code_rate modcod2fec[0x20] = {
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FEC_NONE, FEC_1_4, FEC_1_3, FEC_2_5,
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FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
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FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
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FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
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FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
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FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
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FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
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FEC_9_10, FEC_NONE, FEC_NONE, FEC_NONE,
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};
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const enum fe_code_rate dvbs_fec_lut[8] = {
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FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6,
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FEC_NONE, FEC_7_8, FEC_NONE, FEC_NONE,
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};
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const enum fe_rolloff ro_lut[8] = {
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ROLLOFF_35, ROLLOFF_25, ROLLOFF_20, ROLLOFF_10,
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ROLLOFF_5, ROLLOFF_15, ROLLOFF_35, ROLLOFF_35
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};
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const enum fe_modulation modcod2modS2X[0x3D] = {
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MODULATION_NONE, MODULATION_NONE, //2
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QPSK, QPSK, QPSK, //3
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APSK_8, APSK_8,APSK_8,APSK_8,APSK_8, //5
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APSK_16,APSK_16,APSK_16,APSK_16,APSK_16,APSK_16,APSK_16,APSK_16,APSK_16,APSK_16,APSK_16,APSK_16,APSK_16,//13
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APSK_32,MODULATION_NONE,APSK_32,APSK_32,APSK_32,//5
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APSK_64, APSK_64, MODULATION_NONE, APSK_64,MODULATION_NONE, APSK_64,MODULATION_NONE ,APSK_64,//8
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APSK_128, APSK_128,
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APSK_256, APSK_256,APSK_256,APSK_256,APSK_256,APSK_256,
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QPSK, QPSK,QPSK,QPSK,QPSK,QPSK,
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PSK_8,PSK_8,PSK_8,PSK_8,
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APSK_16,APSK_16,APSK_16,APSK_16,APSK_16,
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APSK_32,APSK_32,
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};
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const enum fe_code_rate modcod2fecS2X[0x3D] = {
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FEC_NONE, FEC_NONE, //2
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FEC_13_45, FEC_9_20, FEC_11_20, //3
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FEC_5_9_L, FEC_26_45_L, FEC_23_36, FEC_25_36, FEC_13_18, //5
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FEC_1_2_L, FEC_8_15_L, FEC_5_9_L, FEC_26_45, FEC_3_5, FEC_3_5_L, FEC_28_45, FEC_23_36,FEC_2_3_L, FEC_25_36, FEC_13_18,FEC_7_9, FEC_77_90, //13
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FEC_2_3_L, FEC_NONE, FEC_32_45, FEC_11_15, FEC_7_9,
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FEC_32_45_L, FEC_11_15,FEC_NONE ,FEC_7_9, FEC_NONE, FEC_4_5, FEC_NONE, FEC_5_6, //8
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FEC_3_4,FEC_7_9, FEC_29_45_L,FEC_2_3_L,FEC_31_45_L,FEC_32_45,FEC_11_15_L,
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FEC_3_4,FEC_11_45,FEC_4_15,FEC_14_45,FEC_7_15,FEC_8_15,
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FEC_32_45,FEC_7_15,FEC_8_15,FEC_26_45,FEC_32_45,FEC_7_15,
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FEC_8_15,FEC_26_45,FEC_3_5,FEC_32_45,FEC_2_3,FEC_32_45,
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};
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p->frequency =
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mci->signal_info.dvbs2_signal_info.frequency;
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switch (p->delivery_system) {
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default:
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case SYS_DVBS:
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case SYS_DVBS2:
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{
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u32 pls_code =
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mci->signal_info.dvbs2_signal_info.pls_code;
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p->frequency =
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mci->signal_info.dvbs2_signal_info.frequency / 1000;
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p->delivery_system =
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(mci->signal_info.dvbs2_signal_info.standard == 2) ?
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SYS_DVBS2 : SYS_DVBS;
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if (mci->signal_info.dvbs2_signal_info.standard == 2) {
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p->delivery_system = SYS_DVBS2;
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p->rolloff =
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ro_lut[mci->signal_info.
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dvbs2_signal_info.roll_off & 7];
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p->pilot = (pls_code & 1) ? PILOT_ON : PILOT_OFF;
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if(pls_code & 0x80) //DVB-S2X
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{
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uint8_t modcodS2X = (pls_code & 0x7F) >> 1;
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p->fec_inner = modcod2fecS2X[modcodS2X];
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p->modulation = modcod2modS2X[modcodS2X];
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}
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else
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{
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u32 modcod = (0x7c & pls_code) >> 2;
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p->fec_inner = modcod2fec[modcod];
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p->modulation = modcod2mod[modcod];
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}
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p->transmission_mode = pls_code;
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} else {
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p->delivery_system = SYS_DVBS;
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p->rolloff = ROLLOFF_35;
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p->pilot = PILOT_OFF;
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p->fec_inner = dvbs_fec_lut[pls_code & 7];
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p->modulation = QPSK;
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}
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break;
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}
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case SYS_DVBC_ANNEX_A:
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break;
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case SYS_DVBT:
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break;
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case SYS_DVBT2:
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break;
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case SYS_DVBC2:
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break;
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case SYS_ISDBT:
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break;
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}
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p->pre_bit_error.len = 1;
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p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
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p->pre_bit_error.stat[0].uvalue =
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mci->signal_info.dvbs2_signal_info.ber_numerator;
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p->pre_bit_count.len = 1;
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p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
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p->pre_bit_count.stat[0].uvalue =
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mci->signal_info.dvbs2_signal_info.ber_denominator;
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p->block_error.len = 1;
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p->block_error.stat[0].scale = FE_SCALE_COUNTER;
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p->block_error.stat[0].uvalue =
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mci->signal_info.dvbs2_signal_info.packet_errors;
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p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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p->cnr.len = 1;
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p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
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p->cnr.stat[0].svalue = (s64) mci->
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signal_info.dvbs2_signal_info.signal_to_noise * 10;
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p->strength.len = 1;
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p->strength.stat[0].scale = FE_SCALE_DECIBEL;
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p->strength.stat[0].svalue =
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mci->signal_info.dvbs2_signal_info.channel_power * 10;
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}
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static void mci_handler(void *priv)
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{
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struct mci_base *base = (struct mci_base *)priv;
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complete(&base->completion);
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}
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static struct mci_base *match_base(void *key)
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{
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struct mci_base *p;
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list_for_each_entry(p, &mci_list, mci_list)
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if (p->key == key)
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return p;
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return NULL;
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}
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static int probe(struct mci *state)
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{
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mci_reset(state);
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return 0;
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}
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struct dvb_frontend *ddb_mci_attach(struct ddb_input *input, struct mci_cfg *cfg, int nr, int tuner)
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{
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struct ddb_port *port = input->port;
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struct ddb *dev = port->dev;
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struct ddb_link *link = &dev->link[port->lnr];
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struct mci_base *base;
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struct mci *state;
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void *key = cfg->type ? (void *) port : (void *) link;
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state = kzalloc(cfg->state_size, GFP_KERNEL);
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if (!state)
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return NULL;
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base = match_base(key);
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if (base) {
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base->count++;
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state->base = base;
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} else {
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base = kzalloc(cfg->base_size, GFP_KERNEL);
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if (!base)
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goto fail;
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base->key = key;
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base->count = 1;
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base->link = link;
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mutex_init(&base->mci_lock);
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mutex_init(&base->tuner_lock);
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ddb_irq_set(dev, link->nr, 0, mci_handler, base);
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init_completion(&base->completion);
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state->base = base;
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if (probe(state) < 0) {
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kfree(base);
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goto fail;
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}
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list_add(&base->mci_list, &mci_list);
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if (cfg->base_init)
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cfg->base_init(base);
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}
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memcpy(&state->fe.ops, cfg->fe_ops, sizeof(struct dvb_frontend_ops));
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state->fe.demodulator_priv = state;
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state->nr = nr;
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state->demod = nr;
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state->tuner = tuner;
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if (cfg->init)
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cfg->init(state);
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return &state->fe;
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fail:
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kfree(state);
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return NULL;
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}
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