mirror of
https://github.com/DigitalDevices/dddvb.git
synced 2023-10-10 13:37:43 +02:00
409 lines
11 KiB
C
409 lines
11 KiB
C
/*
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* ddbridge.c: Digital Devices PCIe bridge driver
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*
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* Copyright (C) 2010-2017 Digital Devices GmbH
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* Ralph Metzler <rjkm@metzlerbros.de>
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* Marcus Metzler <mocm@metzlerbros.de>
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 only, as published by the Free Software Foundation.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, point your browser to
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "ddbridge.h"
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#include "ddbridge-io.h"
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#ifdef CONFIG_PCI_MSI
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static int msi = 1;
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module_param(msi, int, 0444);
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MODULE_PARM_DESC(msi,
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" Control MSI interrupts: 0-disable, 1-enable (default)");
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#endif
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extern struct workqueue_struct *ddb_wq;
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/****************************************************************************/
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/****************************************************************************/
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/****************************************************************************/
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static void __devexit ddb_irq_disable(struct ddb *dev)
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{
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if (dev->link[0].info->regmap->irq_version == 2) {
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_CONTROL);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_1);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_2);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_3);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_4);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_5);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_6);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_7);
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} else {
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ddbwritel(dev, 0, INTERRUPT_ENABLE);
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ddbwritel(dev, 0, MSI1_ENABLE);
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}
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}
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static void __devexit ddb_irq_exit(struct ddb *dev)
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{
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ddb_irq_disable(dev);
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if (dev->msi == 2)
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free_irq(dev->pdev->irq + 1, dev);
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free_irq(dev->pdev->irq, dev);
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#ifdef CONFIG_PCI_MSI
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if (dev->msi)
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pci_disable_msi(dev->pdev);
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#endif
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}
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static void __devexit ddb_remove(struct pci_dev *pdev)
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{
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struct ddb *dev = (struct ddb *)pci_get_drvdata(pdev);
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ddb_device_destroy(dev);
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ddb_nsd_detach(dev);
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ddb_ports_detach(dev);
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ddb_i2c_release(dev);
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if (dev->link[0].info->ns_num)
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ddbwritel(dev, 0, ETHER_CONTROL);
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ddb_irq_exit(dev);
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ddb_ports_release(dev);
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ddb_buffers_free(dev);
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ddb_unmap(dev);
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pci_set_drvdata(pdev, NULL);
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pci_disable_device(pdev);
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}
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#if (KERNEL_VERSION(3, 8, 0) <= LINUX_VERSION_CODE)
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#define __devinit
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#define __devinitdata
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#endif
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static int __devinit ddb_irq_msi(struct ddb *dev, int nr)
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{
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int stat = 0;
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#ifdef CONFIG_PCI_MSI
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if (msi && pci_msi_enabled()) {
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#if (KERNEL_VERSION(3, 15, 0) <= LINUX_VERSION_CODE)
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#if (KERNEL_VERSION(4, 11, 0) <= LINUX_VERSION_CODE)
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stat = pci_alloc_irq_vectors(dev->pdev, 1, nr, PCI_IRQ_MSI);
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#else
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stat = pci_enable_msi_range(dev->pdev, 1, nr);
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#endif
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if (stat >= 1) {
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dev->msi = stat;
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dev_info(dev->dev, "using %d MSI interrupt(s)\n",
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dev->msi);
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} else {
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dev_info(dev->dev, "MSI not available.\n");
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}
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#else
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stat = pci_enable_msi_block(dev->pdev, nr);
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if (stat == 0) {
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dev->msi = nr;
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dev_info(dev->dev, "using %d MSI interrupts\n", nr);
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} else if (stat == 1) {
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stat = pci_enable_msi(dev->pdev);
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dev->msi = 1;
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}
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if (stat < 0)
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dev_info(dev->dev, "MSI not available.\n");
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#endif
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}
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#endif
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return stat;
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}
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static int __devinit ddb_irq_init2(struct ddb *dev)
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{
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int stat;
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int irq_flag = IRQF_SHARED;
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dev_info(dev->dev, "init type 2 IRQ hardware block\n");
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_CONTROL);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_1);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_2);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_3);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_4);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_5);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_6);
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ddbwritel(dev, 0x00000000, INTERRUPT_V2_ENABLE_7);
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ddb_irq_msi(dev, 1);
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if (dev->msi)
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irq_flag = 0;
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stat = request_irq(dev->pdev->irq, ddb_irq_handler_v2,
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irq_flag, "ddbridge", (void *)dev);
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if (stat < 0)
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return stat;
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ddbwritel(dev, 0x0000ff7f, INTERRUPT_V2_CONTROL);
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ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_1);
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ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_2);
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ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_3);
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ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_4);
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ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_5);
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ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_6);
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ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_7);
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return stat;
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}
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static int __devinit ddb_irq_init(struct ddb *dev)
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{
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int stat;
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int irq_flag = IRQF_SHARED;
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if (dev->link[0].info->regmap->irq_version == 2)
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return ddb_irq_init2(dev);
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ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE);
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ddbwritel(dev, 0x00000000, MSI1_ENABLE);
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ddbwritel(dev, 0x00000000, MSI2_ENABLE);
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ddbwritel(dev, 0x00000000, MSI3_ENABLE);
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ddbwritel(dev, 0x00000000, MSI4_ENABLE);
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ddbwritel(dev, 0x00000000, MSI5_ENABLE);
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ddbwritel(dev, 0x00000000, MSI6_ENABLE);
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ddbwritel(dev, 0x00000000, MSI7_ENABLE);
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ddb_irq_msi(dev, 2);
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if (dev->msi)
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irq_flag = 0;
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if (dev->msi == 2) {
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stat = request_irq(dev->pdev->irq, ddb_irq_handler0,
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irq_flag, "ddbridge", (void *)dev);
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if (stat < 0)
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return stat;
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stat = request_irq(dev->pdev->irq + 1, ddb_irq_handler1,
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irq_flag, "ddbridge", (void *)dev);
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if (stat < 0) {
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free_irq(dev->pdev->irq, dev);
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return stat;
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}
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} else {
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#ifdef DDB_TEST_THREADED
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stat = request_threaded_irq(dev->pdev->irq, ddb_irq_handler,
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irq_thread,
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irq_flag,
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"ddbridge", (void *)dev);
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#else
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stat = request_irq(dev->pdev->irq, ddb_irq_handler,
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irq_flag, "ddbridge", (void *)dev);
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#endif
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if (stat < 0)
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return stat;
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}
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/*ddbwritel(dev, 0xffffffff, INTERRUPT_ACK);*/
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if (dev->msi == 2) {
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ddbwritel(dev, 0x0fffff00, INTERRUPT_ENABLE);
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ddbwritel(dev, 0x0000000f, MSI1_ENABLE);
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} else {
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ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE);
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ddbwritel(dev, 0x00000000, MSI1_ENABLE);
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}
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return stat;
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}
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static int __devinit ddb_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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struct ddb *dev;
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int stat = 0;
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if (pci_enable_device(pdev) < 0)
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return -ENODEV;
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pci_set_master(pdev);
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if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
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if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
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return -ENODEV;
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dev = vzalloc(sizeof(*dev));
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if (!dev)
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return -ENOMEM;
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mutex_init(&dev->mutex);
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dev->has_dma = 1;
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dev->pdev = pdev;
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dev->dev = &pdev->dev;
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pci_set_drvdata(pdev, dev);
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dev->link[0].ids.vendor = id->vendor;
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dev->link[0].ids.device = id->device;
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dev->link[0].ids.subvendor = id->subvendor;
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dev->link[0].ids.subdevice = pdev->subsystem_device;
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dev->link[0].dev = dev;
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dev->link[0].info = get_ddb_info(id->vendor, id->device,
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id->subvendor, pdev->subsystem_device);
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dev_info(dev->dev, "device name: %s\n", dev->link[0].info->name);
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dev->regs_len = pci_resource_len(dev->pdev, 0);
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dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
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pci_resource_len(dev->pdev, 0));
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if (!dev->regs) {
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dev_err(dev->dev, "not enough memory for register map\n");
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stat = -ENOMEM;
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goto fail;
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}
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if (ddbreadl(dev, 0) == 0xffffffff) {
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dev_err(dev->dev, "cannot read registers\n");
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stat = -ENODEV;
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goto fail;
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}
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dev->link[0].ids.hwid = ddbreadl(dev, 0);
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dev->link[0].ids.regmapid = ddbreadl(dev, 4);
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dev_info(dev->dev, "HW %08x REGMAP %08x\n",
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dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
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if (dev->link[0].info->ns_num) {
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ddbwritel(dev, 0, ETHER_CONTROL);
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ddb_reset_ios(dev);
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}
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ddbwritel(dev, 0, DMA_BASE_READ);
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if (dev->link[0].info->type != DDB_MOD)
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ddbwritel(dev, 0, DMA_BASE_WRITE);
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if (dev->link[0].info->type == DDB_MOD
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&& dev->link[0].info->version <= 1) {
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if (ddbreadl(dev, 0x1c) == 4)
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dev->link[0].info =
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get_ddb_info(0xdd01, 0x0201, 0xdd01, 0x0004);
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}
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if (dev->link[0].info->type == DDB_MOD
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&& dev->link[0].info->version == 2) {
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u32 lic = ddbreadl(dev, 0x1c) & 7;
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switch (lic) {
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case 0:
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dev->link[0].info =
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get_ddb_info(0xdd01, 0x0210, 0xdd01, 0x0000);
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break;
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case 1:
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dev->link[0].info =
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get_ddb_info(0xdd01, 0x0210, 0xdd01, 0x0003);
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break;
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case 3:
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dev->link[0].info =
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get_ddb_info(0xdd01, 0x0210, 0xdd01, 0x0002);
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break;
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default:
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break;
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}
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}
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stat = ddb_irq_init(dev);
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if (stat < 0)
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goto fail0;
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if (ddb_init(dev) == 0)
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return 0;
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ddb_irq_exit(dev);
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fail0:
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dev_err(dev->dev, "fail0\n");
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if (dev->msi)
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pci_disable_msi(dev->pdev);
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fail:
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dev_err(dev->dev, "fail\n");
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ddb_unmap(dev);
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pci_set_drvdata(pdev, NULL);
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pci_disable_device(pdev);
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return -1;
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}
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/****************************************************************************/
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/****************************************************************************/
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/****************************************************************************/
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#define DDB_DEVICE_ANY(_device) \
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{ PCI_DEVICE_SUB(0xdd01, _device, 0xdd01, PCI_ANY_ID) }
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static const struct pci_device_id ddb_id_table[] __devinitconst = {
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DDB_DEVICE_ANY(0x0002),
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DDB_DEVICE_ANY(0x0003),
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DDB_DEVICE_ANY(0x0005),
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DDB_DEVICE_ANY(0x0006),
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DDB_DEVICE_ANY(0x0007),
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DDB_DEVICE_ANY(0x0008),
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DDB_DEVICE_ANY(0x0011),
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DDB_DEVICE_ANY(0x0012),
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DDB_DEVICE_ANY(0x0013),
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DDB_DEVICE_ANY(0x0201),
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DDB_DEVICE_ANY(0x0203),
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DDB_DEVICE_ANY(0x0210),
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DDB_DEVICE_ANY(0x0220),
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DDB_DEVICE_ANY(0x0320),
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DDB_DEVICE_ANY(0x0321),
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DDB_DEVICE_ANY(0x0322),
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DDB_DEVICE_ANY(0x0323),
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DDB_DEVICE_ANY(0x0328),
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DDB_DEVICE_ANY(0x0329),
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{0}
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};
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MODULE_DEVICE_TABLE(pci, ddb_id_table);
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static struct pci_driver ddb_pci_driver = {
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.name = "ddbridge",
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.id_table = ddb_id_table,
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.probe = ddb_probe,
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.remove = ddb_remove,
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};
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static __init int module_init_ddbridge(void)
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{
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int stat = -1;
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pr_info("Digital Devices PCIE bridge driver "
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DDBRIDGE_VERSION
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", Copyright (C) 2010-17 Digital Devices GmbH\n");
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if (ddb_class_create() < 0)
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return -1;
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ddb_wq = create_workqueue("ddbridge");
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if (!ddb_wq)
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goto exit1;
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stat = pci_register_driver(&ddb_pci_driver);
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if (stat < 0)
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goto exit2;
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return stat;
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exit2:
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destroy_workqueue(ddb_wq);
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exit1:
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ddb_class_destroy();
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return stat;
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}
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static __exit void module_exit_ddbridge(void)
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{
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pci_unregister_driver(&ddb_pci_driver);
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destroy_workqueue(ddb_wq);
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ddb_class_destroy();
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}
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module_init(module_init_ddbridge);
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module_exit(module_exit_ddbridge);
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MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
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MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(DDBRIDGE_VERSION);
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