727 lines
15 KiB
C
727 lines
15 KiB
C
/*
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* cxd2099.c: Driver for the CXD2099AR Common Interface Controller
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*
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* Copyright (C) 2010-2013 Digital Devices GmbH
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 only, as published by the Free Software Foundation.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA
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* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/version.h>
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#include <linux/slab.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <linux/wait.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include "cxd2099.h"
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//#define BUFFER_MODE 1
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static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount);
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struct cxd {
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struct dvb_ca_en50221 en;
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struct i2c_adapter *i2c;
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struct cxd2099_cfg cfg;
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u8 regs[0x23];
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u8 lastaddress;
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u8 clk_reg_f;
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u8 clk_reg_b;
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int mode;
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int ready;
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int dr;
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int write_busy;
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int slot_stat;
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u8 amem[1024];
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int amem_read;
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int cammode;
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struct mutex lock;
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u8 rbuf[1028];
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u8 wbuf[1028];
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};
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static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
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u8 reg, u8 data)
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{
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u8 m[2] = {reg, data};
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struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};
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if (i2c_transfer(adapter, &msg, 1) != 1) {
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pr_err("Failed to write to I2C register %02x@%02x!\n",
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reg, adr);
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return -1;
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}
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return 0;
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}
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static int i2c_write(struct i2c_adapter *adapter, u8 adr,
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u8 *data, u16 len)
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{
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struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len};
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if (i2c_transfer(adapter, &msg, 1) != 1) {
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pr_err("Failed to write to I2C!\n");
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return -1;
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}
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return 0;
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}
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static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr,
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u8 reg, u8 *val)
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{
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struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
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.buf = ®, .len = 1},
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{.addr = adr, .flags = I2C_M_RD,
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.buf = val, .len = 1} };
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if (i2c_transfer(adapter, msgs, 2) != 2) {
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pr_err("error in i2c_read_reg\n");
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return -1;
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}
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return 0;
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}
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static int i2c_read(struct i2c_adapter *adapter, u8 adr,
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u8 reg, u8 *data, u16 n)
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{
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struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
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.buf = ®, .len = 1},
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{.addr = adr, .flags = I2C_M_RD,
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.buf = data, .len = n} };
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if (i2c_transfer(adapter, msgs, 2) != 2) {
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pr_err("error in i2c_read\n");
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return -1;
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}
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return 0;
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}
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static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
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{
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int status = 0;
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if (ci->lastaddress != adr)
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status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
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if (!status) {
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ci->lastaddress = adr;
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while (n) {
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int len = n;
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if (ci->cfg.max_i2c &&
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len > ci->cfg.max_i2c)
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len = ci->cfg.max_i2c;
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status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, len);
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if (status)
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return status;
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data += len;
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n -= len;
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}
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}
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return status;
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}
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static int read_reg(struct cxd *ci, u8 reg, u8 *val)
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{
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return read_block(ci, reg, val, 1);
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}
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static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
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{
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int status;
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u8 addr[3] = {2, address & 0xff, address >> 8};
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status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
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if (!status)
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status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
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return status;
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}
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static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
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{
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int status;
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u8 addr[3] = {2, address & 0xff, address >> 8};
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status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
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if (!status) {
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u8 buf[256] = {3};
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memcpy(buf + 1, data, n);
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status = i2c_write(ci->i2c, ci->cfg.adr, buf, n+1);
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}
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return status;
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}
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static int read_io(struct cxd *ci, u16 address, u8 *val)
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{
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int status;
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u8 addr[3] = {2, address & 0xff, address >> 8};
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status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
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if (!status)
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status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1);
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return status;
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}
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static int write_io(struct cxd *ci, u16 address, u8 val)
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{
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int status;
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u8 addr[3] = {2, address & 0xff, address >> 8};
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u8 buf[2] = {3, val};
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status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
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if (!status)
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status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2);
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return status;
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}
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#if 0
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static int read_io_data(struct cxd *ci, u8 *data, u16 n)
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{
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int status;
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u8 addr[3] = { 2, 0, 0 };
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status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
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if (!status)
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status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
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return 0;
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}
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static int write_io_data(struct cxd *ci, u8 *data, u16 n)
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{
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int status;
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u8 addr[3] = {2, 0, 0};
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status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
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if (!status) {
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u8 buf[256] = {3};
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memcpy(buf + 1, data, n);
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status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
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}
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return 0;
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}
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#endif
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static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
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{
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int status = 0;
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if (ci->lastaddress != reg)
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status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
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if (!status && reg >= 6 && reg <= 8 && mask != 0xff)
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status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]);
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ci->lastaddress = reg;
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ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
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if (!status)
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status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]);
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if (reg == 0x20)
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ci->regs[reg] &= 0x7f;
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return status;
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}
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static int write_reg(struct cxd *ci, u8 reg, u8 val)
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{
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return write_regm(ci, reg, val, 0xff);
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}
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#ifdef BUFFER_MODE
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static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
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{
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int status = 0;
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u8 *buf = ci->wbuf;
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if (ci->lastaddress != adr)
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status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
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if (status)
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return status;
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printk("write_block %d\n", n);
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ci->lastaddress = adr;
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buf[0] = 1;
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while (n) {
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int len = n;
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if (ci->cfg.max_i2c &&
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len + 1 > ci->cfg.max_i2c)
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len = ci->cfg.max_i2c - 1;
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printk("write %d\n", len);
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memcpy(buf + 1, data, len);
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status = i2c_write(ci->i2c, ci->cfg.adr, buf, len + 1);
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if (status)
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return status;
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n -= len;
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data += len;
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}
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return status;
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}
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#endif
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static void set_mode(struct cxd *ci, int mode)
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{
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if (mode == ci->mode)
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return;
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switch (mode) {
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case 0x00: /* IO mem */
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write_regm(ci, 0x06, 0x00, 0x07);
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break;
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case 0x01: /* ATT mem */
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write_regm(ci, 0x06, 0x02, 0x07);
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break;
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default:
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break;
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}
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ci->mode = mode;
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}
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static void cam_mode(struct cxd *ci, int mode)
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{
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u8 dummy;
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if (mode == ci->cammode)
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return;
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switch (mode) {
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case 0x00:
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write_regm(ci, 0x20, 0x80, 0x80);
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break;
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case 0x01:
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if (!ci->en.read_data)
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return;
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ci->write_busy = 0;
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pr_info("enable cam buffer mode\n");
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write_reg(ci, 0x0d, 0x00);
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write_reg(ci, 0x0e, 0x01);
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write_regm(ci, 0x08, 0x40, 0x40);
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read_reg(ci, 0x12, &dummy);
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write_regm(ci, 0x08, 0x80, 0x80);
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break;
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default:
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break;
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}
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ci->cammode = mode;
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}
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#define CHK_ERROR(s) if ((status = s)) break
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static int init(struct cxd *ci)
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{
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int status;
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mutex_lock(&ci->lock);
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ci->mode = -1;
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do {
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CHK_ERROR(write_reg(ci, 0x00, 0x00));
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CHK_ERROR(write_reg(ci, 0x01, 0x00));
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CHK_ERROR(write_reg(ci, 0x02, 0x10));
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CHK_ERROR(write_reg(ci, 0x03, 0x00));
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CHK_ERROR(write_reg(ci, 0x05, 0xFF));
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CHK_ERROR(write_reg(ci, 0x06, 0x1F));
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CHK_ERROR(write_reg(ci, 0x07, 0x1F));
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CHK_ERROR(write_reg(ci, 0x08, 0x28));
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CHK_ERROR(write_reg(ci, 0x14, 0x20));
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/* TOSTRT = 8, Mode B (gated clock), falling Edge,
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Serial, POL=HIGH, MSB */
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CHK_ERROR(write_reg(ci, 0x0A, 0xA7));
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CHK_ERROR(write_reg(ci, 0x0B, 0x33));
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CHK_ERROR(write_reg(ci, 0x0C, 0x33));
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CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F));
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CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b));
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CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F));
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CHK_ERROR(write_reg(ci, 0x17, ci->clk_reg_f));
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if (ci->cfg.clock_mode == 2) {
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/* bitrate*2^13/ 72000 */
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u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
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if (ci->cfg.polarity) {
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CHK_ERROR(write_reg(ci, 0x09, 0x6f));
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} else {
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CHK_ERROR(write_reg(ci, 0x09, 0x6d));
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}
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CHK_ERROR(write_reg(ci, 0x20, 0x08));
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CHK_ERROR(write_reg(ci, 0x21, (reg >> 8) & 0xff));
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CHK_ERROR(write_reg(ci, 0x22, reg & 0xff));
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} else if (ci->cfg.clock_mode == 1) {
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if (ci->cfg.polarity) {
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CHK_ERROR(write_reg(ci, 0x09, 0x6f)); /* D */
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} else {
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CHK_ERROR(write_reg(ci, 0x09, 0x6d));
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}
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CHK_ERROR(write_reg(ci, 0x20, 0x68));
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CHK_ERROR(write_reg(ci, 0x21, 0x00));
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CHK_ERROR(write_reg(ci, 0x22, 0x02));
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} else {
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if (ci->cfg.polarity) {
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CHK_ERROR(write_reg(ci, 0x09, 0x4f)); /* C */
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} else {
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CHK_ERROR(write_reg(ci, 0x09, 0x4d));
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}
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CHK_ERROR(write_reg(ci, 0x20, 0x28));
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CHK_ERROR(write_reg(ci, 0x21, 0x00));
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CHK_ERROR(write_reg(ci, 0x22, 0x07));
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}
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CHK_ERROR(write_regm(ci, 0x20, 0x80, 0x80));
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CHK_ERROR(write_regm(ci, 0x03, 0x02, 0x02));
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CHK_ERROR(write_reg(ci, 0x01, 0x04));
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CHK_ERROR(write_reg(ci, 0x00, 0x31));
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/* Put TS in bypass */
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CHK_ERROR(write_regm(ci, 0x09, 0x08, 0x08));
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ci->cammode = -1;
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cam_mode(ci, 0);
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} while (0);
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mutex_unlock(&ci->lock);
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return 0;
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}
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static int read_attribute_mem(struct dvb_ca_en50221 *ca,
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int slot, int address)
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{
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struct cxd *ci = ca->data;
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#if 0
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if (ci->amem_read) {
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if (address <= 0 || address > 1024)
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return -EIO;
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return ci->amem[address];
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}
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mutex_lock(&ci->lock);
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write_regm(ci, 0x06, 0x00, 0x05);
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read_pccard(ci, 0, &ci->amem[0], 128);
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read_pccard(ci, 128, &ci->amem[0], 128);
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read_pccard(ci, 256, &ci->amem[0], 128);
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read_pccard(ci, 384, &ci->amem[0], 128);
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write_regm(ci, 0x06, 0x05, 0x05);
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mutex_unlock(&ci->lock);
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return ci->amem[address];
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#else
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u8 val;
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mutex_lock(&ci->lock);
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set_mode(ci, 1);
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read_pccard(ci, address, &val, 1);
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mutex_unlock(&ci->lock);
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return val;
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#endif
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}
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static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
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int address, u8 value)
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{
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struct cxd *ci = ca->data;
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mutex_lock(&ci->lock);
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set_mode(ci, 1);
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write_pccard(ci, address, &value, 1);
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mutex_unlock(&ci->lock);
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return 0;
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}
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static int read_cam_control(struct dvb_ca_en50221 *ca,
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int slot, u8 address)
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{
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struct cxd *ci = ca->data;
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u8 val;
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mutex_lock(&ci->lock);
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set_mode(ci, 0);
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read_io(ci, address, &val);
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mutex_unlock(&ci->lock);
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return val;
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}
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static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
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u8 address, u8 value)
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{
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struct cxd *ci = ca->data;
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mutex_lock(&ci->lock);
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set_mode(ci, 0);
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write_io(ci, address, value);
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mutex_unlock(&ci->lock);
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return 0;
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}
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static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
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{
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struct cxd *ci = ca->data;
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if (ci->cammode)
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read_data(ca, slot, ci->rbuf, 0);
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mutex_lock(&ci->lock);
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#if 0
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write_reg(ci, 0x00, 0x21);
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write_reg(ci, 0x06, 0x1F);
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write_reg(ci, 0x00, 0x31);
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#else
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#if 0
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write_reg(ci, 0x06, 0x1F);
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write_reg(ci, 0x06, 0x2F);
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#else
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cam_mode(ci, 0);
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write_reg(ci, 0x00, 0x21);
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write_reg(ci, 0x06, 0x1F);
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/*msleep(300);*/
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write_reg(ci, 0x00, 0x31);
|
|
write_regm(ci, 0x20, 0x80, 0x80);
|
|
write_reg(ci, 0x03, 0x02);
|
|
ci->ready = 0;
|
|
#endif
|
|
#endif
|
|
ci->mode = -1;
|
|
{
|
|
int i;
|
|
#if 0
|
|
u8 val;
|
|
#endif
|
|
for (i = 0; i < 100; i++) {
|
|
msleep(20);
|
|
#if 0
|
|
read_reg(ci, 0x06, &val);
|
|
pr_info(KERN_INFO "%d:%02x\n", i, val);
|
|
if (!(val&0x10))
|
|
break;
|
|
#else
|
|
if (ci->ready)
|
|
break;
|
|
#endif
|
|
}
|
|
}
|
|
mutex_unlock(&ci->lock);
|
|
/* msleep(500); */
|
|
return 0;
|
|
}
|
|
|
|
static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
|
|
{
|
|
struct cxd *ci = ca->data;
|
|
|
|
pr_info("slot_shutdown\n");
|
|
if (ci->cammode)
|
|
read_data(ca, slot, ci->rbuf, 0);
|
|
mutex_lock(&ci->lock);
|
|
write_reg(ci, 0x00, 0x21);
|
|
write_reg(ci, 0x06, 0x1F);
|
|
msleep(300);
|
|
|
|
write_regm(ci, 0x09, 0x08, 0x08);
|
|
write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
|
|
write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
|
|
|
|
ci->mode = -1;
|
|
ci->write_busy = 0;
|
|
mutex_unlock(&ci->lock);
|
|
return 0;
|
|
}
|
|
|
|
static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
|
|
{
|
|
struct cxd *ci = ca->data;
|
|
|
|
mutex_lock(&ci->lock);
|
|
write_regm(ci, 0x09, 0x00, 0x08);
|
|
set_mode(ci, 0);
|
|
cam_mode(ci, 1);
|
|
mutex_unlock(&ci->lock);
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int campoll(struct cxd *ci)
|
|
{
|
|
u8 istat;
|
|
|
|
read_reg(ci, 0x04, &istat);
|
|
if (!istat)
|
|
return 0;
|
|
write_reg(ci, 0x05, istat);
|
|
|
|
if (istat & 0x40)
|
|
ci->dr = 1;
|
|
if (istat & 0x20)
|
|
ci->write_busy = 0;
|
|
if (istat & 2) {
|
|
u8 slotstat;
|
|
|
|
read_reg(ci, 0x01, &slotstat);
|
|
if (!(2 & slotstat)) {
|
|
if (!ci->slot_stat) {
|
|
ci->slot_stat |=
|
|
DVB_CA_EN50221_POLL_CAM_PRESENT;
|
|
write_regm(ci, 0x03, 0x08, 0x08);
|
|
}
|
|
|
|
} else {
|
|
if (ci->slot_stat) {
|
|
ci->slot_stat = 0;
|
|
write_regm(ci, 0x03, 0x00, 0x08);
|
|
pr_info("NO CAM\n");
|
|
ci->ready = 0;
|
|
}
|
|
}
|
|
if ((istat & 8) &&
|
|
(ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT)) {
|
|
ci->ready = 1;
|
|
ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
|
|
{
|
|
struct cxd *ci = ca->data;
|
|
u8 slotstat;
|
|
|
|
mutex_lock(&ci->lock);
|
|
campoll(ci);
|
|
read_reg(ci, 0x01, &slotstat);
|
|
mutex_unlock(&ci->lock);
|
|
|
|
return ci->slot_stat;
|
|
}
|
|
|
|
static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
|
|
{
|
|
struct cxd *ci = ca->data;
|
|
u8 msb, lsb;
|
|
u16 len;
|
|
|
|
mutex_lock(&ci->lock);
|
|
campoll(ci);
|
|
mutex_unlock(&ci->lock);
|
|
|
|
if (!ci->dr)
|
|
return 0;
|
|
|
|
mutex_lock(&ci->lock);
|
|
read_reg(ci, 0x0f, &msb);
|
|
read_reg(ci, 0x10, &lsb);
|
|
len = ((u16) msb << 8) | lsb;
|
|
if (len > ecount || len < 2) {
|
|
/* read it anyway or cxd may hang */
|
|
read_block(ci, 0x12, ci->rbuf, len);
|
|
mutex_unlock(&ci->lock);
|
|
return -EIO;
|
|
}
|
|
read_block(ci, 0x12, ebuf, len);
|
|
ci->dr = 0;
|
|
mutex_unlock(&ci->lock);
|
|
#if 0
|
|
pr_info("read_data %d\n", len);
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < len; i++)
|
|
pr_info("%02x ", ebuf[i]);
|
|
pr_info("\n");
|
|
}
|
|
#endif
|
|
return len;
|
|
}
|
|
|
|
#ifdef BUFFER_MODE
|
|
|
|
static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
|
|
{
|
|
struct cxd *ci = ca->data;
|
|
|
|
if (ci->write_busy)
|
|
return -EAGAIN;
|
|
mutex_lock(&ci->lock);
|
|
write_reg(ci, 0x0d, ecount >> 8);
|
|
write_reg(ci, 0x0e, ecount & 0xff);
|
|
write_block(ci, 0x11, ebuf, ecount);
|
|
ci->write_busy = 1;
|
|
mutex_unlock(&ci->lock);
|
|
return ecount;
|
|
}
|
|
#endif
|
|
|
|
static struct dvb_ca_en50221 en_templ = {
|
|
.read_attribute_mem = read_attribute_mem,
|
|
.write_attribute_mem = write_attribute_mem,
|
|
.read_cam_control = read_cam_control,
|
|
.write_cam_control = write_cam_control,
|
|
.slot_reset = slot_reset,
|
|
.slot_shutdown = slot_shutdown,
|
|
.slot_ts_enable = slot_ts_enable,
|
|
.poll_slot_status = poll_slot_status,
|
|
#ifdef BUFFER_MODE
|
|
.read_data = read_data,
|
|
.write_data = write_data,
|
|
#endif
|
|
};
|
|
|
|
struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
|
|
void *priv,
|
|
struct i2c_adapter *i2c)
|
|
{
|
|
struct cxd *ci = 0;
|
|
u8 val;
|
|
|
|
if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) {
|
|
pr_info("No CXD2099 detected at %02x\n", cfg->adr);
|
|
return 0;
|
|
}
|
|
|
|
ci = kzalloc(sizeof(struct cxd), GFP_KERNEL);
|
|
if (!ci)
|
|
return 0;
|
|
|
|
mutex_init(&ci->lock);
|
|
memcpy(&ci->cfg, cfg, sizeof(struct cxd2099_cfg));
|
|
ci->i2c = i2c;
|
|
ci->lastaddress = 0xff;
|
|
ci->clk_reg_b = 0x4a;
|
|
ci->clk_reg_f = 0x1b;
|
|
|
|
memcpy(&ci->en, &en_templ, sizeof(en_templ));
|
|
ci->en.data = ci;
|
|
init(ci);
|
|
pr_info("Attached CXD2099AR at %02x\n", ci->cfg.adr);
|
|
return &ci->en;
|
|
}
|
|
EXPORT_SYMBOL(cxd2099_attach);
|
|
|
|
MODULE_DESCRIPTION("cxd2099");
|
|
MODULE_AUTHOR("Ralph Metzler");
|
|
MODULE_LICENSE("GPL");
|