81 lines
3.1 KiB
Plaintext
81 lines
3.1 KiB
Plaintext
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README on the Vectored Interrupt Controller of the LH7A404
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==========================================================
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The 404 revision of the LH7A40X series comes with two vectored
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interrupts controllers. While the kernel does use some of the
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features of these devices, it is far from the purpose for which they
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were designed.
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When this README was written, the implementation of the VICs was in
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flux. It is possible that some details, especially with priorities,
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will change.
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The VIC support code is inspired by routines written by Sharp.
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Priority Control
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----------------
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The significant reason for using the VIC's vectoring is to control
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interrupt priorities. There are two tables in
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arch/arm/mach-lh7a40x/irq-lh7a404.c that look something like this.
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static unsigned char irq_pri_vic1[] = { IRQ_GPIO3INTR, };
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static unsigned char irq_pri_vic2[] = {
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IRQ_T3UI, IRQ_GPIO7INTR,
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IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR, };
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The initialization code reads these tables and inserts a vector
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address and enable for each indicated IRQ. Vectored interrupts have
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higher priority than non-vectored interrupts. So, on VIC1,
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IRQ_GPIO3INTR will be served before any other non-FIQ interrupt. Due
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to the way that the vectoring works, IRQ_T3UI is the next highest
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priority followed by the other vectored interrupts on VIC2. After
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that, the non-vectored interrupts are scanned in VIC1 then in VIC2.
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ISR
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---
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The interrupt service routine macro get_irqnr() in
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arch/arm/kernel/entry-armv.S scans the VICs for the next active
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interrupt. The vectoring makes this code somewhat larger than it was
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before using vectoring (refer to the LH7A400 implementation). In the
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case where an interrupt is vectored, the implementation will tend to
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be faster than the non-vectored version. However, the worst-case path
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is longer.
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It is worth noting that at present, there is no need to read
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VIC2_VECTADDR because the register appears to be shared between the
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controllers. The code is written such that if this changes, it ought
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to still work properly.
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Vector Addresses
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----------------
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The proper use of the vectoring hardware would jump to the ISR
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specified by the vectoring address. Linux isn't structured to take
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advantage of this feature, though it might be possible to change
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things to support it.
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In this implementation, the vectoring address is used to speed the
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search for the active IRQ. The address is coded such that the lowest
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6 bits store the IRQ number for vectored interrupts. These numbers
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correspond to the bits in the interrupt status registers. IRQ zero is
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the lowest interrupt bit in VIC1. IRQ 32 is the lowest interrupt bit
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in VIC2. Because zero is a valid IRQ number and because we cannot
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detect whether or not there is a valid vectoring address if that
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address is zero, the eigth bit (0x100) is set for vectored interrupts.
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The address for IRQ 0x18 (VIC2) is 0x118. Only the ninth bit is set
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for the default handler on VIC1 and only the tenth bit is set for the
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default handler on VIC2.
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In other words.
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0x000 - no active interrupt
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0x1ii - vectored interrupt 0xii
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0x2xx - unvectored interrupt on VIC1 (xx is don't care)
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0x4xx - unvectored interrupt on VIC2 (xx is don't care)
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