484 lines
13 KiB
C
484 lines
13 KiB
C
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/*
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* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX4_DEVICE_H
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#define MLX4_DEVICE_H
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#include <linux/pci.h>
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#include <linux/completion.h>
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#include <linux/radix-tree.h>
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#include <asm/atomic.h>
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enum {
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MLX4_FLAG_MSI_X = 1 << 0,
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MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
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};
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enum {
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MLX4_MAX_PORTS = 2
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};
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enum {
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MLX4_BOARD_ID_LEN = 64
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};
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enum {
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MLX4_DEV_CAP_FLAG_RC = 1 << 0,
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MLX4_DEV_CAP_FLAG_UC = 1 << 1,
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MLX4_DEV_CAP_FLAG_UD = 1 << 2,
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MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
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MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
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MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
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MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
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MLX4_DEV_CAP_FLAG_DPDP = 1 << 12,
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MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
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MLX4_DEV_CAP_FLAG_APM = 1 << 17,
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MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
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MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
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MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
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MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
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};
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enum {
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MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
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MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
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MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
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MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
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MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
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};
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enum mlx4_event {
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MLX4_EVENT_TYPE_COMP = 0x00,
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MLX4_EVENT_TYPE_PATH_MIG = 0x01,
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MLX4_EVENT_TYPE_COMM_EST = 0x02,
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MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
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MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
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MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
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MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
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MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
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MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
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MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
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MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
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MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
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MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
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MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
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MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
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MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
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MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
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MLX4_EVENT_TYPE_CMD = 0x0a
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};
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enum {
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MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
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MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
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};
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enum {
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MLX4_PERM_LOCAL_READ = 1 << 10,
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MLX4_PERM_LOCAL_WRITE = 1 << 11,
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MLX4_PERM_REMOTE_READ = 1 << 12,
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MLX4_PERM_REMOTE_WRITE = 1 << 13,
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MLX4_PERM_ATOMIC = 1 << 14
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};
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enum {
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MLX4_OPCODE_NOP = 0x00,
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MLX4_OPCODE_SEND_INVAL = 0x01,
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MLX4_OPCODE_RDMA_WRITE = 0x08,
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MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
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MLX4_OPCODE_SEND = 0x0a,
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MLX4_OPCODE_SEND_IMM = 0x0b,
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MLX4_OPCODE_LSO = 0x0e,
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MLX4_OPCODE_RDMA_READ = 0x10,
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MLX4_OPCODE_ATOMIC_CS = 0x11,
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MLX4_OPCODE_ATOMIC_FA = 0x12,
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MLX4_OPCODE_ATOMIC_MASK_CS = 0x14,
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MLX4_OPCODE_ATOMIC_MASK_FA = 0x15,
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MLX4_OPCODE_BIND_MW = 0x18,
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MLX4_OPCODE_FMR = 0x19,
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MLX4_OPCODE_LOCAL_INVAL = 0x1b,
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MLX4_OPCODE_CONFIG_CMD = 0x1f,
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MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
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MLX4_RECV_OPCODE_SEND = 0x01,
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MLX4_RECV_OPCODE_SEND_IMM = 0x02,
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MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
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MLX4_CQE_OPCODE_ERROR = 0x1e,
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MLX4_CQE_OPCODE_RESIZE = 0x16,
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};
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enum {
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MLX4_STAT_RATE_OFFSET = 5
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};
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enum {
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MLX4_MTT_FLAG_PRESENT = 1
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};
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enum mlx4_qp_region {
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MLX4_QP_REGION_FW = 0,
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MLX4_QP_REGION_ETH_ADDR,
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MLX4_QP_REGION_FC_ADDR,
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MLX4_QP_REGION_FC_EXCH,
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MLX4_NUM_QP_REGION
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};
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enum mlx4_port_type {
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MLX4_PORT_TYPE_IB = 1,
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MLX4_PORT_TYPE_ETH = 2,
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MLX4_PORT_TYPE_AUTO = 3
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};
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enum mlx4_special_vlan_idx {
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MLX4_NO_VLAN_IDX = 0,
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MLX4_VLAN_MISS_IDX,
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MLX4_VLAN_REGULAR
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};
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enum {
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MLX4_NUM_FEXCH = 64 * 1024,
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};
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static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
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{
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return (major << 32) | (minor << 16) | subminor;
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}
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struct mlx4_caps {
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u64 fw_ver;
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int num_ports;
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int vl_cap[MLX4_MAX_PORTS + 1];
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int ib_mtu_cap[MLX4_MAX_PORTS + 1];
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__be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
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u64 def_mac[MLX4_MAX_PORTS + 1];
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int eth_mtu_cap[MLX4_MAX_PORTS + 1];
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int gid_table_len[MLX4_MAX_PORTS + 1];
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int pkey_table_len[MLX4_MAX_PORTS + 1];
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int local_ca_ack_delay;
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int num_uars;
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int bf_reg_size;
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int bf_regs_per_page;
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int max_sq_sg;
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int max_rq_sg;
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int num_qps;
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int max_wqes;
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int max_sq_desc_sz;
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int max_rq_desc_sz;
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int max_qp_init_rdma;
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int max_qp_dest_rdma;
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int sqp_start;
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int num_srqs;
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int max_srq_wqes;
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int max_srq_sge;
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int reserved_srqs;
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int num_cqs;
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int max_cqes;
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int reserved_cqs;
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int num_eqs;
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int reserved_eqs;
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int num_comp_vectors;
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int num_mpts;
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int num_mtt_segs;
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int mtts_per_seg;
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int fmr_reserved_mtts;
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int reserved_mtts;
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int reserved_mrws;
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int reserved_uars;
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int num_mgms;
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int num_amgms;
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int reserved_mcgs;
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int num_qp_per_mgm;
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int num_pds;
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int reserved_pds;
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int mtt_entry_sz;
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u32 max_msg_sz;
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u32 page_size_cap;
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u32 flags;
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u32 bmme_flags;
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u32 reserved_lkey;
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u16 stat_rate_support;
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u8 port_width_cap[MLX4_MAX_PORTS + 1];
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int max_gso_sz;
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int reserved_qps_cnt[MLX4_NUM_QP_REGION];
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int reserved_qps;
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int reserved_qps_base[MLX4_NUM_QP_REGION];
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int log_num_macs;
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int log_num_vlans;
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int log_num_prios;
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enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
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u8 supported_type[MLX4_MAX_PORTS + 1];
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u32 port_mask;
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enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
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};
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struct mlx4_buf_list {
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void *buf;
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dma_addr_t map;
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};
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struct mlx4_buf {
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struct mlx4_buf_list direct;
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struct mlx4_buf_list *page_list;
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int nbufs;
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int npages;
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int page_shift;
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};
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struct mlx4_mtt {
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u32 first_seg;
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int order;
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int page_shift;
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};
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enum {
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MLX4_DB_PER_PAGE = PAGE_SIZE / 4
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};
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struct mlx4_db_pgdir {
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struct list_head list;
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DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
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DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
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unsigned long *bits[2];
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__be32 *db_page;
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dma_addr_t db_dma;
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};
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struct mlx4_ib_user_db_page;
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struct mlx4_db {
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__be32 *db;
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union {
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struct mlx4_db_pgdir *pgdir;
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struct mlx4_ib_user_db_page *user_page;
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} u;
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dma_addr_t dma;
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int index;
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int order;
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};
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struct mlx4_hwq_resources {
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struct mlx4_db db;
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struct mlx4_mtt mtt;
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struct mlx4_buf buf;
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};
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struct mlx4_mr {
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struct mlx4_mtt mtt;
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u64 iova;
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u64 size;
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u32 key;
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u32 pd;
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u32 access;
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int enabled;
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};
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struct mlx4_fmr {
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struct mlx4_mr mr;
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struct mlx4_mpt_entry *mpt;
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__be64 *mtts;
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dma_addr_t dma_handle;
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int max_pages;
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int max_maps;
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int maps;
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u8 page_shift;
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};
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struct mlx4_uar {
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unsigned long pfn;
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int index;
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};
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struct mlx4_cq {
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void (*comp) (struct mlx4_cq *);
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void (*event) (struct mlx4_cq *, enum mlx4_event);
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struct mlx4_uar *uar;
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u32 cons_index;
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__be32 *set_ci_db;
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__be32 *arm_db;
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int arm_sn;
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int cqn;
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unsigned vector;
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atomic_t refcount;
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struct completion free;
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};
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struct mlx4_qp {
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void (*event) (struct mlx4_qp *, enum mlx4_event);
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int qpn;
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atomic_t refcount;
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struct completion free;
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};
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struct mlx4_srq {
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void (*event) (struct mlx4_srq *, enum mlx4_event);
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int srqn;
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int max;
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int max_gs;
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int wqe_shift;
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atomic_t refcount;
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struct completion free;
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};
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struct mlx4_av {
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__be32 port_pd;
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u8 reserved1;
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u8 g_slid;
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__be16 dlid;
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||
|
|
u8 reserved2;
|
||
|
|
u8 gid_index;
|
||
|
|
u8 stat_rate;
|
||
|
|
u8 hop_limit;
|
||
|
|
__be32 sl_tclass_flowlabel;
|
||
|
|
u8 dgid[16];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct mlx4_dev {
|
||
|
|
struct pci_dev *pdev;
|
||
|
|
unsigned long flags;
|
||
|
|
struct mlx4_caps caps;
|
||
|
|
struct radix_tree_root qp_table_tree;
|
||
|
|
u32 rev_id;
|
||
|
|
char board_id[MLX4_BOARD_ID_LEN];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct mlx4_init_port_param {
|
||
|
|
int set_guid0;
|
||
|
|
int set_node_guid;
|
||
|
|
int set_si_guid;
|
||
|
|
u16 mtu;
|
||
|
|
int port_width_cap;
|
||
|
|
u16 vl_cap;
|
||
|
|
u16 max_gid;
|
||
|
|
u16 max_pkey;
|
||
|
|
u64 guid0;
|
||
|
|
u64 node_guid;
|
||
|
|
u64 si_guid;
|
||
|
|
};
|
||
|
|
|
||
|
|
#define mlx4_foreach_port(port, dev, type) \
|
||
|
|
for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
|
||
|
|
if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
|
||
|
|
~(dev)->caps.port_mask) & 1 << ((port) - 1))
|
||
|
|
|
||
|
|
int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
|
||
|
|
struct mlx4_buf *buf);
|
||
|
|
void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
|
||
|
|
static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
|
||
|
|
{
|
||
|
|
if (BITS_PER_LONG == 64 || buf->nbufs == 1)
|
||
|
|
return buf->direct.buf + offset;
|
||
|
|
else
|
||
|
|
return buf->page_list[offset >> PAGE_SHIFT].buf +
|
||
|
|
(offset & (PAGE_SIZE - 1));
|
||
|
|
}
|
||
|
|
|
||
|
|
int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
|
||
|
|
void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
|
||
|
|
|
||
|
|
int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
|
||
|
|
void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
|
||
|
|
|
||
|
|
int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
|
||
|
|
struct mlx4_mtt *mtt);
|
||
|
|
void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
|
||
|
|
u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
|
||
|
|
|
||
|
|
int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
|
||
|
|
int npages, int page_shift, struct mlx4_mr *mr);
|
||
|
|
void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
|
||
|
|
int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
|
||
|
|
int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
|
||
|
|
int start_index, int npages, u64 *page_list);
|
||
|
|
int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
|
||
|
|
struct mlx4_buf *buf);
|
||
|
|
|
||
|
|
int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
|
||
|
|
void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
|
||
|
|
|
||
|
|
int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
|
||
|
|
int size, int max_direct);
|
||
|
|
void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
|
||
|
|
int size);
|
||
|
|
|
||
|
|
int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
|
||
|
|
struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
|
||
|
|
unsigned vector, int collapsed);
|
||
|
|
void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
|
||
|
|
|
||
|
|
int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
|
||
|
|
void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
|
||
|
|
|
||
|
|
int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
|
||
|
|
void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
|
||
|
|
|
||
|
|
int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
|
||
|
|
u64 db_rec, struct mlx4_srq *srq);
|
||
|
|
void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
|
||
|
|
int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
|
||
|
|
int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
|
||
|
|
|
||
|
|
int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
|
||
|
|
int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
|
||
|
|
|
||
|
|
int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
|
||
|
|
int block_mcast_loopback);
|
||
|
|
int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
|
||
|
|
|
||
|
|
int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index);
|
||
|
|
void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);
|
||
|
|
|
||
|
|
int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
|
||
|
|
void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
|
||
|
|
|
||
|
|
int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
|
||
|
|
int npages, u64 iova, u32 *lkey, u32 *rkey);
|
||
|
|
int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
|
||
|
|
int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
|
||
|
|
int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
|
||
|
|
void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
|
||
|
|
u32 *lkey, u32 *rkey);
|
||
|
|
int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
|
||
|
|
int mlx4_SYNC_TPT(struct mlx4_dev *dev);
|
||
|
|
|
||
|
|
#endif /* MLX4_DEVICE_H */
|