86 lines
2.9 KiB
C
86 lines
2.9 KiB
C
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/*
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* Copyright (C) 2001 Mike Corrigan IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_POWERPC_ISERIES_LPAR_MAP_H
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#define _ASM_POWERPC_ISERIES_LPAR_MAP_H
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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#endif
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/*
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* The iSeries hypervisor will set up mapping for one or more
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* ESID/VSID pairs (in SLB/segment registers) and will set up
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* mappings of one or more ranges of pages to VAs.
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* We will have the hypervisor set up the ESID->VSID mapping
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* for the four kernel segments (C-F). With shared processors,
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* the hypervisor will clear all segment registers and reload
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* these four whenever the processor is switched from one
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* partition to another.
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*/
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/* The Vsid and Esid identified below will be used by the hypervisor
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* to set up a memory mapping for part of the load area before giving
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* control to the Linux kernel. The load area is 64 MB, but this must
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* not attempt to map the whole load area. The Hashed Page Table may
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* need to be located within the load area (if the total partition size
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* is 64 MB), but cannot be mapped. Typically, this should specify
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* to map half (32 MB) of the load area.
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*
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* The hypervisor will set up page table entries for the number of
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* pages specified.
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*
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* In 32-bit mode, the hypervisor will load all four of the
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* segment registers (identified by the low-order four bits of the
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* Esid field. In 64-bit mode, the hypervisor will load one SLB
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* entry to map the Esid to the Vsid.
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*/
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#define HvEsidsToMap 2
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#define HvRangesToMap 1
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/* Hypervisor initially maps 32MB of the load area */
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#define HvPagesToMap 8192
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#ifndef __ASSEMBLY__
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struct LparMap {
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u64 xNumberEsids; // Number of ESID/VSID pairs
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u64 xNumberRanges; // Number of VA ranges to map
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u64 xSegmentTableOffs; // Page number within load area of seg table
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u64 xRsvd[5];
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struct {
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u64 xKernelEsid; // Esid used to map kernel load
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u64 xKernelVsid; // Vsid used to map kernel load
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} xEsids[HvEsidsToMap];
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struct {
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u64 xPages; // Number of pages to be mapped
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u64 xOffset; // Offset from start of load area
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u64 xVPN; // Virtual Page Number
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} xRanges[HvRangesToMap];
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};
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extern const struct LparMap xLparMap;
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#endif /* __ASSEMBLY__ */
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/* the fixed address where the LparMap exists */
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#define LPARMAP_PHYS 0x7000
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#endif /* _ASM_POWERPC_ISERIES_LPAR_MAP_H */
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