333 lines
12 KiB
C
333 lines
12 KiB
C
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/*
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* Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
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* Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/*
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* Internal RX/TX descriptor structures
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* (rX: reserved fields possibily used by future versions of the ar5k chipset)
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*/
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/*
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* common hardware RX control descriptor
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*/
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struct ath5k_hw_rx_ctl {
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u32 rx_control_0; /* RX control word 0 */
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u32 rx_control_1; /* RX control word 1 */
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} __packed;
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/* RX control word 0 field/sflags */
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#define AR5K_DESC_RX_CTL0 0x00000000
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/* RX control word 1 fields/flags */
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#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff
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#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000
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/*
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* common hardware RX status descriptor
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* 5210/11 and 5212 differ only in the flags defined below
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*/
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struct ath5k_hw_rx_status {
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u32 rx_status_0; /* RX status word 0 */
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u32 rx_status_1; /* RX status word 1 */
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} __packed;
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/* 5210/5211 */
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/* RX status word 0 fields/flags */
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#define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff
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#define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S 15
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27
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/* RX status word 1 fields/flags */
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#define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001
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#define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
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#define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004
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#define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008
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#define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010
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#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0
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#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5
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#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
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#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00
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#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9
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#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000
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#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15
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#define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000
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/* 5212 */
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/* RX status word 0 fields/flags */
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#define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff
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#define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000
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#define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S 15
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28
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/* RX status word 1 fields/flags */
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#define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001
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#define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
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#define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004
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#define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008
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#define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010
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#define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020
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#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
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#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00
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#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S 9
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#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000
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#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16
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#define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000
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/*
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* common hardware RX error descriptor
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*/
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struct ath5k_hw_rx_error {
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u32 rx_error_0; /* RX status word 0 */
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u32 rx_error_1; /* RX status word 1 */
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} __packed;
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/* RX error word 0 fields/flags */
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#define AR5K_RX_DESC_ERROR0 0x00000000
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/* RX error word 1 fields/flags */
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#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00
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#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8
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/* PHY Error codes */
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#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00
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#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20
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#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40
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#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60
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#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80
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#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0
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#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0
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#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0
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/*
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* 5210/5211 hardware 2-word TX control descriptor
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*/
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struct ath5k_hw_2w_tx_ctl {
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u32 tx_control_0; /* TX control word 0 */
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u32 tx_control_1; /* TX control word 1 */
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} __packed;
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/* TX control word 0 fields/flags */
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#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
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#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/
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#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12
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#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000
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#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18
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#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000
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#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000
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#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/
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#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/
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#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/
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#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26
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#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000
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#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000
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#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT \
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(ah->ah_version == AR5K_AR5210 ? \
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AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \
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AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211)
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#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
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#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000
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#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
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/* TX control word 1 fields/flags */
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#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff
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#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000
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#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000
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#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000
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#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX \
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(ah->ah_version == AR5K_AR5210 ? \
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AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \
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AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211)
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#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13
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#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/
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#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20
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#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/
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#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/
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/* Frame types */
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#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00
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#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04
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#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08
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#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c
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#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10
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/*
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* 5212 hardware 4-word TX control descriptor
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*/
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struct ath5k_hw_4w_tx_ctl {
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u32 tx_control_0; /* TX control word 0 */
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#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
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#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000
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#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16
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#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000
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#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000
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#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000
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#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000
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#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
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#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000
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#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
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#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000
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u32 tx_control_1; /* TX control word 1 */
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#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff
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#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000
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#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000
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#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13
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#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000
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#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20
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#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000
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#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000
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#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25
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#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000
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#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27
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#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000
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#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29
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u32 tx_control_2; /* TX control word 2 */
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#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff
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#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000
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#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000
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#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16
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#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000
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#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20
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#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000
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#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24
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#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000
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#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28
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u32 tx_control_3; /* TX control word 3 */
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#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f
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#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0
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#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5
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#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00
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#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10
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#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000
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#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15
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#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000
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#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20
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} __packed;
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/*
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* Common TX status descriptor
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*/
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struct ath5k_hw_tx_status {
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u32 tx_status_0; /* TX status word 0 */
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u32 tx_status_1; /* TX status word 1 */
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} __packed;
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/* TX status word 0 fields/flags */
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#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001
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#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002
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#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004
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#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008
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/*???
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#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0
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#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4
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*/
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#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0
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#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4
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/*???
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#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00
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#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8
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*/
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#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00
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#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8
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#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000
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#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12
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#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000
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#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16
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/* TX status word 1 fields/flags */
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#define AR5K_DESC_TX_STATUS1_DONE 0x00000001
|
||
|
|
#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe
|
||
|
|
#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1
|
||
|
|
#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000
|
||
|
|
#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13
|
||
|
|
#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000
|
||
|
|
#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21
|
||
|
|
#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000
|
||
|
|
#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000
|
||
|
|
|
||
|
|
/*
|
||
|
|
* 5210/5211 hardware TX descriptor
|
||
|
|
*/
|
||
|
|
struct ath5k_hw_5210_tx_desc {
|
||
|
|
struct ath5k_hw_2w_tx_ctl tx_ctl;
|
||
|
|
struct ath5k_hw_tx_status tx_stat;
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* 5212 hardware TX descriptor
|
||
|
|
*/
|
||
|
|
struct ath5k_hw_5212_tx_desc {
|
||
|
|
struct ath5k_hw_4w_tx_ctl tx_ctl;
|
||
|
|
struct ath5k_hw_tx_status tx_stat;
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* common hardware RX descriptor
|
||
|
|
*/
|
||
|
|
struct ath5k_hw_all_rx_desc {
|
||
|
|
struct ath5k_hw_rx_ctl rx_ctl;
|
||
|
|
union {
|
||
|
|
struct ath5k_hw_rx_status rx_stat;
|
||
|
|
struct ath5k_hw_rx_error rx_err;
|
||
|
|
} u;
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Atheros hardware descriptor
|
||
|
|
* This is read and written to by the hardware
|
||
|
|
*/
|
||
|
|
struct ath5k_desc {
|
||
|
|
u32 ds_link; /* physical address of the next descriptor */
|
||
|
|
u32 ds_data; /* physical address of data buffer (skb) */
|
||
|
|
|
||
|
|
union {
|
||
|
|
struct ath5k_hw_5210_tx_desc ds_tx5210;
|
||
|
|
struct ath5k_hw_5212_tx_desc ds_tx5212;
|
||
|
|
struct ath5k_hw_all_rx_desc ds_rx;
|
||
|
|
} ud;
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
#define AR5K_RXDESC_INTREQ 0x0020
|
||
|
|
|
||
|
|
#define AR5K_TXDESC_CLRDMASK 0x0001
|
||
|
|
#define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/
|
||
|
|
#define AR5K_TXDESC_RTSENA 0x0004
|
||
|
|
#define AR5K_TXDESC_CTSENA 0x0008
|
||
|
|
#define AR5K_TXDESC_INTREQ 0x0010
|
||
|
|
#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/
|
||
|
|
|