487 lines
11 KiB
C
487 lines
11 KiB
C
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/*
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* IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
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*
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* Copyright 2007-2009 Analog Devices Inc.
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* Philippe Gerum <rpm@xenomai.org>
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*
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* Licensed under the GPL-2.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/cache.h>
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#include <linux/profile.h>
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#include <linux/errno.h>
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#include <linux/mm.h>
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#include <linux/cpu.h>
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#include <linux/smp.h>
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#include <linux/seq_file.h>
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#include <linux/irq.h>
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#include <asm/atomic.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/cpu.h>
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#include <asm/time.h>
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#include <linux/err.h>
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/*
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* Anomaly notes:
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* 05000120 - we always define corelock as 32-bit integer in L2
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*/
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struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
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void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
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*init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
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*init_saved_dcplb_fault_addr_coreb;
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cpumask_t cpu_possible_map;
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EXPORT_SYMBOL(cpu_possible_map);
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cpumask_t cpu_online_map;
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EXPORT_SYMBOL(cpu_online_map);
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#define BFIN_IPI_RESCHEDULE 0
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#define BFIN_IPI_CALL_FUNC 1
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#define BFIN_IPI_CPU_STOP 2
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struct blackfin_flush_data {
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unsigned long start;
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unsigned long end;
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};
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void *secondary_stack;
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struct smp_call_struct {
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void (*func)(void *info);
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void *info;
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int wait;
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cpumask_t pending;
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cpumask_t waitmask;
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};
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static struct blackfin_flush_data smp_flush_data;
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static DEFINE_SPINLOCK(stop_lock);
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struct ipi_message {
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struct list_head list;
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unsigned long type;
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struct smp_call_struct call_struct;
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};
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struct ipi_message_queue {
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struct list_head head;
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spinlock_t lock;
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unsigned long count;
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};
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static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
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static void ipi_cpu_stop(unsigned int cpu)
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{
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spin_lock(&stop_lock);
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printk(KERN_CRIT "CPU%u: stopping\n", cpu);
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dump_stack();
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spin_unlock(&stop_lock);
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cpu_clear(cpu, cpu_online_map);
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local_irq_disable();
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while (1)
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SSYNC();
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}
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static void ipi_flush_icache(void *info)
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{
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struct blackfin_flush_data *fdata = info;
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/* Invalidate the memory holding the bounds of the flushed region. */
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blackfin_dcache_invalidate_range((unsigned long)fdata,
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(unsigned long)fdata + sizeof(*fdata));
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blackfin_icache_flush_range(fdata->start, fdata->end);
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}
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static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
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{
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int wait;
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void (*func)(void *info);
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void *info;
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func = msg->call_struct.func;
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info = msg->call_struct.info;
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wait = msg->call_struct.wait;
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cpu_clear(cpu, msg->call_struct.pending);
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func(info);
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if (wait)
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cpu_clear(cpu, msg->call_struct.waitmask);
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else
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kfree(msg);
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}
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static irqreturn_t ipi_handler(int irq, void *dev_instance)
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{
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struct ipi_message *msg;
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struct ipi_message_queue *msg_queue;
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unsigned int cpu = smp_processor_id();
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platform_clear_ipi(cpu);
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msg_queue = &__get_cpu_var(ipi_msg_queue);
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msg_queue->count++;
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spin_lock(&msg_queue->lock);
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while (!list_empty(&msg_queue->head)) {
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msg = list_entry(msg_queue->head.next, typeof(*msg), list);
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list_del(&msg->list);
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switch (msg->type) {
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case BFIN_IPI_RESCHEDULE:
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/* That's the easiest one; leave it to
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* return_from_int. */
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kfree(msg);
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break;
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case BFIN_IPI_CALL_FUNC:
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spin_unlock(&msg_queue->lock);
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ipi_call_function(cpu, msg);
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spin_lock(&msg_queue->lock);
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break;
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case BFIN_IPI_CPU_STOP:
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spin_unlock(&msg_queue->lock);
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ipi_cpu_stop(cpu);
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spin_lock(&msg_queue->lock);
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kfree(msg);
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break;
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default:
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printk(KERN_CRIT "CPU%u: Unknown IPI message \
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0x%lx\n", cpu, msg->type);
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kfree(msg);
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break;
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}
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}
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spin_unlock(&msg_queue->lock);
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return IRQ_HANDLED;
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}
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static void ipi_queue_init(void)
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{
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unsigned int cpu;
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struct ipi_message_queue *msg_queue;
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for_each_possible_cpu(cpu) {
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msg_queue = &per_cpu(ipi_msg_queue, cpu);
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INIT_LIST_HEAD(&msg_queue->head);
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spin_lock_init(&msg_queue->lock);
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msg_queue->count = 0;
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}
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}
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int smp_call_function(void (*func)(void *info), void *info, int wait)
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{
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unsigned int cpu;
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cpumask_t callmap;
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unsigned long flags;
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struct ipi_message_queue *msg_queue;
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struct ipi_message *msg;
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callmap = cpu_online_map;
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cpu_clear(smp_processor_id(), callmap);
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if (cpus_empty(callmap))
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return 0;
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msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
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if (!msg)
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return -ENOMEM;
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INIT_LIST_HEAD(&msg->list);
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msg->call_struct.func = func;
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msg->call_struct.info = info;
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msg->call_struct.wait = wait;
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msg->call_struct.pending = callmap;
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msg->call_struct.waitmask = callmap;
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msg->type = BFIN_IPI_CALL_FUNC;
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for_each_cpu_mask(cpu, callmap) {
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msg_queue = &per_cpu(ipi_msg_queue, cpu);
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spin_lock_irqsave(&msg_queue->lock, flags);
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list_add_tail(&msg->list, &msg_queue->head);
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spin_unlock_irqrestore(&msg_queue->lock, flags);
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platform_send_ipi_cpu(cpu);
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}
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if (wait) {
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while (!cpus_empty(msg->call_struct.waitmask))
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blackfin_dcache_invalidate_range(
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(unsigned long)(&msg->call_struct.waitmask),
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(unsigned long)(&msg->call_struct.waitmask));
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kfree(msg);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(smp_call_function);
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int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
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int wait)
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{
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unsigned int cpu = cpuid;
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cpumask_t callmap;
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unsigned long flags;
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struct ipi_message_queue *msg_queue;
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struct ipi_message *msg;
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if (cpu_is_offline(cpu))
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return 0;
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cpus_clear(callmap);
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cpu_set(cpu, callmap);
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msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
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if (!msg)
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return -ENOMEM;
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INIT_LIST_HEAD(&msg->list);
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msg->call_struct.func = func;
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msg->call_struct.info = info;
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msg->call_struct.wait = wait;
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msg->call_struct.pending = callmap;
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msg->call_struct.waitmask = callmap;
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msg->type = BFIN_IPI_CALL_FUNC;
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msg_queue = &per_cpu(ipi_msg_queue, cpu);
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spin_lock_irqsave(&msg_queue->lock, flags);
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list_add_tail(&msg->list, &msg_queue->head);
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spin_unlock_irqrestore(&msg_queue->lock, flags);
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platform_send_ipi_cpu(cpu);
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if (wait) {
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while (!cpus_empty(msg->call_struct.waitmask))
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blackfin_dcache_invalidate_range(
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(unsigned long)(&msg->call_struct.waitmask),
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(unsigned long)(&msg->call_struct.waitmask));
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kfree(msg);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(smp_call_function_single);
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void smp_send_reschedule(int cpu)
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{
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unsigned long flags;
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struct ipi_message_queue *msg_queue;
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struct ipi_message *msg;
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if (cpu_is_offline(cpu))
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return;
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msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
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if (!msg)
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return;
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INIT_LIST_HEAD(&msg->list);
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msg->type = BFIN_IPI_RESCHEDULE;
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msg_queue = &per_cpu(ipi_msg_queue, cpu);
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spin_lock_irqsave(&msg_queue->lock, flags);
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list_add_tail(&msg->list, &msg_queue->head);
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spin_unlock_irqrestore(&msg_queue->lock, flags);
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platform_send_ipi_cpu(cpu);
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return;
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}
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void smp_send_stop(void)
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{
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unsigned int cpu;
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cpumask_t callmap;
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unsigned long flags;
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struct ipi_message_queue *msg_queue;
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struct ipi_message *msg;
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callmap = cpu_online_map;
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cpu_clear(smp_processor_id(), callmap);
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if (cpus_empty(callmap))
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return;
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msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
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if (!msg)
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return;
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INIT_LIST_HEAD(&msg->list);
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msg->type = BFIN_IPI_CPU_STOP;
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for_each_cpu_mask(cpu, callmap) {
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msg_queue = &per_cpu(ipi_msg_queue, cpu);
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spin_lock_irqsave(&msg_queue->lock, flags);
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list_add_tail(&msg->list, &msg_queue->head);
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spin_unlock_irqrestore(&msg_queue->lock, flags);
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platform_send_ipi_cpu(cpu);
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}
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return;
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}
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int __cpuinit __cpu_up(unsigned int cpu)
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{
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struct task_struct *idle;
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int ret;
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idle = fork_idle(cpu);
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if (IS_ERR(idle)) {
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printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
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return PTR_ERR(idle);
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}
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secondary_stack = task_stack_page(idle) + THREAD_SIZE;
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smp_wmb();
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ret = platform_boot_secondary(cpu, idle);
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if (ret) {
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cpu_clear(cpu, cpu_present_map);
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printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret);
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free_task(idle);
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} else
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cpu_set(cpu, cpu_online_map);
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secondary_stack = NULL;
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return ret;
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}
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static void __cpuinit setup_secondary(unsigned int cpu)
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{
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#if !defined(CONFIG_TICKSOURCE_GPTMR0)
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struct irq_desc *timer_desc;
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#endif
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unsigned long ilat;
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bfin_write_IMASK(0);
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CSYNC();
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ilat = bfin_read_ILAT();
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CSYNC();
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bfin_write_ILAT(ilat);
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CSYNC();
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/* Enable interrupt levels IVG7-15. IARs have been already
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* programmed by the boot CPU. */
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bfin_irq_flags |= IMASK_IVG15 |
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IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
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IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
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#if defined(CONFIG_TICKSOURCE_GPTMR0)
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/* Power down the core timer, just to play safe. */
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bfin_write_TCNTL(0);
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/* system timer0 has been setup by CoreA. */
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#else
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timer_desc = irq_desc + IRQ_CORETMR;
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setup_core_timer();
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timer_desc->chip->enable(IRQ_CORETMR);
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#endif
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}
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|
|
|
||
|
|
void __cpuinit secondary_start_kernel(void)
|
||
|
|
{
|
||
|
|
unsigned int cpu = smp_processor_id();
|
||
|
|
struct mm_struct *mm = &init_mm;
|
||
|
|
|
||
|
|
if (_bfin_swrst & SWRST_DBL_FAULT_B) {
|
||
|
|
printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
|
||
|
|
#ifdef CONFIG_DEBUG_DOUBLEFAULT
|
||
|
|
printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
|
||
|
|
(int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
|
||
|
|
printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
|
||
|
|
printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
|
||
|
|
#endif
|
||
|
|
printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
|
||
|
|
init_retx_coreb);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* We want the D-cache to be enabled early, in case the atomic
|
||
|
|
* support code emulates cache coherence (see
|
||
|
|
* __ARCH_SYNC_CORE_DCACHE).
|
||
|
|
*/
|
||
|
|
init_exception_vectors();
|
||
|
|
|
||
|
|
bfin_setup_caches(cpu);
|
||
|
|
|
||
|
|
local_irq_disable();
|
||
|
|
|
||
|
|
/* Attach the new idle task to the global mm. */
|
||
|
|
atomic_inc(&mm->mm_users);
|
||
|
|
atomic_inc(&mm->mm_count);
|
||
|
|
current->active_mm = mm;
|
||
|
|
BUG_ON(current->mm); /* Can't be, but better be safe than sorry. */
|
||
|
|
|
||
|
|
preempt_disable();
|
||
|
|
|
||
|
|
setup_secondary(cpu);
|
||
|
|
|
||
|
|
local_irq_enable();
|
||
|
|
|
||
|
|
platform_secondary_init(cpu);
|
||
|
|
|
||
|
|
cpu_idle();
|
||
|
|
}
|
||
|
|
|
||
|
|
void __init smp_prepare_boot_cpu(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
void __init smp_prepare_cpus(unsigned int max_cpus)
|
||
|
|
{
|
||
|
|
platform_prepare_cpus(max_cpus);
|
||
|
|
ipi_queue_init();
|
||
|
|
platform_request_ipi(&ipi_handler);
|
||
|
|
}
|
||
|
|
|
||
|
|
void __init smp_cpus_done(unsigned int max_cpus)
|
||
|
|
{
|
||
|
|
unsigned long bogosum = 0;
|
||
|
|
unsigned int cpu;
|
||
|
|
|
||
|
|
for_each_online_cpu(cpu)
|
||
|
|
bogosum += loops_per_jiffy;
|
||
|
|
|
||
|
|
printk(KERN_INFO "SMP: Total of %d processors activated "
|
||
|
|
"(%lu.%02lu BogoMIPS).\n",
|
||
|
|
num_online_cpus(),
|
||
|
|
bogosum / (500000/HZ),
|
||
|
|
(bogosum / (5000/HZ)) % 100);
|
||
|
|
}
|
||
|
|
|
||
|
|
void smp_icache_flush_range_others(unsigned long start, unsigned long end)
|
||
|
|
{
|
||
|
|
smp_flush_data.start = start;
|
||
|
|
smp_flush_data.end = end;
|
||
|
|
|
||
|
|
if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
|
||
|
|
printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
|
||
|
|
|
||
|
|
#ifdef __ARCH_SYNC_CORE_ICACHE
|
||
|
|
void resync_core_icache(void)
|
||
|
|
{
|
||
|
|
unsigned int cpu = get_cpu();
|
||
|
|
blackfin_invalidate_entire_icache();
|
||
|
|
++per_cpu(cpu_data, cpu).icache_invld_count;
|
||
|
|
put_cpu();
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(resync_core_icache);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||
|
|
unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
|
||
|
|
|
||
|
|
void resync_core_dcache(void)
|
||
|
|
{
|
||
|
|
unsigned int cpu = get_cpu();
|
||
|
|
blackfin_invalidate_entire_dcache();
|
||
|
|
++per_cpu(cpu_data, cpu).dcache_invld_count;
|
||
|
|
put_cpu();
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(resync_core_dcache);
|
||
|
|
#endif
|