324 lines
10 KiB
ArmAsm
324 lines
10 KiB
ArmAsm
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/*
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*
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* Optmized version of the standard do_csum() function
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*
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* Return: a 64bit quantity containing the 16bit Internet checksum
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*
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* Inputs:
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* in0: address of buffer to checksum (char *)
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* in1: length of the buffer (int)
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*
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* Copyright (C) 1999, 2001-2002 Hewlett-Packard Co
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* Stephane Eranian <eranian@hpl.hp.com>
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*
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* 02/04/22 Ken Chen <kenneth.w.chen@intel.com>
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* Data locality study on the checksum buffer.
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* More optimization cleanup - remove excessive stop bits.
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* 02/04/08 David Mosberger <davidm@hpl.hp.com>
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* More cleanup and tuning.
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* 01/04/18 Jun Nakajima <jun.nakajima@intel.com>
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* Clean up and optimize and the software pipeline, loading two
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* back-to-back 8-byte words per loop. Clean up the initialization
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* for the loop. Support the cases where load latency = 1 or 2.
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* Set CONFIG_IA64_LOAD_LATENCY to 1 or 2 (default).
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*/
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#include <asm/asmmacro.h>
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//
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// Theory of operations:
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// The goal is to go as quickly as possible to the point where
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// we can checksum 16 bytes/loop. Before reaching that point we must
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// take care of incorrect alignment of first byte.
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//
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// The code hereafter also takes care of the "tail" part of the buffer
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// before entering the core loop, if any. The checksum is a sum so it
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// allows us to commute operations. So we do the "head" and "tail"
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// first to finish at full speed in the body. Once we get the head and
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// tail values, we feed them into the pipeline, very handy initialization.
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//
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// Of course we deal with the special case where the whole buffer fits
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// into one 8 byte word. In this case we have only one entry in the pipeline.
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//
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// We use a (LOAD_LATENCY+2)-stage pipeline in the loop to account for
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// possible load latency and also to accommodate for head and tail.
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//
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// The end of the function deals with folding the checksum from 64bits
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// down to 16bits taking care of the carry.
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//
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// This version avoids synchronization in the core loop by also using a
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// pipeline for the accumulation of the checksum in resultx[] (x=1,2).
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//
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// wordx[] (x=1,2)
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// |---|
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// | | 0 : new value loaded in pipeline
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// |---|
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// | | - : in transit data
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// |---|
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// | | LOAD_LATENCY : current value to add to checksum
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// |---|
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// | | LOAD_LATENCY+1 : previous value added to checksum
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// |---| (previous iteration)
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//
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// resultx[] (x=1,2)
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// |---|
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// | | 0 : initial value
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// |---|
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// | | LOAD_LATENCY-1 : new checksum
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// |---|
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// | | LOAD_LATENCY : previous value of checksum
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// |---|
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// | | LOAD_LATENCY+1 : final checksum when out of the loop
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// |---|
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//
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//
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// See RFC1071 "Computing the Internet Checksum" for various techniques for
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// calculating the Internet checksum.
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//
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// NOT YET DONE:
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// - Maybe another algorithm which would take care of the folding at the
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// end in a different manner
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// - Work with people more knowledgeable than me on the network stack
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// to figure out if we could not split the function depending on the
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// type of packet or alignment we get. Like the ip_fast_csum() routine
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// where we know we have at least 20bytes worth of data to checksum.
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// - Do a better job of handling small packets.
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// - Note on prefetching: it was found that under various load, i.e. ftp read/write,
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// nfs read/write, the L1 cache hit rate is at 60% and L2 cache hit rate is at 99.8%
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// on the data that buffer points to (partly because the checksum is often preceded by
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// a copy_from_user()). This finding indiate that lfetch will not be beneficial since
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// the data is already in the cache.
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//
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#define saved_pfs r11
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#define hmask r16
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#define tmask r17
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#define first1 r18
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#define firstval r19
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#define firstoff r20
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#define last r21
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#define lastval r22
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#define lastoff r23
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#define saved_lc r24
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#define saved_pr r25
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#define tmp1 r26
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#define tmp2 r27
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#define tmp3 r28
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#define carry1 r29
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#define carry2 r30
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#define first2 r31
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#define buf in0
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#define len in1
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#define LOAD_LATENCY 2 // XXX fix me
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#if (LOAD_LATENCY != 1) && (LOAD_LATENCY != 2)
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# error "Only 1 or 2 is supported/tested for LOAD_LATENCY."
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#endif
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#define PIPE_DEPTH (LOAD_LATENCY+2)
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#define ELD p[LOAD_LATENCY] // end of load
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#define ELD_1 p[LOAD_LATENCY+1] // and next stage
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// unsigned long do_csum(unsigned char *buf,long len)
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GLOBAL_ENTRY(do_csum)
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.prologue
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.save ar.pfs, saved_pfs
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alloc saved_pfs=ar.pfs,2,16,0,16
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.rotr word1[4], word2[4],result1[LOAD_LATENCY+2],result2[LOAD_LATENCY+2]
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.rotp p[PIPE_DEPTH], pC1[2], pC2[2]
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mov ret0=r0 // in case we have zero length
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cmp.lt p0,p6=r0,len // check for zero length or negative (32bit len)
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;;
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add tmp1=buf,len // last byte's address
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.save pr, saved_pr
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mov saved_pr=pr // preserve predicates (rotation)
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(p6) br.ret.spnt.many rp // return if zero or negative length
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mov hmask=-1 // initialize head mask
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tbit.nz p15,p0=buf,0 // is buf an odd address?
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and first1=-8,buf // 8-byte align down address of first1 element
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and firstoff=7,buf // how many bytes off for first1 element
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mov tmask=-1 // initialize tail mask
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;;
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adds tmp2=-1,tmp1 // last-1
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and lastoff=7,tmp1 // how many bytes off for last element
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;;
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sub tmp1=8,lastoff // complement to lastoff
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and last=-8,tmp2 // address of word containing last byte
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;;
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sub tmp3=last,first1 // tmp3=distance from first1 to last
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.save ar.lc, saved_lc
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mov saved_lc=ar.lc // save lc
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cmp.eq p8,p9=last,first1 // everything fits in one word ?
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ld8 firstval=[first1],8 // load, ahead of time, "first1" word
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and tmp1=7, tmp1 // make sure that if tmp1==8 -> tmp1=0
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shl tmp2=firstoff,3 // number of bits
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;;
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(p9) ld8 lastval=[last] // load, ahead of time, "last" word, if needed
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shl tmp1=tmp1,3 // number of bits
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(p9) adds tmp3=-8,tmp3 // effectively loaded
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;;
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(p8) mov lastval=r0 // we don't need lastval if first1==last
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shl hmask=hmask,tmp2 // build head mask, mask off [0,first1off[
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shr.u tmask=tmask,tmp1 // build tail mask, mask off ]8,lastoff]
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;;
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.body
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#define count tmp3
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(p8) and hmask=hmask,tmask // apply tail mask to head mask if 1 word only
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(p9) and word2[0]=lastval,tmask // mask last it as appropriate
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shr.u count=count,3 // how many 8-byte?
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;;
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// If count is odd, finish this 8-byte word so that we can
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// load two back-to-back 8-byte words per loop thereafter.
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and word1[0]=firstval,hmask // and mask it as appropriate
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tbit.nz p10,p11=count,0 // if (count is odd)
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;;
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(p8) mov result1[0]=word1[0]
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(p9) add result1[0]=word1[0],word2[0]
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;;
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cmp.ltu p6,p0=result1[0],word1[0] // check the carry
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cmp.eq.or.andcm p8,p0=0,count // exit if zero 8-byte
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;;
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(p6) adds result1[0]=1,result1[0]
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(p8) br.cond.dptk .do_csum_exit // if (within an 8-byte word)
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(p11) br.cond.dptk .do_csum16 // if (count is even)
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// Here count is odd.
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ld8 word1[1]=[first1],8 // load an 8-byte word
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cmp.eq p9,p10=1,count // if (count == 1)
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adds count=-1,count // loaded an 8-byte word
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;;
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add result1[0]=result1[0],word1[1]
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;;
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cmp.ltu p6,p0=result1[0],word1[1]
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;;
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(p6) adds result1[0]=1,result1[0]
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(p9) br.cond.sptk .do_csum_exit // if (count == 1) exit
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// Fall through to caluculate the checksum, feeding result1[0] as
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// the initial value in result1[0].
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//
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// Calculate the checksum loading two 8-byte words per loop.
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//
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.do_csum16:
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add first2=8,first1
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shr.u count=count,1 // we do 16 bytes per loop
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;;
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adds count=-1,count
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mov carry1=r0
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mov carry2=r0
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brp.loop.imp 1f,2f
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;;
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mov ar.ec=PIPE_DEPTH
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mov ar.lc=count // set lc
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mov pr.rot=1<<16
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// result1[0] must be initialized in advance.
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mov result2[0]=r0
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;;
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.align 32
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1:
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(ELD_1) cmp.ltu pC1[0],p0=result1[LOAD_LATENCY],word1[LOAD_LATENCY+1]
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(pC1[1])adds carry1=1,carry1
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(ELD_1) cmp.ltu pC2[0],p0=result2[LOAD_LATENCY],word2[LOAD_LATENCY+1]
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(pC2[1])adds carry2=1,carry2
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(ELD) add result1[LOAD_LATENCY-1]=result1[LOAD_LATENCY],word1[LOAD_LATENCY]
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(ELD) add result2[LOAD_LATENCY-1]=result2[LOAD_LATENCY],word2[LOAD_LATENCY]
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2:
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(p[0]) ld8 word1[0]=[first1],16
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(p[0]) ld8 word2[0]=[first2],16
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br.ctop.sptk 1b
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;;
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// Since len is a 32-bit value, carry cannot be larger than a 64-bit value.
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(pC1[1])adds carry1=1,carry1 // since we miss the last one
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(pC2[1])adds carry2=1,carry2
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;;
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add result1[LOAD_LATENCY+1]=result1[LOAD_LATENCY+1],carry1
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add result2[LOAD_LATENCY+1]=result2[LOAD_LATENCY+1],carry2
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;;
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cmp.ltu p6,p0=result1[LOAD_LATENCY+1],carry1
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cmp.ltu p7,p0=result2[LOAD_LATENCY+1],carry2
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;;
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(p6) adds result1[LOAD_LATENCY+1]=1,result1[LOAD_LATENCY+1]
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(p7) adds result2[LOAD_LATENCY+1]=1,result2[LOAD_LATENCY+1]
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;;
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add result1[0]=result1[LOAD_LATENCY+1],result2[LOAD_LATENCY+1]
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;;
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cmp.ltu p6,p0=result1[0],result2[LOAD_LATENCY+1]
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;;
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(p6) adds result1[0]=1,result1[0]
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;;
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.do_csum_exit:
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//
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// now fold 64 into 16 bits taking care of carry
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// that's not very good because it has lots of sequentiality
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//
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mov tmp3=0xffff
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zxt4 tmp1=result1[0]
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shr.u tmp2=result1[0],32
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;;
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add result1[0]=tmp1,tmp2
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;;
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and tmp1=result1[0],tmp3
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shr.u tmp2=result1[0],16
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;;
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add result1[0]=tmp1,tmp2
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;;
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and tmp1=result1[0],tmp3
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shr.u tmp2=result1[0],16
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;;
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add result1[0]=tmp1,tmp2
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;;
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and tmp1=result1[0],tmp3
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shr.u tmp2=result1[0],16
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;;
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add ret0=tmp1,tmp2
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mov pr=saved_pr,0xffffffffffff0000
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;;
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// if buf was odd then swap bytes
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mov ar.pfs=saved_pfs // restore ar.ec
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(p15) mux1 ret0=ret0,@rev // reverse word
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;;
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mov ar.lc=saved_lc
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(p15) shr.u ret0=ret0,64-16 // + shift back to position = swap bytes
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br.ret.sptk.many rp
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// I (Jun Nakajima) wrote an equivalent code (see below), but it was
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// not much better than the original. So keep the original there so that
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// someone else can challenge.
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//
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// shr.u word1[0]=result1[0],32
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// zxt4 result1[0]=result1[0]
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// ;;
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// add result1[0]=result1[0],word1[0]
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// ;;
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// zxt2 result2[0]=result1[0]
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// extr.u word1[0]=result1[0],16,16
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// shr.u carry1=result1[0],32
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// ;;
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// add result2[0]=result2[0],word1[0]
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// ;;
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// add result2[0]=result2[0],carry1
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// ;;
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// extr.u ret0=result2[0],16,16
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// ;;
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// add ret0=ret0,result2[0]
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// ;;
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// zxt2 ret0=ret0
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// mov ar.pfs=saved_pfs // restore ar.ec
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// mov pr=saved_pr,0xffffffffffff0000
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// ;;
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// // if buf was odd then swap bytes
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// mov ar.lc=saved_lc
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//(p15) mux1 ret0=ret0,@rev // reverse word
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// ;;
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//(p15) shr.u ret0=ret0,64-16 // + shift back to position = swap bytes
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// br.ret.sptk.many rp
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END(do_csum)
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