277 lines
7.3 KiB
C
277 lines
7.3 KiB
C
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/* $Id: hscx.c,v 1.24.2.4 2004/01/24 20:47:23 keil Exp $
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*
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* HSCX specific routines
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*
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* Author Karsten Keil
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* Copyright by Karsten Keil <keil@isdn4linux.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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#include <linux/init.h>
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#include "hisax.h"
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#include "hscx.h"
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#include "isac.h"
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#include "isdnl1.h"
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#include <linux/interrupt.h>
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static char *HSCXVer[] =
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{"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
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"?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
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int
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HscxVersion(struct IsdnCardState *cs, char *s)
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{
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int verA, verB;
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verA = cs->BC_Read_Reg(cs, 0, HSCX_VSTR) & 0xf;
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verB = cs->BC_Read_Reg(cs, 1, HSCX_VSTR) & 0xf;
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printk(KERN_INFO "%s HSCX version A: %s B: %s\n", s,
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HSCXVer[verA], HSCXVer[verB]);
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if ((verA == 0) | (verA == 0xf) | (verB == 0) | (verB == 0xf))
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return (1);
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else
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return (0);
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}
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void
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modehscx(struct BCState *bcs, int mode, int bc)
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{
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struct IsdnCardState *cs = bcs->cs;
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int hscx = bcs->hw.hscx.hscx;
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if (cs->debug & L1_DEB_HSCX)
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debugl1(cs, "hscx %c mode %d ichan %d",
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'A' + hscx, mode, bc);
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bcs->mode = mode;
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bcs->channel = bc;
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cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF);
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cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF);
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cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF);
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cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0);
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cs->BC_Write_Reg(cs, hscx, HSCX_RLCR, 0x0);
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cs->BC_Write_Reg(cs, hscx, HSCX_CCR1,
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test_bit(HW_IPAC, &cs->HW_Flags) ? 0x82 : 0x85);
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cs->BC_Write_Reg(cs, hscx, HSCX_CCR2, 0x30);
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cs->BC_Write_Reg(cs, hscx, HSCX_XCCR, 7);
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cs->BC_Write_Reg(cs, hscx, HSCX_RCCR, 7);
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/* Switch IOM 1 SSI */
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if (test_bit(HW_IOM1, &cs->HW_Flags) && (hscx == 0))
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bc = 1 - bc;
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if (bc == 0) {
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cs->BC_Write_Reg(cs, hscx, HSCX_TSAX,
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test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0);
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cs->BC_Write_Reg(cs, hscx, HSCX_TSAR,
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test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0);
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} else {
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cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, bcs->hw.hscx.tsaxr1);
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cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, bcs->hw.hscx.tsaxr1);
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}
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switch (mode) {
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case (L1_MODE_NULL):
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cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, 0x1f);
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cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, 0x1f);
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cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x84);
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break;
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case (L1_MODE_TRANS):
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cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0xe4);
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break;
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case (L1_MODE_HDLC):
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cs->BC_Write_Reg(cs, hscx, HSCX_CCR1,
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test_bit(HW_IPAC, &cs->HW_Flags) ? 0x8a : 0x8d);
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cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x8c);
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break;
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}
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if (mode)
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cs->BC_Write_Reg(cs, hscx, HSCX_CMDR, 0x41);
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cs->BC_Write_Reg(cs, hscx, HSCX_ISTA, 0x00);
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}
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void
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hscx_l2l1(struct PStack *st, int pr, void *arg)
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{
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struct BCState *bcs = st->l1.bcs;
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u_long flags;
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struct sk_buff *skb = arg;
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switch (pr) {
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case (PH_DATA | REQUEST):
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spin_lock_irqsave(&bcs->cs->lock, flags);
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if (bcs->tx_skb) {
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skb_queue_tail(&bcs->squeue, skb);
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} else {
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bcs->tx_skb = skb;
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test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
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bcs->hw.hscx.count = 0;
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bcs->cs->BC_Send_Data(bcs);
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}
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spin_unlock_irqrestore(&bcs->cs->lock, flags);
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break;
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case (PH_PULL | INDICATION):
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spin_lock_irqsave(&bcs->cs->lock, flags);
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if (bcs->tx_skb) {
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printk(KERN_WARNING "hscx_l2l1: this shouldn't happen\n");
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} else {
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test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
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bcs->tx_skb = skb;
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bcs->hw.hscx.count = 0;
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bcs->cs->BC_Send_Data(bcs);
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}
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spin_unlock_irqrestore(&bcs->cs->lock, flags);
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break;
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case (PH_PULL | REQUEST):
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if (!bcs->tx_skb) {
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test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
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st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
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} else
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test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
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break;
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case (PH_ACTIVATE | REQUEST):
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spin_lock_irqsave(&bcs->cs->lock, flags);
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test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
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modehscx(bcs, st->l1.mode, st->l1.bc);
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spin_unlock_irqrestore(&bcs->cs->lock, flags);
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l1_msg_b(st, pr, arg);
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break;
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case (PH_DEACTIVATE | REQUEST):
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l1_msg_b(st, pr, arg);
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break;
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case (PH_DEACTIVATE | CONFIRM):
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spin_lock_irqsave(&bcs->cs->lock, flags);
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test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
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test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
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modehscx(bcs, 0, st->l1.bc);
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spin_unlock_irqrestore(&bcs->cs->lock, flags);
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st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
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break;
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}
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}
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static void
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close_hscxstate(struct BCState *bcs)
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{
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modehscx(bcs, 0, bcs->channel);
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if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
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kfree(bcs->hw.hscx.rcvbuf);
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bcs->hw.hscx.rcvbuf = NULL;
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kfree(bcs->blog);
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bcs->blog = NULL;
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skb_queue_purge(&bcs->rqueue);
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skb_queue_purge(&bcs->squeue);
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if (bcs->tx_skb) {
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dev_kfree_skb_any(bcs->tx_skb);
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bcs->tx_skb = NULL;
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test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
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}
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}
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}
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int
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open_hscxstate(struct IsdnCardState *cs, struct BCState *bcs)
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{
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if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
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if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
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printk(KERN_WARNING
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"HiSax: No memory for hscx.rcvbuf\n");
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test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
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return (1);
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}
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if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
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printk(KERN_WARNING
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"HiSax: No memory for bcs->blog\n");
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test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
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kfree(bcs->hw.hscx.rcvbuf);
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bcs->hw.hscx.rcvbuf = NULL;
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return (2);
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}
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skb_queue_head_init(&bcs->rqueue);
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skb_queue_head_init(&bcs->squeue);
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}
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bcs->tx_skb = NULL;
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test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
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bcs->event = 0;
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bcs->hw.hscx.rcvidx = 0;
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bcs->tx_cnt = 0;
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return (0);
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}
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static int
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setstack_hscx(struct PStack *st, struct BCState *bcs)
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{
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bcs->channel = st->l1.bc;
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if (open_hscxstate(st->l1.hardware, bcs))
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return (-1);
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st->l1.bcs = bcs;
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st->l2.l2l1 = hscx_l2l1;
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setstack_manager(st);
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bcs->st = st;
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setstack_l1_B(st);
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return (0);
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}
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void
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clear_pending_hscx_ints(struct IsdnCardState *cs)
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{
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int val, eval;
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val = cs->BC_Read_Reg(cs, 1, HSCX_ISTA);
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debugl1(cs, "HSCX B ISTA %x", val);
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if (val & 0x01) {
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eval = cs->BC_Read_Reg(cs, 1, HSCX_EXIR);
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debugl1(cs, "HSCX B EXIR %x", eval);
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}
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if (val & 0x02) {
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eval = cs->BC_Read_Reg(cs, 0, HSCX_EXIR);
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debugl1(cs, "HSCX A EXIR %x", eval);
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}
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val = cs->BC_Read_Reg(cs, 0, HSCX_ISTA);
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debugl1(cs, "HSCX A ISTA %x", val);
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val = cs->BC_Read_Reg(cs, 1, HSCX_STAR);
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debugl1(cs, "HSCX B STAR %x", val);
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val = cs->BC_Read_Reg(cs, 0, HSCX_STAR);
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debugl1(cs, "HSCX A STAR %x", val);
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/* disable all IRQ */
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cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0xFF);
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cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0xFF);
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}
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void
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inithscx(struct IsdnCardState *cs)
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{
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cs->bcs[0].BC_SetStack = setstack_hscx;
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cs->bcs[1].BC_SetStack = setstack_hscx;
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cs->bcs[0].BC_Close = close_hscxstate;
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cs->bcs[1].BC_Close = close_hscxstate;
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cs->bcs[0].hw.hscx.hscx = 0;
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cs->bcs[1].hw.hscx.hscx = 1;
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cs->bcs[0].hw.hscx.tsaxr0 = 0x2f;
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cs->bcs[0].hw.hscx.tsaxr1 = 3;
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cs->bcs[1].hw.hscx.tsaxr0 = 0x2f;
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cs->bcs[1].hw.hscx.tsaxr1 = 3;
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modehscx(cs->bcs, 0, 0);
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modehscx(cs->bcs + 1, 0, 0);
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}
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void
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inithscxisac(struct IsdnCardState *cs, int part)
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{
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if (part & 1) {
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clear_pending_isac_ints(cs);
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clear_pending_hscx_ints(cs);
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initisac(cs);
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inithscx(cs);
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}
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if (part & 2) {
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/* Reenable all IRQ */
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cs->writeisac(cs, ISAC_MASK, 0);
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cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0);
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cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0);
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/* RESET Receiver and Transmitter */
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cs->writeisac(cs, ISAC_CMDR, 0x41);
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}
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}
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