818 lines
23 KiB
Plaintext
818 lines
23 KiB
Plaintext
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PVR350 Video decoder registers 0x02002800 -> 0x02002B00
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=======================================================
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This list has been worked out through trial and error. There will be mistakes
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and omissions. Some registers have no obvious effect so it's hard to say what
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they do, while others interact with each other, or require a certain load
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sequence. Horizontal filter setup is one example, with six registers working
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in unison and requiring a certain load sequence to correctly configure. The
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indexed colour palette is much easier to set at just two registers, but again
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it requires a certain load sequence.
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Some registers are fussy about what they are set to. Load in a bad value & the
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decoder will fail. A firmware reload will often recover, but sometimes a reset
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is required. For registers containing size information, setting them to 0 is
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generally a bad idea. For other control registers i.e. 2878, you'll only find
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out what values are bad when it hangs.
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--------------------------------------------------------------------------------
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2800
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bit 0
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Decoder enable
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0 = disable
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1 = enable
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--------------------------------------------------------------------------------
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2804
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bits 0:31
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Decoder horizontal Y alias register 1
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---------------
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2808
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bits 0:31
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Decoder horizontal Y alias register 2
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---------------
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280C
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bits 0:31
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Decoder horizontal Y alias register 3
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---------------
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2810
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bits 0:31
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Decoder horizontal Y alias register 4
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---------------
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2814
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bits 0:31
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Decoder horizontal Y alias register 5
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---------------
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2818
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bits 0:31
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Decoder horizontal Y alias trigger
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These six registers control the horizontal aliasing filter for the Y plane.
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The first five registers must all be loaded before accessing the trigger
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(2818), as this register actually clocks the data through for the first
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five.
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To correctly program set the filter, this whole procedure must be done 16
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times. The actual register contents are copied from a lookup-table in the
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firmware which contains 4 different filter settings.
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--------------------------------------------------------------------------------
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281C
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bits 0:31
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Decoder horizontal UV alias register 1
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---------------
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2820
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bits 0:31
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Decoder horizontal UV alias register 2
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---------------
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2824
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bits 0:31
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Decoder horizontal UV alias register 3
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---------------
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2828
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bits 0:31
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Decoder horizontal UV alias register 4
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---------------
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282C
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bits 0:31
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Decoder horizontal UV alias register 5
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---------------
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2830
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bits 0:31
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Decoder horizontal UV alias trigger
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These six registers control the horizontal aliasing for the UV plane.
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Operation is the same as the Y filter, with 2830 being the trigger
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register.
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--------------------------------------------------------------------------------
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2834
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bits 0:15
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Decoder Y source width in pixels
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bits 16:31
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Decoder Y destination width in pixels
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---------------
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2838
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bits 0:15
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Decoder UV source width in pixels
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bits 16:31
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Decoder UV destination width in pixels
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NOTE: For both registers, the resulting image must be fully visible on
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screen. If the image exceeds the right edge both the source and destination
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size must be adjusted to reflect the visible portion. For the source width,
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you must take into account the scaling when calculating the new value.
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--------------------------------------------------------------------------------
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283C
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bits 0:31
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Decoder Y horizontal scaling
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Normally = Reg 2854 >> 2
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---------------
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2840
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bits 0:31
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Decoder ?? unknown - horizontal scaling
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Usually 0x00080514
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---------------
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2844
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bits 0:31
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Decoder UV horizontal scaling
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Normally = Reg 2854 >> 2
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---------------
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2848
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bits 0:31
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Decoder ?? unknown - horizontal scaling
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Usually 0x00100514
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---------------
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284C
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bits 0:31
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Decoder ?? unknown - Y plane
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Usually 0x00200020
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---------------
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2850
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bits 0:31
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Decoder ?? unknown - UV plane
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Usually 0x00200020
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---------------
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2854
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bits 0:31
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Decoder 'master' value for horizontal scaling
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---------------
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2858
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bits 0:31
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Decoder ?? unknown
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Usually 0
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---------------
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285C
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bits 0:31
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Decoder ?? unknown
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Normally = Reg 2854 >> 1
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---------------
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2860
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bits 0:31
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Decoder ?? unknown
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Usually 0
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---------------
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2864
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bits 0:31
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Decoder ?? unknown
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Normally = Reg 2854 >> 1
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---------------
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2868
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bits 0:31
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Decoder ?? unknown
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Usually 0
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Most of these registers either control horizontal scaling, or appear linked
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to it in some way. Register 2854 contains the 'master' value & the other
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registers can be calculated from that one. You must also remember to
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correctly set the divider in Reg 2874.
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To enlarge:
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Reg 2854 = (source_width * 0x00200000) / destination_width
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Reg 2874 = No divide
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To reduce from full size down to half size:
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Reg 2854 = (source_width/2 * 0x00200000) / destination width
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Reg 2874 = Divide by 2
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To reduce from half size down to quarter size:
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Reg 2854 = (source_width/4 * 0x00200000) / destination width
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Reg 2874 = Divide by 4
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The result is always rounded up.
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--------------------------------------------------------------------------------
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286C
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bits 0:15
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Decoder horizontal Y buffer offset
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bits 15:31
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Decoder horizontal UV buffer offset
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Offset into the video image buffer. If the offset is gradually incremented,
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the on screen image will move left & wrap around higher up on the right.
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--------------------------------------------------------------------------------
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2870
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bits 0:15
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Decoder horizontal Y output offset
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bits 16:31
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Decoder horizontal UV output offset
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Offsets the actual video output. Controls output alignment of the Y & UV
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planes. The higher the value, the greater the shift to the left. Use
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reg 2890 to move the image right.
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--------------------------------------------------------------------------------
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2874
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bits 0:1
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Decoder horizontal Y output size divider
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00 = No divide
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01 = Divide by 2
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10 = Divide by 3
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bits 4:5
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Decoder horizontal UV output size divider
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00 = No divide
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01 = Divide by 2
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10 = Divide by 3
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bit 8
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Decoder ?? unknown
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0 = Normal
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1 = Affects video output levels
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bit 16
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Decoder ?? unknown
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0 = Normal
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1 = Disable horizontal filter
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--------------------------------------------------------------------------------
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2878
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bit 0
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?? unknown
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bit 1
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osd on/off
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0 = osd off
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1 = osd on
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bit 2
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Decoder + osd video timing
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0 = NTSC
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1 = PAL
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bits 3:4
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?? unknown
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bit 5
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Decoder + osd
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Swaps upper & lower fields
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--------------------------------------------------------------------------------
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287C
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bits 0:10
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Decoder & osd ?? unknown
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Moves entire screen horizontally. Starts at 0x005 with the screen
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shifted heavily to the right. Incrementing in steps of 0x004 will
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gradually shift the screen to the left.
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bits 11:31
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?? unknown
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Normally contents are 0x00101111 (NTSC) or 0x1010111d (PAL)
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--------------------------------------------------------------------------------
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2880 -------- ?? unknown
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2884 -------- ?? unknown
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--------------------------------------------------------------------------------
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2888
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bit 0
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Decoder + osd ?? unknown
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0 = Normal
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1 = Misaligned fields (Correctable through 289C & 28A4)
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bit 4
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?? unknown
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bit 8
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?? unknown
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Warning: Bad values will require a firmware reload to recover.
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Known to be bad are 0x000,0x011,0x100,0x111
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--------------------------------------------------------------------------------
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288C
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bits 0:15
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osd ?? unknown
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Appears to affect the osd position stability. The higher the value the
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more unstable it becomes. Decoder output remains stable.
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bits 16:31
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osd ?? unknown
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Same as bits 0:15
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--------------------------------------------------------------------------------
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2890
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bits 0:11
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Decoder output horizontal offset.
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Horizontal offset moves the video image right. A small left shift is
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possible, but it's better to use reg 2870 for that due to its greater
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range.
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NOTE: Video corruption will occur if video window is shifted off the right
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edge. To avoid this read the notes for 2834 & 2838.
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--------------------------------------------------------------------------------
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2894
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bits 0:23
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Decoder output video surround colour.
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Contains the colour (in yuv) used to fill the screen when the video is
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running in a window.
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--------------------------------------------------------------------------------
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2898
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bits 0:23
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Decoder video window colour
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Contains the colour (in yuv) used to fill the video window when the
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video is turned off.
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bit 24
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Decoder video output
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0 = Video on
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1 = Video off
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bit 28
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Decoder plane order
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0 = Y,UV
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1 = UV,Y
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bit 29
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Decoder second plane byte order
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0 = Normal (UV)
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1 = Swapped (VU)
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In normal usage, the first plane is Y & the second plane is UV. Though the
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order of the planes can be swapped, only the byte order of the second plane
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can be swapped. This isn't much use for the Y plane, but can be useful for
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the UV plane.
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--------------------------------------------------------------------------------
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289C
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bits 0:15
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Decoder vertical field offset 1
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bits 16:31
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Decoder vertical field offset 2
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Controls field output vertical alignment. The higher the number, the lower
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the image on screen. Known starting values are 0x011E0017 (NTSC) &
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0x01500017 (PAL)
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--------------------------------------------------------------------------------
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28A0
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bits 0:15
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Decoder & osd width in pixels
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bits 16:31
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Decoder & osd height in pixels
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All output from the decoder & osd are disabled beyond this area. Decoder
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output will simply go black outside of this region. If the osd tries to
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exceed this area it will become corrupt.
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--------------------------------------------------------------------------------
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28A4
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bits 0:11
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osd left shift.
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Has a range of 0x770->0x7FF. With the exception of 0, any value outside of
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this range corrupts the osd.
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--------------------------------------------------------------------------------
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28A8
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bits 0:15
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osd vertical field offset 1
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bits 16:31
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osd vertical field offset 2
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Controls field output vertical alignment. The higher the number, the lower
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the image on screen. Known starting values are 0x011E0017 (NTSC) &
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0x01500017 (PAL)
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--------------------------------------------------------------------------------
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28AC -------- ?? unknown
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V
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28BC -------- ?? unknown
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--------------------------------------------------------------------------------
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28C0
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bit 0
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Current output field
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0 = first field
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1 = second field
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bits 16:31
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Current scanline
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The scanline counts from the top line of the first field
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through to the last line of the second field.
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--------------------------------------------------------------------------------
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28C4 -------- ?? unknown
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V
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28F8 -------- ?? unknown
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--------------------------------------------------------------------------------
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28FC
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bit 0
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?? unknown
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0 = Normal
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1 = Breaks decoder & osd output
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--------------------------------------------------------------------------------
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2900
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bits 0:31
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Decoder vertical Y alias register 1
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---------------
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2904
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bits 0:31
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Decoder vertical Y alias register 2
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---------------
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2908
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bits 0:31
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Decoder vertical Y alias trigger
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These three registers control the vertical aliasing filter for the Y plane.
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Operation is similar to the horizontal Y filter (2804). The only real
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difference is that there are only two registers to set before accessing
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the trigger register (2908). As for the horizontal filter, the values are
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taken from a lookup table in the firmware, and the procedure must be
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repeated 16 times to fully program the filter.
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--------------------------------------------------------------------------------
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290C
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bits 0:31
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Decoder vertical UV alias register 1
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---------------
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2910
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bits 0:31
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Decoder vertical UV alias register 2
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---------------
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2914
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bits 0:31
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|
|
Decoder vertical UV alias trigger
|
||
|
|
|
||
|
|
These three registers control the vertical aliasing filter for the UV
|
||
|
|
plane. Operation is the same as the Y filter, with 2914 being the trigger.
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2918
|
||
|
|
bits 0:15
|
||
|
|
Decoder Y source height in pixels
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
Decoder Y destination height in pixels
|
||
|
|
---------------
|
||
|
|
291C
|
||
|
|
bits 0:15
|
||
|
|
Decoder UV source height in pixels divided by 2
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
Decoder UV destination height in pixels
|
||
|
|
|
||
|
|
NOTE: For both registers, the resulting image must be fully visible on
|
||
|
|
screen. If the image exceeds the bottom edge both the source and
|
||
|
|
destination size must be adjusted to reflect the visible portion. For the
|
||
|
|
source height, you must take into account the scaling when calculating the
|
||
|
|
new value.
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2920
|
||
|
|
bits 0:31
|
||
|
|
Decoder Y vertical scaling
|
||
|
|
Normally = Reg 2930 >> 2
|
||
|
|
---------------
|
||
|
|
2924
|
||
|
|
bits 0:31
|
||
|
|
Decoder Y vertical scaling
|
||
|
|
Normally = Reg 2920 + 0x514
|
||
|
|
---------------
|
||
|
|
2928
|
||
|
|
bits 0:31
|
||
|
|
Decoder UV vertical scaling
|
||
|
|
When enlarging = Reg 2930 >> 2
|
||
|
|
When reducing = Reg 2930 >> 3
|
||
|
|
---------------
|
||
|
|
292C
|
||
|
|
bits 0:31
|
||
|
|
Decoder UV vertical scaling
|
||
|
|
Normally = Reg 2928 + 0x514
|
||
|
|
---------------
|
||
|
|
2930
|
||
|
|
bits 0:31
|
||
|
|
Decoder 'master' value for vertical scaling
|
||
|
|
---------------
|
||
|
|
2934
|
||
|
|
bits 0:31
|
||
|
|
Decoder ?? unknown - Y vertical scaling
|
||
|
|
---------------
|
||
|
|
2938
|
||
|
|
bits 0:31
|
||
|
|
Decoder Y vertical scaling
|
||
|
|
Normally = Reg 2930
|
||
|
|
---------------
|
||
|
|
293C
|
||
|
|
bits 0:31
|
||
|
|
Decoder ?? unknown - Y vertical scaling
|
||
|
|
---------------
|
||
|
|
2940
|
||
|
|
bits 0:31
|
||
|
|
Decoder UV vertical scaling
|
||
|
|
When enlarging = Reg 2930 >> 1
|
||
|
|
When reducing = Reg 2930
|
||
|
|
---------------
|
||
|
|
2944
|
||
|
|
bits 0:31
|
||
|
|
Decoder ?? unknown - UV vertical scaling
|
||
|
|
---------------
|
||
|
|
2948
|
||
|
|
bits 0:31
|
||
|
|
Decoder UV vertical scaling
|
||
|
|
Normally = Reg 2940
|
||
|
|
---------------
|
||
|
|
294C
|
||
|
|
bits 0:31
|
||
|
|
Decoder ?? unknown - UV vertical scaling
|
||
|
|
|
||
|
|
Most of these registers either control vertical scaling, or appear linked
|
||
|
|
to it in some way. Register 2930 contains the 'master' value & all other
|
||
|
|
registers can be calculated from that one. You must also remember to
|
||
|
|
correctly set the divider in Reg 296C
|
||
|
|
|
||
|
|
To enlarge:
|
||
|
|
Reg 2930 = (source_height * 0x00200000) / destination_height
|
||
|
|
Reg 296C = No divide
|
||
|
|
|
||
|
|
To reduce from full size down to half size:
|
||
|
|
Reg 2930 = (source_height/2 * 0x00200000) / destination height
|
||
|
|
Reg 296C = Divide by 2
|
||
|
|
|
||
|
|
To reduce from half down to quarter.
|
||
|
|
Reg 2930 = (source_height/4 * 0x00200000) / destination height
|
||
|
|
Reg 296C = Divide by 4
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2950
|
||
|
|
bits 0:15
|
||
|
|
Decoder Y line index into display buffer, first field
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
Decoder Y vertical line skip, first field
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2954
|
||
|
|
bits 0:15
|
||
|
|
Decoder Y line index into display buffer, second field
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
Decoder Y vertical line skip, second field
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2958
|
||
|
|
bits 0:15
|
||
|
|
Decoder UV line index into display buffer, first field
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
Decoder UV vertical line skip, first field
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
295C
|
||
|
|
bits 0:15
|
||
|
|
Decoder UV line index into display buffer, second field
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
Decoder UV vertical line skip, second field
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2960
|
||
|
|
bits 0:15
|
||
|
|
Decoder destination height minus 1
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
Decoder destination height divided by 2
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2964
|
||
|
|
bits 0:15
|
||
|
|
Decoder Y vertical offset, second field
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
Decoder Y vertical offset, first field
|
||
|
|
|
||
|
|
These two registers shift the Y plane up. The higher the number, the
|
||
|
|
greater the shift.
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2968
|
||
|
|
bits 0:15
|
||
|
|
Decoder UV vertical offset, second field
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
Decoder UV vertical offset, first field
|
||
|
|
|
||
|
|
These two registers shift the UV plane up. The higher the number, the
|
||
|
|
greater the shift.
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
296C
|
||
|
|
bits 0:1
|
||
|
|
Decoder vertical Y output size divider
|
||
|
|
00 = No divide
|
||
|
|
01 = Divide by 2
|
||
|
|
10 = Divide by 4
|
||
|
|
|
||
|
|
bits 8:9
|
||
|
|
Decoder vertical UV output size divider
|
||
|
|
00 = No divide
|
||
|
|
01 = Divide by 2
|
||
|
|
10 = Divide by 4
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2970
|
||
|
|
bit 0
|
||
|
|
Decoder ?? unknown
|
||
|
|
0 = Normal
|
||
|
|
1 = Affect video output levels
|
||
|
|
|
||
|
|
bit 16
|
||
|
|
Decoder ?? unknown
|
||
|
|
0 = Normal
|
||
|
|
1 = Disable vertical filter
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2974 -------- ?? unknown
|
||
|
|
|
|
||
|
|
V
|
||
|
|
29EF -------- ?? unknown
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A00
|
||
|
|
bits 0:2
|
||
|
|
osd colour mode
|
||
|
|
000 = 8 bit indexed
|
||
|
|
001 = 16 bit (565)
|
||
|
|
010 = 15 bit (555)
|
||
|
|
011 = 12 bit (444)
|
||
|
|
100 = 32 bit (8888)
|
||
|
|
|
||
|
|
bits 4:5
|
||
|
|
osd display bpp
|
||
|
|
01 = 8 bit
|
||
|
|
10 = 16 bit
|
||
|
|
11 = 32 bit
|
||
|
|
|
||
|
|
bit 8
|
||
|
|
osd global alpha
|
||
|
|
0 = Off
|
||
|
|
1 = On
|
||
|
|
|
||
|
|
bit 9
|
||
|
|
osd local alpha
|
||
|
|
0 = Off
|
||
|
|
1 = On
|
||
|
|
|
||
|
|
bit 10
|
||
|
|
osd colour key
|
||
|
|
0 = Off
|
||
|
|
1 = On
|
||
|
|
|
||
|
|
bit 11
|
||
|
|
osd ?? unknown
|
||
|
|
Must be 1
|
||
|
|
|
||
|
|
bit 13
|
||
|
|
osd colour space
|
||
|
|
0 = ARGB
|
||
|
|
1 = AYVU
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
osd ?? unknown
|
||
|
|
Must be 0x001B (some kind of buffer pointer ?)
|
||
|
|
|
||
|
|
When the bits-per-pixel is set to 8, the colour mode is ignored and
|
||
|
|
assumed to be 8 bit indexed. For 16 & 32 bits-per-pixel the colour depth
|
||
|
|
is honoured, and when using a colour depth that requires fewer bytes than
|
||
|
|
allocated the extra bytes are used as padding. So for a 32 bpp with 8 bit
|
||
|
|
index colour, there are 3 padding bytes per pixel. It's also possible to
|
||
|
|
select 16bpp with a 32 bit colour mode. This results in the pixel width
|
||
|
|
being doubled, but the color key will not work as expected in this mode.
|
||
|
|
|
||
|
|
Colour key is as it suggests. You designate a colour which will become
|
||
|
|
completely transparent. When using 565, 555 or 444 colour modes, the
|
||
|
|
colour key is always 16 bits wide. The colour to key on is set in Reg 2A18.
|
||
|
|
|
||
|
|
Local alpha works differently depending on the colour mode. For 32bpp & 8
|
||
|
|
bit indexed, local alpha is a per-pixel 256 step transparency, with 0 being
|
||
|
|
transparent and 255 being solid. For the 16bpp modes 555 & 444, the unused
|
||
|
|
bit(s) act as a simple transparency switch, with 0 being solid & 1 being
|
||
|
|
fully transparent. There is no local alpha support for 16bit 565.
|
||
|
|
|
||
|
|
Global alpha is a 256 step transparency that applies to the entire osd,
|
||
|
|
with 0 being transparent & 255 being solid.
|
||
|
|
|
||
|
|
It's possible to combine colour key, local alpha & global alpha.
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A04
|
||
|
|
bits 0:15
|
||
|
|
osd x coord for left edge
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
osd y coord for top edge
|
||
|
|
---------------
|
||
|
|
2A08
|
||
|
|
bits 0:15
|
||
|
|
osd x coord for right edge
|
||
|
|
|
||
|
|
bits 16:31
|
||
|
|
osd y coord for bottom edge
|
||
|
|
|
||
|
|
For both registers, (0,0) = top left corner of the display area. These
|
||
|
|
registers do not control the osd size, only where it's positioned & how
|
||
|
|
much is visible. The visible osd area cannot exceed the right edge of the
|
||
|
|
display, otherwise the osd will become corrupt. See reg 2A10 for
|
||
|
|
setting osd width.
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A0C
|
||
|
|
bits 0:31
|
||
|
|
osd buffer index
|
||
|
|
|
||
|
|
An index into the osd buffer. Slowly incrementing this moves the osd left,
|
||
|
|
wrapping around onto the right edge
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A10
|
||
|
|
bits 0:11
|
||
|
|
osd buffer 32 bit word width
|
||
|
|
|
||
|
|
Contains the width of the osd measured in 32 bit words. This means that all
|
||
|
|
colour modes are restricted to a byte width which is divisible by 4.
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A14
|
||
|
|
bits 0:15
|
||
|
|
osd height in pixels
|
||
|
|
|
||
|
|
bits 16:32
|
||
|
|
osd line index into buffer
|
||
|
|
osd will start displaying from this line.
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A18
|
||
|
|
bits 0:31
|
||
|
|
osd colour key
|
||
|
|
|
||
|
|
Contains the colour value which will be transparent.
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A1C
|
||
|
|
bits 0:7
|
||
|
|
osd global alpha
|
||
|
|
|
||
|
|
Contains the global alpha value (equiv ivtvfbctl --alpha XX)
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A20 -------- ?? unknown
|
||
|
|
|
|
||
|
|
V
|
||
|
|
2A2C -------- ?? unknown
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A30
|
||
|
|
bits 0:7
|
||
|
|
osd colour to change in indexed palette
|
||
|
|
---------------
|
||
|
|
2A34
|
||
|
|
bits 0:31
|
||
|
|
osd colour for indexed palette
|
||
|
|
|
||
|
|
To set the new palette, first load the index of the colour to change into
|
||
|
|
2A30, then load the new colour into 2A34. The full palette is 256 colours,
|
||
|
|
so the index range is 0x00-0xFF
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A38 -------- ?? unknown
|
||
|
|
2A3C -------- ?? unknown
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A40
|
||
|
|
bits 0:31
|
||
|
|
osd ?? unknown
|
||
|
|
|
||
|
|
Affects overall brightness, wrapping around to black
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A44
|
||
|
|
bits 0:31
|
||
|
|
osd ?? unknown
|
||
|
|
|
||
|
|
Green tint
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A48
|
||
|
|
bits 0:31
|
||
|
|
osd ?? unknown
|
||
|
|
|
||
|
|
Red tint
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A4C
|
||
|
|
bits 0:31
|
||
|
|
osd ?? unknown
|
||
|
|
|
||
|
|
Affects overall brightness, wrapping around to black
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A50
|
||
|
|
bits 0:31
|
||
|
|
osd ?? unknown
|
||
|
|
|
||
|
|
Colour shift
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A54
|
||
|
|
bits 0:31
|
||
|
|
osd ?? unknown
|
||
|
|
|
||
|
|
Colour shift
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2A58 -------- ?? unknown
|
||
|
|
|
|
||
|
|
V
|
||
|
|
2AFC -------- ?? unknown
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
2B00
|
||
|
|
bit 0
|
||
|
|
osd filter control
|
||
|
|
0 = filter off
|
||
|
|
1 = filter on
|
||
|
|
|
||
|
|
bits 1:4
|
||
|
|
osd ?? unknown
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------------
|
||
|
|
|
||
|
|
v0.4 - 12 March 2007 - Ian Armstrong (ian@iarmst.demon.co.uk)
|
||
|
|
|