401 lines
8.5 KiB
C
401 lines
8.5 KiB
C
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/*
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* Clock and PLL control for DaVinci devices
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*
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* Copyright (C) 2006-2007 Texas Instruments.
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* Copyright (C) 2008-2009 Deep Root Systems, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/psc.h>
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#include <mach/cputype.h>
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#include "clock.h"
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static LIST_HEAD(clocks);
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static DEFINE_MUTEX(clocks_mutex);
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static DEFINE_SPINLOCK(clockfw_lock);
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static unsigned psc_domain(struct clk *clk)
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{
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return (clk->flags & PSC_DSP)
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? DAVINCI_GPSC_DSPDOMAIN
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: DAVINCI_GPSC_ARMDOMAIN;
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}
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static void __clk_enable(struct clk *clk)
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{
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if (clk->parent)
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__clk_enable(clk->parent);
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if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
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davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
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clk->lpsc, 1);
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}
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static void __clk_disable(struct clk *clk)
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{
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if (WARN_ON(clk->usecount == 0))
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return;
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if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
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davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
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clk->lpsc, 0);
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if (clk->parent)
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__clk_disable(clk->parent);
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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spin_lock_irqsave(&clockfw_lock, flags);
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__clk_enable(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return;
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spin_lock_irqsave(&clockfw_lock, flags);
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__clk_disable(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_round_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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/* changing the clk rate is not supported */
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return -EINVAL;
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}
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EXPORT_SYMBOL(clk_set_rate);
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int clk_register(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if (WARN(clk->parent && !clk->parent->rate,
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"CLK: %s parent %s has no rate!\n",
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clk->name, clk->parent->name))
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return -EINVAL;
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mutex_lock(&clocks_mutex);
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list_add_tail(&clk->node, &clocks);
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mutex_unlock(&clocks_mutex);
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/* If rate is already set, use it */
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if (clk->rate)
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return 0;
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/* Otherwise, default to parent rate */
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if (clk->parent)
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clk->rate = clk->parent->rate;
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return 0;
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}
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EXPORT_SYMBOL(clk_register);
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void clk_unregister(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return;
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mutex_lock(&clocks_mutex);
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list_del(&clk->node);
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mutex_unlock(&clocks_mutex);
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}
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EXPORT_SYMBOL(clk_unregister);
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#ifdef CONFIG_DAVINCI_RESET_CLOCKS
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/*
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* Disable any unused clocks left on by the bootloader
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*/
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static int __init clk_disable_unused(void)
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{
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struct clk *ck;
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spin_lock_irq(&clockfw_lock);
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list_for_each_entry(ck, &clocks, node) {
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if (ck->usecount > 0)
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continue;
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if (!(ck->flags & CLK_PSC))
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continue;
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/* ignore if in Disabled or SwRstDisable states */
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if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc))
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continue;
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pr_info("Clocks: disable unused %s\n", ck->name);
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davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0);
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}
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spin_unlock_irq(&clockfw_lock);
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return 0;
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}
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late_initcall(clk_disable_unused);
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#endif
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static void clk_sysclk_recalc(struct clk *clk)
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{
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u32 v, plldiv;
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struct pll_data *pll;
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/* If this is the PLL base clock, no more calculations needed */
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if (clk->pll_data)
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return;
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if (WARN_ON(!clk->parent))
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return;
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clk->rate = clk->parent->rate;
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/* Otherwise, the parent must be a PLL */
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if (WARN_ON(!clk->parent->pll_data))
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return;
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pll = clk->parent->pll_data;
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/* If pre-PLL, source clock is before the multiplier and divider(s) */
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if (clk->flags & PRE_PLL)
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clk->rate = pll->input_rate;
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if (!clk->div_reg)
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return;
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v = __raw_readl(pll->base + clk->div_reg);
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if (v & PLLDIV_EN) {
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plldiv = (v & PLLDIV_RATIO_MASK) + 1;
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if (plldiv)
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clk->rate /= plldiv;
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}
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}
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static void __init clk_pll_init(struct clk *clk)
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{
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u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
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u8 bypass;
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struct pll_data *pll = clk->pll_data;
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pll->base = IO_ADDRESS(pll->phys_base);
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ctrl = __raw_readl(pll->base + PLLCTL);
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clk->rate = pll->input_rate = clk->parent->rate;
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if (ctrl & PLLCTL_PLLEN) {
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bypass = 0;
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mult = __raw_readl(pll->base + PLLM);
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if (cpu_is_davinci_dm365())
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mult = 2 * (mult & PLLM_PLLM_MASK);
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else
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mult = (mult & PLLM_PLLM_MASK) + 1;
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} else
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bypass = 1;
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if (pll->flags & PLL_HAS_PREDIV) {
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prediv = __raw_readl(pll->base + PREDIV);
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if (prediv & PLLDIV_EN)
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prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
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else
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prediv = 1;
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}
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/* pre-divider is fixed, but (some?) chips won't report that */
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if (cpu_is_davinci_dm355() && pll->num == 1)
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prediv = 8;
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if (pll->flags & PLL_HAS_POSTDIV) {
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postdiv = __raw_readl(pll->base + POSTDIV);
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if (postdiv & PLLDIV_EN)
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postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
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else
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postdiv = 1;
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}
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if (!bypass) {
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clk->rate /= prediv;
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clk->rate *= mult;
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clk->rate /= postdiv;
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}
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pr_debug("PLL%d: input = %lu MHz [ ",
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pll->num, clk->parent->rate / 1000000);
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if (bypass)
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pr_debug("bypass ");
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if (prediv > 1)
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pr_debug("/ %d ", prediv);
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if (mult > 1)
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pr_debug("* %d ", mult);
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if (postdiv > 1)
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pr_debug("/ %d ", postdiv);
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pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000);
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}
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int __init davinci_clk_init(struct davinci_clk *clocks)
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{
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struct davinci_clk *c;
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struct clk *clk;
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for (c = clocks; c->lk.clk; c++) {
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clk = c->lk.clk;
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if (clk->pll_data)
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clk_pll_init(clk);
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/* Calculate rates for PLL-derived clocks */
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else if (clk->flags & CLK_PLL)
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clk_sysclk_recalc(clk);
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if (clk->lpsc)
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clk->flags |= CLK_PSC;
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clkdev_add(&c->lk);
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clk_register(clk);
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/* Turn on clocks that Linux doesn't otherwise manage */
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if (clk->flags & ALWAYS_ENABLED)
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clk_enable(clk);
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}
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return 0;
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}
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#ifdef CONFIG_PROC_FS
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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static void *davinci_ck_start(struct seq_file *m, loff_t *pos)
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{
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return *pos < 1 ? (void *)1 : NULL;
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}
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static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos)
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{
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++*pos;
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return NULL;
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}
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static void davinci_ck_stop(struct seq_file *m, void *v)
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{
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}
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#define CLKNAME_MAX 10 /* longest clock name */
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#define NEST_DELTA 2
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#define NEST_MAX 4
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static void
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dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
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{
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char *state;
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char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
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struct clk *clk;
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unsigned i;
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if (parent->flags & CLK_PLL)
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state = "pll";
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else if (parent->flags & CLK_PSC)
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state = "psc";
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else
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state = "";
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/* <nest spaces> name <pad to end> */
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memset(buf, ' ', sizeof(buf) - 1);
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buf[sizeof(buf) - 1] = 0;
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i = strlen(parent->name);
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memcpy(buf + nest, parent->name,
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min(i, (unsigned)(sizeof(buf) - 1 - nest)));
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seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
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buf, parent->usecount, state, clk_get_rate(parent));
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/* REVISIT show device associations too */
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/* cost is now small, but not linear... */
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list_for_each_entry(clk, &clocks, node) {
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if (clk->parent == parent)
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dump_clock(s, nest + NEST_DELTA, clk);
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}
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}
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static int davinci_ck_show(struct seq_file *m, void *v)
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{
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/* Show clock tree; we know the main oscillator is first.
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* We trust nonzero usecounts equate to PSC enables...
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*/
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mutex_lock(&clocks_mutex);
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if (!list_empty(&clocks))
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dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
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mutex_unlock(&clocks_mutex);
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return 0;
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}
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static const struct seq_operations davinci_ck_op = {
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.start = davinci_ck_start,
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.next = davinci_ck_next,
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.stop = davinci_ck_stop,
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.show = davinci_ck_show
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};
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static int davinci_ck_open(struct inode *inode, struct file *file)
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{
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return seq_open(file, &davinci_ck_op);
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}
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static const struct file_operations proc_davinci_ck_operations = {
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.open = davinci_ck_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = seq_release,
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};
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static int __init davinci_ck_proc_init(void)
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{
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proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations);
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return 0;
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}
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__initcall(davinci_ck_proc_init);
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#endif /* CONFIG_DEBUG_PROC_FS */
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