386 lines
9.2 KiB
C
386 lines
9.2 KiB
C
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/*
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* OMAP34XX powerdomain definitions
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2008 Nokia Corporation
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*
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* Written by Paul Walmsley
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* Debugging and integration fixes by Jouni Högander
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
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#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
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/*
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* N.B. If powerdomains are added or removed from this file, update
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* the array in mach-omap2/powerdomains.h.
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*/
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#include <mach/powerdomain.h>
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#include "prcm-common.h"
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#include "prm.h"
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#include "prm-regbits-34xx.h"
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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/*
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* 34XX-specific powerdomains, dependencies
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*/
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#ifdef CONFIG_ARCH_OMAP34XX
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/*
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* 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
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* (USBHOST is ES2 only)
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*/
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static struct pwrdm_dep per_usbhost_wkdeps[] = {
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{
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.pwrdm_name = "core_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "iva2_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "wkup_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/*
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* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
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*/
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static struct pwrdm_dep mpu_34xx_wkdeps[] = {
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{
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.pwrdm_name = "core_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "iva2_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "dss_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "per_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/*
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* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
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*/
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static struct pwrdm_dep iva2_wkdeps[] = {
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{
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.pwrdm_name = "core_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "wkup_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "dss_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "per_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
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static struct pwrdm_dep cam_dss_wkdeps[] = {
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{
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.pwrdm_name = "iva2_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "wkup_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430: PM_WKDEP_NEON: MPU */
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static struct pwrdm_dep neon_wkdeps[] = {
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
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/*
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* 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
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* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
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*/
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static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
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{
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.pwrdm_name = "mpu_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm_name = "iva2_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/*
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* Powerdomains
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*/
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static struct powerdomain iva2_pwrdm = {
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.name = "iva2_pwrdm",
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.prcm_offs = OMAP3430_IVA2_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
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.wkdep_srcs = iva2_wkdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 4,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET,
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[1] = PWRSTS_OFF_RET,
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[2] = PWRSTS_OFF_RET,
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[3] = PWRSTS_OFF_RET,
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON,
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[1] = PWRDM_POWER_ON,
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[2] = PWRSTS_OFF_ON,
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[3] = PWRDM_POWER_ON,
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},
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};
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static struct powerdomain mpu_34xx_pwrdm = {
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.name = "mpu_pwrdm",
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.prcm_offs = MPU_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.dep_bit = OMAP3430_EN_MPU_SHIFT,
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.wkdep_srcs = mpu_34xx_wkdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET,
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_ON,
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},
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};
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/* No wkdeps or sleepdeps for 34xx core apparently */
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static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = CORE_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
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CHIP_IS_OMAP3430ES2 |
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CHIP_IS_OMAP3430ES3_0),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.dep_bit = OMAP3430_EN_CORE_SHIFT,
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
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[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
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[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
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},
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};
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/* No wkdeps or sleepdeps for 34xx core apparently */
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static struct powerdomain core_34xx_es3_1_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = CORE_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.dep_bit = OMAP3430_EN_CORE_SHIFT,
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.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
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[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
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[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
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},
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};
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/* Another case of bit name collisions between several registers: EN_DSS */
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static struct powerdomain dss_pwrdm = {
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.name = "dss_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.prcm_offs = OMAP3430_DSS_MOD,
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.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
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.wkdep_srcs = cam_dss_wkdeps,
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.sleepdep_srcs = dss_per_usbhost_sleepdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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/*
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* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
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* possible SGX powerstate, the SGX device itself does not support
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* retention.
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*/
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static struct powerdomain sgx_pwrdm = {
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.name = "sgx_pwrdm",
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.prcm_offs = OMAP3430ES2_SGX_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
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.wkdep_srcs = gfx_sgx_wkdeps,
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.sleepdep_srcs = cam_gfx_sleepdeps,
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/* XXX This is accurate for 3430 SGX, but what about GFX? */
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.pwrsts = PWRSTS_OFF_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain cam_pwrdm = {
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.name = "cam_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.prcm_offs = OMAP3430_CAM_MOD,
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.wkdep_srcs = cam_dss_wkdeps,
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.sleepdep_srcs = cam_gfx_sleepdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain per_pwrdm = {
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.name = "per_pwrdm",
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.prcm_offs = OMAP3430_PER_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.dep_bit = OMAP3430_EN_PER_SHIFT,
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.wkdep_srcs = per_usbhost_wkdeps,
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.sleepdep_srcs = dss_per_usbhost_sleepdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain emu_pwrdm = {
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.name = "emu_pwrdm",
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.prcm_offs = OMAP3430_EMU_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct powerdomain neon_pwrdm = {
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.name = "neon_pwrdm",
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.prcm_offs = OMAP3430_NEON_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.wkdep_srcs = neon_wkdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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};
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static struct powerdomain usbhost_pwrdm = {
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.name = "usbhost_pwrdm",
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.prcm_offs = OMAP3430ES2_USBHOST_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
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.wkdep_srcs = per_usbhost_wkdeps,
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.sleepdep_srcs = dss_per_usbhost_sleepdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
|
||
|
|
.flags = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */
|
||
|
|
.banks = 1,
|
||
|
|
.pwrsts_mem_ret = {
|
||
|
|
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
|
||
|
|
},
|
||
|
|
.pwrsts_mem_on = {
|
||
|
|
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct powerdomain dpll1_pwrdm = {
|
||
|
|
.name = "dpll1_pwrdm",
|
||
|
|
.prcm_offs = MPU_MOD,
|
||
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct powerdomain dpll2_pwrdm = {
|
||
|
|
.name = "dpll2_pwrdm",
|
||
|
|
.prcm_offs = OMAP3430_IVA2_MOD,
|
||
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct powerdomain dpll3_pwrdm = {
|
||
|
|
.name = "dpll3_pwrdm",
|
||
|
|
.prcm_offs = PLL_MOD,
|
||
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct powerdomain dpll4_pwrdm = {
|
||
|
|
.name = "dpll4_pwrdm",
|
||
|
|
.prcm_offs = PLL_MOD,
|
||
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct powerdomain dpll5_pwrdm = {
|
||
|
|
.name = "dpll5_pwrdm",
|
||
|
|
.prcm_offs = PLL_MOD,
|
||
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* CONFIG_ARCH_OMAP34XX */
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|