348 lines
8.5 KiB
C
348 lines
8.5 KiB
C
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/*
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* linux/arch/arm/plat-pxa/gpio.c
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*
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* Generic PXA GPIO handling
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/sysdev.h>
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#include <linux/slab.h>
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#include <mach/gpio.h>
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int pxa_last_gpio;
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struct pxa_gpio_chip {
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struct gpio_chip chip;
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void __iomem *regbase;
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char label[10];
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unsigned long irq_mask;
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unsigned long irq_edge_rise;
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unsigned long irq_edge_fall;
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#ifdef CONFIG_PM
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unsigned long saved_gplr;
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unsigned long saved_gpdr;
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unsigned long saved_grer;
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unsigned long saved_gfer;
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#endif
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};
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static DEFINE_SPINLOCK(gpio_lock);
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static struct pxa_gpio_chip *pxa_gpio_chips;
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#define for_each_gpio_chip(i, c) \
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for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
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static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
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{
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return container_of(c, struct pxa_gpio_chip, chip)->regbase;
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}
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static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio)
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{
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return &pxa_gpio_chips[gpio_to_bank(gpio)];
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}
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static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *base = gpio_chip_base(chip);
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uint32_t value, mask = 1 << offset;
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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value = __raw_readl(base + GPDR_OFFSET);
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if (__gpio_is_inverted(chip->base + offset))
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value |= mask;
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else
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value &= ~mask;
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__raw_writel(value, base + GPDR_OFFSET);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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static int pxa_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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void __iomem *base = gpio_chip_base(chip);
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uint32_t tmp, mask = 1 << offset;
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unsigned long flags;
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__raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
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spin_lock_irqsave(&gpio_lock, flags);
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tmp = __raw_readl(base + GPDR_OFFSET);
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if (__gpio_is_inverted(chip->base + offset))
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tmp &= ~mask;
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else
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tmp |= mask;
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__raw_writel(tmp, base + GPDR_OFFSET);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
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}
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static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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__raw_writel(1 << offset, gpio_chip_base(chip) +
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(value ? GPSR_OFFSET : GPCR_OFFSET));
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}
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static int __init pxa_init_gpio_chip(int gpio_end)
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{
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int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
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struct pxa_gpio_chip *chips;
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chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
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if (chips == NULL) {
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pr_err("%s: failed to allocate GPIO chips\n", __func__);
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return -ENOMEM;
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}
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for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
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struct gpio_chip *c = &chips[i].chip;
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sprintf(chips[i].label, "gpio-%d", i);
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chips[i].regbase = (void __iomem *)GPIO_BANK(i);
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c->base = gpio;
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c->label = chips[i].label;
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c->direction_input = pxa_gpio_direction_input;
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c->direction_output = pxa_gpio_direction_output;
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c->get = pxa_gpio_get;
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c->set = pxa_gpio_set;
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/* number of GPIOs on last bank may be less than 32 */
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c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
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gpiochip_add(c);
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}
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pxa_gpio_chips = chips;
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return 0;
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}
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/* Update only those GRERx and GFERx edge detection register bits if those
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* bits are set in c->irq_mask
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*/
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static inline void update_edge_detect(struct pxa_gpio_chip *c)
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{
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uint32_t grer, gfer;
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grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
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gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
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grer |= c->irq_edge_rise & c->irq_mask;
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gfer |= c->irq_edge_fall & c->irq_mask;
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__raw_writel(grer, c->regbase + GRER_OFFSET);
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__raw_writel(gfer, c->regbase + GFER_OFFSET);
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}
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static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
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{
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struct pxa_gpio_chip *c;
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int gpio = irq_to_gpio(irq);
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unsigned long gpdr, mask = GPIO_bit(gpio);
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c = gpio_to_chip(gpio);
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if (type == IRQ_TYPE_PROBE) {
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/* Don't mess with enabled GPIOs using preconfigured edges or
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* GPIOs set to alternate function or to output during probe
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*/
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if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
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return 0;
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if (__gpio_is_occupied(gpio))
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return 0;
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type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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}
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gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
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if (__gpio_is_inverted(gpio))
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__raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET);
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else
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__raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
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if (type & IRQ_TYPE_EDGE_RISING)
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c->irq_edge_rise |= mask;
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else
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c->irq_edge_rise &= ~mask;
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if (type & IRQ_TYPE_EDGE_FALLING)
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c->irq_edge_fall |= mask;
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else
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c->irq_edge_fall &= ~mask;
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update_edge_detect(c);
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pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
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((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
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((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
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return 0;
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}
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static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct pxa_gpio_chip *c;
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int loop, gpio, gpio_base, n;
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unsigned long gedr;
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do {
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loop = 0;
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for_each_gpio_chip(gpio, c) {
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gpio_base = c->chip.base;
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gedr = __raw_readl(c->regbase + GEDR_OFFSET);
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gedr = gedr & c->irq_mask;
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__raw_writel(gedr, c->regbase + GEDR_OFFSET);
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n = find_first_bit(&gedr, BITS_PER_LONG);
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while (n < BITS_PER_LONG) {
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loop = 1;
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generic_handle_irq(gpio_to_irq(gpio_base + n));
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n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
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}
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}
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} while (loop);
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}
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static void pxa_ack_muxed_gpio(unsigned int irq)
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{
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int gpio = irq_to_gpio(irq);
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struct pxa_gpio_chip *c = gpio_to_chip(gpio);
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__raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
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}
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static void pxa_mask_muxed_gpio(unsigned int irq)
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{
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int gpio = irq_to_gpio(irq);
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struct pxa_gpio_chip *c = gpio_to_chip(gpio);
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uint32_t grer, gfer;
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c->irq_mask &= ~GPIO_bit(gpio);
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grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
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gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
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__raw_writel(grer, c->regbase + GRER_OFFSET);
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__raw_writel(gfer, c->regbase + GFER_OFFSET);
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}
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static void pxa_unmask_muxed_gpio(unsigned int irq)
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{
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int gpio = irq_to_gpio(irq);
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struct pxa_gpio_chip *c = gpio_to_chip(gpio);
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c->irq_mask |= GPIO_bit(gpio);
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update_edge_detect(c);
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}
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static struct irq_chip pxa_muxed_gpio_chip = {
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.name = "GPIO",
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.ack = pxa_ack_muxed_gpio,
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.mask = pxa_mask_muxed_gpio,
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.unmask = pxa_unmask_muxed_gpio,
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.set_type = pxa_gpio_irq_type,
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};
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void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
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{
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struct pxa_gpio_chip *c;
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int gpio, irq;
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pxa_last_gpio = end;
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/* Initialize GPIO chips */
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pxa_init_gpio_chip(end);
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/* clear all GPIO edge detects */
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for_each_gpio_chip(gpio, c) {
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__raw_writel(0, c->regbase + GFER_OFFSET);
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__raw_writel(0, c->regbase + GRER_OFFSET);
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__raw_writel(~0,c->regbase + GEDR_OFFSET);
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}
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for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
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set_irq_chip(irq, &pxa_muxed_gpio_chip);
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set_irq_handler(irq, handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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/* Install handler for GPIO>=2 edge detect interrupts */
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set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler);
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pxa_muxed_gpio_chip.set_wake = fn;
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}
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#ifdef CONFIG_PM
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static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
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{
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struct pxa_gpio_chip *c;
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int gpio;
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for_each_gpio_chip(gpio, c) {
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c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
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c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
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c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
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c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
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/* Clear GPIO transition detect bits */
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__raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
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}
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return 0;
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}
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static int pxa_gpio_resume(struct sys_device *dev)
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{
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struct pxa_gpio_chip *c;
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int gpio;
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for_each_gpio_chip(gpio, c) {
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/* restore level with set/clear */
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__raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
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__raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
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__raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
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__raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
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__raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
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}
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return 0;
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}
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#else
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#define pxa_gpio_suspend NULL
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#define pxa_gpio_resume NULL
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#endif
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struct sysdev_class pxa_gpio_sysclass = {
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.name = "gpio",
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.suspend = pxa_gpio_suspend,
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.resume = pxa_gpio_resume,
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};
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static int __init pxa_gpio_init(void)
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{
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return sysdev_class_register(&pxa_gpio_sysclass);
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}
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core_initcall(pxa_gpio_init);
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