107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
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/*
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* panic kernel with dump information
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*
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* Copyright 2005-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <linux/kernel_stat.h>
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#include <linux/sched.h>
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#include <asm/blackfin.h>
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#define L1_ICACHE_START 0xffa10000
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#define L1_ICACHE_END 0xffa13fff
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/*
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* irq_panic - calls panic with string setup
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*/
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__attribute__ ((l1_text))
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asmlinkage void irq_panic(int reason, struct pt_regs *regs)
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{
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unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa;
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unsigned short i, j, die;
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unsigned int bad[10][6];
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/* check entire cache for coherency
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* Since printk is in cacheable memory,
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* don't call it until you have checked everything
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*/
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die = 0;
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i = 0;
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/* check icache */
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for (ca = L1_ICACHE_START; ca <= L1_ICACHE_END && i < 10; ca += 32) {
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/* Grab various address bits for the itest_cmd fields */
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cmd = (((ca & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
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((ca & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
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((ca & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
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0); /* Access Tag, Read access */
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SSYNC();
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bfin_write_ITEST_COMMAND(cmd);
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SSYNC();
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tag = bfin_read_ITEST_DATA0();
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SSYNC();
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/* if tag is marked as valid, check it */
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if (tag & 1) {
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/* The icache is arranged in 4 groups of 64-bits */
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for (j = 0; j < 32; j += 8) {
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cmd = ((((ca + j) & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
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(((ca + j) & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
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(((ca + j) & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
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4); /* Access Data, Read access */
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SSYNC();
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bfin_write_ITEST_COMMAND(cmd);
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SSYNC();
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cache_hi = bfin_read_ITEST_DATA1();
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cache_lo = bfin_read_ITEST_DATA0();
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pa = ((unsigned int *)((tag & 0xffffcc00) |
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((ca + j) & ~(0xffffcc00))));
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/*
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* Debugging this, enable
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*
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* printk("addr: %08x %08x%08x | %08x%08x\n",
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* ((unsigned int *)((tag & 0xffffcc00) | ((ca+j) & ~(0xffffcc00)))),
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* cache_hi, cache_lo, *(pa+1), *pa);
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*/
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if (cache_hi != *(pa + 1) || cache_lo != *pa) {
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/* Since icache is not working, stay out of it, by not printing */
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die = 1;
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bad[i][0] = (ca + j);
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bad[i][1] = cache_hi;
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bad[i][2] = cache_lo;
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bad[i][3] = ((tag & 0xffffcc00) |
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((ca + j) & ~(0xffffcc00)));
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bad[i][4] = *(pa + 1);
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bad[i][5] = *(pa);
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i++;
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}
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}
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}
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}
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if (die) {
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printk(KERN_EMERG "icache coherency error\n");
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for (j = 0; j <= i; j++) {
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printk(KERN_EMERG
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"cache address : %08x cache value : %08x%08x\n",
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bad[j][0], bad[j][1], bad[j][2]);
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printk(KERN_EMERG
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"physical address: %08x SDRAM value : %08x%08x\n",
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bad[j][3], bad[j][4], bad[j][5]);
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}
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panic("icache coherency error");
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} else
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printk(KERN_EMERG "icache checked, and OK\n");
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}
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