231 lines
5.4 KiB
C
231 lines
5.4 KiB
C
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/* Wrapper for DMA channel allocator that starts clocks etc */
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <asm/dma.h>
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <hwregs/marb_defs.h>
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#include <hwregs/config_defs.h>
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#include <hwregs/strmux_defs.h>
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#include <linux/errno.h>
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#include <asm/system.h>
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#include <mach/arbiter.h>
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static char used_dma_channels[MAX_DMA_CHANNELS];
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static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
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static DEFINE_SPINLOCK(dma_lock);
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int crisv32_request_dma(unsigned int dmanr, const char *device_id,
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unsigned options, unsigned int bandwidth,
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enum dma_owner owner)
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{
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unsigned long flags;
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reg_config_rw_clk_ctrl clk_ctrl;
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reg_strmux_rw_cfg strmux_cfg;
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if (crisv32_arbiter_allocate_bandwidth(dmanr,
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options & DMA_INT_MEM ?
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INT_REGION : EXT_REGION,
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bandwidth))
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return -ENOMEM;
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spin_lock_irqsave(&dma_lock, flags);
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if (used_dma_channels[dmanr]) {
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spin_unlock_irqrestore(&dma_lock, flags);
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if (options & DMA_VERBOSE_ON_ERROR) {
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printk(KERN_ERR "Failed to request DMA %i for %s, "
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"already allocated by %s\n",
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dmanr,
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device_id,
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used_dma_channels_users[dmanr]);
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}
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if (options & DMA_PANIC_ON_ERROR)
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panic("request_dma error!");
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spin_unlock_irqrestore(&dma_lock, flags);
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return -EBUSY;
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}
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clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
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strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
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switch (dmanr) {
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case 0:
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case 1:
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clk_ctrl.dma01_eth0 = 1;
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break;
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case 2:
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case 3:
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clk_ctrl.dma23 = 1;
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break;
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case 4:
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case 5:
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clk_ctrl.dma45 = 1;
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break;
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case 6:
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case 7:
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clk_ctrl.dma67 = 1;
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break;
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case 8:
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case 9:
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clk_ctrl.dma89_strcop = 1;
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break;
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#if MAX_DMA_CHANNELS-1 != 9
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#error Check dma.c
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#endif
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default:
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spin_unlock_irqrestore(&dma_lock, flags);
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if (options & DMA_VERBOSE_ON_ERROR) {
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printk(KERN_ERR "Failed to request DMA %i for %s, "
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"only 0-%i valid)\n",
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dmanr, device_id, MAX_DMA_CHANNELS - 1);
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}
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if (options & DMA_PANIC_ON_ERROR)
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panic("request_dma error!");
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return -EINVAL;
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}
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switch (owner) {
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case dma_eth0:
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if (dmanr == 0)
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strmux_cfg.dma0 = regk_strmux_eth0;
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else if (dmanr == 1)
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strmux_cfg.dma1 = regk_strmux_eth0;
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else
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panic("Invalid DMA channel for eth0\n");
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break;
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case dma_eth1:
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if (dmanr == 6)
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strmux_cfg.dma6 = regk_strmux_eth1;
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else if (dmanr == 7)
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strmux_cfg.dma7 = regk_strmux_eth1;
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else
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panic("Invalid DMA channel for eth1\n");
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break;
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case dma_iop0:
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if (dmanr == 2)
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strmux_cfg.dma2 = regk_strmux_iop0;
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else if (dmanr == 3)
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strmux_cfg.dma3 = regk_strmux_iop0;
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else
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panic("Invalid DMA channel for iop0\n");
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break;
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case dma_iop1:
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if (dmanr == 4)
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strmux_cfg.dma4 = regk_strmux_iop1;
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else if (dmanr == 5)
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strmux_cfg.dma5 = regk_strmux_iop1;
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else
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panic("Invalid DMA channel for iop1\n");
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break;
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case dma_ser0:
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if (dmanr == 6)
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strmux_cfg.dma6 = regk_strmux_ser0;
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else if (dmanr == 7)
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strmux_cfg.dma7 = regk_strmux_ser0;
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else
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panic("Invalid DMA channel for ser0\n");
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break;
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case dma_ser1:
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if (dmanr == 4)
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strmux_cfg.dma4 = regk_strmux_ser1;
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else if (dmanr == 5)
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strmux_cfg.dma5 = regk_strmux_ser1;
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else
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panic("Invalid DMA channel for ser1\n");
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break;
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case dma_ser2:
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if (dmanr == 2)
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strmux_cfg.dma2 = regk_strmux_ser2;
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else if (dmanr == 3)
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strmux_cfg.dma3 = regk_strmux_ser2;
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else
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panic("Invalid DMA channel for ser2\n");
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break;
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case dma_ser3:
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if (dmanr == 8)
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strmux_cfg.dma8 = regk_strmux_ser3;
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else if (dmanr == 9)
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strmux_cfg.dma9 = regk_strmux_ser3;
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else
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panic("Invalid DMA channel for ser3\n");
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break;
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case dma_sser0:
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if (dmanr == 4)
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strmux_cfg.dma4 = regk_strmux_sser0;
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else if (dmanr == 5)
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strmux_cfg.dma5 = regk_strmux_sser0;
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else
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panic("Invalid DMA channel for sser0\n");
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break;
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case dma_sser1:
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if (dmanr == 6)
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strmux_cfg.dma6 = regk_strmux_sser1;
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else if (dmanr == 7)
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strmux_cfg.dma7 = regk_strmux_sser1;
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else
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panic("Invalid DMA channel for sser1\n");
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break;
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case dma_ata:
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if (dmanr == 2)
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strmux_cfg.dma2 = regk_strmux_ata;
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else if (dmanr == 3)
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strmux_cfg.dma3 = regk_strmux_ata;
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else
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panic("Invalid DMA channel for ata\n");
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break;
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case dma_strp:
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if (dmanr == 8)
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strmux_cfg.dma8 = regk_strmux_strcop;
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else if (dmanr == 9)
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strmux_cfg.dma9 = regk_strmux_strcop;
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else
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panic("Invalid DMA channel for strp\n");
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break;
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case dma_ext0:
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if (dmanr == 6)
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strmux_cfg.dma6 = regk_strmux_ext0;
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else
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panic("Invalid DMA channel for ext0\n");
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break;
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case dma_ext1:
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if (dmanr == 7)
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strmux_cfg.dma7 = regk_strmux_ext1;
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else
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panic("Invalid DMA channel for ext1\n");
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break;
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case dma_ext2:
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if (dmanr == 2)
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strmux_cfg.dma2 = regk_strmux_ext2;
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else if (dmanr == 8)
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strmux_cfg.dma8 = regk_strmux_ext2;
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else
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panic("Invalid DMA channel for ext2\n");
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break;
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case dma_ext3:
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if (dmanr == 3)
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strmux_cfg.dma3 = regk_strmux_ext3;
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else if (dmanr == 9)
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strmux_cfg.dma9 = regk_strmux_ext2;
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else
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panic("Invalid DMA channel for ext2\n");
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break;
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}
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used_dma_channels[dmanr] = 1;
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used_dma_channels_users[dmanr] = device_id;
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REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
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REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
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spin_unlock_irqrestore(&dma_lock, flags);
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return 0;
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}
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void crisv32_free_dma(unsigned int dmanr)
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{
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spin_lock(&dma_lock);
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used_dma_channels[dmanr] = 0;
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spin_unlock(&dma_lock);
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}
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