524 lines
14 KiB
C
524 lines
14 KiB
C
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/**
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* Copyright (C) 2005 - 2009 ServerEngines
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation. The full GNU General
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* Public License is included in this distribution in the file called COPYING.
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*
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* Contact Information:
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* linux-drivers@serverengines.com
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*
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* ServerEngines
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* 209 N. Fair Oaks Ave
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* Sunnyvale, CA 94085
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*/
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#include "be.h"
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#include "be_mgmt.h"
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#include "be_main.h"
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static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
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{
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if (compl->flags != 0) {
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compl->flags = le32_to_cpu(compl->flags);
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WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
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return true;
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} else
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return false;
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}
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static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
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{
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compl->flags = 0;
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}
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static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
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struct be_mcc_compl *compl)
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{
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u16 compl_status, extd_status;
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be_dws_le_to_cpu(compl, 4);
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compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
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CQE_STATUS_COMPL_MASK;
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if (compl_status != MCC_STATUS_SUCCESS) {
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extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
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CQE_STATUS_EXTD_MASK;
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dev_err(&ctrl->pdev->dev,
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"error in cmd completion: status(compl/extd)=%d/%d\n",
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compl_status, extd_status);
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return -1;
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}
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return 0;
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}
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static inline bool is_link_state_evt(u32 trailer)
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{
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return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
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ASYNC_TRAILER_EVENT_CODE_MASK) == ASYNC_EVENT_CODE_LINK_STATE);
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}
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void beiscsi_cq_notify(struct be_ctrl_info *ctrl, u16 qid, bool arm,
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u16 num_popped)
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{
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u32 val = 0;
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val |= qid & DB_CQ_RING_ID_MASK;
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if (arm)
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val |= 1 << DB_CQ_REARM_SHIFT;
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val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
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iowrite32(val, ctrl->db + DB_CQ_OFFSET);
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}
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static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl)
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{
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#define long_delay 2000
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void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
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int cnt = 0, wait = 5; /* in usecs */
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u32 ready;
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do {
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ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
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if (ready)
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break;
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if (cnt > 6000000) {
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dev_err(&ctrl->pdev->dev, "mbox_db poll timed out\n");
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return -1;
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}
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if (cnt > 50) {
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wait = long_delay;
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mdelay(long_delay / 1000);
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} else
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udelay(wait);
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cnt += wait;
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} while (true);
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return 0;
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}
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int be_mbox_notify(struct be_ctrl_info *ctrl)
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{
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int status;
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u32 val = 0;
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void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
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struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
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struct be_mcc_mailbox *mbox = mbox_mem->va;
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struct be_mcc_compl *compl = &mbox->compl;
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val &= ~MPU_MAILBOX_DB_RDY_MASK;
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val |= MPU_MAILBOX_DB_HI_MASK;
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val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
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iowrite32(val, db);
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status = be_mbox_db_ready_wait(ctrl);
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if (status != 0) {
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SE_DEBUG(DBG_LVL_1, " be_mbox_db_ready_wait failed 1\n");
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return status;
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}
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val = 0;
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val &= ~MPU_MAILBOX_DB_RDY_MASK;
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val &= ~MPU_MAILBOX_DB_HI_MASK;
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val |= (u32) (mbox_mem->dma >> 4) << 2;
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iowrite32(val, db);
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status = be_mbox_db_ready_wait(ctrl);
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if (status != 0) {
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SE_DEBUG(DBG_LVL_1, " be_mbox_db_ready_wait failed 2\n");
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return status;
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}
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if (be_mcc_compl_is_new(compl)) {
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status = be_mcc_compl_process(ctrl, &mbox->compl);
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be_mcc_compl_use(compl);
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if (status) {
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SE_DEBUG(DBG_LVL_1, "After be_mcc_compl_process \n");
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return status;
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}
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} else {
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dev_err(&ctrl->pdev->dev, "invalid mailbox completion\n");
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return -1;
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}
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return 0;
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}
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void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
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bool embedded, u8 sge_cnt)
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{
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if (embedded)
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wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
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else
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wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
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MCC_WRB_SGE_CNT_SHIFT;
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wrb->payload_length = payload_len;
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be_dws_cpu_to_le(wrb, 8);
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}
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void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
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u8 subsystem, u8 opcode, int cmd_len)
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{
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req_hdr->opcode = opcode;
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req_hdr->subsystem = subsystem;
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req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
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}
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static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
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struct be_dma_mem *mem)
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{
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int i, buf_pages;
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u64 dma = (u64) mem->dma;
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buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
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for (i = 0; i < buf_pages; i++) {
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pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
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pages[i].hi = cpu_to_le32(upper_32_bits(dma));
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dma += PAGE_SIZE_4K;
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}
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}
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static u32 eq_delay_to_mult(u32 usec_delay)
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{
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#define MAX_INTR_RATE 651042
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const u32 round = 10;
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u32 multiplier;
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if (usec_delay == 0)
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multiplier = 0;
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else {
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u32 interrupt_rate = 1000000 / usec_delay;
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if (interrupt_rate == 0)
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multiplier = 1023;
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else {
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multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
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multiplier /= interrupt_rate;
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multiplier = (multiplier + round / 2) / round;
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multiplier = min(multiplier, (u32) 1023);
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}
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}
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return multiplier;
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}
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struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
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{
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return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
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}
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int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
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struct be_queue_info *eq, int eq_delay)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_cmd_req_eq_create *req = embedded_payload(wrb);
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struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
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struct be_dma_mem *q_mem = &eq->dma_mem;
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int status;
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spin_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
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be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
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OPCODE_COMMON_EQ_CREATE, sizeof(*req));
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req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
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AMAP_SET_BITS(struct amap_eq_context, func, req->context,
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PCI_FUNC(ctrl->pdev->devfn));
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AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
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AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
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AMAP_SET_BITS(struct amap_eq_context, count, req->context,
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__ilog2_u32(eq->len / 256));
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AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
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eq_delay_to_mult(eq_delay));
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be_dws_cpu_to_le(req->context, sizeof(req->context));
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be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
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status = be_mbox_notify(ctrl);
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if (!status) {
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eq->id = le16_to_cpu(resp->eq_id);
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eq->created = true;
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}
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spin_unlock(&ctrl->mbox_lock);
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return status;
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}
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int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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int status;
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u8 *endian_check;
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spin_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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endian_check = (u8 *) wrb;
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*endian_check++ = 0xFF;
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*endian_check++ = 0x12;
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*endian_check++ = 0x34;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xFF;
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*endian_check++ = 0x56;
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*endian_check++ = 0x78;
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*endian_check++ = 0xFF;
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be_dws_cpu_to_le(wrb, sizeof(*wrb));
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status = be_mbox_notify(ctrl);
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if (status)
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SE_DEBUG(DBG_LVL_1, "be_cmd_fw_initialize Failed \n");
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spin_unlock(&ctrl->mbox_lock);
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return status;
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}
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int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
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struct be_queue_info *cq, struct be_queue_info *eq,
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bool sol_evts, bool no_delay, int coalesce_wm)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_cmd_req_cq_create *req = embedded_payload(wrb);
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struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
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struct be_dma_mem *q_mem = &cq->dma_mem;
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void *ctxt = &req->context;
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int status;
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spin_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
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be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
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OPCODE_COMMON_CQ_CREATE, sizeof(*req));
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if (!q_mem->va)
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SE_DEBUG(DBG_LVL_1, "uninitialized q_mem->va\n");
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req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
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AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
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AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
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AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
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__ilog2_u32(cq->len / 256));
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AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
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AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
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AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
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AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
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AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
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AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
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PCI_FUNC(ctrl->pdev->devfn));
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be_dws_cpu_to_le(ctxt, sizeof(req->context));
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be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
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status = be_mbox_notify(ctrl);
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if (!status) {
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cq->id = le16_to_cpu(resp->cq_id);
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cq->created = true;
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} else
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SE_DEBUG(DBG_LVL_1, "In be_cmd_cq_create, status=ox%08x \n",
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status);
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spin_unlock(&ctrl->mbox_lock);
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return status;
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}
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static u32 be_encoded_q_len(int q_len)
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{
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u32 len_encoded = fls(q_len); /* log2(len) + 1 */
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if (len_encoded == 16)
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len_encoded = 0;
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return len_encoded;
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}
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int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
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int queue_type)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
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u8 subsys = 0, opcode = 0;
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int status;
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spin_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
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switch (queue_type) {
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case QTYPE_EQ:
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|
subsys = CMD_SUBSYSTEM_COMMON;
|
||
|
|
opcode = OPCODE_COMMON_EQ_DESTROY;
|
||
|
|
break;
|
||
|
|
case QTYPE_CQ:
|
||
|
|
subsys = CMD_SUBSYSTEM_COMMON;
|
||
|
|
opcode = OPCODE_COMMON_CQ_DESTROY;
|
||
|
|
break;
|
||
|
|
case QTYPE_WRBQ:
|
||
|
|
subsys = CMD_SUBSYSTEM_ISCSI;
|
||
|
|
opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
|
||
|
|
break;
|
||
|
|
case QTYPE_DPDUQ:
|
||
|
|
subsys = CMD_SUBSYSTEM_ISCSI;
|
||
|
|
opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
|
||
|
|
break;
|
||
|
|
case QTYPE_SGL:
|
||
|
|
subsys = CMD_SUBSYSTEM_ISCSI;
|
||
|
|
opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
spin_unlock(&ctrl->mbox_lock);
|
||
|
|
BUG();
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
|
||
|
|
if (queue_type != QTYPE_SGL)
|
||
|
|
req->id = cpu_to_le16(q->id);
|
||
|
|
|
||
|
|
status = be_mbox_notify(ctrl);
|
||
|
|
|
||
|
|
spin_unlock(&ctrl->mbox_lock);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
int be_cmd_get_mac_addr(struct be_ctrl_info *ctrl, u8 *mac_addr)
|
||
|
|
{
|
||
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||
|
|
struct be_cmd_req_get_mac_addr *req = embedded_payload(wrb);
|
||
|
|
int status;
|
||
|
|
|
||
|
|
spin_lock(&ctrl->mbox_lock);
|
||
|
|
memset(wrb, 0, sizeof(*wrb));
|
||
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
||
|
|
OPCODE_COMMON_ISCSI_NTWK_GET_NIC_CONFIG,
|
||
|
|
sizeof(*req));
|
||
|
|
|
||
|
|
status = be_mbox_notify(ctrl);
|
||
|
|
if (!status) {
|
||
|
|
struct be_cmd_resp_get_mac_addr *resp = embedded_payload(wrb);
|
||
|
|
|
||
|
|
memcpy(mac_addr, resp->mac_address, ETH_ALEN);
|
||
|
|
}
|
||
|
|
|
||
|
|
spin_unlock(&ctrl->mbox_lock);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
|
||
|
|
struct be_queue_info *cq,
|
||
|
|
struct be_queue_info *dq, int length,
|
||
|
|
int entry_size)
|
||
|
|
{
|
||
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||
|
|
struct be_defq_create_req *req = embedded_payload(wrb);
|
||
|
|
struct be_dma_mem *q_mem = &dq->dma_mem;
|
||
|
|
void *ctxt = &req->context;
|
||
|
|
int status;
|
||
|
|
|
||
|
|
spin_lock(&ctrl->mbox_lock);
|
||
|
|
memset(wrb, 0, sizeof(*wrb));
|
||
|
|
|
||
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||
|
|
|
||
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
||
|
|
OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
|
||
|
|
|
||
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
||
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context, rx_pdid, ctxt, 0);
|
||
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context, rx_pdid_valid, ctxt,
|
||
|
|
1);
|
||
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context, pci_func_id, ctxt,
|
||
|
|
PCI_FUNC(ctrl->pdev->devfn));
|
||
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context, ring_size, ctxt,
|
||
|
|
be_encoded_q_len(length / sizeof(struct phys_addr)));
|
||
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context, default_buffer_size,
|
||
|
|
ctxt, entry_size);
|
||
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context, cq_id_recv, ctxt,
|
||
|
|
cq->id);
|
||
|
|
|
||
|
|
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
||
|
|
|
||
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
||
|
|
|
||
|
|
status = be_mbox_notify(ctrl);
|
||
|
|
if (!status) {
|
||
|
|
struct be_defq_create_resp *resp = embedded_payload(wrb);
|
||
|
|
|
||
|
|
dq->id = le16_to_cpu(resp->id);
|
||
|
|
dq->created = true;
|
||
|
|
}
|
||
|
|
spin_unlock(&ctrl->mbox_lock);
|
||
|
|
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem,
|
||
|
|
struct be_queue_info *wrbq)
|
||
|
|
{
|
||
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||
|
|
struct be_wrbq_create_req *req = embedded_payload(wrb);
|
||
|
|
struct be_wrbq_create_resp *resp = embedded_payload(wrb);
|
||
|
|
int status;
|
||
|
|
|
||
|
|
spin_lock(&ctrl->mbox_lock);
|
||
|
|
memset(wrb, 0, sizeof(*wrb));
|
||
|
|
|
||
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||
|
|
|
||
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
||
|
|
OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
|
||
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
||
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
||
|
|
|
||
|
|
status = be_mbox_notify(ctrl);
|
||
|
|
if (!status)
|
||
|
|
wrbq->id = le16_to_cpu(resp->cid);
|
||
|
|
spin_unlock(&ctrl->mbox_lock);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
|
||
|
|
struct be_dma_mem *q_mem,
|
||
|
|
u32 page_offset, u32 num_pages)
|
||
|
|
{
|
||
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||
|
|
struct be_post_sgl_pages_req *req = embedded_payload(wrb);
|
||
|
|
int status;
|
||
|
|
unsigned int curr_pages;
|
||
|
|
u32 internal_page_offset = 0;
|
||
|
|
u32 temp_num_pages = num_pages;
|
||
|
|
|
||
|
|
if (num_pages == 0xff)
|
||
|
|
num_pages = 1;
|
||
|
|
|
||
|
|
spin_lock(&ctrl->mbox_lock);
|
||
|
|
do {
|
||
|
|
memset(wrb, 0, sizeof(*wrb));
|
||
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
||
|
|
OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
|
||
|
|
sizeof(*req));
|
||
|
|
curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
|
||
|
|
pages);
|
||
|
|
req->num_pages = min(num_pages, curr_pages);
|
||
|
|
req->page_offset = page_offset;
|
||
|
|
be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
|
||
|
|
q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
|
||
|
|
internal_page_offset += req->num_pages;
|
||
|
|
page_offset += req->num_pages;
|
||
|
|
num_pages -= req->num_pages;
|
||
|
|
|
||
|
|
if (temp_num_pages == 0xff)
|
||
|
|
req->num_pages = temp_num_pages;
|
||
|
|
|
||
|
|
status = be_mbox_notify(ctrl);
|
||
|
|
if (status) {
|
||
|
|
SE_DEBUG(DBG_LVL_1,
|
||
|
|
"FW CMD to map iscsi frags failed.\n");
|
||
|
|
goto error;
|
||
|
|
}
|
||
|
|
} while (num_pages > 0);
|
||
|
|
error:
|
||
|
|
spin_unlock(&ctrl->mbox_lock);
|
||
|
|
if (status != 0)
|
||
|
|
beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
|
||
|
|
return status;
|
||
|
|
}
|