355 lines
7.1 KiB
ArmAsm
355 lines
7.1 KiB
ArmAsm
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/*
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* linux/arch/m32r/mm/mmu.S
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*
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* Copyright (C) 2001 by Hiroyuki Kondo
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/smp.h>
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.text
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#ifdef CONFIG_MMU
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#include <asm/mmu_context.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/m32r.h>
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/*
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* TLB Miss Exception handler
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*/
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.balign 16
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ENTRY(tme_handler)
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.global tlb_entry_i_dat
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.global tlb_entry_d_dat
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SWITCH_TO_KERNEL_STACK
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#if defined(CONFIG_ISA_M32R2)
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st r0, @-sp
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st r1, @-sp
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st r2, @-sp
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st r3, @-sp
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seth r3, #high(MMU_REG_BASE)
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ld r1, @(MESTS_offset, r3) ; r1: status (MESTS reg.)
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ld r0, @(MDEVP_offset, r3) ; r0: PFN + ASID (MDEVP reg.)
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st r1, @(MESTS_offset, r3) ; clear status (MESTS reg.)
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and3 r1, r1, #(MESTS_IT)
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bnez r1, 1f ; instruction TLB miss?
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;; data TLB miss
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;; input
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;; r0: PFN + ASID (MDEVP reg.)
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;; r1 - r3: free
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;; output
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;; r0: PFN + ASID
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;; r1: TLB entry base address
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;; r2: &tlb_entry_{i|d}_dat
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;; r3: free
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#ifndef CONFIG_SMP
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seth r2, #high(tlb_entry_d_dat)
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or3 r2, r2, #low(tlb_entry_d_dat)
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#else /* CONFIG_SMP */
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ldi r1, #-8192
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seth r2, #high(tlb_entry_d_dat)
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or3 r2, r2, #low(tlb_entry_d_dat)
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and r1, sp
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ld r1, @(16, r1) ; current_thread_info->cpu
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slli r1, #2
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add r2, r1
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#endif /* !CONFIG_SMP */
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seth r1, #high(DTLB_BASE)
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or3 r1, r1, #low(DTLB_BASE)
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bra 2f
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.balign 16
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.fillinsn
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1:
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;; instrucntion TLB miss
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;; input
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;; r0: MDEVP reg. (included ASID)
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;; r1 - r3: free
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;; output
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;; r0: PFN + ASID
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;; r1: TLB entry base address
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;; r2: &tlb_entry_{i|d}_dat
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;; r3: free
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ldi r3, #-4096
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and3 r0, r0, #(MMU_CONTEXT_ASID_MASK)
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mvfc r1, bpc
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and r1, r3
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or r0, r1 ; r0: PFN + ASID
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#ifndef CONFIG_SMP
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seth r2, #high(tlb_entry_i_dat)
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or3 r2, r2, #low(tlb_entry_i_dat)
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#else /* CONFIG_SMP */
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ldi r1, #-8192
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seth r2, #high(tlb_entry_i_dat)
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or3 r2, r2, #low(tlb_entry_i_dat)
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and r1, sp
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ld r1, @(16, r1) ; current_thread_info->cpu
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slli r1, #2
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add r2, r1
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#endif /* !CONFIG_SMP */
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seth r1, #high(ITLB_BASE)
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or3 r1, r1, #low(ITLB_BASE)
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.fillinsn
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2:
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;; select TLB entry
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;; input
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;; r0: PFN + ASID
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;; r1: TLB entry base address
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;; r2: &tlb_entry_{i|d}_dat
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;; r3: free
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;; output
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;; r0: PFN + ASID
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;; r1: TLB entry address
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;; r2, r3: free
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#ifdef CONFIG_ISA_DUAL_ISSUE
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ld r3, @r2 || srli r1, #3
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#else
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ld r3, @r2
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srli r1, #3
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#endif
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add r1, r3
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; tlb_entry_{d|i}_dat++;
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addi r3, #1
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and3 r3, r3, #(NR_TLB_ENTRIES - 1)
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#ifdef CONFIG_ISA_DUAL_ISSUE
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st r3, @r2 || slli r1, #3
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#else
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st r3, @r2
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slli r1, #3
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#endif
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;; load pte
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;; input
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;; r0: PFN + ASID
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;; r1: TLB entry address
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;; r2, r3: free
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;; output
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;; r0: PFN + ASID
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;; r1: TLB entry address
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;; r2: pte_data
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;; r3: free
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; pgd = *(unsigned long *)MPTB;
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ld24 r2, #(-MPTB - 1)
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srl3 r3, r0, #22
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#ifdef CONFIG_ISA_DUAL_ISSUE
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not r2, r2 || slli r3, #2 ; r3: pgd offset
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#else
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not r2, r2
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slli r3, #2
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#endif
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ld r2, @r2 ; r2: pgd base addr (MPTB reg.)
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or r3, r2 ; r3: pmd addr
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; pmd = pmd_offset(pgd, address);
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ld r3, @r3 ; r3: pmd data
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beqz r3, 3f ; pmd_none(*pmd) ?
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and3 r2, r3, #0xfff
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add3 r2, r2, #-355 ; _KERNPG_TABLE(=0x163)
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bnez r2, 3f ; pmd_bad(*pmd) ?
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ldi r2, #-4096
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; pte = pte_offset(pmd, address);
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and r2, r3 ; r2: pte base addr
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srl3 r3, r0, #10
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and3 r3, r3, #0xffc ; r3: pte offset
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or r3, r2
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seth r2, #0x8000
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or r3, r2 ; r3: pte addr
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; pte_data = (unsigned long)pte_val(*pte);
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ld r2, @r3 ; r2: pte data
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and3 r3, r2, #2 ; _PAGE_PRESENT(=2) check
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beqz r3, 3f
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.fillinsn
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5:
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;; set tlb
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;; input
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;; r0: PFN + ASID
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;; r1: TLB entry address
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;; r2: pte_data
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;; r3: free
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st r0, @r1 ; set_tlb_tag(entry++, address);
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st r2, @+r1 ; set_tlb_data(entry, pte_data);
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.fillinsn
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6:
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ld r3, @sp+
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ld r2, @sp+
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ld r1, @sp+
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ld r0, @sp+
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rte
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.fillinsn
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3:
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;; error
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;; input
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;; r0: PFN + ASID
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;; r1: TLB entry address
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;; r2, r3: free
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;; output
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;; r0: PFN + ASID
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;; r1: TLB entry address
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;; r2: pte_data
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;; r3: free
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#ifdef CONFIG_ISA_DUAL_ISSUE
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bra 5b || ldi r2, #2
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#else
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ldi r2, #2 ; r2: pte_data = 0 | _PAGE_PRESENT(=2)
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bra 5b
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#endif
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#elif defined (CONFIG_ISA_M32R)
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st sp, @-sp
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st r0, @-sp
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st r1, @-sp
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st r2, @-sp
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st r3, @-sp
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st r4, @-sp
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seth r3, #high(MMU_REG_BASE)
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ld r0, @(MDEVA_offset,r3) ; r0: address (MDEVA reg.)
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mvfc r2, bpc ; r2: bpc
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ld r1, @(MESTS_offset,r3) ; r1: status (MESTS reg.)
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st r1, @(MESTS_offset,r3) ; clear status (MESTS reg.)
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and3 r1, r1, #(MESTS_IT)
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beqz r1, 1f ; data TLB miss?
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;; instrucntion TLB miss
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mv r0, r2 ; address = bpc;
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; entry = (unsigned long *)ITLB_BASE+tlb_entry_i*2;
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seth r3, #shigh(tlb_entry_i_dat)
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ld r4, @(low(tlb_entry_i_dat),r3)
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sll3 r2, r4, #3
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seth r1, #high(ITLB_BASE)
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or3 r1, r1, #low(ITLB_BASE)
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add r2, r1 ; r2: entry
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addi r4, #1 ; tlb_entry_i++;
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and3 r4, r4, #(NR_TLB_ENTRIES-1)
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st r4, @(low(tlb_entry_i_dat),r3)
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bra 2f
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.fillinsn
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1:
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;; data TLB miss
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; entry = (unsigned long *)DTLB_BASE+tlb_entry_d*2;
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seth r3, #shigh(tlb_entry_d_dat)
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ld r4, @(low(tlb_entry_d_dat),r3)
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sll3 r2, r4, #3
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seth r1, #high(DTLB_BASE)
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or3 r1, r1, #low(DTLB_BASE)
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add r2, r1 ; r2: entry
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addi r4, #1 ; tlb_entry_d++;
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and3 r4, r4, #(NR_TLB_ENTRIES-1)
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st r4, @(low(tlb_entry_d_dat),r3)
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.fillinsn
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2:
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;; load pte
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; r0: address, r2: entry
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; r1,r3,r4: (free)
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; pgd = *(unsigned long *)MPTB;
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ld24 r1, #(-MPTB-1)
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not r1, r1
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ld r1, @r1
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srl3 r4, r0, #22
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sll3 r3, r4, #2
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add r3, r1 ; r3: pgd
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; pmd = pmd_offset(pgd, address);
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ld r1, @r3 ; r1: pmd
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beqz r1, 3f ; pmd_none(*pmd) ?
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;
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and3 r1, r1, #0x3ff
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ldi r4, #0x163 ; _KERNPG_TABLE(=0x163)
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bne r1, r4, 3f ; pmd_bad(*pmd) ?
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.fillinsn
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4:
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; pte = pte_offset(pmd, address);
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ld r4, @r3 ; r4: pte
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ldi r3, #-4096
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and r4, r3
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srl3 r3, r0, #10
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and3 r3, r3, #0xffc
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add r4, r3
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seth r3, #0x8000
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add r4, r3 ; r4: pte
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; pte_data = (unsigned long)pte_val(*pte);
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ld r1, @r4 ; r1: pte_data
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and3 r3, r1, #2 ; _PAGE_PRESENT(=2) check
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beqz r3, 3f
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.fillinsn
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;; set tlb
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; r0: address, r1: pte_data, r2: entry
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; r3,r4: (free)
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5:
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ldi r3, #-4096 ; set_tlb_tag(entry++, address);
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and r3, r0
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seth r4, #shigh(MASID)
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ld r4, @(low(MASID),r4) ; r4: MASID
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and3 r4, r4, #(MMU_CONTEXT_ASID_MASK)
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or r3, r4
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st r3, @r2
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st r1, @(4,r2) ; set_tlb_data(entry, pte_data);
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ld r4, @sp+
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ld r3, @sp+
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ld r2, @sp+
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ld r1, @sp+
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ld r0, @sp+
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ld sp, @sp+
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rte
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.fillinsn
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3:
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ldi r1, #2 ; r1: pte_data = 0 | _PAGE_PRESENT(=2)
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bra 5b
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#else
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#error unknown isa configuration
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#endif
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ENTRY(init_tlb)
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;; Set MMU Register
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seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
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or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
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ldi r1, #0
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st r1, @(MPSZ_offset,r0) ; Set MPSZ Reg(Page size 4KB:0 16KB:1 64KB:2)
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ldi r1, #0
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st r1, @(MASID_offset,r0) ; Set ASID Zero
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;; Set TLB
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seth r0, #high(ITLB_BASE) ; Set ITLB_BASE higher
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or3 r0, r0, #low(ITLB_BASE) ; Set ITLB_BASE lower
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seth r1, #high(DTLB_BASE) ; Set DTLB_BASE higher
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or3 r1, r1, #low(DTLB_BASE) ; Set DTLB_BASE lower
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ldi r2, #0
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ldi r3, #NR_TLB_ENTRIES
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addi r0, #-4
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addi r1, #-4
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clear_tlb:
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st r2, @+r0 ; VPA <- 0
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st r2, @+r0 ; PPA <- 0
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st r2, @+r1 ; VPA <- 0
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st r2, @+r1 ; PPA <- 0
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addi r3, #-1
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bnez r3, clear_tlb
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;;
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jmp r14
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ENTRY(m32r_itlb_entrys)
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ENTRY(m32r_otlb_entrys)
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#endif /* CONFIG_MMU */
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||
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|
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||
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.end
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