74 lines
4.1 KiB
Plaintext
74 lines
4.1 KiB
Plaintext
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Freescale Synchronous Serial Interface
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The SSI is a serial device that communicates with audio codecs. It can
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be programmed in AC97, I2S, left-justified, or right-justified modes.
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Required properties:
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- compatible: Compatible list, contains "fsl,ssi".
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- cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
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- reg: Offset and length of the register set for the device.
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- interrupts: <a b> where a is the interrupt number and b is a
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field that represents an encoding of the sense and
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level information for the interrupt. This should be
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encoded based on the information in section 2)
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depending on the type of interrupt controller you
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have.
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- interrupt-parent: The phandle for the interrupt controller that
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services interrupts for this device.
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- fsl,mode: The operating mode for the SSI interface.
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"i2s-slave" - I2S mode, SSI is clock slave
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"i2s-master" - I2S mode, SSI is clock master
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"lj-slave" - left-justified mode, SSI is clock slave
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"lj-master" - l.j. mode, SSI is clock master
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"rj-slave" - right-justified mode, SSI is clock slave
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"rj-master" - r.j., SSI is clock master
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"ac97-slave" - AC97 mode, SSI is clock slave
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"ac97-master" - AC97 mode, SSI is clock master
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- fsl,playback-dma: Phandle to a node for the DMA channel to use for
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playback of audio. This is typically dictated by SOC
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design. See the notes below.
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- fsl,capture-dma: Phandle to a node for the DMA channel to use for
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capture (recording) of audio. This is typically dictated
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by SOC design. See the notes below.
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- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
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This number is the maximum allowed value for SFCSR[TFWM0].
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- fsl,ssi-asynchronous:
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If specified, the SSI is to be programmed in asynchronous
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mode. In this mode, pins SRCK, STCK, SRFS, and STFS must
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all be connected to valid signals. In synchronous mode,
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SRCK and SRFS are ignored. Asynchronous mode allows
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playback and capture to use different sample sizes and
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sample rates. Some drivers may require that SRCK and STCK
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be connected together, and SRFS and STFS be connected
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together. This would still allow different sample sizes,
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but not different sample rates.
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Optional properties:
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- codec-handle: Phandle to a 'codec' node that defines an audio
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codec connected to this SSI. This node is typically
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a child of an I2C or other control node.
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Child 'codec' node required properties:
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- compatible: Compatible list, contains the name of the codec
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Child 'codec' node optional properties:
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- clock-frequency: The frequency of the input clock, which typically comes
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from an on-board dedicated oscillator.
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Notes on fsl,playback-dma and fsl,capture-dma:
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On SOCs that have an SSI, specific DMA channels are hard-wired for playback
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and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
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playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
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playback and DMA channel 3 for capture. The developer can choose which
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DMA controller to use, but the channels themselves are hard-wired. The
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purpose of these two properties is to represent this hardware design.
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The device tree nodes for the DMA channels that are referenced by
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"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
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"fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
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"fsl,mpc8610-dma-channel") can remain. If these nodes are left as
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"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
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drivers (fsldma) will attempt to use them, and it will conflict with the
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sound drivers.
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