297 lines
8.2 KiB
C
297 lines
8.2 KiB
C
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/*
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* vpif - DM646x Video Port Interface driver
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* VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
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* that receiveing video byte stream and two channels(2, 3) for video output.
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* The hardware supports SDTV, HDTV formats, raw data capture.
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* Currently, the driver supports NTSC and PAL standards.
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*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed .as is. WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include "vpif.h"
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MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
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MODULE_LICENSE("GPL");
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#define VPIF_CH0_MAX_MODES (22)
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#define VPIF_CH1_MAX_MODES (02)
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#define VPIF_CH2_MAX_MODES (15)
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#define VPIF_CH3_MAX_MODES (02)
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static resource_size_t res_len;
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static struct resource *res;
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spinlock_t vpif_lock;
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void __iomem *vpif_base;
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static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
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{
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if (val)
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vpif_set_bit(reg, bit);
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else
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vpif_clr_bit(reg, bit);
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}
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/* This structure is used to keep track of VPIF size register's offsets */
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struct vpif_registers {
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u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
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u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
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u32 vanc1_size, width_mask, len_mask;
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u8 max_modes;
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};
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static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
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/* Channel0 */
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{
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VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
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VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
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VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
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VPIF_CH0_MAX_MODES,
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},
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/* Channel1 */
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{
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VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
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VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
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VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
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VPIF_CH1_MAX_MODES,
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},
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/* Channel2 */
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{
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VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
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VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
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VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
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VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
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VPIF_CH2_MAX_MODES
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},
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/* Channel3 */
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{
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VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
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VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
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VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
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VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
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VPIF_CH3_MAX_MODES
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},
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};
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/* vpif_set_mode_info:
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* This function is used to set horizontal and vertical config parameters
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* As per the standard in the channel, configure the values of L1, L3,
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* L5, L7 L9, L11 in VPIF Register , also write width and height
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*/
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static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
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u8 channel_id, u8 config_channel_id)
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{
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u32 value;
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value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
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value <<= VPIF_CH_LEN_SHIFT;
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value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
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regw(value, vpifregs[channel_id].h_cfg);
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value = (config->l1 & vpifregs[config_channel_id].len_mask);
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value <<= VPIF_CH_LEN_SHIFT;
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value |= (config->l3 & vpifregs[config_channel_id].len_mask);
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regw(value, vpifregs[channel_id].v_cfg_00);
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value = (config->l5 & vpifregs[config_channel_id].len_mask);
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value <<= VPIF_CH_LEN_SHIFT;
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value |= (config->l7 & vpifregs[config_channel_id].len_mask);
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regw(value, vpifregs[channel_id].v_cfg_01);
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value = (config->l9 & vpifregs[config_channel_id].len_mask);
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value <<= VPIF_CH_LEN_SHIFT;
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value |= (config->l11 & vpifregs[config_channel_id].len_mask);
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regw(value, vpifregs[channel_id].v_cfg_02);
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value = (config->vsize & vpifregs[config_channel_id].len_mask);
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regw(value, vpifregs[channel_id].v_cfg);
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}
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/* config_vpif_params
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* Function to set the parameters of a channel
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* Mainly modifies the channel ciontrol register
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* It sets frame format, yc mux mode
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*/
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static void config_vpif_params(struct vpif_params *vpifparams,
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u8 channel_id, u8 found)
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{
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const struct vpif_channel_config_params *config = &vpifparams->std_info;
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u32 value, ch_nip, reg;
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u8 start, end;
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int i;
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start = channel_id;
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end = channel_id + found;
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for (i = start; i < end; i++) {
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reg = vpifregs[i].ch_ctrl;
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if (channel_id < 2)
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ch_nip = VPIF_CAPTURE_CH_NIP;
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else
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ch_nip = VPIF_DISPLAY_CH_NIP;
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vpif_wr_bit(reg, ch_nip, config->frm_fmt);
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vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
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vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
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vpifparams->video_params.storage_mode);
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/* Set raster scanning SDR Format */
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vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
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vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
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if (channel_id > 1) /* Set the Pixel enable bit */
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vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
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else if (config->capture_format) {
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/* Set the polarity of various pins */
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vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
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vpifparams->iface.fid_pol);
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vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
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vpifparams->iface.vd_pol);
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vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
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vpifparams->iface.hd_pol);
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value = regr(reg);
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/* Set data width */
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value &= ((~(unsigned int)(0x3)) <<
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VPIF_CH_DATA_WIDTH_BIT);
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value |= ((vpifparams->params.data_sz) <<
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VPIF_CH_DATA_WIDTH_BIT);
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regw(value, reg);
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}
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/* Write the pitch in the driver */
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regw((vpifparams->video_params.hpitch),
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vpifregs[i].line_offset);
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}
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}
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/* vpif_set_video_params
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* This function is used to set video parameters in VPIF register
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*/
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int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
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{
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const struct vpif_channel_config_params *config = &vpifparams->std_info;
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int found = 1;
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vpif_set_mode_info(config, channel_id, channel_id);
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if (!config->ycmux_mode) {
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/* YC are on separate channels (HDTV formats) */
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vpif_set_mode_info(config, channel_id + 1, channel_id);
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found = 2;
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}
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config_vpif_params(vpifparams, channel_id, found);
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regw(0x80, VPIF_REQ_SIZE);
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regw(0x01, VPIF_EMULATION_CTRL);
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return found;
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}
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EXPORT_SYMBOL(vpif_set_video_params);
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void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
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u8 channel_id)
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{
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u32 value;
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value = 0x3F8 & (vbiparams->hstart0);
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value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
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regw(value, vpifregs[channel_id].vanc0_strt);
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value = 0x3F8 & (vbiparams->hstart1);
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value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
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regw(value, vpifregs[channel_id].vanc1_strt);
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value = 0x3F8 & (vbiparams->hsize0);
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value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
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regw(value, vpifregs[channel_id].vanc0_size);
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value = 0x3F8 & (vbiparams->hsize1);
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value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
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regw(value, vpifregs[channel_id].vanc1_size);
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}
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EXPORT_SYMBOL(vpif_set_vbi_display_params);
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int vpif_channel_getfid(u8 channel_id)
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{
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return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
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>> VPIF_CH_FID_SHIFT;
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}
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EXPORT_SYMBOL(vpif_channel_getfid);
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static int __init vpif_probe(struct platform_device *pdev)
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{
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int status = 0;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENOENT;
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res_len = res->end - res->start + 1;
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res = request_mem_region(res->start, res_len, res->name);
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if (!res)
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return -EBUSY;
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vpif_base = ioremap(res->start, res_len);
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if (!vpif_base) {
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status = -EBUSY;
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goto fail;
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}
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spin_lock_init(&vpif_lock);
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dev_info(&pdev->dev, "vpif probe success\n");
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return 0;
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fail:
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release_mem_region(res->start, res_len);
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return status;
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}
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static int vpif_remove(struct platform_device *pdev)
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{
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iounmap(vpif_base);
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release_mem_region(res->start, res_len);
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return 0;
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}
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static struct platform_driver vpif_driver = {
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.driver = {
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.name = "vpif",
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.owner = THIS_MODULE,
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},
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.remove = __devexit_p(vpif_remove),
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.probe = vpif_probe,
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};
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static void vpif_exit(void)
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{
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platform_driver_unregister(&vpif_driver);
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}
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static int __init vpif_init(void)
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{
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return platform_driver_register(&vpif_driver);
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}
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subsys_initcall(vpif_init);
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module_exit(vpif_exit);
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