163 lines
6.4 KiB
C
163 lines
6.4 KiB
C
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/*
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*
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* IPACX specific defines
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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/* All Registers original Siemens Spec */
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#ifndef INCLUDE_IPACX_H
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#define INCLUDE_IPACX_H
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/* D-channel registers */
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#define IPACX_RFIFOD 0x00 /* RD */
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#define IPACX_XFIFOD 0x00 /* WR */
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#define IPACX_ISTAD 0x20 /* RD */
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#define IPACX_MASKD 0x20 /* WR */
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#define IPACX_STARD 0x21 /* RD */
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#define IPACX_CMDRD 0x21 /* WR */
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#define IPACX_MODED 0x22 /* RD/WR */
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#define IPACX_EXMD1 0x23 /* RD/WR */
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#define IPACX_TIMR1 0x24 /* RD/WR */
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#define IPACX_SAP1 0x25 /* WR */
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#define IPACX_SAP2 0x26 /* WR */
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#define IPACX_RBCLD 0x26 /* RD */
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#define IPACX_RBCHD 0x27 /* RD */
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#define IPACX_TEI1 0x27 /* WR */
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#define IPACX_TEI2 0x28 /* WR */
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#define IPACX_RSTAD 0x28 /* RD */
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#define IPACX_TMD 0x29 /* RD/WR */
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#define IPACX_CIR0 0x2E /* RD */
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#define IPACX_CIX0 0x2E /* WR */
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#define IPACX_CIR1 0x2F /* RD */
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#define IPACX_CIX1 0x2F /* WR */
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/* Transceiver registers */
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#define IPACX_TR_CONF0 0x30 /* RD/WR */
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#define IPACX_TR_CONF1 0x31 /* RD/WR */
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#define IPACX_TR_CONF2 0x32 /* RD/WR */
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#define IPACX_TR_STA 0x33 /* RD */
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#define IPACX_TR_CMD 0x34 /* RD/WR */
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#define IPACX_SQRR1 0x35 /* RD */
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#define IPACX_SQXR1 0x35 /* WR */
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#define IPACX_SQRR2 0x36 /* RD */
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#define IPACX_SQXR2 0x36 /* WR */
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#define IPACX_SQRR3 0x37 /* RD */
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#define IPACX_SQXR3 0x37 /* WR */
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#define IPACX_ISTATR 0x38 /* RD */
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#define IPACX_MASKTR 0x39 /* RD/WR */
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#define IPACX_TR_MODE 0x3A /* RD/WR */
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#define IPACX_ACFG1 0x3C /* RD/WR */
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#define IPACX_ACFG2 0x3D /* RD/WR */
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#define IPACX_AOE 0x3E /* RD/WR */
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#define IPACX_ARX 0x3F /* RD */
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#define IPACX_ATX 0x3F /* WR */
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/* IOM: Timeslot, DPS, CDA */
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#define IPACX_CDA10 0x40 /* RD/WR */
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#define IPACX_CDA11 0x41 /* RD/WR */
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#define IPACX_CDA20 0x42 /* RD/WR */
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#define IPACX_CDA21 0x43 /* RD/WR */
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#define IPACX_CDA_TSDP10 0x44 /* RD/WR */
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#define IPACX_CDA_TSDP11 0x45 /* RD/WR */
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#define IPACX_CDA_TSDP20 0x46 /* RD/WR */
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#define IPACX_CDA_TSDP21 0x47 /* RD/WR */
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#define IPACX_BCHA_TSDP_BC1 0x48 /* RD/WR */
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#define IPACX_BCHA_TSDP_BC2 0x49 /* RD/WR */
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#define IPACX_BCHB_TSDP_BC1 0x4A /* RD/WR */
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#define IPACX_BCHB_TSDP_BC2 0x4B /* RD/WR */
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#define IPACX_TR_TSDP_BC1 0x4C /* RD/WR */
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#define IPACX_TR_TSDP_BC2 0x4D /* RD/WR */
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#define IPACX_CDA1_CR 0x4E /* RD/WR */
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#define IPACX_CDA2_CR 0x4F /* RD/WR */
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/* IOM: Contol, Sync transfer, Monitor */
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#define IPACX_TR_CR 0x50 /* RD/WR */
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#define IPACX_TRC_CR 0x50 /* RD/WR */
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#define IPACX_BCHA_CR 0x51 /* RD/WR */
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#define IPACX_BCHB_CR 0x52 /* RD/WR */
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#define IPACX_DCI_CR 0x53 /* RD/WR */
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#define IPACX_DCIC_CR 0x53 /* RD/WR */
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#define IPACX_MON_CR 0x54 /* RD/WR */
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#define IPACX_SDS1_CR 0x55 /* RD/WR */
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#define IPACX_SDS2_CR 0x56 /* RD/WR */
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#define IPACX_IOM_CR 0x57 /* RD/WR */
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#define IPACX_STI 0x58 /* RD */
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#define IPACX_ASTI 0x58 /* WR */
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#define IPACX_MSTI 0x59 /* RD/WR */
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#define IPACX_SDS_CONF 0x5A /* RD/WR */
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#define IPACX_MCDA 0x5B /* RD */
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#define IPACX_MOR 0x5C /* RD */
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#define IPACX_MOX 0x5C /* WR */
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#define IPACX_MOSR 0x5D /* RD */
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#define IPACX_MOCR 0x5E /* RD/WR */
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#define IPACX_MSTA 0x5F /* RD */
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#define IPACX_MCONF 0x5F /* WR */
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/* Interrupt and general registers */
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#define IPACX_ISTA 0x60 /* RD */
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#define IPACX_MASK 0x60 /* WR */
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#define IPACX_AUXI 0x61 /* RD */
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#define IPACX_AUXM 0x61 /* WR */
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#define IPACX_MODE1 0x62 /* RD/WR */
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#define IPACX_MODE2 0x63 /* RD/WR */
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#define IPACX_ID 0x64 /* RD */
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#define IPACX_SRES 0x64 /* WR */
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#define IPACX_TIMR2 0x65 /* RD/WR */
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/* B-channel registers */
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#define IPACX_OFF_B1 0x70
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#define IPACX_OFF_B2 0x80
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#define IPACX_ISTAB 0x00 /* RD */
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#define IPACX_MASKB 0x00 /* WR */
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#define IPACX_STARB 0x01 /* RD */
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#define IPACX_CMDRB 0x01 /* WR */
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#define IPACX_MODEB 0x02 /* RD/WR */
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#define IPACX_EXMB 0x03 /* RD/WR */
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#define IPACX_RAH1 0x05 /* WR */
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#define IPACX_RAH2 0x06 /* WR */
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#define IPACX_RBCLB 0x06 /* RD */
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#define IPACX_RBCHB 0x07 /* RD */
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#define IPACX_RAL1 0x07 /* WR */
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#define IPACX_RAL2 0x08 /* WR */
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#define IPACX_RSTAB 0x08 /* RD */
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#define IPACX_TMB 0x09 /* RD/WR */
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#define IPACX_RFIFOB 0x0A /*- RD */
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#define IPACX_XFIFOB 0x0A /*- WR */
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/* Layer 1 Commands */
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#define IPACX_CMD_TIM 0x0
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#define IPACX_CMD_RES 0x1
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#define IPACX_CMD_SSP 0x2
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#define IPACX_CMD_SCP 0x3
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#define IPACX_CMD_AR8 0x8
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#define IPACX_CMD_AR10 0x9
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#define IPACX_CMD_ARL 0xa
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#define IPACX_CMD_DI 0xf
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/* Layer 1 Indications */
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#define IPACX_IND_DR 0x0
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#define IPACX_IND_RES 0x1
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#define IPACX_IND_TMA 0x2
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#define IPACX_IND_SLD 0x3
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#define IPACX_IND_RSY 0x4
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#define IPACX_IND_DR6 0x5
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#define IPACX_IND_PU 0x7
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#define IPACX_IND_AR 0x8
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#define IPACX_IND_ARL 0xa
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#define IPACX_IND_CVR 0xb
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#define IPACX_IND_AI8 0xc
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#define IPACX_IND_AI10 0xd
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#define IPACX_IND_AIL 0xe
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#define IPACX_IND_DC 0xf
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extern void init_ipacx(struct IsdnCardState *, int);
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extern void interrupt_ipacx(struct IsdnCardState *);
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extern void setup_isac(struct IsdnCardState *);
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#endif
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