127 lines
4.7 KiB
C
127 lines
4.7 KiB
C
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/*****************************************************************************
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*
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* File name : clock-regs-fli7510.h
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* Description : Low Level API - Base addresses & register definitions.
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*
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* COPYRIGHT (C) 2011 STMicroelectronics - All Rights Reserved
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* May be copied or modified under the terms of the GNU General Public
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* License V2 _ONLY_. See linux/COPYING for more information.
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*
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*****************************************************************************/
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#ifndef __CLOCK_LLA_REGS_H
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#define __CLOCK_LLA_REGS_H
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/* --- Base addresses ---------------------------------------- */
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#define CKGA_BASE_ADDRESS 0xfde00000
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/* --- CKGA registers --- */
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#define CKGA_PLL0_CFG 0x000
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#define CKGA_PLL1_CFG 0x004
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#define CKGA_POWER_CFG 0x010
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#define CKGA_CLKOPSRC_SWITCH_CFG 0x014
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#define CKGA_OSC_ENABLE_FB 0x018
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#define CKGA_PLL0_ENABLE_FB 0x01c
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#define CKGA_PLL1_ENABLE_FB 0x020
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#define CKGA_CLKOPSRC_SWITCH_CFG2 0x024
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#define CKGA_CLKOBS_MUX1_CFG 0x030
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#define CKGA_CLKOBS_MASTER_MAXCOUNT 0x034
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#define CKGA_CLKOBS_CMD 0x038
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#define CKGA_CLKOBS_STATUS 0x03c
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#define CKGA_CLKOBS_SLAVE0_COUNT 0x040
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#define CKGA_OSCMUX_DEBUG 0x044
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#define CKGA_CLKOBS_MUX2_CFG 0x048
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#define CKGA_LOW_POWER_CTRL 0x04C
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/*
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* The CKGA_SOURCE_CFG(..) replaces the
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* - CKGA_OSC_DIV0_CFG
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* - CKGA_PLL0HS_DIV0_CFG
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* - CKGA_PLL0LS_DIV0_CFG
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* - CKGA_PLL1_DIV0_CFG
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* macros.
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* The _parent_id identifies the parent as:
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* - 0: OSC
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* - 1: PLL0_HS
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* - 2: PLL0_LS
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* - 3: PLL1
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*/
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#define CKGA_SOURCE_CFG(_parent_id) (0x800 + (_parent_id) * 0x100)
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/*
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* Audio clockgen ---------------------------------------------------------
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* Original Code from Pawel Moll
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*/
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#define CTL_EN(base) ((base) + 0x00)
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#define EN_CLK_512FS_FREE_RUN 0
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#define EN_CLK_512FS_FREE_RUN__DISABLED (0 << EN_CLK_512FS_FREE_RUN)
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#define EN_CLK_512FS_FREE_RUN__ENABLED (1 << EN_CLK_512FS_FREE_RUN)
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#define EN_CLK_256FS_FREE_RUN 1
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#define EN_CLK_256FS_FREE_RUN__DISABLED (0 << EN_CLK_256FS_FREE_RUN)
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#define EN_CLK_256FS_FREE_RUN__ENABLED (1 << EN_CLK_256FS_FREE_RUN)
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#define EN_CLK_FS_FREE_RUN 2
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#define EN_CLK_FS_FREE_RUN__DISABLED (0 << EN_CLK_FS_FREE_RUN)
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#define EN_CLK_FS_FREE_RUN__ENABLED (1 << EN_CLK_FS_FREE_RUN)
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#define EN_CLK_256FS_DEC_1 3
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#define EN_CLK_256FS_DEC_1__DISABLED (0 << EN_CLK_256FS_DEC_1)
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#define EN_CLK_256FS_DEC_1__ENABLED (1 << EN_CLK_256FS_DEC_1)
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#define EN_CLK_FS_DEC_1 4
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#define EN_CLK_FS_DEC_1__DISABLED (0 << EN_CLK_FS_DEC_1)
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#define EN_CLK_FS_DEC_1__ENABLED (1 << EN_CLK_FS_DEC_1)
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#define EN_CLK_SPDIF_RX 5
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#define EN_CLK_SPDIF_RX__DISABLED (0 << EN_CLK_SPDIF_RX)
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#define EN_CLK_SPDIF_RX__ENABLED (1 << EN_CLK_SPDIF_RX)
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#define EN_CLK_256FS_DEC_2 6
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#define EN_CLK_256FS_DEC_2__DISABLED (0 << EN_CLK_256FS_DEC_2)
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#define EN_CLK_256FS_DEC_2__ENABLED (1 << EN_CLK_256FS_DEC_2)
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#define EN_CLK_FS_DEC_2 7
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#define EN_CLK_FS_DEC_2__DISABLED (0 << EN_CLK_FS_DEC_2)
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#define EN_CLK_FS_DEC_2__ENABLED (1 << EN_CLK_FS_DEC_2)
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#define CTL_SYNTH4X_AUD(base) ((base) + 0x04)
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#define SYNTH4X_AUD_NDIV 0
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#define SYNTH4X_AUD_NDIV__30_MHZ (0 << SYNTH4X_AUD_NDIV)
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#define SYNTH4X_AUD_NDIV__60_MHZ (1 << SYNTH4X_AUD_NDIV)
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#define SYNTH4X_AUD_SELCLKIN 1
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#define SYNTH4X_AUD_SELCLKIN__CLKIN2V5 (0 << SYNTH4X_AUD_SELCLKIN)
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#define SYNTH4X_AUD_SELCLKIN__CLKIN1V2 (1 << SYNTH4X_AUD_SELCLKIN)
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#define SYNTH4X_AUD_SELBW 2
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#define SYNTH4X_AUD_SELBW__VERY_GOOD_REFERENCE (0 << SYNTH4X_AUD_SELBW)
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#define SYNTH4X_AUD_SELBW__GOOD_REFERENCE (1 << SYNTH4X_AUD_SELBW)
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#define SYNTH4X_AUD_SELBW__BAD_REFERENCE (2 << SYNTH4X_AUD_SELBW)
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#define SYNTH4X_AUD_SELBW__VERY_BAD_REFERENCE (3 << SYNTH4X_AUD_SELBW)
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#define SYNTH4X_AUD_NPDA 4
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#define SYNTH4X_AUD_NPDA__POWER_DOWN (0 << SYNTH4X_AUD_NPDA)
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#define SYNTH4X_AUD_NPDA__ACTIVE (1 << SYNTH4X_AUD_NPDA)
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#define SYNTH4X_AUD_NRST 5
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#define SYNTH4X_AUD_NRST__MASK (1 << SYNTH4X_AUD_NRST)
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#define SYNTH4X_AUD_NRST__RESET (0 << SYNTH4X_AUD_NRST)
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#define SYNTH4X_AUD_NRST__NORMAL (1 << SYNTH4X_AUD_NRST)
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/* Warning! Registers spec defines these registers as 1 ... 4,
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* instead of 0 ... 3! */
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#define CTL_SYNTH4X_AUD_N(base, n) ((base) + 0x08 + ((n - 1) * 0x4))
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#define MD 0
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#define MD__MASK (0x1f << MD)
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#define MD__(value) (((value) << MD) & MD__MASK)
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#define SDIV 5
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#define SDIV__MASK (0x7 << SDIV)
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#define SDIV__(value) (((value) << SDIV) & SDIV__MASK)
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#define PE 8
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#define PE__MASK (0xffff << PE)
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#define PE__(value) (((value) << PE) & PE__MASK)
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#define SEL_CLK_OUT 24
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#define SEL_CLK_OUT__EXTCLK (0 << SEL_CLK_OUT)
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#define SEL_CLK_OUT__FSYNTH (1 << SEL_CLK_OUT)
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#define NSB 25
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#define NSB__MASK (1 << NSB)
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#define NSB__STANDBY (0 << NSB)
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#define NSB__ACTIVE (1 << NSB)
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#define NSDIV3 26
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#define NSDIV3__ACTIVE (0 << NSDIV3)
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#define NSDIV3__BYPASSED (1 << NSDIV3)
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#endif /* End __CLOCK_LLA_REGS_H */
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