416 lines
15 KiB
C
416 lines
15 KiB
C
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/*
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* Amiga Linux/m68k Ariadne Ethernet Driver
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*
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* © Copyright 1995 by Geert Uytterhoeven (geert@linux-m68k.org)
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* Peter De Schrijver
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* (Peter.DeSchrijver@linux.cc.kuleuven.ac.be)
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*
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* ----------------------------------------------------------------------------------
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*
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* This program is based on
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*
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* lance.c: An AMD LANCE ethernet driver for linux.
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* Written 1993-94 by Donald Becker.
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*
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* Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller
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* Advanced Micro Devices
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* Publication #16907, Rev. B, Amendment/0, May 1994
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*
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* MC68230: Parallel Interface/Timer (PI/T)
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* Motorola Semiconductors, December, 1983
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*
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* ----------------------------------------------------------------------------------
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of the Linux
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* distribution for more details.
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*
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* ----------------------------------------------------------------------------------
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*
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* The Ariadne is a Zorro-II board made by Village Tronic. It contains:
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*
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* - an Am79C960 PCnet-ISA Single-Chip Ethernet Controller with both
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* 10BASE-2 (thin coax) and 10BASE-T (UTP) connectors
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*
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* - an MC68230 Parallel Interface/Timer configured as 2 parallel ports
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*/
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/*
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* Am79C960 PCnet-ISA
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*/
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struct Am79C960 {
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volatile u_short AddressPROM[8];
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/* IEEE Address PROM (Unused in the Ariadne) */
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volatile u_short RDP; /* Register Data Port */
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volatile u_short RAP; /* Register Address Port */
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volatile u_short Reset; /* Reset Chip on Read Access */
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volatile u_short IDP; /* ISACSR Data Port */
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};
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/*
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* Am79C960 Control and Status Registers
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*
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* These values are already swap()ed!!
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*
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* Only registers marked with a `-' are intended for network software
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* access
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*/
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#define CSR0 0x0000 /* - PCnet-ISA Controller Status */
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#define CSR1 0x0100 /* - IADR[15:0] */
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#define CSR2 0x0200 /* - IADR[23:16] */
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#define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
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#define CSR4 0x0400 /* - Test and Features Control */
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#define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
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#define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
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#define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
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#define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
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#define CSR11 0x0b00 /* - Logical Address Filter, LADRF[63:48] */
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#define CSR12 0x0c00 /* - Physical Address Register, PADR[15:0] */
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#define CSR13 0x0d00 /* - Physical Address Register, PADR[31:16] */
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#define CSR14 0x0e00 /* - Physical Address Register, PADR[47:32] */
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#define CSR15 0x0f00 /* - Mode Register */
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#define CSR16 0x1000 /* Initialization Block Address Lower */
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#define CSR17 0x1100 /* Initialization Block Address Upper */
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#define CSR18 0x1200 /* Current Receive Buffer Address */
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#define CSR19 0x1300 /* Current Receive Buffer Address */
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#define CSR20 0x1400 /* Current Transmit Buffer Address */
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#define CSR21 0x1500 /* Current Transmit Buffer Address */
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#define CSR22 0x1600 /* Next Receive Buffer Address */
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#define CSR23 0x1700 /* Next Receive Buffer Address */
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#define CSR24 0x1800 /* - Base Address of Receive Ring */
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#define CSR25 0x1900 /* - Base Address of Receive Ring */
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#define CSR26 0x1a00 /* Next Receive Descriptor Address */
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#define CSR27 0x1b00 /* Next Receive Descriptor Address */
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#define CSR28 0x1c00 /* Current Receive Descriptor Address */
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#define CSR29 0x1d00 /* Current Receive Descriptor Address */
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#define CSR30 0x1e00 /* - Base Address of Transmit Ring */
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#define CSR31 0x1f00 /* - Base Address of transmit Ring */
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#define CSR32 0x2000 /* Next Transmit Descriptor Address */
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#define CSR33 0x2100 /* Next Transmit Descriptor Address */
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#define CSR34 0x2200 /* Current Transmit Descriptor Address */
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#define CSR35 0x2300 /* Current Transmit Descriptor Address */
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#define CSR36 0x2400 /* Next Next Receive Descriptor Address */
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#define CSR37 0x2500 /* Next Next Receive Descriptor Address */
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#define CSR38 0x2600 /* Next Next Transmit Descriptor Address */
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#define CSR39 0x2700 /* Next Next Transmit Descriptor Address */
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#define CSR40 0x2800 /* Current Receive Status and Byte Count */
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#define CSR41 0x2900 /* Current Receive Status and Byte Count */
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#define CSR42 0x2a00 /* Current Transmit Status and Byte Count */
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#define CSR43 0x2b00 /* Current Transmit Status and Byte Count */
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#define CSR44 0x2c00 /* Next Receive Status and Byte Count */
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#define CSR45 0x2d00 /* Next Receive Status and Byte Count */
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#define CSR46 0x2e00 /* Poll Time Counter */
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#define CSR47 0x2f00 /* Polling Interval */
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#define CSR48 0x3000 /* Temporary Storage */
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#define CSR49 0x3100 /* Temporary Storage */
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#define CSR50 0x3200 /* Temporary Storage */
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#define CSR51 0x3300 /* Temporary Storage */
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#define CSR52 0x3400 /* Temporary Storage */
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#define CSR53 0x3500 /* Temporary Storage */
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#define CSR54 0x3600 /* Temporary Storage */
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#define CSR55 0x3700 /* Temporary Storage */
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#define CSR56 0x3800 /* Temporary Storage */
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#define CSR57 0x3900 /* Temporary Storage */
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#define CSR58 0x3a00 /* Temporary Storage */
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#define CSR59 0x3b00 /* Temporary Storage */
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#define CSR60 0x3c00 /* Previous Transmit Descriptor Address */
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#define CSR61 0x3d00 /* Previous Transmit Descriptor Address */
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#define CSR62 0x3e00 /* Previous Transmit Status and Byte Count */
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#define CSR63 0x3f00 /* Previous Transmit Status and Byte Count */
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#define CSR64 0x4000 /* Next Transmit Buffer Address */
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#define CSR65 0x4100 /* Next Transmit Buffer Address */
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#define CSR66 0x4200 /* Next Transmit Status and Byte Count */
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#define CSR67 0x4300 /* Next Transmit Status and Byte Count */
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#define CSR68 0x4400 /* Transmit Status Temporary Storage */
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#define CSR69 0x4500 /* Transmit Status Temporary Storage */
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#define CSR70 0x4600 /* Temporary Storage */
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#define CSR71 0x4700 /* Temporary Storage */
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#define CSR72 0x4800 /* Receive Ring Counter */
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#define CSR74 0x4a00 /* Transmit Ring Counter */
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#define CSR76 0x4c00 /* - Receive Ring Length */
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#define CSR78 0x4e00 /* - Transmit Ring Length */
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#define CSR80 0x5000 /* - Burst and FIFO Threshold Control */
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#define CSR82 0x5200 /* - Bus Activity Timer */
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#define CSR84 0x5400 /* DMA Address */
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#define CSR85 0x5500 /* DMA Address */
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#define CSR86 0x5600 /* Buffer Byte Counter */
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#define CSR88 0x5800 /* - Chip ID */
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#define CSR89 0x5900 /* - Chip ID */
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#define CSR92 0x5c00 /* Ring Length Conversion */
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#define CSR94 0x5e00 /* Transmit Time Domain Reflectometry Count */
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#define CSR96 0x6000 /* Bus Interface Scratch Register 0 */
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#define CSR97 0x6100 /* Bus Interface Scratch Register 0 */
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#define CSR98 0x6200 /* Bus Interface Scratch Register 1 */
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#define CSR99 0x6300 /* Bus Interface Scratch Register 1 */
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#define CSR104 0x6800 /* SWAP */
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#define CSR105 0x6900 /* SWAP */
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#define CSR108 0x6c00 /* Buffer Management Scratch */
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#define CSR109 0x6d00 /* Buffer Management Scratch */
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#define CSR112 0x7000 /* - Missed Frame Count */
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#define CSR114 0x7200 /* - Receive Collision Count */
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#define CSR124 0x7c00 /* - Buffer Management Unit Test */
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/*
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* Am79C960 ISA Control and Status Registers
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*
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* These values are already swap()ed!!
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*/
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#define ISACSR0 0x0000 /* Master Mode Read Active */
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#define ISACSR1 0x0100 /* Master Mode Write Active */
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#define ISACSR2 0x0200 /* Miscellaneous Configuration */
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#define ISACSR4 0x0400 /* LED0 Status (Link Integrity) */
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#define ISACSR5 0x0500 /* LED1 Status */
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#define ISACSR6 0x0600 /* LED2 Status */
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#define ISACSR7 0x0700 /* LED3 Status */
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/*
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* Bit definitions for CSR0 (PCnet-ISA Controller Status)
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*
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* These values are already swap()ed!!
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*/
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#define ERR 0x0080 /* Error */
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#define BABL 0x0040 /* Babble: Transmitted too many bits */
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#define CERR 0x0020 /* No Heartbeat (10BASE-T) */
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#define MISS 0x0010 /* Missed Frame */
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#define MERR 0x0008 /* Memory Error */
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#define RINT 0x0004 /* Receive Interrupt */
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#define TINT 0x0002 /* Transmit Interrupt */
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#define IDON 0x0001 /* Initialization Done */
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#define INTR 0x8000 /* Interrupt Flag */
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#define INEA 0x4000 /* Interrupt Enable */
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#define RXON 0x2000 /* Receive On */
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#define TXON 0x1000 /* Transmit On */
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#define TDMD 0x0800 /* Transmit Demand */
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#define STOP 0x0400 /* Stop */
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#define STRT 0x0200 /* Start */
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#define INIT 0x0100 /* Initialize */
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/*
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* Bit definitions for CSR3 (Interrupt Masks and Deferral Control)
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*
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* These values are already swap()ed!!
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*/
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#define BABLM 0x0040 /* Babble Mask */
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#define MISSM 0x0010 /* Missed Frame Mask */
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#define MERRM 0x0008 /* Memory Error Mask */
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#define RINTM 0x0004 /* Receive Interrupt Mask */
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#define TINTM 0x0002 /* Transmit Interrupt Mask */
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#define IDONM 0x0001 /* Initialization Done Mask */
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#define DXMT2PD 0x1000 /* Disable Transmit Two Part Deferral */
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#define EMBA 0x0800 /* Enable Modified Back-off Algorithm */
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/*
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* Bit definitions for CSR4 (Test and Features Control)
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*
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* These values are already swap()ed!!
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*/
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#define ENTST 0x0080 /* Enable Test Mode */
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#define DMAPLUS 0x0040 /* Disable Burst Transaction Counter */
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#define TIMER 0x0020 /* Timer Enable Register */
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#define DPOLL 0x0010 /* Disable Transmit Polling */
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#define APAD_XMT 0x0008 /* Auto Pad Transmit */
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#define ASTRP_RCV 0x0004 /* Auto Pad Stripping */
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#define MFCO 0x0002 /* Missed Frame Counter Overflow Interrupt */
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#define MFCOM 0x0001 /* Missed Frame Counter Overflow Mask */
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#define RCVCCO 0x2000 /* Receive Collision Counter Overflow Interrupt */
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#define RCVCCOM 0x1000 /* Receive Collision Counter Overflow Mask */
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#define TXSTRT 0x0800 /* Transmit Start Status */
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#define TXSTRTM 0x0400 /* Transmit Start Mask */
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#define JAB 0x0200 /* Jabber Error */
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#define JABM 0x0100 /* Jabber Error Mask */
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/*
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* Bit definitions for CSR15 (Mode Register)
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*
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* These values are already swap()ed!!
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*/
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#define PROM 0x0080 /* Promiscuous Mode */
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#define DRCVBC 0x0040 /* Disable Receive Broadcast */
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#define DRCVPA 0x0020 /* Disable Receive Physical Address */
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#define DLNKTST 0x0010 /* Disable Link Status */
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#define DAPC 0x0008 /* Disable Automatic Polarity Correction */
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#define MENDECL 0x0004 /* MENDEC Loopback Mode */
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#define LRTTSEL 0x0002 /* Low Receive Treshold/Transmit Mode Select */
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#define PORTSEL1 0x0001 /* Port Select Bits */
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#define PORTSEL2 0x8000 /* Port Select Bits */
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#define INTL 0x4000 /* Internal Loopback */
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#define DRTY 0x2000 /* Disable Retry */
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#define FCOLL 0x1000 /* Force Collision */
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#define DXMTFCS 0x0800 /* Disable Transmit CRC */
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#define LOOP 0x0400 /* Loopback Enable */
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#define DTX 0x0200 /* Disable Transmitter */
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#define DRX 0x0100 /* Disable Receiver */
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/*
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* Bit definitions for ISACSR2 (Miscellaneous Configuration)
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*
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* These values are already swap()ed!!
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*/
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#define ASEL 0x0200 /* Media Interface Port Auto Select */
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/*
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* Bit definitions for ISACSR5-7 (LED1-3 Status)
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*
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* These values are already swap()ed!!
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*/
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#define LEDOUT 0x0080 /* Current LED Status */
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#define PSE 0x8000 /* Pulse Stretcher Enable */
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#define XMTE 0x1000 /* Enable Transmit Status Signal */
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#define RVPOLE 0x0800 /* Enable Receive Polarity Signal */
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#define RCVE 0x0400 /* Enable Receive Status Signal */
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#define JABE 0x0200 /* Enable Jabber Signal */
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#define COLE 0x0100 /* Enable Collision Signal */
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/*
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* Receive Descriptor Ring Entry
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*/
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struct RDRE {
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volatile u_short RMD0; /* LADR[15:0] */
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volatile u_short RMD1; /* HADR[23:16] | Receive Flags */
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volatile u_short RMD2; /* Buffer Byte Count (two's complement) */
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volatile u_short RMD3; /* Message Byte Count */
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};
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/*
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* Transmit Descriptor Ring Entry
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*/
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struct TDRE {
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volatile u_short TMD0; /* LADR[15:0] */
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volatile u_short TMD1; /* HADR[23:16] | Transmit Flags */
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volatile u_short TMD2; /* Buffer Byte Count (two's complement) */
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volatile u_short TMD3; /* Error Flags */
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};
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/*
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* Receive Flags
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*/
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#define RF_OWN 0x0080 /* PCnet-ISA controller owns the descriptor */
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#define RF_ERR 0x0040 /* Error */
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#define RF_FRAM 0x0020 /* Framing Error */
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#define RF_OFLO 0x0010 /* Overflow Error */
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#define RF_CRC 0x0008 /* CRC Error */
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#define RF_BUFF 0x0004 /* Buffer Error */
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#define RF_STP 0x0002 /* Start of Packet */
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#define RF_ENP 0x0001 /* End of Packet */
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/*
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* Transmit Flags
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*/
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#define TF_OWN 0x0080 /* PCnet-ISA controller owns the descriptor */
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#define TF_ERR 0x0040 /* Error */
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#define TF_ADD_FCS 0x0020 /* Controls FCS Generation */
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#define TF_MORE 0x0010 /* More than one retry needed */
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#define TF_ONE 0x0008 /* One retry needed */
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#define TF_DEF 0x0004 /* Deferred */
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#define TF_STP 0x0002 /* Start of Packet */
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#define TF_ENP 0x0001 /* End of Packet */
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||
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|
||
|
|
|
||
|
|
/*
|
||
|
|
* Error Flags
|
||
|
|
*/
|
||
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|
|
||
|
|
#define EF_BUFF 0x0080 /* Buffer Error */
|
||
|
|
#define EF_UFLO 0x0040 /* Underflow Error */
|
||
|
|
#define EF_LCOL 0x0010 /* Late Collision */
|
||
|
|
#define EF_LCAR 0x0008 /* Loss of Carrier */
|
||
|
|
#define EF_RTRY 0x0004 /* Retry Error */
|
||
|
|
#define EF_TDR 0xff03 /* Time Domain Reflectometry */
|
||
|
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|
||
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|
||
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|
|
||
|
|
/*
|
||
|
|
* MC68230 Parallel Interface/Timer
|
||
|
|
*/
|
||
|
|
|
||
|
|
struct MC68230 {
|
||
|
|
volatile u_char PGCR; /* Port General Control Register */
|
||
|
|
u_char Pad1[1];
|
||
|
|
volatile u_char PSRR; /* Port Service Request Register */
|
||
|
|
u_char Pad2[1];
|
||
|
|
volatile u_char PADDR; /* Port A Data Direction Register */
|
||
|
|
u_char Pad3[1];
|
||
|
|
volatile u_char PBDDR; /* Port B Data Direction Register */
|
||
|
|
u_char Pad4[1];
|
||
|
|
volatile u_char PCDDR; /* Port C Data Direction Register */
|
||
|
|
u_char Pad5[1];
|
||
|
|
volatile u_char PIVR; /* Port Interrupt Vector Register */
|
||
|
|
u_char Pad6[1];
|
||
|
|
volatile u_char PACR; /* Port A Control Register */
|
||
|
|
u_char Pad7[1];
|
||
|
|
volatile u_char PBCR; /* Port B Control Register */
|
||
|
|
u_char Pad8[1];
|
||
|
|
volatile u_char PADR; /* Port A Data Register */
|
||
|
|
u_char Pad9[1];
|
||
|
|
volatile u_char PBDR; /* Port B Data Register */
|
||
|
|
u_char Pad10[1];
|
||
|
|
volatile u_char PAAR; /* Port A Alternate Register */
|
||
|
|
u_char Pad11[1];
|
||
|
|
volatile u_char PBAR; /* Port B Alternate Register */
|
||
|
|
u_char Pad12[1];
|
||
|
|
volatile u_char PCDR; /* Port C Data Register */
|
||
|
|
u_char Pad13[1];
|
||
|
|
volatile u_char PSR; /* Port Status Register */
|
||
|
|
u_char Pad14[5];
|
||
|
|
volatile u_char TCR; /* Timer Control Register */
|
||
|
|
u_char Pad15[1];
|
||
|
|
volatile u_char TIVR; /* Timer Interrupt Vector Register */
|
||
|
|
u_char Pad16[3];
|
||
|
|
volatile u_char CPRH; /* Counter Preload Register (High) */
|
||
|
|
u_char Pad17[1];
|
||
|
|
volatile u_char CPRM; /* Counter Preload Register (Mid) */
|
||
|
|
u_char Pad18[1];
|
||
|
|
volatile u_char CPRL; /* Counter Preload Register (Low) */
|
||
|
|
u_char Pad19[3];
|
||
|
|
volatile u_char CNTRH; /* Count Register (High) */
|
||
|
|
u_char Pad20[1];
|
||
|
|
volatile u_char CNTRM; /* Count Register (Mid) */
|
||
|
|
u_char Pad21[1];
|
||
|
|
volatile u_char CNTRL; /* Count Register (Low) */
|
||
|
|
u_char Pad22[1];
|
||
|
|
volatile u_char TSR; /* Timer Status Register */
|
||
|
|
u_char Pad23[11];
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Ariadne Expansion Board Structure
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define ARIADNE_LANCE 0x360
|
||
|
|
|
||
|
|
#define ARIADNE_PIT 0x1000
|
||
|
|
|
||
|
|
#define ARIADNE_BOOTPROM 0x4000 /* I guess it's here :-) */
|
||
|
|
#define ARIADNE_BOOTPROM_SIZE 0x4000
|
||
|
|
|
||
|
|
#define ARIADNE_RAM 0x8000 /* Always access WORDs!! */
|
||
|
|
#define ARIADNE_RAM_SIZE 0x8000
|
||
|
|
|