108 lines
3.4 KiB
C
108 lines
3.4 KiB
C
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/*
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* STMicroelectronics NAND Controller
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*
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* See ADCS #7864584: "NAND Flash support upgrades for FMI Functional
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* Secification".
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*
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* Copyright (c) 2008 STMicroelectronics Limited
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* Author: Angus Clark <angus.clark@st.com>
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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*/
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#ifndef STM_NANDC_REGS_H
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#define STM_NANDC_REGS_H
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#define EMINAND_CONFIG_SIZE 0x1000
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/* Register Addresses (OFFSET from EMINAND_CONFIG_BASE) */
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#define EMINAND_BOOTBANK_CONFIG 0x000
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#define EMINAND_RBN_STATUS 0x004
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#define EMINAND_INTERRUPT_ENABLE 0x010
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#define EMINAND_INTERRUPT_STATUS 0x014
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#define EMINAND_INTERRUPT_CLEAR 0x018
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#define EMINAND_INTERRUPT_EDGECONFIG 0x01C
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#define EMINAND_CONTROL_TIMING 0x040
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#define EMINAND_WEN_TIMING 0x044
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#define EMINAND_REN_TIMING 0x048
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#define EMINAND_FLEXMODE_CONFIG 0x100
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#define EMINAND_MUXCONTROL_REG 0x104
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#define EMINAND_CSN_ALTERNATE 0x108
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#define EMINAND_FLEX_DATAWRITE_CONFIG 0x10C
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#define EMINAND_FLEX_DATAREAD_CONFIG 0x110
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#define EMINAND_FLEX_COMMAND_REG 0x114
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#define EMINAND_FLEX_ADDRESS_REG 0x118
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#define EMINAND_FLEX_DATA 0x120
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#define EMINAND_VERSION_REG 0x144
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#define EMINAND_MULTI_CS_CONFIG_REG 0x1EC
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/* Advanced Flex Mode registers (OFFSET from EMINAND_CONFIG_BASE) */
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#define EMINAND_AFM_SEQUENCE_REG_1 0x200
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#define EMINAND_AFM_SEQUENCE_REG_2 0x204
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#define EMINAND_AFM_SEQUENCE_REG_3 0x208
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#define EMINAND_AFM_SEQUENCE_REG_4 0x20C
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#define EMINAND_AFM_ADDRESS_REG 0x210
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#define EMINAND_AFM_EXTRA_REG 0x214
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#define EMINAND_AFM_COMMAND_REG 0x218
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#define EMINAND_AFM_SEQUENCE_CONFIG_REG 0x21C
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#define EMINAND_AFM_GENERIC_CONFIG_REG 0x220
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#define EMINAND_AFM_SEQUENCE_STATUS_REG 0x240
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#define EMINAND_AFM_ECC_CHECKCODE_REG_0 0x280
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#define EMINAND_AFM_ECC_CHECKCODE_REG_1 0x284
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#define EMINAND_AFM_ECC_CHECKCODE_REG_2 0x288
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#define EMINAND_AFM_ECC_CHECKCODE_REG_3 0x28C
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#define EMINAND_AFM_DATA_FIFO 0x300
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/* AFM Commands */
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#define AFM_STOP 0x0
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#define AFM_CMD 0x1
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#define AFM_INC 0x2
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#define AFM_DEC_JUMP 0x3
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#define AFM_DATA 0x4
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#define AFM_SPARE 0x5
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#define AFM_CHECK 0x6
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#define AFM_ADDR 0x7
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#define AFM_WRBN 0xA
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/* FLEX: Address Register Fields */
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#define FLX_ADDR_REG_RBN (0x1 << 27)
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#define FLX_ADDR_REG_BEAT_1 (0x1 << 28)
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#define FLX_ADDR_REG_BEAT_2 (0x2 << 28)
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#define FLX_ADDR_REG_BEAT_3 (0x3 << 28)
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#define FLX_ADDR_REG_BEAT_4 (0x0 << 28)
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#define FLX_ADDR_REG_ADD8_VALID (0x1 << 30)
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#define FLX_ADDR_REG_CSN_STATUS (0x1 << 31)
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/* FLEX: Commad Register fields */
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#define FLX_CMD_REG_RBN (0x1 << 27)
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#define FLX_CMD_REG_BEAT_1 (0x1 << 28)
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#define FLX_CMD_REG_BEAT_2 (0x2 << 28)
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#define FLX_CMD_REG_BEAT_3 (0x3 << 28)
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#define FLX_CMD_REG_BEAT_4 (0x0 << 28)
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#define FLX_CMD_REG_CSN_STATUS (0x1 << 31)
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#define FLX_CMD(x) (((x) & 0xff) | \
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FLX_CMD_REG_RBN | \
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FLX_CMD_REG_BEAT_1 | \
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FLX_CMD_REG_CSN_STATUS)
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/* FLEX: Data Config fields */
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#define FLX_DATA_CFG_RBN (0x1 << 27)
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#define FLX_DATA_CFG_BEAT_1 (0x1 << 28)
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#define FLX_DATA_CFG_BEAT_2 (0x2 << 28)
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#define FLX_DATA_CFG_BEAT_3 (0x3 << 28)
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#define FLX_DATA_CFG_BEAT_4 (0x0 << 28)
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#define FLX_DATA_CFG_BYTES_1 (0x0 << 30)
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#define FLX_DATA_CFG_BYTES_2 (0x1 << 30)
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#define FLX_DATA_CFG_CSN_STATUS (0x1 << 31)
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/* AFM: Sequence Config fields */
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#define AFM_SEQ_CFG_GO (0x1 << 26)
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#define AFM_SEQ_CFG_DIR_WRITE (0x1 << 24)
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#endif /* STM_NANDC_REGS_H */
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