122 lines
4.1 KiB
Plaintext
122 lines
4.1 KiB
Plaintext
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Register Usage for Linux/PA-RISC
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[ an asterisk is used for planned usage which is currently unimplemented ]
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General Registers as specified by ABI
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Control Registers
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CR 0 (Recovery Counter) used for ptrace
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CR 1-CR 7(undefined) unused
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CR 8 (Protection ID) per-process value*
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CR 9, 12, 13 (PIDS) unused
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CR10 (CCR) lazy FPU saving*
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CR11 as specified by ABI (SAR)
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CR14 (interruption vector) initialized to fault_vector
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CR15 (EIEM) initialized to all ones*
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CR16 (Interval Timer) read for cycle count/write starts Interval Tmr
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CR17-CR22 interruption parameters
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CR19 Interrupt Instruction Register
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CR20 Interrupt Space Register
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CR21 Interrupt Offset Register
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CR22 Interrupt PSW
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CR23 (EIRR) read for pending interrupts/write clears bits
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CR24 (TR 0) Kernel Space Page Directory Pointer
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CR25 (TR 1) User Space Page Directory Pointer
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CR26 (TR 2) not used
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CR27 (TR 3) Thread descriptor pointer
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CR28 (TR 4) not used
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CR29 (TR 5) not used
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CR30 (TR 6) current / 0
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CR31 (TR 7) Temporary register, used in various places
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Space Registers (kernel mode)
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SR0 temporary space register
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SR4-SR7 set to 0
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SR1 temporary space register
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SR2 kernel should not clobber this
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SR3 used for userspace accesses (current process)
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Space Registers (user mode)
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SR0 temporary space register
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SR1 temporary space register
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SR2 holds space of linux gateway page
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SR3 holds user address space value while in kernel
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SR4-SR7 Defines short address space for user/kernel
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Processor Status Word
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W (64-bit addresses) 0
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E (Little-endian) 0
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S (Secure Interval Timer) 0
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T (Taken Branch Trap) 0
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H (Higher-privilege trap) 0
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L (Lower-privilege trap) 0
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N (Nullify next instruction) used by C code
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X (Data memory break disable) 0
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B (Taken Branch) used by C code
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C (code address translation) 1, 0 while executing real-mode code
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V (divide step correction) used by C code
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M (HPMC mask) 0, 1 while executing HPMC handler*
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C/B (carry/borrow bits) used by C code
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O (ordered references) 1*
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F (performance monitor) 0
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R (Recovery Counter trap) 0
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Q (collect interruption state) 1 (0 in code directly preceding an rfi)
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P (Protection Identifiers) 1*
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D (Data address translation) 1, 0 while executing real-mode code
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I (external interrupt mask) used by cli()/sti() macros
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"Invisible" Registers
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PSW default W value 0
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PSW default E value 0
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Shadow Registers used by interruption handler code
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TOC enable bit 1
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=========================================================================
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Register usage notes, originally from John Marvin, with some additional
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notes from Randolph Chung.
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For the general registers:
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r1,r2,r19-r26,r28,r29 & r31 can be used without saving them first. And of
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course, you need to save them if you care about them, before calling
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another procedure. Some of the above registers do have special meanings
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that you should be aware of:
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r1: The addil instruction is hardwired to place its result in r1,
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so if you use that instruction be aware of that.
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r2: This is the return pointer. In general you don't want to
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use this, since you need the pointer to get back to your
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caller. However, it is grouped with this set of registers
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since the caller can't rely on the value being the same
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when you return, i.e. you can copy r2 to another register
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and return through that register after trashing r2, and
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that should not cause a problem for the calling routine.
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r19-r22: these are generally regarded as temporary registers.
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Note that in 64 bit they are arg7-arg4.
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r23-r26: these are arg3-arg0, i.e. you can use them if you
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don't care about the values that were passed in anymore.
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r28,r29: are ret0 and ret1. They are what you pass return values
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in. r28 is the primary return. When returning small structures
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r29 may also be used to pass data back to the caller.
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r30: stack pointer
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r31: the ble instruction puts the return pointer in here.
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r3-r18,r27,r30 need to be saved and restored. r3-r18 are just
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general purpose registers. r27 is the data pointer, and is
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used to make references to global variables easier. r30 is
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the stack pointer.
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