285 lines
6.7 KiB
Plaintext
285 lines
6.7 KiB
Plaintext
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/*
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* Manroland uc101 board Device Tree Source
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*
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* Copyright (C) 2009 DENX Software Engineering GmbH
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* Heiko Schocher <hs@denx.de>
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* Copyright 2006-2007 Secret Lab Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "manroland,uc101";
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compatible = "manroland,uc101";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&mpc5200_pic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,5200@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <0x4000>; // L1, 16K
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i-cache-size = <0x4000>; // L1, 16K
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x04000000>; // 64MB
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};
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soc5200@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc5200b-immr";
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ranges = <0 0xf0000000 0x0000c000>;
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reg = <0xf0000000 0x00000100>;
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bus-frequency = <0>; // from bootloader
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system-frequency = <0>; // from bootloader
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cdm@200 {
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compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
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reg = <0x200 0x38>;
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};
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mpc5200_pic: interrupt-controller@500 {
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// 5200 interrupts are encoded into two levels;
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interrupt-controller;
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#interrupt-cells = <3>;
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compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
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reg = <0x500 0x80>;
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};
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gpt0: timer@600 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x600 0x10>;
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interrupts = <1 9 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt1: timer@610 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x610 0x10>;
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interrupts = <1 10 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt2: timer@620 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x620 0x10>;
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interrupts = <1 11 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt3: timer@630 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x630 0x10>;
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interrupts = <1 12 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt4: timer@640 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x640 0x10>;
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interrupts = <1 13 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt5: timer@650 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x650 0x10>;
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interrupts = <1 14 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt6: timer@660 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x660 0x10>;
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interrupts = <1 15 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt7: timer@670 { // General Purpose Timer in GPIO mode
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x670 0x10>;
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interrupts = <1 16 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio_simple: gpio@b00 {
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compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
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reg = <0xb00 0x40>;
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interrupts = <1 7 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio_wkup: gpio@c00 {
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compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
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reg = <0xc00 0x40>;
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interrupts = <1 8 0 0 3 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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dma-controller@1200 {
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compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
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reg = <0x1200 0x80>;
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interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
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3 4 0 3 5 0 3 6 0 3 7 0
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3 8 0 3 9 0 3 10 0 3 11 0
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3 12 0 3 13 0 3 14 0 3 15 0>;
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};
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xlb@1f00 {
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compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
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reg = <0x1f00 0x100>;
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};
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serial@2000 { /* PSC1 in UART mode */
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2000 0x100>;
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interrupts = <2 1 0>;
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};
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serial@2200 { /* PSC2 in UART mode */
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2200 0x100>;
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interrupts = <2 2 0>;
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};
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serial@2c00 { /* PSC6 in UART mode */
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2c00 0x100>;
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interrupts = <2 4 0>;
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};
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ethernet@3000 {
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compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
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reg = <0x3000 0x400>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <2 5 0>;
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phy-handle = <&phy0>;
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};
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mdio@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
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reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
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interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
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phy0: ethernet-phy@0 {
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compatible = "intel,lxt971";
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reg = <0>;
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};
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};
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ata@3a00 {
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compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
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reg = <0x3a00 0x100>;
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interrupts = <2 7 0>;
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};
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i2c@3d40 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
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reg = <0x3d40 0x40>;
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interrupts = <2 16 0>;
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fsl,preserve-clocking;
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clock-frequency = <400000>;
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hwmon@2c {
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compatible = "ad,adm9240";
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reg = <0x2c>;
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};
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rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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};
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sram@8000 {
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compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
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reg = <0x8000 0x4000>;
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};
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};
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localbus {
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compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0xff800000 0x00800000
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1 0 0x80000000 0x00800000
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3 0 0x80000000 0x00800000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x00800000>;
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bank-width = <2>;
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device-width = <2>;
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#size-cells = <1>;
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#address-cells = <1>;
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partition@0 {
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label = "DTS";
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reg = <0x0 0x00100000>;
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};
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partition@100000 {
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label = "Kernel";
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reg = <0x100000 0x00200000>;
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};
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partition@300000 {
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label = "RootFS";
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reg = <0x00300000 0x00200000>;
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};
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partition@500000 {
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label = "user";
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reg = <0x00500000 0x00200000>;
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};
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partition@700000 {
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label = "U-Boot";
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reg = <0x00700000 0x00040000>;
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};
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partition@740000 {
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label = "Env";
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reg = <0x00740000 0x00010000>;
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};
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partition@750000 {
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label = "red. Env";
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reg = <0x00750000 0x00010000>;
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};
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partition@760000 {
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label = "reserve";
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reg = <0x00760000 0x000a0000>;
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};
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};
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};
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};
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