125 lines
5.8 KiB
C
125 lines
5.8 KiB
C
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/*****************************************************************************
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* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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/* ---- Include Files ---------------------------------------------------- */
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#include <csp/stdint.h>
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#include <mach/csp/chipcHw_def.h>
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#include <mach/csp/chipcHw_inline.h>
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#include <csp/intcHw.h>
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#include <csp/cache.h>
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/* ---- Private Constants and Types --------------------------------------- */
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/* ---- Private Variables ------------------------------------------------- */
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void chipcHw_reset_run_from_aram(void);
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typedef void (*RUNFUNC) (void);
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/****************************************************************************/
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/**
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* @brief warmReset
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*
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* @note warmReset configures the clocks which are not reset back to the state
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* required to execute on reset. To do so we need to copy the code into internal
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* memory to change the ARM clock while we are not executing from DDR.
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*/
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/****************************************************************************/
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void chipcHw_reset(uint32_t mask)
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{
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int i = 0;
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RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
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/* Disable all interrupts */
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intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
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intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
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intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
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{
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REG_LOCAL_IRQ_SAVE;
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if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
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chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
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}
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/* Bypass the PLL clocks before reboot */
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pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
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pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
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/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
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do {
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((uint32_t *) MM_IO_BASE_ARAM)[i] =
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((uint32_t *) &chipcHw_reset_run_from_aram)[i];
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i++;
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} while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
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CSP_CACHE_FLUSH_ALL;
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/* run the function from ARAM */
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runFunc();
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/* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
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REG_LOCAL_IRQ_RESTORE;
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}
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}
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/* This function must run from internal memory */
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void chipcHw_reset_run_from_aram(void)
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{
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/* Make sure, pipeline is filled with instructions coming from ARAM */
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__asm (" nop \n\t"
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" nop \n\t"
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#if defined(__KERNEL__) && !defined(STANDALONE)
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" MRC p15,#0x0,r0,c1,c0,#0 \n\t"
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" BIC r0,r0,#0xd \n\t"
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" MCR p15,#0x0,r0,c1,c0,#0 \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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#endif
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" nop \n\t"
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" nop \n\t"
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/* Bypass the ARM clock and switch to XTAL clock */
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" MOV r2,#0x80000000 \n\t"
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" LDR r3,[r2,#8] \n\t"
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" ORR r3,r3,#0x20000 \n\t"
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" STR r3,[r2,#8] \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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" nop \n\t"
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/* Issue reset */
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" MOV r3,#0x2 \n\t"
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" STR r3,[r2,#0x80] \n\t"
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/* End here */
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" MOV pc,pc \n\t");
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/* 0xe1a0f00f == asm ("mov r15, r15"); */
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}
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