421 lines
15 KiB
C
421 lines
15 KiB
C
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/*
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* Wireless Host Controller (WHC) data structures.
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*
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* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#ifndef _WHCI_WHCI_HC_H
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#define _WHCI_WHCI_HC_H
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#include <linux/list.h>
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/**
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* WHCI_PAGE_SIZE - page size use by WHCI
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*
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* WHCI assumes that host system uses pages of 4096 octets.
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*/
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#define WHCI_PAGE_SIZE 4096
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/**
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* QTD_MAX_TXFER_SIZE - max number of bytes to transfer with a single
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* qtd.
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*
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* This is 2^20 - 1.
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*/
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#define QTD_MAX_XFER_SIZE 1048575
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/**
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* struct whc_qtd - Queue Element Transfer Descriptors (qTD)
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*
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* This describes the data for a bulk, control or interrupt transfer.
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*
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* [WHCI] section 3.2.4
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*/
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struct whc_qtd {
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__le32 status; /*< remaining transfer len and transfer status */
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__le32 options;
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__le64 page_list_ptr; /*< physical pointer to data buffer page list*/
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__u8 setup[8]; /*< setup data for control transfers */
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} __attribute__((packed));
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#define QTD_STS_ACTIVE (1 << 31) /* enable execution of transaction */
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#define QTD_STS_HALTED (1 << 30) /* transfer halted */
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#define QTD_STS_DBE (1 << 29) /* data buffer error */
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#define QTD_STS_BABBLE (1 << 28) /* babble detected */
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#define QTD_STS_RCE (1 << 27) /* retry count exceeded */
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#define QTD_STS_LAST_PKT (1 << 26) /* set Last Packet Flag in WUSB header */
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#define QTD_STS_INACTIVE (1 << 25) /* queue set is marked inactive */
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#define QTD_STS_IALT_VALID (1 << 23) /* iAlt field is valid */
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#define QTD_STS_IALT(i) (QTD_STS_IALT_VALID | ((i) << 20)) /* iAlt field */
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#define QTD_STS_LEN(l) ((l) << 0) /* transfer length */
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#define QTD_STS_TO_LEN(s) ((s) & 0x000fffff)
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#define QTD_OPT_IOC (1 << 1) /* page_list_ptr points to buffer directly */
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#define QTD_OPT_SMALL (1 << 0) /* interrupt on complete */
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/**
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* struct whc_itd - Isochronous Queue Element Transfer Descriptors (iTD)
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*
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* This describes the data and other parameters for an isochronous
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* transfer.
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*
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* [WHCI] section 3.2.5
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*/
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struct whc_itd {
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__le16 presentation_time; /*< presentation time for OUT transfers */
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__u8 num_segments; /*< number of data segments in segment list */
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__u8 status; /*< command execution status */
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__le32 options; /*< misc transfer options */
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__le64 page_list_ptr; /*< physical pointer to data buffer page list */
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__le64 seg_list_ptr; /*< physical pointer to segment list */
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} __attribute__((packed));
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#define ITD_STS_ACTIVE (1 << 7) /* enable execution of transaction */
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#define ITD_STS_DBE (1 << 5) /* data buffer error */
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#define ITD_STS_BABBLE (1 << 4) /* babble detected */
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#define ITD_STS_INACTIVE (1 << 1) /* queue set is marked inactive */
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#define ITD_OPT_IOC (1 << 1) /* interrupt on complete */
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#define ITD_OPT_SMALL (1 << 0) /* page_list_ptr points to buffer directly */
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/**
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* Page list entry.
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*
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* A TD's page list must contain sufficient page list entries for the
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* total data length in the TD.
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*
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* [WHCI] section 3.2.4.3
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*/
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struct whc_page_list_entry {
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__le64 buf_ptr; /*< physical pointer to buffer */
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} __attribute__((packed));
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/**
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* struct whc_seg_list_entry - Segment list entry.
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*
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* Describes a portion of the data buffer described in the containing
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* qTD's page list.
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*
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* seg_ptr = qtd->page_list_ptr[qtd->seg_list_ptr[seg].idx].buf_ptr
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* + qtd->seg_list_ptr[seg].offset;
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*
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* Segments can't cross page boundries.
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*
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* [WHCI] section 3.2.5.5
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*/
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struct whc_seg_list_entry {
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__le16 len; /*< segment length */
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__u8 idx; /*< index into page list */
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__u8 status; /*< segment status */
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__le16 offset; /*< 12 bit offset into page */
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} __attribute__((packed));
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/**
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* struct whc_qhead - endpoint and status information for a qset.
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*
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* [WHCI] section 3.2.6
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*/
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struct whc_qhead {
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__le64 link; /*< next qset in list */
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__le32 info1;
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__le32 info2;
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__le32 info3;
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__le16 status;
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__le16 err_count; /*< transaction error count */
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__le32 cur_window;
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__le32 scratch[3]; /*< h/w scratch area */
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union {
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struct whc_qtd qtd;
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struct whc_itd itd;
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} overlay;
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} __attribute__((packed));
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#define QH_LINK_PTR_MASK (~0x03Full)
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#define QH_LINK_PTR(ptr) ((ptr) & QH_LINK_PTR_MASK)
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#define QH_LINK_IQS (1 << 4) /* isochronous queue set */
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#define QH_LINK_NTDS(n) (((n) - 1) << 1) /* number of TDs in queue set */
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#define QH_LINK_T (1 << 0) /* last queue set in periodic schedule list */
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#define QH_INFO1_EP(e) ((e) << 0) /* endpoint number */
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#define QH_INFO1_DIR_IN (1 << 4) /* IN transfer */
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#define QH_INFO1_DIR_OUT (0 << 4) /* OUT transfer */
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#define QH_INFO1_TR_TYPE_CTRL (0x0 << 5) /* control transfer */
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#define QH_INFO1_TR_TYPE_ISOC (0x1 << 5) /* isochronous transfer */
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#define QH_INFO1_TR_TYPE_BULK (0x2 << 5) /* bulk transfer */
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#define QH_INFO1_TR_TYPE_INT (0x3 << 5) /* interrupt */
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#define QH_INFO1_TR_TYPE_LP_INT (0x7 << 5) /* low power interrupt */
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#define QH_INFO1_DEV_INFO_IDX(i) ((i) << 8) /* index into device info buffer */
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#define QH_INFO1_SET_INACTIVE (1 << 15) /* set inactive after transfer */
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#define QH_INFO1_MAX_PKT_LEN(l) ((l) << 16) /* maximum packet length */
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#define QH_INFO2_BURST(b) ((b) << 0) /* maximum burst length */
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#define QH_INFO2_DBP(p) ((p) << 5) /* data burst policy (see [WUSB] table 5-7) */
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#define QH_INFO2_MAX_COUNT(c) ((c) << 8) /* max isoc/int pkts per zone */
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#define QH_INFO2_RQS (1 << 15) /* reactivate queue set */
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#define QH_INFO2_MAX_RETRY(r) ((r) << 16) /* maximum transaction retries */
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#define QH_INFO2_MAX_SEQ(s) ((s) << 20) /* maximum sequence number */
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#define QH_INFO3_MAX_DELAY(d) ((d) << 0) /* maximum stream delay in 125 us units (isoc only) */
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#define QH_INFO3_INTERVAL(i) ((i) << 16) /* segment interval in 125 us units (isoc only) */
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#define QH_INFO3_TX_RATE_53_3 (0 << 24)
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#define QH_INFO3_TX_RATE_80 (1 << 24)
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#define QH_INFO3_TX_RATE_106_7 (2 << 24)
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#define QH_INFO3_TX_RATE_160 (3 << 24)
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#define QH_INFO3_TX_RATE_200 (4 << 24)
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#define QH_INFO3_TX_RATE_320 (5 << 24)
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#define QH_INFO3_TX_RATE_400 (6 << 24)
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#define QH_INFO3_TX_RATE_480 (7 << 24)
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#define QH_INFO3_TX_PWR(p) ((p) << 29) /* transmit power (see [WUSB] section 5.2.1.2) */
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#define QH_STATUS_FLOW_CTRL (1 << 15)
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#define QH_STATUS_ICUR(i) ((i) << 5)
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#define QH_STATUS_TO_ICUR(s) (((s) >> 5) & 0x7)
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#define QH_STATUS_SEQ_MASK 0x1f
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/**
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* usb_pipe_to_qh_type - USB core pipe type to QH transfer type
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*
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* Returns the QH type field for a USB core pipe type.
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*/
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static inline unsigned usb_pipe_to_qh_type(unsigned pipe)
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{
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static const unsigned type[] = {
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[PIPE_ISOCHRONOUS] = QH_INFO1_TR_TYPE_ISOC,
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[PIPE_INTERRUPT] = QH_INFO1_TR_TYPE_INT,
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[PIPE_CONTROL] = QH_INFO1_TR_TYPE_CTRL,
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[PIPE_BULK] = QH_INFO1_TR_TYPE_BULK,
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};
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return type[usb_pipetype(pipe)];
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}
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/**
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* Maxiumum number of TDs in a qset.
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*/
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#define WHCI_QSET_TD_MAX 8
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/**
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* struct whc_qset - WUSB data transfers to a specific endpoint
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* @qh: the QHead of this qset
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* @qtd: up to 8 qTDs (for qsets for control, bulk and interrupt
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* transfers)
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* @itd: up to 8 iTDs (for qsets for isochronous transfers)
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* @qset_dma: DMA address for this qset
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* @whc: WHCI HC this qset is for
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* @ep: endpoint
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* @stds: list of sTDs queued to this qset
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* @ntds: number of qTDs queued (not necessarily the same as nTDs
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* field in the QH)
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* @td_start: index of the first qTD in the list
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* @td_end: index of next free qTD in the list (provided
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* ntds < WHCI_QSET_TD_MAX)
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*
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* Queue Sets (qsets) are added to the asynchronous schedule list
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* (ASL) or the periodic zone list (PZL).
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*
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* qsets may contain up to 8 TDs (either qTDs or iTDs as appropriate).
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* Each TD may refer to at most 1 MiB of data. If a single transfer
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* has > 8MiB of data, TDs can be reused as they are completed since
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* the TD list is used as a circular buffer. Similarly, several
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* (smaller) transfers may be queued in a qset.
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*
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* WHCI controllers may cache portions of the qsets in the ASL and
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* PZL, requiring the WHCD to inform the WHC that the lists have been
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* updated (fields changed or qsets inserted or removed). For safe
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* insertion and removal of qsets from the lists the schedule must be
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* stopped to avoid races in updating the QH link pointers.
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*
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* Since the HC is free to execute qsets in any order, all transfers
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* to an endpoint should use the same qset to ensure transfers are
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* executed in the order they're submitted.
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*
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* [WHCI] section 3.2.3
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*/
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struct whc_qset {
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struct whc_qhead qh;
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union {
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struct whc_qtd qtd[WHCI_QSET_TD_MAX];
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struct whc_itd itd[WHCI_QSET_TD_MAX];
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};
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/* private data for WHCD */
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dma_addr_t qset_dma;
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struct whc *whc;
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struct usb_host_endpoint *ep;
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struct list_head stds;
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int ntds;
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int td_start;
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int td_end;
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struct list_head list_node;
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unsigned in_sw_list:1;
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unsigned in_hw_list:1;
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unsigned remove:1;
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unsigned reset:1;
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struct urb *pause_after_urb;
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struct completion remove_complete;
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int max_burst;
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int max_seq;
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};
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static inline void whc_qset_set_link_ptr(u64 *ptr, u64 target)
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{
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if (target)
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*ptr = (*ptr & ~(QH_LINK_PTR_MASK | QH_LINK_T)) | QH_LINK_PTR(target);
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else
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*ptr = QH_LINK_T;
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}
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/**
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* struct di_buf_entry - Device Information (DI) buffer entry.
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*
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* There's one of these per connected device.
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*/
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struct di_buf_entry {
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__le32 availability_info[8]; /*< MAS availability information, one MAS per bit */
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__le32 addr_sec_info; /*< addressing and security info */
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__le32 reserved[7];
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} __attribute__((packed));
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#define WHC_DI_SECURE (1 << 31)
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#define WHC_DI_DISABLE (1 << 30)
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#define WHC_DI_KEY_IDX(k) ((k) << 8)
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#define WHC_DI_KEY_IDX_MASK 0x0000ff00
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#define WHC_DI_DEV_ADDR(a) ((a) << 0)
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#define WHC_DI_DEV_ADDR_MASK 0x000000ff
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/**
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* struct dn_buf_entry - Device Notification (DN) buffer entry.
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*
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* [WHCI] section 3.2.8
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*/
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struct dn_buf_entry {
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__u8 msg_size; /*< number of octets of valid DN data */
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__u8 reserved1;
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__u8 src_addr; /*< source address */
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__u8 status; /*< buffer entry status */
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__le32 tkid; /*< TKID for source device, valid if secure bit is set */
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__u8 dn_data[56]; /*< up to 56 octets of DN data */
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} __attribute__((packed));
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#define WHC_DN_STATUS_VALID (1 << 7) /* buffer entry is valid */
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#define WHC_DN_STATUS_SECURE (1 << 6) /* notification received using secure frame */
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#define WHC_N_DN_ENTRIES (4096 / sizeof(struct dn_buf_entry))
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/* The Add MMC IE WUSB Generic Command may take up to 256 bytes of
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data. [WHCI] section 2.4.7. */
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#define WHC_GEN_CMD_DATA_LEN 256
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/*
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* HC registers.
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*
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* [WHCI] section 2.4
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*/
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#define WHCIVERSION 0x00
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#define WHCSPARAMS 0x04
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# define WHCSPARAMS_TO_N_MMC_IES(p) (((p) >> 16) & 0xff)
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# define WHCSPARAMS_TO_N_KEYS(p) (((p) >> 8) & 0xff)
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# define WHCSPARAMS_TO_N_DEVICES(p) (((p) >> 0) & 0x7f)
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#define WUSBCMD 0x08
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# define WUSBCMD_BCID(b) ((b) << 16)
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# define WUSBCMD_BCID_MASK (0xff << 16)
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# define WUSBCMD_ASYNC_QSET_RM (1 << 12)
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# define WUSBCMD_PERIODIC_QSET_RM (1 << 11)
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# define WUSBCMD_WUSBSI(s) ((s) << 8)
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# define WUSBCMD_WUSBSI_MASK (0x7 << 8)
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# define WUSBCMD_ASYNC_SYNCED_DB (1 << 7)
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# define WUSBCMD_PERIODIC_SYNCED_DB (1 << 6)
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||
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# define WUSBCMD_ASYNC_UPDATED (1 << 5)
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# define WUSBCMD_PERIODIC_UPDATED (1 << 4)
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# define WUSBCMD_ASYNC_EN (1 << 3)
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# define WUSBCMD_PERIODIC_EN (1 << 2)
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# define WUSBCMD_WHCRESET (1 << 1)
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||
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# define WUSBCMD_RUN (1 << 0)
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||
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|
||
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#define WUSBSTS 0x0c
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||
|
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# define WUSBSTS_ASYNC_SCHED (1 << 15)
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||
|
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# define WUSBSTS_PERIODIC_SCHED (1 << 14)
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||
|
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# define WUSBSTS_DNTS_SCHED (1 << 13)
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||
|
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# define WUSBSTS_HCHALTED (1 << 12)
|
||
|
|
# define WUSBSTS_GEN_CMD_DONE (1 << 9)
|
||
|
|
# define WUSBSTS_CHAN_TIME_ROLLOVER (1 << 8)
|
||
|
|
# define WUSBSTS_DNTS_OVERFLOW (1 << 7)
|
||
|
|
# define WUSBSTS_BPST_ADJUSTMENT_CHANGED (1 << 6)
|
||
|
|
# define WUSBSTS_HOST_ERR (1 << 5)
|
||
|
|
# define WUSBSTS_ASYNC_SCHED_SYNCED (1 << 4)
|
||
|
|
# define WUSBSTS_PERIODIC_SCHED_SYNCED (1 << 3)
|
||
|
|
# define WUSBSTS_DNTS_INT (1 << 2)
|
||
|
|
# define WUSBSTS_ERR_INT (1 << 1)
|
||
|
|
# define WUSBSTS_INT (1 << 0)
|
||
|
|
# define WUSBSTS_INT_MASK 0x3ff
|
||
|
|
|
||
|
|
#define WUSBINTR 0x10
|
||
|
|
# define WUSBINTR_GEN_CMD_DONE (1 << 9)
|
||
|
|
# define WUSBINTR_CHAN_TIME_ROLLOVER (1 << 8)
|
||
|
|
# define WUSBINTR_DNTS_OVERFLOW (1 << 7)
|
||
|
|
# define WUSBINTR_BPST_ADJUSTMENT_CHANGED (1 << 6)
|
||
|
|
# define WUSBINTR_HOST_ERR (1 << 5)
|
||
|
|
# define WUSBINTR_ASYNC_SCHED_SYNCED (1 << 4)
|
||
|
|
# define WUSBINTR_PERIODIC_SCHED_SYNCED (1 << 3)
|
||
|
|
# define WUSBINTR_DNTS_INT (1 << 2)
|
||
|
|
# define WUSBINTR_ERR_INT (1 << 1)
|
||
|
|
# define WUSBINTR_INT (1 << 0)
|
||
|
|
# define WUSBINTR_ALL 0x3ff
|
||
|
|
|
||
|
|
#define WUSBGENCMDSTS 0x14
|
||
|
|
# define WUSBGENCMDSTS_ACTIVE (1 << 31)
|
||
|
|
# define WUSBGENCMDSTS_ERROR (1 << 24)
|
||
|
|
# define WUSBGENCMDSTS_IOC (1 << 23)
|
||
|
|
# define WUSBGENCMDSTS_MMCIE_ADD 0x01
|
||
|
|
# define WUSBGENCMDSTS_MMCIE_RM 0x02
|
||
|
|
# define WUSBGENCMDSTS_SET_MAS 0x03
|
||
|
|
# define WUSBGENCMDSTS_CHAN_STOP 0x04
|
||
|
|
# define WUSBGENCMDSTS_RWP_EN 0x05
|
||
|
|
|
||
|
|
#define WUSBGENCMDPARAMS 0x18
|
||
|
|
#define WUSBGENADDR 0x20
|
||
|
|
#define WUSBASYNCLISTADDR 0x28
|
||
|
|
#define WUSBDNTSBUFADDR 0x30
|
||
|
|
#define WUSBDEVICEINFOADDR 0x38
|
||
|
|
|
||
|
|
#define WUSBSETSECKEYCMD 0x40
|
||
|
|
# define WUSBSETSECKEYCMD_SET (1 << 31)
|
||
|
|
# define WUSBSETSECKEYCMD_ERASE (1 << 30)
|
||
|
|
# define WUSBSETSECKEYCMD_GTK (1 << 8)
|
||
|
|
# define WUSBSETSECKEYCMD_IDX(i) ((i) << 0)
|
||
|
|
|
||
|
|
#define WUSBTKID 0x44
|
||
|
|
#define WUSBSECKEY 0x48
|
||
|
|
#define WUSBPERIODICLISTBASE 0x58
|
||
|
|
#define WUSBMASINDEX 0x60
|
||
|
|
|
||
|
|
#define WUSBDNTSCTRL 0x64
|
||
|
|
# define WUSBDNTSCTRL_ACTIVE (1 << 31)
|
||
|
|
# define WUSBDNTSCTRL_INTERVAL(i) ((i) << 8)
|
||
|
|
# define WUSBDNTSCTRL_SLOTS(s) ((s) << 0)
|
||
|
|
|
||
|
|
#define WUSBTIME 0x68
|
||
|
|
# define WUSBTIME_CHANNEL_TIME_MASK 0x00ffffff
|
||
|
|
|
||
|
|
#define WUSBBPST 0x6c
|
||
|
|
#define WUSBDIBUPDATED 0x70
|
||
|
|
|
||
|
|
#endif /* #ifndef _WHCI_WHCI_HC_H */
|