327 lines
7.4 KiB
C
327 lines
7.4 KiB
C
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/*
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* MUSB OTG controller driver for Blackfin Processors
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*
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* Copyright 2006-2008 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include "musb_core.h"
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#include "blackfin.h"
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/*
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* Load an endpoint's FIFO
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*/
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void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
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{
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void __iomem *fifo = hw_ep->fifo;
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void __iomem *epio = hw_ep->regs;
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prefetch((u8 *)src);
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musb_writew(epio, MUSB_TXCOUNT, len);
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DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
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hw_ep->epnum, fifo, len, src, epio);
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dump_fifo_data(src, len);
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if (unlikely((unsigned long)src & 0x01))
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outsw_8((unsigned long)fifo, src,
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len & 0x01 ? (len >> 1) + 1 : len >> 1);
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else
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outsw((unsigned long)fifo, src,
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len & 0x01 ? (len >> 1) + 1 : len >> 1);
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}
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/*
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* Unload an endpoint's FIFO
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*/
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void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
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{
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void __iomem *fifo = hw_ep->fifo;
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u8 epnum = hw_ep->epnum;
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u16 dma_reg = 0;
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DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
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'R', hw_ep->epnum, fifo, len, dst);
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#ifdef CONFIG_BF52x
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invalidate_dcache_range((unsigned int)dst,
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(unsigned int)(dst + len));
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/* Setup DMA address register */
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dma_reg = (u16) ((u32) dst & 0xFFFF);
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
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SSYNC();
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dma_reg = (u16) (((u32) dst >> 16) & 0xFFFF);
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
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SSYNC();
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/* Setup DMA count register */
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
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SSYNC();
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/* Enable the DMA */
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dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
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SSYNC();
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/* Wait for compelete */
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while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
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cpu_relax();
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/* acknowledge dma interrupt */
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bfin_write_USB_DMA_INTERRUPT(1 << epnum);
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SSYNC();
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/* Reset DMA */
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
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SSYNC();
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#else
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if (unlikely((unsigned long)dst & 0x01))
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insw_8((unsigned long)fifo, dst,
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len & 0x01 ? (len >> 1) + 1 : len >> 1);
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else
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insw((unsigned long)fifo, dst,
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len & 0x01 ? (len >> 1) + 1 : len >> 1);
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#endif
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dump_fifo_data(dst, len);
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}
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static irqreturn_t blackfin_interrupt(int irq, void *__hci)
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{
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unsigned long flags;
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irqreturn_t retval = IRQ_NONE;
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struct musb *musb = __hci;
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spin_lock_irqsave(&musb->lock, flags);
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musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
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musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
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musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
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if (musb->int_usb || musb->int_tx || musb->int_rx) {
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musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
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musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
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musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
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retval = musb_interrupt(musb);
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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/* REVISIT we sometimes get spurious IRQs on g_ep0
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* not clear why... fall in BF54x too.
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*/
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if (retval != IRQ_HANDLED)
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DBG(5, "spurious?\n");
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return IRQ_HANDLED;
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}
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static void musb_conn_timer_handler(unsigned long _musb)
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{
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struct musb *musb = (void *)_musb;
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unsigned long flags;
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u16 val;
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spin_lock_irqsave(&musb->lock, flags);
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switch (musb->xceiv->state) {
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case OTG_STATE_A_IDLE:
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case OTG_STATE_A_WAIT_BCON:
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/* Start a new session */
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val = musb_readw(musb->mregs, MUSB_DEVCTL);
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val |= MUSB_DEVCTL_SESSION;
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musb_writew(musb->mregs, MUSB_DEVCTL, val);
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val = musb_readw(musb->mregs, MUSB_DEVCTL);
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if (!(val & MUSB_DEVCTL_BDEVICE)) {
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gpio_set_value(musb->config->gpio_vrsel, 1);
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musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
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} else {
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gpio_set_value(musb->config->gpio_vrsel, 0);
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/* Ignore VBUSERROR and SUSPEND IRQ */
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val = musb_readb(musb->mregs, MUSB_INTRUSBE);
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val &= ~MUSB_INTR_VBUSERROR;
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musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
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val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
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musb_writeb(musb->mregs, MUSB_INTRUSB, val);
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val = MUSB_POWER_HSENAB;
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musb_writeb(musb->mregs, MUSB_POWER, val);
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}
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mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
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break;
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default:
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DBG(1, "%s state not handled\n", otg_state_string(musb));
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break;
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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DBG(4, "state is %s\n", otg_state_string(musb));
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}
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void musb_platform_enable(struct musb *musb)
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{
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if (is_host_enabled(musb)) {
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mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
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musb->a_wait_bcon = TIMER_DELAY;
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}
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}
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void musb_platform_disable(struct musb *musb)
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{
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}
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static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
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{
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}
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static void bfin_set_vbus(struct musb *musb, int is_on)
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{
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if (is_on)
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gpio_set_value(musb->config->gpio_vrsel, 1);
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else
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gpio_set_value(musb->config->gpio_vrsel, 0);
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DBG(1, "VBUS %s, devctl %02x "
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/* otg %3x conf %08x prcm %08x */ "\n",
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otg_state_string(musb),
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musb_readb(musb->mregs, MUSB_DEVCTL));
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}
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static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
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{
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return 0;
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}
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void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
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{
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if (is_host_enabled(musb))
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mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
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}
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int musb_platform_get_vbus_status(struct musb *musb)
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{
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return 0;
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}
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void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
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{
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}
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int __init musb_platform_init(struct musb *musb)
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{
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/*
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* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
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* and OTG HOST modes, while rev 1.1 and greater require PE7 to
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* be low for DEVICE mode and high for HOST mode. We set it high
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* here because we are in host mode
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*/
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if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
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printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
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musb->config->gpio_vrsel);
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return -ENODEV;
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}
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gpio_direction_output(musb->config->gpio_vrsel, 0);
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usb_nop_xceiv_register();
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musb->xceiv = otg_get_transceiver();
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if (!musb->xceiv) {
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gpio_free(musb->config->gpio_vrsel);
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return -ENODEV;
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}
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if (ANOMALY_05000346) {
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bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
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SSYNC();
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}
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if (ANOMALY_05000347) {
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bfin_write_USB_APHY_CNTRL(0x0);
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SSYNC();
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}
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/* TODO
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* Set SIC-IVG register
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*/
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/* Configure PLL oscillator register */
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bfin_write_USB_PLLOSC_CTRL(0x30a8);
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SSYNC();
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bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
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SSYNC();
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bfin_write_USB_EP_NI0_RXMAXP(64);
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SSYNC();
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bfin_write_USB_EP_NI0_TXMAXP(64);
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SSYNC();
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/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
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bfin_write_USB_GLOBINTR(0x7);
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SSYNC();
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bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
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EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
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EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
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EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
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EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
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SSYNC();
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if (is_host_enabled(musb)) {
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musb->board_set_vbus = bfin_set_vbus;
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setup_timer(&musb_conn_timer,
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musb_conn_timer_handler, (unsigned long) musb);
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}
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if (is_peripheral_enabled(musb))
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musb->xceiv->set_power = bfin_set_power;
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musb->isr = blackfin_interrupt;
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return 0;
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}
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int musb_platform_suspend(struct musb *musb)
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{
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return 0;
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}
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int musb_platform_resume(struct musb *musb)
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{
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return 0;
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}
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int musb_platform_exit(struct musb *musb)
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{
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bfin_vbus_power(musb, 0 /*off*/, 1);
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gpio_free(musb->config->gpio_vrsel);
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musb_platform_suspend(musb);
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return 0;
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}
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