341 lines
9.5 KiB
C
341 lines
9.5 KiB
C
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/*
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* Copyright (c) 2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "ath9k.h"
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static const struct ath_btcoex_config ath_bt_config = { 0, true, true,
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ATH_BT_COEX_MODE_SLOTTED, true, true, 2, 5, true };
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static const u16 ath_subsysid_tbl[] = {
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AR9280_COEX2WIRE_SUBSYSID,
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AT9285_COEX3WIRE_SA_SUBSYSID,
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AT9285_COEX3WIRE_DA_SUBSYSID
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};
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/*
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* Checks the subsystem id of the device to see if it
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* supports btcoex
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*/
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bool ath_btcoex_supported(u16 subsysid)
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{
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int i;
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if (!subsysid)
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return false;
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for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
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if (subsysid == ath_subsysid_tbl[i])
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return true;
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return false;
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}
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/*
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* Detects if there is any priority bt traffic
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*/
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static void ath_detect_bt_priority(struct ath_softc *sc)
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{
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struct ath_btcoex_info *btinfo = &sc->btcoex_info;
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if (ath9k_hw_gpio_get(sc->sc_ah, btinfo->btpriority_gpio))
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btinfo->bt_priority_cnt++;
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if (time_after(jiffies, btinfo->bt_priority_time +
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msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
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if (btinfo->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
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DPRINTF(sc, ATH_DBG_BTCOEX,
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"BT priority traffic detected");
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sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
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} else {
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sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
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}
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btinfo->bt_priority_cnt = 0;
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btinfo->bt_priority_time = jiffies;
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}
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}
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/*
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* Configures appropriate weight based on stomp type.
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*/
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static void ath_btcoex_bt_stomp(struct ath_softc *sc,
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struct ath_btcoex_info *btinfo,
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int stomp_type)
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{
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switch (stomp_type) {
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case ATH_BTCOEX_STOMP_ALL:
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ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
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AR_STOMP_ALL_WLAN_WGHT);
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break;
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case ATH_BTCOEX_STOMP_LOW:
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ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
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AR_STOMP_LOW_WLAN_WGHT);
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break;
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case ATH_BTCOEX_STOMP_NONE:
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ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
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AR_STOMP_NONE_WLAN_WGHT);
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break;
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default:
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DPRINTF(sc, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
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break;
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}
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ath9k_hw_btcoex_enable(sc->sc_ah);
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}
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/*
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* This is the master bt coex timer which runs for every
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* 45ms, bt traffic will be given priority during 55% of this
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* period while wlan gets remaining 45%
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*/
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static void ath_btcoex_period_timer(unsigned long data)
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{
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struct ath_softc *sc = (struct ath_softc *) data;
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struct ath_btcoex_info *btinfo = &sc->btcoex_info;
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ath_detect_bt_priority(sc);
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spin_lock_bh(&btinfo->btcoex_lock);
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ath_btcoex_bt_stomp(sc, btinfo, btinfo->bt_stomp_type);
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spin_unlock_bh(&btinfo->btcoex_lock);
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if (btinfo->btcoex_period != btinfo->btcoex_no_stomp) {
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if (btinfo->hw_timer_enabled)
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ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer);
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ath_gen_timer_start(sc->sc_ah,
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btinfo->no_stomp_timer,
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(ath9k_hw_gettsf32(sc->sc_ah) +
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btinfo->btcoex_no_stomp),
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btinfo->btcoex_no_stomp * 10);
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btinfo->hw_timer_enabled = true;
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}
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mod_timer(&btinfo->period_timer, jiffies +
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msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
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}
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/*
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* Generic tsf based hw timer which configures weight
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* registers to time slice between wlan and bt traffic
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*/
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static void ath_btcoex_no_stomp_timer(void *arg)
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{
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struct ath_softc *sc = (struct ath_softc *)arg;
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struct ath_btcoex_info *btinfo = &sc->btcoex_info;
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DPRINTF(sc, ATH_DBG_BTCOEX, "no stomp timer running \n");
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spin_lock_bh(&btinfo->btcoex_lock);
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if (btinfo->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
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ath_btcoex_bt_stomp(sc, btinfo, ATH_BTCOEX_STOMP_NONE);
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else if (btinfo->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
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ath_btcoex_bt_stomp(sc, btinfo, ATH_BTCOEX_STOMP_LOW);
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spin_unlock_bh(&btinfo->btcoex_lock);
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}
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static int ath_init_btcoex_info(struct ath_hw *hw,
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struct ath_btcoex_info *btcoex_info)
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{
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u32 i;
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int qnum;
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qnum = ath_tx_get_qnum(hw->ah_sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
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btcoex_info->bt_coex_mode =
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(btcoex_info->bt_coex_mode & AR_BT_QCU_THRESH) |
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SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
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SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
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SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
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SM(ath_bt_config.bt_mode, AR_BT_MODE) |
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SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
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SM(ath_bt_config.bt_rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
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SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
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SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
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SM(qnum, AR_BT_QCU_THRESH);
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btcoex_info->bt_coex_mode2 =
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SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
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SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
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AR_BT_DISABLE_BT_ANT;
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btcoex_info->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
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btcoex_info->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
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btcoex_info->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
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btcoex_info->btcoex_period / 100;
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for (i = 0; i < 32; i++)
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hw->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
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setup_timer(&btcoex_info->period_timer, ath_btcoex_period_timer,
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(unsigned long) hw->ah_sc);
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btcoex_info->no_stomp_timer = ath_gen_timer_alloc(hw,
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ath_btcoex_no_stomp_timer,
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ath_btcoex_no_stomp_timer,
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(void *)hw->ah_sc, AR_FIRST_NDP_TIMER);
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if (btcoex_info->no_stomp_timer == NULL)
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return -ENOMEM;
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spin_lock_init(&btcoex_info->btcoex_lock);
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return 0;
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}
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int ath9k_hw_btcoex_init(struct ath_hw *ah)
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{
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struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
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int ret = 0;
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if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) {
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/* connect bt_active to baseband */
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REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
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(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
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AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
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REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
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AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
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/* Set input mux for bt_active to gpio pin */
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REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
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AR_GPIO_INPUT_MUX1_BT_ACTIVE,
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btcoex_info->btactive_gpio);
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/* Configure the desired gpio port for input */
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ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio);
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} else {
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/* btcoex 3-wire */
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REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
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(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
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AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
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/* Set input mux for bt_prority_async and
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* bt_active_async to GPIO pins */
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REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
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AR_GPIO_INPUT_MUX1_BT_ACTIVE,
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btcoex_info->btactive_gpio);
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REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
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AR_GPIO_INPUT_MUX1_BT_PRIORITY,
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btcoex_info->btpriority_gpio);
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/* Configure the desired GPIO ports for input */
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ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio);
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ath9k_hw_cfg_gpio_input(ah, btcoex_info->btpriority_gpio);
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ret = ath_init_btcoex_info(ah, btcoex_info);
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}
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return ret;
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}
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void ath9k_hw_btcoex_enable(struct ath_hw *ah)
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{
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struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
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if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) {
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/* Configure the desired GPIO port for TX_FRAME output */
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ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
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AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
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} else {
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/*
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* Program coex mode and weight registers to
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* enable coex 3-wire
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*/
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REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_info->bt_coex_mode);
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REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_info->bt_coex_weights);
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REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_info->bt_coex_mode2);
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REG_RMW_FIELD(ah, AR_QUIET1,
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AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
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REG_RMW_FIELD(ah, AR_PCU_MISC,
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AR_PCU_BT_ANT_PREVENT_RX, 0);
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ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
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AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
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}
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REG_RMW(ah, AR_GPIO_PDPU,
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(0x2 << (btcoex_info->btactive_gpio * 2)),
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(0x3 << (btcoex_info->btactive_gpio * 2)));
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ah->ah_sc->sc_flags |= SC_OP_BTCOEX_ENABLED;
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}
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void ath9k_hw_btcoex_disable(struct ath_hw *ah)
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{
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struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
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ath9k_hw_set_gpio(ah, btcoex_info->wlanactive_gpio, 0);
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ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
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AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
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if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) {
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REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
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REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
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REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
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}
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ah->ah_sc->sc_flags &= ~SC_OP_BTCOEX_ENABLED;
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}
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/*
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* Pause btcoex timer and bt duty cycle timer
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*/
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void ath_btcoex_timer_pause(struct ath_softc *sc,
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struct ath_btcoex_info *btinfo)
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{
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del_timer_sync(&btinfo->period_timer);
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if (btinfo->hw_timer_enabled)
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ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer);
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btinfo->hw_timer_enabled = false;
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}
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/*
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* (Re)start btcoex timers
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*/
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void ath_btcoex_timer_resume(struct ath_softc *sc,
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struct ath_btcoex_info *btinfo)
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{
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DPRINTF(sc, ATH_DBG_BTCOEX, "Starting btcoex timers");
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/* make sure duty cycle timer is also stopped when resuming */
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if (btinfo->hw_timer_enabled)
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ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer);
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btinfo->bt_priority_cnt = 0;
|
||
|
|
btinfo->bt_priority_time = jiffies;
|
||
|
|
sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
|
||
|
|
|
||
|
|
mod_timer(&btinfo->period_timer, jiffies);
|
||
|
|
}
|