171 lines
6.7 KiB
C
171 lines
6.7 KiB
C
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/*
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* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef _MALI200_REGS_H_
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#define _MALI200_REGS_H_
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/**
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* Enum for management register addresses.
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*/
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enum mali200_mgmt_reg
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{
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MALI200_REG_ADDR_MGMT_VERSION = 0x1000,
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MALI200_REG_ADDR_MGMT_CURRENT_REND_LIST_ADDR = 0x1004,
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MALI200_REG_ADDR_MGMT_STATUS = 0x1008,
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MALI200_REG_ADDR_MGMT_CTRL_MGMT = 0x100c,
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MALI200_REG_ADDR_MGMT_INT_RAWSTAT = 0x1020,
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MALI200_REG_ADDR_MGMT_INT_CLEAR = 0x1024,
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MALI200_REG_ADDR_MGMT_INT_MASK = 0x1028,
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MALI200_REG_ADDR_MGMT_INT_STATUS = 0x102c,
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MALI200_REG_ADDR_MGMT_WRITE_BOUNDARY_LOW = 0x1044,
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MALI200_REG_ADDR_MGMT_BUS_ERROR_STATUS = 0x1050,
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MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE = 0x1080,
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MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC = 0x1084,
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MALI200_REG_ADDR_MGMT_PERF_CNT_0_VALUE = 0x108c,
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MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE = 0x10a0,
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MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC = 0x10a4,
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MALI200_REG_ADDR_MGMT_PERF_CNT_1_VALUE = 0x10ac,
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MALI200_REG_SIZEOF_REGISTER_BANK = 0x10f0
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};
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#define MALI200_REG_VAL_PERF_CNT_ENABLE 1
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enum mali200_mgmt_ctrl_mgmt {
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MALI200_REG_VAL_CTRL_MGMT_STOP_BUS = (1<<0),
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#if defined(USING_MALI200)
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MALI200_REG_VAL_CTRL_MGMT_FLUSH_CACHES = (1<<3),
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#endif
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MALI200_REG_VAL_CTRL_MGMT_FORCE_RESET = (1<<5),
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MALI200_REG_VAL_CTRL_MGMT_START_RENDERING = (1<<6),
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#if defined(USING_MALI400)
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MALI400PP_REG_VAL_CTRL_MGMT_SOFT_RESET = (1<<7),
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#endif
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};
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enum mali200_mgmt_irq {
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MALI200_REG_VAL_IRQ_END_OF_FRAME = (1<<0),
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MALI200_REG_VAL_IRQ_END_OF_TILE = (1<<1),
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MALI200_REG_VAL_IRQ_HANG = (1<<2),
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MALI200_REG_VAL_IRQ_FORCE_HANG = (1<<3),
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MALI200_REG_VAL_IRQ_BUS_ERROR = (1<<4),
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MALI200_REG_VAL_IRQ_BUS_STOP = (1<<5),
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MALI200_REG_VAL_IRQ_CNT_0_LIMIT = (1<<6),
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MALI200_REG_VAL_IRQ_CNT_1_LIMIT = (1<<7),
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MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR = (1<<8),
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MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND = (1<<9),
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MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW = (1<<10),
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MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW = (1<<11),
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MALI400PP_REG_VAL_IRQ_RESET_COMPLETED = (1<<12),
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};
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#if defined USING_MALI200
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#define MALI200_REG_VAL_IRQ_MASK_ALL ((enum mali200_mgmt_irq) (\
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MALI200_REG_VAL_IRQ_END_OF_FRAME |\
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MALI200_REG_VAL_IRQ_END_OF_TILE |\
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MALI200_REG_VAL_IRQ_HANG |\
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MALI200_REG_VAL_IRQ_FORCE_HANG |\
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MALI200_REG_VAL_IRQ_BUS_ERROR |\
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MALI200_REG_VAL_IRQ_BUS_STOP |\
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MALI200_REG_VAL_IRQ_CNT_0_LIMIT |\
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MALI200_REG_VAL_IRQ_CNT_1_LIMIT |\
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MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR))
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#elif defined USING_MALI400
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#define MALI200_REG_VAL_IRQ_MASK_ALL ((enum mali200_mgmt_irq) (\
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MALI200_REG_VAL_IRQ_END_OF_FRAME |\
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MALI200_REG_VAL_IRQ_END_OF_TILE |\
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MALI200_REG_VAL_IRQ_HANG |\
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MALI200_REG_VAL_IRQ_FORCE_HANG |\
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MALI200_REG_VAL_IRQ_BUS_ERROR |\
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MALI200_REG_VAL_IRQ_BUS_STOP |\
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MALI200_REG_VAL_IRQ_CNT_0_LIMIT |\
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MALI200_REG_VAL_IRQ_CNT_1_LIMIT |\
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MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR |\
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MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND |\
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MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW |\
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MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW |\
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MALI400PP_REG_VAL_IRQ_RESET_COMPLETED))
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#else
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#error "No supported mali core defined"
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#endif
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#if defined USING_MALI200
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#define MALI200_REG_VAL_IRQ_MASK_USED ((enum mali200_mgmt_irq) (\
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MALI200_REG_VAL_IRQ_END_OF_FRAME |\
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MALI200_REG_VAL_IRQ_HANG |\
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MALI200_REG_VAL_IRQ_FORCE_HANG |\
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MALI200_REG_VAL_IRQ_BUS_ERROR |\
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MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR))
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#elif defined USING_MALI400
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#define MALI200_REG_VAL_IRQ_MASK_USED ((enum mali200_mgmt_irq) (\
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MALI200_REG_VAL_IRQ_END_OF_FRAME |\
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MALI200_REG_VAL_IRQ_HANG |\
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MALI200_REG_VAL_IRQ_FORCE_HANG |\
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MALI200_REG_VAL_IRQ_BUS_ERROR |\
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MALI200_REG_VAL_IRQ_BUS_STOP |\
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MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR |\
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MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND |\
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MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW |\
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MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW))
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#else
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#error "No supported mali core defined"
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#endif
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#define MALI200_REG_VAL_IRQ_MASK_NONE ((enum mali200_mgmt_irq)(0))
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enum mali200_mgmt_status {
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MALI200_REG_VAL_STATUS_RENDERING_ACTIVE = (1<<0),
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MALI200_REG_VAL_STATUS_BUS_STOPPED = (1<<4),
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};
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enum mali200_render_unit
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{
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MALI200_REG_ADDR_FRAME = 0x0000,
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};
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#if defined USING_MALI200
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#define MALI200_NUM_REGS_FRAME ((0x04C/4)+1)
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#elif defined USING_MALI400
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#define MALI200_NUM_REGS_FRAME ((0x058/4)+1)
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#else
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#error "No supported mali core defined"
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#endif
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enum mali200_wb_unit {
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MALI200_REG_ADDR_WB0 = 0x0100,
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MALI200_REG_ADDR_WB1 = 0x0200,
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MALI200_REG_ADDR_WB2 = 0x0300
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};
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/** The number of registers in one single writeback unit */
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#ifndef MALI200_NUM_REGS_WBx
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#define MALI200_NUM_REGS_WBx ((0x02C/4)+1)
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#endif
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/* This should be in the top 16 bit of the version register of Mali PP */
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#if defined USING_MALI200
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#define MALI_PP_PRODUCT_ID 0xC807
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#elif defined USING_MALI400
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#define MALI300_PP_PRODUCT_ID 0xCE07
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#define MALI400_PP_PRODUCT_ID 0xCD07
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#define MALI_PP_PRODUCT_ID MALI400_PP_PRODUCT_ID
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#else
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#error "No supported mali core defined"
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#endif
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#endif /* _MALI200_REGS_H_ */
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