220 lines
8.3 KiB
C
220 lines
8.3 KiB
C
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/*
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* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef _MALIGP2_CONROL_REGS_H_
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#define _MALIGP2_CONROL_REGS_H_
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/**
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* These are the different geometry processor controll registers.
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* Their usage is to control and monitor the operation of the
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* Vertex Shader and the Polygon List Builer in the geometry processor.
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* Addresses are in 32-bit word relative sizes.
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* @see [P0081] "Geometry Processor Data Structures" for details
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*/
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typedef enum {
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MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR = 0x00,
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MALIGP2_REG_ADDR_MGMT_VSCL_END_ADDR = 0x04,
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MALIGP2_REG_ADDR_MGMT_PLBUCL_START_ADDR = 0x08,
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MALIGP2_REG_ADDR_MGMT_PLBUCL_END_ADDR = 0x0c,
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MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR = 0x10,
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MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_END_ADDR = 0x14,
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MALIGP2_REG_ADDR_MGMT_CMD = 0x20,
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MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT = 0x24,
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MALIGP2_REG_ADDR_MGMT_INT_CLEAR = 0x28,
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MALIGP2_REG_ADDR_MGMT_INT_MASK = 0x2C,
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MALIGP2_REG_ADDR_MGMT_INT_STAT = 0x30,
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MALIGP2_REG_ADDR_MGMT_WRITE_BOUND_LOW = 0x34,
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MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE = 0x3C,
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MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE = 0x40,
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MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC = 0x44,
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MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC = 0x48,
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MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE = 0x4C,
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MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE = 0x50,
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MALIGP2_REG_ADDR_MGMT_STATUS = 0x68,
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MALIGP2_REG_ADDR_MGMT_VERSION = 0x6C,
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MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR_READ = 0x80,
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MALIGP2_REG_ADDR_MGMT_PLBCL_START_ADDR_READ = 0x84,
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MALIGP2_CONTR_AXI_BUS_ERROR_STAT = 0x94,
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MALIGP2_REGISTER_ADDRESS_SPACE_SIZE = 0x98,
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} maligp_reg_addr_mgmt_addr;
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#define MALIGP2_REG_VAL_PERF_CNT_ENABLE 1
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/**
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* Commands to geometry processor.
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* @see MALIGP2_CTRL_REG_CMD
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*/
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typedef enum
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{
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MALIGP2_REG_VAL_CMD_START_VS = (1<< 0),
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MALIGP2_REG_VAL_CMD_START_PLBU = (1<< 1),
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MALIGP2_REG_VAL_CMD_UPDATE_PLBU_ALLOC = (1<< 4),
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MALIGP2_REG_VAL_CMD_RESET = (1<< 5),
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MALIGP2_REG_VAL_CMD_FORCE_HANG = (1<< 6),
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MALIGP2_REG_VAL_CMD_STOP_BUS = (1<< 9),
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#if defined(USING_MALI400)
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MALI400GP_REG_VAL_CMD_SOFT_RESET = (1<<10),
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#endif
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} mgp_contr_reg_val_cmd;
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/** @defgroup MALIGP2_IRQ
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* Interrupt status of geometry processor.
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* @see MALIGP2_CTRL_REG_INT_RAWSTAT, MALIGP2_REG_ADDR_MGMT_INT_CLEAR,
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* MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_ADDR_MGMT_INT_STAT
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* @{
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*/
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#define MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST (1 << 0)
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#define MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST (1 << 1)
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#define MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM (1 << 2)
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#define MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ (1 << 3)
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#define MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ (1 << 4)
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#define MALIGP2_REG_VAL_IRQ_HANG (1 << 5)
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#define MALIGP2_REG_VAL_IRQ_FORCE_HANG (1 << 6)
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#define MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT (1 << 7)
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#define MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT (1 << 8)
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#define MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR (1 << 9)
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#define MALIGP2_REG_VAL_IRQ_SYNC_ERROR (1 << 10)
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#define MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR (1 << 11)
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#if defined USING_MALI400
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#define MALI400GP_REG_VAL_IRQ_AXI_BUS_STOPPED (1 << 12)
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#define MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD (1 << 13)
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#define MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD (1 << 14)
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#define MALI400GP_REG_VAL_IRQ_RESET_COMPLETED (1 << 19)
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#define MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW (1 << 20)
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#define MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW (1 << 21)
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#define MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS (1 << 22)
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#elif !defined USING_MALI200
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#error "No supported mali core defined"
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#endif
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/* Mask defining all IRQs in MaliGP2 */
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#if defined USING_MALI200
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#define MALIGP2_REG_VAL_IRQ_MASK_ALL \
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(\
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MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST | \
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MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST | \
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MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM | \
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MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ | \
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MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ | \
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MALIGP2_REG_VAL_IRQ_HANG | \
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MALIGP2_REG_VAL_IRQ_FORCE_HANG | \
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MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT | \
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MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT | \
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MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR | \
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MALIGP2_REG_VAL_IRQ_SYNC_ERROR | \
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MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR)
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#elif defined USING_MALI400
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#define MALIGP2_REG_VAL_IRQ_MASK_ALL \
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(\
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MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST | \
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MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST | \
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MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM | \
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MALIGP2_REG_VAL_IRQ_VS_SEM_IRQ | \
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MALIGP2_REG_VAL_IRQ_PLBU_SEM_IRQ | \
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MALIGP2_REG_VAL_IRQ_HANG | \
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MALIGP2_REG_VAL_IRQ_FORCE_HANG | \
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MALIGP2_REG_VAL_IRQ_PERF_CNT_0_LIMIT | \
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MALIGP2_REG_VAL_IRQ_PERF_CNT_1_LIMIT | \
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MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR | \
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MALIGP2_REG_VAL_IRQ_SYNC_ERROR | \
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MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR | \
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MALI400GP_REG_VAL_IRQ_AXI_BUS_STOPPED | \
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MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD | \
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MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD | \
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MALI400GP_REG_VAL_IRQ_RESET_COMPLETED | \
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MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW | \
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MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW | \
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MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
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#else
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#error "No supported mali core defined"
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#endif
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/* Mask defining the IRQs in MaliGP2 which we use*/
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#if defined USING_MALI200
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#define MALIGP2_REG_VAL_IRQ_MASK_USED \
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(\
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MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST | \
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MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST | \
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MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM | \
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MALIGP2_REG_VAL_IRQ_HANG | \
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MALIGP2_REG_VAL_IRQ_FORCE_HANG | \
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MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR | \
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MALIGP2_REG_VAL_IRQ_SYNC_ERROR | \
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MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR)
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#elif defined USING_MALI400
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#define MALIGP2_REG_VAL_IRQ_MASK_USED \
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(\
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MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST | \
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MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST | \
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MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM | \
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MALIGP2_REG_VAL_IRQ_HANG | \
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MALIGP2_REG_VAL_IRQ_FORCE_HANG | \
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MALIGP2_REG_VAL_IRQ_WRITE_BOUND_ERR | \
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MALIGP2_REG_VAL_IRQ_SYNC_ERROR | \
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MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR | \
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MALI400GP_REG_VAL_IRQ_VS_INVALID_CMD | \
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MALI400GP_REG_VAL_IRQ_PLB_INVALID_CMD | \
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MALI400GP_REG_VAL_IRQ_SEMAPHORE_UNDERFLOW | \
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MALI400GP_REG_VAL_IRQ_SEMAPHORE_OVERFLOW | \
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MALI400GP_REG_VAL_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
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#else
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#error "No supported mali core defined"
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#endif
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/* Mask defining non IRQs on MaliGP2*/
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#define MALIGP2_REG_VAL_IRQ_MASK_NONE 0
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/** }@ defgroup MALIGP2_IRQ*/
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/** @defgroup MALIGP2_STATUS
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* The different Status values to the geometry processor.
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* @see MALIGP2_CTRL_REG_STATUS
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* @{
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*/
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#define MALIGP2_REG_VAL_STATUS_VS_ACTIVE 0x0002
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#define MALIGP2_REG_VAL_STATUS_BUS_STOPPED 0x0004
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#define MALIGP2_REG_VAL_STATUS_PLBU_ACTIVE 0x0008
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#define MALIGP2_REG_VAL_STATUS_BUS_ERROR 0x0040
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#define MALIGP2_REG_VAL_STATUS_WRITE_BOUND_ERR 0x0100
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/** }@ defgroup MALIGP2_STATUS*/
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#define MALIGP2_REG_VAL_STATUS_MASK_ACTIVE (\
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MALIGP2_REG_VAL_STATUS_VS_ACTIVE|\
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MALIGP2_REG_VAL_STATUS_PLBU_ACTIVE)
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#define MALIGP2_REG_VAL_STATUS_MASK_ERROR (\
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MALIGP2_REG_VAL_STATUS_BUS_ERROR |\
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MALIGP2_REG_VAL_STATUS_WRITE_BOUND_ERR )
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/* This should be in the top 16 bit of the version register of gp.*/
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#if defined(USING_MALI200)
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#define MALI_GP_PRODUCT_ID 0xA07
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#elif defined(USING_MALI400)
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#define MALI300_GP_PRODUCT_ID 0xC07
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#define MALI400_GP_PRODUCT_ID 0xB07
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#define MALI_GP_PRODUCT_ID MALI400_GP_PRODUCT_ID
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#else
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#error "No supported mali core defined"
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#endif
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/**
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* The different sources for instrumented on the geometry processor.
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* @see MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC
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*/
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enum MALIGP2_cont_reg_perf_cnt_src {
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MALIGP2_REG_VAL_PERF_CNT1_SRC_NUMBER_OF_VERTICES_PROCESSED = 0x0a,
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};
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#endif
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