185 lines
6.1 KiB
C
185 lines
6.1 KiB
C
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/*
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* Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
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* Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/*
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* This file is conditionally built on x86_64 only. Otherwise weak symbol
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* versions of the functions exported from here are used.
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*/
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#include <linux/pci.h>
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#include <asm/mtrr.h>
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#include <asm/processor.h>
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#include "ipath_kernel.h"
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/**
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* ipath_enable_wc - enable write combining for MMIO writes to the device
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* @dd: infinipath device
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*
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* This routine is x86_64-specific; it twiddles the CPU's MTRRs to enable
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* write combining.
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*/
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int ipath_enable_wc(struct ipath_devdata *dd)
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{
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int ret = 0;
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u64 pioaddr, piolen;
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unsigned bits;
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const unsigned long addr = pci_resource_start(dd->pcidev, 0);
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const size_t len = pci_resource_len(dd->pcidev, 0);
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/*
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* Set the PIO buffers to be WCCOMB, so we get HT bursts to the
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* chip. Linux (possibly the hardware) requires it to be on a power
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* of 2 address matching the length (which has to be a power of 2).
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* For rev1, that means the base address, for rev2, it will be just
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* the PIO buffers themselves.
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* For chips with two sets of buffers, the calculations are
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* somewhat more complicated; we need to sum, and the piobufbase
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* register has both offsets, 2K in low 32 bits, 4K in high 32 bits.
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* The buffers are still packed, so a single range covers both.
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*/
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if (dd->ipath_piobcnt2k && dd->ipath_piobcnt4k) { /* 2 sizes */
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unsigned long pio2kbase, pio4kbase;
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pio2kbase = dd->ipath_piobufbase & 0xffffffffUL;
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pio4kbase = (dd->ipath_piobufbase >> 32) & 0xffffffffUL;
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if (pio2kbase < pio4kbase) { /* all, for now */
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pioaddr = addr + pio2kbase;
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piolen = pio4kbase - pio2kbase +
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dd->ipath_piobcnt4k * dd->ipath_4kalign;
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} else {
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pioaddr = addr + pio4kbase;
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piolen = pio2kbase - pio4kbase +
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dd->ipath_piobcnt2k * dd->ipath_palign;
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}
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} else { /* single buffer size (2K, currently) */
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pioaddr = addr + dd->ipath_piobufbase;
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piolen = dd->ipath_piobcnt2k * dd->ipath_palign +
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dd->ipath_piobcnt4k * dd->ipath_4kalign;
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}
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for (bits = 0; !(piolen & (1ULL << bits)); bits++)
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/* do nothing */ ;
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if (piolen != (1ULL << bits)) {
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piolen >>= bits;
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while (piolen >>= 1)
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bits++;
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piolen = 1ULL << (bits + 1);
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}
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if (pioaddr & (piolen - 1)) {
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u64 atmp;
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ipath_dbg("pioaddr %llx not on right boundary for size "
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"%llx, fixing\n",
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(unsigned long long) pioaddr,
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(unsigned long long) piolen);
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atmp = pioaddr & ~(piolen - 1);
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if (atmp < addr || (atmp + piolen) > (addr + len)) {
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ipath_dev_err(dd, "No way to align address/size "
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"(%llx/%llx), no WC mtrr\n",
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(unsigned long long) atmp,
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(unsigned long long) piolen << 1);
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ret = -ENODEV;
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} else {
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ipath_dbg("changing WC base from %llx to %llx, "
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"len from %llx to %llx\n",
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(unsigned long long) pioaddr,
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(unsigned long long) atmp,
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(unsigned long long) piolen,
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(unsigned long long) piolen << 1);
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pioaddr = atmp;
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piolen <<= 1;
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}
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}
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if (!ret) {
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int cookie;
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ipath_cdbg(VERBOSE, "Setting mtrr for chip to WC "
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"(addr %llx, len=0x%llx)\n",
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(unsigned long long) pioaddr,
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(unsigned long long) piolen);
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cookie = mtrr_add(pioaddr, piolen, MTRR_TYPE_WRCOMB, 0);
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if (cookie < 0) {
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{
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dev_info(&dd->pcidev->dev,
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"mtrr_add() WC for PIO bufs "
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"failed (%d)\n",
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cookie);
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ret = -EINVAL;
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}
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} else {
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ipath_cdbg(VERBOSE, "Set mtrr for chip to WC, "
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"cookie is %d\n", cookie);
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dd->ipath_wc_cookie = cookie;
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dd->ipath_wc_base = (unsigned long) pioaddr;
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dd->ipath_wc_len = (unsigned long) piolen;
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}
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}
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return ret;
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}
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/**
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* ipath_disable_wc - disable write combining for MMIO writes to the device
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* @dd: infinipath device
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*/
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void ipath_disable_wc(struct ipath_devdata *dd)
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{
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if (dd->ipath_wc_cookie) {
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int r;
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ipath_cdbg(VERBOSE, "undoing WCCOMB on pio buffers\n");
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r = mtrr_del(dd->ipath_wc_cookie, dd->ipath_wc_base,
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dd->ipath_wc_len);
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if (r < 0)
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dev_info(&dd->pcidev->dev,
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"mtrr_del(%lx, %lx, %lx) failed: %d\n",
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dd->ipath_wc_cookie, dd->ipath_wc_base,
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dd->ipath_wc_len, r);
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dd->ipath_wc_cookie = 0; /* even on failure */
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}
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}
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/**
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* ipath_unordered_wc - indicate whether write combining is ordered
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*
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* Because our performance depends on our ability to do write combining mmio
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* writes in the most efficient way, we need to know if we are on an Intel
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* or AMD x86_64 processor. AMD x86_64 processors flush WC buffers out in
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* the order completed, and so no special flushing is required to get
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* correct ordering. Intel processors, however, will flush write buffers
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* out in "random" orders, and so explicit ordering is needed at times.
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*/
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int ipath_unordered_wc(void)
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{
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return boot_cpu_data.x86_vendor != X86_VENDOR_AMD;
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}
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