161 lines
4.4 KiB
C
161 lines
4.4 KiB
C
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/*
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* stm_spi_fsm.h Support for STM SPI FSM Controller
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*
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* Author: Angus Clark <angus.clark@st.com>
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*
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* Copyright (C) 2010 STMicroelectronics Limited
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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*/
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#ifndef STM_SPI_FSM_H
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#define STM_SPI_FSM_H
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/*
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* FSM SPI Controller Registers
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*/
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#define SPI_CLOCKDIV 0x0010
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#define SPI_MODESELECT 0x0018
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#define SPI_CONFIGDATA 0x0020
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#define SPI_STA_MODE_CHANGE 0x0028
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#define SPI_FAST_SEQ_TRANSFER_SIZE 0x0100
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#define SPI_FAST_SEQ_ADD1 0x0104
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#define SPI_FAST_SEQ_ADD2 0x0108
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#define SPI_FAST_SEQ_ADD_CFG 0x010c
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#define SPI_FAST_SEQ_OPC1 0x0110
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#define SPI_FAST_SEQ_OPC2 0x0114
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#define SPI_FAST_SEQ_OPC3 0x0118
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#define SPI_FAST_SEQ_OPC4 0x011c
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#define SPI_FAST_SEQ_OPC5 0x0120
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#define SPI_MODE_BITS 0x0124
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#define SPI_DUMMY_BITS 0x0128
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#define SPI_FAST_SEQ_FLASH_STA_DATA 0x012c
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#define SPI_FAST_SEQ_1 0x0130
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#define SPI_FAST_SEQ_2 0x0134
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#define SPI_FAST_SEQ_3 0x0138
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#define SPI_FAST_SEQ_4 0x013c
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#define SPI_FAST_SEQ_CFG 0x0140
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#define SPI_FAST_SEQ_STA 0x0144
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#define SPI_QUAD_BOOT_SEQ_INIT_1 0x0148
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#define SPI_QUAD_BOOT_SEQ_INIT_2 0x014c
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#define SPI_QUAD_BOOT_READ_SEQ_1 0x0150
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#define SPI_QUAD_BOOT_READ_SEQ_2 0x0154
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#define SPI_PROGRAM_ERASE_TIME 0x0158
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#define SPI_MULT_PAGE_REPEAT_SEQ_1 0x015c
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#define SPI_MULT_PAGE_REPEAT_SEQ_2 0x0160
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#define SPI_STATUS_WR_TIME_REG 0x0164
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#define SPI_FAST_SEQ_DATA_REG 0x0300
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/*
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* Register: SPI_MODESELECT
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*/
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#define SPI_MODESELECT_CONTIG 0x01
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#define SPI_MODESELECT_FASTREAD 0x02
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#define SPI_MODESELECT_DUALIO 0x04
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#define SPI_MODESELECT_FSM 0x08
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#define SPI_MODESELECT_QUAD 0x10
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/*
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* Register: SPI_CONFIGDATA
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*/
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#define SPI_CFG_DEVICE_ST 0x1
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#define SPI_CFG_DEVICE_ATMEL 0x4
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#define SPI_CFG_MIN_CS_HIGH(x) (((x) & 0xfff) << 4)
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#define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16)
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#define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24)
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/*
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* Register: SPI_FAST_SEQ_TRANSFER_SIZE
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*/
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#define TRANSFER_SIZE(x) ((x) * 8)
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/*
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* Register: SPI_FAST_SEQ_ADD_CFG
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*/
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#define ADR_CFG_CYCLES_ADD1(x) ((x) << 0)
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#define ADR_CFG_PADS_1_ADD1 (0x0 << 6)
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#define ADR_CFG_PADS_2_ADD1 (0x1 << 6)
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#define ADR_CFG_PADS_4_ADD1 (0x3 << 6)
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#define ADR_CFG_CSDEASSERT_ADD1 (1 << 8)
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#define ADR_CFG_CYCLES_ADD2(x) ((x) << (0+16))
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#define ADR_CFG_PADS_1_ADD2 (0x0 << (6+16))
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#define ADR_CFG_PADS_2_ADD2 (0x1 << (6+16))
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#define ADR_CFG_PADS_4_ADD2 (0x3 << (6+16))
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#define ADR_CFG_CSDEASSERT_ADD2 (1 << (8+16))
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/*
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* Register: SPI_FAST_SEQ_n
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*/
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#define SEQ_OPC_OPCODE(x) ((x) << 0)
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#define SEQ_OPC_CYCLES(x) ((x) << 8)
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#define SEQ_OPC_PADS_1 (0x0 << 14)
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#define SEQ_OPC_PADS_2 (0x1 << 14)
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#define SEQ_OPC_PADS_4 (0x3 << 14)
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#define SEQ_OPC_CSDEASSERT (1 << 16)
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/*
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* Register: SPI_FAST_SEQ_CFG
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*/
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#define SEQ_CFG_STARTSEQ (1 << 0)
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#define SEQ_CFG_SWRESET (1 << 5)
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#define SEQ_CFG_CSDEASSERT (1 << 6)
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#define SEQ_CFG_READNOTWRITE (1 << 7)
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#define SEQ_CFG_ERASE (1 << 8)
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#define SEQ_CFG_PADS_1 (0x0 << 16)
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#define SEQ_CFG_PADS_2 (0x1 << 16)
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#define SEQ_CFG_PADS_4 (0x3 << 16)
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/*
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* Register: SPI_DUMMY_BITS
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*/
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#define DUMMY_CYCLES(x) ((x) << 16)
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#define DUMMY_PADS_1 (0x0 << 22)
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#define DUMMY_PADS_2 (0x1 << 22)
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#define DUMMY_PADS_4 (0x3 << 22)
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#define DUMMY_CSDEASSERT (1 << 24)
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/*
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* FSM SPI Instruction Opcodes
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*/
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#define FSM_OPC_CMD 0x1
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#define FSM_OPC_ADD 0x2
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#define FSM_OPC_STATUS_REG_DATA 0x3
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#define FSM_OPC_MODE 0x4
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#define FSM_OPC_DUMMY 0x5
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#define FSM_OPC_DATA 0x6
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#define FSM_OPC_WAIT 0x7
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#define FSM_OPC_JUMP 0x8
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#define FSM_OPC_GOTO 0x9
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#define FSM_OPC_STOP 0xF
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/*
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* FSM SPI Instructions (== opcode + operand).
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*/
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#define FSM_INSTR(cmd, op) ((cmd) | ((op) << 4))
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#define FSM_INST_CMD1 FSM_INSTR(FSM_OPC_CMD, 1)
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#define FSM_INST_CMD2 FSM_INSTR(FSM_OPC_CMD, 2)
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#define FSM_INST_CMD3 FSM_INSTR(FSM_OPC_CMD, 3)
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#define FSM_INST_CMD4 FSM_INSTR(FSM_OPC_CMD, 4)
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#define FSM_INST_CMD5 FSM_INSTR(FSM_OPC_CMD, 5)
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#define FSM_INST_ADD1 FSM_INSTR(FSM_OPC_ADD, 1)
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#define FSM_INST_ADD2 FSM_INSTR(FSM_OPC_ADD, 2)
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#define FSM_INST_DATA_WRITE FSM_INSTR(FSM_OPC_DATA, 1)
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#define FSM_INST_DATA_READ FSM_INSTR(FSM_OPC_DATA, 2)
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#define FSM_INST_MODE FSM_INSTR(FSM_OPC_MODE, 0)
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#define FSM_INST_DUMMY FSM_INSTR(FSM_OPC_DUMMY, 0)
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#define FSM_INST_WAIT FSM_INSTR(FSM_OPC_WAIT, 0)
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#define FSM_INST_STOP FSM_INSTR(FSM_OPC_STOP, 0)
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#endif /* STM_SPI_FSM_H */
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