397 lines
11 KiB
C
397 lines
11 KiB
C
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/*
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* MPC5200 General Purpose Timer device driver
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*
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* Copyright (c) 2009 Secret Lab Technologies Ltd.
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* Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This file is a driver for the the General Purpose Timer (gpt) devices
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* found on the MPC5200 SoC. Each timer has an IO pin which can be used
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* for GPIO or can be used to raise interrupts. The timer function can
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* be used independently from the IO pin, or it can be used to control
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* output signals or measure input signals.
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*
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* This driver supports the GPIO and IRQ controller functions of the GPT
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* device. Timer functions are not yet supported, nor is the watchdog
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* timer.
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*
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* To use the GPIO function, the following two properties must be added
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* to the device tree node for the gpt device (typically in the .dts file
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* for the board):
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* gpio-controller;
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* #gpio-cells = < 2 >;
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* This driver will register the GPIO pin if it finds the gpio-controller
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* property in the device tree.
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*
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* To use the IRQ controller function, the following two properties must
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* be added to the device tree node for the gpt device:
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* interrupt-controller;
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* #interrupt-cells = < 1 >;
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* The IRQ controller binding only uses one cell to specify the interrupt,
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* and the IRQ flags are encoded in the cell. A cell is not used to encode
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* the IRQ number because the GPT only has a single IRQ source. For flags,
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* a value of '1' means rising edge sensitive and '2' means falling edge.
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*
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* The GPIO and the IRQ controller functions can be used at the same time,
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* but in this use case the IO line will only work as an input. Trying to
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* use it as a GPIO output will not work.
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*
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* When using the GPIO line as an output, it can either be driven as normal
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* IO, or it can be an Open Collector (OC) output. At the moment it is the
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* responsibility of either the bootloader or the platform setup code to set
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* the output mode. This driver does not change the output mode setting.
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*/
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/kernel.h>
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#include <asm/mpc52xx.h>
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MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
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MODULE_AUTHOR("Sascha Hauer, Grant Likely");
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MODULE_LICENSE("GPL");
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/**
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* struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
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* @dev: pointer to device structure
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* @regs: virtual address of GPT registers
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* @lock: spinlock to coordinate between different functions.
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* @of_gc: of_gpio_chip instance structure; used when GPIO is enabled
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* @irqhost: Pointer to irq_host instance; used when IRQ mode is supported
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*/
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struct mpc52xx_gpt_priv {
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struct device *dev;
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struct mpc52xx_gpt __iomem *regs;
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spinlock_t lock;
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struct irq_host *irqhost;
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#if defined(CONFIG_GPIOLIB)
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struct of_gpio_chip of_gc;
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#endif
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};
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#define MPC52xx_GPT_MODE_MS_MASK (0x07)
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#define MPC52xx_GPT_MODE_MS_IC (0x01)
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#define MPC52xx_GPT_MODE_MS_OC (0x02)
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#define MPC52xx_GPT_MODE_MS_PWM (0x03)
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#define MPC52xx_GPT_MODE_MS_GPIO (0x04)
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#define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
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#define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
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#define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
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#define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
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#define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
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#define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
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#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
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#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
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#define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
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/* ---------------------------------------------------------------------
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* Cascaded interrupt controller hooks
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*/
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static void mpc52xx_gpt_irq_unmask(unsigned int virq)
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{
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struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
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unsigned long flags;
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spin_lock_irqsave(&gpt->lock, flags);
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setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
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spin_unlock_irqrestore(&gpt->lock, flags);
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}
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static void mpc52xx_gpt_irq_mask(unsigned int virq)
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{
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struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
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unsigned long flags;
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spin_lock_irqsave(&gpt->lock, flags);
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clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
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spin_unlock_irqrestore(&gpt->lock, flags);
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}
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static void mpc52xx_gpt_irq_ack(unsigned int virq)
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{
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struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
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out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
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}
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static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type)
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{
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struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
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unsigned long flags;
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u32 reg;
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dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, virq, flow_type);
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spin_lock_irqsave(&gpt->lock, flags);
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reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
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if (flow_type & IRQF_TRIGGER_RISING)
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reg |= MPC52xx_GPT_MODE_ICT_RISING;
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if (flow_type & IRQF_TRIGGER_FALLING)
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reg |= MPC52xx_GPT_MODE_ICT_FALLING;
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out_be32(&gpt->regs->mode, reg);
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spin_unlock_irqrestore(&gpt->lock, flags);
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return 0;
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}
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static struct irq_chip mpc52xx_gpt_irq_chip = {
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.typename = "MPC52xx GPT",
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.unmask = mpc52xx_gpt_irq_unmask,
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.mask = mpc52xx_gpt_irq_mask,
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.ack = mpc52xx_gpt_irq_ack,
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.set_type = mpc52xx_gpt_irq_set_type,
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};
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void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
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{
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struct mpc52xx_gpt_priv *gpt = get_irq_data(virq);
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int sub_virq;
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u32 status;
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status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
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if (status) {
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sub_virq = irq_linear_revmap(gpt->irqhost, 0);
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generic_handle_irq(sub_virq);
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}
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}
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static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct mpc52xx_gpt_priv *gpt = h->host_data;
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dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
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set_irq_chip_data(virq, gpt);
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set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
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return 0;
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}
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static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_flags)
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{
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struct mpc52xx_gpt_priv *gpt = h->host_data;
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dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
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if ((intsize < 1) || (intspec[0] < 1) || (intspec[0] > 3)) {
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dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name);
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return -EINVAL;
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}
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*out_hwirq = 0; /* The GPT only has 1 IRQ line */
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*out_flags = intspec[0];
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return 0;
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}
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static struct irq_host_ops mpc52xx_gpt_irq_ops = {
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.map = mpc52xx_gpt_irq_map,
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.xlate = mpc52xx_gpt_irq_xlate,
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};
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static void
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mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
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{
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int cascade_virq;
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unsigned long flags;
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/* Only setup cascaded IRQ if device tree claims the GPT is
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* an interrupt controller */
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if (!of_find_property(node, "interrupt-controller", NULL))
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return;
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cascade_virq = irq_of_parse_and_map(node, 0);
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gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1,
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&mpc52xx_gpt_irq_ops, -1);
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if (!gpt->irqhost) {
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dev_err(gpt->dev, "irq_alloc_host() failed\n");
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return;
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}
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gpt->irqhost->host_data = gpt;
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set_irq_data(cascade_virq, gpt);
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set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
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/* Set to Input Capture mode */
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spin_lock_irqsave(&gpt->lock, flags);
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clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
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MPC52xx_GPT_MODE_MS_IC);
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spin_unlock_irqrestore(&gpt->lock, flags);
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dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
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}
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/* ---------------------------------------------------------------------
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* GPIOLIB hooks
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*/
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#if defined(CONFIG_GPIOLIB)
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static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc)
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{
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return container_of(to_of_gpio_chip(gc), struct mpc52xx_gpt_priv,of_gc);
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}
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static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
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return (in_be32(&gpt->regs->status) >> 8) & 1;
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}
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static void
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mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
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{
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struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
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unsigned long flags;
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u32 r;
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dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
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r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
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spin_lock_irqsave(&gpt->lock, flags);
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clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
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spin_unlock_irqrestore(&gpt->lock, flags);
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}
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static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
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unsigned long flags;
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dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
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spin_lock_irqsave(&gpt->lock, flags);
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clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
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spin_unlock_irqrestore(&gpt->lock, flags);
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return 0;
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}
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static int
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mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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mpc52xx_gpt_gpio_set(gc, gpio, val);
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return 0;
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}
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static void
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mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
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{
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int rc;
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/* Only setup GPIO if the device tree claims the GPT is
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* a GPIO controller */
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if (!of_find_property(node, "gpio-controller", NULL))
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return;
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gpt->of_gc.gc.label = kstrdup(node->full_name, GFP_KERNEL);
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if (!gpt->of_gc.gc.label) {
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dev_err(gpt->dev, "out of memory\n");
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return;
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}
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gpt->of_gc.gpio_cells = 2;
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gpt->of_gc.gc.ngpio = 1;
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gpt->of_gc.gc.direction_input = mpc52xx_gpt_gpio_dir_in;
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gpt->of_gc.gc.direction_output = mpc52xx_gpt_gpio_dir_out;
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gpt->of_gc.gc.get = mpc52xx_gpt_gpio_get;
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gpt->of_gc.gc.set = mpc52xx_gpt_gpio_set;
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gpt->of_gc.gc.base = -1;
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gpt->of_gc.xlate = of_gpio_simple_xlate;
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node->data = &gpt->of_gc;
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of_node_get(node);
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/* Setup external pin in GPIO mode */
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clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
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MPC52xx_GPT_MODE_MS_GPIO);
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rc = gpiochip_add(&gpt->of_gc.gc);
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if (rc)
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dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc);
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dev_dbg(gpt->dev, "%s() complete.\n", __func__);
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}
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#else /* defined(CONFIG_GPIOLIB) */
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static void
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mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
|
||
|
|
#endif /* defined(CONFIG_GPIOLIB) */
|
||
|
|
|
||
|
|
/* ---------------------------------------------------------------------
|
||
|
|
* of_platform bus binding code
|
||
|
|
*/
|
||
|
|
static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
|
||
|
|
const struct of_device_id *match)
|
||
|
|
{
|
||
|
|
struct mpc52xx_gpt_priv *gpt;
|
||
|
|
|
||
|
|
gpt = kzalloc(sizeof *gpt, GFP_KERNEL);
|
||
|
|
if (!gpt)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
spin_lock_init(&gpt->lock);
|
||
|
|
gpt->dev = &ofdev->dev;
|
||
|
|
gpt->regs = of_iomap(ofdev->node, 0);
|
||
|
|
if (!gpt->regs) {
|
||
|
|
kfree(gpt);
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
dev_set_drvdata(&ofdev->dev, gpt);
|
||
|
|
|
||
|
|
mpc52xx_gpt_gpio_setup(gpt, ofdev->node);
|
||
|
|
mpc52xx_gpt_irq_setup(gpt, ofdev->node);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mpc52xx_gpt_remove(struct of_device *ofdev)
|
||
|
|
{
|
||
|
|
return -EBUSY;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id mpc52xx_gpt_match[] = {
|
||
|
|
{ .compatible = "fsl,mpc5200-gpt", },
|
||
|
|
|
||
|
|
/* Depreciated compatible values; don't use for new dts files */
|
||
|
|
{ .compatible = "fsl,mpc5200-gpt-gpio", },
|
||
|
|
{ .compatible = "mpc5200-gpt", },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct of_platform_driver mpc52xx_gpt_driver = {
|
||
|
|
.name = "mpc52xx-gpt",
|
||
|
|
.match_table = mpc52xx_gpt_match,
|
||
|
|
.probe = mpc52xx_gpt_probe,
|
||
|
|
.remove = mpc52xx_gpt_remove,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init mpc52xx_gpt_init(void)
|
||
|
|
{
|
||
|
|
if (of_register_platform_driver(&mpc52xx_gpt_driver))
|
||
|
|
pr_err("error registering MPC52xx GPT driver\n");
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Make sure GPIOs and IRQs get set up before anyone tries to use them */
|
||
|
|
subsys_initcall(mpc52xx_gpt_init);
|