321 lines
8.9 KiB
C
321 lines
8.9 KiB
C
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/*
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* pci-vr41xx.c, PCI Control Unit routines for the NEC VR4100 series.
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*
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* Copyright (C) 2001-2003 MontaVista Software Inc.
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* Author: Yoichi Yuasa <source@mvista.com>
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* Copyright (C) 2004-2008 Yoichi Yuasa <yuasa@linux-mips.org>
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* Changes:
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* MontaVista Software Inc. <source@mvista.com>
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* - New creation, NEC VR4122 and VR4131 are supported.
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/vr41xx/pci.h>
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#include <asm/vr41xx/vr41xx.h>
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#include "pci-vr41xx.h"
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extern struct pci_ops vr41xx_pci_ops;
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static void __iomem *pciu_base;
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#define pciu_read(offset) readl(pciu_base + (offset))
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#define pciu_write(offset, value) writel((value), pciu_base + (offset))
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static struct pci_master_address_conversion pci_master_memory1 = {
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.bus_base_address = PCI_MASTER_MEM1_BUS_BASE_ADDRESS,
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.address_mask = PCI_MASTER_MEM1_ADDRESS_MASK,
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.pci_base_address = PCI_MASTER_MEM1_PCI_BASE_ADDRESS,
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};
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static struct pci_target_address_conversion pci_target_memory1 = {
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.address_mask = PCI_TARGET_MEM1_ADDRESS_MASK,
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.bus_base_address = PCI_TARGET_MEM1_BUS_BASE_ADDRESS,
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};
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static struct pci_master_address_conversion pci_master_io = {
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.bus_base_address = PCI_MASTER_IO_BUS_BASE_ADDRESS,
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.address_mask = PCI_MASTER_IO_ADDRESS_MASK,
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.pci_base_address = PCI_MASTER_IO_PCI_BASE_ADDRESS,
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};
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static struct pci_mailbox_address pci_mailbox = {
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.base_address = PCI_MAILBOX_BASE_ADDRESS,
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};
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static struct pci_target_address_window pci_target_window1 = {
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.base_address = PCI_TARGET_WINDOW1_BASE_ADDRESS,
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};
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static struct resource pci_mem_resource = {
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.name = "PCI Memory resources",
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.start = PCI_MEM_RESOURCE_START,
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.end = PCI_MEM_RESOURCE_END,
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.flags = IORESOURCE_MEM,
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};
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static struct resource pci_io_resource = {
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.name = "PCI I/O resources",
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.start = PCI_IO_RESOURCE_START,
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.end = PCI_IO_RESOURCE_END,
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.flags = IORESOURCE_IO,
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};
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static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
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.master_memory1 = &pci_master_memory1,
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.target_memory1 = &pci_target_memory1,
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.master_io = &pci_master_io,
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.exclusive_access = CANNOT_LOCK_FROM_DEVICE,
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.wait_time_limit_from_irdy_to_trdy = 0,
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.mailbox = &pci_mailbox,
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.target_window1 = &pci_target_window1,
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.master_latency_timer = 0x80,
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.retry_limit = 0,
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.arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR,
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.take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE,
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};
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static struct pci_controller vr41xx_pci_controller = {
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.pci_ops = &vr41xx_pci_ops,
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.mem_resource = &pci_mem_resource,
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.io_resource = &pci_io_resource,
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};
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void __init vr41xx_pciu_setup(struct pci_controller_unit_setup *setup)
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{
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vr41xx_pci_controller_unit_setup = *setup;
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}
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static int __init vr41xx_pciu_init(void)
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{
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struct pci_controller_unit_setup *setup;
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struct pci_master_address_conversion *master;
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struct pci_target_address_conversion *target;
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struct pci_mailbox_address *mailbox;
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struct pci_target_address_window *window;
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unsigned long vtclock, pci_clock_max;
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uint32_t val;
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setup = &vr41xx_pci_controller_unit_setup;
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if (request_mem_region(PCIU_BASE, PCIU_SIZE, "PCIU") == NULL)
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return -EBUSY;
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pciu_base = ioremap(PCIU_BASE, PCIU_SIZE);
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if (pciu_base == NULL) {
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release_mem_region(PCIU_BASE, PCIU_SIZE);
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return -EBUSY;
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}
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/* Disable PCI interrupt */
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vr41xx_disable_pciint();
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/* Supply VTClock to PCIU */
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vr41xx_supply_clock(PCIU_CLOCK);
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/* Dummy write, waiting for supply of VTClock. */
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vr41xx_disable_pciint();
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/* Select PCI clock */
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if (setup->pci_clock_max != 0)
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pci_clock_max = setup->pci_clock_max;
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else
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pci_clock_max = PCI_CLOCK_MAX;
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vtclock = vr41xx_get_vtclock_frequency();
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if (vtclock < pci_clock_max)
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pciu_write(PCICLKSELREG, EQUAL_VTCLOCK);
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else if ((vtclock / 2) < pci_clock_max)
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pciu_write(PCICLKSELREG, HALF_VTCLOCK);
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else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&
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(vtclock / 3) < pci_clock_max)
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pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);
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else if ((vtclock / 4) < pci_clock_max)
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pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
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else {
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printk(KERN_ERR "PCI Clock is over 33MHz.\n");
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iounmap(pciu_base);
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return -EINVAL;
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}
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/* Supply PCI clock by PCI bus */
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vr41xx_supply_clock(PCI_CLOCK);
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if (setup->master_memory1 != NULL) {
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master = setup->master_memory1;
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val = IBA(master->bus_base_address) |
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MASTER_MSK(master->address_mask) |
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WINEN |
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PCIA(master->pci_base_address);
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pciu_write(PCIMMAW1REG, val);
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} else {
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val = pciu_read(PCIMMAW1REG);
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val &= ~WINEN;
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pciu_write(PCIMMAW1REG, val);
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}
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if (setup->master_memory2 != NULL) {
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master = setup->master_memory2;
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val = IBA(master->bus_base_address) |
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MASTER_MSK(master->address_mask) |
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WINEN |
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PCIA(master->pci_base_address);
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pciu_write(PCIMMAW2REG, val);
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} else {
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val = pciu_read(PCIMMAW2REG);
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val &= ~WINEN;
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pciu_write(PCIMMAW2REG, val);
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}
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if (setup->target_memory1 != NULL) {
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target = setup->target_memory1;
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val = TARGET_MSK(target->address_mask) |
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WINEN |
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ITA(target->bus_base_address);
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pciu_write(PCITAW1REG, val);
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} else {
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val = pciu_read(PCITAW1REG);
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val &= ~WINEN;
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pciu_write(PCITAW1REG, val);
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}
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if (setup->target_memory2 != NULL) {
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target = setup->target_memory2;
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val = TARGET_MSK(target->address_mask) |
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WINEN |
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ITA(target->bus_base_address);
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pciu_write(PCITAW2REG, val);
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} else {
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val = pciu_read(PCITAW2REG);
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val &= ~WINEN;
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pciu_write(PCITAW2REG, val);
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}
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if (setup->master_io != NULL) {
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master = setup->master_io;
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val = IBA(master->bus_base_address) |
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MASTER_MSK(master->address_mask) |
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WINEN |
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PCIIA(master->pci_base_address);
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pciu_write(PCIMIOAWREG, val);
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} else {
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val = pciu_read(PCIMIOAWREG);
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val &= ~WINEN;
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pciu_write(PCIMIOAWREG, val);
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}
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if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE)
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pciu_write(PCIEXACCREG, UNLOCK);
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else
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pciu_write(PCIEXACCREG, 0);
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if (current_cpu_type() == CPU_VR4122)
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pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy));
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pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer));
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if (setup->mailbox != NULL) {
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mailbox = setup->mailbox;
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val = MBADD(mailbox->base_address) | TYPE_32BITSPACE |
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MSI_MEMORY | PREF_APPROVAL;
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pciu_write(MAILBAREG, val);
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}
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if (setup->target_window1) {
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window = setup->target_window1;
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val = PMBA(window->base_address) | TYPE_32BITSPACE |
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MSI_MEMORY | PREF_APPROVAL;
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pciu_write(PCIMBA1REG, val);
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}
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if (setup->target_window2) {
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window = setup->target_window2;
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val = PMBA(window->base_address) | TYPE_32BITSPACE |
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MSI_MEMORY | PREF_APPROVAL;
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pciu_write(PCIMBA2REG, val);
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}
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val = pciu_read(RETVALREG);
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val &= ~RTYVAL_MASK;
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val |= RTYVAL(setup->retry_limit);
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pciu_write(RETVALREG, val);
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val = pciu_read(PCIAPCNTREG);
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val &= ~(TKYGNT | PAPC);
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switch (setup->arbiter_priority_control) {
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case PCI_ARBITRATION_MODE_ALTERNATE_0:
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val |= PAPC_ALTERNATE_0;
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break;
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case PCI_ARBITRATION_MODE_ALTERNATE_B:
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val |= PAPC_ALTERNATE_B;
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break;
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default:
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val |= PAPC_FAIR;
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break;
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}
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if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE)
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val |= TKYGNT_ENABLE;
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pciu_write(PCIAPCNTREG, val);
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pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
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PCI_COMMAND_SERR);
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/* Clear bus error */
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pciu_read(BUSERRADREG);
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pciu_write(PCIENREG, PCIU_CONFIG_DONE);
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if (setup->mem_resource != NULL)
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vr41xx_pci_controller.mem_resource = setup->mem_resource;
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if (setup->io_resource != NULL) {
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vr41xx_pci_controller.io_resource = setup->io_resource;
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} else {
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set_io_port_base(IO_PORT_BASE);
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ioport_resource.start = IO_PORT_RESOURCE_START;
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ioport_resource.end = IO_PORT_RESOURCE_END;
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}
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if (setup->master_io) {
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void __iomem *io_map_base;
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struct resource *res = vr41xx_pci_controller.io_resource;
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master = setup->master_io;
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io_map_base = ioremap(master->bus_base_address,
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res->end - res->start + 1);
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if (!io_map_base)
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return -EBUSY;
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vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base;
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}
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register_pci_controller(&vr41xx_pci_controller);
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return 0;
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}
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arch_initcall(vr41xx_pciu_init);
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